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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_hal_rcc_ex.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of RCC HAL Extension module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_HAL_RCC_EX_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	47	#include "stm32f4xx_hal_def.h"
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	50	* @{
NYX	0:85b3fd62ea1a	51	*/
NYX	0:85b3fd62ea1a	52
NYX	0:85b3fd62ea1a	53	/** @addtogroup RCCEx
NYX	0:85b3fd62ea1a	54	* @{
NYX	0:85b3fd62ea1a	55	*/
NYX	0:85b3fd62ea1a	56
NYX	0:85b3fd62ea1a	57	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
NYX	0:85b3fd62ea1a	59	* @{
NYX	0:85b3fd62ea1a	60	*/
NYX	0:85b3fd62ea1a	61
NYX	0:85b3fd62ea1a	62	/**
NYX	0:85b3fd62ea1a	63	* @brief RCC PLL configuration structure definition
NYX	0:85b3fd62ea1a	64	*/
NYX	0:85b3fd62ea1a	65	typedef struct
NYX	0:85b3fd62ea1a	66	{
NYX	0:85b3fd62ea1a	67	uint32_t PLLState; /*!< The new state of the PLL.
NYX	0:85b3fd62ea1a	68	This parameter can be a value of @ref RCC_PLL_Config */
NYX	0:85b3fd62ea1a	69
NYX	0:85b3fd62ea1a	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
NYX	0:85b3fd62ea1a	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
NYX	0:85b3fd62ea1a	72
NYX	0:85b3fd62ea1a	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
NYX	0:85b3fd62ea1a	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
NYX	0:85b3fd62ea1a	75
NYX	0:85b3fd62ea1a	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
NYX	0:85b3fd62ea1a	77	This parameter must be a number between Min_Data = 50 and Max_Data = 432
NYX	0:85b3fd62ea1a	78	except for STM32F411xE devices where the Min_Data = 192 */
NYX	0:85b3fd62ea1a	79
NYX	0:85b3fd62ea1a	80	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
NYX	0:85b3fd62ea1a	81	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
NYX	0:85b3fd62ea1a	82
NYX	0:85b3fd62ea1a	83	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
NYX	0:85b3fd62ea1a	84	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
NYX	0:85b3fd62ea1a	85	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	86	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
NYX	0:85b3fd62ea1a	87	defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	88	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
NYX	0:85b3fd62ea1a	89	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
NYX	0:85b3fd62ea1a	90	and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
NYX	0:85b3fd62ea1a	91	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
NYX	0:85b3fd62ea1a	92	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	93	}RCC_PLLInitTypeDef;
NYX	0:85b3fd62ea1a	94
NYX	0:85b3fd62ea1a	95	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	96	/**
NYX	0:85b3fd62ea1a	97	* @brief PLLI2S Clock structure definition
NYX	0:85b3fd62ea1a	98	*/
NYX	0:85b3fd62ea1a	99	typedef struct
NYX	0:85b3fd62ea1a	100	{
NYX	0:85b3fd62ea1a	101	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
NYX	0:85b3fd62ea1a	102	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
NYX	0:85b3fd62ea1a	103
NYX	0:85b3fd62ea1a	104	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
NYX	0:85b3fd62ea1a	105	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
NYX	0:85b3fd62ea1a	106
NYX	0:85b3fd62ea1a	107	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
NYX	0:85b3fd62ea1a	108	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
NYX	0:85b3fd62ea1a	109
NYX	0:85b3fd62ea1a	110	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
NYX	0:85b3fd62ea1a	111	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	112	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	113
NYX	0:85b3fd62ea1a	114	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
NYX	0:85b3fd62ea1a	115	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	116	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
NYX	0:85b3fd62ea1a	117	}RCC_PLLI2SInitTypeDef;
NYX	0:85b3fd62ea1a	118
NYX	0:85b3fd62ea1a	119	/**
NYX	0:85b3fd62ea1a	120	* @brief PLLSAI Clock structure definition
NYX	0:85b3fd62ea1a	121	*/
NYX	0:85b3fd62ea1a	122	typedef struct
NYX	0:85b3fd62ea1a	123	{
NYX	0:85b3fd62ea1a	124	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
NYX	0:85b3fd62ea1a	125	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
NYX	0:85b3fd62ea1a	126
NYX	0:85b3fd62ea1a	127	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
NYX	0:85b3fd62ea1a	128	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
NYX	0:85b3fd62ea1a	129
NYX	0:85b3fd62ea1a	130	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
NYX	0:85b3fd62ea1a	131	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
NYX	0:85b3fd62ea1a	132
NYX	0:85b3fd62ea1a	133	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
NYX	0:85b3fd62ea1a	134	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	135	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	136	}RCC_PLLSAIInitTypeDef;
NYX	0:85b3fd62ea1a	137
NYX	0:85b3fd62ea1a	138	/**
NYX	0:85b3fd62ea1a	139	* @brief RCC extended clocks structure definition
NYX	0:85b3fd62ea1a	140	*/
NYX	0:85b3fd62ea1a	141	typedef struct
NYX	0:85b3fd62ea1a	142	{
NYX	0:85b3fd62ea1a	143	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
NYX	0:85b3fd62ea1a	144	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
NYX	0:85b3fd62ea1a	145
NYX	0:85b3fd62ea1a	146	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
NYX	0:85b3fd62ea1a	147	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
NYX	0:85b3fd62ea1a	148
NYX	0:85b3fd62ea1a	149	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
NYX	0:85b3fd62ea1a	150	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
NYX	0:85b3fd62ea1a	151
NYX	0:85b3fd62ea1a	152	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	153	This parameter must be a number between Min_Data = 1 and Max_Data = 32
NYX	0:85b3fd62ea1a	154	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	155
NYX	0:85b3fd62ea1a	156	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	157	This parameter must be a number between Min_Data = 1 and Max_Data = 32
NYX	0:85b3fd62ea1a	158	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	159
NYX	0:85b3fd62ea1a	160	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
NYX	0:85b3fd62ea1a	161	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
NYX	0:85b3fd62ea1a	162
NYX	0:85b3fd62ea1a	163	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
NYX	0:85b3fd62ea1a	164	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
NYX	0:85b3fd62ea1a	165
NYX	0:85b3fd62ea1a	166	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
NYX	0:85b3fd62ea1a	167	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
NYX	0:85b3fd62ea1a	168
NYX	0:85b3fd62ea1a	169	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
NYX	0:85b3fd62ea1a	170	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
NYX	0:85b3fd62ea1a	171
NYX	0:85b3fd62ea1a	172	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
NYX	0:85b3fd62ea1a	173	This parameter can be a value of @ref RCC_RTC_Clock_Source */
NYX	0:85b3fd62ea1a	174
NYX	0:85b3fd62ea1a	175	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
NYX	0:85b3fd62ea1a	176	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
NYX	0:85b3fd62ea1a	177
NYX	0:85b3fd62ea1a	178	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
NYX	0:85b3fd62ea1a	179	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
NYX	0:85b3fd62ea1a	180
NYX	0:85b3fd62ea1a	181	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
NYX	0:85b3fd62ea1a	182	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
NYX	0:85b3fd62ea1a	183
NYX	0:85b3fd62ea1a	184	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
NYX	0:85b3fd62ea1a	185	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
NYX	0:85b3fd62ea1a	186
NYX	0:85b3fd62ea1a	187	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
NYX	0:85b3fd62ea1a	188	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
NYX	0:85b3fd62ea1a	189
NYX	0:85b3fd62ea1a	190	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
NYX	0:85b3fd62ea1a	191	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
NYX	0:85b3fd62ea1a	192	}RCC_PeriphCLKInitTypeDef;
NYX	0:85b3fd62ea1a	193	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	194
NYX	0:85b3fd62ea1a	195	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	196	/**
NYX	0:85b3fd62ea1a	197	* @brief RCC extended clocks structure definition
NYX	0:85b3fd62ea1a	198	*/
NYX	0:85b3fd62ea1a	199	typedef struct
NYX	0:85b3fd62ea1a	200	{
NYX	0:85b3fd62ea1a	201	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
NYX	0:85b3fd62ea1a	202	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
NYX	0:85b3fd62ea1a	203
NYX	0:85b3fd62ea1a	204	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
NYX	0:85b3fd62ea1a	205	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
NYX	0:85b3fd62ea1a	206
NYX	0:85b3fd62ea1a	207	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
NYX	0:85b3fd62ea1a	208	This parameter can be a value of @ref RCC_RTC_Clock_Source */
NYX	0:85b3fd62ea1a	209
NYX	0:85b3fd62ea1a	210	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
NYX	0:85b3fd62ea1a	211	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
NYX	0:85b3fd62ea1a	212
NYX	0:85b3fd62ea1a	213	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
NYX	0:85b3fd62ea1a	214	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
NYX	0:85b3fd62ea1a	215
NYX	0:85b3fd62ea1a	216	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
NYX	0:85b3fd62ea1a	217	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
NYX	0:85b3fd62ea1a	218	}RCC_PeriphCLKInitTypeDef;
NYX	0:85b3fd62ea1a	219	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	220
NYX	0:85b3fd62ea1a	221	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	222	/**
NYX	0:85b3fd62ea1a	223	* @brief PLLI2S Clock structure definition
NYX	0:85b3fd62ea1a	224	*/
NYX	0:85b3fd62ea1a	225	typedef struct
NYX	0:85b3fd62ea1a	226	{
NYX	0:85b3fd62ea1a	227	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
NYX	0:85b3fd62ea1a	228	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
NYX	0:85b3fd62ea1a	229
NYX	0:85b3fd62ea1a	230	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
NYX	0:85b3fd62ea1a	231	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
NYX	0:85b3fd62ea1a	232
NYX	0:85b3fd62ea1a	233	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
NYX	0:85b3fd62ea1a	234	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	235	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	236
NYX	0:85b3fd62ea1a	237	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
NYX	0:85b3fd62ea1a	238	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	239	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
NYX	0:85b3fd62ea1a	240	}RCC_PLLI2SInitTypeDef;
NYX	0:85b3fd62ea1a	241
NYX	0:85b3fd62ea1a	242	/**
NYX	0:85b3fd62ea1a	243	* @brief RCC extended clocks structure definition
NYX	0:85b3fd62ea1a	244	*/
NYX	0:85b3fd62ea1a	245	typedef struct
NYX	0:85b3fd62ea1a	246	{
NYX	0:85b3fd62ea1a	247	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
NYX	0:85b3fd62ea1a	248	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
NYX	0:85b3fd62ea1a	249
NYX	0:85b3fd62ea1a	250	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
NYX	0:85b3fd62ea1a	251	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
NYX	0:85b3fd62ea1a	252
NYX	0:85b3fd62ea1a	253	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	254	uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	255	This parameter must be a number between Min_Data = 1 and Max_Data = 32
NYX	0:85b3fd62ea1a	256	This parameter will be used only when PLL is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	257
NYX	0:85b3fd62ea1a	258	uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	259	This parameter must be a number between Min_Data = 1 and Max_Data = 32
NYX	0:85b3fd62ea1a	260	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	261	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	262
NYX	0:85b3fd62ea1a	263	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
NYX	0:85b3fd62ea1a	264	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
NYX	0:85b3fd62ea1a	265
NYX	0:85b3fd62ea1a	266	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
NYX	0:85b3fd62ea1a	267	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
NYX	0:85b3fd62ea1a	268
NYX	0:85b3fd62ea1a	269	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
NYX	0:85b3fd62ea1a	270	This parameter can be a value of @ref RCC_RTC_Clock_Source */
NYX	0:85b3fd62ea1a	271
NYX	0:85b3fd62ea1a	272	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
NYX	0:85b3fd62ea1a	273	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
NYX	0:85b3fd62ea1a	274
NYX	0:85b3fd62ea1a	275	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
NYX	0:85b3fd62ea1a	276	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
NYX	0:85b3fd62ea1a	277
NYX	0:85b3fd62ea1a	278	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
NYX	0:85b3fd62ea1a	279	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
NYX	0:85b3fd62ea1a	280
NYX	0:85b3fd62ea1a	281	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
NYX	0:85b3fd62ea1a	282	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
NYX	0:85b3fd62ea1a	283
NYX	0:85b3fd62ea1a	284	uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
NYX	0:85b3fd62ea1a	285	This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
NYX	0:85b3fd62ea1a	286
NYX	0:85b3fd62ea1a	287	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	288	uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection.
NYX	0:85b3fd62ea1a	289	This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
NYX	0:85b3fd62ea1a	290
NYX	0:85b3fd62ea1a	291	uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
NYX	0:85b3fd62ea1a	292	This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
NYX	0:85b3fd62ea1a	293
NYX	0:85b3fd62ea1a	294	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
NYX	0:85b3fd62ea1a	295	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
NYX	0:85b3fd62ea1a	296
NYX	0:85b3fd62ea1a	297	uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection
NYX	0:85b3fd62ea1a	298	This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
NYX	0:85b3fd62ea1a	299
NYX	0:85b3fd62ea1a	300	uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection
NYX	0:85b3fd62ea1a	301	This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
NYX	0:85b3fd62ea1a	302	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	303
NYX	0:85b3fd62ea1a	304	uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
NYX	0:85b3fd62ea1a	305	This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
NYX	0:85b3fd62ea1a	306
NYX	0:85b3fd62ea1a	307	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
NYX	0:85b3fd62ea1a	308	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
NYX	0:85b3fd62ea1a	309	}RCC_PeriphCLKInitTypeDef;
NYX	0:85b3fd62ea1a	310	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	311
NYX	0:85b3fd62ea1a	312	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	313	/**
NYX	0:85b3fd62ea1a	314	* @brief PLLI2S Clock structure definition
NYX	0:85b3fd62ea1a	315	*/
NYX	0:85b3fd62ea1a	316	typedef struct
NYX	0:85b3fd62ea1a	317	{
NYX	0:85b3fd62ea1a	318	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
NYX	0:85b3fd62ea1a	319	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	320	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
NYX	0:85b3fd62ea1a	321
NYX	0:85b3fd62ea1a	322	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
NYX	0:85b3fd62ea1a	323	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	324	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
NYX	0:85b3fd62ea1a	325
NYX	0:85b3fd62ea1a	326	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	327	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	328	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	329	}RCC_PLLI2SInitTypeDef;
NYX	0:85b3fd62ea1a	330
NYX	0:85b3fd62ea1a	331	/**
NYX	0:85b3fd62ea1a	332	* @brief PLLSAI Clock structure definition
NYX	0:85b3fd62ea1a	333	*/
NYX	0:85b3fd62ea1a	334	typedef struct
NYX	0:85b3fd62ea1a	335	{
NYX	0:85b3fd62ea1a	336	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
NYX	0:85b3fd62ea1a	337	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	338	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
NYX	0:85b3fd62ea1a	339	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	340	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
NYX	0:85b3fd62ea1a	341	This parameter is only available in STM32F469xx/STM32F479xx devices.
NYX	0:85b3fd62ea1a	342	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
NYX	0:85b3fd62ea1a	343	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	344
NYX	0:85b3fd62ea1a	345	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	346	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	347	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
NYX	0:85b3fd62ea1a	348
NYX	0:85b3fd62ea1a	349	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
NYX	0:85b3fd62ea1a	350	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	351	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
NYX	0:85b3fd62ea1a	352
NYX	0:85b3fd62ea1a	353	}RCC_PLLSAIInitTypeDef;
NYX	0:85b3fd62ea1a	354
NYX	0:85b3fd62ea1a	355	/**
NYX	0:85b3fd62ea1a	356	* @brief RCC extended clocks structure definition
NYX	0:85b3fd62ea1a	357	*/
NYX	0:85b3fd62ea1a	358	typedef struct
NYX	0:85b3fd62ea1a	359	{
NYX	0:85b3fd62ea1a	360	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
NYX	0:85b3fd62ea1a	361	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
NYX	0:85b3fd62ea1a	362
NYX	0:85b3fd62ea1a	363	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
NYX	0:85b3fd62ea1a	364	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
NYX	0:85b3fd62ea1a	365
NYX	0:85b3fd62ea1a	366	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
NYX	0:85b3fd62ea1a	367	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
NYX	0:85b3fd62ea1a	368
NYX	0:85b3fd62ea1a	369	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	370	This parameter must be a number between Min_Data = 1 and Max_Data = 32
NYX	0:85b3fd62ea1a	371	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	372
NYX	0:85b3fd62ea1a	373	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	374	This parameter must be a number between Min_Data = 1 and Max_Data = 32
NYX	0:85b3fd62ea1a	375	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
NYX	0:85b3fd62ea1a	376
NYX	0:85b3fd62ea1a	377	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
NYX	0:85b3fd62ea1a	378	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
NYX	0:85b3fd62ea1a	379
NYX	0:85b3fd62ea1a	380	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
NYX	0:85b3fd62ea1a	381	This parameter can be a value of @ref RCC_RTC_Clock_Source */
NYX	0:85b3fd62ea1a	382
NYX	0:85b3fd62ea1a	383	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
NYX	0:85b3fd62ea1a	384	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
NYX	0:85b3fd62ea1a	385	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	386	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
NYX	0:85b3fd62ea1a	387	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
NYX	0:85b3fd62ea1a	388
NYX	0:85b3fd62ea1a	389	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
NYX	0:85b3fd62ea1a	390	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
NYX	0:85b3fd62ea1a	391	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	392	}RCC_PeriphCLKInitTypeDef;
NYX	0:85b3fd62ea1a	393
NYX	0:85b3fd62ea1a	394	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	395
NYX	0:85b3fd62ea1a	396	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
NYX	0:85b3fd62ea1a	397	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
NYX	0:85b3fd62ea1a	398	/**
NYX	0:85b3fd62ea1a	399	* @brief PLLI2S Clock structure definition
NYX	0:85b3fd62ea1a	400	*/
NYX	0:85b3fd62ea1a	401	typedef struct
NYX	0:85b3fd62ea1a	402	{
NYX	0:85b3fd62ea1a	403	#if defined(STM32F411xE)
NYX	0:85b3fd62ea1a	404	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
NYX	0:85b3fd62ea1a	405	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
NYX	0:85b3fd62ea1a	406	#endif /* STM32F411xE */
NYX	0:85b3fd62ea1a	407
NYX	0:85b3fd62ea1a	408	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
NYX	0:85b3fd62ea1a	409	This parameter must be a number between Min_Data = 50 and Max_Data = 432
NYX	0:85b3fd62ea1a	410	Except for STM32F411xE devices where the Min_Data = 192.
NYX	0:85b3fd62ea1a	411	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
NYX	0:85b3fd62ea1a	412
NYX	0:85b3fd62ea1a	413	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
NYX	0:85b3fd62ea1a	414	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	415	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
NYX	0:85b3fd62ea1a	416
NYX	0:85b3fd62ea1a	417	}RCC_PLLI2SInitTypeDef;
NYX	0:85b3fd62ea1a	418
NYX	0:85b3fd62ea1a	419	/**
NYX	0:85b3fd62ea1a	420	* @brief RCC extended clocks structure definition
NYX	0:85b3fd62ea1a	421	*/
NYX	0:85b3fd62ea1a	422	typedef struct
NYX	0:85b3fd62ea1a	423	{
NYX	0:85b3fd62ea1a	424	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
NYX	0:85b3fd62ea1a	425	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
NYX	0:85b3fd62ea1a	426
NYX	0:85b3fd62ea1a	427	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
NYX	0:85b3fd62ea1a	428	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
NYX	0:85b3fd62ea1a	429
NYX	0:85b3fd62ea1a	430	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
NYX	0:85b3fd62ea1a	431	This parameter can be a value of @ref RCC_RTC_Clock_Source */
NYX	0:85b3fd62ea1a	432	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
NYX	0:85b3fd62ea1a	433	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
NYX	0:85b3fd62ea1a	434	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
NYX	0:85b3fd62ea1a	435	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
NYX	0:85b3fd62ea1a	436	}RCC_PeriphCLKInitTypeDef;
NYX	0:85b3fd62ea1a	437	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
NYX	0:85b3fd62ea1a	438	/**
NYX	0:85b3fd62ea1a	439	* @}
NYX	0:85b3fd62ea1a	440	*/
NYX	0:85b3fd62ea1a	441
NYX	0:85b3fd62ea1a	442	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	443	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
NYX	0:85b3fd62ea1a	444	* @{
NYX	0:85b3fd62ea1a	445	*/
NYX	0:85b3fd62ea1a	446
NYX	0:85b3fd62ea1a	447	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
NYX	0:85b3fd62ea1a	448	* @{
NYX	0:85b3fd62ea1a	449	*/
NYX	0:85b3fd62ea1a	450	/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
NYX	0:85b3fd62ea1a	451	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
NYX	0:85b3fd62ea1a	452	defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	453	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
NYX	0:85b3fd62ea1a	454	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
NYX	0:85b3fd62ea1a	455	#define RCC_PERIPHCLK_TIM 0x00000004U
NYX	0:85b3fd62ea1a	456	#define RCC_PERIPHCLK_RTC 0x00000008U
NYX	0:85b3fd62ea1a	457	#define RCC_PERIPHCLK_FMPI2C1 0x00000010U
NYX	0:85b3fd62ea1a	458	#define RCC_PERIPHCLK_CLK48 0x00000020U
NYX	0:85b3fd62ea1a	459	#define RCC_PERIPHCLK_SDIO 0x00000040U
NYX	0:85b3fd62ea1a	460	#define RCC_PERIPHCLK_PLLI2S 0x00000080U
NYX	0:85b3fd62ea1a	461	#define RCC_PERIPHCLK_DFSDM1 0x00000100U
NYX	0:85b3fd62ea1a	462	#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
NYX	0:85b3fd62ea1a	463	#endif /* STM32F412Zx \|\| STM32F412Vx) \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	464	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	465	#define RCC_PERIPHCLK_DFSDM2 0x00000400U
NYX	0:85b3fd62ea1a	466	#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
NYX	0:85b3fd62ea1a	467	#define RCC_PERIPHCLK_LPTIM1 0x00001000U
NYX	0:85b3fd62ea1a	468	#define RCC_PERIPHCLK_SAIA 0x00002000U
NYX	0:85b3fd62ea1a	469	#define RCC_PERIPHCLK_SAIB 0x00004000U
NYX	0:85b3fd62ea1a	470	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	471	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	472
NYX	0:85b3fd62ea1a	473	/------------------- Peripheral Clock source for STM32F410xx ----------------/
NYX	0:85b3fd62ea1a	474	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	475	#define RCC_PERIPHCLK_I2S 0x00000001U
NYX	0:85b3fd62ea1a	476	#define RCC_PERIPHCLK_TIM 0x00000002U
NYX	0:85b3fd62ea1a	477	#define RCC_PERIPHCLK_RTC 0x00000004U
NYX	0:85b3fd62ea1a	478	#define RCC_PERIPHCLK_FMPI2C1 0x00000008U
NYX	0:85b3fd62ea1a	479	#define RCC_PERIPHCLK_LPTIM1 0x00000010U
NYX	0:85b3fd62ea1a	480	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	481	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	482
NYX	0:85b3fd62ea1a	483	/------------------- Peripheral Clock source for STM32F446xx ----------------/
NYX	0:85b3fd62ea1a	484	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	485	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
NYX	0:85b3fd62ea1a	486	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
NYX	0:85b3fd62ea1a	487	#define RCC_PERIPHCLK_SAI1 0x00000004U
NYX	0:85b3fd62ea1a	488	#define RCC_PERIPHCLK_SAI2 0x00000008U
NYX	0:85b3fd62ea1a	489	#define RCC_PERIPHCLK_TIM 0x00000010U
NYX	0:85b3fd62ea1a	490	#define RCC_PERIPHCLK_RTC 0x00000020U
NYX	0:85b3fd62ea1a	491	#define RCC_PERIPHCLK_CEC 0x00000040U
NYX	0:85b3fd62ea1a	492	#define RCC_PERIPHCLK_FMPI2C1 0x00000080U
NYX	0:85b3fd62ea1a	493	#define RCC_PERIPHCLK_CLK48 0x00000100U
NYX	0:85b3fd62ea1a	494	#define RCC_PERIPHCLK_SDIO 0x00000200U
NYX	0:85b3fd62ea1a	495	#define RCC_PERIPHCLK_SPDIFRX 0x00000400U
NYX	0:85b3fd62ea1a	496	#define RCC_PERIPHCLK_PLLI2S 0x00000800U
NYX	0:85b3fd62ea1a	497	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	498	/-----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	499
NYX	0:85b3fd62ea1a	500	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
NYX	0:85b3fd62ea1a	501	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	502	#define RCC_PERIPHCLK_I2S 0x00000001U
NYX	0:85b3fd62ea1a	503	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
NYX	0:85b3fd62ea1a	504	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
NYX	0:85b3fd62ea1a	505	#define RCC_PERIPHCLK_LTDC 0x00000008U
NYX	0:85b3fd62ea1a	506	#define RCC_PERIPHCLK_TIM 0x00000010U
NYX	0:85b3fd62ea1a	507	#define RCC_PERIPHCLK_RTC 0x00000020U
NYX	0:85b3fd62ea1a	508	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
NYX	0:85b3fd62ea1a	509	#define RCC_PERIPHCLK_CLK48 0x00000080U
NYX	0:85b3fd62ea1a	510	#define RCC_PERIPHCLK_SDIO 0x00000100U
NYX	0:85b3fd62ea1a	511	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	512	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	513
NYX	0:85b3fd62ea1a	514	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
NYX	0:85b3fd62ea1a	515	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
NYX	0:85b3fd62ea1a	516	#define RCC_PERIPHCLK_I2S 0x00000001U
NYX	0:85b3fd62ea1a	517	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
NYX	0:85b3fd62ea1a	518	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
NYX	0:85b3fd62ea1a	519	#define RCC_PERIPHCLK_LTDC 0x00000008U
NYX	0:85b3fd62ea1a	520	#define RCC_PERIPHCLK_TIM 0x00000010U
NYX	0:85b3fd62ea1a	521	#define RCC_PERIPHCLK_RTC 0x00000020U
NYX	0:85b3fd62ea1a	522	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
NYX	0:85b3fd62ea1a	523	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
NYX	0:85b3fd62ea1a	524	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	525
NYX	0:85b3fd62ea1a	526	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
NYX	0:85b3fd62ea1a	527	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
NYX	0:85b3fd62ea1a	528	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
NYX	0:85b3fd62ea1a	529	#define RCC_PERIPHCLK_I2S 0x00000001U
NYX	0:85b3fd62ea1a	530	#define RCC_PERIPHCLK_RTC 0x00000002U
NYX	0:85b3fd62ea1a	531	#define RCC_PERIPHCLK_PLLI2S 0x00000004U
NYX	0:85b3fd62ea1a	532	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
NYX	0:85b3fd62ea1a	533	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
NYX	0:85b3fd62ea1a	534	#define RCC_PERIPHCLK_TIM 0x00000008U
NYX	0:85b3fd62ea1a	535	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
NYX	0:85b3fd62ea1a	536	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	537	/**
NYX	0:85b3fd62ea1a	538	* @}
NYX	0:85b3fd62ea1a	539	*/
NYX	0:85b3fd62ea1a	540	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
NYX	0:85b3fd62ea1a	541	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
NYX	0:85b3fd62ea1a	542	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\| \
NYX	0:85b3fd62ea1a	543	defined(STM32F479xx)
NYX	0:85b3fd62ea1a	544	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
NYX	0:85b3fd62ea1a	545	* @{
NYX	0:85b3fd62ea1a	546	*/
NYX	0:85b3fd62ea1a	547	#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
NYX	0:85b3fd62ea1a	548	#define RCC_I2SCLKSOURCE_EXT 0x00000001U
NYX	0:85b3fd62ea1a	549	/**
NYX	0:85b3fd62ea1a	550	* @}
NYX	0:85b3fd62ea1a	551	*/
NYX	0:85b3fd62ea1a	552	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
NYX	0:85b3fd62ea1a	553	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	554
NYX	0:85b3fd62ea1a	555	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
NYX	0:85b3fd62ea1a	556	* @{
NYX	0:85b3fd62ea1a	557	*/
NYX	0:85b3fd62ea1a	558	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
NYX	0:85b3fd62ea1a	559	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	560	#define RCC_PLLSAIDIVR_2 0x00000000U
NYX	0:85b3fd62ea1a	561	#define RCC_PLLSAIDIVR_4 0x00010000U
NYX	0:85b3fd62ea1a	562	#define RCC_PLLSAIDIVR_8 0x00020000U
NYX	0:85b3fd62ea1a	563	#define RCC_PLLSAIDIVR_16 0x00030000U
NYX	0:85b3fd62ea1a	564	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	565	/**
NYX	0:85b3fd62ea1a	566	* @}
NYX	0:85b3fd62ea1a	567	*/
NYX	0:85b3fd62ea1a	568
NYX	0:85b3fd62ea1a	569	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
NYX	0:85b3fd62ea1a	570	* @{
NYX	0:85b3fd62ea1a	571	*/
NYX	0:85b3fd62ea1a	572	#if defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
NYX	0:85b3fd62ea1a	573	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	574	#define RCC_PLLI2SP_DIV2 0x00000002U
NYX	0:85b3fd62ea1a	575	#define RCC_PLLI2SP_DIV4 0x00000004U
NYX	0:85b3fd62ea1a	576	#define RCC_PLLI2SP_DIV6 0x00000006U
NYX	0:85b3fd62ea1a	577	#define RCC_PLLI2SP_DIV8 0x00000008U
NYX	0:85b3fd62ea1a	578	#endif /* STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	579	/**
NYX	0:85b3fd62ea1a	580	* @}
NYX	0:85b3fd62ea1a	581	*/
NYX	0:85b3fd62ea1a	582
NYX	0:85b3fd62ea1a	583	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
NYX	0:85b3fd62ea1a	584	* @{
NYX	0:85b3fd62ea1a	585	*/
NYX	0:85b3fd62ea1a	586	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	587	#define RCC_PLLSAIP_DIV2 0x00000002U
NYX	0:85b3fd62ea1a	588	#define RCC_PLLSAIP_DIV4 0x00000004U
NYX	0:85b3fd62ea1a	589	#define RCC_PLLSAIP_DIV6 0x00000006U
NYX	0:85b3fd62ea1a	590	#define RCC_PLLSAIP_DIV8 0x00000008U
NYX	0:85b3fd62ea1a	591	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	592	/**
NYX	0:85b3fd62ea1a	593	* @}
NYX	0:85b3fd62ea1a	594	*/
NYX	0:85b3fd62ea1a	595
NYX	0:85b3fd62ea1a	596	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	597	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
NYX	0:85b3fd62ea1a	598	* @{
NYX	0:85b3fd62ea1a	599	*/
NYX	0:85b3fd62ea1a	600	#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
NYX	0:85b3fd62ea1a	601	#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
NYX	0:85b3fd62ea1a	602	#define RCC_SAIACLKSOURCE_EXT 0x00200000U
NYX	0:85b3fd62ea1a	603	/**
NYX	0:85b3fd62ea1a	604	* @}
NYX	0:85b3fd62ea1a	605	*/
NYX	0:85b3fd62ea1a	606
NYX	0:85b3fd62ea1a	607	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
NYX	0:85b3fd62ea1a	608	* @{
NYX	0:85b3fd62ea1a	609	*/
NYX	0:85b3fd62ea1a	610	#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
NYX	0:85b3fd62ea1a	611	#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
NYX	0:85b3fd62ea1a	612	#define RCC_SAIBCLKSOURCE_EXT 0x00800000U
NYX	0:85b3fd62ea1a	613	/**
NYX	0:85b3fd62ea1a	614	* @}
NYX	0:85b3fd62ea1a	615	*/
NYX	0:85b3fd62ea1a	616	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	617
NYX	0:85b3fd62ea1a	618	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	619	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
NYX	0:85b3fd62ea1a	620	* @{
NYX	0:85b3fd62ea1a	621	*/
NYX	0:85b3fd62ea1a	622	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
NYX	0:85b3fd62ea1a	623	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
NYX	0:85b3fd62ea1a	624	/**
NYX	0:85b3fd62ea1a	625	* @}
NYX	0:85b3fd62ea1a	626	*/
NYX	0:85b3fd62ea1a	627
NYX	0:85b3fd62ea1a	628	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
NYX	0:85b3fd62ea1a	629	* @{
NYX	0:85b3fd62ea1a	630	*/
NYX	0:85b3fd62ea1a	631	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
NYX	0:85b3fd62ea1a	632	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
NYX	0:85b3fd62ea1a	633	/**
NYX	0:85b3fd62ea1a	634	* @}
NYX	0:85b3fd62ea1a	635	*/
NYX	0:85b3fd62ea1a	636
NYX	0:85b3fd62ea1a	637	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
NYX	0:85b3fd62ea1a	638	* @{
NYX	0:85b3fd62ea1a	639	*/
NYX	0:85b3fd62ea1a	640	#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
NYX	0:85b3fd62ea1a	641	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
NYX	0:85b3fd62ea1a	642	/**
NYX	0:85b3fd62ea1a	643	* @}
NYX	0:85b3fd62ea1a	644	*/
NYX	0:85b3fd62ea1a	645	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	646
NYX	0:85b3fd62ea1a	647	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	648	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
NYX	0:85b3fd62ea1a	649	* @{
NYX	0:85b3fd62ea1a	650	*/
NYX	0:85b3fd62ea1a	651	#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
NYX	0:85b3fd62ea1a	652	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
NYX	0:85b3fd62ea1a	653	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
NYX	0:85b3fd62ea1a	654	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
NYX	0:85b3fd62ea1a	655	/**
NYX	0:85b3fd62ea1a	656	* @}
NYX	0:85b3fd62ea1a	657	*/
NYX	0:85b3fd62ea1a	658
NYX	0:85b3fd62ea1a	659	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
NYX	0:85b3fd62ea1a	660	* @{
NYX	0:85b3fd62ea1a	661	*/
NYX	0:85b3fd62ea1a	662	#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
NYX	0:85b3fd62ea1a	663	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
NYX	0:85b3fd62ea1a	664	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
NYX	0:85b3fd62ea1a	665	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
NYX	0:85b3fd62ea1a	666	/**
NYX	0:85b3fd62ea1a	667	* @}
NYX	0:85b3fd62ea1a	668	*/
NYX	0:85b3fd62ea1a	669
NYX	0:85b3fd62ea1a	670	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
NYX	0:85b3fd62ea1a	671	* @{
NYX	0:85b3fd62ea1a	672	*/
NYX	0:85b3fd62ea1a	673	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
NYX	0:85b3fd62ea1a	674	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
NYX	0:85b3fd62ea1a	675	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
NYX	0:85b3fd62ea1a	676	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
NYX	0:85b3fd62ea1a	677	/**
NYX	0:85b3fd62ea1a	678	* @}
NYX	0:85b3fd62ea1a	679	*/
NYX	0:85b3fd62ea1a	680
NYX	0:85b3fd62ea1a	681	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
NYX	0:85b3fd62ea1a	682	* @{
NYX	0:85b3fd62ea1a	683	*/
NYX	0:85b3fd62ea1a	684	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
NYX	0:85b3fd62ea1a	685	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
NYX	0:85b3fd62ea1a	686	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
NYX	0:85b3fd62ea1a	687	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
NYX	0:85b3fd62ea1a	688	/**
NYX	0:85b3fd62ea1a	689	* @}
NYX	0:85b3fd62ea1a	690	*/
NYX	0:85b3fd62ea1a	691
NYX	0:85b3fd62ea1a	692	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
NYX	0:85b3fd62ea1a	693	* @{
NYX	0:85b3fd62ea1a	694	*/
NYX	0:85b3fd62ea1a	695	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
NYX	0:85b3fd62ea1a	696	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
NYX	0:85b3fd62ea1a	697	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
NYX	0:85b3fd62ea1a	698	/**
NYX	0:85b3fd62ea1a	699	* @}
NYX	0:85b3fd62ea1a	700	*/
NYX	0:85b3fd62ea1a	701
NYX	0:85b3fd62ea1a	702	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
NYX	0:85b3fd62ea1a	703	* @{
NYX	0:85b3fd62ea1a	704	*/
NYX	0:85b3fd62ea1a	705	#define RCC_CECCLKSOURCE_HSI 0x00000000U
NYX	0:85b3fd62ea1a	706	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
NYX	0:85b3fd62ea1a	707	/**
NYX	0:85b3fd62ea1a	708	* @}
NYX	0:85b3fd62ea1a	709	*/
NYX	0:85b3fd62ea1a	710
NYX	0:85b3fd62ea1a	711	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
NYX	0:85b3fd62ea1a	712	* @{
NYX	0:85b3fd62ea1a	713	*/
NYX	0:85b3fd62ea1a	714	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
NYX	0:85b3fd62ea1a	715	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	716	/**
NYX	0:85b3fd62ea1a	717	* @}
NYX	0:85b3fd62ea1a	718	*/
NYX	0:85b3fd62ea1a	719
NYX	0:85b3fd62ea1a	720	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
NYX	0:85b3fd62ea1a	721	* @{
NYX	0:85b3fd62ea1a	722	*/
NYX	0:85b3fd62ea1a	723	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
NYX	0:85b3fd62ea1a	724	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
NYX	0:85b3fd62ea1a	725	/**
NYX	0:85b3fd62ea1a	726	* @}
NYX	0:85b3fd62ea1a	727	*/
NYX	0:85b3fd62ea1a	728
NYX	0:85b3fd62ea1a	729	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
NYX	0:85b3fd62ea1a	730	* @{
NYX	0:85b3fd62ea1a	731	*/
NYX	0:85b3fd62ea1a	732	#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
NYX	0:85b3fd62ea1a	733	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
NYX	0:85b3fd62ea1a	734	/**
NYX	0:85b3fd62ea1a	735	* @}
NYX	0:85b3fd62ea1a	736	*/
NYX	0:85b3fd62ea1a	737	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	738
NYX	0:85b3fd62ea1a	739	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	740	/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source
NYX	0:85b3fd62ea1a	741	* @{
NYX	0:85b3fd62ea1a	742	*/
NYX	0:85b3fd62ea1a	743	#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
NYX	0:85b3fd62ea1a	744	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
NYX	0:85b3fd62ea1a	745	#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
NYX	0:85b3fd62ea1a	746	#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 \| RCC_DCKCFGR_SAI1ASRC_1)
NYX	0:85b3fd62ea1a	747	/**
NYX	0:85b3fd62ea1a	748	* @}
NYX	0:85b3fd62ea1a	749	*/
NYX	0:85b3fd62ea1a	750
NYX	0:85b3fd62ea1a	751	/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source
NYX	0:85b3fd62ea1a	752	* @{
NYX	0:85b3fd62ea1a	753	*/
NYX	0:85b3fd62ea1a	754	#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
NYX	0:85b3fd62ea1a	755	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
NYX	0:85b3fd62ea1a	756	#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
NYX	0:85b3fd62ea1a	757	#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 \| RCC_DCKCFGR_SAI1BSRC_1)
NYX	0:85b3fd62ea1a	758	/**
NYX	0:85b3fd62ea1a	759	* @}
NYX	0:85b3fd62ea1a	760	*/
NYX	0:85b3fd62ea1a	761
NYX	0:85b3fd62ea1a	762	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
NYX	0:85b3fd62ea1a	763	* @{
NYX	0:85b3fd62ea1a	764	*/
NYX	0:85b3fd62ea1a	765	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
NYX	0:85b3fd62ea1a	766	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
NYX	0:85b3fd62ea1a	767	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
NYX	0:85b3fd62ea1a	768	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
NYX	0:85b3fd62ea1a	769	/**
NYX	0:85b3fd62ea1a	770	* @}
NYX	0:85b3fd62ea1a	771	*/
NYX	0:85b3fd62ea1a	772
NYX	0:85b3fd62ea1a	773
NYX	0:85b3fd62ea1a	774	/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source
NYX	0:85b3fd62ea1a	775	* @{
NYX	0:85b3fd62ea1a	776	*/
NYX	0:85b3fd62ea1a	777	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
NYX	0:85b3fd62ea1a	778	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
NYX	0:85b3fd62ea1a	779	/**
NYX	0:85b3fd62ea1a	780	* @}
NYX	0:85b3fd62ea1a	781	*/
NYX	0:85b3fd62ea1a	782
NYX	0:85b3fd62ea1a	783	/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source
NYX	0:85b3fd62ea1a	784	* @{
NYX	0:85b3fd62ea1a	785	*/
NYX	0:85b3fd62ea1a	786	#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
NYX	0:85b3fd62ea1a	787	#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
NYX	0:85b3fd62ea1a	788	/**
NYX	0:85b3fd62ea1a	789	* @}
NYX	0:85b3fd62ea1a	790	*/
NYX	0:85b3fd62ea1a	791
NYX	0:85b3fd62ea1a	792	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	793
NYX	0:85b3fd62ea1a	794	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	795	/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
NYX	0:85b3fd62ea1a	796	* @{
NYX	0:85b3fd62ea1a	797	*/
NYX	0:85b3fd62ea1a	798	#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
NYX	0:85b3fd62ea1a	799	#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
NYX	0:85b3fd62ea1a	800	/**
NYX	0:85b3fd62ea1a	801	* @}
NYX	0:85b3fd62ea1a	802	*/
NYX	0:85b3fd62ea1a	803
NYX	0:85b3fd62ea1a	804	/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
NYX	0:85b3fd62ea1a	805	* @{
NYX	0:85b3fd62ea1a	806	*/
NYX	0:85b3fd62ea1a	807	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
NYX	0:85b3fd62ea1a	808	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
NYX	0:85b3fd62ea1a	809	/**
NYX	0:85b3fd62ea1a	810	* @}
NYX	0:85b3fd62ea1a	811	*/
NYX	0:85b3fd62ea1a	812
NYX	0:85b3fd62ea1a	813	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
NYX	0:85b3fd62ea1a	814	* @{
NYX	0:85b3fd62ea1a	815	*/
NYX	0:85b3fd62ea1a	816	#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
NYX	0:85b3fd62ea1a	817	#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
NYX	0:85b3fd62ea1a	818	/**
NYX	0:85b3fd62ea1a	819	* @}
NYX	0:85b3fd62ea1a	820	*/
NYX	0:85b3fd62ea1a	821
NYX	0:85b3fd62ea1a	822	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
NYX	0:85b3fd62ea1a	823	* @{
NYX	0:85b3fd62ea1a	824	*/
NYX	0:85b3fd62ea1a	825	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
NYX	0:85b3fd62ea1a	826	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
NYX	0:85b3fd62ea1a	827	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
NYX	0:85b3fd62ea1a	828	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
NYX	0:85b3fd62ea1a	829	/**
NYX	0:85b3fd62ea1a	830	* @}
NYX	0:85b3fd62ea1a	831	*/
NYX	0:85b3fd62ea1a	832
NYX	0:85b3fd62ea1a	833	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
NYX	0:85b3fd62ea1a	834	* @{
NYX	0:85b3fd62ea1a	835	*/
NYX	0:85b3fd62ea1a	836	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
NYX	0:85b3fd62ea1a	837	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
NYX	0:85b3fd62ea1a	838	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
NYX	0:85b3fd62ea1a	839	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
NYX	0:85b3fd62ea1a	840	/**
NYX	0:85b3fd62ea1a	841	* @}
NYX	0:85b3fd62ea1a	842	*/
NYX	0:85b3fd62ea1a	843
NYX	0:85b3fd62ea1a	844	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
NYX	0:85b3fd62ea1a	845	* @{
NYX	0:85b3fd62ea1a	846	*/
NYX	0:85b3fd62ea1a	847	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
NYX	0:85b3fd62ea1a	848	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
NYX	0:85b3fd62ea1a	849	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
NYX	0:85b3fd62ea1a	850	/**
NYX	0:85b3fd62ea1a	851	* @}
NYX	0:85b3fd62ea1a	852	*/
NYX	0:85b3fd62ea1a	853
NYX	0:85b3fd62ea1a	854	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
NYX	0:85b3fd62ea1a	855	* @{
NYX	0:85b3fd62ea1a	856	*/
NYX	0:85b3fd62ea1a	857	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
NYX	0:85b3fd62ea1a	858	#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	859	/**
NYX	0:85b3fd62ea1a	860	* @}
NYX	0:85b3fd62ea1a	861	*/
NYX	0:85b3fd62ea1a	862
NYX	0:85b3fd62ea1a	863	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
NYX	0:85b3fd62ea1a	864	* @{
NYX	0:85b3fd62ea1a	865	*/
NYX	0:85b3fd62ea1a	866	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
NYX	0:85b3fd62ea1a	867	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
NYX	0:85b3fd62ea1a	868	/**
NYX	0:85b3fd62ea1a	869	* @}
NYX	0:85b3fd62ea1a	870	*/
NYX	0:85b3fd62ea1a	871	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	872
NYX	0:85b3fd62ea1a	873	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	874	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
NYX	0:85b3fd62ea1a	875	* @{
NYX	0:85b3fd62ea1a	876	*/
NYX	0:85b3fd62ea1a	877	#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
NYX	0:85b3fd62ea1a	878	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
NYX	0:85b3fd62ea1a	879	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
NYX	0:85b3fd62ea1a	880	/**
NYX	0:85b3fd62ea1a	881	* @}
NYX	0:85b3fd62ea1a	882	*/
NYX	0:85b3fd62ea1a	883
NYX	0:85b3fd62ea1a	884	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
NYX	0:85b3fd62ea1a	885	* @{
NYX	0:85b3fd62ea1a	886	*/
NYX	0:85b3fd62ea1a	887	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
NYX	0:85b3fd62ea1a	888	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
NYX	0:85b3fd62ea1a	889	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
NYX	0:85b3fd62ea1a	890	/**
NYX	0:85b3fd62ea1a	891	* @}
NYX	0:85b3fd62ea1a	892	*/
NYX	0:85b3fd62ea1a	893
NYX	0:85b3fd62ea1a	894	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
NYX	0:85b3fd62ea1a	895	* @{
NYX	0:85b3fd62ea1a	896	*/
NYX	0:85b3fd62ea1a	897	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
NYX	0:85b3fd62ea1a	898	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
NYX	0:85b3fd62ea1a	899	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
NYX	0:85b3fd62ea1a	900	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
NYX	0:85b3fd62ea1a	901	/**
NYX	0:85b3fd62ea1a	902	* @}
NYX	0:85b3fd62ea1a	903	*/
NYX	0:85b3fd62ea1a	904	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	905
NYX	0:85b3fd62ea1a	906	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	907	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	908	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	909	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
NYX	0:85b3fd62ea1a	910	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	911	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
NYX	0:85b3fd62ea1a	912	* @{
NYX	0:85b3fd62ea1a	913	*/
NYX	0:85b3fd62ea1a	914	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
NYX	0:85b3fd62ea1a	915	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
NYX	0:85b3fd62ea1a	916	/**
NYX	0:85b3fd62ea1a	917	* @}
NYX	0:85b3fd62ea1a	918	*/
NYX	0:85b3fd62ea1a	919	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
NYX	0:85b3fd62ea1a	920	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
NYX	0:85b3fd62ea1a	921	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	922
NYX	0:85b3fd62ea1a	923	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
NYX	0:85b3fd62ea1a	924	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	925	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
NYX	0:85b3fd62ea1a	926	defined(STM32F423xx)
NYX	0:85b3fd62ea1a	927	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
NYX	0:85b3fd62ea1a	928	* @{
NYX	0:85b3fd62ea1a	929	*/
NYX	0:85b3fd62ea1a	930	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
NYX	0:85b3fd62ea1a	931	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
NYX	0:85b3fd62ea1a	932	/**
NYX	0:85b3fd62ea1a	933	* @}
NYX	0:85b3fd62ea1a	934	*/
NYX	0:85b3fd62ea1a	935	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
NYX	0:85b3fd62ea1a	936	STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	937
NYX	0:85b3fd62ea1a	938	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
NYX	0:85b3fd62ea1a	939	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
NYX	0:85b3fd62ea1a	940	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
NYX	0:85b3fd62ea1a	941	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
NYX	0:85b3fd62ea1a	942	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	943	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
NYX	0:85b3fd62ea1a	944	* @{
NYX	0:85b3fd62ea1a	945	*/
NYX	0:85b3fd62ea1a	946	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
NYX	0:85b3fd62ea1a	947	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
NYX	0:85b3fd62ea1a	948	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
NYX	0:85b3fd62ea1a	949	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
NYX	0:85b3fd62ea1a	950	/**
NYX	0:85b3fd62ea1a	951	* @}
NYX	0:85b3fd62ea1a	952	*/
NYX	0:85b3fd62ea1a	953	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
NYX	0:85b3fd62ea1a	954	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
NYX	0:85b3fd62ea1a	955	STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
NYX	0:85b3fd62ea1a	956
NYX	0:85b3fd62ea1a	957	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	958	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
NYX	0:85b3fd62ea1a	959	* @{
NYX	0:85b3fd62ea1a	960	*/
NYX	0:85b3fd62ea1a	961	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
NYX	0:85b3fd62ea1a	962	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
NYX	0:85b3fd62ea1a	963	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
NYX	0:85b3fd62ea1a	964	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
NYX	0:85b3fd62ea1a	965	/**
NYX	0:85b3fd62ea1a	966	* @}
NYX	0:85b3fd62ea1a	967	*/
NYX	0:85b3fd62ea1a	968	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	969
NYX	0:85b3fd62ea1a	970	/**
NYX	0:85b3fd62ea1a	971	* @}
NYX	0:85b3fd62ea1a	972	*/
NYX	0:85b3fd62ea1a	973
NYX	0:85b3fd62ea1a	974	/* Exported macro ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	975	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
NYX	0:85b3fd62ea1a	976	* @{
NYX	0:85b3fd62ea1a	977	*/
NYX	0:85b3fd62ea1a	978	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
NYX	0:85b3fd62ea1a	979	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	980	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	981	* @brief Enables or disables the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	982	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	983	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	984	* using it.
NYX	0:85b3fd62ea1a	985	* @{
NYX	0:85b3fd62ea1a	986	*/
NYX	0:85b3fd62ea1a	987	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	988	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	989	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
NYX	0:85b3fd62ea1a	990	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	991	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
NYX	0:85b3fd62ea1a	992	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	993	} while(0U)
NYX	0:85b3fd62ea1a	994	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	995	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	996	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	997	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	998	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	999	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1000	} while(0U)
NYX	0:85b3fd62ea1a	1001	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1002	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1003	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	1004	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1005	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	1006	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1007	} while(0U)
NYX	0:85b3fd62ea1a	1008	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1009	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1010	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	1011	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1012	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	1013	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1014	} while(0U)
NYX	0:85b3fd62ea1a	1015	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1016	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1017	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	1018	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1019	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	1020	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1021	} while(0U)
NYX	0:85b3fd62ea1a	1022	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1023	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1024	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
NYX	0:85b3fd62ea1a	1025	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1026	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
NYX	0:85b3fd62ea1a	1027	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1028	} while(0U)
NYX	0:85b3fd62ea1a	1029	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1030	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1031	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
NYX	0:85b3fd62ea1a	1032	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1033	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
NYX	0:85b3fd62ea1a	1034	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1035	} while(0U)
NYX	0:85b3fd62ea1a	1036	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1037	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1038	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
NYX	0:85b3fd62ea1a	1039	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1040	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
NYX	0:85b3fd62ea1a	1041	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1042	} while(0U)
NYX	0:85b3fd62ea1a	1043	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1044	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1045	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
NYX	0:85b3fd62ea1a	1046	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1047	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
NYX	0:85b3fd62ea1a	1048	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1049	} while(0U)
NYX	0:85b3fd62ea1a	1050	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1051	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1052	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
NYX	0:85b3fd62ea1a	1053	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1054	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
NYX	0:85b3fd62ea1a	1055	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1056	} while(0U)
NYX	0:85b3fd62ea1a	1057	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1058	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1059	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
NYX	0:85b3fd62ea1a	1060	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1061	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
NYX	0:85b3fd62ea1a	1062	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1063	} while(0U)
NYX	0:85b3fd62ea1a	1064	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1065	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1066	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
NYX	0:85b3fd62ea1a	1067	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1068	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
NYX	0:85b3fd62ea1a	1069	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1070	} while(0U)
NYX	0:85b3fd62ea1a	1071	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1072	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1073	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
NYX	0:85b3fd62ea1a	1074	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1075	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
NYX	0:85b3fd62ea1a	1076	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1077	} while(0U)
NYX	0:85b3fd62ea1a	1078	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1079	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1080	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
NYX	0:85b3fd62ea1a	1081	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1082	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
NYX	0:85b3fd62ea1a	1083	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1084	} while(0U)
NYX	0:85b3fd62ea1a	1085	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1086	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1087	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
NYX	0:85b3fd62ea1a	1088	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1089	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
NYX	0:85b3fd62ea1a	1090	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1091	} while(0U)
NYX	0:85b3fd62ea1a	1092	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1093	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1094	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
NYX	0:85b3fd62ea1a	1095	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1096	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
NYX	0:85b3fd62ea1a	1097	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1098	} while(0U)
NYX	0:85b3fd62ea1a	1099	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1100	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1101	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
NYX	0:85b3fd62ea1a	1102	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1103	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
NYX	0:85b3fd62ea1a	1104	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1105	} while(0U)
NYX	0:85b3fd62ea1a	1106	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
NYX	0:85b3fd62ea1a	1107	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
NYX	0:85b3fd62ea1a	1108	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
NYX	0:85b3fd62ea1a	1109	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
NYX	0:85b3fd62ea1a	1110	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
NYX	0:85b3fd62ea1a	1111	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
NYX	0:85b3fd62ea1a	1112	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
NYX	0:85b3fd62ea1a	1113	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
NYX	0:85b3fd62ea1a	1114	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
NYX	0:85b3fd62ea1a	1115	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
NYX	0:85b3fd62ea1a	1116	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
NYX	0:85b3fd62ea1a	1117	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
NYX	0:85b3fd62ea1a	1118	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
NYX	0:85b3fd62ea1a	1119	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
NYX	0:85b3fd62ea1a	1120	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
NYX	0:85b3fd62ea1a	1121	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
NYX	0:85b3fd62ea1a	1122	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
NYX	0:85b3fd62ea1a	1123
NYX	0:85b3fd62ea1a	1124	/**
NYX	0:85b3fd62ea1a	1125	* @brief Enable ETHERNET clock.
NYX	0:85b3fd62ea1a	1126	*/
NYX	0:85b3fd62ea1a	1127	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1128	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
NYX	0:85b3fd62ea1a	1129	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
NYX	0:85b3fd62ea1a	1130	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
NYX	0:85b3fd62ea1a	1131	} while(0U)
NYX	0:85b3fd62ea1a	1132	/**
NYX	0:85b3fd62ea1a	1133	* @brief Disable ETHERNET clock.
NYX	0:85b3fd62ea1a	1134	*/
NYX	0:85b3fd62ea1a	1135	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
NYX	0:85b3fd62ea1a	1136	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
NYX	0:85b3fd62ea1a	1137	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
NYX	0:85b3fd62ea1a	1138	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
NYX	0:85b3fd62ea1a	1139	} while(0U)
NYX	0:85b3fd62ea1a	1140	/**
NYX	0:85b3fd62ea1a	1141	* @}
NYX	0:85b3fd62ea1a	1142	*/
NYX	0:85b3fd62ea1a	1143
NYX	0:85b3fd62ea1a	1144	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	1145	* @brief Get the enable or disable status of the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	1146	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	1147	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	1148	* using it.
NYX	0:85b3fd62ea1a	1149	* @{
NYX	0:85b3fd62ea1a	1150	*/
NYX	0:85b3fd62ea1a	1151	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
NYX	0:85b3fd62ea1a	1152	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
NYX	0:85b3fd62ea1a	1153	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
NYX	0:85b3fd62ea1a	1154	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
NYX	0:85b3fd62ea1a	1155	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
NYX	0:85b3fd62ea1a	1156	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
NYX	0:85b3fd62ea1a	1157	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
NYX	0:85b3fd62ea1a	1158	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
NYX	0:85b3fd62ea1a	1159	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
NYX	0:85b3fd62ea1a	1160	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
NYX	0:85b3fd62ea1a	1161	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
NYX	0:85b3fd62ea1a	1162	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
NYX	0:85b3fd62ea1a	1163	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
NYX	0:85b3fd62ea1a	1164	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
NYX	0:85b3fd62ea1a	1165	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
NYX	0:85b3fd62ea1a	1166	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
NYX	0:85b3fd62ea1a	1167	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
NYX	0:85b3fd62ea1a	1168	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
NYX	0:85b3fd62ea1a	1169	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
NYX	0:85b3fd62ea1a	1170	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
NYX	0:85b3fd62ea1a	1171
NYX	0:85b3fd62ea1a	1172	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
NYX	0:85b3fd62ea1a	1173	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
NYX	0:85b3fd62ea1a	1174	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
NYX	0:85b3fd62ea1a	1175	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
NYX	0:85b3fd62ea1a	1176	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
NYX	0:85b3fd62ea1a	1177	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
NYX	0:85b3fd62ea1a	1178	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
NYX	0:85b3fd62ea1a	1179	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
NYX	0:85b3fd62ea1a	1180	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
NYX	0:85b3fd62ea1a	1181	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
NYX	0:85b3fd62ea1a	1182	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
NYX	0:85b3fd62ea1a	1183	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
NYX	0:85b3fd62ea1a	1184	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
NYX	0:85b3fd62ea1a	1185	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
NYX	0:85b3fd62ea1a	1186	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
NYX	0:85b3fd62ea1a	1187	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
NYX	0:85b3fd62ea1a	1188	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
NYX	0:85b3fd62ea1a	1189	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
NYX	0:85b3fd62ea1a	1190	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
NYX	0:85b3fd62ea1a	1191	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
NYX	0:85b3fd62ea1a	1192	/**
NYX	0:85b3fd62ea1a	1193	* @}
NYX	0:85b3fd62ea1a	1194	*/
NYX	0:85b3fd62ea1a	1195
NYX	0:85b3fd62ea1a	1196	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	1197	* @brief Enable or disable the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	1198	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	1199	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	1200	* using it.
NYX	0:85b3fd62ea1a	1201	* @{
NYX	0:85b3fd62ea1a	1202	*/
NYX	0:85b3fd62ea1a	1203	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1204	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1205	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
NYX	0:85b3fd62ea1a	1206	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1207	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
NYX	0:85b3fd62ea1a	1208	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1209	} while(0U)
NYX	0:85b3fd62ea1a	1210	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
NYX	0:85b3fd62ea1a	1211
NYX	0:85b3fd62ea1a	1212	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1213	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1214	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1215	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
NYX	0:85b3fd62ea1a	1216	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1217	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
NYX	0:85b3fd62ea1a	1218	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1219	} while(0U)
NYX	0:85b3fd62ea1a	1220	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1221	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1222	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
NYX	0:85b3fd62ea1a	1223	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1224	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
NYX	0:85b3fd62ea1a	1225	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1226	} while(0U)
NYX	0:85b3fd62ea1a	1227
NYX	0:85b3fd62ea1a	1228	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
NYX	0:85b3fd62ea1a	1229	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
NYX	0:85b3fd62ea1a	1230	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1231
NYX	0:85b3fd62ea1a	1232	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
NYX	0:85b3fd62ea1a	1233	__HAL_RCC_SYSCFG_CLK_ENABLE();\
NYX	0:85b3fd62ea1a	1234	}while(0U)
NYX	0:85b3fd62ea1a	1235
NYX	0:85b3fd62ea1a	1236	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
NYX	0:85b3fd62ea1a	1237
NYX	0:85b3fd62ea1a	1238	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1239	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1240	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
NYX	0:85b3fd62ea1a	1241	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1242	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
NYX	0:85b3fd62ea1a	1243	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1244	} while(0U)
NYX	0:85b3fd62ea1a	1245	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
NYX	0:85b3fd62ea1a	1246	/**
NYX	0:85b3fd62ea1a	1247	* @}
NYX	0:85b3fd62ea1a	1248	*/
NYX	0:85b3fd62ea1a	1249
NYX	0:85b3fd62ea1a	1250	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	1251	* @brief Get the enable or disable status of the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	1252	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	1253	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	1254	* using it.
NYX	0:85b3fd62ea1a	1255	* @{
NYX	0:85b3fd62ea1a	1256	*/
NYX	0:85b3fd62ea1a	1257	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
NYX	0:85b3fd62ea1a	1258	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
NYX	0:85b3fd62ea1a	1259
NYX	0:85b3fd62ea1a	1260	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1261	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
NYX	0:85b3fd62ea1a	1262	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
NYX	0:85b3fd62ea1a	1263
NYX	0:85b3fd62ea1a	1264	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
NYX	0:85b3fd62ea1a	1265	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
NYX	0:85b3fd62ea1a	1266	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1267
NYX	0:85b3fd62ea1a	1268	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
NYX	0:85b3fd62ea1a	1269	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
NYX	0:85b3fd62ea1a	1270
NYX	0:85b3fd62ea1a	1271	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
NYX	0:85b3fd62ea1a	1272	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
NYX	0:85b3fd62ea1a	1273	/**
NYX	0:85b3fd62ea1a	1274	* @}
NYX	0:85b3fd62ea1a	1275	*/
NYX	0:85b3fd62ea1a	1276
NYX	0:85b3fd62ea1a	1277	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	1278	* @brief Enables or disables the AHB3 peripheral clock.
NYX	0:85b3fd62ea1a	1279	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	1280	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	1281	* using it.
NYX	0:85b3fd62ea1a	1282	* @{
NYX	0:85b3fd62ea1a	1283	*/
NYX	0:85b3fd62ea1a	1284	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1285	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1286	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
NYX	0:85b3fd62ea1a	1287	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1288	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
NYX	0:85b3fd62ea1a	1289	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1290	} while(0U)
NYX	0:85b3fd62ea1a	1291	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
NYX	0:85b3fd62ea1a	1292	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1293	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1294	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1295	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
NYX	0:85b3fd62ea1a	1296	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1297	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
NYX	0:85b3fd62ea1a	1298	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1299	} while(0U)
NYX	0:85b3fd62ea1a	1300	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
NYX	0:85b3fd62ea1a	1301	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1302	/**
NYX	0:85b3fd62ea1a	1303	* @}
NYX	0:85b3fd62ea1a	1304	*/
NYX	0:85b3fd62ea1a	1305
NYX	0:85b3fd62ea1a	1306
NYX	0:85b3fd62ea1a	1307	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	1308	* @brief Get the enable or disable status of the AHB3 peripheral clock.
NYX	0:85b3fd62ea1a	1309	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	1310	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	1311	* using it.
NYX	0:85b3fd62ea1a	1312	* @{
NYX	0:85b3fd62ea1a	1313	*/
NYX	0:85b3fd62ea1a	1314	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
NYX	0:85b3fd62ea1a	1315	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
NYX	0:85b3fd62ea1a	1316	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1317	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
NYX	0:85b3fd62ea1a	1318	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
NYX	0:85b3fd62ea1a	1319	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1320	/**
NYX	0:85b3fd62ea1a	1321	* @}
NYX	0:85b3fd62ea1a	1322	*/
NYX	0:85b3fd62ea1a	1323
NYX	0:85b3fd62ea1a	1324	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	1325	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
NYX	0:85b3fd62ea1a	1326	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	1327	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	1328	* using it.
NYX	0:85b3fd62ea1a	1329	* @{
NYX	0:85b3fd62ea1a	1330	*/
NYX	0:85b3fd62ea1a	1331	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1332	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1333	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	1334	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1335	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	1336	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1337	} while(0U)
NYX	0:85b3fd62ea1a	1338	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1339	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1340	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
NYX	0:85b3fd62ea1a	1341	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1342	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
NYX	0:85b3fd62ea1a	1343	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1344	} while(0U)
NYX	0:85b3fd62ea1a	1345	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1346	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1347	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
NYX	0:85b3fd62ea1a	1348	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1349	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
NYX	0:85b3fd62ea1a	1350	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1351	} while(0U)
NYX	0:85b3fd62ea1a	1352	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1353	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1354	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
NYX	0:85b3fd62ea1a	1355	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1356	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
NYX	0:85b3fd62ea1a	1357	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1358	} while(0U)
NYX	0:85b3fd62ea1a	1359	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1360	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1361	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	1362	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1363	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	1364	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1365	} while(0U)
NYX	0:85b3fd62ea1a	1366	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1367	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1368	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	1369	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1370	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	1371	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1372	} while(0U)
NYX	0:85b3fd62ea1a	1373	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1374	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1375	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
NYX	0:85b3fd62ea1a	1376	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1377	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
NYX	0:85b3fd62ea1a	1378	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1379	} while(0U)
NYX	0:85b3fd62ea1a	1380	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1381	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1382	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
NYX	0:85b3fd62ea1a	1383	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1384	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
NYX	0:85b3fd62ea1a	1385	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1386	} while(0U)
NYX	0:85b3fd62ea1a	1387	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1388	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1389	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
NYX	0:85b3fd62ea1a	1390	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1391	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
NYX	0:85b3fd62ea1a	1392	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1393	} while(0U)
NYX	0:85b3fd62ea1a	1394	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1395	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1396	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
NYX	0:85b3fd62ea1a	1397	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1398	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
NYX	0:85b3fd62ea1a	1399	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1400	} while(0U)
NYX	0:85b3fd62ea1a	1401	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1402	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1403	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
NYX	0:85b3fd62ea1a	1404	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1405	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
NYX	0:85b3fd62ea1a	1406	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1407	} while(0U)
NYX	0:85b3fd62ea1a	1408	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1409	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1410	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	1411	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1412	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	1413	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1414	} while(0U)
NYX	0:85b3fd62ea1a	1415	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1416	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1417	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
NYX	0:85b3fd62ea1a	1418	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1419	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
NYX	0:85b3fd62ea1a	1420	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1421	} while(0U)
NYX	0:85b3fd62ea1a	1422	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1423	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1424	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
NYX	0:85b3fd62ea1a	1425	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1426	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
NYX	0:85b3fd62ea1a	1427	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1428	} while(0U)
NYX	0:85b3fd62ea1a	1429	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1430	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1431	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	1432	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1433	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	1434	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1435	} while(0U)
NYX	0:85b3fd62ea1a	1436	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1437	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1438	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	1439	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1440	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	1441	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1442	} while(0U)
NYX	0:85b3fd62ea1a	1443	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1444	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1445	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	1446	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1447	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	1448	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1449	} while(0U)
NYX	0:85b3fd62ea1a	1450	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1451	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1452	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	1453	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1454	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	1455	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1456	} while(0U)
NYX	0:85b3fd62ea1a	1457	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1458	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1459	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	1460	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1461	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	1462	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1463	} while(0U)
NYX	0:85b3fd62ea1a	1464	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
NYX	0:85b3fd62ea1a	1465	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
NYX	0:85b3fd62ea1a	1466	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
NYX	0:85b3fd62ea1a	1467	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
NYX	0:85b3fd62ea1a	1468	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
NYX	0:85b3fd62ea1a	1469	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
NYX	0:85b3fd62ea1a	1470	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
NYX	0:85b3fd62ea1a	1471	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
NYX	0:85b3fd62ea1a	1472	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
NYX	0:85b3fd62ea1a	1473	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
NYX	0:85b3fd62ea1a	1474	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
NYX	0:85b3fd62ea1a	1475	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
NYX	0:85b3fd62ea1a	1476	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
NYX	0:85b3fd62ea1a	1477	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
NYX	0:85b3fd62ea1a	1478	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
NYX	0:85b3fd62ea1a	1479	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
NYX	0:85b3fd62ea1a	1480	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
NYX	0:85b3fd62ea1a	1481	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
NYX	0:85b3fd62ea1a	1482	/**
NYX	0:85b3fd62ea1a	1483	* @}
NYX	0:85b3fd62ea1a	1484	*/
NYX	0:85b3fd62ea1a	1485
NYX	0:85b3fd62ea1a	1486	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	1487	* @brief Get the enable or disable status of the APB1 peripheral clock.
NYX	0:85b3fd62ea1a	1488	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	1489	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	1490	* using it.
NYX	0:85b3fd62ea1a	1491	* @{
NYX	0:85b3fd62ea1a	1492	*/
NYX	0:85b3fd62ea1a	1493	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
NYX	0:85b3fd62ea1a	1494	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
NYX	0:85b3fd62ea1a	1495	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
NYX	0:85b3fd62ea1a	1496	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
NYX	0:85b3fd62ea1a	1497	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
NYX	0:85b3fd62ea1a	1498	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
NYX	0:85b3fd62ea1a	1499	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
NYX	0:85b3fd62ea1a	1500	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
NYX	0:85b3fd62ea1a	1501	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
NYX	0:85b3fd62ea1a	1502	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
NYX	0:85b3fd62ea1a	1503	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
NYX	0:85b3fd62ea1a	1504	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
NYX	0:85b3fd62ea1a	1505	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
NYX	0:85b3fd62ea1a	1506	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
NYX	0:85b3fd62ea1a	1507	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
NYX	0:85b3fd62ea1a	1508	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
NYX	0:85b3fd62ea1a	1509	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
NYX	0:85b3fd62ea1a	1510	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
NYX	0:85b3fd62ea1a	1511
NYX	0:85b3fd62ea1a	1512	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
NYX	0:85b3fd62ea1a	1513	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
NYX	0:85b3fd62ea1a	1514	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
NYX	0:85b3fd62ea1a	1515	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
NYX	0:85b3fd62ea1a	1516	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
NYX	0:85b3fd62ea1a	1517	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
NYX	0:85b3fd62ea1a	1518	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
NYX	0:85b3fd62ea1a	1519	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
NYX	0:85b3fd62ea1a	1520	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
NYX	0:85b3fd62ea1a	1521	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
NYX	0:85b3fd62ea1a	1522	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
NYX	0:85b3fd62ea1a	1523	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
NYX	0:85b3fd62ea1a	1524	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
NYX	0:85b3fd62ea1a	1525	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
NYX	0:85b3fd62ea1a	1526	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
NYX	0:85b3fd62ea1a	1527	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
NYX	0:85b3fd62ea1a	1528	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
NYX	0:85b3fd62ea1a	1529	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
NYX	0:85b3fd62ea1a	1530	/**
NYX	0:85b3fd62ea1a	1531	* @}
NYX	0:85b3fd62ea1a	1532	*/
NYX	0:85b3fd62ea1a	1533
NYX	0:85b3fd62ea1a	1534	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	1535	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
NYX	0:85b3fd62ea1a	1536	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	1537	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	1538	* using it.
NYX	0:85b3fd62ea1a	1539	* @{
NYX	0:85b3fd62ea1a	1540	*/
NYX	0:85b3fd62ea1a	1541	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1542	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1543	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
NYX	0:85b3fd62ea1a	1544	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1545	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
NYX	0:85b3fd62ea1a	1546	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1547	} while(0U)
NYX	0:85b3fd62ea1a	1548	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1549	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1550	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
NYX	0:85b3fd62ea1a	1551	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1552	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
NYX	0:85b3fd62ea1a	1553	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1554	} while(0U)
NYX	0:85b3fd62ea1a	1555	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1556	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1557	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
NYX	0:85b3fd62ea1a	1558	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1559	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
NYX	0:85b3fd62ea1a	1560	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1561	} while(0U)
NYX	0:85b3fd62ea1a	1562	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1563	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1564	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
NYX	0:85b3fd62ea1a	1565	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1566	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
NYX	0:85b3fd62ea1a	1567	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1568	} while(0U)
NYX	0:85b3fd62ea1a	1569	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1570	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1571	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
NYX	0:85b3fd62ea1a	1572	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1573	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
NYX	0:85b3fd62ea1a	1574	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1575	} while(0U)
NYX	0:85b3fd62ea1a	1576	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1577	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1578	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
NYX	0:85b3fd62ea1a	1579	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1580	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
NYX	0:85b3fd62ea1a	1581	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1582	} while(0U)
NYX	0:85b3fd62ea1a	1583	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1584	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1585	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	1586	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1587	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	1588	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1589	} while(0U)
NYX	0:85b3fd62ea1a	1590	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1591	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1592	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	1593	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1594	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	1595	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1596	} while(0U)
NYX	0:85b3fd62ea1a	1597	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1598	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1599	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	1600	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1601	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	1602	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1603	} while(0U)
NYX	0:85b3fd62ea1a	1604	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
NYX	0:85b3fd62ea1a	1605	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
NYX	0:85b3fd62ea1a	1606	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
NYX	0:85b3fd62ea1a	1607	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
NYX	0:85b3fd62ea1a	1608	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
NYX	0:85b3fd62ea1a	1609	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
NYX	0:85b3fd62ea1a	1610	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
NYX	0:85b3fd62ea1a	1611	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
NYX	0:85b3fd62ea1a	1612	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
NYX	0:85b3fd62ea1a	1613
NYX	0:85b3fd62ea1a	1614	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1615	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1616	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1617	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
NYX	0:85b3fd62ea1a	1618	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1619	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
NYX	0:85b3fd62ea1a	1620	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1621	} while(0U)
NYX	0:85b3fd62ea1a	1622
NYX	0:85b3fd62ea1a	1623	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
NYX	0:85b3fd62ea1a	1624	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1625
NYX	0:85b3fd62ea1a	1626	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1627	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	1628	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	1629	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
NYX	0:85b3fd62ea1a	1630	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	1631	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
NYX	0:85b3fd62ea1a	1632	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	1633	} while(0U)
NYX	0:85b3fd62ea1a	1634
NYX	0:85b3fd62ea1a	1635	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
NYX	0:85b3fd62ea1a	1636	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1637	/**
NYX	0:85b3fd62ea1a	1638	* @}
NYX	0:85b3fd62ea1a	1639	*/
NYX	0:85b3fd62ea1a	1640
NYX	0:85b3fd62ea1a	1641	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	1642	* @brief Get the enable or disable status of the APB2 peripheral clock.
NYX	0:85b3fd62ea1a	1643	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	1644	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	1645	* using it.
NYX	0:85b3fd62ea1a	1646	* @{
NYX	0:85b3fd62ea1a	1647	*/
NYX	0:85b3fd62ea1a	1648	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
NYX	0:85b3fd62ea1a	1649	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
NYX	0:85b3fd62ea1a	1650	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
NYX	0:85b3fd62ea1a	1651	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
NYX	0:85b3fd62ea1a	1652	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
NYX	0:85b3fd62ea1a	1653	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
NYX	0:85b3fd62ea1a	1654	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
NYX	0:85b3fd62ea1a	1655	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
NYX	0:85b3fd62ea1a	1656	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
NYX	0:85b3fd62ea1a	1657
NYX	0:85b3fd62ea1a	1658	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
NYX	0:85b3fd62ea1a	1659	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
NYX	0:85b3fd62ea1a	1660	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
NYX	0:85b3fd62ea1a	1661	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
NYX	0:85b3fd62ea1a	1662	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
NYX	0:85b3fd62ea1a	1663	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
NYX	0:85b3fd62ea1a	1664	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
NYX	0:85b3fd62ea1a	1665	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
NYX	0:85b3fd62ea1a	1666	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
NYX	0:85b3fd62ea1a	1667
NYX	0:85b3fd62ea1a	1668	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1669	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
NYX	0:85b3fd62ea1a	1670	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
NYX	0:85b3fd62ea1a	1671	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1672
NYX	0:85b3fd62ea1a	1673	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1674	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
NYX	0:85b3fd62ea1a	1675	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
NYX	0:85b3fd62ea1a	1676	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1677	/**
NYX	0:85b3fd62ea1a	1678	* @}
NYX	0:85b3fd62ea1a	1679	*/
NYX	0:85b3fd62ea1a	1680
NYX	0:85b3fd62ea1a	1681	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
NYX	0:85b3fd62ea1a	1682	* @brief Force or release AHB1 peripheral reset.
NYX	0:85b3fd62ea1a	1683	* @{
NYX	0:85b3fd62ea1a	1684	*/
NYX	0:85b3fd62ea1a	1685	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	1686	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	1687	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
NYX	0:85b3fd62ea1a	1688	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
NYX	0:85b3fd62ea1a	1689	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
NYX	0:85b3fd62ea1a	1690	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
NYX	0:85b3fd62ea1a	1691	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
NYX	0:85b3fd62ea1a	1692	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
NYX	0:85b3fd62ea1a	1693	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
NYX	0:85b3fd62ea1a	1694	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
NYX	0:85b3fd62ea1a	1695	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	1696
NYX	0:85b3fd62ea1a	1697	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	1698	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	1699	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
NYX	0:85b3fd62ea1a	1700	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
NYX	0:85b3fd62ea1a	1701	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
NYX	0:85b3fd62ea1a	1702	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
NYX	0:85b3fd62ea1a	1703	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
NYX	0:85b3fd62ea1a	1704	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
NYX	0:85b3fd62ea1a	1705	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
NYX	0:85b3fd62ea1a	1706	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
NYX	0:85b3fd62ea1a	1707	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	1708	/**
NYX	0:85b3fd62ea1a	1709	* @}
NYX	0:85b3fd62ea1a	1710	*/
NYX	0:85b3fd62ea1a	1711
NYX	0:85b3fd62ea1a	1712	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
NYX	0:85b3fd62ea1a	1713	* @brief Force or release AHB2 peripheral reset.
NYX	0:85b3fd62ea1a	1714	* @{
NYX	0:85b3fd62ea1a	1715	*/
NYX	0:85b3fd62ea1a	1716	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	1717	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	1718	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
NYX	0:85b3fd62ea1a	1719	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
NYX	0:85b3fd62ea1a	1720
NYX	0:85b3fd62ea1a	1721	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
NYX	0:85b3fd62ea1a	1722	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	1723	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
NYX	0:85b3fd62ea1a	1724	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
NYX	0:85b3fd62ea1a	1725
NYX	0:85b3fd62ea1a	1726	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1727	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
NYX	0:85b3fd62ea1a	1728	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
NYX	0:85b3fd62ea1a	1729
NYX	0:85b3fd62ea1a	1730	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
NYX	0:85b3fd62ea1a	1731	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
NYX	0:85b3fd62ea1a	1732	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1733	/**
NYX	0:85b3fd62ea1a	1734	* @}
NYX	0:85b3fd62ea1a	1735	*/
NYX	0:85b3fd62ea1a	1736
NYX	0:85b3fd62ea1a	1737	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
NYX	0:85b3fd62ea1a	1738	* @brief Force or release AHB3 peripheral reset.
NYX	0:85b3fd62ea1a	1739	* @{
NYX	0:85b3fd62ea1a	1740	*/
NYX	0:85b3fd62ea1a	1741	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	1742	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
NYX	0:85b3fd62ea1a	1743	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
NYX	0:85b3fd62ea1a	1744	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
NYX	0:85b3fd62ea1a	1745
NYX	0:85b3fd62ea1a	1746	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1747	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
NYX	0:85b3fd62ea1a	1748	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
NYX	0:85b3fd62ea1a	1749	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1750	/**
NYX	0:85b3fd62ea1a	1751	* @}
NYX	0:85b3fd62ea1a	1752	*/
NYX	0:85b3fd62ea1a	1753
NYX	0:85b3fd62ea1a	1754	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
NYX	0:85b3fd62ea1a	1755	* @brief Force or release APB1 peripheral reset.
NYX	0:85b3fd62ea1a	1756	* @{
NYX	0:85b3fd62ea1a	1757	*/
NYX	0:85b3fd62ea1a	1758	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	1759	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
NYX	0:85b3fd62ea1a	1760	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
NYX	0:85b3fd62ea1a	1761	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
NYX	0:85b3fd62ea1a	1762	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
NYX	0:85b3fd62ea1a	1763	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
NYX	0:85b3fd62ea1a	1764	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
NYX	0:85b3fd62ea1a	1765	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
NYX	0:85b3fd62ea1a	1766	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
NYX	0:85b3fd62ea1a	1767	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
NYX	0:85b3fd62ea1a	1768	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	1769	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
NYX	0:85b3fd62ea1a	1770	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
NYX	0:85b3fd62ea1a	1771	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	1772	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	1773	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	1774	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	1775	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	1776
NYX	0:85b3fd62ea1a	1777	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	1778	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	1779	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	1780	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	1781	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	1782	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	1783	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
NYX	0:85b3fd62ea1a	1784	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
NYX	0:85b3fd62ea1a	1785	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
NYX	0:85b3fd62ea1a	1786	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
NYX	0:85b3fd62ea1a	1787	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
NYX	0:85b3fd62ea1a	1788	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
NYX	0:85b3fd62ea1a	1789	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
NYX	0:85b3fd62ea1a	1790	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
NYX	0:85b3fd62ea1a	1791	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
NYX	0:85b3fd62ea1a	1792	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	1793	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
NYX	0:85b3fd62ea1a	1794	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
NYX	0:85b3fd62ea1a	1795	/**
NYX	0:85b3fd62ea1a	1796	* @}
NYX	0:85b3fd62ea1a	1797	*/
NYX	0:85b3fd62ea1a	1798
NYX	0:85b3fd62ea1a	1799	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
NYX	0:85b3fd62ea1a	1800	* @brief Force or release APB2 peripheral reset.
NYX	0:85b3fd62ea1a	1801	* @{
NYX	0:85b3fd62ea1a	1802	*/
NYX	0:85b3fd62ea1a	1803	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
NYX	0:85b3fd62ea1a	1804	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
NYX	0:85b3fd62ea1a	1805	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
NYX	0:85b3fd62ea1a	1806	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
NYX	0:85b3fd62ea1a	1807	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	1808	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	1809	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	1810
NYX	0:85b3fd62ea1a	1811	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	1812	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	1813	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	1814	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
NYX	0:85b3fd62ea1a	1815	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
NYX	0:85b3fd62ea1a	1816	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
NYX	0:85b3fd62ea1a	1817	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
NYX	0:85b3fd62ea1a	1818
NYX	0:85b3fd62ea1a	1819	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1820	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
NYX	0:85b3fd62ea1a	1821	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
NYX	0:85b3fd62ea1a	1822	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1823
NYX	0:85b3fd62ea1a	1824	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1825	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
NYX	0:85b3fd62ea1a	1826	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
NYX	0:85b3fd62ea1a	1827	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1828	/**
NYX	0:85b3fd62ea1a	1829	* @}
NYX	0:85b3fd62ea1a	1830	*/
NYX	0:85b3fd62ea1a	1831
NYX	0:85b3fd62ea1a	1832	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	1833	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	1834	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	1835	* power consumption.
NYX	0:85b3fd62ea1a	1836	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	1837	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	1838	* @{
NYX	0:85b3fd62ea1a	1839	*/
NYX	0:85b3fd62ea1a	1840	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	1841	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	1842	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
NYX	0:85b3fd62ea1a	1843	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
NYX	0:85b3fd62ea1a	1844	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
NYX	0:85b3fd62ea1a	1845	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
NYX	0:85b3fd62ea1a	1846	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
NYX	0:85b3fd62ea1a	1847	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
NYX	0:85b3fd62ea1a	1848	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
NYX	0:85b3fd62ea1a	1849	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
NYX	0:85b3fd62ea1a	1850	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
NYX	0:85b3fd62ea1a	1851	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
NYX	0:85b3fd62ea1a	1852	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
NYX	0:85b3fd62ea1a	1853	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
NYX	0:85b3fd62ea1a	1854	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
NYX	0:85b3fd62ea1a	1855	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
NYX	0:85b3fd62ea1a	1856	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	1857	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	1858	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	1859	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
NYX	0:85b3fd62ea1a	1860
NYX	0:85b3fd62ea1a	1861	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	1862	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	1863	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
NYX	0:85b3fd62ea1a	1864	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
NYX	0:85b3fd62ea1a	1865	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
NYX	0:85b3fd62ea1a	1866	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
NYX	0:85b3fd62ea1a	1867	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
NYX	0:85b3fd62ea1a	1868	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
NYX	0:85b3fd62ea1a	1869	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
NYX	0:85b3fd62ea1a	1870	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
NYX	0:85b3fd62ea1a	1871	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
NYX	0:85b3fd62ea1a	1872	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
NYX	0:85b3fd62ea1a	1873	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
NYX	0:85b3fd62ea1a	1874	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
NYX	0:85b3fd62ea1a	1875	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
NYX	0:85b3fd62ea1a	1876	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	1877	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	1878	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	1879	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
NYX	0:85b3fd62ea1a	1880	/**
NYX	0:85b3fd62ea1a	1881	* @}
NYX	0:85b3fd62ea1a	1882	*/
NYX	0:85b3fd62ea1a	1883
NYX	0:85b3fd62ea1a	1884	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	1885	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	1886	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	1887	* power consumption.
NYX	0:85b3fd62ea1a	1888	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	1889	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	1890	* @{
NYX	0:85b3fd62ea1a	1891	*/
NYX	0:85b3fd62ea1a	1892	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	1893	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	1894
NYX	0:85b3fd62ea1a	1895	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	1896	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	1897
NYX	0:85b3fd62ea1a	1898	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
NYX	0:85b3fd62ea1a	1899	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
NYX	0:85b3fd62ea1a	1900
NYX	0:85b3fd62ea1a	1901	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1902	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
NYX	0:85b3fd62ea1a	1903	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
NYX	0:85b3fd62ea1a	1904
NYX	0:85b3fd62ea1a	1905	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
NYX	0:85b3fd62ea1a	1906	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
NYX	0:85b3fd62ea1a	1907	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1908	/**
NYX	0:85b3fd62ea1a	1909	* @}
NYX	0:85b3fd62ea1a	1910	*/
NYX	0:85b3fd62ea1a	1911
NYX	0:85b3fd62ea1a	1912	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	1913	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	1914	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	1915	* power consumption.
NYX	0:85b3fd62ea1a	1916	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	1917	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	1918	* @{
NYX	0:85b3fd62ea1a	1919	*/
NYX	0:85b3fd62ea1a	1920	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
NYX	0:85b3fd62ea1a	1921	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
NYX	0:85b3fd62ea1a	1922
NYX	0:85b3fd62ea1a	1923	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1924	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
NYX	0:85b3fd62ea1a	1925	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
NYX	0:85b3fd62ea1a	1926	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1927	/**
NYX	0:85b3fd62ea1a	1928	* @}
NYX	0:85b3fd62ea1a	1929	*/
NYX	0:85b3fd62ea1a	1930
NYX	0:85b3fd62ea1a	1931	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	1932	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	1933	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	1934	* power consumption.
NYX	0:85b3fd62ea1a	1935	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	1936	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	1937	* @{
NYX	0:85b3fd62ea1a	1938	*/
NYX	0:85b3fd62ea1a	1939	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	1940	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
NYX	0:85b3fd62ea1a	1941	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
NYX	0:85b3fd62ea1a	1942	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
NYX	0:85b3fd62ea1a	1943	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
NYX	0:85b3fd62ea1a	1944	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
NYX	0:85b3fd62ea1a	1945	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
NYX	0:85b3fd62ea1a	1946	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
NYX	0:85b3fd62ea1a	1947	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
NYX	0:85b3fd62ea1a	1948	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
NYX	0:85b3fd62ea1a	1949	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	1950	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
NYX	0:85b3fd62ea1a	1951	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
NYX	0:85b3fd62ea1a	1952	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	1953	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	1954	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	1955	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	1956	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	1957
NYX	0:85b3fd62ea1a	1958	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	1959	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	1960	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	1961	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	1962	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	1963	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	1964	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
NYX	0:85b3fd62ea1a	1965	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
NYX	0:85b3fd62ea1a	1966	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
NYX	0:85b3fd62ea1a	1967	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
NYX	0:85b3fd62ea1a	1968	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
NYX	0:85b3fd62ea1a	1969	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
NYX	0:85b3fd62ea1a	1970	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
NYX	0:85b3fd62ea1a	1971	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
NYX	0:85b3fd62ea1a	1972	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
NYX	0:85b3fd62ea1a	1973	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	1974	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
NYX	0:85b3fd62ea1a	1975	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
NYX	0:85b3fd62ea1a	1976	/**
NYX	0:85b3fd62ea1a	1977	* @}
NYX	0:85b3fd62ea1a	1978	*/
NYX	0:85b3fd62ea1a	1979
NYX	0:85b3fd62ea1a	1980	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	1981	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	1982	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	1983	* power consumption.
NYX	0:85b3fd62ea1a	1984	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	1985	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	1986	* @{
NYX	0:85b3fd62ea1a	1987	*/
NYX	0:85b3fd62ea1a	1988	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
NYX	0:85b3fd62ea1a	1989	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
NYX	0:85b3fd62ea1a	1990	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
NYX	0:85b3fd62ea1a	1991	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
NYX	0:85b3fd62ea1a	1992	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
NYX	0:85b3fd62ea1a	1993	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
NYX	0:85b3fd62ea1a	1994	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	1995	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	1996	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	1997
NYX	0:85b3fd62ea1a	1998	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	1999	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	2000	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	2001	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
NYX	0:85b3fd62ea1a	2002	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
NYX	0:85b3fd62ea1a	2003	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
NYX	0:85b3fd62ea1a	2004	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
NYX	0:85b3fd62ea1a	2005	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
NYX	0:85b3fd62ea1a	2006	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
NYX	0:85b3fd62ea1a	2007
NYX	0:85b3fd62ea1a	2008	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	2009	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
NYX	0:85b3fd62ea1a	2010
NYX	0:85b3fd62ea1a	2011	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
NYX	0:85b3fd62ea1a	2012	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	2013
NYX	0:85b3fd62ea1a	2014	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	2015	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
NYX	0:85b3fd62ea1a	2016	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
NYX	0:85b3fd62ea1a	2017	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	2018	/**
NYX	0:85b3fd62ea1a	2019	* @}
NYX	0:85b3fd62ea1a	2020	*/
NYX	0:85b3fd62ea1a	2021	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	2022	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	2023
NYX	0:85b3fd62ea1a	2024	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
NYX	0:85b3fd62ea1a	2025	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2026	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	2027	* @brief Enables or disables the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	2028	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2029	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2030	* using it.
NYX	0:85b3fd62ea1a	2031	* @{
NYX	0:85b3fd62ea1a	2032	*/
NYX	0:85b3fd62ea1a	2033	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2034	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2035	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
NYX	0:85b3fd62ea1a	2036	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2037	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
NYX	0:85b3fd62ea1a	2038	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2039	} while(0U)
NYX	0:85b3fd62ea1a	2040	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2041	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2042	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	2043	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2044	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	2045	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2046	} while(0U)
NYX	0:85b3fd62ea1a	2047	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2048	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2049	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	2050	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2051	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	2052	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2053	} while(0U)
NYX	0:85b3fd62ea1a	2054	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2055	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2056	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	2057	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2058	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	2059	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2060	} while(0U)
NYX	0:85b3fd62ea1a	2061	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2062	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2063	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	2064	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2065	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	2066	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2067	} while(0U)
NYX	0:85b3fd62ea1a	2068	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2069	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2070	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
NYX	0:85b3fd62ea1a	2071	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2072	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
NYX	0:85b3fd62ea1a	2073	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2074	} while(0U)
NYX	0:85b3fd62ea1a	2075	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2076	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2077	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
NYX	0:85b3fd62ea1a	2078	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2079	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
NYX	0:85b3fd62ea1a	2080	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2081	} while(0U)
NYX	0:85b3fd62ea1a	2082	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2083	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2084	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
NYX	0:85b3fd62ea1a	2085	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2086	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
NYX	0:85b3fd62ea1a	2087	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2088	} while(0U)
NYX	0:85b3fd62ea1a	2089	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2090	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2091	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
NYX	0:85b3fd62ea1a	2092	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2093	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
NYX	0:85b3fd62ea1a	2094	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2095	} while(0U)
NYX	0:85b3fd62ea1a	2096	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2097	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2098	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
NYX	0:85b3fd62ea1a	2099	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2100	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
NYX	0:85b3fd62ea1a	2101	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2102	} while(0U)
NYX	0:85b3fd62ea1a	2103	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
NYX	0:85b3fd62ea1a	2104	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
NYX	0:85b3fd62ea1a	2105	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
NYX	0:85b3fd62ea1a	2106	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
NYX	0:85b3fd62ea1a	2107	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
NYX	0:85b3fd62ea1a	2108	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
NYX	0:85b3fd62ea1a	2109	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
NYX	0:85b3fd62ea1a	2110	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
NYX	0:85b3fd62ea1a	2111	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
NYX	0:85b3fd62ea1a	2112	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
NYX	0:85b3fd62ea1a	2113	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2114	/**
NYX	0:85b3fd62ea1a	2115	* @brief Enable ETHERNET clock.
NYX	0:85b3fd62ea1a	2116	*/
NYX	0:85b3fd62ea1a	2117	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2118	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2119	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
NYX	0:85b3fd62ea1a	2120	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2121	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
NYX	0:85b3fd62ea1a	2122	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2123	} while(0U)
NYX	0:85b3fd62ea1a	2124	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2125	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2126	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
NYX	0:85b3fd62ea1a	2127	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2128	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
NYX	0:85b3fd62ea1a	2129	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2130	} while(0U)
NYX	0:85b3fd62ea1a	2131	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2132	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2133	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
NYX	0:85b3fd62ea1a	2134	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2135	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
NYX	0:85b3fd62ea1a	2136	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2137	} while(0U)
NYX	0:85b3fd62ea1a	2138	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2139	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2140	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
NYX	0:85b3fd62ea1a	2141	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2142	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
NYX	0:85b3fd62ea1a	2143	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2144	} while(0U)
NYX	0:85b3fd62ea1a	2145	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2146	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
NYX	0:85b3fd62ea1a	2147	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
NYX	0:85b3fd62ea1a	2148	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
NYX	0:85b3fd62ea1a	2149	} while(0U)
NYX	0:85b3fd62ea1a	2150
NYX	0:85b3fd62ea1a	2151	/**
NYX	0:85b3fd62ea1a	2152	* @brief Disable ETHERNET clock.
NYX	0:85b3fd62ea1a	2153	*/
NYX	0:85b3fd62ea1a	2154	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
NYX	0:85b3fd62ea1a	2155	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
NYX	0:85b3fd62ea1a	2156	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
NYX	0:85b3fd62ea1a	2157	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
NYX	0:85b3fd62ea1a	2158	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
NYX	0:85b3fd62ea1a	2159	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
NYX	0:85b3fd62ea1a	2160	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
NYX	0:85b3fd62ea1a	2161	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
NYX	0:85b3fd62ea1a	2162	} while(0U)
NYX	0:85b3fd62ea1a	2163	#endif /* STM32F407xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2164	/**
NYX	0:85b3fd62ea1a	2165	* @}
NYX	0:85b3fd62ea1a	2166	*/
NYX	0:85b3fd62ea1a	2167
NYX	0:85b3fd62ea1a	2168	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	2169	* @brief Get the enable or disable status of the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	2170	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2171	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2172	* using it.
NYX	0:85b3fd62ea1a	2173	* @{
NYX	0:85b3fd62ea1a	2174	*/
NYX	0:85b3fd62ea1a	2175	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
NYX	0:85b3fd62ea1a	2176	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
NYX	0:85b3fd62ea1a	2177	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
NYX	0:85b3fd62ea1a	2178	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
NYX	0:85b3fd62ea1a	2179	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
NYX	0:85b3fd62ea1a	2180	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
NYX	0:85b3fd62ea1a	2181	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
NYX	0:85b3fd62ea1a	2182	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
NYX	0:85b3fd62ea1a	2183	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
NYX	0:85b3fd62ea1a	2184	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
NYX	0:85b3fd62ea1a	2185
NYX	0:85b3fd62ea1a	2186	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
NYX	0:85b3fd62ea1a	2187	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
NYX	0:85b3fd62ea1a	2188	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
NYX	0:85b3fd62ea1a	2189	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
NYX	0:85b3fd62ea1a	2190	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
NYX	0:85b3fd62ea1a	2191	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
NYX	0:85b3fd62ea1a	2192	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
NYX	0:85b3fd62ea1a	2193	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
NYX	0:85b3fd62ea1a	2194	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
NYX	0:85b3fd62ea1a	2195	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
NYX	0:85b3fd62ea1a	2196	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2197	/**
NYX	0:85b3fd62ea1a	2198	* @brief Enable ETHERNET clock.
NYX	0:85b3fd62ea1a	2199	*/
NYX	0:85b3fd62ea1a	2200	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
NYX	0:85b3fd62ea1a	2201	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
NYX	0:85b3fd62ea1a	2202	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
NYX	0:85b3fd62ea1a	2203	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
NYX	0:85b3fd62ea1a	2204	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
NYX	0:85b3fd62ea1a	2205	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
NYX	0:85b3fd62ea1a	2206	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
NYX	0:85b3fd62ea1a	2207	/**
NYX	0:85b3fd62ea1a	2208	* @brief Disable ETHERNET clock.
NYX	0:85b3fd62ea1a	2209	*/
NYX	0:85b3fd62ea1a	2210	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
NYX	0:85b3fd62ea1a	2211	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
NYX	0:85b3fd62ea1a	2212	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
NYX	0:85b3fd62ea1a	2213	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
NYX	0:85b3fd62ea1a	2214	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
NYX	0:85b3fd62ea1a	2215	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
NYX	0:85b3fd62ea1a	2216	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
NYX	0:85b3fd62ea1a	2217	#endif /* STM32F407xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2218	/**
NYX	0:85b3fd62ea1a	2219	* @}
NYX	0:85b3fd62ea1a	2220	*/
NYX	0:85b3fd62ea1a	2221
NYX	0:85b3fd62ea1a	2222	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	2223	* @brief Enable or disable the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	2224	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2225	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2226	* using it.
NYX	0:85b3fd62ea1a	2227	* @{
NYX	0:85b3fd62ea1a	2228	*/
NYX	0:85b3fd62ea1a	2229	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
NYX	0:85b3fd62ea1a	2230	__HAL_RCC_SYSCFG_CLK_ENABLE();\
NYX	0:85b3fd62ea1a	2231	}while(0U)
NYX	0:85b3fd62ea1a	2232
NYX	0:85b3fd62ea1a	2233	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
NYX	0:85b3fd62ea1a	2234
NYX	0:85b3fd62ea1a	2235	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2236	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2237	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
NYX	0:85b3fd62ea1a	2238	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2239	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
NYX	0:85b3fd62ea1a	2240	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2241	} while(0U)
NYX	0:85b3fd62ea1a	2242	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
NYX	0:85b3fd62ea1a	2243
NYX	0:85b3fd62ea1a	2244	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2245	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2246	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2247	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
NYX	0:85b3fd62ea1a	2248	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2249	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
NYX	0:85b3fd62ea1a	2250	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2251	} while(0U)
NYX	0:85b3fd62ea1a	2252	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
NYX	0:85b3fd62ea1a	2253	#endif /* STM32F407xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2254
NYX	0:85b3fd62ea1a	2255	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2256	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2257	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2258	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
NYX	0:85b3fd62ea1a	2259	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2260	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
NYX	0:85b3fd62ea1a	2261	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2262	} while(0U)
NYX	0:85b3fd62ea1a	2263	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2264	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2265	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
NYX	0:85b3fd62ea1a	2266	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2267	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
NYX	0:85b3fd62ea1a	2268	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2269	} while(0U)
NYX	0:85b3fd62ea1a	2270	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
NYX	0:85b3fd62ea1a	2271	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
NYX	0:85b3fd62ea1a	2272	#endif /* STM32F415xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2273	/**
NYX	0:85b3fd62ea1a	2274	* @}
NYX	0:85b3fd62ea1a	2275	*/
NYX	0:85b3fd62ea1a	2276
NYX	0:85b3fd62ea1a	2277
NYX	0:85b3fd62ea1a	2278	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	2279	* @brief Get the enable or disable status of the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	2280	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2281	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2282	* using it.
NYX	0:85b3fd62ea1a	2283	* @{
NYX	0:85b3fd62ea1a	2284	*/
NYX	0:85b3fd62ea1a	2285	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
NYX	0:85b3fd62ea1a	2286	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
NYX	0:85b3fd62ea1a	2287
NYX	0:85b3fd62ea1a	2288	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
NYX	0:85b3fd62ea1a	2289	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
NYX	0:85b3fd62ea1a	2290
NYX	0:85b3fd62ea1a	2291	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2292	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
NYX	0:85b3fd62ea1a	2293	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
NYX	0:85b3fd62ea1a	2294	#endif /* STM32F407xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2295
NYX	0:85b3fd62ea1a	2296	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2297	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
NYX	0:85b3fd62ea1a	2298	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
NYX	0:85b3fd62ea1a	2299
NYX	0:85b3fd62ea1a	2300	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
NYX	0:85b3fd62ea1a	2301	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
NYX	0:85b3fd62ea1a	2302	#endif /* STM32F415xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2303	/**
NYX	0:85b3fd62ea1a	2304	* @}
NYX	0:85b3fd62ea1a	2305	*/
NYX	0:85b3fd62ea1a	2306
NYX	0:85b3fd62ea1a	2307	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	2308	* @brief Enables or disables the AHB3 peripheral clock.
NYX	0:85b3fd62ea1a	2309	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2310	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2311	* using it.
NYX	0:85b3fd62ea1a	2312	* @{
NYX	0:85b3fd62ea1a	2313	*/
NYX	0:85b3fd62ea1a	2314	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2315	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2316	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
NYX	0:85b3fd62ea1a	2317	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2318	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
NYX	0:85b3fd62ea1a	2319	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2320	} while(0U)
NYX	0:85b3fd62ea1a	2321	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
NYX	0:85b3fd62ea1a	2322	/**
NYX	0:85b3fd62ea1a	2323	* @}
NYX	0:85b3fd62ea1a	2324	*/
NYX	0:85b3fd62ea1a	2325
NYX	0:85b3fd62ea1a	2326	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	2327	* @brief Get the enable or disable status of the AHB3 peripheral clock.
NYX	0:85b3fd62ea1a	2328	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2329	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2330	* using it.
NYX	0:85b3fd62ea1a	2331	* @{
NYX	0:85b3fd62ea1a	2332	*/
NYX	0:85b3fd62ea1a	2333	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
NYX	0:85b3fd62ea1a	2334	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
NYX	0:85b3fd62ea1a	2335	/**
NYX	0:85b3fd62ea1a	2336	* @}
NYX	0:85b3fd62ea1a	2337	*/
NYX	0:85b3fd62ea1a	2338
NYX	0:85b3fd62ea1a	2339	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	2340	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
NYX	0:85b3fd62ea1a	2341	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2342	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2343	* using it.
NYX	0:85b3fd62ea1a	2344	* @{
NYX	0:85b3fd62ea1a	2345	*/
NYX	0:85b3fd62ea1a	2346	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2347	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	2349	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	2351	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2352	} while(0U)
NYX	0:85b3fd62ea1a	2353	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2354	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
NYX	0:85b3fd62ea1a	2356	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
NYX	0:85b3fd62ea1a	2358	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2359	} while(0U)
NYX	0:85b3fd62ea1a	2360	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2361	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
NYX	0:85b3fd62ea1a	2363	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
NYX	0:85b3fd62ea1a	2365	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2366	} while(0U)
NYX	0:85b3fd62ea1a	2367	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2368	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
NYX	0:85b3fd62ea1a	2370	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
NYX	0:85b3fd62ea1a	2372	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2373	} while(0U)
NYX	0:85b3fd62ea1a	2374	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2375	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2376	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	2377	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2378	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	2379	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2380	} while(0U)
NYX	0:85b3fd62ea1a	2381	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2382	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2383	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
NYX	0:85b3fd62ea1a	2384	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2385	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
NYX	0:85b3fd62ea1a	2386	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2387	} while(0U)
NYX	0:85b3fd62ea1a	2388	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2389	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2390	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
NYX	0:85b3fd62ea1a	2391	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2392	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
NYX	0:85b3fd62ea1a	2393	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2394	} while(0U)
NYX	0:85b3fd62ea1a	2395	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2396	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2397	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
NYX	0:85b3fd62ea1a	2398	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2399	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
NYX	0:85b3fd62ea1a	2400	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2401	} while(0U)
NYX	0:85b3fd62ea1a	2402	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2403	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2404	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
NYX	0:85b3fd62ea1a	2405	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2406	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
NYX	0:85b3fd62ea1a	2407	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2408	} while(0U)
NYX	0:85b3fd62ea1a	2409	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2410	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2411	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
NYX	0:85b3fd62ea1a	2412	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2413	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
NYX	0:85b3fd62ea1a	2414	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2415	} while(0U)
NYX	0:85b3fd62ea1a	2416	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2417	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2418	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	2419	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2420	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	2421	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2422	} while(0U)
NYX	0:85b3fd62ea1a	2423	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2424	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2425	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	2426	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2427	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	2428	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2429	} while(0U)
NYX	0:85b3fd62ea1a	2430	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2431	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2432	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	2433	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2434	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	2435	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2436	} while(0U)
NYX	0:85b3fd62ea1a	2437	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2438	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2439	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	2440	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2441	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	2442	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2443	} while(0U)
NYX	0:85b3fd62ea1a	2444	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2445	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2446	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	2447	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2448	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	2449	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2450	} while(0U)
NYX	0:85b3fd62ea1a	2451	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2452	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2453	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	2454	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2455	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	2456	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2457	} while(0U)
NYX	0:85b3fd62ea1a	2458	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
NYX	0:85b3fd62ea1a	2459	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
NYX	0:85b3fd62ea1a	2460	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
NYX	0:85b3fd62ea1a	2461	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
NYX	0:85b3fd62ea1a	2462	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
NYX	0:85b3fd62ea1a	2463	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
NYX	0:85b3fd62ea1a	2464	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
NYX	0:85b3fd62ea1a	2465	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
NYX	0:85b3fd62ea1a	2466	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
NYX	0:85b3fd62ea1a	2467	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
NYX	0:85b3fd62ea1a	2468	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
NYX	0:85b3fd62ea1a	2469	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
NYX	0:85b3fd62ea1a	2470	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
NYX	0:85b3fd62ea1a	2471	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
NYX	0:85b3fd62ea1a	2472	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
NYX	0:85b3fd62ea1a	2473	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
NYX	0:85b3fd62ea1a	2474	/**
NYX	0:85b3fd62ea1a	2475	* @}
NYX	0:85b3fd62ea1a	2476	*/
NYX	0:85b3fd62ea1a	2477
NYX	0:85b3fd62ea1a	2478	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	2479	* @brief Get the enable or disable status of the APB1 peripheral clock.
NYX	0:85b3fd62ea1a	2480	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2481	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2482	* using it.
NYX	0:85b3fd62ea1a	2483	* @{
NYX	0:85b3fd62ea1a	2484	*/
NYX	0:85b3fd62ea1a	2485	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
NYX	0:85b3fd62ea1a	2486	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
NYX	0:85b3fd62ea1a	2487	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
NYX	0:85b3fd62ea1a	2488	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
NYX	0:85b3fd62ea1a	2489	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
NYX	0:85b3fd62ea1a	2490	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
NYX	0:85b3fd62ea1a	2491	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
NYX	0:85b3fd62ea1a	2492	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
NYX	0:85b3fd62ea1a	2493	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
NYX	0:85b3fd62ea1a	2494	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
NYX	0:85b3fd62ea1a	2495	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
NYX	0:85b3fd62ea1a	2496	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
NYX	0:85b3fd62ea1a	2497	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
NYX	0:85b3fd62ea1a	2498	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
NYX	0:85b3fd62ea1a	2499	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
NYX	0:85b3fd62ea1a	2500	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
NYX	0:85b3fd62ea1a	2501
NYX	0:85b3fd62ea1a	2502	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
NYX	0:85b3fd62ea1a	2503	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
NYX	0:85b3fd62ea1a	2504	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
NYX	0:85b3fd62ea1a	2505	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
NYX	0:85b3fd62ea1a	2506	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
NYX	0:85b3fd62ea1a	2507	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
NYX	0:85b3fd62ea1a	2508	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
NYX	0:85b3fd62ea1a	2509	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
NYX	0:85b3fd62ea1a	2510	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
NYX	0:85b3fd62ea1a	2511	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
NYX	0:85b3fd62ea1a	2512	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
NYX	0:85b3fd62ea1a	2513	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
NYX	0:85b3fd62ea1a	2514	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
NYX	0:85b3fd62ea1a	2515	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
NYX	0:85b3fd62ea1a	2516	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
NYX	0:85b3fd62ea1a	2517	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
NYX	0:85b3fd62ea1a	2518	/**
NYX	0:85b3fd62ea1a	2519	* @}
NYX	0:85b3fd62ea1a	2520	*/
NYX	0:85b3fd62ea1a	2521
NYX	0:85b3fd62ea1a	2522	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	2523	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
NYX	0:85b3fd62ea1a	2524	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2525	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2526	* using it.
NYX	0:85b3fd62ea1a	2527	* @{
NYX	0:85b3fd62ea1a	2528	*/
NYX	0:85b3fd62ea1a	2529	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2530	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2531	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
NYX	0:85b3fd62ea1a	2532	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2533	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
NYX	0:85b3fd62ea1a	2534	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2535	} while(0U)
NYX	0:85b3fd62ea1a	2536	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2537	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2538	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
NYX	0:85b3fd62ea1a	2539	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2540	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
NYX	0:85b3fd62ea1a	2541	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2542	} while(0U)
NYX	0:85b3fd62ea1a	2543	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2544	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2545	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
NYX	0:85b3fd62ea1a	2546	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2547	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
NYX	0:85b3fd62ea1a	2548	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2549	} while(0U)
NYX	0:85b3fd62ea1a	2550	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2551	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2552	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	2553	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2554	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	2555	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2556	} while(0U)
NYX	0:85b3fd62ea1a	2557	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2558	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2559	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	2560	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2561	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	2562	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2563	} while(0U)
NYX	0:85b3fd62ea1a	2564	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2565	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2566	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	2567	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2568	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	2569	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2570	} while(0U)
NYX	0:85b3fd62ea1a	2571
NYX	0:85b3fd62ea1a	2572	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
NYX	0:85b3fd62ea1a	2573	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
NYX	0:85b3fd62ea1a	2574	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
NYX	0:85b3fd62ea1a	2575	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
NYX	0:85b3fd62ea1a	2576	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
NYX	0:85b3fd62ea1a	2577	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
NYX	0:85b3fd62ea1a	2578	/**
NYX	0:85b3fd62ea1a	2579	* @}
NYX	0:85b3fd62ea1a	2580	*/
NYX	0:85b3fd62ea1a	2581
NYX	0:85b3fd62ea1a	2582	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	2583	* @brief Get the enable or disable status of the APB2 peripheral clock.
NYX	0:85b3fd62ea1a	2584	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2585	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2586	* using it.
NYX	0:85b3fd62ea1a	2587	* @{
NYX	0:85b3fd62ea1a	2588	*/
NYX	0:85b3fd62ea1a	2589	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
NYX	0:85b3fd62ea1a	2590	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
NYX	0:85b3fd62ea1a	2591	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
NYX	0:85b3fd62ea1a	2592	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
NYX	0:85b3fd62ea1a	2593	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
NYX	0:85b3fd62ea1a	2594	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
NYX	0:85b3fd62ea1a	2595
NYX	0:85b3fd62ea1a	2596	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
NYX	0:85b3fd62ea1a	2597	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
NYX	0:85b3fd62ea1a	2598	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
NYX	0:85b3fd62ea1a	2599	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
NYX	0:85b3fd62ea1a	2600	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
NYX	0:85b3fd62ea1a	2601	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
NYX	0:85b3fd62ea1a	2602	/**
NYX	0:85b3fd62ea1a	2603	* @}
NYX	0:85b3fd62ea1a	2604	*/
NYX	0:85b3fd62ea1a	2605
NYX	0:85b3fd62ea1a	2606	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
NYX	0:85b3fd62ea1a	2607	* @brief Force or release AHB1 peripheral reset.
NYX	0:85b3fd62ea1a	2608	* @{
NYX	0:85b3fd62ea1a	2609	*/
NYX	0:85b3fd62ea1a	2610	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	2611	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	2612	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
NYX	0:85b3fd62ea1a	2613	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
NYX	0:85b3fd62ea1a	2614	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
NYX	0:85b3fd62ea1a	2615	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
NYX	0:85b3fd62ea1a	2616	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
NYX	0:85b3fd62ea1a	2617	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	2618
NYX	0:85b3fd62ea1a	2619	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	2620	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	2621	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
NYX	0:85b3fd62ea1a	2622	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
NYX	0:85b3fd62ea1a	2623	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
NYX	0:85b3fd62ea1a	2624	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
NYX	0:85b3fd62ea1a	2625	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
NYX	0:85b3fd62ea1a	2626	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	2627	/**
NYX	0:85b3fd62ea1a	2628	* @}
NYX	0:85b3fd62ea1a	2629	*/
NYX	0:85b3fd62ea1a	2630
NYX	0:85b3fd62ea1a	2631	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
NYX	0:85b3fd62ea1a	2632	* @brief Force or release AHB2 peripheral reset.
NYX	0:85b3fd62ea1a	2633	* @{
NYX	0:85b3fd62ea1a	2634	*/
NYX	0:85b3fd62ea1a	2635	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	2636	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
NYX	0:85b3fd62ea1a	2637
NYX	0:85b3fd62ea1a	2638	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2639	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
NYX	0:85b3fd62ea1a	2640	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
NYX	0:85b3fd62ea1a	2641	#endif /* STM32F407xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2642
NYX	0:85b3fd62ea1a	2643	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2644	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
NYX	0:85b3fd62ea1a	2645	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
NYX	0:85b3fd62ea1a	2646
NYX	0:85b3fd62ea1a	2647	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
NYX	0:85b3fd62ea1a	2648	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
NYX	0:85b3fd62ea1a	2649	#endif /* STM32F415xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2650
NYX	0:85b3fd62ea1a	2651	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	2652	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	2653
NYX	0:85b3fd62ea1a	2654	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
NYX	0:85b3fd62ea1a	2655	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
NYX	0:85b3fd62ea1a	2656	/**
NYX	0:85b3fd62ea1a	2657	* @}
NYX	0:85b3fd62ea1a	2658	*/
NYX	0:85b3fd62ea1a	2659
NYX	0:85b3fd62ea1a	2660	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
NYX	0:85b3fd62ea1a	2661	* @brief Force or release AHB3 peripheral reset.
NYX	0:85b3fd62ea1a	2662	* @{
NYX	0:85b3fd62ea1a	2663	*/
NYX	0:85b3fd62ea1a	2664	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	2665	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
NYX	0:85b3fd62ea1a	2666
NYX	0:85b3fd62ea1a	2667	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
NYX	0:85b3fd62ea1a	2668	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
NYX	0:85b3fd62ea1a	2669	/**
NYX	0:85b3fd62ea1a	2670	* @}
NYX	0:85b3fd62ea1a	2671	*/
NYX	0:85b3fd62ea1a	2672
NYX	0:85b3fd62ea1a	2673	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
NYX	0:85b3fd62ea1a	2674	* @brief Force or release APB1 peripheral reset.
NYX	0:85b3fd62ea1a	2675	* @{
NYX	0:85b3fd62ea1a	2676	*/
NYX	0:85b3fd62ea1a	2677	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	2678	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
NYX	0:85b3fd62ea1a	2679	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
NYX	0:85b3fd62ea1a	2680	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
NYX	0:85b3fd62ea1a	2681	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
NYX	0:85b3fd62ea1a	2682	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
NYX	0:85b3fd62ea1a	2683	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
NYX	0:85b3fd62ea1a	2684	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
NYX	0:85b3fd62ea1a	2685	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
NYX	0:85b3fd62ea1a	2686	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
NYX	0:85b3fd62ea1a	2687	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	2688	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	2689	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	2690	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	2691	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	2692	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	2693
NYX	0:85b3fd62ea1a	2694	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	2695	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	2696	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	2697	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	2698	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	2699	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	2700	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
NYX	0:85b3fd62ea1a	2701	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
NYX	0:85b3fd62ea1a	2702	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
NYX	0:85b3fd62ea1a	2703	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
NYX	0:85b3fd62ea1a	2704	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
NYX	0:85b3fd62ea1a	2705	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
NYX	0:85b3fd62ea1a	2706	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
NYX	0:85b3fd62ea1a	2707	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
NYX	0:85b3fd62ea1a	2708	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
NYX	0:85b3fd62ea1a	2709	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	2710	/**
NYX	0:85b3fd62ea1a	2711	* @}
NYX	0:85b3fd62ea1a	2712	*/
NYX	0:85b3fd62ea1a	2713
NYX	0:85b3fd62ea1a	2714	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
NYX	0:85b3fd62ea1a	2715	* @brief Force or release APB2 peripheral reset.
NYX	0:85b3fd62ea1a	2716	* @{
NYX	0:85b3fd62ea1a	2717	*/
NYX	0:85b3fd62ea1a	2718	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
NYX	0:85b3fd62ea1a	2719	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	2720	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	2721	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	2722
NYX	0:85b3fd62ea1a	2723	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	2724	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	2725	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	2726	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
NYX	0:85b3fd62ea1a	2727	/**
NYX	0:85b3fd62ea1a	2728	* @}
NYX	0:85b3fd62ea1a	2729	*/
NYX	0:85b3fd62ea1a	2730
NYX	0:85b3fd62ea1a	2731	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	2732	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	2733	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	2734	* power consumption.
NYX	0:85b3fd62ea1a	2735	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	2736	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	2737	* @{
NYX	0:85b3fd62ea1a	2738	*/
NYX	0:85b3fd62ea1a	2739	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	2740	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	2741	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
NYX	0:85b3fd62ea1a	2742	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
NYX	0:85b3fd62ea1a	2743	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
NYX	0:85b3fd62ea1a	2744	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
NYX	0:85b3fd62ea1a	2745	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
NYX	0:85b3fd62ea1a	2746	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
NYX	0:85b3fd62ea1a	2747	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
NYX	0:85b3fd62ea1a	2748	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
NYX	0:85b3fd62ea1a	2749	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
NYX	0:85b3fd62ea1a	2750	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
NYX	0:85b3fd62ea1a	2751	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	2752	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	2753	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	2754	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
NYX	0:85b3fd62ea1a	2755
NYX	0:85b3fd62ea1a	2756	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	2757	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	2758	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
NYX	0:85b3fd62ea1a	2759	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
NYX	0:85b3fd62ea1a	2760	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
NYX	0:85b3fd62ea1a	2761	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
NYX	0:85b3fd62ea1a	2762	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
NYX	0:85b3fd62ea1a	2763	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
NYX	0:85b3fd62ea1a	2764	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
NYX	0:85b3fd62ea1a	2765	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
NYX	0:85b3fd62ea1a	2766	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
NYX	0:85b3fd62ea1a	2767	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
NYX	0:85b3fd62ea1a	2768	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	2769	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	2770	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	2771	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
NYX	0:85b3fd62ea1a	2772	/**
NYX	0:85b3fd62ea1a	2773	* @}
NYX	0:85b3fd62ea1a	2774	*/
NYX	0:85b3fd62ea1a	2775
NYX	0:85b3fd62ea1a	2776	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	2777	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	2778	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	2779	* power consumption.
NYX	0:85b3fd62ea1a	2780	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	2781	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	2782	* @{
NYX	0:85b3fd62ea1a	2783	*/
NYX	0:85b3fd62ea1a	2784	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	2785	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	2786
NYX	0:85b3fd62ea1a	2787	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	2788	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	2789
NYX	0:85b3fd62ea1a	2790	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2791	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
NYX	0:85b3fd62ea1a	2792	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
NYX	0:85b3fd62ea1a	2793	#endif /* STM32F407xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2794
NYX	0:85b3fd62ea1a	2795	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2796	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
NYX	0:85b3fd62ea1a	2797	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
NYX	0:85b3fd62ea1a	2798
NYX	0:85b3fd62ea1a	2799	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
NYX	0:85b3fd62ea1a	2800	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
NYX	0:85b3fd62ea1a	2801	#endif /* STM32F415xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2802	/**
NYX	0:85b3fd62ea1a	2803	* @}
NYX	0:85b3fd62ea1a	2804	*/
NYX	0:85b3fd62ea1a	2805
NYX	0:85b3fd62ea1a	2806	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	2807	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	2808	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	2809	* power consumption.
NYX	0:85b3fd62ea1a	2810	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	2811	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	2812	* @{
NYX	0:85b3fd62ea1a	2813	*/
NYX	0:85b3fd62ea1a	2814	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
NYX	0:85b3fd62ea1a	2815	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
NYX	0:85b3fd62ea1a	2816	/**
NYX	0:85b3fd62ea1a	2817	* @}
NYX	0:85b3fd62ea1a	2818	*/
NYX	0:85b3fd62ea1a	2819
NYX	0:85b3fd62ea1a	2820	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	2821	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	2822	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	2823	* power consumption.
NYX	0:85b3fd62ea1a	2824	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	2825	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	2826	* @{
NYX	0:85b3fd62ea1a	2827	*/
NYX	0:85b3fd62ea1a	2828	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	2829	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
NYX	0:85b3fd62ea1a	2830	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
NYX	0:85b3fd62ea1a	2831	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
NYX	0:85b3fd62ea1a	2832	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
NYX	0:85b3fd62ea1a	2833	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
NYX	0:85b3fd62ea1a	2834	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
NYX	0:85b3fd62ea1a	2835	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
NYX	0:85b3fd62ea1a	2836	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
NYX	0:85b3fd62ea1a	2837	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
NYX	0:85b3fd62ea1a	2838	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	2839	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	2840	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	2841	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	2842	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	2843	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	2844
NYX	0:85b3fd62ea1a	2845	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	2846	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	2847	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	2848	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	2849	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	2850	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	2851	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
NYX	0:85b3fd62ea1a	2852	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
NYX	0:85b3fd62ea1a	2853	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
NYX	0:85b3fd62ea1a	2854	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
NYX	0:85b3fd62ea1a	2855	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
NYX	0:85b3fd62ea1a	2856	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
NYX	0:85b3fd62ea1a	2857	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
NYX	0:85b3fd62ea1a	2858	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
NYX	0:85b3fd62ea1a	2859	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
NYX	0:85b3fd62ea1a	2860	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	2861	/**
NYX	0:85b3fd62ea1a	2862	* @}
NYX	0:85b3fd62ea1a	2863	*/
NYX	0:85b3fd62ea1a	2864
NYX	0:85b3fd62ea1a	2865	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	2866	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	2867	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	2868	* power consumption.
NYX	0:85b3fd62ea1a	2869	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	2870	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	2871	* @{
NYX	0:85b3fd62ea1a	2872	*/
NYX	0:85b3fd62ea1a	2873	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
NYX	0:85b3fd62ea1a	2874	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
NYX	0:85b3fd62ea1a	2875	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
NYX	0:85b3fd62ea1a	2876	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	2877	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	2878	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	2879
NYX	0:85b3fd62ea1a	2880	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	2881	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	2882	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	2883	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
NYX	0:85b3fd62ea1a	2884	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
NYX	0:85b3fd62ea1a	2885	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
NYX	0:85b3fd62ea1a	2886	/**
NYX	0:85b3fd62ea1a	2887	* @}
NYX	0:85b3fd62ea1a	2888	*/
NYX	0:85b3fd62ea1a	2889	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	2890	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	2891
NYX	0:85b3fd62ea1a	2892	/------------------------- STM32F401xE/STM32F401xC --------------------------/
NYX	0:85b3fd62ea1a	2893	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
NYX	0:85b3fd62ea1a	2894	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	2895	* @brief Enable or disable the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	2896	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2897	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2898	* using it.
NYX	0:85b3fd62ea1a	2899	* @{
NYX	0:85b3fd62ea1a	2900	*/
NYX	0:85b3fd62ea1a	2901	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2902	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2903	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	2904	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2905	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	2906	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2907	} while(0U)
NYX	0:85b3fd62ea1a	2908	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2909	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2910	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	2911	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2912	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	2913	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2914	} while(0U)
NYX	0:85b3fd62ea1a	2915	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2916	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2917	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	2918	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2919	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	2920	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2921	} while(0U)
NYX	0:85b3fd62ea1a	2922	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2923	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2924	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	2925	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2926	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	2927	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	2928	} while(0U)
NYX	0:85b3fd62ea1a	2929
NYX	0:85b3fd62ea1a	2930	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
NYX	0:85b3fd62ea1a	2931	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
NYX	0:85b3fd62ea1a	2932	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
NYX	0:85b3fd62ea1a	2933	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
NYX	0:85b3fd62ea1a	2934	/**
NYX	0:85b3fd62ea1a	2935	* @}
NYX	0:85b3fd62ea1a	2936	*/
NYX	0:85b3fd62ea1a	2937
NYX	0:85b3fd62ea1a	2938	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	2939	* @brief Get the enable or disable status of the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	2940	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2941	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2942	* using it.
NYX	0:85b3fd62ea1a	2943	* @{
NYX	0:85b3fd62ea1a	2944	*/
NYX	0:85b3fd62ea1a	2945	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
NYX	0:85b3fd62ea1a	2946	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
NYX	0:85b3fd62ea1a	2947	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
NYX	0:85b3fd62ea1a	2948	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
NYX	0:85b3fd62ea1a	2949
NYX	0:85b3fd62ea1a	2950	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
NYX	0:85b3fd62ea1a	2951	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
NYX	0:85b3fd62ea1a	2952	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
NYX	0:85b3fd62ea1a	2953	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
NYX	0:85b3fd62ea1a	2954	/**
NYX	0:85b3fd62ea1a	2955	* @}
NYX	0:85b3fd62ea1a	2956	*/
NYX	0:85b3fd62ea1a	2957
NYX	0:85b3fd62ea1a	2958	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	2959	* @brief Enable or disable the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	2960	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2961	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2962	* using it.
NYX	0:85b3fd62ea1a	2963	* @{
NYX	0:85b3fd62ea1a	2964	*/
NYX	0:85b3fd62ea1a	2965	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
NYX	0:85b3fd62ea1a	2966	__HAL_RCC_SYSCFG_CLK_ENABLE();\
NYX	0:85b3fd62ea1a	2967	}while(0U)
NYX	0:85b3fd62ea1a	2968
NYX	0:85b3fd62ea1a	2969	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
NYX	0:85b3fd62ea1a	2970	/**
NYX	0:85b3fd62ea1a	2971	* @}
NYX	0:85b3fd62ea1a	2972	*/
NYX	0:85b3fd62ea1a	2973
NYX	0:85b3fd62ea1a	2974	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	2975	* @brief Get the enable or disable status of the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	2976	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2977	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2978	* using it.
NYX	0:85b3fd62ea1a	2979	* @{
NYX	0:85b3fd62ea1a	2980	*/
NYX	0:85b3fd62ea1a	2981	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
NYX	0:85b3fd62ea1a	2982	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
NYX	0:85b3fd62ea1a	2983	/**
NYX	0:85b3fd62ea1a	2984	* @}
NYX	0:85b3fd62ea1a	2985	*/
NYX	0:85b3fd62ea1a	2986
NYX	0:85b3fd62ea1a	2987	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	2988	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
NYX	0:85b3fd62ea1a	2989	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	2990	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	2991	* using it.
NYX	0:85b3fd62ea1a	2992	* @{
NYX	0:85b3fd62ea1a	2993	*/
NYX	0:85b3fd62ea1a	2994	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	2995	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	2996	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	2997	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	2998	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	2999	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3000	} while(0U)
NYX	0:85b3fd62ea1a	3001	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3002	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3003	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	3004	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3005	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	3006	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3007	} while(0U)
NYX	0:85b3fd62ea1a	3008	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3009	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3010	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	3011	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3012	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	3013	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3014	} while(0U)
NYX	0:85b3fd62ea1a	3015	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3016	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3017	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	3018	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3019	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	3020	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3021	} while(0U)
NYX	0:85b3fd62ea1a	3022	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3023	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3024	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	3025	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3026	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	3027	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3028	} while(0U)
NYX	0:85b3fd62ea1a	3029	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
NYX	0:85b3fd62ea1a	3030	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
NYX	0:85b3fd62ea1a	3031	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
NYX	0:85b3fd62ea1a	3032	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
NYX	0:85b3fd62ea1a	3033	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
NYX	0:85b3fd62ea1a	3034	/**
NYX	0:85b3fd62ea1a	3035	* @}
NYX	0:85b3fd62ea1a	3036	*/
NYX	0:85b3fd62ea1a	3037
NYX	0:85b3fd62ea1a	3038	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	3039	* @brief Get the enable or disable status of the APB1 peripheral clock.
NYX	0:85b3fd62ea1a	3040	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3041	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3042	* using it.
NYX	0:85b3fd62ea1a	3043	* @{
NYX	0:85b3fd62ea1a	3044	*/
NYX	0:85b3fd62ea1a	3045	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
NYX	0:85b3fd62ea1a	3046	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
NYX	0:85b3fd62ea1a	3047	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
NYX	0:85b3fd62ea1a	3048	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
NYX	0:85b3fd62ea1a	3049	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
NYX	0:85b3fd62ea1a	3050
NYX	0:85b3fd62ea1a	3051	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
NYX	0:85b3fd62ea1a	3052	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
NYX	0:85b3fd62ea1a	3053	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
NYX	0:85b3fd62ea1a	3054	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
NYX	0:85b3fd62ea1a	3055	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
NYX	0:85b3fd62ea1a	3056	/**
NYX	0:85b3fd62ea1a	3057	* @}
NYX	0:85b3fd62ea1a	3058	*/
NYX	0:85b3fd62ea1a	3059
NYX	0:85b3fd62ea1a	3060	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	3061	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
NYX	0:85b3fd62ea1a	3062	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3063	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3064	* using it.
NYX	0:85b3fd62ea1a	3065	* @{
NYX	0:85b3fd62ea1a	3066	*/
NYX	0:85b3fd62ea1a	3067	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3068	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3069	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	3070	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3071	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	3072	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3073	} while(0U)
NYX	0:85b3fd62ea1a	3074	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3075	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3076	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	3077	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3078	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	3079	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3080	} while(0U)
NYX	0:85b3fd62ea1a	3081	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3082	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3083	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	3084	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3085	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	3086	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3087	} while(0U)
NYX	0:85b3fd62ea1a	3088
NYX	0:85b3fd62ea1a	3089	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
NYX	0:85b3fd62ea1a	3090	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
NYX	0:85b3fd62ea1a	3091	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
NYX	0:85b3fd62ea1a	3092	/**
NYX	0:85b3fd62ea1a	3093	* @}
NYX	0:85b3fd62ea1a	3094	*/
NYX	0:85b3fd62ea1a	3095
NYX	0:85b3fd62ea1a	3096	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	3097	* @brief Get the enable or disable status of the APB2 peripheral clock.
NYX	0:85b3fd62ea1a	3098	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3099	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3100	* using it.
NYX	0:85b3fd62ea1a	3101	* @{
NYX	0:85b3fd62ea1a	3102	*/
NYX	0:85b3fd62ea1a	3103	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
NYX	0:85b3fd62ea1a	3104	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
NYX	0:85b3fd62ea1a	3105	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
NYX	0:85b3fd62ea1a	3106
NYX	0:85b3fd62ea1a	3107	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
NYX	0:85b3fd62ea1a	3108	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
NYX	0:85b3fd62ea1a	3109	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
NYX	0:85b3fd62ea1a	3110	/**
NYX	0:85b3fd62ea1a	3111	* @}
NYX	0:85b3fd62ea1a	3112	*/
NYX	0:85b3fd62ea1a	3113	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
NYX	0:85b3fd62ea1a	3114	* @brief Force or release AHB1 peripheral reset.
NYX	0:85b3fd62ea1a	3115	* @{
NYX	0:85b3fd62ea1a	3116	*/
NYX	0:85b3fd62ea1a	3117	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	3118	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	3119	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	3120	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	3121
NYX	0:85b3fd62ea1a	3122	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
NYX	0:85b3fd62ea1a	3123	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	3124	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	3125	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	3126	/**
NYX	0:85b3fd62ea1a	3127	* @}
NYX	0:85b3fd62ea1a	3128	*/
NYX	0:85b3fd62ea1a	3129
NYX	0:85b3fd62ea1a	3130	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
NYX	0:85b3fd62ea1a	3131	* @brief Force or release AHB2 peripheral reset.
NYX	0:85b3fd62ea1a	3132	* @{
NYX	0:85b3fd62ea1a	3133	*/
NYX	0:85b3fd62ea1a	3134	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	3135	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	3136
NYX	0:85b3fd62ea1a	3137	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
NYX	0:85b3fd62ea1a	3138	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	3139	/**
NYX	0:85b3fd62ea1a	3140	* @}
NYX	0:85b3fd62ea1a	3141	*/
NYX	0:85b3fd62ea1a	3142
NYX	0:85b3fd62ea1a	3143	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
NYX	0:85b3fd62ea1a	3144	* @brief Force or release APB1 peripheral reset.
NYX	0:85b3fd62ea1a	3145	* @{
NYX	0:85b3fd62ea1a	3146	*/
NYX	0:85b3fd62ea1a	3147	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	3148	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	3149	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	3150	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	3151	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	3152	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	3153
NYX	0:85b3fd62ea1a	3154	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
NYX	0:85b3fd62ea1a	3155	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	3156	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	3157	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	3158	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	3159	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	3160	/**
NYX	0:85b3fd62ea1a	3161	* @}
NYX	0:85b3fd62ea1a	3162	*/
NYX	0:85b3fd62ea1a	3163
NYX	0:85b3fd62ea1a	3164	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
NYX	0:85b3fd62ea1a	3165	* @brief Force or release APB2 peripheral reset.
NYX	0:85b3fd62ea1a	3166	* @{
NYX	0:85b3fd62ea1a	3167	*/
NYX	0:85b3fd62ea1a	3168	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	3169	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	3170	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	3171	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	3172
NYX	0:85b3fd62ea1a	3173	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
NYX	0:85b3fd62ea1a	3174	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	3175	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	3176	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	3177	/**
NYX	0:85b3fd62ea1a	3178	* @}
NYX	0:85b3fd62ea1a	3179	*/
NYX	0:85b3fd62ea1a	3180
NYX	0:85b3fd62ea1a	3181	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
NYX	0:85b3fd62ea1a	3182	* @brief Force or release AHB3 peripheral reset.
NYX	0:85b3fd62ea1a	3183	* @{
NYX	0:85b3fd62ea1a	3184	*/
NYX	0:85b3fd62ea1a	3185	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	3186	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
NYX	0:85b3fd62ea1a	3187	/**
NYX	0:85b3fd62ea1a	3188	* @}
NYX	0:85b3fd62ea1a	3189	*/
NYX	0:85b3fd62ea1a	3190
NYX	0:85b3fd62ea1a	3191	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3192	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3193	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	3194	* power consumption.
NYX	0:85b3fd62ea1a	3195	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	3196	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	3197	* @{
NYX	0:85b3fd62ea1a	3198	*/
NYX	0:85b3fd62ea1a	3199	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	3200	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	3201	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	3202	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	3203	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	3204
NYX	0:85b3fd62ea1a	3205	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	3206	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	3207	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	3208	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	3209	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	3210	/**
NYX	0:85b3fd62ea1a	3211	* @}
NYX	0:85b3fd62ea1a	3212	*/
NYX	0:85b3fd62ea1a	3213
NYX	0:85b3fd62ea1a	3214	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3215	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3216	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	3217	* power consumption.
NYX	0:85b3fd62ea1a	3218	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	3219	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	3220	* @{
NYX	0:85b3fd62ea1a	3221	*/
NYX	0:85b3fd62ea1a	3222	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	3223
NYX	0:85b3fd62ea1a	3224	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	3225	/**
NYX	0:85b3fd62ea1a	3226	* @}
NYX	0:85b3fd62ea1a	3227	*/
NYX	0:85b3fd62ea1a	3228
NYX	0:85b3fd62ea1a	3229	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3230	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3231	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	3232	* power consumption.
NYX	0:85b3fd62ea1a	3233	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	3234	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	3235	* @{
NYX	0:85b3fd62ea1a	3236	*/
NYX	0:85b3fd62ea1a	3237	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	3238	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	3239	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	3240	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	3241	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	3242
NYX	0:85b3fd62ea1a	3243	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	3244	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	3245	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	3246	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	3247	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	3248	/**
NYX	0:85b3fd62ea1a	3249	* @}
NYX	0:85b3fd62ea1a	3250	*/
NYX	0:85b3fd62ea1a	3251
NYX	0:85b3fd62ea1a	3252	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3253	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3254	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	3255	* power consumption.
NYX	0:85b3fd62ea1a	3256	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	3257	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	3258	* @{
NYX	0:85b3fd62ea1a	3259	*/
NYX	0:85b3fd62ea1a	3260	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	3261	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	3262	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	3263
NYX	0:85b3fd62ea1a	3264	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	3265	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	3266	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	3267	/**
NYX	0:85b3fd62ea1a	3268	* @}
NYX	0:85b3fd62ea1a	3269	*/
NYX	0:85b3fd62ea1a	3270	#endif /* STM32F401xC \|\| STM32F401xE*/
NYX	0:85b3fd62ea1a	3271	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	3272
NYX	0:85b3fd62ea1a	3273	/-------------------------------- STM32F410xx -------------------------------/
NYX	0:85b3fd62ea1a	3274	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	3275	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	3276	* @brief Enables or disables the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	3277	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3278	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3279	* using it.
NYX	0:85b3fd62ea1a	3280	* @{
NYX	0:85b3fd62ea1a	3281	*/
NYX	0:85b3fd62ea1a	3282	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3283	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3284	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	3285	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3286	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	3287	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3288	} while(0U)
NYX	0:85b3fd62ea1a	3289	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3290	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3291	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
NYX	0:85b3fd62ea1a	3292	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3293	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
NYX	0:85b3fd62ea1a	3294	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3295	} while(0U)
NYX	0:85b3fd62ea1a	3296	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
NYX	0:85b3fd62ea1a	3297	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
NYX	0:85b3fd62ea1a	3298	/**
NYX	0:85b3fd62ea1a	3299	* @}
NYX	0:85b3fd62ea1a	3300	*/
NYX	0:85b3fd62ea1a	3301
NYX	0:85b3fd62ea1a	3302	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	3303	* @brief Get the enable or disable status of the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	3304	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3305	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3306	* using it.
NYX	0:85b3fd62ea1a	3307	* @{
NYX	0:85b3fd62ea1a	3308	*/
NYX	0:85b3fd62ea1a	3309	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
NYX	0:85b3fd62ea1a	3310	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
NYX	0:85b3fd62ea1a	3311
NYX	0:85b3fd62ea1a	3312	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
NYX	0:85b3fd62ea1a	3313	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
NYX	0:85b3fd62ea1a	3314	/**
NYX	0:85b3fd62ea1a	3315	* @}
NYX	0:85b3fd62ea1a	3316	*/
NYX	0:85b3fd62ea1a	3317
NYX	0:85b3fd62ea1a	3318	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	3319	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
NYX	0:85b3fd62ea1a	3320	* @{
NYX	0:85b3fd62ea1a	3321	*/
NYX	0:85b3fd62ea1a	3322	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3323	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3324	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	3325	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3326	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	3327	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3328	} while(0U)
NYX	0:85b3fd62ea1a	3329	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3330	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3331	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
NYX	0:85b3fd62ea1a	3332	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3333	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
NYX	0:85b3fd62ea1a	3334	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3335	} while(0U)
NYX	0:85b3fd62ea1a	3336	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3337	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3338	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
NYX	0:85b3fd62ea1a	3339	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3340	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
NYX	0:85b3fd62ea1a	3341	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3342	} while(0U)
NYX	0:85b3fd62ea1a	3343	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3344	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3345	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
NYX	0:85b3fd62ea1a	3346	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3347	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
NYX	0:85b3fd62ea1a	3348	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3349	} while(0U)
NYX	0:85b3fd62ea1a	3350	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3351	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3352	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	3353	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3354	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	3355	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3356	} while(0U)
NYX	0:85b3fd62ea1a	3357
NYX	0:85b3fd62ea1a	3358	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
NYX	0:85b3fd62ea1a	3359	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
NYX	0:85b3fd62ea1a	3360	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
NYX	0:85b3fd62ea1a	3361	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
NYX	0:85b3fd62ea1a	3362	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
NYX	0:85b3fd62ea1a	3363	/**
NYX	0:85b3fd62ea1a	3364	* @}
NYX	0:85b3fd62ea1a	3365	*/
NYX	0:85b3fd62ea1a	3366
NYX	0:85b3fd62ea1a	3367	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	3368	* @brief Get the enable or disable status of the APB1 peripheral clock.
NYX	0:85b3fd62ea1a	3369	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3370	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3371	* using it.
NYX	0:85b3fd62ea1a	3372	* @{
NYX	0:85b3fd62ea1a	3373	*/
NYX	0:85b3fd62ea1a	3374	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
NYX	0:85b3fd62ea1a	3375	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
NYX	0:85b3fd62ea1a	3376	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
NYX	0:85b3fd62ea1a	3377	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
NYX	0:85b3fd62ea1a	3378	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
NYX	0:85b3fd62ea1a	3379
NYX	0:85b3fd62ea1a	3380	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
NYX	0:85b3fd62ea1a	3381	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
NYX	0:85b3fd62ea1a	3382	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
NYX	0:85b3fd62ea1a	3383	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
NYX	0:85b3fd62ea1a	3384	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
NYX	0:85b3fd62ea1a	3385	/**
NYX	0:85b3fd62ea1a	3386	* @}
NYX	0:85b3fd62ea1a	3387	*/
NYX	0:85b3fd62ea1a	3388
NYX	0:85b3fd62ea1a	3389	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	3390	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
NYX	0:85b3fd62ea1a	3391	* @{
NYX	0:85b3fd62ea1a	3392	*/
NYX	0:85b3fd62ea1a	3393	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3394	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3395	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
NYX	0:85b3fd62ea1a	3396	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3397	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
NYX	0:85b3fd62ea1a	3398	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3399	} while(0U)
NYX	0:85b3fd62ea1a	3400	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3401	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3402	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
NYX	0:85b3fd62ea1a	3403	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3404	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
NYX	0:85b3fd62ea1a	3405	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3406	} while(0U)
NYX	0:85b3fd62ea1a	3407	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
NYX	0:85b3fd62ea1a	3408	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
NYX	0:85b3fd62ea1a	3409	/**
NYX	0:85b3fd62ea1a	3410	* @}
NYX	0:85b3fd62ea1a	3411	*/
NYX	0:85b3fd62ea1a	3412
NYX	0:85b3fd62ea1a	3413	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	3414	* @brief Get the enable or disable status of the APB2 peripheral clock.
NYX	0:85b3fd62ea1a	3415	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3416	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3417	* using it.
NYX	0:85b3fd62ea1a	3418	* @{
NYX	0:85b3fd62ea1a	3419	*/
NYX	0:85b3fd62ea1a	3420	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
NYX	0:85b3fd62ea1a	3421	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
NYX	0:85b3fd62ea1a	3422
NYX	0:85b3fd62ea1a	3423	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
NYX	0:85b3fd62ea1a	3424	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
NYX	0:85b3fd62ea1a	3425	/**
NYX	0:85b3fd62ea1a	3426	* @}
NYX	0:85b3fd62ea1a	3427	*/
NYX	0:85b3fd62ea1a	3428
NYX	0:85b3fd62ea1a	3429	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
NYX	0:85b3fd62ea1a	3430	* @brief Force or release AHB1 peripheral reset.
NYX	0:85b3fd62ea1a	3431	* @{
NYX	0:85b3fd62ea1a	3432	*/
NYX	0:85b3fd62ea1a	3433	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	3434	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
NYX	0:85b3fd62ea1a	3435	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	3436	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
NYX	0:85b3fd62ea1a	3437	/**
NYX	0:85b3fd62ea1a	3438	* @}
NYX	0:85b3fd62ea1a	3439	*/
NYX	0:85b3fd62ea1a	3440
NYX	0:85b3fd62ea1a	3441	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
NYX	0:85b3fd62ea1a	3442	* @brief Force or release AHB2 peripheral reset.
NYX	0:85b3fd62ea1a	3443	* @{
NYX	0:85b3fd62ea1a	3444	*/
NYX	0:85b3fd62ea1a	3445	#define __HAL_RCC_AHB2_FORCE_RESET()
NYX	0:85b3fd62ea1a	3446	#define __HAL_RCC_AHB2_RELEASE_RESET()
NYX	0:85b3fd62ea1a	3447	/**
NYX	0:85b3fd62ea1a	3448	* @}
NYX	0:85b3fd62ea1a	3449	*/
NYX	0:85b3fd62ea1a	3450
NYX	0:85b3fd62ea1a	3451	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
NYX	0:85b3fd62ea1a	3452	* @brief Force or release AHB3 peripheral reset.
NYX	0:85b3fd62ea1a	3453	* @{
NYX	0:85b3fd62ea1a	3454	*/
NYX	0:85b3fd62ea1a	3455	#define __HAL_RCC_AHB3_FORCE_RESET()
NYX	0:85b3fd62ea1a	3456	#define __HAL_RCC_AHB3_RELEASE_RESET()
NYX	0:85b3fd62ea1a	3457	/**
NYX	0:85b3fd62ea1a	3458	* @}
NYX	0:85b3fd62ea1a	3459	*/
NYX	0:85b3fd62ea1a	3460
NYX	0:85b3fd62ea1a	3461	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
NYX	0:85b3fd62ea1a	3462	* @brief Force or release APB1 peripheral reset.
NYX	0:85b3fd62ea1a	3463	* @{
NYX	0:85b3fd62ea1a	3464	*/
NYX	0:85b3fd62ea1a	3465	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	3466	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
NYX	0:85b3fd62ea1a	3467	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
NYX	0:85b3fd62ea1a	3468	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	3469
NYX	0:85b3fd62ea1a	3470	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	3471	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
NYX	0:85b3fd62ea1a	3472	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
NYX	0:85b3fd62ea1a	3473	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	3474	/**
NYX	0:85b3fd62ea1a	3475	* @}
NYX	0:85b3fd62ea1a	3476	*/
NYX	0:85b3fd62ea1a	3477
NYX	0:85b3fd62ea1a	3478	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
NYX	0:85b3fd62ea1a	3479	* @brief Force or release APB2 peripheral reset.
NYX	0:85b3fd62ea1a	3480	* @{
NYX	0:85b3fd62ea1a	3481	*/
NYX	0:85b3fd62ea1a	3482	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
NYX	0:85b3fd62ea1a	3483	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
NYX	0:85b3fd62ea1a	3484	/**
NYX	0:85b3fd62ea1a	3485	* @}
NYX	0:85b3fd62ea1a	3486	*/
NYX	0:85b3fd62ea1a	3487
NYX	0:85b3fd62ea1a	3488	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3489	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3490	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	3491	* power consumption.
NYX	0:85b3fd62ea1a	3492	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	3493	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	3494	* @{
NYX	0:85b3fd62ea1a	3495	*/
NYX	0:85b3fd62ea1a	3496	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	3497	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	3498	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	3499	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	3500
NYX	0:85b3fd62ea1a	3501	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	3502	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	3503	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	3504	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	3505	/**
NYX	0:85b3fd62ea1a	3506	* @}
NYX	0:85b3fd62ea1a	3507	*/
NYX	0:85b3fd62ea1a	3508
NYX	0:85b3fd62ea1a	3509	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3510	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3511	* @{
NYX	0:85b3fd62ea1a	3512	*/
NYX	0:85b3fd62ea1a	3513	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	3514	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
NYX	0:85b3fd62ea1a	3515	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
NYX	0:85b3fd62ea1a	3516	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
NYX	0:85b3fd62ea1a	3517	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	3518
NYX	0:85b3fd62ea1a	3519	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	3520	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
NYX	0:85b3fd62ea1a	3521	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
NYX	0:85b3fd62ea1a	3522	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
NYX	0:85b3fd62ea1a	3523	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	3524	/**
NYX	0:85b3fd62ea1a	3525	* @}
NYX	0:85b3fd62ea1a	3526	*/
NYX	0:85b3fd62ea1a	3527
NYX	0:85b3fd62ea1a	3528	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3529	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3530	* @{
NYX	0:85b3fd62ea1a	3531	*/
NYX	0:85b3fd62ea1a	3532	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
NYX	0:85b3fd62ea1a	3533	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
NYX	0:85b3fd62ea1a	3534	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
NYX	0:85b3fd62ea1a	3535	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
NYX	0:85b3fd62ea1a	3536	/**
NYX	0:85b3fd62ea1a	3537	* @}
NYX	0:85b3fd62ea1a	3538	*/
NYX	0:85b3fd62ea1a	3539
NYX	0:85b3fd62ea1a	3540	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	3541	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	3542
NYX	0:85b3fd62ea1a	3543	/-------------------------------- STM32F411xx -------------------------------/
NYX	0:85b3fd62ea1a	3544	#if defined(STM32F411xE)
NYX	0:85b3fd62ea1a	3545	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	3546	* @brief Enables or disables the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	3547	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3548	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3549	* using it.
NYX	0:85b3fd62ea1a	3550	* @{
NYX	0:85b3fd62ea1a	3551	*/
NYX	0:85b3fd62ea1a	3552	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3553	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3554	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	3555	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3556	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	3557	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3558	} while(0U)
NYX	0:85b3fd62ea1a	3559	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3560	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3561	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	3562	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3563	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	3564	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3565	} while(0U)
NYX	0:85b3fd62ea1a	3566	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3567	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3568	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	3569	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3570	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	3571	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3572	} while(0U)
NYX	0:85b3fd62ea1a	3573	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3574	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3575	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	3576	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3577	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	3578	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3579	} while(0U)
NYX	0:85b3fd62ea1a	3580	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
NYX	0:85b3fd62ea1a	3581	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
NYX	0:85b3fd62ea1a	3582	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
NYX	0:85b3fd62ea1a	3583	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
NYX	0:85b3fd62ea1a	3584	/**
NYX	0:85b3fd62ea1a	3585	* @}
NYX	0:85b3fd62ea1a	3586	*/
NYX	0:85b3fd62ea1a	3587
NYX	0:85b3fd62ea1a	3588	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	3589	* @brief Get the enable or disable status of the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	3590	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3591	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3592	* using it.
NYX	0:85b3fd62ea1a	3593	* @{
NYX	0:85b3fd62ea1a	3594	*/
NYX	0:85b3fd62ea1a	3595	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
NYX	0:85b3fd62ea1a	3596	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
NYX	0:85b3fd62ea1a	3597	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
NYX	0:85b3fd62ea1a	3598	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
NYX	0:85b3fd62ea1a	3599
NYX	0:85b3fd62ea1a	3600	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
NYX	0:85b3fd62ea1a	3601	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
NYX	0:85b3fd62ea1a	3602	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
NYX	0:85b3fd62ea1a	3603	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
NYX	0:85b3fd62ea1a	3604	/**
NYX	0:85b3fd62ea1a	3605	* @}
NYX	0:85b3fd62ea1a	3606	*/
NYX	0:85b3fd62ea1a	3607
NYX	0:85b3fd62ea1a	3608	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	3609	* @brief Enable or disable the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	3610	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3611	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3612	* using it.
NYX	0:85b3fd62ea1a	3613	* @{
NYX	0:85b3fd62ea1a	3614	*/
NYX	0:85b3fd62ea1a	3615	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
NYX	0:85b3fd62ea1a	3616	__HAL_RCC_SYSCFG_CLK_ENABLE();\
NYX	0:85b3fd62ea1a	3617	}while(0U)
NYX	0:85b3fd62ea1a	3618
NYX	0:85b3fd62ea1a	3619	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
NYX	0:85b3fd62ea1a	3620	/**
NYX	0:85b3fd62ea1a	3621	* @}
NYX	0:85b3fd62ea1a	3622	*/
NYX	0:85b3fd62ea1a	3623
NYX	0:85b3fd62ea1a	3624	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	3625	* @brief Get the enable or disable status of the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	3626	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3627	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3628	* using it.
NYX	0:85b3fd62ea1a	3629	* @{
NYX	0:85b3fd62ea1a	3630	*/
NYX	0:85b3fd62ea1a	3631	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
NYX	0:85b3fd62ea1a	3632	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
NYX	0:85b3fd62ea1a	3633	/**
NYX	0:85b3fd62ea1a	3634	* @}
NYX	0:85b3fd62ea1a	3635	*/
NYX	0:85b3fd62ea1a	3636
NYX	0:85b3fd62ea1a	3637	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	3638	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
NYX	0:85b3fd62ea1a	3639	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3640	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3641	* using it.
NYX	0:85b3fd62ea1a	3642	* @{
NYX	0:85b3fd62ea1a	3643	*/
NYX	0:85b3fd62ea1a	3644	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3645	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3646	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	3647	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3648	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	3649	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3650	} while(0U)
NYX	0:85b3fd62ea1a	3651	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3652	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3653	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	3654	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3655	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	3656	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3657	} while(0U)
NYX	0:85b3fd62ea1a	3658	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3659	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3660	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	3661	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3662	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	3663	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3664	} while(0U)
NYX	0:85b3fd62ea1a	3665	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3666	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3667	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	3668	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3669	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	3670	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3671	} while(0U)
NYX	0:85b3fd62ea1a	3672	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3673	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3674	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	3675	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3676	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	3677	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3678	} while(0U)
NYX	0:85b3fd62ea1a	3679	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
NYX	0:85b3fd62ea1a	3680	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
NYX	0:85b3fd62ea1a	3681	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
NYX	0:85b3fd62ea1a	3682	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
NYX	0:85b3fd62ea1a	3683	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
NYX	0:85b3fd62ea1a	3684	/**
NYX	0:85b3fd62ea1a	3685	* @}
NYX	0:85b3fd62ea1a	3686	*/
NYX	0:85b3fd62ea1a	3687
NYX	0:85b3fd62ea1a	3688	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	3689	* @brief Get the enable or disable status of the APB1 peripheral clock.
NYX	0:85b3fd62ea1a	3690	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3691	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3692	* using it.
NYX	0:85b3fd62ea1a	3693	* @{
NYX	0:85b3fd62ea1a	3694	*/
NYX	0:85b3fd62ea1a	3695	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
NYX	0:85b3fd62ea1a	3696	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
NYX	0:85b3fd62ea1a	3697	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
NYX	0:85b3fd62ea1a	3698	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
NYX	0:85b3fd62ea1a	3699	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
NYX	0:85b3fd62ea1a	3700
NYX	0:85b3fd62ea1a	3701	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
NYX	0:85b3fd62ea1a	3702	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
NYX	0:85b3fd62ea1a	3703	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
NYX	0:85b3fd62ea1a	3704	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
NYX	0:85b3fd62ea1a	3705	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
NYX	0:85b3fd62ea1a	3706	/**
NYX	0:85b3fd62ea1a	3707	* @}
NYX	0:85b3fd62ea1a	3708	*/
NYX	0:85b3fd62ea1a	3709
NYX	0:85b3fd62ea1a	3710	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	3711	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
NYX	0:85b3fd62ea1a	3712	* @{
NYX	0:85b3fd62ea1a	3713	*/
NYX	0:85b3fd62ea1a	3714	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3715	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3716	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
NYX	0:85b3fd62ea1a	3717	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3718	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
NYX	0:85b3fd62ea1a	3719	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3720	} while(0U)
NYX	0:85b3fd62ea1a	3721	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3722	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3723	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	3724	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3725	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	3726	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3727	} while(0U)
NYX	0:85b3fd62ea1a	3728	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3729	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3730	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	3731	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3732	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	3733	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3734	} while(0U)
NYX	0:85b3fd62ea1a	3735	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3736	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3737	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	3738	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3739	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	3740	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3741	} while(0U)
NYX	0:85b3fd62ea1a	3742	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
NYX	0:85b3fd62ea1a	3743	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
NYX	0:85b3fd62ea1a	3744	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
NYX	0:85b3fd62ea1a	3745	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
NYX	0:85b3fd62ea1a	3746	/**
NYX	0:85b3fd62ea1a	3747	* @}
NYX	0:85b3fd62ea1a	3748	*/
NYX	0:85b3fd62ea1a	3749
NYX	0:85b3fd62ea1a	3750	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	3751	* @brief Get the enable or disable status of the APB2 peripheral clock.
NYX	0:85b3fd62ea1a	3752	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3753	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3754	* using it.
NYX	0:85b3fd62ea1a	3755	* @{
NYX	0:85b3fd62ea1a	3756	*/
NYX	0:85b3fd62ea1a	3757	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
NYX	0:85b3fd62ea1a	3758	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
NYX	0:85b3fd62ea1a	3759	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
NYX	0:85b3fd62ea1a	3760	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
NYX	0:85b3fd62ea1a	3761
NYX	0:85b3fd62ea1a	3762	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
NYX	0:85b3fd62ea1a	3763	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
NYX	0:85b3fd62ea1a	3764	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
NYX	0:85b3fd62ea1a	3765	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
NYX	0:85b3fd62ea1a	3766	/**
NYX	0:85b3fd62ea1a	3767	* @}
NYX	0:85b3fd62ea1a	3768	*/
NYX	0:85b3fd62ea1a	3769
NYX	0:85b3fd62ea1a	3770	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
NYX	0:85b3fd62ea1a	3771	* @brief Force or release AHB1 peripheral reset.
NYX	0:85b3fd62ea1a	3772	* @{
NYX	0:85b3fd62ea1a	3773	*/
NYX	0:85b3fd62ea1a	3774	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	3775	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	3776	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	3777
NYX	0:85b3fd62ea1a	3778	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	3779	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	3780	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	3781	/**
NYX	0:85b3fd62ea1a	3782	* @}
NYX	0:85b3fd62ea1a	3783	*/
NYX	0:85b3fd62ea1a	3784
NYX	0:85b3fd62ea1a	3785	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
NYX	0:85b3fd62ea1a	3786	* @brief Force or release AHB2 peripheral reset.
NYX	0:85b3fd62ea1a	3787	* @{
NYX	0:85b3fd62ea1a	3788	*/
NYX	0:85b3fd62ea1a	3789	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	3790	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	3791
NYX	0:85b3fd62ea1a	3792	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
NYX	0:85b3fd62ea1a	3793	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	3794	/**
NYX	0:85b3fd62ea1a	3795	* @}
NYX	0:85b3fd62ea1a	3796	*/
NYX	0:85b3fd62ea1a	3797
NYX	0:85b3fd62ea1a	3798	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
NYX	0:85b3fd62ea1a	3799	* @brief Force or release AHB3 peripheral reset.
NYX	0:85b3fd62ea1a	3800	* @{
NYX	0:85b3fd62ea1a	3801	*/
NYX	0:85b3fd62ea1a	3802	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	3803	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
NYX	0:85b3fd62ea1a	3804	/**
NYX	0:85b3fd62ea1a	3805	* @}
NYX	0:85b3fd62ea1a	3806	*/
NYX	0:85b3fd62ea1a	3807
NYX	0:85b3fd62ea1a	3808	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
NYX	0:85b3fd62ea1a	3809	* @brief Force or release APB1 peripheral reset.
NYX	0:85b3fd62ea1a	3810	* @{
NYX	0:85b3fd62ea1a	3811	*/
NYX	0:85b3fd62ea1a	3812	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	3813	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	3814	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	3815	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	3816	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	3817
NYX	0:85b3fd62ea1a	3818	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	3819	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	3820	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	3821	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	3822	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	3823	/**
NYX	0:85b3fd62ea1a	3824	* @}
NYX	0:85b3fd62ea1a	3825	*/
NYX	0:85b3fd62ea1a	3826
NYX	0:85b3fd62ea1a	3827	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
NYX	0:85b3fd62ea1a	3828	* @brief Force or release APB2 peripheral reset.
NYX	0:85b3fd62ea1a	3829	* @{
NYX	0:85b3fd62ea1a	3830	*/
NYX	0:85b3fd62ea1a	3831	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
NYX	0:85b3fd62ea1a	3832	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	3833	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	3834	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	3835
NYX	0:85b3fd62ea1a	3836	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	3837	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	3838	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	3839	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
NYX	0:85b3fd62ea1a	3840	/**
NYX	0:85b3fd62ea1a	3841	* @}
NYX	0:85b3fd62ea1a	3842	*/
NYX	0:85b3fd62ea1a	3843
NYX	0:85b3fd62ea1a	3844	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3845	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3846	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	3847	* power consumption.
NYX	0:85b3fd62ea1a	3848	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	3849	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	3850	* @{
NYX	0:85b3fd62ea1a	3851	*/
NYX	0:85b3fd62ea1a	3852	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	3853	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	3854	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	3855	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	3856	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	3857
NYX	0:85b3fd62ea1a	3858	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	3859	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	3860	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	3861	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	3862	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	3863	/**
NYX	0:85b3fd62ea1a	3864	* @}
NYX	0:85b3fd62ea1a	3865	*/
NYX	0:85b3fd62ea1a	3866
NYX	0:85b3fd62ea1a	3867	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3868	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3869	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	3870	* power consumption.
NYX	0:85b3fd62ea1a	3871	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	3872	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	3873	* @{
NYX	0:85b3fd62ea1a	3874	*/
NYX	0:85b3fd62ea1a	3875	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	3876	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	3877	/**
NYX	0:85b3fd62ea1a	3878	* @}
NYX	0:85b3fd62ea1a	3879	*/
NYX	0:85b3fd62ea1a	3880
NYX	0:85b3fd62ea1a	3881	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3882	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3883	* @{
NYX	0:85b3fd62ea1a	3884	*/
NYX	0:85b3fd62ea1a	3885	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	3886	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	3887	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	3888	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	3889	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	3890
NYX	0:85b3fd62ea1a	3891	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	3892	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	3893	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	3894	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	3895	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	3896	/**
NYX	0:85b3fd62ea1a	3897	* @}
NYX	0:85b3fd62ea1a	3898	*/
NYX	0:85b3fd62ea1a	3899
NYX	0:85b3fd62ea1a	3900	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	3901	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	3902	* @{
NYX	0:85b3fd62ea1a	3903	*/
NYX	0:85b3fd62ea1a	3904	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
NYX	0:85b3fd62ea1a	3905	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	3906	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	3907	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	3908
NYX	0:85b3fd62ea1a	3909	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	3910	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	3911	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	3912	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
NYX	0:85b3fd62ea1a	3913	/**
NYX	0:85b3fd62ea1a	3914	* @}
NYX	0:85b3fd62ea1a	3915	*/
NYX	0:85b3fd62ea1a	3916	#endif /* STM32F411xE */
NYX	0:85b3fd62ea1a	3917	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	3918
NYX	0:85b3fd62ea1a	3919	/---------------------------------- STM32F446xx -----------------------------/
NYX	0:85b3fd62ea1a	3920	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	3921	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	3922	* @brief Enables or disables the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	3923	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	3924	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	3925	* using it.
NYX	0:85b3fd62ea1a	3926	* @{
NYX	0:85b3fd62ea1a	3927	*/
NYX	0:85b3fd62ea1a	3928	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3929	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3930	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
NYX	0:85b3fd62ea1a	3931	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3932	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
NYX	0:85b3fd62ea1a	3933	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3934	} while(0U)
NYX	0:85b3fd62ea1a	3935	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3936	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3937	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	3938	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3939	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
NYX	0:85b3fd62ea1a	3940	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3941	} while(0U)
NYX	0:85b3fd62ea1a	3942	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3943	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3944	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	3945	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3946	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	3947	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3948	} while(0U)
NYX	0:85b3fd62ea1a	3949	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3950	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3951	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	3952	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3953	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	3954	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3955	} while(0U)
NYX	0:85b3fd62ea1a	3956	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3957	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3958	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	3959	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3960	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	3961	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3962	} while(0U)
NYX	0:85b3fd62ea1a	3963	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3964	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3965	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
NYX	0:85b3fd62ea1a	3966	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3967	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
NYX	0:85b3fd62ea1a	3968	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3969	} while(0U)
NYX	0:85b3fd62ea1a	3970	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3971	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3972	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
NYX	0:85b3fd62ea1a	3973	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3974	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
NYX	0:85b3fd62ea1a	3975	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3976	} while(0U)
NYX	0:85b3fd62ea1a	3977	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3978	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3979	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
NYX	0:85b3fd62ea1a	3980	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3981	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
NYX	0:85b3fd62ea1a	3982	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3983	} while(0U)
NYX	0:85b3fd62ea1a	3984	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	3985	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	3986	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
NYX	0:85b3fd62ea1a	3987	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	3988	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
NYX	0:85b3fd62ea1a	3989	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	3990	} while(0U)
NYX	0:85b3fd62ea1a	3991	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
NYX	0:85b3fd62ea1a	3992	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
NYX	0:85b3fd62ea1a	3993	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
NYX	0:85b3fd62ea1a	3994	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
NYX	0:85b3fd62ea1a	3995	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
NYX	0:85b3fd62ea1a	3996	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
NYX	0:85b3fd62ea1a	3997	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
NYX	0:85b3fd62ea1a	3998	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
NYX	0:85b3fd62ea1a	3999	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
NYX	0:85b3fd62ea1a	4000	/**
NYX	0:85b3fd62ea1a	4001	* @}
NYX	0:85b3fd62ea1a	4002	*/
NYX	0:85b3fd62ea1a	4003
NYX	0:85b3fd62ea1a	4004	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	4005	* @brief Get the enable or disable status of the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	4006	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4007	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4008	* using it.
NYX	0:85b3fd62ea1a	4009	* @{
NYX	0:85b3fd62ea1a	4010	*/
NYX	0:85b3fd62ea1a	4011	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
NYX	0:85b3fd62ea1a	4012	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
NYX	0:85b3fd62ea1a	4013	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
NYX	0:85b3fd62ea1a	4014	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
NYX	0:85b3fd62ea1a	4015	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
NYX	0:85b3fd62ea1a	4016	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
NYX	0:85b3fd62ea1a	4017	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
NYX	0:85b3fd62ea1a	4018	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
NYX	0:85b3fd62ea1a	4019	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
NYX	0:85b3fd62ea1a	4020
NYX	0:85b3fd62ea1a	4021	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
NYX	0:85b3fd62ea1a	4022	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
NYX	0:85b3fd62ea1a	4023	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
NYX	0:85b3fd62ea1a	4024	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
NYX	0:85b3fd62ea1a	4025	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
NYX	0:85b3fd62ea1a	4026	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
NYX	0:85b3fd62ea1a	4027	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
NYX	0:85b3fd62ea1a	4028	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
NYX	0:85b3fd62ea1a	4029	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
NYX	0:85b3fd62ea1a	4030	/**
NYX	0:85b3fd62ea1a	4031	* @}
NYX	0:85b3fd62ea1a	4032	*/
NYX	0:85b3fd62ea1a	4033
NYX	0:85b3fd62ea1a	4034	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	4035	* @brief Enable or disable the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	4036	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4037	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4038	* using it.
NYX	0:85b3fd62ea1a	4039	* @{
NYX	0:85b3fd62ea1a	4040	*/
NYX	0:85b3fd62ea1a	4041	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4042	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4043	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
NYX	0:85b3fd62ea1a	4044	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4045	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
NYX	0:85b3fd62ea1a	4046	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4047	} while(0U)
NYX	0:85b3fd62ea1a	4048	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
NYX	0:85b3fd62ea1a	4049	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
NYX	0:85b3fd62ea1a	4050	__HAL_RCC_SYSCFG_CLK_ENABLE();\
NYX	0:85b3fd62ea1a	4051	}while(0U)
NYX	0:85b3fd62ea1a	4052
NYX	0:85b3fd62ea1a	4053	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
NYX	0:85b3fd62ea1a	4054
NYX	0:85b3fd62ea1a	4055	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4056	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4057	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
NYX	0:85b3fd62ea1a	4058	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4059	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
NYX	0:85b3fd62ea1a	4060	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4061	} while(0U)
NYX	0:85b3fd62ea1a	4062	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
NYX	0:85b3fd62ea1a	4063	/**
NYX	0:85b3fd62ea1a	4064	* @}
NYX	0:85b3fd62ea1a	4065	*/
NYX	0:85b3fd62ea1a	4066
NYX	0:85b3fd62ea1a	4067	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	4068	* @brief Get the enable or disable status of the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	4069	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4070	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4071	* using it.
NYX	0:85b3fd62ea1a	4072	* @{
NYX	0:85b3fd62ea1a	4073	*/
NYX	0:85b3fd62ea1a	4074	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
NYX	0:85b3fd62ea1a	4075	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
NYX	0:85b3fd62ea1a	4076
NYX	0:85b3fd62ea1a	4077	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
NYX	0:85b3fd62ea1a	4078	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
NYX	0:85b3fd62ea1a	4079
NYX	0:85b3fd62ea1a	4080	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
NYX	0:85b3fd62ea1a	4081	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
NYX	0:85b3fd62ea1a	4082	/**
NYX	0:85b3fd62ea1a	4083	* @}
NYX	0:85b3fd62ea1a	4084	*/
NYX	0:85b3fd62ea1a	4085
NYX	0:85b3fd62ea1a	4086	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	4087	* @brief Enables or disables the AHB3 peripheral clock.
NYX	0:85b3fd62ea1a	4088	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4089	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4090	* using it.
NYX	0:85b3fd62ea1a	4091	* @{
NYX	0:85b3fd62ea1a	4092	*/
NYX	0:85b3fd62ea1a	4093	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4094	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4095	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
NYX	0:85b3fd62ea1a	4096	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4097	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
NYX	0:85b3fd62ea1a	4098	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4099	} while(0U)
NYX	0:85b3fd62ea1a	4100	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4101	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4102	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
NYX	0:85b3fd62ea1a	4103	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4104	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
NYX	0:85b3fd62ea1a	4105	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4106	} while(0U)
NYX	0:85b3fd62ea1a	4107
NYX	0:85b3fd62ea1a	4108	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
NYX	0:85b3fd62ea1a	4109	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
NYX	0:85b3fd62ea1a	4110	/**
NYX	0:85b3fd62ea1a	4111	* @}
NYX	0:85b3fd62ea1a	4112	*/
NYX	0:85b3fd62ea1a	4113
NYX	0:85b3fd62ea1a	4114	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	4115	* @brief Get the enable or disable status of the AHB3 peripheral clock.
NYX	0:85b3fd62ea1a	4116	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4117	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4118	* using it.
NYX	0:85b3fd62ea1a	4119	* @{
NYX	0:85b3fd62ea1a	4120	*/
NYX	0:85b3fd62ea1a	4121	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
NYX	0:85b3fd62ea1a	4122	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
NYX	0:85b3fd62ea1a	4123
NYX	0:85b3fd62ea1a	4124	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
NYX	0:85b3fd62ea1a	4125	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
NYX	0:85b3fd62ea1a	4126	/**
NYX	0:85b3fd62ea1a	4127	* @}
NYX	0:85b3fd62ea1a	4128	*/
NYX	0:85b3fd62ea1a	4129
NYX	0:85b3fd62ea1a	4130	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	4131	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
NYX	0:85b3fd62ea1a	4132	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4133	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4134	* using it.
NYX	0:85b3fd62ea1a	4135	* @{
NYX	0:85b3fd62ea1a	4136	*/
NYX	0:85b3fd62ea1a	4137	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4138	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4139	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	4140	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4141	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	4142	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4143	} while(0U)
NYX	0:85b3fd62ea1a	4144	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4145	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4146	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
NYX	0:85b3fd62ea1a	4147	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4148	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
NYX	0:85b3fd62ea1a	4149	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4150	} while(0U)
NYX	0:85b3fd62ea1a	4151	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4152	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4153	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
NYX	0:85b3fd62ea1a	4154	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4155	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
NYX	0:85b3fd62ea1a	4156	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4157	} while(0U)
NYX	0:85b3fd62ea1a	4158	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4159	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4160	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
NYX	0:85b3fd62ea1a	4161	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4162	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
NYX	0:85b3fd62ea1a	4163	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4164	} while(0U)
NYX	0:85b3fd62ea1a	4165	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4166	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4167	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	4168	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4169	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	4170	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4171	} while(0U)
NYX	0:85b3fd62ea1a	4172	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4173	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4174	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
NYX	0:85b3fd62ea1a	4175	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4176	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
NYX	0:85b3fd62ea1a	4177	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4178	} while(0U)
NYX	0:85b3fd62ea1a	4179	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4180	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4181	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
NYX	0:85b3fd62ea1a	4182	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4183	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
NYX	0:85b3fd62ea1a	4184	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4185	} while(0U)
NYX	0:85b3fd62ea1a	4186	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4187	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4188	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
NYX	0:85b3fd62ea1a	4189	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4190	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
NYX	0:85b3fd62ea1a	4191	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4192	} while(0U)
NYX	0:85b3fd62ea1a	4193	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4194	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4195	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
NYX	0:85b3fd62ea1a	4196	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4197	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
NYX	0:85b3fd62ea1a	4198	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4199	} while(0U)
NYX	0:85b3fd62ea1a	4200	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4201	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4202	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
NYX	0:85b3fd62ea1a	4203	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4204	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
NYX	0:85b3fd62ea1a	4205	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4206	} while(0U)
NYX	0:85b3fd62ea1a	4207	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4208	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4209	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
NYX	0:85b3fd62ea1a	4210	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4211	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
NYX	0:85b3fd62ea1a	4212	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4213	} while(0U)
NYX	0:85b3fd62ea1a	4214	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4215	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4216	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
NYX	0:85b3fd62ea1a	4217	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4218	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
NYX	0:85b3fd62ea1a	4219	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4220	} while(0U)
NYX	0:85b3fd62ea1a	4221	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4222	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4223	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
NYX	0:85b3fd62ea1a	4224	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4225	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
NYX	0:85b3fd62ea1a	4226	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4227	} while(0U)
NYX	0:85b3fd62ea1a	4228	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4229	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4230	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	4231	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4232	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	4233	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4234	} while(0U)
NYX	0:85b3fd62ea1a	4235	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4236	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4237	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	4238	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4239	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	4240	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4241	} while(0U)
NYX	0:85b3fd62ea1a	4242	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4243	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4244	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	4245	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4246	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	4247	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4248	} while(0U)
NYX	0:85b3fd62ea1a	4249	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4250	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4251	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	4252	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4253	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	4254	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4255	} while(0U)
NYX	0:85b3fd62ea1a	4256	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4257	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4258	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	4259	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4260	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	4261	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4262	} while(0U)
NYX	0:85b3fd62ea1a	4263	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4264	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4265	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	4266	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4267	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	4268	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4269	} while(0U)
NYX	0:85b3fd62ea1a	4270	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
NYX	0:85b3fd62ea1a	4271	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
NYX	0:85b3fd62ea1a	4272	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
NYX	0:85b3fd62ea1a	4273	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
NYX	0:85b3fd62ea1a	4274	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
NYX	0:85b3fd62ea1a	4275	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
NYX	0:85b3fd62ea1a	4276	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
NYX	0:85b3fd62ea1a	4277	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
NYX	0:85b3fd62ea1a	4278	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
NYX	0:85b3fd62ea1a	4279	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
NYX	0:85b3fd62ea1a	4280	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
NYX	0:85b3fd62ea1a	4281	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
NYX	0:85b3fd62ea1a	4282	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
NYX	0:85b3fd62ea1a	4283	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
NYX	0:85b3fd62ea1a	4284	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
NYX	0:85b3fd62ea1a	4285	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
NYX	0:85b3fd62ea1a	4286	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
NYX	0:85b3fd62ea1a	4287	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
NYX	0:85b3fd62ea1a	4288	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
NYX	0:85b3fd62ea1a	4289	/**
NYX	0:85b3fd62ea1a	4290	* @}
NYX	0:85b3fd62ea1a	4291	*/
NYX	0:85b3fd62ea1a	4292
NYX	0:85b3fd62ea1a	4293	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	4294	* @brief Get the enable or disable status of the APB1 peripheral clock.
NYX	0:85b3fd62ea1a	4295	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4296	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4297	* using it.
NYX	0:85b3fd62ea1a	4298	* @{
NYX	0:85b3fd62ea1a	4299	*/
NYX	0:85b3fd62ea1a	4300	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
NYX	0:85b3fd62ea1a	4301	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
NYX	0:85b3fd62ea1a	4302	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
NYX	0:85b3fd62ea1a	4303	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
NYX	0:85b3fd62ea1a	4304	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
NYX	0:85b3fd62ea1a	4305	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
NYX	0:85b3fd62ea1a	4306	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
NYX	0:85b3fd62ea1a	4307	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
NYX	0:85b3fd62ea1a	4308	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
NYX	0:85b3fd62ea1a	4309	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
NYX	0:85b3fd62ea1a	4310	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
NYX	0:85b3fd62ea1a	4311	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
NYX	0:85b3fd62ea1a	4312	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
NYX	0:85b3fd62ea1a	4313	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
NYX	0:85b3fd62ea1a	4314	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
NYX	0:85b3fd62ea1a	4315	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
NYX	0:85b3fd62ea1a	4316	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
NYX	0:85b3fd62ea1a	4317	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
NYX	0:85b3fd62ea1a	4318	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
NYX	0:85b3fd62ea1a	4319
NYX	0:85b3fd62ea1a	4320	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
NYX	0:85b3fd62ea1a	4321	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
NYX	0:85b3fd62ea1a	4322	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
NYX	0:85b3fd62ea1a	4323	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
NYX	0:85b3fd62ea1a	4324	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
NYX	0:85b3fd62ea1a	4325	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
NYX	0:85b3fd62ea1a	4326	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
NYX	0:85b3fd62ea1a	4327	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
NYX	0:85b3fd62ea1a	4328	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
NYX	0:85b3fd62ea1a	4329	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
NYX	0:85b3fd62ea1a	4330	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
NYX	0:85b3fd62ea1a	4331	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
NYX	0:85b3fd62ea1a	4332	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
NYX	0:85b3fd62ea1a	4333	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
NYX	0:85b3fd62ea1a	4334	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
NYX	0:85b3fd62ea1a	4335	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
NYX	0:85b3fd62ea1a	4336	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
NYX	0:85b3fd62ea1a	4337	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
NYX	0:85b3fd62ea1a	4338	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
NYX	0:85b3fd62ea1a	4339	/**
NYX	0:85b3fd62ea1a	4340	* @}
NYX	0:85b3fd62ea1a	4341	*/
NYX	0:85b3fd62ea1a	4342
NYX	0:85b3fd62ea1a	4343	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	4344	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
NYX	0:85b3fd62ea1a	4345	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4346	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4347	* using it.
NYX	0:85b3fd62ea1a	4348	* @{
NYX	0:85b3fd62ea1a	4349	*/
NYX	0:85b3fd62ea1a	4350	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4351	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4352	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
NYX	0:85b3fd62ea1a	4353	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4354	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
NYX	0:85b3fd62ea1a	4355	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4356	} while(0U)
NYX	0:85b3fd62ea1a	4357	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4358	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4359	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
NYX	0:85b3fd62ea1a	4360	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4361	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
NYX	0:85b3fd62ea1a	4362	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4363	} while(0U)
NYX	0:85b3fd62ea1a	4364	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4365	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4366	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
NYX	0:85b3fd62ea1a	4367	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4368	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
NYX	0:85b3fd62ea1a	4369	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4370	} while(0U)
NYX	0:85b3fd62ea1a	4371	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4372	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4373	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
NYX	0:85b3fd62ea1a	4374	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4375	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
NYX	0:85b3fd62ea1a	4376	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4377	} while(0U)
NYX	0:85b3fd62ea1a	4378	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4379	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4380	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
NYX	0:85b3fd62ea1a	4381	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4382	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
NYX	0:85b3fd62ea1a	4383	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4384	} while(0U)
NYX	0:85b3fd62ea1a	4385	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4386	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4387	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	4388	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4389	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	4390	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4391	} while(0U)
NYX	0:85b3fd62ea1a	4392	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4393	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4394	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	4395	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4396	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	4397	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4398	} while(0U)
NYX	0:85b3fd62ea1a	4399	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4400	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4401	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	4402	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4403	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	4404	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4405	} while(0U)
NYX	0:85b3fd62ea1a	4406	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
NYX	0:85b3fd62ea1a	4407	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
NYX	0:85b3fd62ea1a	4408	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
NYX	0:85b3fd62ea1a	4409	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
NYX	0:85b3fd62ea1a	4410	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
NYX	0:85b3fd62ea1a	4411	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
NYX	0:85b3fd62ea1a	4412	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
NYX	0:85b3fd62ea1a	4413	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
NYX	0:85b3fd62ea1a	4414	/**
NYX	0:85b3fd62ea1a	4415	* @}
NYX	0:85b3fd62ea1a	4416	*/
NYX	0:85b3fd62ea1a	4417
NYX	0:85b3fd62ea1a	4418	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	4419	* @brief Get the enable or disable status of the APB2 peripheral clock.
NYX	0:85b3fd62ea1a	4420	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4421	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4422	* using it.
NYX	0:85b3fd62ea1a	4423	* @{
NYX	0:85b3fd62ea1a	4424	*/
NYX	0:85b3fd62ea1a	4425	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
NYX	0:85b3fd62ea1a	4426	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
NYX	0:85b3fd62ea1a	4427	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
NYX	0:85b3fd62ea1a	4428	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
NYX	0:85b3fd62ea1a	4429	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
NYX	0:85b3fd62ea1a	4430	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
NYX	0:85b3fd62ea1a	4431	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
NYX	0:85b3fd62ea1a	4432	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
NYX	0:85b3fd62ea1a	4433
NYX	0:85b3fd62ea1a	4434	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
NYX	0:85b3fd62ea1a	4435	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
NYX	0:85b3fd62ea1a	4436	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
NYX	0:85b3fd62ea1a	4437	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
NYX	0:85b3fd62ea1a	4438	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
NYX	0:85b3fd62ea1a	4439	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
NYX	0:85b3fd62ea1a	4440	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
NYX	0:85b3fd62ea1a	4441	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
NYX	0:85b3fd62ea1a	4442	/**
NYX	0:85b3fd62ea1a	4443	* @}
NYX	0:85b3fd62ea1a	4444	*/
NYX	0:85b3fd62ea1a	4445
NYX	0:85b3fd62ea1a	4446	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
NYX	0:85b3fd62ea1a	4447	* @brief Force or release AHB1 peripheral reset.
NYX	0:85b3fd62ea1a	4448	* @{
NYX	0:85b3fd62ea1a	4449	*/
NYX	0:85b3fd62ea1a	4450	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	4451	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	4452	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
NYX	0:85b3fd62ea1a	4453	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
NYX	0:85b3fd62ea1a	4454	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
NYX	0:85b3fd62ea1a	4455	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	4456
NYX	0:85b3fd62ea1a	4457	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	4458	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	4459	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
NYX	0:85b3fd62ea1a	4460	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
NYX	0:85b3fd62ea1a	4461	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
NYX	0:85b3fd62ea1a	4462	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	4463	/**
NYX	0:85b3fd62ea1a	4464	* @}
NYX	0:85b3fd62ea1a	4465	*/
NYX	0:85b3fd62ea1a	4466
NYX	0:85b3fd62ea1a	4467	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
NYX	0:85b3fd62ea1a	4468	* @brief Force or release AHB2 peripheral reset.
NYX	0:85b3fd62ea1a	4469	* @{
NYX	0:85b3fd62ea1a	4470	*/
NYX	0:85b3fd62ea1a	4471	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	4472	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	4473	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
NYX	0:85b3fd62ea1a	4474	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
NYX	0:85b3fd62ea1a	4475
NYX	0:85b3fd62ea1a	4476	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
NYX	0:85b3fd62ea1a	4477	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	4478	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
NYX	0:85b3fd62ea1a	4479	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
NYX	0:85b3fd62ea1a	4480	/**
NYX	0:85b3fd62ea1a	4481	* @}
NYX	0:85b3fd62ea1a	4482	*/
NYX	0:85b3fd62ea1a	4483
NYX	0:85b3fd62ea1a	4484	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
NYX	0:85b3fd62ea1a	4485	* @brief Force or release AHB3 peripheral reset.
NYX	0:85b3fd62ea1a	4486	* @{
NYX	0:85b3fd62ea1a	4487	*/
NYX	0:85b3fd62ea1a	4488	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	4489	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
NYX	0:85b3fd62ea1a	4490
NYX	0:85b3fd62ea1a	4491	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
NYX	0:85b3fd62ea1a	4492	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
NYX	0:85b3fd62ea1a	4493
NYX	0:85b3fd62ea1a	4494	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
NYX	0:85b3fd62ea1a	4495	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
NYX	0:85b3fd62ea1a	4496	/**
NYX	0:85b3fd62ea1a	4497	* @}
NYX	0:85b3fd62ea1a	4498	*/
NYX	0:85b3fd62ea1a	4499
NYX	0:85b3fd62ea1a	4500	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
NYX	0:85b3fd62ea1a	4501	* @brief Force or release APB1 peripheral reset.
NYX	0:85b3fd62ea1a	4502	* @{
NYX	0:85b3fd62ea1a	4503	*/
NYX	0:85b3fd62ea1a	4504	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	4505	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
NYX	0:85b3fd62ea1a	4506	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
NYX	0:85b3fd62ea1a	4507	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
NYX	0:85b3fd62ea1a	4508	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
NYX	0:85b3fd62ea1a	4509	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
NYX	0:85b3fd62ea1a	4510	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
NYX	0:85b3fd62ea1a	4511	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
NYX	0:85b3fd62ea1a	4512	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
NYX	0:85b3fd62ea1a	4513	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
NYX	0:85b3fd62ea1a	4514	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
NYX	0:85b3fd62ea1a	4515	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
NYX	0:85b3fd62ea1a	4516	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
NYX	0:85b3fd62ea1a	4517	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	4518	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	4519	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	4520	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	4521	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	4522	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	4523
NYX	0:85b3fd62ea1a	4524	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	4525	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	4526	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	4527	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	4528	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	4529	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	4530	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
NYX	0:85b3fd62ea1a	4531	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
NYX	0:85b3fd62ea1a	4532	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
NYX	0:85b3fd62ea1a	4533	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
NYX	0:85b3fd62ea1a	4534	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
NYX	0:85b3fd62ea1a	4535	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
NYX	0:85b3fd62ea1a	4536	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
NYX	0:85b3fd62ea1a	4537	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
NYX	0:85b3fd62ea1a	4538	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
NYX	0:85b3fd62ea1a	4539	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
NYX	0:85b3fd62ea1a	4540	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
NYX	0:85b3fd62ea1a	4541	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
NYX	0:85b3fd62ea1a	4542	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	4543	/**
NYX	0:85b3fd62ea1a	4544	* @}
NYX	0:85b3fd62ea1a	4545	*/
NYX	0:85b3fd62ea1a	4546
NYX	0:85b3fd62ea1a	4547	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
NYX	0:85b3fd62ea1a	4548	* @brief Force or release APB2 peripheral reset.
NYX	0:85b3fd62ea1a	4549	* @{
NYX	0:85b3fd62ea1a	4550	*/
NYX	0:85b3fd62ea1a	4551	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
NYX	0:85b3fd62ea1a	4552	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
NYX	0:85b3fd62ea1a	4553	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
NYX	0:85b3fd62ea1a	4554	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	4555	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	4556	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	4557
NYX	0:85b3fd62ea1a	4558	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	4559	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	4560	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	4561	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
NYX	0:85b3fd62ea1a	4562	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
NYX	0:85b3fd62ea1a	4563	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
NYX	0:85b3fd62ea1a	4564	/**
NYX	0:85b3fd62ea1a	4565	* @}
NYX	0:85b3fd62ea1a	4566	*/
NYX	0:85b3fd62ea1a	4567
NYX	0:85b3fd62ea1a	4568	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	4569	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	4570	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	4571	* power consumption.
NYX	0:85b3fd62ea1a	4572	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	4573	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	4574	* @{
NYX	0:85b3fd62ea1a	4575	*/
NYX	0:85b3fd62ea1a	4576	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	4577	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	4578	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
NYX	0:85b3fd62ea1a	4579	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
NYX	0:85b3fd62ea1a	4580	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
NYX	0:85b3fd62ea1a	4581	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
NYX	0:85b3fd62ea1a	4582	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
NYX	0:85b3fd62ea1a	4583	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	4584	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	4585	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	4586	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
NYX	0:85b3fd62ea1a	4587
NYX	0:85b3fd62ea1a	4588	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	4589	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	4590	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
NYX	0:85b3fd62ea1a	4591	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
NYX	0:85b3fd62ea1a	4592	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
NYX	0:85b3fd62ea1a	4593	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
NYX	0:85b3fd62ea1a	4594	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
NYX	0:85b3fd62ea1a	4595	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	4596	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	4597	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	4598	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
NYX	0:85b3fd62ea1a	4599	/**
NYX	0:85b3fd62ea1a	4600	* @}
NYX	0:85b3fd62ea1a	4601	*/
NYX	0:85b3fd62ea1a	4602
NYX	0:85b3fd62ea1a	4603	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	4604	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	4605	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	4606	* power consumption.
NYX	0:85b3fd62ea1a	4607	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	4608	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	4609	* @{
NYX	0:85b3fd62ea1a	4610	*/
NYX	0:85b3fd62ea1a	4611	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	4612	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	4613
NYX	0:85b3fd62ea1a	4614	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	4615	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	4616
NYX	0:85b3fd62ea1a	4617	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
NYX	0:85b3fd62ea1a	4618	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
NYX	0:85b3fd62ea1a	4619	/**
NYX	0:85b3fd62ea1a	4620	* @}
NYX	0:85b3fd62ea1a	4621	*/
NYX	0:85b3fd62ea1a	4622
NYX	0:85b3fd62ea1a	4623	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	4624	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	4625	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	4626	* power consumption.
NYX	0:85b3fd62ea1a	4627	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	4628	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	4629	* @{
NYX	0:85b3fd62ea1a	4630	*/
NYX	0:85b3fd62ea1a	4631	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
NYX	0:85b3fd62ea1a	4632	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
NYX	0:85b3fd62ea1a	4633
NYX	0:85b3fd62ea1a	4634	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
NYX	0:85b3fd62ea1a	4635	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
NYX	0:85b3fd62ea1a	4636	/**
NYX	0:85b3fd62ea1a	4637	* @}
NYX	0:85b3fd62ea1a	4638	*/
NYX	0:85b3fd62ea1a	4639
NYX	0:85b3fd62ea1a	4640	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	4641	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	4642	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	4643	* power consumption.
NYX	0:85b3fd62ea1a	4644	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	4645	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	4646	* @{
NYX	0:85b3fd62ea1a	4647	*/
NYX	0:85b3fd62ea1a	4648	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	4649	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
NYX	0:85b3fd62ea1a	4650	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
NYX	0:85b3fd62ea1a	4651	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
NYX	0:85b3fd62ea1a	4652	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
NYX	0:85b3fd62ea1a	4653	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
NYX	0:85b3fd62ea1a	4654	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
NYX	0:85b3fd62ea1a	4655	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
NYX	0:85b3fd62ea1a	4656	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
NYX	0:85b3fd62ea1a	4657	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
NYX	0:85b3fd62ea1a	4658	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
NYX	0:85b3fd62ea1a	4659	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
NYX	0:85b3fd62ea1a	4660	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
NYX	0:85b3fd62ea1a	4661	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	4662	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	4663	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	4664	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	4665	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	4666	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	4667
NYX	0:85b3fd62ea1a	4668	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	4669	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	4670	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	4671	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	4672	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	4673	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	4674	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
NYX	0:85b3fd62ea1a	4675	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
NYX	0:85b3fd62ea1a	4676	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
NYX	0:85b3fd62ea1a	4677	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
NYX	0:85b3fd62ea1a	4678	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
NYX	0:85b3fd62ea1a	4679	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
NYX	0:85b3fd62ea1a	4680	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
NYX	0:85b3fd62ea1a	4681	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
NYX	0:85b3fd62ea1a	4682	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
NYX	0:85b3fd62ea1a	4683	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
NYX	0:85b3fd62ea1a	4684	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
NYX	0:85b3fd62ea1a	4685	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
NYX	0:85b3fd62ea1a	4686	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	4687	/**
NYX	0:85b3fd62ea1a	4688	* @}
NYX	0:85b3fd62ea1a	4689	*/
NYX	0:85b3fd62ea1a	4690
NYX	0:85b3fd62ea1a	4691	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	4692	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	4693	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	4694	* power consumption.
NYX	0:85b3fd62ea1a	4695	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	4696	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	4697	* @{
NYX	0:85b3fd62ea1a	4698	*/
NYX	0:85b3fd62ea1a	4699	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
NYX	0:85b3fd62ea1a	4700	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
NYX	0:85b3fd62ea1a	4701	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
NYX	0:85b3fd62ea1a	4702	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
NYX	0:85b3fd62ea1a	4703	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
NYX	0:85b3fd62ea1a	4704	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	4705	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	4706	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	4707
NYX	0:85b3fd62ea1a	4708	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	4709	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	4710	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	4711	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
NYX	0:85b3fd62ea1a	4712	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
NYX	0:85b3fd62ea1a	4713	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
NYX	0:85b3fd62ea1a	4714	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
NYX	0:85b3fd62ea1a	4715	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
NYX	0:85b3fd62ea1a	4716	/**
NYX	0:85b3fd62ea1a	4717	* @}
NYX	0:85b3fd62ea1a	4718	*/
NYX	0:85b3fd62ea1a	4719
NYX	0:85b3fd62ea1a	4720	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	4721	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	4722
NYX	0:85b3fd62ea1a	4723	/-------STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx-------/
NYX	0:85b3fd62ea1a	4724	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	4725	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	4726	* @brief Enables or disables the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	4727	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4728	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4729	* using it.
NYX	0:85b3fd62ea1a	4730	* @{
NYX	0:85b3fd62ea1a	4731	*/
NYX	0:85b3fd62ea1a	4732	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4733	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4734	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	4735	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4736	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
NYX	0:85b3fd62ea1a	4737	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4738	} while(0U)
NYX	0:85b3fd62ea1a	4739	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4740	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4741	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	4742	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4743	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
NYX	0:85b3fd62ea1a	4744	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4745	} while(0U)
NYX	0:85b3fd62ea1a	4746	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4747	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4748	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
NYX	0:85b3fd62ea1a	4749	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4750	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
NYX	0:85b3fd62ea1a	4751	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4752	} while(0U)
NYX	0:85b3fd62ea1a	4753	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4754	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4755	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
NYX	0:85b3fd62ea1a	4756	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4757	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
NYX	0:85b3fd62ea1a	4758	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4759	} while(0U)
NYX	0:85b3fd62ea1a	4760	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4761	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4762	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	4763	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4764	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
NYX	0:85b3fd62ea1a	4765	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4766	} while(0U)
NYX	0:85b3fd62ea1a	4767
NYX	0:85b3fd62ea1a	4768	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
NYX	0:85b3fd62ea1a	4769	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
NYX	0:85b3fd62ea1a	4770	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
NYX	0:85b3fd62ea1a	4771	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
NYX	0:85b3fd62ea1a	4772	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
NYX	0:85b3fd62ea1a	4773	/**
NYX	0:85b3fd62ea1a	4774	* @}
NYX	0:85b3fd62ea1a	4775	*/
NYX	0:85b3fd62ea1a	4776
NYX	0:85b3fd62ea1a	4777	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	4778	* @brief Get the enable or disable status of the AHB1 peripheral clock.
NYX	0:85b3fd62ea1a	4779	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4780	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4781	* using it.
NYX	0:85b3fd62ea1a	4782	* @{
NYX	0:85b3fd62ea1a	4783	*/
NYX	0:85b3fd62ea1a	4784	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
NYX	0:85b3fd62ea1a	4785	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
NYX	0:85b3fd62ea1a	4786	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
NYX	0:85b3fd62ea1a	4787	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
NYX	0:85b3fd62ea1a	4788	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
NYX	0:85b3fd62ea1a	4789
NYX	0:85b3fd62ea1a	4790	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
NYX	0:85b3fd62ea1a	4791	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
NYX	0:85b3fd62ea1a	4792	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
NYX	0:85b3fd62ea1a	4793	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
NYX	0:85b3fd62ea1a	4794	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
NYX	0:85b3fd62ea1a	4795	/**
NYX	0:85b3fd62ea1a	4796	* @}
NYX	0:85b3fd62ea1a	4797	*/
NYX	0:85b3fd62ea1a	4798
NYX	0:85b3fd62ea1a	4799	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	4800	* @brief Enable or disable the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	4801	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4802	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4803	* using it.
NYX	0:85b3fd62ea1a	4804	* @{
NYX	0:85b3fd62ea1a	4805	*/
NYX	0:85b3fd62ea1a	4806	#if defined(STM32F423xx)
NYX	0:85b3fd62ea1a	4807	#define __HAL_RCC_AES_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4808	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4809	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
NYX	0:85b3fd62ea1a	4810	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4811	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
NYX	0:85b3fd62ea1a	4812	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4813	} while(0U)
NYX	0:85b3fd62ea1a	4814
NYX	0:85b3fd62ea1a	4815	#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
NYX	0:85b3fd62ea1a	4816	#endif /* STM32F423xx */
NYX	0:85b3fd62ea1a	4817
NYX	0:85b3fd62ea1a	4818	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4819	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4820	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
NYX	0:85b3fd62ea1a	4821	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4822	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
NYX	0:85b3fd62ea1a	4823	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4824	} while(0U)
NYX	0:85b3fd62ea1a	4825	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
NYX	0:85b3fd62ea1a	4826
NYX	0:85b3fd62ea1a	4827	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
NYX	0:85b3fd62ea1a	4828	__HAL_RCC_SYSCFG_CLK_ENABLE();\
NYX	0:85b3fd62ea1a	4829	}while(0U)
NYX	0:85b3fd62ea1a	4830
NYX	0:85b3fd62ea1a	4831	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
NYX	0:85b3fd62ea1a	4832	/**
NYX	0:85b3fd62ea1a	4833	* @}
NYX	0:85b3fd62ea1a	4834	*/
NYX	0:85b3fd62ea1a	4835
NYX	0:85b3fd62ea1a	4836	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	4837	* @brief Get the enable or disable status of the AHB2 peripheral clock.
NYX	0:85b3fd62ea1a	4838	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4839	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4840	* using it.
NYX	0:85b3fd62ea1a	4841	* @{
NYX	0:85b3fd62ea1a	4842	*/
NYX	0:85b3fd62ea1a	4843	#if defined(STM32F423xx)
NYX	0:85b3fd62ea1a	4844	#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
NYX	0:85b3fd62ea1a	4845	#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
NYX	0:85b3fd62ea1a	4846	#endif /* STM32F423xx */
NYX	0:85b3fd62ea1a	4847
NYX	0:85b3fd62ea1a	4848	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
NYX	0:85b3fd62ea1a	4849	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
NYX	0:85b3fd62ea1a	4850
NYX	0:85b3fd62ea1a	4851	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
NYX	0:85b3fd62ea1a	4852	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
NYX	0:85b3fd62ea1a	4853	/**
NYX	0:85b3fd62ea1a	4854	* @}
NYX	0:85b3fd62ea1a	4855	*/
NYX	0:85b3fd62ea1a	4856
NYX	0:85b3fd62ea1a	4857	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	4858	* @brief Enables or disables the AHB3 peripheral clock.
NYX	0:85b3fd62ea1a	4859	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4860	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4861	* using it.
NYX	0:85b3fd62ea1a	4862	* @{
NYX	0:85b3fd62ea1a	4863	*/
NYX	0:85b3fd62ea1a	4864	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	4865	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4866	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4867	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
NYX	0:85b3fd62ea1a	4868	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4869	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
NYX	0:85b3fd62ea1a	4870	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4871	} while(0U)
NYX	0:85b3fd62ea1a	4872	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4873	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4874	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
NYX	0:85b3fd62ea1a	4875	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4876	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
NYX	0:85b3fd62ea1a	4877	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4878	} while(0U)
NYX	0:85b3fd62ea1a	4879
NYX	0:85b3fd62ea1a	4880	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
NYX	0:85b3fd62ea1a	4881	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
NYX	0:85b3fd62ea1a	4882	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	4883	/**
NYX	0:85b3fd62ea1a	4884	* @}
NYX	0:85b3fd62ea1a	4885	*/
NYX	0:85b3fd62ea1a	4886
NYX	0:85b3fd62ea1a	4887	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	4888	* @brief Get the enable or disable status of the AHB3 peripheral clock.
NYX	0:85b3fd62ea1a	4889	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4890	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4891	* using it.
NYX	0:85b3fd62ea1a	4892	* @{
NYX	0:85b3fd62ea1a	4893	*/
NYX	0:85b3fd62ea1a	4894	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	4895	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
NYX	0:85b3fd62ea1a	4896	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
NYX	0:85b3fd62ea1a	4897
NYX	0:85b3fd62ea1a	4898	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
NYX	0:85b3fd62ea1a	4899	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
NYX	0:85b3fd62ea1a	4900	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	4901
NYX	0:85b3fd62ea1a	4902	/**
NYX	0:85b3fd62ea1a	4903	* @}
NYX	0:85b3fd62ea1a	4904	*/
NYX	0:85b3fd62ea1a	4905
NYX	0:85b3fd62ea1a	4906	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	4907	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
NYX	0:85b3fd62ea1a	4908	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	4909	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	4910	* using it.
NYX	0:85b3fd62ea1a	4911	* @{
NYX	0:85b3fd62ea1a	4912	*/
NYX	0:85b3fd62ea1a	4913	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4914	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4915	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	4916	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4917	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
NYX	0:85b3fd62ea1a	4918	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4919	} while(0U)
NYX	0:85b3fd62ea1a	4920	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4921	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4922	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
NYX	0:85b3fd62ea1a	4923	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4924	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
NYX	0:85b3fd62ea1a	4925	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4926	} while(0U)
NYX	0:85b3fd62ea1a	4927	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4928	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4929	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
NYX	0:85b3fd62ea1a	4930	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4931	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
NYX	0:85b3fd62ea1a	4932	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4933	} while(0U)
NYX	0:85b3fd62ea1a	4934	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4935	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4936	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
NYX	0:85b3fd62ea1a	4937	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4938	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
NYX	0:85b3fd62ea1a	4939	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4940	} while(0U)
NYX	0:85b3fd62ea1a	4941	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4942	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4943	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	4944	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4945	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
NYX	0:85b3fd62ea1a	4946	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4947	} while(0U)
NYX	0:85b3fd62ea1a	4948	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	4949	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4950	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4951	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
NYX	0:85b3fd62ea1a	4952	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4953	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
NYX	0:85b3fd62ea1a	4954	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4955	} while(0U)
NYX	0:85b3fd62ea1a	4956	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	4957	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4958	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4959	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
NYX	0:85b3fd62ea1a	4960	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4961	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
NYX	0:85b3fd62ea1a	4962	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4963	} while(0U)
NYX	0:85b3fd62ea1a	4964	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	4965	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4966	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4967	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
NYX	0:85b3fd62ea1a	4968	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4969	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
NYX	0:85b3fd62ea1a	4970	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4971	} while(0U)
NYX	0:85b3fd62ea1a	4972	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	4973
NYX	0:85b3fd62ea1a	4974	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	4975	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4976	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4977	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
NYX	0:85b3fd62ea1a	4978	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4979	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
NYX	0:85b3fd62ea1a	4980	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4981	} while(0U)
NYX	0:85b3fd62ea1a	4982	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4983	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4984	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
NYX	0:85b3fd62ea1a	4985	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4986	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
NYX	0:85b3fd62ea1a	4987	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4988	} while(0U)
NYX	0:85b3fd62ea1a	4989	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	4990
NYX	0:85b3fd62ea1a	4991	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4992	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	4993	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
NYX	0:85b3fd62ea1a	4994	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	4995	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
NYX	0:85b3fd62ea1a	4996	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	4997	} while(0U)
NYX	0:85b3fd62ea1a	4998	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	4999	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5000	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
NYX	0:85b3fd62ea1a	5001	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5002	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
NYX	0:85b3fd62ea1a	5003	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5004	} while(0U)
NYX	0:85b3fd62ea1a	5005	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5006	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5007	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
NYX	0:85b3fd62ea1a	5008	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5009	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
NYX	0:85b3fd62ea1a	5010	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5011	} while(0U)
NYX	0:85b3fd62ea1a	5012	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5013	#define __HAL_RCC_CAN3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5014	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5015	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
NYX	0:85b3fd62ea1a	5016	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5017	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
NYX	0:85b3fd62ea1a	5018	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5019	} while(0U)
NYX	0:85b3fd62ea1a	5020	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5021	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5022	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5023	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	5024	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5025	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
NYX	0:85b3fd62ea1a	5026	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5027	} while(0U)
NYX	0:85b3fd62ea1a	5028	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5029	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5030	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	5031	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5032	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
NYX	0:85b3fd62ea1a	5033	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5034	} while(0U)
NYX	0:85b3fd62ea1a	5035	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5036	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5037	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	5038	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5039	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
NYX	0:85b3fd62ea1a	5040	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5041	} while(0U)
NYX	0:85b3fd62ea1a	5042	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5043	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5044	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	5045	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5046	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
NYX	0:85b3fd62ea1a	5047	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5048	} while(0U)
NYX	0:85b3fd62ea1a	5049	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5050	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5051	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	5052	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5053	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
NYX	0:85b3fd62ea1a	5054	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5055	} while(0U)
NYX	0:85b3fd62ea1a	5056	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5057	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5058	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5059	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	5060	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5061	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
NYX	0:85b3fd62ea1a	5062	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5063	} while(0U)
NYX	0:85b3fd62ea1a	5064	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5065	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5066	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
NYX	0:85b3fd62ea1a	5067	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5068	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
NYX	0:85b3fd62ea1a	5069	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5070	} while(0U)
NYX	0:85b3fd62ea1a	5071	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5072	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5073	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
NYX	0:85b3fd62ea1a	5074	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5075	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
NYX	0:85b3fd62ea1a	5076	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5077	} while(0U)
NYX	0:85b3fd62ea1a	5078	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5079
NYX	0:85b3fd62ea1a	5080	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
NYX	0:85b3fd62ea1a	5081	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
NYX	0:85b3fd62ea1a	5082	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
NYX	0:85b3fd62ea1a	5083	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
NYX	0:85b3fd62ea1a	5084	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
NYX	0:85b3fd62ea1a	5085	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
NYX	0:85b3fd62ea1a	5086	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
NYX	0:85b3fd62ea1a	5087	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
NYX	0:85b3fd62ea1a	5088	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5089	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
NYX	0:85b3fd62ea1a	5090	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5091	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
NYX	0:85b3fd62ea1a	5092	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
NYX	0:85b3fd62ea1a	5093	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5094	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
NYX	0:85b3fd62ea1a	5095	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5096	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5097	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
NYX	0:85b3fd62ea1a	5098	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
NYX	0:85b3fd62ea1a	5099	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5100	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
NYX	0:85b3fd62ea1a	5101	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
NYX	0:85b3fd62ea1a	5102	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
NYX	0:85b3fd62ea1a	5103	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
NYX	0:85b3fd62ea1a	5104	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5105	#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
NYX	0:85b3fd62ea1a	5106	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
NYX	0:85b3fd62ea1a	5107	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
NYX	0:85b3fd62ea1a	5108	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
NYX	0:85b3fd62ea1a	5109	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5110
NYX	0:85b3fd62ea1a	5111	/**
NYX	0:85b3fd62ea1a	5112	* @}
NYX	0:85b3fd62ea1a	5113	*/
NYX	0:85b3fd62ea1a	5114
NYX	0:85b3fd62ea1a	5115	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	5116	* @brief Get the enable or disable status of the APB1 peripheral clock.
NYX	0:85b3fd62ea1a	5117	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	5118	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	5119	* using it.
NYX	0:85b3fd62ea1a	5120	* @{
NYX	0:85b3fd62ea1a	5121	*/
NYX	0:85b3fd62ea1a	5122	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
NYX	0:85b3fd62ea1a	5123	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
NYX	0:85b3fd62ea1a	5124	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
NYX	0:85b3fd62ea1a	5125	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
NYX	0:85b3fd62ea1a	5126	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
NYX	0:85b3fd62ea1a	5127	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
NYX	0:85b3fd62ea1a	5128	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
NYX	0:85b3fd62ea1a	5129	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
NYX	0:85b3fd62ea1a	5130	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5131	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
NYX	0:85b3fd62ea1a	5132	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5133	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
NYX	0:85b3fd62ea1a	5134	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
NYX	0:85b3fd62ea1a	5135	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5136	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
NYX	0:85b3fd62ea1a	5137	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
NYX	0:85b3fd62ea1a	5138	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5139	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
NYX	0:85b3fd62ea1a	5140	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
NYX	0:85b3fd62ea1a	5141	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5142	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
NYX	0:85b3fd62ea1a	5143	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
NYX	0:85b3fd62ea1a	5144	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
NYX	0:85b3fd62ea1a	5145	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
NYX	0:85b3fd62ea1a	5146	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5147	#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
NYX	0:85b3fd62ea1a	5148	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
NYX	0:85b3fd62ea1a	5149	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
NYX	0:85b3fd62ea1a	5150	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
NYX	0:85b3fd62ea1a	5151	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5152
NYX	0:85b3fd62ea1a	5153	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
NYX	0:85b3fd62ea1a	5154	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
NYX	0:85b3fd62ea1a	5155	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
NYX	0:85b3fd62ea1a	5156	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
NYX	0:85b3fd62ea1a	5157	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
NYX	0:85b3fd62ea1a	5158	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
NYX	0:85b3fd62ea1a	5159	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
NYX	0:85b3fd62ea1a	5160	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
NYX	0:85b3fd62ea1a	5161	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5162	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
NYX	0:85b3fd62ea1a	5163	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5164	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
NYX	0:85b3fd62ea1a	5165	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
NYX	0:85b3fd62ea1a	5166	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5167	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
NYX	0:85b3fd62ea1a	5168	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
NYX	0:85b3fd62ea1a	5169	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5170	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
NYX	0:85b3fd62ea1a	5171	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
NYX	0:85b3fd62ea1a	5172	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5173	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
NYX	0:85b3fd62ea1a	5174	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
NYX	0:85b3fd62ea1a	5175	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
NYX	0:85b3fd62ea1a	5176	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
NYX	0:85b3fd62ea1a	5177	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5178	#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
NYX	0:85b3fd62ea1a	5179	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
NYX	0:85b3fd62ea1a	5180	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
NYX	0:85b3fd62ea1a	5181	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
NYX	0:85b3fd62ea1a	5182	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5183	/**
NYX	0:85b3fd62ea1a	5184	* @}
NYX	0:85b3fd62ea1a	5185	*/
NYX	0:85b3fd62ea1a	5186	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
NYX	0:85b3fd62ea1a	5187	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
NYX	0:85b3fd62ea1a	5188	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	5189	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	5190	* using it.
NYX	0:85b3fd62ea1a	5191	* @{
NYX	0:85b3fd62ea1a	5192	*/
NYX	0:85b3fd62ea1a	5193	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5194	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5195	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
NYX	0:85b3fd62ea1a	5196	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5197	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
NYX	0:85b3fd62ea1a	5198	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5199	} while(0U)
NYX	0:85b3fd62ea1a	5200	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5201	#define __HAL_RCC_UART9_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5202	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5203	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
NYX	0:85b3fd62ea1a	5204	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5205	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
NYX	0:85b3fd62ea1a	5206	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5207	} while(0U)
NYX	0:85b3fd62ea1a	5208	#define __HAL_RCC_UART10_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5209	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5210	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
NYX	0:85b3fd62ea1a	5211	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5212	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
NYX	0:85b3fd62ea1a	5213	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5214	} while(0U)
NYX	0:85b3fd62ea1a	5215	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5216	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5217	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5218	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	5219	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5220	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
NYX	0:85b3fd62ea1a	5221	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5222	} while(0U)
NYX	0:85b3fd62ea1a	5223	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5224	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5225	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	5226	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5227	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
NYX	0:85b3fd62ea1a	5228	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5229	} while(0U)
NYX	0:85b3fd62ea1a	5230	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5231	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5232	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
NYX	0:85b3fd62ea1a	5233	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5234	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
NYX	0:85b3fd62ea1a	5235	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5236	} while(0U)
NYX	0:85b3fd62ea1a	5237	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5238	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5239	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	5240	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5241	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
NYX	0:85b3fd62ea1a	5242	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5243	} while(0U)
NYX	0:85b3fd62ea1a	5244	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5245	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5246	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
NYX	0:85b3fd62ea1a	5247	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5248	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
NYX	0:85b3fd62ea1a	5249	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5250	} while(0U)
NYX	0:85b3fd62ea1a	5251	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5252	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5253	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5254	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
NYX	0:85b3fd62ea1a	5255	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5256	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
NYX	0:85b3fd62ea1a	5257	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5258	} while(0U)
NYX	0:85b3fd62ea1a	5259	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5260	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5261	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5262	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
NYX	0:85b3fd62ea1a	5263	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5264	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
NYX	0:85b3fd62ea1a	5265	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5266	} while(0U)
NYX	0:85b3fd62ea1a	5267	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5268	#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
NYX	0:85b3fd62ea1a	5269	__IO uint32_t tmpreg = 0x00U; \
NYX	0:85b3fd62ea1a	5270	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
NYX	0:85b3fd62ea1a	5271	/* Delay after an RCC peripheral clock enabling */ \
NYX	0:85b3fd62ea1a	5272	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
NYX	0:85b3fd62ea1a	5273	UNUSED(tmpreg); \
NYX	0:85b3fd62ea1a	5274	} while(0U)
NYX	0:85b3fd62ea1a	5275	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5276
NYX	0:85b3fd62ea1a	5277	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
NYX	0:85b3fd62ea1a	5278	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5279	#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
NYX	0:85b3fd62ea1a	5280	#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))
NYX	0:85b3fd62ea1a	5281	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5282	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
NYX	0:85b3fd62ea1a	5283	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
NYX	0:85b3fd62ea1a	5284	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
NYX	0:85b3fd62ea1a	5285	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
NYX	0:85b3fd62ea1a	5286	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
NYX	0:85b3fd62ea1a	5287	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5288	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
NYX	0:85b3fd62ea1a	5289	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5290	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
NYX	0:85b3fd62ea1a	5291	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5292	#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))
NYX	0:85b3fd62ea1a	5293	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5294	/**
NYX	0:85b3fd62ea1a	5295	* @}
NYX	0:85b3fd62ea1a	5296	*/
NYX	0:85b3fd62ea1a	5297
NYX	0:85b3fd62ea1a	5298	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
NYX	0:85b3fd62ea1a	5299	* @brief Get the enable or disable status of the APB2 peripheral clock.
NYX	0:85b3fd62ea1a	5300	* @note After reset, the peripheral clock (used for registers read/write access)
NYX	0:85b3fd62ea1a	5301	* is disabled and the application software has to enable this clock before
NYX	0:85b3fd62ea1a	5302	* using it.
NYX	0:85b3fd62ea1a	5303	* @{
NYX	0:85b3fd62ea1a	5304	*/
NYX	0:85b3fd62ea1a	5305	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
NYX	0:85b3fd62ea1a	5306	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5307	#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
NYX	0:85b3fd62ea1a	5308	#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)
NYX	0:85b3fd62ea1a	5309	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5310	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
NYX	0:85b3fd62ea1a	5311	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
NYX	0:85b3fd62ea1a	5312	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
NYX	0:85b3fd62ea1a	5313	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
NYX	0:85b3fd62ea1a	5314	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
NYX	0:85b3fd62ea1a	5315	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5316	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
NYX	0:85b3fd62ea1a	5317	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5318	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
NYX	0:85b3fd62ea1a	5319	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5320	#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)
NYX	0:85b3fd62ea1a	5321	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5322
NYX	0:85b3fd62ea1a	5323	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
NYX	0:85b3fd62ea1a	5324	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5325	#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET)
NYX	0:85b3fd62ea1a	5326	#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)
NYX	0:85b3fd62ea1a	5327	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5328	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
NYX	0:85b3fd62ea1a	5329	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
NYX	0:85b3fd62ea1a	5330	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
NYX	0:85b3fd62ea1a	5331	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
NYX	0:85b3fd62ea1a	5332	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
NYX	0:85b3fd62ea1a	5333	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5334	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
NYX	0:85b3fd62ea1a	5335	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5336	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
NYX	0:85b3fd62ea1a	5337	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5338	#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)
NYX	0:85b3fd62ea1a	5339	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5340	/**
NYX	0:85b3fd62ea1a	5341	* @}
NYX	0:85b3fd62ea1a	5342	*/
NYX	0:85b3fd62ea1a	5343
NYX	0:85b3fd62ea1a	5344	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
NYX	0:85b3fd62ea1a	5345	* @brief Force or release AHB1 peripheral reset.
NYX	0:85b3fd62ea1a	5346	* @{
NYX	0:85b3fd62ea1a	5347	*/
NYX	0:85b3fd62ea1a	5348	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	5349	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	5350	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
NYX	0:85b3fd62ea1a	5351	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
NYX	0:85b3fd62ea1a	5352	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	5353
NYX	0:85b3fd62ea1a	5354	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
NYX	0:85b3fd62ea1a	5355	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
NYX	0:85b3fd62ea1a	5356	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
NYX	0:85b3fd62ea1a	5357	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
NYX	0:85b3fd62ea1a	5358	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
NYX	0:85b3fd62ea1a	5359	/**
NYX	0:85b3fd62ea1a	5360	* @}
NYX	0:85b3fd62ea1a	5361	*/
NYX	0:85b3fd62ea1a	5362
NYX	0:85b3fd62ea1a	5363	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
NYX	0:85b3fd62ea1a	5364	* @brief Force or release AHB2 peripheral reset.
NYX	0:85b3fd62ea1a	5365	* @{
NYX	0:85b3fd62ea1a	5366	*/
NYX	0:85b3fd62ea1a	5367	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	5368	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
NYX	0:85b3fd62ea1a	5369
NYX	0:85b3fd62ea1a	5370	#if defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5371	#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_AESRST))
NYX	0:85b3fd62ea1a	5372	#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
NYX	0:85b3fd62ea1a	5373	#endif /* STM32F423xx */
NYX	0:85b3fd62ea1a	5374
NYX	0:85b3fd62ea1a	5375	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	5376	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
NYX	0:85b3fd62ea1a	5377
NYX	0:85b3fd62ea1a	5378	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
NYX	0:85b3fd62ea1a	5379	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
NYX	0:85b3fd62ea1a	5380	/**
NYX	0:85b3fd62ea1a	5381	* @}
NYX	0:85b3fd62ea1a	5382	*/
NYX	0:85b3fd62ea1a	5383
NYX	0:85b3fd62ea1a	5384	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
NYX	0:85b3fd62ea1a	5385	* @brief Force or release AHB3 peripheral reset.
NYX	0:85b3fd62ea1a	5386	* @{
NYX	0:85b3fd62ea1a	5387	*/
NYX	0:85b3fd62ea1a	5388	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5389	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
NYX	0:85b3fd62ea1a	5390	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
NYX	0:85b3fd62ea1a	5391
NYX	0:85b3fd62ea1a	5392	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
NYX	0:85b3fd62ea1a	5393	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
NYX	0:85b3fd62ea1a	5394
NYX	0:85b3fd62ea1a	5395	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
NYX	0:85b3fd62ea1a	5396	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
NYX	0:85b3fd62ea1a	5397	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5398	#if defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	5399	#define __HAL_RCC_AHB3_FORCE_RESET()
NYX	0:85b3fd62ea1a	5400	#define __HAL_RCC_AHB3_RELEASE_RESET()
NYX	0:85b3fd62ea1a	5401
NYX	0:85b3fd62ea1a	5402	#define __HAL_RCC_FSMC_FORCE_RESET()
NYX	0:85b3fd62ea1a	5403	#define __HAL_RCC_QSPI_FORCE_RESET()
NYX	0:85b3fd62ea1a	5404
NYX	0:85b3fd62ea1a	5405	#define __HAL_RCC_FSMC_RELEASE_RESET()
NYX	0:85b3fd62ea1a	5406	#define __HAL_RCC_QSPI_RELEASE_RESET()
NYX	0:85b3fd62ea1a	5407	#endif /* STM32F412Cx */
NYX	0:85b3fd62ea1a	5408	/**
NYX	0:85b3fd62ea1a	5409	* @}
NYX	0:85b3fd62ea1a	5410	*/
NYX	0:85b3fd62ea1a	5411
NYX	0:85b3fd62ea1a	5412	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
NYX	0:85b3fd62ea1a	5413	* @brief Force or release APB1 peripheral reset.
NYX	0:85b3fd62ea1a	5414	* @{
NYX	0:85b3fd62ea1a	5415	*/
NYX	0:85b3fd62ea1a	5416	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	5417	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	5418	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	5419	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	5420	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
NYX	0:85b3fd62ea1a	5421	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
NYX	0:85b3fd62ea1a	5422	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
NYX	0:85b3fd62ea1a	5423	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
NYX	0:85b3fd62ea1a	5424	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5425	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
NYX	0:85b3fd62ea1a	5426	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5427	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	5428	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5429	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
NYX	0:85b3fd62ea1a	5430	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5431	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5432	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
NYX	0:85b3fd62ea1a	5433	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
NYX	0:85b3fd62ea1a	5434	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5435	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	5436	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
NYX	0:85b3fd62ea1a	5437	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
NYX	0:85b3fd62ea1a	5438	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
NYX	0:85b3fd62ea1a	5439	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5440	#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN3RST))
NYX	0:85b3fd62ea1a	5441	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	5442	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
NYX	0:85b3fd62ea1a	5443	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
NYX	0:85b3fd62ea1a	5444	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5445
NYX	0:85b3fd62ea1a	5446	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
NYX	0:85b3fd62ea1a	5447	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
NYX	0:85b3fd62ea1a	5448	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
NYX	0:85b3fd62ea1a	5449	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
NYX	0:85b3fd62ea1a	5450	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
NYX	0:85b3fd62ea1a	5451	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
NYX	0:85b3fd62ea1a	5452	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
NYX	0:85b3fd62ea1a	5453	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
NYX	0:85b3fd62ea1a	5454	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5455	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
NYX	0:85b3fd62ea1a	5456	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5457	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
NYX	0:85b3fd62ea1a	5458	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5459	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
NYX	0:85b3fd62ea1a	5460	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5461	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5462	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
NYX	0:85b3fd62ea1a	5463	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
NYX	0:85b3fd62ea1a	5464	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5465	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
NYX	0:85b3fd62ea1a	5466	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
NYX	0:85b3fd62ea1a	5467	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
NYX	0:85b3fd62ea1a	5468	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
NYX	0:85b3fd62ea1a	5469	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5470	#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
NYX	0:85b3fd62ea1a	5471	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
NYX	0:85b3fd62ea1a	5472	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
NYX	0:85b3fd62ea1a	5473	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
NYX	0:85b3fd62ea1a	5474	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5475	/**
NYX	0:85b3fd62ea1a	5476	* @}
NYX	0:85b3fd62ea1a	5477	*/
NYX	0:85b3fd62ea1a	5478
NYX	0:85b3fd62ea1a	5479	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
NYX	0:85b3fd62ea1a	5480	* @brief Force or release APB2 peripheral reset.
NYX	0:85b3fd62ea1a	5481	* @{
NYX	0:85b3fd62ea1a	5482	*/
NYX	0:85b3fd62ea1a	5483	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
NYX	0:85b3fd62ea1a	5484	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5485	#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART9RST))
NYX	0:85b3fd62ea1a	5486	#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART10RST))
NYX	0:85b3fd62ea1a	5487	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5488	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	5489	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	5490	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	5491	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
NYX	0:85b3fd62ea1a	5492	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5493	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
NYX	0:85b3fd62ea1a	5494	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5495	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
NYX	0:85b3fd62ea1a	5496	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5497	#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM2RST))
NYX	0:85b3fd62ea1a	5498	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5499
NYX	0:85b3fd62ea1a	5500	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
NYX	0:85b3fd62ea1a	5501	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5502	#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
NYX	0:85b3fd62ea1a	5503	#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))
NYX	0:85b3fd62ea1a	5504	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5505	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
NYX	0:85b3fd62ea1a	5506	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
NYX	0:85b3fd62ea1a	5507	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
NYX	0:85b3fd62ea1a	5508	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
NYX	0:85b3fd62ea1a	5509	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5510	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
NYX	0:85b3fd62ea1a	5511	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5512	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
NYX	0:85b3fd62ea1a	5513	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5514	#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
NYX	0:85b3fd62ea1a	5515	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5516	/**
NYX	0:85b3fd62ea1a	5517	* @}
NYX	0:85b3fd62ea1a	5518	*/
NYX	0:85b3fd62ea1a	5519
NYX	0:85b3fd62ea1a	5520	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	5521	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	5522	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	5523	* power consumption.
NYX	0:85b3fd62ea1a	5524	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	5525	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	5526	* @{
NYX	0:85b3fd62ea1a	5527	*/
NYX	0:85b3fd62ea1a	5528	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	5529	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	5530	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
NYX	0:85b3fd62ea1a	5531	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
NYX	0:85b3fd62ea1a	5532	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	5533	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	5534	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	5535	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5536	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
NYX	0:85b3fd62ea1a	5537	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5538
NYX	0:85b3fd62ea1a	5539	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
NYX	0:85b3fd62ea1a	5540	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
NYX	0:85b3fd62ea1a	5541	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
NYX	0:85b3fd62ea1a	5542	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
NYX	0:85b3fd62ea1a	5543	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
NYX	0:85b3fd62ea1a	5544	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
NYX	0:85b3fd62ea1a	5545	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
NYX	0:85b3fd62ea1a	5546	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5547	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
NYX	0:85b3fd62ea1a	5548	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5549	/**
NYX	0:85b3fd62ea1a	5550	* @}
NYX	0:85b3fd62ea1a	5551	*/
NYX	0:85b3fd62ea1a	5552
NYX	0:85b3fd62ea1a	5553	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	5554	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	5555	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	5556	* power consumption.
NYX	0:85b3fd62ea1a	5557	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	5558	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	5559	* @{
NYX	0:85b3fd62ea1a	5560	*/
NYX	0:85b3fd62ea1a	5561	#if defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5562	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AESLPEN))
NYX	0:85b3fd62ea1a	5563	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
NYX	0:85b3fd62ea1a	5564	#endif /* STM32F423xx */
NYX	0:85b3fd62ea1a	5565
NYX	0:85b3fd62ea1a	5566	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	5567	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
NYX	0:85b3fd62ea1a	5568
NYX	0:85b3fd62ea1a	5569	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	5570	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
NYX	0:85b3fd62ea1a	5571	/**
NYX	0:85b3fd62ea1a	5572	* @}
NYX	0:85b3fd62ea1a	5573	*/
NYX	0:85b3fd62ea1a	5574
NYX	0:85b3fd62ea1a	5575	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	5576	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	5577	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	5578	* power consumption.
NYX	0:85b3fd62ea1a	5579	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	5580	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	5581	* @{
NYX	0:85b3fd62ea1a	5582	*/
NYX	0:85b3fd62ea1a	5583	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5584	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
NYX	0:85b3fd62ea1a	5585	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
NYX	0:85b3fd62ea1a	5586
NYX	0:85b3fd62ea1a	5587	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
NYX	0:85b3fd62ea1a	5588	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
NYX	0:85b3fd62ea1a	5589	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5590
NYX	0:85b3fd62ea1a	5591	/**
NYX	0:85b3fd62ea1a	5592	* @}
NYX	0:85b3fd62ea1a	5593	*/
NYX	0:85b3fd62ea1a	5594
NYX	0:85b3fd62ea1a	5595	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	5596	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	5597	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	5598	* power consumption.
NYX	0:85b3fd62ea1a	5599	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	5600	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	5601	* @{
NYX	0:85b3fd62ea1a	5602	*/
NYX	0:85b3fd62ea1a	5603	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	5604	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	5605	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	5606	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	5607	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
NYX	0:85b3fd62ea1a	5608	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
NYX	0:85b3fd62ea1a	5609	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
NYX	0:85b3fd62ea1a	5610	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
NYX	0:85b3fd62ea1a	5611	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5612	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
NYX	0:85b3fd62ea1a	5613	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5614	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
NYX	0:85b3fd62ea1a	5615	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	5616	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5617	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
NYX	0:85b3fd62ea1a	5618	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5619	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5620	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
NYX	0:85b3fd62ea1a	5621	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
NYX	0:85b3fd62ea1a	5622	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5623	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	5624	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
NYX	0:85b3fd62ea1a	5625	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
NYX	0:85b3fd62ea1a	5626	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
NYX	0:85b3fd62ea1a	5627	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5628	#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN3LPEN))
NYX	0:85b3fd62ea1a	5629	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	5630	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
NYX	0:85b3fd62ea1a	5631	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
NYX	0:85b3fd62ea1a	5632	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5633
NYX	0:85b3fd62ea1a	5634	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
NYX	0:85b3fd62ea1a	5635	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
NYX	0:85b3fd62ea1a	5636	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
NYX	0:85b3fd62ea1a	5637	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
NYX	0:85b3fd62ea1a	5638	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
NYX	0:85b3fd62ea1a	5639	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
NYX	0:85b3fd62ea1a	5640	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
NYX	0:85b3fd62ea1a	5641	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
NYX	0:85b3fd62ea1a	5642	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5643	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
NYX	0:85b3fd62ea1a	5644	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5645	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
NYX	0:85b3fd62ea1a	5646	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
NYX	0:85b3fd62ea1a	5647	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5648	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
NYX	0:85b3fd62ea1a	5649	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5650	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5651	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
NYX	0:85b3fd62ea1a	5652	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
NYX	0:85b3fd62ea1a	5653	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5654	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
NYX	0:85b3fd62ea1a	5655	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
NYX	0:85b3fd62ea1a	5656	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
NYX	0:85b3fd62ea1a	5657	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
NYX	0:85b3fd62ea1a	5658	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5659	#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
NYX	0:85b3fd62ea1a	5660	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
NYX	0:85b3fd62ea1a	5661	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
NYX	0:85b3fd62ea1a	5662	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
NYX	0:85b3fd62ea1a	5663	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5664	/**
NYX	0:85b3fd62ea1a	5665	* @}
NYX	0:85b3fd62ea1a	5666	*/
NYX	0:85b3fd62ea1a	5667
NYX	0:85b3fd62ea1a	5668	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
NYX	0:85b3fd62ea1a	5669	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
NYX	0:85b3fd62ea1a	5670	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX	0:85b3fd62ea1a	5671	* power consumption.
NYX	0:85b3fd62ea1a	5672	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
NYX	0:85b3fd62ea1a	5673	* @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX	0:85b3fd62ea1a	5674	* @{
NYX	0:85b3fd62ea1a	5675	*/
NYX	0:85b3fd62ea1a	5676	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
NYX	0:85b3fd62ea1a	5677	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5678	#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART9LPEN))
NYX	0:85b3fd62ea1a	5679	#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART10LPEN))
NYX	0:85b3fd62ea1a	5680	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5681	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	5682	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	5683	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
NYX	0:85b3fd62ea1a	5684	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	5685	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
NYX	0:85b3fd62ea1a	5686	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5687	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
NYX	0:85b3fd62ea1a	5688	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5689	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
NYX	0:85b3fd62ea1a	5690	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5691	#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM2LPEN))
NYX	0:85b3fd62ea1a	5692	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5693
NYX	0:85b3fd62ea1a	5694	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
NYX	0:85b3fd62ea1a	5695	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5696	#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
NYX	0:85b3fd62ea1a	5697	#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))
NYX	0:85b3fd62ea1a	5698	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5699	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
NYX	0:85b3fd62ea1a	5700	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
NYX	0:85b3fd62ea1a	5701	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
NYX	0:85b3fd62ea1a	5702	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
NYX	0:85b3fd62ea1a	5703	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
NYX	0:85b3fd62ea1a	5704	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5705	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
NYX	0:85b3fd62ea1a	5706	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5707	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
NYX	0:85b3fd62ea1a	5708	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5709	#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
NYX	0:85b3fd62ea1a	5710	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5711	/**
NYX	0:85b3fd62ea1a	5712	* @}
NYX	0:85b3fd62ea1a	5713	*/
NYX	0:85b3fd62ea1a	5714	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	5715	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	5716
NYX	0:85b3fd62ea1a	5717	/------------------------------- PLL Configuration --------------------------/
NYX	0:85b3fd62ea1a	5718	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
NYX	0:85b3fd62ea1a	5719	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
NYX	0:85b3fd62ea1a	5720	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5721	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
NYX	0:85b3fd62ea1a	5722	* @note This function must be used only when the main PLL is disabled.
NYX	0:85b3fd62ea1a	5723	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
NYX	0:85b3fd62ea1a	5724	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5725	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
NYX	0:85b3fd62ea1a	5726	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
NYX	0:85b3fd62ea1a	5727	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
NYX	0:85b3fd62ea1a	5728	* @param __PLLM__: specifies the division factor for PLL VCO input clock
NYX	0:85b3fd62ea1a	5729	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
NYX	0:85b3fd62ea1a	5730	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
NYX	0:85b3fd62ea1a	5731	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
NYX	0:85b3fd62ea1a	5732	* of 2 MHz to limit PLL jitter.
NYX	0:85b3fd62ea1a	5733	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
NYX	0:85b3fd62ea1a	5734	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	5735	* @note You have to set the PLLN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	5736	* output frequency is between 100 and 432 MHz.
NYX	0:85b3fd62ea1a	5737	*
NYX	0:85b3fd62ea1a	5738	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
NYX	0:85b3fd62ea1a	5739	* This parameter must be a number in the range {2, 4, 6, or 8}.
NYX	0:85b3fd62ea1a	5740	*
NYX	0:85b3fd62ea1a	5741	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
NYX	0:85b3fd62ea1a	5742	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	5743	* @note If the USB OTG FS is used in your application, you have to set the
NYX	0:85b3fd62ea1a	5744	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
NYX	0:85b3fd62ea1a	5745	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
NYX	0:85b3fd62ea1a	5746	* correctly.
NYX	0:85b3fd62ea1a	5747	*
NYX	0:85b3fd62ea1a	5748	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
NYX	0:85b3fd62ea1a	5749	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	5750	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
NYX	0:85b3fd62ea1a	5751	STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
NYX	0:85b3fd62ea1a	5752	*
NYX	0:85b3fd62ea1a	5753	*/
NYX	0:85b3fd62ea1a	5754	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
NYX	0:85b3fd62ea1a	5755	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
NYX	0:85b3fd62ea1a	5756	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
NYX	0:85b3fd62ea1a	5757	((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
NYX	0:85b3fd62ea1a	5758	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
NYX	0:85b3fd62ea1a	5759	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
NYX	0:85b3fd62ea1a	5760	#else
NYX	0:85b3fd62ea1a	5761	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
NYX	0:85b3fd62ea1a	5762	* @note This function must be used only when the main PLL is disabled.
NYX	0:85b3fd62ea1a	5763	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
NYX	0:85b3fd62ea1a	5764	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5765	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
NYX	0:85b3fd62ea1a	5766	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
NYX	0:85b3fd62ea1a	5767	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
NYX	0:85b3fd62ea1a	5768	* @param __PLLM__: specifies the division factor for PLL VCO input clock
NYX	0:85b3fd62ea1a	5769	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
NYX	0:85b3fd62ea1a	5770	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
NYX	0:85b3fd62ea1a	5771	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
NYX	0:85b3fd62ea1a	5772	* of 2 MHz to limit PLL jitter.
NYX	0:85b3fd62ea1a	5773	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
NYX	0:85b3fd62ea1a	5774	* This parameter must be a number between Min_Data = 50 and Max_Data = 432
NYX	0:85b3fd62ea1a	5775	* Except for STM32F411xE devices where Min_Data = 192.
NYX	0:85b3fd62ea1a	5776	* @note You have to set the PLLN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	5777	* output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
NYX	0:85b3fd62ea1a	5778	* where frequency is between 192 and 432 MHz.
NYX	0:85b3fd62ea1a	5779	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
NYX	0:85b3fd62ea1a	5780	* This parameter must be a number in the range {2, 4, 6, or 8}.
NYX	0:85b3fd62ea1a	5781	*
NYX	0:85b3fd62ea1a	5782	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
NYX	0:85b3fd62ea1a	5783	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	5784	* @note If the USB OTG FS is used in your application, you have to set the
NYX	0:85b3fd62ea1a	5785	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
NYX	0:85b3fd62ea1a	5786	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
NYX	0:85b3fd62ea1a	5787	* correctly.
NYX	0:85b3fd62ea1a	5788	*
NYX	0:85b3fd62ea1a	5789	*/
NYX	0:85b3fd62ea1a	5790	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
NYX	0:85b3fd62ea1a	5791	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
NYX	0:85b3fd62ea1a	5792	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
NYX	0:85b3fd62ea1a	5793	((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
NYX	0:85b3fd62ea1a	5794	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
NYX	0:85b3fd62ea1a	5795	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	5796	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	5797
NYX	0:85b3fd62ea1a	5798	/----------------------------PLLI2S Configuration ---------------------------/
NYX	0:85b3fd62ea1a	5799	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
NYX	0:85b3fd62ea1a	5800	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
NYX	0:85b3fd62ea1a	5801	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
NYX	0:85b3fd62ea1a	5802	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
NYX	0:85b3fd62ea1a	5803	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5804
NYX	0:85b3fd62ea1a	5805	/** @brief Macros to enable or disable the PLLI2S.
NYX	0:85b3fd62ea1a	5806	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
NYX	0:85b3fd62ea1a	5807	*/
NYX	0:85b3fd62ea1a	5808	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
NYX	0:85b3fd62ea1a	5809	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
NYX	0:85b3fd62ea1a	5810
NYX	0:85b3fd62ea1a	5811	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
NYX	0:85b3fd62ea1a	5812	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
NYX	0:85b3fd62ea1a	5813	STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	5814	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	5815	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
NYX	0:85b3fd62ea1a	5816	* @note This macro must be used only when the PLLI2S is disabled.
NYX	0:85b3fd62ea1a	5817	* @note PLLI2S clock source is common with the main PLL (configured in
NYX	0:85b3fd62ea1a	5818	* HAL_RCC_ClockConfig() API).
NYX	0:85b3fd62ea1a	5819	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
NYX	0:85b3fd62ea1a	5820	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
NYX	0:85b3fd62ea1a	5821	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
NYX	0:85b3fd62ea1a	5822	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
NYX	0:85b3fd62ea1a	5823	* of 1 MHz to limit PLLI2S jitter.
NYX	0:85b3fd62ea1a	5824	*
NYX	0:85b3fd62ea1a	5825	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
NYX	0:85b3fd62ea1a	5826	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	5827	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	5828	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
NYX	0:85b3fd62ea1a	5829	*
NYX	0:85b3fd62ea1a	5830	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
NYX	0:85b3fd62ea1a	5831	* This parameter must be a number in the range {2, 4, 6, or 8}.
NYX	0:85b3fd62ea1a	5832	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
NYX	0:85b3fd62ea1a	5833	*
NYX	0:85b3fd62ea1a	5834	* @param __PLLI2SR__: specifies the division factor for I2S clock
NYX	0:85b3fd62ea1a	5835	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	5836	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
NYX	0:85b3fd62ea1a	5837	* on the I2S clock frequency.
NYX	0:85b3fd62ea1a	5838	*
NYX	0:85b3fd62ea1a	5839	* @param __PLLI2SQ__: specifies the division factor for SAI clock
NYX	0:85b3fd62ea1a	5840	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	5841	*/
NYX	0:85b3fd62ea1a	5842	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
NYX	0:85b3fd62ea1a	5843	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
NYX	0:85b3fd62ea1a	5844	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
NYX	0:85b3fd62ea1a	5845	((((__PLLI2SP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
NYX	0:85b3fd62ea1a	5846	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
NYX	0:85b3fd62ea1a	5847	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
NYX	0:85b3fd62ea1a	5848	#elif defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
NYX	0:85b3fd62ea1a	5849	defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	5850	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
NYX	0:85b3fd62ea1a	5851	* @note This macro must be used only when the PLLI2S is disabled.
NYX	0:85b3fd62ea1a	5852	* @note PLLI2S clock source is common with the main PLL (configured in
NYX	0:85b3fd62ea1a	5853	* HAL_RCC_ClockConfig() API).
NYX	0:85b3fd62ea1a	5854	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
NYX	0:85b3fd62ea1a	5855	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
NYX	0:85b3fd62ea1a	5856	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
NYX	0:85b3fd62ea1a	5857	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
NYX	0:85b3fd62ea1a	5858	* of 1 MHz to limit PLLI2S jitter.
NYX	0:85b3fd62ea1a	5859	*
NYX	0:85b3fd62ea1a	5860	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
NYX	0:85b3fd62ea1a	5861	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	5862	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	5863	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
NYX	0:85b3fd62ea1a	5864	*
NYX	0:85b3fd62ea1a	5865	* @param __PLLI2SR__: specifies the division factor for I2S clock
NYX	0:85b3fd62ea1a	5866	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	5867	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
NYX	0:85b3fd62ea1a	5868	* on the I2S clock frequency.
NYX	0:85b3fd62ea1a	5869	*
NYX	0:85b3fd62ea1a	5870	* @param __PLLI2SQ__: specifies the division factor for SAI clock
NYX	0:85b3fd62ea1a	5871	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	5872	*/
NYX	0:85b3fd62ea1a	5873	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
NYX	0:85b3fd62ea1a	5874	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
NYX	0:85b3fd62ea1a	5875	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
NYX	0:85b3fd62ea1a	5876	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
NYX	0:85b3fd62ea1a	5877	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
NYX	0:85b3fd62ea1a	5878	#else
NYX	0:85b3fd62ea1a	5879	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
NYX	0:85b3fd62ea1a	5880	* @note This macro must be used only when the PLLI2S is disabled.
NYX	0:85b3fd62ea1a	5881	* @note PLLI2S clock source is common with the main PLL (configured in
NYX	0:85b3fd62ea1a	5882	* HAL_RCC_ClockConfig() API).
NYX	0:85b3fd62ea1a	5883	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
NYX	0:85b3fd62ea1a	5884	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	5885	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	5886	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
NYX	0:85b3fd62ea1a	5887	*
NYX	0:85b3fd62ea1a	5888	* @param __PLLI2SR__: specifies the division factor for I2S clock
NYX	0:85b3fd62ea1a	5889	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	5890	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
NYX	0:85b3fd62ea1a	5891	* on the I2S clock frequency.
NYX	0:85b3fd62ea1a	5892	*
NYX	0:85b3fd62ea1a	5893	*/
NYX	0:85b3fd62ea1a	5894	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
NYX	0:85b3fd62ea1a	5895	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
NYX	0:85b3fd62ea1a	5896	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
NYX	0:85b3fd62ea1a	5897	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	5898
NYX	0:85b3fd62ea1a	5899	#if defined(STM32F411xE)
NYX	0:85b3fd62ea1a	5900	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
NYX	0:85b3fd62ea1a	5901	* @note This macro must be used only when the PLLI2S is disabled.
NYX	0:85b3fd62ea1a	5902	* @note This macro must be used only when the PLLI2S is disabled.
NYX	0:85b3fd62ea1a	5903	* @note PLLI2S clock source is common with the main PLL (configured in
NYX	0:85b3fd62ea1a	5904	* HAL_RCC_ClockConfig() API).
NYX	0:85b3fd62ea1a	5905	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
NYX	0:85b3fd62ea1a	5906	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
NYX	0:85b3fd62ea1a	5907	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
NYX	0:85b3fd62ea1a	5908	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
NYX	0:85b3fd62ea1a	5909	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
NYX	0:85b3fd62ea1a	5910	* of 2 MHz to limit PLLI2S jitter.
NYX	0:85b3fd62ea1a	5911	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
NYX	0:85b3fd62ea1a	5912	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
NYX	0:85b3fd62ea1a	5913	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	5914	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
NYX	0:85b3fd62ea1a	5915	* @param __PLLI2SR__: specifies the division factor for I2S clock
NYX	0:85b3fd62ea1a	5916	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	5917	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
NYX	0:85b3fd62ea1a	5918	* on the I2S clock frequency.
NYX	0:85b3fd62ea1a	5919	*/
NYX	0:85b3fd62ea1a	5920	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
NYX	0:85b3fd62ea1a	5921	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
NYX	0:85b3fd62ea1a	5922	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
NYX	0:85b3fd62ea1a	5923	#endif /* STM32F411xE */
NYX	0:85b3fd62ea1a	5924
NYX	0:85b3fd62ea1a	5925	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	5926	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
NYX	0:85b3fd62ea1a	5927	* @note This macro must be used only when the PLLI2S is disabled.
NYX	0:85b3fd62ea1a	5928	* @note PLLI2S clock source is common with the main PLL (configured in
NYX	0:85b3fd62ea1a	5929	* HAL_RCC_ClockConfig() API)
NYX	0:85b3fd62ea1a	5930	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
NYX	0:85b3fd62ea1a	5931	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	5932	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	5933	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
NYX	0:85b3fd62ea1a	5934	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	5935	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	5936	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
NYX	0:85b3fd62ea1a	5937	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
NYX	0:85b3fd62ea1a	5938	* @param __PLLI2SR__: specifies the division factor for I2S clock
NYX	0:85b3fd62ea1a	5939	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	5940	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
NYX	0:85b3fd62ea1a	5941	* on the I2S clock frequency.
NYX	0:85b3fd62ea1a	5942	*/
NYX	0:85b3fd62ea1a	5943	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) \|\
NYX	0:85b3fd62ea1a	5944	((__PLLI2SQ__) << 24U) \|\
NYX	0:85b3fd62ea1a	5945	((__PLLI2SR__) << 28U))
NYX	0:85b3fd62ea1a	5946	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	5947	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	5948
NYX	0:85b3fd62ea1a	5949	/------------------------------ PLLSAI Configuration ------------------------/
NYX	0:85b3fd62ea1a	5950	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	5951	/** @brief Macros to Enable or Disable the PLLISAI.
NYX	0:85b3fd62ea1a	5952	* @note The PLLSAI is only available with STM32F429x/439x Devices.
NYX	0:85b3fd62ea1a	5953	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
NYX	0:85b3fd62ea1a	5954	*/
NYX	0:85b3fd62ea1a	5955	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
NYX	0:85b3fd62ea1a	5956	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
NYX	0:85b3fd62ea1a	5957
NYX	0:85b3fd62ea1a	5958	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	5959	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
NYX	0:85b3fd62ea1a	5960	*
NYX	0:85b3fd62ea1a	5961	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
NYX	0:85b3fd62ea1a	5962	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
NYX	0:85b3fd62ea1a	5963	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
NYX	0:85b3fd62ea1a	5964	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
NYX	0:85b3fd62ea1a	5965	* of 1 MHz to limit PLLI2S jitter.
NYX	0:85b3fd62ea1a	5966	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
NYX	0:85b3fd62ea1a	5967	*
NYX	0:85b3fd62ea1a	5968	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
NYX	0:85b3fd62ea1a	5969	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	5970	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	5971	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
NYX	0:85b3fd62ea1a	5972	*
NYX	0:85b3fd62ea1a	5973	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
NYX	0:85b3fd62ea1a	5974	* This parameter must be a number in the range {2, 4, 6, or 8}.
NYX	0:85b3fd62ea1a	5975	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
NYX	0:85b3fd62ea1a	5976	*
NYX	0:85b3fd62ea1a	5977	* @param __PLLSAIQ__: specifies the division factor for SAI clock
NYX	0:85b3fd62ea1a	5978	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	5979	*
NYX	0:85b3fd62ea1a	5980	* @param __PLLSAIR__: specifies the division factor for LTDC clock
NYX	0:85b3fd62ea1a	5981	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	5982	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
NYX	0:85b3fd62ea1a	5983	*/
NYX	0:85b3fd62ea1a	5984	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
NYX	0:85b3fd62ea1a	5985	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
NYX	0:85b3fd62ea1a	5986	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
NYX	0:85b3fd62ea1a	5987	((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
NYX	0:85b3fd62ea1a	5988	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
NYX	0:85b3fd62ea1a	5989	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	5990
NYX	0:85b3fd62ea1a	5991	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	5992	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
NYX	0:85b3fd62ea1a	5993	*
NYX	0:85b3fd62ea1a	5994	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
NYX	0:85b3fd62ea1a	5995	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	5996	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	5997	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
NYX	0:85b3fd62ea1a	5998	*
NYX	0:85b3fd62ea1a	5999	* @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
NYX	0:85b3fd62ea1a	6000	* This parameter must be a number in the range {2, 4, 6, or 8}.
NYX	0:85b3fd62ea1a	6001	*
NYX	0:85b3fd62ea1a	6002	* @param __PLLSAIQ__: specifies the division factor for SAI clock
NYX	0:85b3fd62ea1a	6003	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	6004	*
NYX	0:85b3fd62ea1a	6005	* @param __PLLSAIR__: specifies the division factor for LTDC clock
NYX	0:85b3fd62ea1a	6006	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	6007	*/
NYX	0:85b3fd62ea1a	6008	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
NYX	0:85b3fd62ea1a	6009	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
NYX	0:85b3fd62ea1a	6010	((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
NYX	0:85b3fd62ea1a	6011	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
NYX	0:85b3fd62ea1a	6012	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
NYX	0:85b3fd62ea1a	6013	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6014
NYX	0:85b3fd62ea1a	6015	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
NYX	0:85b3fd62ea1a	6016	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
NYX	0:85b3fd62ea1a	6017	*
NYX	0:85b3fd62ea1a	6018	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
NYX	0:85b3fd62ea1a	6019	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
NYX	0:85b3fd62ea1a	6020	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
NYX	0:85b3fd62ea1a	6021	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
NYX	0:85b3fd62ea1a	6022	*
NYX	0:85b3fd62ea1a	6023	* @param __PLLSAIQ__: specifies the division factor for SAI clock
NYX	0:85b3fd62ea1a	6024	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
NYX	0:85b3fd62ea1a	6025	*
NYX	0:85b3fd62ea1a	6026	* @param __PLLSAIR__: specifies the division factor for LTDC clock
NYX	0:85b3fd62ea1a	6027	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
NYX	0:85b3fd62ea1a	6028	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
NYX	0:85b3fd62ea1a	6029	*/
NYX	0:85b3fd62ea1a	6030	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
NYX	0:85b3fd62ea1a	6031	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
NYX	0:85b3fd62ea1a	6032	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
NYX	0:85b3fd62ea1a	6033	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
NYX	0:85b3fd62ea1a	6034	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
NYX	0:85b3fd62ea1a	6035
NYX	0:85b3fd62ea1a	6036	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6037	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	6038
NYX	0:85b3fd62ea1a	6039	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
NYX	0:85b3fd62ea1a	6040	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6041	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
NYX	0:85b3fd62ea1a	6042	* @note This function must be called before enabling the PLLI2S.
NYX	0:85b3fd62ea1a	6043	* @param __PLLI2SDivR__: specifies the PLLI2S division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	6044	* This parameter must be a number between 1 and 32.
NYX	0:85b3fd62ea1a	6045	* SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__
NYX	0:85b3fd62ea1a	6046	*/
NYX	0:85b3fd62ea1a	6047	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
NYX	0:85b3fd62ea1a	6048
NYX	0:85b3fd62ea1a	6049	/** @brief Macro to configure the SAI clock Divider coming from PLL.
NYX	0:85b3fd62ea1a	6050	* @param __PLLDivR__: specifies the PLL division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	6051	* This parameter must be a number between 1 and 32.
NYX	0:85b3fd62ea1a	6052	* SAI1 clock frequency = f(PLLR) / __PLLDivR__
NYX	0:85b3fd62ea1a	6053	*/
NYX	0:85b3fd62ea1a	6054	#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))
NYX	0:85b3fd62ea1a	6055	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	6056
NYX	0:85b3fd62ea1a	6057	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
NYX	0:85b3fd62ea1a	6058	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6059	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
NYX	0:85b3fd62ea1a	6060	* @note This function must be called before enabling the PLLI2S.
NYX	0:85b3fd62ea1a	6061	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
NYX	0:85b3fd62ea1a	6062	* This parameter must be a number between 1 and 32.
NYX	0:85b3fd62ea1a	6063	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
NYX	0:85b3fd62ea1a	6064	*/
NYX	0:85b3fd62ea1a	6065	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
NYX	0:85b3fd62ea1a	6066
NYX	0:85b3fd62ea1a	6067	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
NYX	0:85b3fd62ea1a	6068	* @note This function must be called before enabling the PLLSAI.
NYX	0:85b3fd62ea1a	6069	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
NYX	0:85b3fd62ea1a	6070	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
NYX	0:85b3fd62ea1a	6071	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
NYX	0:85b3fd62ea1a	6072	*/
NYX	0:85b3fd62ea1a	6073	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
NYX	0:85b3fd62ea1a	6074	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6075
NYX	0:85b3fd62ea1a	6076	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6077	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
NYX	0:85b3fd62ea1a	6078	*
NYX	0:85b3fd62ea1a	6079	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
NYX	0:85b3fd62ea1a	6080	* @note This function must be called before enabling the PLLSAI.
NYX	0:85b3fd62ea1a	6081	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
NYX	0:85b3fd62ea1a	6082	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
NYX	0:85b3fd62ea1a	6083	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
NYX	0:85b3fd62ea1a	6084	*/
NYX	0:85b3fd62ea1a	6085	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
NYX	0:85b3fd62ea1a	6086	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6087	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	6088
NYX	0:85b3fd62ea1a	6089	/------------------------- Peripheral Clock selection -----------------------/
NYX	0:85b3fd62ea1a	6090	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
NYX	0:85b3fd62ea1a	6091	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	6092	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	6093	defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6094	/** @brief Macro to configure the I2S clock source (I2SCLK).
NYX	0:85b3fd62ea1a	6095	* @note This function must be called before enabling the I2S APB clock.
NYX	0:85b3fd62ea1a	6096	* @param __SOURCE__: specifies the I2S clock source.
NYX	0:85b3fd62ea1a	6097	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6098	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
NYX	0:85b3fd62ea1a	6099	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
NYX	0:85b3fd62ea1a	6100	* used as I2S clock source.
NYX	0:85b3fd62ea1a	6101	*/
NYX	0:85b3fd62ea1a	6102	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
NYX	0:85b3fd62ea1a	6103
NYX	0:85b3fd62ea1a	6104
NYX	0:85b3fd62ea1a	6105	/** @brief Macro to get the I2S clock source (I2SCLK).
NYX	0:85b3fd62ea1a	6106	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6107	* @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
NYX	0:85b3fd62ea1a	6108	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
NYX	0:85b3fd62ea1a	6109	* used as I2S clock source
NYX	0:85b3fd62ea1a	6110	*/
NYX	0:85b3fd62ea1a	6111	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
NYX	0:85b3fd62ea1a	6112	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6113
NYX	0:85b3fd62ea1a	6114	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6115
NYX	0:85b3fd62ea1a	6116	/** @brief Macro to configure SAI1BlockA clock source selection.
NYX	0:85b3fd62ea1a	6117	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
NYX	0:85b3fd62ea1a	6118	* @note This function must be called before enabling PLLSAI, PLLI2S and
NYX	0:85b3fd62ea1a	6119	* the SAI clock.
NYX	0:85b3fd62ea1a	6120	* @param __SOURCE__: specifies the SAI Block A clock source.
NYX	0:85b3fd62ea1a	6121	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6122	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
NYX	0:85b3fd62ea1a	6123	* as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6124	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
NYX	0:85b3fd62ea1a	6125	* as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6126	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
NYX	0:85b3fd62ea1a	6127	* used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6128	*/
NYX	0:85b3fd62ea1a	6129	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6130
NYX	0:85b3fd62ea1a	6131	/** @brief Macro to configure SAI1BlockB clock source selection.
NYX	0:85b3fd62ea1a	6132	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
NYX	0:85b3fd62ea1a	6133	* @note This function must be called before enabling PLLSAI, PLLI2S and
NYX	0:85b3fd62ea1a	6134	* the SAI clock.
NYX	0:85b3fd62ea1a	6135	* @param __SOURCE__: specifies the SAI Block B clock source.
NYX	0:85b3fd62ea1a	6136	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6137	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
NYX	0:85b3fd62ea1a	6138	* as SAI1 Block B clock.
NYX	0:85b3fd62ea1a	6139	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
NYX	0:85b3fd62ea1a	6140	* as SAI1 Block B clock.
NYX	0:85b3fd62ea1a	6141	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
NYX	0:85b3fd62ea1a	6142	* used as SAI1 Block B clock.
NYX	0:85b3fd62ea1a	6143	*/
NYX	0:85b3fd62ea1a	6144	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6145	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6146
NYX	0:85b3fd62ea1a	6147	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	6148	/** @brief Macro to configure SAI1 clock source selection.
NYX	0:85b3fd62ea1a	6149	* @note This configuration is only available with STM32F446xx Devices.
NYX	0:85b3fd62ea1a	6150	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
NYX	0:85b3fd62ea1a	6151	* the SAI clock.
NYX	0:85b3fd62ea1a	6152	* @param __SOURCE__: specifies the SAI1 clock source.
NYX	0:85b3fd62ea1a	6153	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6154	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
NYX	0:85b3fd62ea1a	6155	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
NYX	0:85b3fd62ea1a	6156	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
NYX	0:85b3fd62ea1a	6157	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
NYX	0:85b3fd62ea1a	6158	*/
NYX	0:85b3fd62ea1a	6159	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6160
NYX	0:85b3fd62ea1a	6161	/** @brief Macro to Get SAI1 clock source selection.
NYX	0:85b3fd62ea1a	6162	* @note This configuration is only available with STM32F446xx Devices.
NYX	0:85b3fd62ea1a	6163	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6164	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
NYX	0:85b3fd62ea1a	6165	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
NYX	0:85b3fd62ea1a	6166	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
NYX	0:85b3fd62ea1a	6167	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
NYX	0:85b3fd62ea1a	6168	*/
NYX	0:85b3fd62ea1a	6169	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
NYX	0:85b3fd62ea1a	6170
NYX	0:85b3fd62ea1a	6171	/** @brief Macro to configure SAI2 clock source selection.
NYX	0:85b3fd62ea1a	6172	* @note This configuration is only available with STM32F446xx Devices.
NYX	0:85b3fd62ea1a	6173	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
NYX	0:85b3fd62ea1a	6174	* the SAI clock.
NYX	0:85b3fd62ea1a	6175	* @param __SOURCE__: specifies the SAI2 clock source.
NYX	0:85b3fd62ea1a	6176	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6177	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
NYX	0:85b3fd62ea1a	6178	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
NYX	0:85b3fd62ea1a	6179	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
NYX	0:85b3fd62ea1a	6180	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
NYX	0:85b3fd62ea1a	6181	*/
NYX	0:85b3fd62ea1a	6182	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6183
NYX	0:85b3fd62ea1a	6184	/** @brief Macro to Get SAI2 clock source selection.
NYX	0:85b3fd62ea1a	6185	* @note This configuration is only available with STM32F446xx Devices.
NYX	0:85b3fd62ea1a	6186	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6187	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
NYX	0:85b3fd62ea1a	6188	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
NYX	0:85b3fd62ea1a	6189	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
NYX	0:85b3fd62ea1a	6190	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
NYX	0:85b3fd62ea1a	6191	*/
NYX	0:85b3fd62ea1a	6192	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
NYX	0:85b3fd62ea1a	6193
NYX	0:85b3fd62ea1a	6194	/** @brief Macro to configure I2S APB1 clock source selection.
NYX	0:85b3fd62ea1a	6195	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
NYX	0:85b3fd62ea1a	6196	* @param __SOURCE__: specifies the I2S APB1 clock source.
NYX	0:85b3fd62ea1a	6197	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6198	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
NYX	0:85b3fd62ea1a	6199	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
NYX	0:85b3fd62ea1a	6200	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
NYX	0:85b3fd62ea1a	6201	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6202	*/
NYX	0:85b3fd62ea1a	6203	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6204
NYX	0:85b3fd62ea1a	6205	/** @brief Macro to Get I2S APB1 clock source selection.
NYX	0:85b3fd62ea1a	6206	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6207	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
NYX	0:85b3fd62ea1a	6208	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
NYX	0:85b3fd62ea1a	6209	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
NYX	0:85b3fd62ea1a	6210	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6211	*/
NYX	0:85b3fd62ea1a	6212	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
NYX	0:85b3fd62ea1a	6213
NYX	0:85b3fd62ea1a	6214	/** @brief Macro to configure I2S APB2 clock source selection.
NYX	0:85b3fd62ea1a	6215	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
NYX	0:85b3fd62ea1a	6216	* @param __SOURCE__: specifies the SAI Block A clock source.
NYX	0:85b3fd62ea1a	6217	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6218	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
NYX	0:85b3fd62ea1a	6219	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
NYX	0:85b3fd62ea1a	6220	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
NYX	0:85b3fd62ea1a	6221	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6222	*/
NYX	0:85b3fd62ea1a	6223	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6224
NYX	0:85b3fd62ea1a	6225	/** @brief Macro to Get I2S APB2 clock source selection.
NYX	0:85b3fd62ea1a	6226	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6227	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
NYX	0:85b3fd62ea1a	6228	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
NYX	0:85b3fd62ea1a	6229	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
NYX	0:85b3fd62ea1a	6230	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6231	*/
NYX	0:85b3fd62ea1a	6232	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
NYX	0:85b3fd62ea1a	6233
NYX	0:85b3fd62ea1a	6234	/** @brief Macro to configure the CEC clock.
NYX	0:85b3fd62ea1a	6235	* @param __SOURCE__: specifies the CEC clock source.
NYX	0:85b3fd62ea1a	6236	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6237	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
NYX	0:85b3fd62ea1a	6238	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
NYX	0:85b3fd62ea1a	6239	*/
NYX	0:85b3fd62ea1a	6240	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6241
NYX	0:85b3fd62ea1a	6242	/** @brief Macro to Get the CEC clock.
NYX	0:85b3fd62ea1a	6243	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6244	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
NYX	0:85b3fd62ea1a	6245	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
NYX	0:85b3fd62ea1a	6246	*/
NYX	0:85b3fd62ea1a	6247	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
NYX	0:85b3fd62ea1a	6248
NYX	0:85b3fd62ea1a	6249	/** @brief Macro to configure the FMPI2C1 clock.
NYX	0:85b3fd62ea1a	6250	* @param __SOURCE__: specifies the FMPI2C1 clock source.
NYX	0:85b3fd62ea1a	6251	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6252	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6253	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6254	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6255	*/
NYX	0:85b3fd62ea1a	6256	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6257
NYX	0:85b3fd62ea1a	6258	/** @brief Macro to Get the FMPI2C1 clock.
NYX	0:85b3fd62ea1a	6259	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6260	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6261	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6262	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6263	*/
NYX	0:85b3fd62ea1a	6264	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
NYX	0:85b3fd62ea1a	6265
NYX	0:85b3fd62ea1a	6266	/** @brief Macro to configure the CLK48 clock.
NYX	0:85b3fd62ea1a	6267	* @param __SOURCE__: specifies the CLK48 clock source.
NYX	0:85b3fd62ea1a	6268	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6269	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
NYX	0:85b3fd62ea1a	6270	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
NYX	0:85b3fd62ea1a	6271	*/
NYX	0:85b3fd62ea1a	6272	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6273
NYX	0:85b3fd62ea1a	6274	/** @brief Macro to Get the CLK48 clock.
NYX	0:85b3fd62ea1a	6275	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6276	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
NYX	0:85b3fd62ea1a	6277	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
NYX	0:85b3fd62ea1a	6278	*/
NYX	0:85b3fd62ea1a	6279	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
NYX	0:85b3fd62ea1a	6280
NYX	0:85b3fd62ea1a	6281	/** @brief Macro to configure the SDIO clock.
NYX	0:85b3fd62ea1a	6282	* @param __SOURCE__: specifies the SDIO clock source.
NYX	0:85b3fd62ea1a	6283	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6284	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
NYX	0:85b3fd62ea1a	6285	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
NYX	0:85b3fd62ea1a	6286	*/
NYX	0:85b3fd62ea1a	6287	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6288
NYX	0:85b3fd62ea1a	6289	/** @brief Macro to Get the SDIO clock.
NYX	0:85b3fd62ea1a	6290	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6291	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
NYX	0:85b3fd62ea1a	6292	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
NYX	0:85b3fd62ea1a	6293	*/
NYX	0:85b3fd62ea1a	6294	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
NYX	0:85b3fd62ea1a	6295
NYX	0:85b3fd62ea1a	6296	/** @brief Macro to configure the SPDIFRX clock.
NYX	0:85b3fd62ea1a	6297	* @param __SOURCE__: specifies the SPDIFRX clock source.
NYX	0:85b3fd62ea1a	6298	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6299	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
NYX	0:85b3fd62ea1a	6300	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
NYX	0:85b3fd62ea1a	6301	*/
NYX	0:85b3fd62ea1a	6302	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6303
NYX	0:85b3fd62ea1a	6304	/** @brief Macro to Get the SPDIFRX clock.
NYX	0:85b3fd62ea1a	6305	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6306	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
NYX	0:85b3fd62ea1a	6307	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
NYX	0:85b3fd62ea1a	6308	*/
NYX	0:85b3fd62ea1a	6309	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
NYX	0:85b3fd62ea1a	6310	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	6311
NYX	0:85b3fd62ea1a	6312	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6313
NYX	0:85b3fd62ea1a	6314	/** @brief Macro to configure the CLK48 clock.
NYX	0:85b3fd62ea1a	6315	* @param __SOURCE__: specifies the CLK48 clock source.
NYX	0:85b3fd62ea1a	6316	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6317	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
NYX	0:85b3fd62ea1a	6318	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
NYX	0:85b3fd62ea1a	6319	*/
NYX	0:85b3fd62ea1a	6320	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6321
NYX	0:85b3fd62ea1a	6322	/** @brief Macro to Get the CLK48 clock.
NYX	0:85b3fd62ea1a	6323	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6324	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
NYX	0:85b3fd62ea1a	6325	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
NYX	0:85b3fd62ea1a	6326	*/
NYX	0:85b3fd62ea1a	6327	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
NYX	0:85b3fd62ea1a	6328
NYX	0:85b3fd62ea1a	6329	/** @brief Macro to configure the SDIO clock.
NYX	0:85b3fd62ea1a	6330	* @param __SOURCE__: specifies the SDIO clock source.
NYX	0:85b3fd62ea1a	6331	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6332	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
NYX	0:85b3fd62ea1a	6333	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
NYX	0:85b3fd62ea1a	6334	*/
NYX	0:85b3fd62ea1a	6335	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6336
NYX	0:85b3fd62ea1a	6337	/** @brief Macro to Get the SDIO clock.
NYX	0:85b3fd62ea1a	6338	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6339	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
NYX	0:85b3fd62ea1a	6340	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
NYX	0:85b3fd62ea1a	6341	*/
NYX	0:85b3fd62ea1a	6342	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
NYX	0:85b3fd62ea1a	6343
NYX	0:85b3fd62ea1a	6344	/** @brief Macro to configure the DSI clock.
NYX	0:85b3fd62ea1a	6345	* @param __SOURCE__: specifies the DSI clock source.
NYX	0:85b3fd62ea1a	6346	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6347	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
NYX	0:85b3fd62ea1a	6348	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
NYX	0:85b3fd62ea1a	6349	*/
NYX	0:85b3fd62ea1a	6350	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6351
NYX	0:85b3fd62ea1a	6352	/** @brief Macro to Get the DSI clock.
NYX	0:85b3fd62ea1a	6353	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6354	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
NYX	0:85b3fd62ea1a	6355	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
NYX	0:85b3fd62ea1a	6356	*/
NYX	0:85b3fd62ea1a	6357	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
NYX	0:85b3fd62ea1a	6358
NYX	0:85b3fd62ea1a	6359	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6360
NYX	0:85b3fd62ea1a	6361	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
NYX	0:85b3fd62ea1a	6362	defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6363	/** @brief Macro to configure the DFSDM1 clock.
NYX	0:85b3fd62ea1a	6364	* @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
NYX	0:85b3fd62ea1a	6365	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6366	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
NYX	0:85b3fd62ea1a	6367	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
NYX	0:85b3fd62ea1a	6368	* @retval None
NYX	0:85b3fd62ea1a	6369	*/
NYX	0:85b3fd62ea1a	6370	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
NYX	0:85b3fd62ea1a	6371
NYX	0:85b3fd62ea1a	6372	/** @brief Macro to get the DFSDM1 clock source.
NYX	0:85b3fd62ea1a	6373	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6374	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
NYX	0:85b3fd62ea1a	6375	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
NYX	0:85b3fd62ea1a	6376	*/
NYX	0:85b3fd62ea1a	6377	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
NYX	0:85b3fd62ea1a	6378
NYX	0:85b3fd62ea1a	6379	/** @brief Macro to configure DFSDM1 Audio clock source selection.
NYX	0:85b3fd62ea1a	6380	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
NYX	0:85b3fd62ea1a	6381	STM32F413xx/STM32F423xx Devices.
NYX	0:85b3fd62ea1a	6382	* @param __SOURCE__: specifies the DFSDM1 Audio clock source.
NYX	0:85b3fd62ea1a	6383	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6384	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
NYX	0:85b3fd62ea1a	6385	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
NYX	0:85b3fd62ea1a	6386	*/
NYX	0:85b3fd62ea1a	6387	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6388
NYX	0:85b3fd62ea1a	6389	/** @brief Macro to Get DFSDM1 Audio clock source selection.
NYX	0:85b3fd62ea1a	6390	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
NYX	0:85b3fd62ea1a	6391	STM32F413xx/STM32F423xx Devices.
NYX	0:85b3fd62ea1a	6392	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6393	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
NYX	0:85b3fd62ea1a	6394	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
NYX	0:85b3fd62ea1a	6395	*/
NYX	0:85b3fd62ea1a	6396	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
NYX	0:85b3fd62ea1a	6397
NYX	0:85b3fd62ea1a	6398	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6399	/** @brief Macro to configure the DFSDM2 clock.
NYX	0:85b3fd62ea1a	6400	* @param __DFSDM2_CLKSOURCE__: specifies the DFSDM1 clock source.
NYX	0:85b3fd62ea1a	6401	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6402	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
NYX	0:85b3fd62ea1a	6403	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
NYX	0:85b3fd62ea1a	6404	* @retval None
NYX	0:85b3fd62ea1a	6405	*/
NYX	0:85b3fd62ea1a	6406	#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
NYX	0:85b3fd62ea1a	6407
NYX	0:85b3fd62ea1a	6408	/** @brief Macro to get the DFSDM2 clock source.
NYX	0:85b3fd62ea1a	6409	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6410	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
NYX	0:85b3fd62ea1a	6411	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
NYX	0:85b3fd62ea1a	6412	*/
NYX	0:85b3fd62ea1a	6413	#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
NYX	0:85b3fd62ea1a	6414
NYX	0:85b3fd62ea1a	6415	/** @brief Macro to configure DFSDM1 Audio clock source selection.
NYX	0:85b3fd62ea1a	6416	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
NYX	0:85b3fd62ea1a	6417	* @param __SOURCE__: specifies the DFSDM2 Audio clock source.
NYX	0:85b3fd62ea1a	6418	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6419	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
NYX	0:85b3fd62ea1a	6420	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
NYX	0:85b3fd62ea1a	6421	*/
NYX	0:85b3fd62ea1a	6422	#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6423
NYX	0:85b3fd62ea1a	6424	/** @brief Macro to Get DFSDM2 Audio clock source selection.
NYX	0:85b3fd62ea1a	6425	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
NYX	0:85b3fd62ea1a	6426	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6427	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
NYX	0:85b3fd62ea1a	6428	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
NYX	0:85b3fd62ea1a	6429	*/
NYX	0:85b3fd62ea1a	6430	#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
NYX	0:85b3fd62ea1a	6431
NYX	0:85b3fd62ea1a	6432	/** @brief Macro to configure SAI1BlockA clock source selection.
NYX	0:85b3fd62ea1a	6433	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
NYX	0:85b3fd62ea1a	6434	* @note This function must be called before enabling PLLSAI, PLLI2S and
NYX	0:85b3fd62ea1a	6435	* the SAI clock.
NYX	0:85b3fd62ea1a	6436	* @param __SOURCE__: specifies the SAI Block A clock source.
NYX	0:85b3fd62ea1a	6437	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6438	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6439	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6440	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6441	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6442	*/
NYX	0:85b3fd62ea1a	6443	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6444
NYX	0:85b3fd62ea1a	6445	/** @brief Macro to Get SAI1 BlockA clock source selection.
NYX	0:85b3fd62ea1a	6446	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
NYX	0:85b3fd62ea1a	6447	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6448	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6449	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6450	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6451	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6452	*/
NYX	0:85b3fd62ea1a	6453	#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
NYX	0:85b3fd62ea1a	6454
NYX	0:85b3fd62ea1a	6455	/** @brief Macro to configure SAI1 BlockB clock source selection.
NYX	0:85b3fd62ea1a	6456	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
NYX	0:85b3fd62ea1a	6457	* @note This function must be called before enabling PLLSAI, PLLI2S and
NYX	0:85b3fd62ea1a	6458	* the SAI clock.
NYX	0:85b3fd62ea1a	6459	* @param __SOURCE__: specifies the SAI Block B clock source.
NYX	0:85b3fd62ea1a	6460	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6461	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6462	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6463	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6464	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6465	*/
NYX	0:85b3fd62ea1a	6466	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6467
NYX	0:85b3fd62ea1a	6468	/** @brief Macro to Get SAI1 BlockB clock source selection.
NYX	0:85b3fd62ea1a	6469	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
NYX	0:85b3fd62ea1a	6470	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6471	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6472	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6473	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
NYX	0:85b3fd62ea1a	6474	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6475	*/
NYX	0:85b3fd62ea1a	6476	#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
NYX	0:85b3fd62ea1a	6477
NYX	0:85b3fd62ea1a	6478	/** @brief Macro to configure the LPTIM1 clock.
NYX	0:85b3fd62ea1a	6479	* @param __SOURCE__: specifies the LPTIM1 clock source.
NYX	0:85b3fd62ea1a	6480	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6481	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6482	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6483	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6484	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6485	*/
NYX	0:85b3fd62ea1a	6486	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6487
NYX	0:85b3fd62ea1a	6488	/** @brief Macro to Get the LPTIM1 clock.
NYX	0:85b3fd62ea1a	6489	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6490	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6491	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6492	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6493	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6494	*/
NYX	0:85b3fd62ea1a	6495	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
NYX	0:85b3fd62ea1a	6496	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	6497
NYX	0:85b3fd62ea1a	6498	/** @brief Macro to configure I2S APB1 clock source selection.
NYX	0:85b3fd62ea1a	6499	* @param __SOURCE__: specifies the I2S APB1 clock source.
NYX	0:85b3fd62ea1a	6500	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6501	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
NYX	0:85b3fd62ea1a	6502	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
NYX	0:85b3fd62ea1a	6503	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
NYX	0:85b3fd62ea1a	6504	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6505	*/
NYX	0:85b3fd62ea1a	6506	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6507
NYX	0:85b3fd62ea1a	6508	/** @brief Macro to Get I2S APB1 clock source selection.
NYX	0:85b3fd62ea1a	6509	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6510	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
NYX	0:85b3fd62ea1a	6511	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
NYX	0:85b3fd62ea1a	6512	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
NYX	0:85b3fd62ea1a	6513	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6514	*/
NYX	0:85b3fd62ea1a	6515	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
NYX	0:85b3fd62ea1a	6516
NYX	0:85b3fd62ea1a	6517	/** @brief Macro to configure I2S APB2 clock source selection.
NYX	0:85b3fd62ea1a	6518	* @param __SOURCE__: specifies the I2S APB2 clock source.
NYX	0:85b3fd62ea1a	6519	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6520	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
NYX	0:85b3fd62ea1a	6521	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
NYX	0:85b3fd62ea1a	6522	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
NYX	0:85b3fd62ea1a	6523	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6524	*/
NYX	0:85b3fd62ea1a	6525	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6526
NYX	0:85b3fd62ea1a	6527	/** @brief Macro to Get I2S APB2 clock source selection.
NYX	0:85b3fd62ea1a	6528	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6529	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
NYX	0:85b3fd62ea1a	6530	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
NYX	0:85b3fd62ea1a	6531	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
NYX	0:85b3fd62ea1a	6532	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6533	*/
NYX	0:85b3fd62ea1a	6534	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
NYX	0:85b3fd62ea1a	6535
NYX	0:85b3fd62ea1a	6536	/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
NYX	0:85b3fd62ea1a	6537	* @note This macro must be called before enabling the I2S APB clock.
NYX	0:85b3fd62ea1a	6538	* @param __SOURCE__: specifies the I2S clock source.
NYX	0:85b3fd62ea1a	6539	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6540	* @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
NYX	0:85b3fd62ea1a	6541	* @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
NYX	0:85b3fd62ea1a	6542	* used as I2S clock source.
NYX	0:85b3fd62ea1a	6543	*/
NYX	0:85b3fd62ea1a	6544	#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
NYX	0:85b3fd62ea1a	6545
NYX	0:85b3fd62ea1a	6546	/** @brief Macro to configure the FMPI2C1 clock.
NYX	0:85b3fd62ea1a	6547	* @param __SOURCE__: specifies the FMPI2C1 clock source.
NYX	0:85b3fd62ea1a	6548	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6549	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6550	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6551	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6552	*/
NYX	0:85b3fd62ea1a	6553	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6554
NYX	0:85b3fd62ea1a	6555	/** @brief Macro to Get the FMPI2C1 clock.
NYX	0:85b3fd62ea1a	6556	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6557	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6558	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6559	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6560	*/
NYX	0:85b3fd62ea1a	6561	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
NYX	0:85b3fd62ea1a	6562
NYX	0:85b3fd62ea1a	6563	/** @brief Macro to configure the CLK48 clock.
NYX	0:85b3fd62ea1a	6564	* @param __SOURCE__: specifies the CLK48 clock source.
NYX	0:85b3fd62ea1a	6565	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6566	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
NYX	0:85b3fd62ea1a	6567	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
NYX	0:85b3fd62ea1a	6568	*/
NYX	0:85b3fd62ea1a	6569	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6570
NYX	0:85b3fd62ea1a	6571	/** @brief Macro to Get the CLK48 clock.
NYX	0:85b3fd62ea1a	6572	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6573	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
NYX	0:85b3fd62ea1a	6574	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
NYX	0:85b3fd62ea1a	6575	*/
NYX	0:85b3fd62ea1a	6576	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
NYX	0:85b3fd62ea1a	6577
NYX	0:85b3fd62ea1a	6578	/** @brief Macro to configure the SDIO clock.
NYX	0:85b3fd62ea1a	6579	* @param __SOURCE__: specifies the SDIO clock source.
NYX	0:85b3fd62ea1a	6580	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6581	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
NYX	0:85b3fd62ea1a	6582	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
NYX	0:85b3fd62ea1a	6583	*/
NYX	0:85b3fd62ea1a	6584	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6585
NYX	0:85b3fd62ea1a	6586	/** @brief Macro to Get the SDIO clock.
NYX	0:85b3fd62ea1a	6587	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6588	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
NYX	0:85b3fd62ea1a	6589	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
NYX	0:85b3fd62ea1a	6590	*/
NYX	0:85b3fd62ea1a	6591	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
NYX	0:85b3fd62ea1a	6592
NYX	0:85b3fd62ea1a	6593	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	6594
NYX	0:85b3fd62ea1a	6595	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	6596	/** @brief Macro to configure I2S clock source selection.
NYX	0:85b3fd62ea1a	6597	* @param __SOURCE__: specifies the I2S clock source.
NYX	0:85b3fd62ea1a	6598	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6599	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
NYX	0:85b3fd62ea1a	6600	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
NYX	0:85b3fd62ea1a	6601	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
NYX	0:85b3fd62ea1a	6602	*/
NYX	0:85b3fd62ea1a	6603	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
NYX	0:85b3fd62ea1a	6604
NYX	0:85b3fd62ea1a	6605	/** @brief Macro to Get I2S clock source selection.
NYX	0:85b3fd62ea1a	6606	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6607	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
NYX	0:85b3fd62ea1a	6608	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
NYX	0:85b3fd62ea1a	6609	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
NYX	0:85b3fd62ea1a	6610	*/
NYX	0:85b3fd62ea1a	6611	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
NYX	0:85b3fd62ea1a	6612
NYX	0:85b3fd62ea1a	6613	/** @brief Macro to configure the FMPI2C1 clock.
NYX	0:85b3fd62ea1a	6614	* @param __SOURCE__: specifies the FMPI2C1 clock source.
NYX	0:85b3fd62ea1a	6615	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6616	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6617	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6618	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6619	*/
NYX	0:85b3fd62ea1a	6620	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6621
NYX	0:85b3fd62ea1a	6622	/** @brief Macro to Get the FMPI2C1 clock.
NYX	0:85b3fd62ea1a	6623	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6624	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6625	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6626	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
NYX	0:85b3fd62ea1a	6627	*/
NYX	0:85b3fd62ea1a	6628	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
NYX	0:85b3fd62ea1a	6629
NYX	0:85b3fd62ea1a	6630	/** @brief Macro to configure the LPTIM1 clock.
NYX	0:85b3fd62ea1a	6631	* @param __SOURCE__: specifies the LPTIM1 clock source.
NYX	0:85b3fd62ea1a	6632	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6633	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6634	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6635	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6636	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6637	*/
NYX	0:85b3fd62ea1a	6638	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
NYX	0:85b3fd62ea1a	6639
NYX	0:85b3fd62ea1a	6640	/** @brief Macro to Get the LPTIM1 clock.
NYX	0:85b3fd62ea1a	6641	* @retval The clock source can be one of the following values:
NYX	0:85b3fd62ea1a	6642	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6643	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6644	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6645	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
NYX	0:85b3fd62ea1a	6646	*/
NYX	0:85b3fd62ea1a	6647	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
NYX	0:85b3fd62ea1a	6648	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	6649
NYX	0:85b3fd62ea1a	6650	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	6651	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	6652	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	6653	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
NYX	0:85b3fd62ea1a	6654	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6655	/** @brief Macro to configure the Timers clocks prescalers
NYX	0:85b3fd62ea1a	6656	* @note This feature is only available with STM32F429x/439x Devices.
NYX	0:85b3fd62ea1a	6657	* @param __PRESC__ : specifies the Timers clocks prescalers selection
NYX	0:85b3fd62ea1a	6658	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6659	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
NYX	0:85b3fd62ea1a	6660	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
NYX	0:85b3fd62ea1a	6661	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
NYX	0:85b3fd62ea1a	6662	* division by 4 or more.
NYX	0:85b3fd62ea1a	6663	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
NYX	0:85b3fd62ea1a	6664	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
NYX	0:85b3fd62ea1a	6665	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
NYX	0:85b3fd62ea1a	6666	* to division by 8 or more.
NYX	0:85b3fd62ea1a	6667	*/
NYX	0:85b3fd62ea1a	6668	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
NYX	0:85b3fd62ea1a	6669
NYX	0:85b3fd62ea1a	6670	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
NYX	0:85b3fd62ea1a	6671	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\|\
NYX	0:85b3fd62ea1a	6672	STM32F423xx */
NYX	0:85b3fd62ea1a	6673
NYX	0:85b3fd62ea1a	6674	/----------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	6675
NYX	0:85b3fd62ea1a	6676	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6677	/** @brief Enable PLLSAI_RDY interrupt.
NYX	0:85b3fd62ea1a	6678	*/
NYX	0:85b3fd62ea1a	6679	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
NYX	0:85b3fd62ea1a	6680
NYX	0:85b3fd62ea1a	6681	/** @brief Disable PLLSAI_RDY interrupt.
NYX	0:85b3fd62ea1a	6682	*/
NYX	0:85b3fd62ea1a	6683	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
NYX	0:85b3fd62ea1a	6684
NYX	0:85b3fd62ea1a	6685	/** @brief Clear the PLLSAI RDY interrupt pending bits.
NYX	0:85b3fd62ea1a	6686	*/
NYX	0:85b3fd62ea1a	6687	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
NYX	0:85b3fd62ea1a	6688
NYX	0:85b3fd62ea1a	6689	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
NYX	0:85b3fd62ea1a	6690	* @retval The new state (TRUE or FALSE).
NYX	0:85b3fd62ea1a	6691	*/
NYX	0:85b3fd62ea1a	6692	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
NYX	0:85b3fd62ea1a	6693
NYX	0:85b3fd62ea1a	6694	/** @brief Check PLLSAI RDY flag is set or not.
NYX	0:85b3fd62ea1a	6695	* @retval The new state (TRUE or FALSE).
NYX	0:85b3fd62ea1a	6696	*/
NYX	0:85b3fd62ea1a	6697	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
NYX	0:85b3fd62ea1a	6698
NYX	0:85b3fd62ea1a	6699	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6700
NYX	0:85b3fd62ea1a	6701	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	6702	/** @brief Macros to enable or disable the RCC MCO1 feature.
NYX	0:85b3fd62ea1a	6703	*/
NYX	0:85b3fd62ea1a	6704	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
NYX	0:85b3fd62ea1a	6705	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
NYX	0:85b3fd62ea1a	6706
NYX	0:85b3fd62ea1a	6707	/** @brief Macros to enable or disable the RCC MCO2 feature.
NYX	0:85b3fd62ea1a	6708	*/
NYX	0:85b3fd62ea1a	6709	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
NYX	0:85b3fd62ea1a	6710	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
NYX	0:85b3fd62ea1a	6711
NYX	0:85b3fd62ea1a	6712	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	6713
NYX	0:85b3fd62ea1a	6714	/**
NYX	0:85b3fd62ea1a	6715	* @}
NYX	0:85b3fd62ea1a	6716	*/
NYX	0:85b3fd62ea1a	6717
NYX	0:85b3fd62ea1a	6718	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	6719	/** @addtogroup RCCEx_Exported_Functions
NYX	0:85b3fd62ea1a	6720	* @{
NYX	0:85b3fd62ea1a	6721	*/
NYX	0:85b3fd62ea1a	6722
NYX	0:85b3fd62ea1a	6723	/** @addtogroup RCCEx_Exported_Functions_Group1
NYX	0:85b3fd62ea1a	6724	* @{
NYX	0:85b3fd62ea1a	6725	*/
NYX	0:85b3fd62ea1a	6726	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
NYX	0:85b3fd62ea1a	6727	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
NYX	0:85b3fd62ea1a	6728
NYX	0:85b3fd62ea1a	6729	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
NYX	0:85b3fd62ea1a	6730
NYX	0:85b3fd62ea1a	6731	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
NYX	0:85b3fd62ea1a	6732	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	6733	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
NYX	0:85b3fd62ea1a	6734	defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6735	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
NYX	0:85b3fd62ea1a	6736	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	6737	/**
NYX	0:85b3fd62ea1a	6738	* @}
NYX	0:85b3fd62ea1a	6739	*/
NYX	0:85b3fd62ea1a	6740
NYX	0:85b3fd62ea1a	6741	/**
NYX	0:85b3fd62ea1a	6742	* @}
NYX	0:85b3fd62ea1a	6743	*/
NYX	0:85b3fd62ea1a	6744	/* Private types -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	6745	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	6746	/* Private constants ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	6747	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
NYX	0:85b3fd62ea1a	6748	* @{
NYX	0:85b3fd62ea1a	6749	*/
NYX	0:85b3fd62ea1a	6750
NYX	0:85b3fd62ea1a	6751	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
NYX	0:85b3fd62ea1a	6752	* @brief RCC registers bit address in the alias region
NYX	0:85b3fd62ea1a	6753	* @{
NYX	0:85b3fd62ea1a	6754	*/
NYX	0:85b3fd62ea1a	6755	/* --- CR Register ---*/
NYX	0:85b3fd62ea1a	6756	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	6757	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6758	/* Alias word address of PLLSAION bit */
NYX	0:85b3fd62ea1a	6759	#define RCC_PLLSAION_BIT_NUMBER 0x1CU
NYX	0:85b3fd62ea1a	6760	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
NYX	0:85b3fd62ea1a	6761
NYX	0:85b3fd62ea1a	6762	#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
NYX	0:85b3fd62ea1a	6763	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6764
NYX	0:85b3fd62ea1a	6765	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
NYX	0:85b3fd62ea1a	6766	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
NYX	0:85b3fd62ea1a	6767	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
NYX	0:85b3fd62ea1a	6768	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
NYX	0:85b3fd62ea1a	6769	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6770	/* Alias word address of PLLI2SON bit */
NYX	0:85b3fd62ea1a	6771	#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
NYX	0:85b3fd62ea1a	6772	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
NYX	0:85b3fd62ea1a	6773	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
NYX	0:85b3fd62ea1a	6774	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
NYX	0:85b3fd62ea1a	6775	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	6776
NYX	0:85b3fd62ea1a	6777	/* --- DCKCFGR Register ---*/
NYX	0:85b3fd62ea1a	6778	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	6779	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F401xC) \|\|\
NYX	0:85b3fd62ea1a	6780	defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	6781	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
NYX	0:85b3fd62ea1a	6782	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6783	/* Alias word address of TIMPRE bit */
NYX	0:85b3fd62ea1a	6784	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU)
NYX	0:85b3fd62ea1a	6785	#define RCC_TIMPRE_BIT_NUMBER 0x18U
NYX	0:85b3fd62ea1a	6786	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
NYX	0:85b3fd62ea1a	6787	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F401xC \|\|\
NYX	0:85b3fd62ea1a	6788	STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
NYX	0:85b3fd62ea1a	6789	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	6790
NYX	0:85b3fd62ea1a	6791	/* --- CFGR Register ---*/
NYX	0:85b3fd62ea1a	6792	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
NYX	0:85b3fd62ea1a	6793	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
NYX	0:85b3fd62ea1a	6794	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
NYX	0:85b3fd62ea1a	6795	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
NYX	0:85b3fd62ea1a	6796	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6797	/* Alias word address of I2SSRC bit */
NYX	0:85b3fd62ea1a	6798	#define RCC_I2SSRC_BIT_NUMBER 0x17U
NYX	0:85b3fd62ea1a	6799	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
NYX	0:85b3fd62ea1a	6800
NYX	0:85b3fd62ea1a	6801	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
NYX	0:85b3fd62ea1a	6802	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
NYX	0:85b3fd62ea1a	6803	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6804
NYX	0:85b3fd62ea1a	6805	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
NYX	0:85b3fd62ea1a	6806	defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6807	/* --- PLLI2SCFGR Register ---*/
NYX	0:85b3fd62ea1a	6808	#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
NYX	0:85b3fd62ea1a	6809	/* Alias word address of PLLI2SSRC bit */
NYX	0:85b3fd62ea1a	6810	#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U
NYX	0:85b3fd62ea1a	6811	#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
NYX	0:85b3fd62ea1a	6812
NYX	0:85b3fd62ea1a	6813	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
NYX	0:85b3fd62ea1a	6814	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \| STM32F423xx */
NYX	0:85b3fd62ea1a	6815
NYX	0:85b3fd62ea1a	6816	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	6817	/* Alias word address of MCO1EN bit */
NYX	0:85b3fd62ea1a	6818	#define RCC_MCO1EN_BIT_NUMBER 0x8U
NYX	0:85b3fd62ea1a	6819	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
NYX	0:85b3fd62ea1a	6820
NYX	0:85b3fd62ea1a	6821	/* Alias word address of MCO2EN bit */
NYX	0:85b3fd62ea1a	6822	#define RCC_MCO2EN_BIT_NUMBER 0x9U
NYX	0:85b3fd62ea1a	6823	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
NYX	0:85b3fd62ea1a	6824	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	6825
NYX	0:85b3fd62ea1a	6826	#define PLL_TIMEOUT_VALUE 2U /* 2 ms */
NYX	0:85b3fd62ea1a	6827	/**
NYX	0:85b3fd62ea1a	6828	* @}
NYX	0:85b3fd62ea1a	6829	*/
NYX	0:85b3fd62ea1a	6830
NYX	0:85b3fd62ea1a	6831	/**
NYX	0:85b3fd62ea1a	6832	* @}
NYX	0:85b3fd62ea1a	6833	*/
NYX	0:85b3fd62ea1a	6834
NYX	0:85b3fd62ea1a	6835	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	6836	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
NYX	0:85b3fd62ea1a	6837	* @{
NYX	0:85b3fd62ea1a	6838	*/
NYX	0:85b3fd62ea1a	6839	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
NYX	0:85b3fd62ea1a	6840	* @{
NYX	0:85b3fd62ea1a	6841	*/
NYX	0:85b3fd62ea1a	6842	#if defined(STM32F411xE)
NYX	0:85b3fd62ea1a	6843	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
NYX	0:85b3fd62ea1a	6844	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
NYX	0:85b3fd62ea1a	6845	#else /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\|
NYX	0:85b3fd62ea1a	6846	STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410Tx \|\| STM32F410Cx \|\|
NYX	0:85b3fd62ea1a	6847	STM32F410Rx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Cx \|\| STM32F412Rx \|\|
NYX	0:85b3fd62ea1a	6848	STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	6849	#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
NYX	0:85b3fd62ea1a	6850	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
NYX	0:85b3fd62ea1a	6851	#endif /* STM32F411xE */
NYX	0:85b3fd62ea1a	6852
NYX	0:85b3fd62ea1a	6853	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
NYX	0:85b3fd62ea1a	6854	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
NYX	0:85b3fd62ea1a	6855	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
NYX	0:85b3fd62ea1a	6856
NYX	0:85b3fd62ea1a	6857	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	6858	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
NYX	0:85b3fd62ea1a	6859	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	6860
NYX	0:85b3fd62ea1a	6861	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
NYX	0:85b3fd62ea1a	6862	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
NYX	0:85b3fd62ea1a	6863	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
NYX	0:85b3fd62ea1a	6864
NYX	0:85b3fd62ea1a	6865	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	6866	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
NYX	0:85b3fd62ea1a	6867	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	6868
NYX	0:85b3fd62ea1a	6869	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	6870	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
NYX	0:85b3fd62ea1a	6871	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	6872
NYX	0:85b3fd62ea1a	6873	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6874	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
NYX	0:85b3fd62ea1a	6875	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6876
NYX	0:85b3fd62ea1a	6877	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	6878	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
NYX	0:85b3fd62ea1a	6879	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	6880
NYX	0:85b3fd62ea1a	6881	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6882	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
NYX	0:85b3fd62ea1a	6883	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	6884
NYX	0:85b3fd62ea1a	6885	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
NYX	0:85b3fd62ea1a	6886
NYX	0:85b3fd62ea1a	6887	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	6888	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6889	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
NYX	0:85b3fd62ea1a	6890
NYX	0:85b3fd62ea1a	6891	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
NYX	0:85b3fd62ea1a	6892
NYX	0:85b3fd62ea1a	6893	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
NYX	0:85b3fd62ea1a	6894
NYX	0:85b3fd62ea1a	6895	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
NYX	0:85b3fd62ea1a	6896
NYX	0:85b3fd62ea1a	6897	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
NYX	0:85b3fd62ea1a	6898
NYX	0:85b3fd62ea1a	6899	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
NYX	0:85b3fd62ea1a	6900
NYX	0:85b3fd62ea1a	6901	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
NYX	0:85b3fd62ea1a	6902	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
NYX	0:85b3fd62ea1a	6903	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
NYX	0:85b3fd62ea1a	6904	((VALUE) == RCC_PLLSAIDIVR_16))
NYX	0:85b3fd62ea1a	6905	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	6906
NYX	0:85b3fd62ea1a	6907	#if defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
NYX	0:85b3fd62ea1a	6908	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	6909	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
NYX	0:85b3fd62ea1a	6910
NYX	0:85b3fd62ea1a	6911	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
NYX	0:85b3fd62ea1a	6912	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
NYX	0:85b3fd62ea1a	6913	#endif /* STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	6914
NYX	0:85b3fd62ea1a	6915	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	6916	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
NYX	0:85b3fd62ea1a	6917
NYX	0:85b3fd62ea1a	6918	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
NYX	0:85b3fd62ea1a	6919	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
NYX	0:85b3fd62ea1a	6920
NYX	0:85b3fd62ea1a	6921	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
NYX	0:85b3fd62ea1a	6922	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
NYX	0:85b3fd62ea1a	6923	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
NYX	0:85b3fd62ea1a	6924
NYX	0:85b3fd62ea1a	6925	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
NYX	0:85b3fd62ea1a	6926	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
NYX	0:85b3fd62ea1a	6927	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
NYX	0:85b3fd62ea1a	6928	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
NYX	0:85b3fd62ea1a	6929
NYX	0:85b3fd62ea1a	6930	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	6931	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
NYX	0:85b3fd62ea1a	6932	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
NYX	0:85b3fd62ea1a	6933	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	6934
NYX	0:85b3fd62ea1a	6935	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	6936	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
NYX	0:85b3fd62ea1a	6937
NYX	0:85b3fd62ea1a	6938	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
NYX	0:85b3fd62ea1a	6939	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
NYX	0:85b3fd62ea1a	6940	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
NYX	0:85b3fd62ea1a	6941	((VALUE) == RCC_PLLI2SP_DIV8))
NYX	0:85b3fd62ea1a	6942
NYX	0:85b3fd62ea1a	6943	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
NYX	0:85b3fd62ea1a	6944
NYX	0:85b3fd62ea1a	6945	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
NYX	0:85b3fd62ea1a	6946	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
NYX	0:85b3fd62ea1a	6947	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
NYX	0:85b3fd62ea1a	6948	((VALUE) == RCC_PLLSAIP_DIV8))
NYX	0:85b3fd62ea1a	6949
NYX	0:85b3fd62ea1a	6950	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
NYX	0:85b3fd62ea1a	6951	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
NYX	0:85b3fd62ea1a	6952	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	6953	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
NYX	0:85b3fd62ea1a	6954
NYX	0:85b3fd62ea1a	6955	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
NYX	0:85b3fd62ea1a	6956	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
NYX	0:85b3fd62ea1a	6957	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	6958	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
NYX	0:85b3fd62ea1a	6959
NYX	0:85b3fd62ea1a	6960	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
NYX	0:85b3fd62ea1a	6961	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
NYX	0:85b3fd62ea1a	6962	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	6963	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
NYX	0:85b3fd62ea1a	6964
NYX	0:85b3fd62ea1a	6965	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
NYX	0:85b3fd62ea1a	6966	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
NYX	0:85b3fd62ea1a	6967	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	6968	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
NYX	0:85b3fd62ea1a	6969
NYX	0:85b3fd62ea1a	6970	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
NYX	0:85b3fd62ea1a	6971	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
NYX	0:85b3fd62ea1a	6972	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
NYX	0:85b3fd62ea1a	6973
NYX	0:85b3fd62ea1a	6974	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
NYX	0:85b3fd62ea1a	6975	((SOURCE) == RCC_CECCLKSOURCE_LSE))
NYX	0:85b3fd62ea1a	6976
NYX	0:85b3fd62ea1a	6977	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
NYX	0:85b3fd62ea1a	6978	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
NYX	0:85b3fd62ea1a	6979
NYX	0:85b3fd62ea1a	6980	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
NYX	0:85b3fd62ea1a	6981	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
NYX	0:85b3fd62ea1a	6982
NYX	0:85b3fd62ea1a	6983	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	6984	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
NYX	0:85b3fd62ea1a	6985	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	6986
NYX	0:85b3fd62ea1a	6987	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	6988	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
NYX	0:85b3fd62ea1a	6989
NYX	0:85b3fd62ea1a	6990	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
NYX	0:85b3fd62ea1a	6991	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
NYX	0:85b3fd62ea1a	6992	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
NYX	0:85b3fd62ea1a	6993	((VALUE) == RCC_PLLSAIP_DIV8))
NYX	0:85b3fd62ea1a	6994
NYX	0:85b3fd62ea1a	6995	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
NYX	0:85b3fd62ea1a	6996	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
NYX	0:85b3fd62ea1a	6997
NYX	0:85b3fd62ea1a	6998	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
NYX	0:85b3fd62ea1a	6999	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
NYX	0:85b3fd62ea1a	7000
NYX	0:85b3fd62ea1a	7001	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	7002	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
NYX	0:85b3fd62ea1a	7003
NYX	0:85b3fd62ea1a	7004	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
NYX	0:85b3fd62ea1a	7005	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
NYX	0:85b3fd62ea1a	7006	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	7007
NYX	0:85b3fd62ea1a	7008	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
NYX	0:85b3fd62ea1a	7009	defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	7010	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
NYX	0:85b3fd62ea1a	7011
NYX	0:85b3fd62ea1a	7012	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
NYX	0:85b3fd62ea1a	7013
NYX	0:85b3fd62ea1a	7014	#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) \|\| \
NYX	0:85b3fd62ea1a	7015	((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
NYX	0:85b3fd62ea1a	7016
NYX	0:85b3fd62ea1a	7017	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
NYX	0:85b3fd62ea1a	7018	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
NYX	0:85b3fd62ea1a	7019	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	7020	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
NYX	0:85b3fd62ea1a	7021
NYX	0:85b3fd62ea1a	7022	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
NYX	0:85b3fd62ea1a	7023	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
NYX	0:85b3fd62ea1a	7024	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	7025	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
NYX	0:85b3fd62ea1a	7026
NYX	0:85b3fd62ea1a	7027	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
NYX	0:85b3fd62ea1a	7028	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
NYX	0:85b3fd62ea1a	7029	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
NYX	0:85b3fd62ea1a	7030
NYX	0:85b3fd62ea1a	7031	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
NYX	0:85b3fd62ea1a	7032	((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
NYX	0:85b3fd62ea1a	7033
NYX	0:85b3fd62ea1a	7034	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
NYX	0:85b3fd62ea1a	7035	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
NYX	0:85b3fd62ea1a	7036
NYX	0:85b3fd62ea1a	7037	#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) \|\| \
NYX	0:85b3fd62ea1a	7038	((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
NYX	0:85b3fd62ea1a	7039
NYX	0:85b3fd62ea1a	7040	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) \|\| \
NYX	0:85b3fd62ea1a	7041	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
NYX	0:85b3fd62ea1a	7042
NYX	0:85b3fd62ea1a	7043	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	7044	#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) \|\| \
NYX	0:85b3fd62ea1a	7045	((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
NYX	0:85b3fd62ea1a	7046
NYX	0:85b3fd62ea1a	7047	#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) \|\| \
NYX	0:85b3fd62ea1a	7048	((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
NYX	0:85b3fd62ea1a	7049
NYX	0:85b3fd62ea1a	7050	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
NYX	0:85b3fd62ea1a	7051	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
NYX	0:85b3fd62ea1a	7052	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
NYX	0:85b3fd62ea1a	7053	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
NYX	0:85b3fd62ea1a	7054
NYX	0:85b3fd62ea1a	7055	#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) \|\|\
NYX	0:85b3fd62ea1a	7056	((SOURCE) == RCC_SAIACLKSOURCE_EXT) \|\|\
NYX	0:85b3fd62ea1a	7057	((SOURCE) == RCC_SAIACLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	7058	((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
NYX	0:85b3fd62ea1a	7059
NYX	0:85b3fd62ea1a	7060	#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) \|\|\
NYX	0:85b3fd62ea1a	7061	((SOURCE) == RCC_SAIBCLKSOURCE_EXT) \|\|\
NYX	0:85b3fd62ea1a	7062	((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) \|\|\
NYX	0:85b3fd62ea1a	7063	((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
NYX	0:85b3fd62ea1a	7064
NYX	0:85b3fd62ea1a	7065	#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
NYX	0:85b3fd62ea1a	7066
NYX	0:85b3fd62ea1a	7067	#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
NYX	0:85b3fd62ea1a	7068
NYX	0:85b3fd62ea1a	7069	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	7070	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	7071
NYX	0:85b3fd62ea1a	7072	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
NYX	0:85b3fd62ea1a	7073	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
NYX	0:85b3fd62ea1a	7074	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
NYX	0:85b3fd62ea1a	7075	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
NYX	0:85b3fd62ea1a	7076	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	7077
NYX	0:85b3fd62ea1a	7078	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
NYX	0:85b3fd62ea1a	7079	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
NYX	0:85b3fd62ea1a	7080
NYX	0:85b3fd62ea1a	7081	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
NYX	0:85b3fd62ea1a	7082	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| \
NYX	0:85b3fd62ea1a	7083	STM32F412Rx */
NYX	0:85b3fd62ea1a	7084
NYX	0:85b3fd62ea1a	7085	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	7086	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
NYX	0:85b3fd62ea1a	7087	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
NYX	0:85b3fd62ea1a	7088	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	7089	/**
NYX	0:85b3fd62ea1a	7090	* @}
NYX	0:85b3fd62ea1a	7091	*/
NYX	0:85b3fd62ea1a	7092
NYX	0:85b3fd62ea1a	7093	/**
NYX	0:85b3fd62ea1a	7094	* @}
NYX	0:85b3fd62ea1a	7095	*/
NYX	0:85b3fd62ea1a	7096
NYX	0:85b3fd62ea1a	7097	/**
NYX	0:85b3fd62ea1a	7098	* @}
NYX	0:85b3fd62ea1a	7099	*/
NYX	0:85b3fd62ea1a	7100
NYX	0:85b3fd62ea1a	7101	/**
NYX	0:85b3fd62ea1a	7102	* @}
NYX	0:85b3fd62ea1a	7103	*/
NYX	0:85b3fd62ea1a	7104	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	7105	}
NYX	0:85b3fd62ea1a	7106	#endif
NYX	0:85b3fd62ea1a	7107
NYX	0:85b3fd62ea1a	7108	#endif /* __STM32F4xx_HAL_RCC_EX_H */
NYX	0:85b3fd62ea1a	7109
NYX	0:85b3fd62ea1a	7110	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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