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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_hal_rcc_ex.c
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Extension RCC HAL module driver.
NYX	0:85b3fd62ea1a	8	* This file provides firmware functions to manage the following
NYX	0:85b3fd62ea1a	9	* functionalities RCC extension peripheral:
NYX	0:85b3fd62ea1a	10	* + Extended Peripheral Control functions
NYX	0:85b3fd62ea1a	11	*
NYX	0:85b3fd62ea1a	12	******************************************************************************
NYX	0:85b3fd62ea1a	13	* @attention
NYX	0:85b3fd62ea1a	14	*
NYX	0:85b3fd62ea1a	15	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	16	*
NYX	0:85b3fd62ea1a	17	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	18	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	19	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	20	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	21	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	22	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	23	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	24	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	25	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	26	* without specific prior written permission.
NYX	0:85b3fd62ea1a	27	*
NYX	0:85b3fd62ea1a	28	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	29	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	30	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	31	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	32	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	34	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	35	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	36	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	37	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	38	*
NYX	0:85b3fd62ea1a	39	******************************************************************************
NYX	0:85b3fd62ea1a	40	*/
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	43	#include "stm32f4xx_hal.h"
NYX	0:85b3fd62ea1a	44
NYX	0:85b3fd62ea1a	45	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	46	* @{
NYX	0:85b3fd62ea1a	47	*/
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @defgroup RCCEx RCCEx
NYX	0:85b3fd62ea1a	50	* @brief RCCEx HAL module driver
NYX	0:85b3fd62ea1a	51	* @{
NYX	0:85b3fd62ea1a	52	*/
NYX	0:85b3fd62ea1a	53
NYX	0:85b3fd62ea1a	54	#ifdef HAL_RCC_MODULE_ENABLED
NYX	0:85b3fd62ea1a	55
NYX	0:85b3fd62ea1a	56	/* Private typedef -----------------------------------------------------------*/
NYX	0:85b3fd62ea1a	57	/* Private define ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	58	/** @addtogroup RCCEx_Private_Constants
NYX	0:85b3fd62ea1a	59	* @{
NYX	0:85b3fd62ea1a	60	*/
NYX	0:85b3fd62ea1a	61	/**
NYX	0:85b3fd62ea1a	62	* @}
NYX	0:85b3fd62ea1a	63	*/
NYX	0:85b3fd62ea1a	64	/* Private macro -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	65	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	66	/* Private function prototypes -----------------------------------------------*/
NYX	0:85b3fd62ea1a	67	/* Private functions ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	68	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
NYX	0:85b3fd62ea1a	69	* @{
NYX	0:85b3fd62ea1a	70	*/
NYX	0:85b3fd62ea1a	71
NYX	0:85b3fd62ea1a	72	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
NYX	0:85b3fd62ea1a	73	* @brief Extended Peripheral Control functions
NYX	0:85b3fd62ea1a	74	*
NYX	0:85b3fd62ea1a	75	@verbatim
NYX	0:85b3fd62ea1a	76	===============================================================================
NYX	0:85b3fd62ea1a	77	##### Extended Peripheral Control functions #####
NYX	0:85b3fd62ea1a	78	===============================================================================
NYX	0:85b3fd62ea1a	79	[..]
NYX	0:85b3fd62ea1a	80	This subsection provides a set of functions allowing to control the RCC Clocks
NYX	0:85b3fd62ea1a	81	frequencies.
NYX	0:85b3fd62ea1a	82	[..]
NYX	0:85b3fd62ea1a	83	(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
NYX	0:85b3fd62ea1a	84	select the RTC clock source; in this case the Backup domain will be reset in
NYX	0:85b3fd62ea1a	85	order to modify the RTC Clock source, as consequence RTC registers (including
NYX	0:85b3fd62ea1a	86	the backup registers) and RCC_BDCR register are set to their reset values.
NYX	0:85b3fd62ea1a	87
NYX	0:85b3fd62ea1a	88	@endverbatim
NYX	0:85b3fd62ea1a	89	* @{
NYX	0:85b3fd62ea1a	90	*/
NYX	0:85b3fd62ea1a	91
NYX	0:85b3fd62ea1a	92	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	93	/**
NYX	0:85b3fd62ea1a	94	* @brief Initializes the RCC extended peripherals clocks according to the specified
NYX	0:85b3fd62ea1a	95	* parameters in the RCC_PeriphCLKInitTypeDef.
NYX	0:85b3fd62ea1a	96	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	97	* contains the configuration information for the Extended Peripherals
NYX	0:85b3fd62ea1a	98	* clocks(I2S, SAI, LTDC RTC and TIM).
NYX	0:85b3fd62ea1a	99	*
NYX	0:85b3fd62ea1a	100	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
NYX	0:85b3fd62ea1a	101	* the RTC clock source; in this case the Backup domain will be reset in
NYX	0:85b3fd62ea1a	102	* order to modify the RTC Clock source, as consequence RTC registers (including
NYX	0:85b3fd62ea1a	103	* the backup registers) and RCC_BDCR register are set to their reset values.
NYX	0:85b3fd62ea1a	104	*
NYX	0:85b3fd62ea1a	105	* @retval HAL status
NYX	0:85b3fd62ea1a	106	*/
NYX	0:85b3fd62ea1a	107	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	108	{
NYX	0:85b3fd62ea1a	109	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	110	uint32_t tmpreg1 = 0U;
NYX	0:85b3fd62ea1a	111	uint32_t plli2sp = 0U;
NYX	0:85b3fd62ea1a	112	uint32_t plli2sq = 0U;
NYX	0:85b3fd62ea1a	113	uint32_t plli2sr = 0U;
NYX	0:85b3fd62ea1a	114	uint32_t pllsaip = 0U;
NYX	0:85b3fd62ea1a	115	uint32_t pllsaiq = 0U;
NYX	0:85b3fd62ea1a	116	uint32_t plli2sused = 0U;
NYX	0:85b3fd62ea1a	117	uint32_t pllsaiused = 0U;
NYX	0:85b3fd62ea1a	118
NYX	0:85b3fd62ea1a	119	/* Check the peripheral clock selection parameters */
NYX	0:85b3fd62ea1a	120	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
NYX	0:85b3fd62ea1a	121
NYX	0:85b3fd62ea1a	122	/------------------------ I2S APB1 configuration --------------------------/
NYX	0:85b3fd62ea1a	123	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
NYX	0:85b3fd62ea1a	124	{
NYX	0:85b3fd62ea1a	125	/* Check the parameters */
NYX	0:85b3fd62ea1a	126	assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
NYX	0:85b3fd62ea1a	127
NYX	0:85b3fd62ea1a	128	/* Configure I2S Clock source */
NYX	0:85b3fd62ea1a	129	__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
NYX	0:85b3fd62ea1a	130	/* Enable the PLLI2S when it's used as clock source for I2S */
NYX	0:85b3fd62ea1a	131	if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
NYX	0:85b3fd62ea1a	132	{
NYX	0:85b3fd62ea1a	133	plli2sused = 1U;
NYX	0:85b3fd62ea1a	134	}
NYX	0:85b3fd62ea1a	135	}
NYX	0:85b3fd62ea1a	136	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	137
NYX	0:85b3fd62ea1a	138	/---------------------------- I2S APB2 configuration ----------------------/
NYX	0:85b3fd62ea1a	139	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
NYX	0:85b3fd62ea1a	140	{
NYX	0:85b3fd62ea1a	141	/* Check the parameters */
NYX	0:85b3fd62ea1a	142	assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
NYX	0:85b3fd62ea1a	143
NYX	0:85b3fd62ea1a	144	/* Configure I2S Clock source */
NYX	0:85b3fd62ea1a	145	__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
NYX	0:85b3fd62ea1a	146	/* Enable the PLLI2S when it's used as clock source for I2S */
NYX	0:85b3fd62ea1a	147	if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
NYX	0:85b3fd62ea1a	148	{
NYX	0:85b3fd62ea1a	149	plli2sused = 1U;
NYX	0:85b3fd62ea1a	150	}
NYX	0:85b3fd62ea1a	151	}
NYX	0:85b3fd62ea1a	152	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	153
NYX	0:85b3fd62ea1a	154	/--------------------------- SAI1 configuration ---------------------------/
NYX	0:85b3fd62ea1a	155	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
NYX	0:85b3fd62ea1a	156	{
NYX	0:85b3fd62ea1a	157	/* Check the parameters */
NYX	0:85b3fd62ea1a	158	assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
NYX	0:85b3fd62ea1a	159
NYX	0:85b3fd62ea1a	160	/* Configure SAI1 Clock source */
NYX	0:85b3fd62ea1a	161	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
NYX	0:85b3fd62ea1a	162	/* Enable the PLLI2S when it's used as clock source for SAI */
NYX	0:85b3fd62ea1a	163	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
NYX	0:85b3fd62ea1a	164	{
NYX	0:85b3fd62ea1a	165	plli2sused = 1U;
NYX	0:85b3fd62ea1a	166	}
NYX	0:85b3fd62ea1a	167	/* Enable the PLLSAI when it's used as clock source for SAI */
NYX	0:85b3fd62ea1a	168	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
NYX	0:85b3fd62ea1a	169	{
NYX	0:85b3fd62ea1a	170	pllsaiused = 1U;
NYX	0:85b3fd62ea1a	171	}
NYX	0:85b3fd62ea1a	172	}
NYX	0:85b3fd62ea1a	173	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	174
NYX	0:85b3fd62ea1a	175	/-------------------------- SAI2 configuration ----------------------------/
NYX	0:85b3fd62ea1a	176	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
NYX	0:85b3fd62ea1a	177	{
NYX	0:85b3fd62ea1a	178	/* Check the parameters */
NYX	0:85b3fd62ea1a	179	assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
NYX	0:85b3fd62ea1a	180
NYX	0:85b3fd62ea1a	181	/* Configure SAI2 Clock source */
NYX	0:85b3fd62ea1a	182	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
NYX	0:85b3fd62ea1a	183
NYX	0:85b3fd62ea1a	184	/* Enable the PLLI2S when it's used as clock source for SAI */
NYX	0:85b3fd62ea1a	185	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
NYX	0:85b3fd62ea1a	186	{
NYX	0:85b3fd62ea1a	187	plli2sused = 1U;
NYX	0:85b3fd62ea1a	188	}
NYX	0:85b3fd62ea1a	189	/* Enable the PLLSAI when it's used as clock source for SAI */
NYX	0:85b3fd62ea1a	190	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
NYX	0:85b3fd62ea1a	191	{
NYX	0:85b3fd62ea1a	192	pllsaiused = 1U;
NYX	0:85b3fd62ea1a	193	}
NYX	0:85b3fd62ea1a	194	}
NYX	0:85b3fd62ea1a	195	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	196
NYX	0:85b3fd62ea1a	197	/----------------------------- RTC configuration --------------------------/
NYX	0:85b3fd62ea1a	198	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
NYX	0:85b3fd62ea1a	199	{
NYX	0:85b3fd62ea1a	200	/* Check for RTC Parameters used to output RTCCLK */
NYX	0:85b3fd62ea1a	201	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
NYX	0:85b3fd62ea1a	202
NYX	0:85b3fd62ea1a	203	/* Enable Power Clock*/
NYX	0:85b3fd62ea1a	204	__HAL_RCC_PWR_CLK_ENABLE();
NYX	0:85b3fd62ea1a	205
NYX	0:85b3fd62ea1a	206	/* Enable write access to Backup domain */
NYX	0:85b3fd62ea1a	207	PWR->CR \|= PWR_CR_DBP;
NYX	0:85b3fd62ea1a	208
NYX	0:85b3fd62ea1a	209	/* Get tick */
NYX	0:85b3fd62ea1a	210	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	211
NYX	0:85b3fd62ea1a	212	while((PWR->CR & PWR_CR_DBP) == RESET)
NYX	0:85b3fd62ea1a	213	{
NYX	0:85b3fd62ea1a	214	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	215	{
NYX	0:85b3fd62ea1a	216	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	217	}
NYX	0:85b3fd62ea1a	218	}
NYX	0:85b3fd62ea1a	219	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
NYX	0:85b3fd62ea1a	220	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
NYX	0:85b3fd62ea1a	221	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
NYX	0:85b3fd62ea1a	222	{
NYX	0:85b3fd62ea1a	223	/* Store the content of BDCR register before the reset of Backup Domain */
NYX	0:85b3fd62ea1a	224	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	225	/* RTC Clock selection can be changed only if the Backup Domain is reset */
NYX	0:85b3fd62ea1a	226	__HAL_RCC_BACKUPRESET_FORCE();
NYX	0:85b3fd62ea1a	227	__HAL_RCC_BACKUPRESET_RELEASE();
NYX	0:85b3fd62ea1a	228	/* Restore the Content of BDCR register */
NYX	0:85b3fd62ea1a	229	RCC->BDCR = tmpreg1;
NYX	0:85b3fd62ea1a	230
NYX	0:85b3fd62ea1a	231	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
NYX	0:85b3fd62ea1a	232	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
NYX	0:85b3fd62ea1a	233	{
NYX	0:85b3fd62ea1a	234	/* Get tick */
NYX	0:85b3fd62ea1a	235	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	236
NYX	0:85b3fd62ea1a	237	/* Wait till LSE is ready */
NYX	0:85b3fd62ea1a	238	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
NYX	0:85b3fd62ea1a	239	{
NYX	0:85b3fd62ea1a	240	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	241	{
NYX	0:85b3fd62ea1a	242	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	243	}
NYX	0:85b3fd62ea1a	244	}
NYX	0:85b3fd62ea1a	245	}
NYX	0:85b3fd62ea1a	246	}
NYX	0:85b3fd62ea1a	247	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
NYX	0:85b3fd62ea1a	248	}
NYX	0:85b3fd62ea1a	249	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	250
NYX	0:85b3fd62ea1a	251	/---------------------------- TIM configuration ---------------------------/
NYX	0:85b3fd62ea1a	252	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
NYX	0:85b3fd62ea1a	253	{
NYX	0:85b3fd62ea1a	254	/* Configure Timer Prescaler */
NYX	0:85b3fd62ea1a	255	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
NYX	0:85b3fd62ea1a	256	}
NYX	0:85b3fd62ea1a	257	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	258
NYX	0:85b3fd62ea1a	259	/---------------------------- FMPI2C1 Configuration -----------------------/
NYX	0:85b3fd62ea1a	260	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
NYX	0:85b3fd62ea1a	261	{
NYX	0:85b3fd62ea1a	262	/* Check the parameters */
NYX	0:85b3fd62ea1a	263	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
NYX	0:85b3fd62ea1a	264
NYX	0:85b3fd62ea1a	265	/* Configure the FMPI2C1 clock source */
NYX	0:85b3fd62ea1a	266	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
NYX	0:85b3fd62ea1a	267	}
NYX	0:85b3fd62ea1a	268	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	269
NYX	0:85b3fd62ea1a	270	/------------------------------ CEC Configuration -------------------------/
NYX	0:85b3fd62ea1a	271	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
NYX	0:85b3fd62ea1a	272	{
NYX	0:85b3fd62ea1a	273	/* Check the parameters */
NYX	0:85b3fd62ea1a	274	assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
NYX	0:85b3fd62ea1a	275
NYX	0:85b3fd62ea1a	276	/* Configure the CEC clock source */
NYX	0:85b3fd62ea1a	277	__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
NYX	0:85b3fd62ea1a	278	}
NYX	0:85b3fd62ea1a	279	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	280
NYX	0:85b3fd62ea1a	281	/----------------------------- CLK48 Configuration ------------------------/
NYX	0:85b3fd62ea1a	282	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
NYX	0:85b3fd62ea1a	283	{
NYX	0:85b3fd62ea1a	284	/* Check the parameters */
NYX	0:85b3fd62ea1a	285	assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
NYX	0:85b3fd62ea1a	286
NYX	0:85b3fd62ea1a	287	/* Configure the CLK48 clock source */
NYX	0:85b3fd62ea1a	288	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
NYX	0:85b3fd62ea1a	289
NYX	0:85b3fd62ea1a	290	/* Enable the PLLSAI when it's used as clock source for CLK48 */
NYX	0:85b3fd62ea1a	291	if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
NYX	0:85b3fd62ea1a	292	{
NYX	0:85b3fd62ea1a	293	pllsaiused = 1U;
NYX	0:85b3fd62ea1a	294	}
NYX	0:85b3fd62ea1a	295	}
NYX	0:85b3fd62ea1a	296	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	297
NYX	0:85b3fd62ea1a	298	/----------------------------- SDIO Configuration -------------------------/
NYX	0:85b3fd62ea1a	299	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
NYX	0:85b3fd62ea1a	300	{
NYX	0:85b3fd62ea1a	301	/* Check the parameters */
NYX	0:85b3fd62ea1a	302	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
NYX	0:85b3fd62ea1a	303
NYX	0:85b3fd62ea1a	304	/* Configure the SDIO clock source */
NYX	0:85b3fd62ea1a	305	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
NYX	0:85b3fd62ea1a	306	}
NYX	0:85b3fd62ea1a	307	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	308
NYX	0:85b3fd62ea1a	309	/------------------------------ SPDIFRX Configuration ---------------------/
NYX	0:85b3fd62ea1a	310	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
NYX	0:85b3fd62ea1a	311	{
NYX	0:85b3fd62ea1a	312	/* Check the parameters */
NYX	0:85b3fd62ea1a	313	assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
NYX	0:85b3fd62ea1a	314
NYX	0:85b3fd62ea1a	315	/* Configure the SPDIFRX clock source */
NYX	0:85b3fd62ea1a	316	__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
NYX	0:85b3fd62ea1a	317	/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
NYX	0:85b3fd62ea1a	318	if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
NYX	0:85b3fd62ea1a	319	{
NYX	0:85b3fd62ea1a	320	plli2sused = 1U;
NYX	0:85b3fd62ea1a	321	}
NYX	0:85b3fd62ea1a	322	}
NYX	0:85b3fd62ea1a	323	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	324
NYX	0:85b3fd62ea1a	325	/---------------------------- PLLI2S Configuration ------------------------/
NYX	0:85b3fd62ea1a	326	/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
NYX	0:85b3fd62ea1a	327	I2S on APB2 or SPDIFRX */
NYX	0:85b3fd62ea1a	328	if((plli2sused == 1U) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
NYX	0:85b3fd62ea1a	329	{
NYX	0:85b3fd62ea1a	330	/* Disable the PLLI2S */
NYX	0:85b3fd62ea1a	331	__HAL_RCC_PLLI2S_DISABLE();
NYX	0:85b3fd62ea1a	332	/* Get tick */
NYX	0:85b3fd62ea1a	333	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	334	/* Wait till PLLI2S is disabled */
NYX	0:85b3fd62ea1a	335	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
NYX	0:85b3fd62ea1a	336	{
NYX	0:85b3fd62ea1a	337	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	338	{
NYX	0:85b3fd62ea1a	339	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	340	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	341	}
NYX	0:85b3fd62ea1a	342	}
NYX	0:85b3fd62ea1a	343
NYX	0:85b3fd62ea1a	344	/* check for common PLLI2S Parameters */
NYX	0:85b3fd62ea1a	345	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
NYX	0:85b3fd62ea1a	346	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
NYX	0:85b3fd62ea1a	347
NYX	0:85b3fd62ea1a	348	/------ In Case of PLLI2S is selected as source clock for I2S -----------/
NYX	0:85b3fd62ea1a	349	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) \|\|
NYX	0:85b3fd62ea1a	350	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
NYX	0:85b3fd62ea1a	351	{
NYX	0:85b3fd62ea1a	352	/* check for Parameters */
NYX	0:85b3fd62ea1a	353	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
NYX	0:85b3fd62ea1a	354
NYX	0:85b3fd62ea1a	355	/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
NYX	0:85b3fd62ea1a	356	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
NYX	0:85b3fd62ea1a	357	plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
NYX	0:85b3fd62ea1a	358	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	359	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
NYX	0:85b3fd62ea1a	360	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
NYX	0:85b3fd62ea1a	361	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	362	}
NYX	0:85b3fd62ea1a	363
NYX	0:85b3fd62ea1a	364	/------- In Case of PLLI2S is selected as source clock for SAI ----------/
NYX	0:85b3fd62ea1a	365	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) \|\|
NYX	0:85b3fd62ea1a	366	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
NYX	0:85b3fd62ea1a	367	{
NYX	0:85b3fd62ea1a	368	/* Check for PLLI2S Parameters */
NYX	0:85b3fd62ea1a	369	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
NYX	0:85b3fd62ea1a	370	/* Check for PLLI2S/DIVQ parameters */
NYX	0:85b3fd62ea1a	371	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
NYX	0:85b3fd62ea1a	372
NYX	0:85b3fd62ea1a	373	/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
NYX	0:85b3fd62ea1a	374	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
NYX	0:85b3fd62ea1a	375	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	376	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	377	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
NYX	0:85b3fd62ea1a	378	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	379	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
NYX	0:85b3fd62ea1a	380	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
NYX	0:85b3fd62ea1a	381
NYX	0:85b3fd62ea1a	382	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	383	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
NYX	0:85b3fd62ea1a	384	}
NYX	0:85b3fd62ea1a	385
NYX	0:85b3fd62ea1a	386	/------ In Case of PLLI2S is selected as source clock for SPDIFRX -------/
NYX	0:85b3fd62ea1a	387	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
NYX	0:85b3fd62ea1a	388	{
NYX	0:85b3fd62ea1a	389	/* check for Parameters */
NYX	0:85b3fd62ea1a	390	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
NYX	0:85b3fd62ea1a	391	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	392	plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
NYX	0:85b3fd62ea1a	393	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	394	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	395	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
NYX	0:85b3fd62ea1a	396	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
NYX	0:85b3fd62ea1a	397	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
NYX	0:85b3fd62ea1a	398	}
NYX	0:85b3fd62ea1a	399
NYX	0:85b3fd62ea1a	400	/----------------- In Case of PLLI2S is just selected -----------------/
NYX	0:85b3fd62ea1a	401	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
NYX	0:85b3fd62ea1a	402	{
NYX	0:85b3fd62ea1a	403	/* Check for Parameters */
NYX	0:85b3fd62ea1a	404	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
NYX	0:85b3fd62ea1a	405	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
NYX	0:85b3fd62ea1a	406	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
NYX	0:85b3fd62ea1a	407
NYX	0:85b3fd62ea1a	408	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	409	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
NYX	0:85b3fd62ea1a	410	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	411	}
NYX	0:85b3fd62ea1a	412
NYX	0:85b3fd62ea1a	413	/* Enable the PLLI2S */
NYX	0:85b3fd62ea1a	414	__HAL_RCC_PLLI2S_ENABLE();
NYX	0:85b3fd62ea1a	415	/* Get tick */
NYX	0:85b3fd62ea1a	416	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	417	/* Wait till PLLI2S is ready */
NYX	0:85b3fd62ea1a	418	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
NYX	0:85b3fd62ea1a	419	{
NYX	0:85b3fd62ea1a	420	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	421	{
NYX	0:85b3fd62ea1a	422	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	423	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	424	}
NYX	0:85b3fd62ea1a	425	}
NYX	0:85b3fd62ea1a	426	}
NYX	0:85b3fd62ea1a	427	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	428
NYX	0:85b3fd62ea1a	429	/----------------------------- PLLSAI Configuration -----------------------/
NYX	0:85b3fd62ea1a	430	/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
NYX	0:85b3fd62ea1a	431	if(pllsaiused == 1U)
NYX	0:85b3fd62ea1a	432	{
NYX	0:85b3fd62ea1a	433	/* Disable PLLSAI Clock */
NYX	0:85b3fd62ea1a	434	__HAL_RCC_PLLSAI_DISABLE();
NYX	0:85b3fd62ea1a	435	/* Get tick */
NYX	0:85b3fd62ea1a	436	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	437	/* Wait till PLLSAI is disabled */
NYX	0:85b3fd62ea1a	438	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
NYX	0:85b3fd62ea1a	439	{
NYX	0:85b3fd62ea1a	440	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	441	{
NYX	0:85b3fd62ea1a	442	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	443	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	444	}
NYX	0:85b3fd62ea1a	445	}
NYX	0:85b3fd62ea1a	446
NYX	0:85b3fd62ea1a	447	/* Check the PLLSAI division factors */
NYX	0:85b3fd62ea1a	448	assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
NYX	0:85b3fd62ea1a	449	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
NYX	0:85b3fd62ea1a	450
NYX	0:85b3fd62ea1a	451	/------ In Case of PLLSAI is selected as source clock for SAI -----------/
NYX	0:85b3fd62ea1a	452	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) \|\|
NYX	0:85b3fd62ea1a	453	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
NYX	0:85b3fd62ea1a	454	{
NYX	0:85b3fd62ea1a	455	/* check for PLLSAIQ Parameter */
NYX	0:85b3fd62ea1a	456	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
NYX	0:85b3fd62ea1a	457	/* check for PLLSAI/DIVQ Parameter */
NYX	0:85b3fd62ea1a	458	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
NYX	0:85b3fd62ea1a	459
NYX	0:85b3fd62ea1a	460	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
NYX	0:85b3fd62ea1a	461	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
NYX	0:85b3fd62ea1a	462	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	463	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
NYX	0:85b3fd62ea1a	464	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
NYX	0:85b3fd62ea1a	465	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
NYX	0:85b3fd62ea1a	466
NYX	0:85b3fd62ea1a	467	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
NYX	0:85b3fd62ea1a	468	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
NYX	0:85b3fd62ea1a	469	}
NYX	0:85b3fd62ea1a	470
NYX	0:85b3fd62ea1a	471	/------ In Case of PLLSAI is selected as source clock for CLK48 ---------/
NYX	0:85b3fd62ea1a	472	/* In Case of PLLI2S is selected as source clock for CLK48 */
NYX	0:85b3fd62ea1a	473	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
NYX	0:85b3fd62ea1a	474	{
NYX	0:85b3fd62ea1a	475	/* check for Parameters */
NYX	0:85b3fd62ea1a	476	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
NYX	0:85b3fd62ea1a	477	/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	478	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
NYX	0:85b3fd62ea1a	479	/* Configure the PLLSAI division factors */
NYX	0:85b3fd62ea1a	480	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
NYX	0:85b3fd62ea1a	481	/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
NYX	0:85b3fd62ea1a	482	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
NYX	0:85b3fd62ea1a	483	}
NYX	0:85b3fd62ea1a	484
NYX	0:85b3fd62ea1a	485	/* Enable PLLSAI Clock */
NYX	0:85b3fd62ea1a	486	__HAL_RCC_PLLSAI_ENABLE();
NYX	0:85b3fd62ea1a	487	/* Get tick */
NYX	0:85b3fd62ea1a	488	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	489	/* Wait till PLLSAI is ready */
NYX	0:85b3fd62ea1a	490	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
NYX	0:85b3fd62ea1a	491	{
NYX	0:85b3fd62ea1a	492	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	493	{
NYX	0:85b3fd62ea1a	494	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	495	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	496	}
NYX	0:85b3fd62ea1a	497	}
NYX	0:85b3fd62ea1a	498	}
NYX	0:85b3fd62ea1a	499	return HAL_OK;
NYX	0:85b3fd62ea1a	500	}
NYX	0:85b3fd62ea1a	501
NYX	0:85b3fd62ea1a	502	/**
NYX	0:85b3fd62ea1a	503	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
NYX	0:85b3fd62ea1a	504	* RCC configuration registers.
NYX	0:85b3fd62ea1a	505	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	506	* will be configured.
NYX	0:85b3fd62ea1a	507	* @retval None
NYX	0:85b3fd62ea1a	508	*/
NYX	0:85b3fd62ea1a	509	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	510	{
NYX	0:85b3fd62ea1a	511	uint32_t tempreg;
NYX	0:85b3fd62ea1a	512
NYX	0:85b3fd62ea1a	513	/* Set all possible values for the extended clock type parameter------------*/
NYX	0:85b3fd62ea1a	514	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
NYX	0:85b3fd62ea1a	515	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
NYX	0:85b3fd62ea1a	516	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
NYX	0:85b3fd62ea1a	517	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_FMPI2C1 \|\
NYX	0:85b3fd62ea1a	518	RCC_PERIPHCLK_CLK48 \| RCC_PERIPHCLK_SDIO \|\
NYX	0:85b3fd62ea1a	519	RCC_PERIPHCLK_SPDIFRX;
NYX	0:85b3fd62ea1a	520
NYX	0:85b3fd62ea1a	521	/* Get the PLLI2S Clock configuration --------------------------------------*/
NYX	0:85b3fd62ea1a	522	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	523	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
NYX	0:85b3fd62ea1a	524	PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
NYX	0:85b3fd62ea1a	525	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
NYX	0:85b3fd62ea1a	526	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	527	/* Get the PLLSAI Clock configuration --------------------------------------*/
NYX	0:85b3fd62ea1a	528	PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
NYX	0:85b3fd62ea1a	529	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
NYX	0:85b3fd62ea1a	530	PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
NYX	0:85b3fd62ea1a	531	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
NYX	0:85b3fd62ea1a	532	/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
NYX	0:85b3fd62ea1a	533	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
NYX	0:85b3fd62ea1a	534	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
NYX	0:85b3fd62ea1a	535
NYX	0:85b3fd62ea1a	536	/* Get the SAI1 clock configuration ----------------------------------------*/
NYX	0:85b3fd62ea1a	537	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
NYX	0:85b3fd62ea1a	538
NYX	0:85b3fd62ea1a	539	/* Get the SAI2 clock configuration ----------------------------------------*/
NYX	0:85b3fd62ea1a	540	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
NYX	0:85b3fd62ea1a	541
NYX	0:85b3fd62ea1a	542	/* Get the I2S APB1 clock configuration ------------------------------------*/
NYX	0:85b3fd62ea1a	543	PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
NYX	0:85b3fd62ea1a	544
NYX	0:85b3fd62ea1a	545	/* Get the I2S APB2 clock configuration ------------------------------------*/
NYX	0:85b3fd62ea1a	546	PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
NYX	0:85b3fd62ea1a	547
NYX	0:85b3fd62ea1a	548	/* Get the RTC Clock configuration -----------------------------------------*/
NYX	0:85b3fd62ea1a	549	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
NYX	0:85b3fd62ea1a	550	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	551
NYX	0:85b3fd62ea1a	552	/* Get the CEC clock configuration -----------------------------------------*/
NYX	0:85b3fd62ea1a	553	PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
NYX	0:85b3fd62ea1a	554
NYX	0:85b3fd62ea1a	555	/* Get the FMPI2C1 clock configuration -------------------------------------*/
NYX	0:85b3fd62ea1a	556	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
NYX	0:85b3fd62ea1a	557
NYX	0:85b3fd62ea1a	558	/* Get the CLK48 clock configuration ----------------------------------------*/
NYX	0:85b3fd62ea1a	559	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
NYX	0:85b3fd62ea1a	560
NYX	0:85b3fd62ea1a	561	/* Get the SDIO clock configuration ----------------------------------------*/
NYX	0:85b3fd62ea1a	562	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
NYX	0:85b3fd62ea1a	563
NYX	0:85b3fd62ea1a	564	/* Get the SPDIFRX clock configuration -------------------------------------*/
NYX	0:85b3fd62ea1a	565	PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
NYX	0:85b3fd62ea1a	566
NYX	0:85b3fd62ea1a	567	/* Get the TIM Prescaler configuration -------------------------------------*/
NYX	0:85b3fd62ea1a	568	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
NYX	0:85b3fd62ea1a	569	{
NYX	0:85b3fd62ea1a	570	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
NYX	0:85b3fd62ea1a	571	}
NYX	0:85b3fd62ea1a	572	else
NYX	0:85b3fd62ea1a	573	{
NYX	0:85b3fd62ea1a	574	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
NYX	0:85b3fd62ea1a	575	}
NYX	0:85b3fd62ea1a	576	}
NYX	0:85b3fd62ea1a	577
NYX	0:85b3fd62ea1a	578	/**
NYX	0:85b3fd62ea1a	579	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
NYX	0:85b3fd62ea1a	580	* @note Return 0 if peripheral clock identifier not managed by this API
NYX	0:85b3fd62ea1a	581	* @param PeriphClk: Peripheral clock identifier
NYX	0:85b3fd62ea1a	582	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	583	* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
NYX	0:85b3fd62ea1a	584	* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
NYX	0:85b3fd62ea1a	585	* @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
NYX	0:85b3fd62ea1a	586	* @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
NYX	0:85b3fd62ea1a	587	* @retval Frequency in KHz
NYX	0:85b3fd62ea1a	588	*/
NYX	0:85b3fd62ea1a	589	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
NYX	0:85b3fd62ea1a	590	{
NYX	0:85b3fd62ea1a	591	uint32_t tmpreg1 = 0U;
NYX	0:85b3fd62ea1a	592	/* This variable used to store the SAI clock frequency (value in Hz) */
NYX	0:85b3fd62ea1a	593	uint32_t frequency = 0U;
NYX	0:85b3fd62ea1a	594	/* This variable used to store the VCO Input (value in Hz) */
NYX	0:85b3fd62ea1a	595	uint32_t vcoinput = 0U;
NYX	0:85b3fd62ea1a	596	/* This variable used to store the SAI clock source */
NYX	0:85b3fd62ea1a	597	uint32_t saiclocksource = 0U;
NYX	0:85b3fd62ea1a	598	uint32_t srcclk = 0U;
NYX	0:85b3fd62ea1a	599	/* This variable used to store the VCO Output (value in Hz) */
NYX	0:85b3fd62ea1a	600	uint32_t vcooutput = 0U;
NYX	0:85b3fd62ea1a	601	switch (PeriphClk)
NYX	0:85b3fd62ea1a	602	{
NYX	0:85b3fd62ea1a	603	case RCC_PERIPHCLK_SAI1:
NYX	0:85b3fd62ea1a	604	case RCC_PERIPHCLK_SAI2:
NYX	0:85b3fd62ea1a	605	{
NYX	0:85b3fd62ea1a	606	saiclocksource = RCC->DCKCFGR;
NYX	0:85b3fd62ea1a	607	saiclocksource &= (RCC_DCKCFGR_SAI1SRC \| RCC_DCKCFGR_SAI2SRC);
NYX	0:85b3fd62ea1a	608	switch (saiclocksource)
NYX	0:85b3fd62ea1a	609	{
NYX	0:85b3fd62ea1a	610	case 0U: /* PLLSAI is the clock source for SAI*/
NYX	0:85b3fd62ea1a	611	{
NYX	0:85b3fd62ea1a	612	/* Configure the PLLSAI division factor */
NYX	0:85b3fd62ea1a	613	/* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
NYX	0:85b3fd62ea1a	614	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
NYX	0:85b3fd62ea1a	615	{
NYX	0:85b3fd62ea1a	616	/* In Case the PLL Source is HSI (Internal Clock) */
NYX	0:85b3fd62ea1a	617	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
NYX	0:85b3fd62ea1a	618	}
NYX	0:85b3fd62ea1a	619	else
NYX	0:85b3fd62ea1a	620	{
NYX	0:85b3fd62ea1a	621	/* In Case the PLL Source is HSE (External Clock) */
NYX	0:85b3fd62ea1a	622	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
NYX	0:85b3fd62ea1a	623	}
NYX	0:85b3fd62ea1a	624	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
NYX	0:85b3fd62ea1a	625	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
NYX	0:85b3fd62ea1a	626	tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
NYX	0:85b3fd62ea1a	627	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
NYX	0:85b3fd62ea1a	628
NYX	0:85b3fd62ea1a	629	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
NYX	0:85b3fd62ea1a	630	tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
NYX	0:85b3fd62ea1a	631	frequency = frequency/(tmpreg1);
NYX	0:85b3fd62ea1a	632	break;
NYX	0:85b3fd62ea1a	633	}
NYX	0:85b3fd62ea1a	634	case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
NYX	0:85b3fd62ea1a	635	case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
NYX	0:85b3fd62ea1a	636	{
NYX	0:85b3fd62ea1a	637	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	638	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
NYX	0:85b3fd62ea1a	639	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
NYX	0:85b3fd62ea1a	640	{
NYX	0:85b3fd62ea1a	641	/* In Case the PLL Source is HSI (Internal Clock) */
NYX	0:85b3fd62ea1a	642	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	643	}
NYX	0:85b3fd62ea1a	644	else
NYX	0:85b3fd62ea1a	645	{
NYX	0:85b3fd62ea1a	646	/* In Case the PLL Source is HSE (External Clock) */
NYX	0:85b3fd62ea1a	647	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
NYX	0:85b3fd62ea1a	648	}
NYX	0:85b3fd62ea1a	649
NYX	0:85b3fd62ea1a	650	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	651	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
NYX	0:85b3fd62ea1a	652	tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
NYX	0:85b3fd62ea1a	653	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
NYX	0:85b3fd62ea1a	654
NYX	0:85b3fd62ea1a	655	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	656	tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
NYX	0:85b3fd62ea1a	657	frequency = frequency/(tmpreg1);
NYX	0:85b3fd62ea1a	658	break;
NYX	0:85b3fd62ea1a	659	}
NYX	0:85b3fd62ea1a	660	case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
NYX	0:85b3fd62ea1a	661	case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
NYX	0:85b3fd62ea1a	662	{
NYX	0:85b3fd62ea1a	663	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	664	/* PLL_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	665	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
NYX	0:85b3fd62ea1a	666	{
NYX	0:85b3fd62ea1a	667	/* In Case the PLL Source is HSI (Internal Clock) */
NYX	0:85b3fd62ea1a	668	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	669	}
NYX	0:85b3fd62ea1a	670	else
NYX	0:85b3fd62ea1a	671	{
NYX	0:85b3fd62ea1a	672	/* In Case the PLL Source is HSE (External Clock) */
NYX	0:85b3fd62ea1a	673	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
NYX	0:85b3fd62ea1a	674	}
NYX	0:85b3fd62ea1a	675
NYX	0:85b3fd62ea1a	676	/* PLL_VCO Output = PLL_VCO Input * PLLN */
NYX	0:85b3fd62ea1a	677	/* SAI_CLK_x = PLL_VCO Output/PLLR */
NYX	0:85b3fd62ea1a	678	tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
NYX	0:85b3fd62ea1a	679	frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
NYX	0:85b3fd62ea1a	680	break;
NYX	0:85b3fd62ea1a	681	}
NYX	0:85b3fd62ea1a	682	case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
NYX	0:85b3fd62ea1a	683	{
NYX	0:85b3fd62ea1a	684	frequency = EXTERNAL_CLOCK_VALUE;
NYX	0:85b3fd62ea1a	685	break;
NYX	0:85b3fd62ea1a	686	}
NYX	0:85b3fd62ea1a	687	case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
NYX	0:85b3fd62ea1a	688	{
NYX	0:85b3fd62ea1a	689	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
NYX	0:85b3fd62ea1a	690	{
NYX	0:85b3fd62ea1a	691	/* In Case the PLL Source is HSI (Internal Clock) */
NYX	0:85b3fd62ea1a	692	frequency = (uint32_t)(HSI_VALUE);
NYX	0:85b3fd62ea1a	693	}
NYX	0:85b3fd62ea1a	694	else
NYX	0:85b3fd62ea1a	695	{
NYX	0:85b3fd62ea1a	696	/* In Case the PLL Source is HSE (External Clock) */
NYX	0:85b3fd62ea1a	697	frequency = (uint32_t)(HSE_VALUE);
NYX	0:85b3fd62ea1a	698	}
NYX	0:85b3fd62ea1a	699	break;
NYX	0:85b3fd62ea1a	700	}
NYX	0:85b3fd62ea1a	701	default :
NYX	0:85b3fd62ea1a	702	{
NYX	0:85b3fd62ea1a	703	break;
NYX	0:85b3fd62ea1a	704	}
NYX	0:85b3fd62ea1a	705	}
NYX	0:85b3fd62ea1a	706	break;
NYX	0:85b3fd62ea1a	707	}
NYX	0:85b3fd62ea1a	708	case RCC_PERIPHCLK_I2S_APB1:
NYX	0:85b3fd62ea1a	709	{
NYX	0:85b3fd62ea1a	710	/* Get the current I2S source */
NYX	0:85b3fd62ea1a	711	srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
NYX	0:85b3fd62ea1a	712	switch (srcclk)
NYX	0:85b3fd62ea1a	713	{
NYX	0:85b3fd62ea1a	714	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
NYX	0:85b3fd62ea1a	715	case RCC_I2SAPB1CLKSOURCE_EXT:
NYX	0:85b3fd62ea1a	716	{
NYX	0:85b3fd62ea1a	717	/* Set the I2S clock to the external clock value */
NYX	0:85b3fd62ea1a	718	frequency = EXTERNAL_CLOCK_VALUE;
NYX	0:85b3fd62ea1a	719	break;
NYX	0:85b3fd62ea1a	720	}
NYX	0:85b3fd62ea1a	721	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
NYX	0:85b3fd62ea1a	722	case RCC_I2SAPB1CLKSOURCE_PLLI2S:
NYX	0:85b3fd62ea1a	723	{
NYX	0:85b3fd62ea1a	724	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	725	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
NYX	0:85b3fd62ea1a	726	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	727	{
NYX	0:85b3fd62ea1a	728	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	729	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	730	}
NYX	0:85b3fd62ea1a	731	else
NYX	0:85b3fd62ea1a	732	{
NYX	0:85b3fd62ea1a	733	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	734	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	735	}
NYX	0:85b3fd62ea1a	736
NYX	0:85b3fd62ea1a	737	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	738	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
NYX	0:85b3fd62ea1a	739	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
NYX	0:85b3fd62ea1a	740	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
NYX	0:85b3fd62ea1a	741	break;
NYX	0:85b3fd62ea1a	742	}
NYX	0:85b3fd62ea1a	743	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
NYX	0:85b3fd62ea1a	744	case RCC_I2SAPB1CLKSOURCE_PLLR:
NYX	0:85b3fd62ea1a	745	{
NYX	0:85b3fd62ea1a	746	/* Configure the PLL division factor R */
NYX	0:85b3fd62ea1a	747	/* PLL_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	748	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	749	{
NYX	0:85b3fd62ea1a	750	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	751	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	752	}
NYX	0:85b3fd62ea1a	753	else
NYX	0:85b3fd62ea1a	754	{
NYX	0:85b3fd62ea1a	755	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	756	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	757	}
NYX	0:85b3fd62ea1a	758
NYX	0:85b3fd62ea1a	759	/* PLL_VCO Output = PLL_VCO Input * PLLN */
NYX	0:85b3fd62ea1a	760	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
NYX	0:85b3fd62ea1a	761	/* I2S_CLK = PLL_VCO Output/PLLR */
NYX	0:85b3fd62ea1a	762	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
NYX	0:85b3fd62ea1a	763	break;
NYX	0:85b3fd62ea1a	764	}
NYX	0:85b3fd62ea1a	765	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
NYX	0:85b3fd62ea1a	766	case RCC_I2SAPB1CLKSOURCE_PLLSRC:
NYX	0:85b3fd62ea1a	767	{
NYX	0:85b3fd62ea1a	768	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	769	{
NYX	0:85b3fd62ea1a	770	frequency = HSE_VALUE;
NYX	0:85b3fd62ea1a	771	}
NYX	0:85b3fd62ea1a	772	else
NYX	0:85b3fd62ea1a	773	{
NYX	0:85b3fd62ea1a	774	frequency = HSI_VALUE;
NYX	0:85b3fd62ea1a	775	}
NYX	0:85b3fd62ea1a	776	break;
NYX	0:85b3fd62ea1a	777	}
NYX	0:85b3fd62ea1a	778	/* Clock not enabled for I2S*/
NYX	0:85b3fd62ea1a	779	default:
NYX	0:85b3fd62ea1a	780	{
NYX	0:85b3fd62ea1a	781	frequency = 0U;
NYX	0:85b3fd62ea1a	782	break;
NYX	0:85b3fd62ea1a	783	}
NYX	0:85b3fd62ea1a	784	}
NYX	0:85b3fd62ea1a	785	break;
NYX	0:85b3fd62ea1a	786	}
NYX	0:85b3fd62ea1a	787	case RCC_PERIPHCLK_I2S_APB2:
NYX	0:85b3fd62ea1a	788	{
NYX	0:85b3fd62ea1a	789	/* Get the current I2S source */
NYX	0:85b3fd62ea1a	790	srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
NYX	0:85b3fd62ea1a	791	switch (srcclk)
NYX	0:85b3fd62ea1a	792	{
NYX	0:85b3fd62ea1a	793	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
NYX	0:85b3fd62ea1a	794	case RCC_I2SAPB2CLKSOURCE_EXT:
NYX	0:85b3fd62ea1a	795	{
NYX	0:85b3fd62ea1a	796	/* Set the I2S clock to the external clock value */
NYX	0:85b3fd62ea1a	797	frequency = EXTERNAL_CLOCK_VALUE;
NYX	0:85b3fd62ea1a	798	break;
NYX	0:85b3fd62ea1a	799	}
NYX	0:85b3fd62ea1a	800	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
NYX	0:85b3fd62ea1a	801	case RCC_I2SAPB2CLKSOURCE_PLLI2S:
NYX	0:85b3fd62ea1a	802	{
NYX	0:85b3fd62ea1a	803	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	804	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
NYX	0:85b3fd62ea1a	805	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	806	{
NYX	0:85b3fd62ea1a	807	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	808	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	809	}
NYX	0:85b3fd62ea1a	810	else
NYX	0:85b3fd62ea1a	811	{
NYX	0:85b3fd62ea1a	812	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	813	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	814	}
NYX	0:85b3fd62ea1a	815
NYX	0:85b3fd62ea1a	816	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	817	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
NYX	0:85b3fd62ea1a	818	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
NYX	0:85b3fd62ea1a	819	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
NYX	0:85b3fd62ea1a	820	break;
NYX	0:85b3fd62ea1a	821	}
NYX	0:85b3fd62ea1a	822	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
NYX	0:85b3fd62ea1a	823	case RCC_I2SAPB2CLKSOURCE_PLLR:
NYX	0:85b3fd62ea1a	824	{
NYX	0:85b3fd62ea1a	825	/* Configure the PLL division factor R */
NYX	0:85b3fd62ea1a	826	/* PLL_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	827	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	828	{
NYX	0:85b3fd62ea1a	829	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	830	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	831	}
NYX	0:85b3fd62ea1a	832	else
NYX	0:85b3fd62ea1a	833	{
NYX	0:85b3fd62ea1a	834	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	835	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	836	}
NYX	0:85b3fd62ea1a	837
NYX	0:85b3fd62ea1a	838	/* PLL_VCO Output = PLL_VCO Input * PLLN */
NYX	0:85b3fd62ea1a	839	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
NYX	0:85b3fd62ea1a	840	/* I2S_CLK = PLL_VCO Output/PLLR */
NYX	0:85b3fd62ea1a	841	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
NYX	0:85b3fd62ea1a	842	break;
NYX	0:85b3fd62ea1a	843	}
NYX	0:85b3fd62ea1a	844	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
NYX	0:85b3fd62ea1a	845	case RCC_I2SAPB2CLKSOURCE_PLLSRC:
NYX	0:85b3fd62ea1a	846	{
NYX	0:85b3fd62ea1a	847	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	848	{
NYX	0:85b3fd62ea1a	849	frequency = HSE_VALUE;
NYX	0:85b3fd62ea1a	850	}
NYX	0:85b3fd62ea1a	851	else
NYX	0:85b3fd62ea1a	852	{
NYX	0:85b3fd62ea1a	853	frequency = HSI_VALUE;
NYX	0:85b3fd62ea1a	854	}
NYX	0:85b3fd62ea1a	855	break;
NYX	0:85b3fd62ea1a	856	}
NYX	0:85b3fd62ea1a	857	/* Clock not enabled for I2S*/
NYX	0:85b3fd62ea1a	858	default:
NYX	0:85b3fd62ea1a	859	{
NYX	0:85b3fd62ea1a	860	frequency = 0U;
NYX	0:85b3fd62ea1a	861	break;
NYX	0:85b3fd62ea1a	862	}
NYX	0:85b3fd62ea1a	863	}
NYX	0:85b3fd62ea1a	864	break;
NYX	0:85b3fd62ea1a	865	}
NYX	0:85b3fd62ea1a	866	}
NYX	0:85b3fd62ea1a	867	return frequency;
NYX	0:85b3fd62ea1a	868	}
NYX	0:85b3fd62ea1a	869	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	870
NYX	0:85b3fd62ea1a	871	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	872	/**
NYX	0:85b3fd62ea1a	873	* @brief Initializes the RCC extended peripherals clocks according to the specified
NYX	0:85b3fd62ea1a	874	* parameters in the RCC_PeriphCLKInitTypeDef.
NYX	0:85b3fd62ea1a	875	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	876	* contains the configuration information for the Extended Peripherals
NYX	0:85b3fd62ea1a	877	* clocks(I2S, SAI, LTDC, RTC and TIM).
NYX	0:85b3fd62ea1a	878	*
NYX	0:85b3fd62ea1a	879	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
NYX	0:85b3fd62ea1a	880	* the RTC clock source; in this case the Backup domain will be reset in
NYX	0:85b3fd62ea1a	881	* order to modify the RTC Clock source, as consequence RTC registers (including
NYX	0:85b3fd62ea1a	882	* the backup registers) and RCC_BDCR register are set to their reset values.
NYX	0:85b3fd62ea1a	883	*
NYX	0:85b3fd62ea1a	884	* @retval HAL status
NYX	0:85b3fd62ea1a	885	*/
NYX	0:85b3fd62ea1a	886	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	887	{
NYX	0:85b3fd62ea1a	888	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	889	uint32_t tmpreg1 = 0U;
NYX	0:85b3fd62ea1a	890	uint32_t pllsaip = 0U;
NYX	0:85b3fd62ea1a	891	uint32_t pllsaiq = 0U;
NYX	0:85b3fd62ea1a	892	uint32_t pllsair = 0U;
NYX	0:85b3fd62ea1a	893
NYX	0:85b3fd62ea1a	894	/* Check the parameters */
NYX	0:85b3fd62ea1a	895	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
NYX	0:85b3fd62ea1a	896
NYX	0:85b3fd62ea1a	897	/--------------------------- CLK48 Configuration --------------------------/
NYX	0:85b3fd62ea1a	898	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
NYX	0:85b3fd62ea1a	899	{
NYX	0:85b3fd62ea1a	900	/* Check the parameters */
NYX	0:85b3fd62ea1a	901	assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
NYX	0:85b3fd62ea1a	902
NYX	0:85b3fd62ea1a	903	/* Configure the CLK48 clock source */
NYX	0:85b3fd62ea1a	904	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
NYX	0:85b3fd62ea1a	905	}
NYX	0:85b3fd62ea1a	906	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	907
NYX	0:85b3fd62ea1a	908	/------------------------------ SDIO Configuration ------------------------/
NYX	0:85b3fd62ea1a	909	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
NYX	0:85b3fd62ea1a	910	{
NYX	0:85b3fd62ea1a	911	/* Check the parameters */
NYX	0:85b3fd62ea1a	912	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
NYX	0:85b3fd62ea1a	913
NYX	0:85b3fd62ea1a	914	/* Configure the SDIO clock source */
NYX	0:85b3fd62ea1a	915	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
NYX	0:85b3fd62ea1a	916	}
NYX	0:85b3fd62ea1a	917	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	918
NYX	0:85b3fd62ea1a	919	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------/
NYX	0:85b3fd62ea1a	920	/------------------- Common configuration SAI/I2S -------------------------/
NYX	0:85b3fd62ea1a	921	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
NYX	0:85b3fd62ea1a	922	factor is common parameters for both peripherals */
NYX	0:85b3fd62ea1a	923	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
NYX	0:85b3fd62ea1a	924	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) \|\|
NYX	0:85b3fd62ea1a	925	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
NYX	0:85b3fd62ea1a	926	{
NYX	0:85b3fd62ea1a	927	/* check for Parameters */
NYX	0:85b3fd62ea1a	928	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
NYX	0:85b3fd62ea1a	929
NYX	0:85b3fd62ea1a	930	/* Disable the PLLI2S */
NYX	0:85b3fd62ea1a	931	__HAL_RCC_PLLI2S_DISABLE();
NYX	0:85b3fd62ea1a	932	/* Get tick */
NYX	0:85b3fd62ea1a	933	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	934	/* Wait till PLLI2S is disabled */
NYX	0:85b3fd62ea1a	935	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
NYX	0:85b3fd62ea1a	936	{
NYX	0:85b3fd62ea1a	937	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	938	{
NYX	0:85b3fd62ea1a	939	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	940	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	941	}
NYX	0:85b3fd62ea1a	942	}
NYX	0:85b3fd62ea1a	943
NYX	0:85b3fd62ea1a	944	/---------------------- I2S configuration -------------------------------/
NYX	0:85b3fd62ea1a	945	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
NYX	0:85b3fd62ea1a	946	only for I2S configuration */
NYX	0:85b3fd62ea1a	947	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
NYX	0:85b3fd62ea1a	948	{
NYX	0:85b3fd62ea1a	949	/* check for Parameters */
NYX	0:85b3fd62ea1a	950	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
NYX	0:85b3fd62ea1a	951	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	952	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
NYX	0:85b3fd62ea1a	953	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
NYX	0:85b3fd62ea1a	954	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	955	}
NYX	0:85b3fd62ea1a	956
NYX	0:85b3fd62ea1a	957	/---------------------------- SAI configuration -------------------------/
NYX	0:85b3fd62ea1a	958	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
NYX	0:85b3fd62ea1a	959	be added only for SAI configuration */
NYX	0:85b3fd62ea1a	960	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
NYX	0:85b3fd62ea1a	961	{
NYX	0:85b3fd62ea1a	962	/* Check the PLLI2S division factors */
NYX	0:85b3fd62ea1a	963	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
NYX	0:85b3fd62ea1a	964	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
NYX	0:85b3fd62ea1a	965
NYX	0:85b3fd62ea1a	966	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	967	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	968	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	969	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	970	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	971	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
NYX	0:85b3fd62ea1a	972	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
NYX	0:85b3fd62ea1a	973	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	974	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
NYX	0:85b3fd62ea1a	975	}
NYX	0:85b3fd62ea1a	976
NYX	0:85b3fd62ea1a	977	/----------------- In Case of PLLI2S is just selected -----------------/
NYX	0:85b3fd62ea1a	978	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
NYX	0:85b3fd62ea1a	979	{
NYX	0:85b3fd62ea1a	980	/* Check for Parameters */
NYX	0:85b3fd62ea1a	981	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
NYX	0:85b3fd62ea1a	982	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
NYX	0:85b3fd62ea1a	983
NYX	0:85b3fd62ea1a	984	/* Configure the PLLI2S multiplication and division factors */
NYX	0:85b3fd62ea1a	985	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	986	}
NYX	0:85b3fd62ea1a	987
NYX	0:85b3fd62ea1a	988	/* Enable the PLLI2S */
NYX	0:85b3fd62ea1a	989	__HAL_RCC_PLLI2S_ENABLE();
NYX	0:85b3fd62ea1a	990	/* Get tick */
NYX	0:85b3fd62ea1a	991	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	992	/* Wait till PLLI2S is ready */
NYX	0:85b3fd62ea1a	993	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
NYX	0:85b3fd62ea1a	994	{
NYX	0:85b3fd62ea1a	995	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	996	{
NYX	0:85b3fd62ea1a	997	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	998	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	999	}
NYX	0:85b3fd62ea1a	1000	}
NYX	0:85b3fd62ea1a	1001	}
NYX	0:85b3fd62ea1a	1002	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1003
NYX	0:85b3fd62ea1a	1004	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
NYX	0:85b3fd62ea1a	1005	/----------------------- Common configuration SAI/LTDC --------------------/
NYX	0:85b3fd62ea1a	1006	/* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
NYX	0:85b3fd62ea1a	1007	factor is common parameters for these peripherals */
NYX	0:85b3fd62ea1a	1008	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
NYX	0:85b3fd62ea1a	1009	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\|
NYX	0:85b3fd62ea1a	1010	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) &&
NYX	0:85b3fd62ea1a	1011	(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
NYX	0:85b3fd62ea1a	1012	{
NYX	0:85b3fd62ea1a	1013	/* Check the PLLSAI division factors */
NYX	0:85b3fd62ea1a	1014	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
NYX	0:85b3fd62ea1a	1015
NYX	0:85b3fd62ea1a	1016	/* Disable PLLSAI Clock */
NYX	0:85b3fd62ea1a	1017	__HAL_RCC_PLLSAI_DISABLE();
NYX	0:85b3fd62ea1a	1018	/* Get tick */
NYX	0:85b3fd62ea1a	1019	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1020	/* Wait till PLLSAI is disabled */
NYX	0:85b3fd62ea1a	1021	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
NYX	0:85b3fd62ea1a	1022	{
NYX	0:85b3fd62ea1a	1023	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	1024	{
NYX	0:85b3fd62ea1a	1025	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	1026	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1027	}
NYX	0:85b3fd62ea1a	1028	}
NYX	0:85b3fd62ea1a	1029
NYX	0:85b3fd62ea1a	1030	/---------------------------- SAI configuration -------------------------/
NYX	0:85b3fd62ea1a	1031	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
NYX	0:85b3fd62ea1a	1032	be added only for SAI configuration */
NYX	0:85b3fd62ea1a	1033	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
NYX	0:85b3fd62ea1a	1034	{
NYX	0:85b3fd62ea1a	1035	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
NYX	0:85b3fd62ea1a	1036	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
NYX	0:85b3fd62ea1a	1037
NYX	0:85b3fd62ea1a	1038	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
NYX	0:85b3fd62ea1a	1039	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
NYX	0:85b3fd62ea1a	1040	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	1041	pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
NYX	0:85b3fd62ea1a	1042	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	1043	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
NYX	0:85b3fd62ea1a	1044	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
NYX	0:85b3fd62ea1a	1045	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
NYX	0:85b3fd62ea1a	1046	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
NYX	0:85b3fd62ea1a	1047	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
NYX	0:85b3fd62ea1a	1048	}
NYX	0:85b3fd62ea1a	1049
NYX	0:85b3fd62ea1a	1050	/---------------------------- LTDC configuration ------------------------/
NYX	0:85b3fd62ea1a	1051	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
NYX	0:85b3fd62ea1a	1052	{
NYX	0:85b3fd62ea1a	1053	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
NYX	0:85b3fd62ea1a	1054	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
NYX	0:85b3fd62ea1a	1055
NYX	0:85b3fd62ea1a	1056	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
NYX	0:85b3fd62ea1a	1057	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
NYX	0:85b3fd62ea1a	1058	/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	1059	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
NYX	0:85b3fd62ea1a	1060	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	1061	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
NYX	0:85b3fd62ea1a	1062	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
NYX	0:85b3fd62ea1a	1063	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
NYX	0:85b3fd62ea1a	1064	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
NYX	0:85b3fd62ea1a	1065	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
NYX	0:85b3fd62ea1a	1066	}
NYX	0:85b3fd62ea1a	1067
NYX	0:85b3fd62ea1a	1068	/---------------------------- CLK48 configuration ------------------------/
NYX	0:85b3fd62ea1a	1069	/* Configure the PLLSAI when it is used as clock source for CLK48 */
NYX	0:85b3fd62ea1a	1070	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
NYX	0:85b3fd62ea1a	1071	(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
NYX	0:85b3fd62ea1a	1072	{
NYX	0:85b3fd62ea1a	1073	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
NYX	0:85b3fd62ea1a	1074
NYX	0:85b3fd62ea1a	1075	/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	1076	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
NYX	0:85b3fd62ea1a	1077	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	1078	pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
NYX	0:85b3fd62ea1a	1079	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	1080	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
NYX	0:85b3fd62ea1a	1081	/* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
NYX	0:85b3fd62ea1a	1082	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
NYX	0:85b3fd62ea1a	1083	}
NYX	0:85b3fd62ea1a	1084
NYX	0:85b3fd62ea1a	1085	/* Enable PLLSAI Clock */
NYX	0:85b3fd62ea1a	1086	__HAL_RCC_PLLSAI_ENABLE();
NYX	0:85b3fd62ea1a	1087	/* Get tick */
NYX	0:85b3fd62ea1a	1088	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1089	/* Wait till PLLSAI is ready */
NYX	0:85b3fd62ea1a	1090	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
NYX	0:85b3fd62ea1a	1091	{
NYX	0:85b3fd62ea1a	1092	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	1093	{
NYX	0:85b3fd62ea1a	1094	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	1095	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1096	}
NYX	0:85b3fd62ea1a	1097	}
NYX	0:85b3fd62ea1a	1098	}
NYX	0:85b3fd62ea1a	1099
NYX	0:85b3fd62ea1a	1100	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1101
NYX	0:85b3fd62ea1a	1102	/---------------------------- RTC configuration ---------------------------/
NYX	0:85b3fd62ea1a	1103	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
NYX	0:85b3fd62ea1a	1104	{
NYX	0:85b3fd62ea1a	1105	/* Check for RTC Parameters used to output RTCCLK */
NYX	0:85b3fd62ea1a	1106	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
NYX	0:85b3fd62ea1a	1107
NYX	0:85b3fd62ea1a	1108	/* Enable Power Clock*/
NYX	0:85b3fd62ea1a	1109	__HAL_RCC_PWR_CLK_ENABLE();
NYX	0:85b3fd62ea1a	1110
NYX	0:85b3fd62ea1a	1111	/* Enable write access to Backup domain */
NYX	0:85b3fd62ea1a	1112	PWR->CR \|= PWR_CR_DBP;
NYX	0:85b3fd62ea1a	1113
NYX	0:85b3fd62ea1a	1114	/* Get tick */
NYX	0:85b3fd62ea1a	1115	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1116
NYX	0:85b3fd62ea1a	1117	while((PWR->CR & PWR_CR_DBP) == RESET)
NYX	0:85b3fd62ea1a	1118	{
NYX	0:85b3fd62ea1a	1119	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	1120	{
NYX	0:85b3fd62ea1a	1121	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1122	}
NYX	0:85b3fd62ea1a	1123	}
NYX	0:85b3fd62ea1a	1124	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
NYX	0:85b3fd62ea1a	1125	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
NYX	0:85b3fd62ea1a	1126	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
NYX	0:85b3fd62ea1a	1127	{
NYX	0:85b3fd62ea1a	1128	/* Store the content of BDCR register before the reset of Backup Domain */
NYX	0:85b3fd62ea1a	1129	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	1130	/* RTC Clock selection can be changed only if the Backup Domain is reset */
NYX	0:85b3fd62ea1a	1131	__HAL_RCC_BACKUPRESET_FORCE();
NYX	0:85b3fd62ea1a	1132	__HAL_RCC_BACKUPRESET_RELEASE();
NYX	0:85b3fd62ea1a	1133	/* Restore the Content of BDCR register */
NYX	0:85b3fd62ea1a	1134	RCC->BDCR = tmpreg1;
NYX	0:85b3fd62ea1a	1135
NYX	0:85b3fd62ea1a	1136	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
NYX	0:85b3fd62ea1a	1137	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
NYX	0:85b3fd62ea1a	1138	{
NYX	0:85b3fd62ea1a	1139	/* Get tick */
NYX	0:85b3fd62ea1a	1140	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1141
NYX	0:85b3fd62ea1a	1142	/* Wait till LSE is ready */
NYX	0:85b3fd62ea1a	1143	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
NYX	0:85b3fd62ea1a	1144	{
NYX	0:85b3fd62ea1a	1145	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	1146	{
NYX	0:85b3fd62ea1a	1147	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1148	}
NYX	0:85b3fd62ea1a	1149	}
NYX	0:85b3fd62ea1a	1150	}
NYX	0:85b3fd62ea1a	1151	}
NYX	0:85b3fd62ea1a	1152	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
NYX	0:85b3fd62ea1a	1153	}
NYX	0:85b3fd62ea1a	1154	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1155
NYX	0:85b3fd62ea1a	1156	/---------------------------- TIM configuration ---------------------------/
NYX	0:85b3fd62ea1a	1157	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
NYX	0:85b3fd62ea1a	1158	{
NYX	0:85b3fd62ea1a	1159	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
NYX	0:85b3fd62ea1a	1160	}
NYX	0:85b3fd62ea1a	1161	return HAL_OK;
NYX	0:85b3fd62ea1a	1162	}
NYX	0:85b3fd62ea1a	1163
NYX	0:85b3fd62ea1a	1164	/**
NYX	0:85b3fd62ea1a	1165	* @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal
NYX	0:85b3fd62ea1a	1166	* RCC configuration registers.
NYX	0:85b3fd62ea1a	1167	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	1168	* will be configured.
NYX	0:85b3fd62ea1a	1169	* @retval None
NYX	0:85b3fd62ea1a	1170	*/
NYX	0:85b3fd62ea1a	1171	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	1172	{
NYX	0:85b3fd62ea1a	1173	uint32_t tempreg;
NYX	0:85b3fd62ea1a	1174
NYX	0:85b3fd62ea1a	1175	/* Set all possible values for the extended clock type parameter------------*/
NYX	0:85b3fd62ea1a	1176	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \|\
NYX	0:85b3fd62ea1a	1177	RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \|\
NYX	0:85b3fd62ea1a	1178	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
NYX	0:85b3fd62ea1a	1179	RCC_PERIPHCLK_CLK48 \| RCC_PERIPHCLK_SDIO;
NYX	0:85b3fd62ea1a	1180
NYX	0:85b3fd62ea1a	1181	/* Get the PLLI2S Clock configuration --------------------------------------*/
NYX	0:85b3fd62ea1a	1182	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
NYX	0:85b3fd62ea1a	1183	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	1184	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
NYX	0:85b3fd62ea1a	1185	/* Get the PLLSAI Clock configuration --------------------------------------*/
NYX	0:85b3fd62ea1a	1186	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
NYX	0:85b3fd62ea1a	1187	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
NYX	0:85b3fd62ea1a	1188	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
NYX	0:85b3fd62ea1a	1189	/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
NYX	0:85b3fd62ea1a	1190	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
NYX	0:85b3fd62ea1a	1191	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
NYX	0:85b3fd62ea1a	1192	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
NYX	0:85b3fd62ea1a	1193	/* Get the RTC Clock configuration -----------------------------------------*/
NYX	0:85b3fd62ea1a	1194	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
NYX	0:85b3fd62ea1a	1195	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	1196
NYX	0:85b3fd62ea1a	1197	/* Get the CLK48 clock configuration -------------------------------------*/
NYX	0:85b3fd62ea1a	1198	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
NYX	0:85b3fd62ea1a	1199
NYX	0:85b3fd62ea1a	1200	/* Get the SDIO clock configuration ----------------------------------------*/
NYX	0:85b3fd62ea1a	1201	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
NYX	0:85b3fd62ea1a	1202
NYX	0:85b3fd62ea1a	1203	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
NYX	0:85b3fd62ea1a	1204	{
NYX	0:85b3fd62ea1a	1205	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
NYX	0:85b3fd62ea1a	1206	}
NYX	0:85b3fd62ea1a	1207	else
NYX	0:85b3fd62ea1a	1208	{
NYX	0:85b3fd62ea1a	1209	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
NYX	0:85b3fd62ea1a	1210	}
NYX	0:85b3fd62ea1a	1211	}
NYX	0:85b3fd62ea1a	1212
NYX	0:85b3fd62ea1a	1213	/**
NYX	0:85b3fd62ea1a	1214	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
NYX	0:85b3fd62ea1a	1215	* @note Return 0 if peripheral clock identifier not managed by this API
NYX	0:85b3fd62ea1a	1216	* @param PeriphClk: Peripheral clock identifier
NYX	0:85b3fd62ea1a	1217	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1218	* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
NYX	0:85b3fd62ea1a	1219	* @retval Frequency in KHz
NYX	0:85b3fd62ea1a	1220	*/
NYX	0:85b3fd62ea1a	1221	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
NYX	0:85b3fd62ea1a	1222	{
NYX	0:85b3fd62ea1a	1223	/* This variable used to store the I2S clock frequency (value in Hz) */
NYX	0:85b3fd62ea1a	1224	uint32_t frequency = 0U;
NYX	0:85b3fd62ea1a	1225	/* This variable used to store the VCO Input (value in Hz) */
NYX	0:85b3fd62ea1a	1226	uint32_t vcoinput = 0U;
NYX	0:85b3fd62ea1a	1227	uint32_t srcclk = 0U;
NYX	0:85b3fd62ea1a	1228	/* This variable used to store the VCO Output (value in Hz) */
NYX	0:85b3fd62ea1a	1229	uint32_t vcooutput = 0U;
NYX	0:85b3fd62ea1a	1230	switch (PeriphClk)
NYX	0:85b3fd62ea1a	1231	{
NYX	0:85b3fd62ea1a	1232	case RCC_PERIPHCLK_I2S:
NYX	0:85b3fd62ea1a	1233	{
NYX	0:85b3fd62ea1a	1234	/* Get the current I2S source */
NYX	0:85b3fd62ea1a	1235	srcclk = __HAL_RCC_GET_I2S_SOURCE();
NYX	0:85b3fd62ea1a	1236	switch (srcclk)
NYX	0:85b3fd62ea1a	1237	{
NYX	0:85b3fd62ea1a	1238	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
NYX	0:85b3fd62ea1a	1239	case RCC_I2SCLKSOURCE_EXT:
NYX	0:85b3fd62ea1a	1240	{
NYX	0:85b3fd62ea1a	1241	/* Set the I2S clock to the external clock value */
NYX	0:85b3fd62ea1a	1242	frequency = EXTERNAL_CLOCK_VALUE;
NYX	0:85b3fd62ea1a	1243	break;
NYX	0:85b3fd62ea1a	1244	}
NYX	0:85b3fd62ea1a	1245	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
NYX	0:85b3fd62ea1a	1246	case RCC_I2SCLKSOURCE_PLLI2S:
NYX	0:85b3fd62ea1a	1247	{
NYX	0:85b3fd62ea1a	1248	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	1249	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
NYX	0:85b3fd62ea1a	1250	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	1251	{
NYX	0:85b3fd62ea1a	1252	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1253	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	1254	}
NYX	0:85b3fd62ea1a	1255	else
NYX	0:85b3fd62ea1a	1256	{
NYX	0:85b3fd62ea1a	1257	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1258	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	1259	}
NYX	0:85b3fd62ea1a	1260
NYX	0:85b3fd62ea1a	1261	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	1262	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
NYX	0:85b3fd62ea1a	1263	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
NYX	0:85b3fd62ea1a	1264	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
NYX	0:85b3fd62ea1a	1265	break;
NYX	0:85b3fd62ea1a	1266	}
NYX	0:85b3fd62ea1a	1267	/* Clock not enabled for I2S*/
NYX	0:85b3fd62ea1a	1268	default:
NYX	0:85b3fd62ea1a	1269	{
NYX	0:85b3fd62ea1a	1270	frequency = 0U;
NYX	0:85b3fd62ea1a	1271	break;
NYX	0:85b3fd62ea1a	1272	}
NYX	0:85b3fd62ea1a	1273	}
NYX	0:85b3fd62ea1a	1274	break;
NYX	0:85b3fd62ea1a	1275	}
NYX	0:85b3fd62ea1a	1276	}
NYX	0:85b3fd62ea1a	1277	return frequency;
NYX	0:85b3fd62ea1a	1278	}
NYX	0:85b3fd62ea1a	1279	#endif /* STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1280
NYX	0:85b3fd62ea1a	1281	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1282	/**
NYX	0:85b3fd62ea1a	1283	* @brief Initializes the RCC extended peripherals clocks according to the specified
NYX	0:85b3fd62ea1a	1284	* parameters in the RCC_PeriphCLKInitTypeDef.
NYX	0:85b3fd62ea1a	1285	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	1286	* contains the configuration information for the Extended Peripherals
NYX	0:85b3fd62ea1a	1287	* clocks(I2S, LTDC RTC and TIM).
NYX	0:85b3fd62ea1a	1288	*
NYX	0:85b3fd62ea1a	1289	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
NYX	0:85b3fd62ea1a	1290	* the RTC clock source; in this case the Backup domain will be reset in
NYX	0:85b3fd62ea1a	1291	* order to modify the RTC Clock source, as consequence RTC registers (including
NYX	0:85b3fd62ea1a	1292	* the backup registers) and RCC_BDCR register are set to their reset values.
NYX	0:85b3fd62ea1a	1293	*
NYX	0:85b3fd62ea1a	1294	* @retval HAL status
NYX	0:85b3fd62ea1a	1295	*/
NYX	0:85b3fd62ea1a	1296	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	1297	{
NYX	0:85b3fd62ea1a	1298	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	1299	uint32_t tmpreg1 = 0U;
NYX	0:85b3fd62ea1a	1300	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1301	uint32_t plli2sq = 0U;
NYX	0:85b3fd62ea1a	1302	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1303	uint32_t plli2sused = 0U;
NYX	0:85b3fd62ea1a	1304
NYX	0:85b3fd62ea1a	1305	/* Check the peripheral clock selection parameters */
NYX	0:85b3fd62ea1a	1306	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
NYX	0:85b3fd62ea1a	1307
NYX	0:85b3fd62ea1a	1308	/----------------------------------- I2S APB1 configuration ---------------/
NYX	0:85b3fd62ea1a	1309	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
NYX	0:85b3fd62ea1a	1310	{
NYX	0:85b3fd62ea1a	1311	/* Check the parameters */
NYX	0:85b3fd62ea1a	1312	assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
NYX	0:85b3fd62ea1a	1313
NYX	0:85b3fd62ea1a	1314	/* Configure I2S Clock source */
NYX	0:85b3fd62ea1a	1315	__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
NYX	0:85b3fd62ea1a	1316	/* Enable the PLLI2S when it's used as clock source for I2S */
NYX	0:85b3fd62ea1a	1317	if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
NYX	0:85b3fd62ea1a	1318	{
NYX	0:85b3fd62ea1a	1319	plli2sused = 1U;
NYX	0:85b3fd62ea1a	1320	}
NYX	0:85b3fd62ea1a	1321	}
NYX	0:85b3fd62ea1a	1322	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1323
NYX	0:85b3fd62ea1a	1324	/----------------------------------- I2S APB2 configuration ---------------/
NYX	0:85b3fd62ea1a	1325	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
NYX	0:85b3fd62ea1a	1326	{
NYX	0:85b3fd62ea1a	1327	/* Check the parameters */
NYX	0:85b3fd62ea1a	1328	assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
NYX	0:85b3fd62ea1a	1329
NYX	0:85b3fd62ea1a	1330	/* Configure I2S Clock source */
NYX	0:85b3fd62ea1a	1331	__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
NYX	0:85b3fd62ea1a	1332	/* Enable the PLLI2S when it's used as clock source for I2S */
NYX	0:85b3fd62ea1a	1333	if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
NYX	0:85b3fd62ea1a	1334	{
NYX	0:85b3fd62ea1a	1335	plli2sused = 1U;
NYX	0:85b3fd62ea1a	1336	}
NYX	0:85b3fd62ea1a	1337	}
NYX	0:85b3fd62ea1a	1338	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1339
NYX	0:85b3fd62ea1a	1340	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1341	/----------------------- SAI1 Block A configuration -----------------------/
NYX	0:85b3fd62ea1a	1342	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))
NYX	0:85b3fd62ea1a	1343	{
NYX	0:85b3fd62ea1a	1344	/* Check the parameters */
NYX	0:85b3fd62ea1a	1345	assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection));
NYX	0:85b3fd62ea1a	1346
NYX	0:85b3fd62ea1a	1347	/* Configure SAI1 Clock source */
NYX	0:85b3fd62ea1a	1348	__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection);
NYX	0:85b3fd62ea1a	1349	/* Enable the PLLI2S when it's used as clock source for SAI */
NYX	0:85b3fd62ea1a	1350	if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)
NYX	0:85b3fd62ea1a	1351	{
NYX	0:85b3fd62ea1a	1352	plli2sused = 1U;
NYX	0:85b3fd62ea1a	1353	}
NYX	0:85b3fd62ea1a	1354	/* Enable the PLLSAI when it's used as clock source for SAI */
NYX	0:85b3fd62ea1a	1355	if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)
NYX	0:85b3fd62ea1a	1356	{
NYX	0:85b3fd62ea1a	1357	/* Check for PLL/DIVR parameters */
NYX	0:85b3fd62ea1a	1358	assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
NYX	0:85b3fd62ea1a	1359
NYX	0:85b3fd62ea1a	1360	/* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
NYX	0:85b3fd62ea1a	1361	__HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
NYX	0:85b3fd62ea1a	1362	}
NYX	0:85b3fd62ea1a	1363	}
NYX	0:85b3fd62ea1a	1364	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1365
NYX	0:85b3fd62ea1a	1366	/---------------------- SAI1 Block B configuration ------------------------/
NYX	0:85b3fd62ea1a	1367	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))
NYX	0:85b3fd62ea1a	1368	{
NYX	0:85b3fd62ea1a	1369	/* Check the parameters */
NYX	0:85b3fd62ea1a	1370	assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection));
NYX	0:85b3fd62ea1a	1371
NYX	0:85b3fd62ea1a	1372	/* Configure SAI1 Clock source */
NYX	0:85b3fd62ea1a	1373	__HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection);
NYX	0:85b3fd62ea1a	1374	/* Enable the PLLI2S when it's used as clock source for SAI */
NYX	0:85b3fd62ea1a	1375	if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)
NYX	0:85b3fd62ea1a	1376	{
NYX	0:85b3fd62ea1a	1377	plli2sused = 1U;
NYX	0:85b3fd62ea1a	1378	}
NYX	0:85b3fd62ea1a	1379	/* Enable the PLLSAI when it's used as clock source for SAI */
NYX	0:85b3fd62ea1a	1380	if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)
NYX	0:85b3fd62ea1a	1381	{
NYX	0:85b3fd62ea1a	1382	/* Check for PLL/DIVR parameters */
NYX	0:85b3fd62ea1a	1383	assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
NYX	0:85b3fd62ea1a	1384
NYX	0:85b3fd62ea1a	1385	/* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
NYX	0:85b3fd62ea1a	1386	__HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
NYX	0:85b3fd62ea1a	1387	}
NYX	0:85b3fd62ea1a	1388	}
NYX	0:85b3fd62ea1a	1389	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1390	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1391
NYX	0:85b3fd62ea1a	1392	/------------------------------------ RTC configuration -------------------/
NYX	0:85b3fd62ea1a	1393	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
NYX	0:85b3fd62ea1a	1394	{
NYX	0:85b3fd62ea1a	1395	/* Check for RTC Parameters used to output RTCCLK */
NYX	0:85b3fd62ea1a	1396	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
NYX	0:85b3fd62ea1a	1397
NYX	0:85b3fd62ea1a	1398	/* Enable Power Clock*/
NYX	0:85b3fd62ea1a	1399	__HAL_RCC_PWR_CLK_ENABLE();
NYX	0:85b3fd62ea1a	1400
NYX	0:85b3fd62ea1a	1401	/* Enable write access to Backup domain */
NYX	0:85b3fd62ea1a	1402	PWR->CR \|= PWR_CR_DBP;
NYX	0:85b3fd62ea1a	1403
NYX	0:85b3fd62ea1a	1404	/* Get tick */
NYX	0:85b3fd62ea1a	1405	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1406
NYX	0:85b3fd62ea1a	1407	while((PWR->CR & PWR_CR_DBP) == RESET)
NYX	0:85b3fd62ea1a	1408	{
NYX	0:85b3fd62ea1a	1409	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	1410	{
NYX	0:85b3fd62ea1a	1411	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1412	}
NYX	0:85b3fd62ea1a	1413	}
NYX	0:85b3fd62ea1a	1414	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
NYX	0:85b3fd62ea1a	1415	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
NYX	0:85b3fd62ea1a	1416	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
NYX	0:85b3fd62ea1a	1417	{
NYX	0:85b3fd62ea1a	1418	/* Store the content of BDCR register before the reset of Backup Domain */
NYX	0:85b3fd62ea1a	1419	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	1420	/* RTC Clock selection can be changed only if the Backup Domain is reset */
NYX	0:85b3fd62ea1a	1421	__HAL_RCC_BACKUPRESET_FORCE();
NYX	0:85b3fd62ea1a	1422	__HAL_RCC_BACKUPRESET_RELEASE();
NYX	0:85b3fd62ea1a	1423	/* Restore the Content of BDCR register */
NYX	0:85b3fd62ea1a	1424	RCC->BDCR = tmpreg1;
NYX	0:85b3fd62ea1a	1425
NYX	0:85b3fd62ea1a	1426	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
NYX	0:85b3fd62ea1a	1427	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
NYX	0:85b3fd62ea1a	1428	{
NYX	0:85b3fd62ea1a	1429	/* Get tick */
NYX	0:85b3fd62ea1a	1430	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1431
NYX	0:85b3fd62ea1a	1432	/* Wait till LSE is ready */
NYX	0:85b3fd62ea1a	1433	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
NYX	0:85b3fd62ea1a	1434	{
NYX	0:85b3fd62ea1a	1435	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	1436	{
NYX	0:85b3fd62ea1a	1437	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1438	}
NYX	0:85b3fd62ea1a	1439	}
NYX	0:85b3fd62ea1a	1440	}
NYX	0:85b3fd62ea1a	1441	}
NYX	0:85b3fd62ea1a	1442	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
NYX	0:85b3fd62ea1a	1443	}
NYX	0:85b3fd62ea1a	1444	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1445
NYX	0:85b3fd62ea1a	1446	/------------------------------------ TIM configuration -------------------/
NYX	0:85b3fd62ea1a	1447	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
NYX	0:85b3fd62ea1a	1448	{
NYX	0:85b3fd62ea1a	1449	/* Configure Timer Prescaler */
NYX	0:85b3fd62ea1a	1450	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
NYX	0:85b3fd62ea1a	1451	}
NYX	0:85b3fd62ea1a	1452	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1453
NYX	0:85b3fd62ea1a	1454	/------------------------------------- FMPI2C1 Configuration --------------/
NYX	0:85b3fd62ea1a	1455	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
NYX	0:85b3fd62ea1a	1456	{
NYX	0:85b3fd62ea1a	1457	/* Check the parameters */
NYX	0:85b3fd62ea1a	1458	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
NYX	0:85b3fd62ea1a	1459
NYX	0:85b3fd62ea1a	1460	/* Configure the FMPI2C1 clock source */
NYX	0:85b3fd62ea1a	1461	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
NYX	0:85b3fd62ea1a	1462	}
NYX	0:85b3fd62ea1a	1463	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1464
NYX	0:85b3fd62ea1a	1465	/------------------------------------- CLK48 Configuration ----------------/
NYX	0:85b3fd62ea1a	1466	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
NYX	0:85b3fd62ea1a	1467	{
NYX	0:85b3fd62ea1a	1468	/* Check the parameters */
NYX	0:85b3fd62ea1a	1469	assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
NYX	0:85b3fd62ea1a	1470
NYX	0:85b3fd62ea1a	1471	/* Configure the SDIO clock source */
NYX	0:85b3fd62ea1a	1472	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
NYX	0:85b3fd62ea1a	1473
NYX	0:85b3fd62ea1a	1474	/* Enable the PLLI2S when it's used as clock source for CLK48 */
NYX	0:85b3fd62ea1a	1475	if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
NYX	0:85b3fd62ea1a	1476	{
NYX	0:85b3fd62ea1a	1477	plli2sused = 1U;
NYX	0:85b3fd62ea1a	1478	}
NYX	0:85b3fd62ea1a	1479	}
NYX	0:85b3fd62ea1a	1480	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1481
NYX	0:85b3fd62ea1a	1482	/------------------------------------- SDIO Configuration -----------------/
NYX	0:85b3fd62ea1a	1483	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
NYX	0:85b3fd62ea1a	1484	{
NYX	0:85b3fd62ea1a	1485	/* Check the parameters */
NYX	0:85b3fd62ea1a	1486	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
NYX	0:85b3fd62ea1a	1487
NYX	0:85b3fd62ea1a	1488	/* Configure the SDIO clock source */
NYX	0:85b3fd62ea1a	1489	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
NYX	0:85b3fd62ea1a	1490	}
NYX	0:85b3fd62ea1a	1491	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1492
NYX	0:85b3fd62ea1a	1493	/-------------------------------------- PLLI2S Configuration --------------/
NYX	0:85b3fd62ea1a	1494	/* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
NYX	0:85b3fd62ea1a	1495	I2S on APB2*/
NYX	0:85b3fd62ea1a	1496	if((plli2sused == 1U) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
NYX	0:85b3fd62ea1a	1497	{
NYX	0:85b3fd62ea1a	1498	/* Disable the PLLI2S */
NYX	0:85b3fd62ea1a	1499	__HAL_RCC_PLLI2S_DISABLE();
NYX	0:85b3fd62ea1a	1500	/* Get tick */
NYX	0:85b3fd62ea1a	1501	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1502	/* Wait till PLLI2S is disabled */
NYX	0:85b3fd62ea1a	1503	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
NYX	0:85b3fd62ea1a	1504	{
NYX	0:85b3fd62ea1a	1505	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	1506	{
NYX	0:85b3fd62ea1a	1507	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	1508	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1509	}
NYX	0:85b3fd62ea1a	1510	}
NYX	0:85b3fd62ea1a	1511
NYX	0:85b3fd62ea1a	1512	/* check for common PLLI2S Parameters */
NYX	0:85b3fd62ea1a	1513	assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));
NYX	0:85b3fd62ea1a	1514	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
NYX	0:85b3fd62ea1a	1515	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
NYX	0:85b3fd62ea1a	1516	/-------------------- Set the PLL I2S clock -----------------------------/
NYX	0:85b3fd62ea1a	1517	__HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
NYX	0:85b3fd62ea1a	1518
NYX	0:85b3fd62ea1a	1519	/------- In Case of PLLI2S is selected as source clock for I2S ----------/
NYX	0:85b3fd62ea1a	1520	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) \|\|
NYX	0:85b3fd62ea1a	1521	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) \|\|
NYX	0:85b3fd62ea1a	1522	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) \|\|
NYX	0:85b3fd62ea1a	1523	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
NYX	0:85b3fd62ea1a	1524	{
NYX	0:85b3fd62ea1a	1525	/* check for Parameters */
NYX	0:85b3fd62ea1a	1526	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
NYX	0:85b3fd62ea1a	1527	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
NYX	0:85b3fd62ea1a	1528
NYX	0:85b3fd62ea1a	1529	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	1530	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
NYX	0:85b3fd62ea1a	1531	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
NYX	0:85b3fd62ea1a	1532	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	1533	}
NYX	0:85b3fd62ea1a	1534
NYX	0:85b3fd62ea1a	1535	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1536	/------- In Case of PLLI2S is selected as source clock for SAI ----------/
NYX	0:85b3fd62ea1a	1537	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) \|\|
NYX	0:85b3fd62ea1a	1538	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
NYX	0:85b3fd62ea1a	1539	{
NYX	0:85b3fd62ea1a	1540	/* Check for PLLI2S Parameters */
NYX	0:85b3fd62ea1a	1541	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
NYX	0:85b3fd62ea1a	1542	/* Check for PLLI2S/DIVR parameters */
NYX	0:85b3fd62ea1a	1543	assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR));
NYX	0:85b3fd62ea1a	1544
NYX	0:85b3fd62ea1a	1545	/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
NYX	0:85b3fd62ea1a	1546	plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
NYX	0:85b3fd62ea1a	1547	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	1548	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
NYX	0:85b3fd62ea1a	1549	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	1550	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
NYX	0:85b3fd62ea1a	1551	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	1552
NYX	0:85b3fd62ea1a	1553	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
NYX	0:85b3fd62ea1a	1554	__HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);
NYX	0:85b3fd62ea1a	1555	}
NYX	0:85b3fd62ea1a	1556	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1557
NYX	0:85b3fd62ea1a	1558	/----------------- In Case of PLLI2S is just selected ------------------/
NYX	0:85b3fd62ea1a	1559	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
NYX	0:85b3fd62ea1a	1560	{
NYX	0:85b3fd62ea1a	1561	/* Check for Parameters */
NYX	0:85b3fd62ea1a	1562	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
NYX	0:85b3fd62ea1a	1563	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
NYX	0:85b3fd62ea1a	1564
NYX	0:85b3fd62ea1a	1565	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	1566	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
NYX	0:85b3fd62ea1a	1567	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
NYX	0:85b3fd62ea1a	1568	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	1569	}
NYX	0:85b3fd62ea1a	1570
NYX	0:85b3fd62ea1a	1571	/* Enable the PLLI2S */
NYX	0:85b3fd62ea1a	1572	__HAL_RCC_PLLI2S_ENABLE();
NYX	0:85b3fd62ea1a	1573	/* Get tick */
NYX	0:85b3fd62ea1a	1574	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1575	/* Wait till PLLI2S is ready */
NYX	0:85b3fd62ea1a	1576	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
NYX	0:85b3fd62ea1a	1577	{
NYX	0:85b3fd62ea1a	1578	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	1579	{
NYX	0:85b3fd62ea1a	1580	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	1581	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1582	}
NYX	0:85b3fd62ea1a	1583	}
NYX	0:85b3fd62ea1a	1584	}
NYX	0:85b3fd62ea1a	1585	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1586
NYX	0:85b3fd62ea1a	1587	/-------------------- DFSDM1 clock source configuration -------------------/
NYX	0:85b3fd62ea1a	1588	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
NYX	0:85b3fd62ea1a	1589	{
NYX	0:85b3fd62ea1a	1590	/* Check the parameters */
NYX	0:85b3fd62ea1a	1591	assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
NYX	0:85b3fd62ea1a	1592
NYX	0:85b3fd62ea1a	1593	/* Configure the DFSDM1 interface clock source */
NYX	0:85b3fd62ea1a	1594	__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
NYX	0:85b3fd62ea1a	1595	}
NYX	0:85b3fd62ea1a	1596	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1597
NYX	0:85b3fd62ea1a	1598	/-------------------- DFSDM1 Audio clock source configuration -------------/
NYX	0:85b3fd62ea1a	1599	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
NYX	0:85b3fd62ea1a	1600	{
NYX	0:85b3fd62ea1a	1601	/* Check the parameters */
NYX	0:85b3fd62ea1a	1602	assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
NYX	0:85b3fd62ea1a	1603
NYX	0:85b3fd62ea1a	1604	/* Configure the DFSDM1 Audio interface clock source */
NYX	0:85b3fd62ea1a	1605	__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
NYX	0:85b3fd62ea1a	1606	}
NYX	0:85b3fd62ea1a	1607	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1608
NYX	0:85b3fd62ea1a	1609	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1610	/-------------------- DFSDM2 clock source configuration -------------------/
NYX	0:85b3fd62ea1a	1611	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
NYX	0:85b3fd62ea1a	1612	{
NYX	0:85b3fd62ea1a	1613	/* Check the parameters */
NYX	0:85b3fd62ea1a	1614	assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
NYX	0:85b3fd62ea1a	1615
NYX	0:85b3fd62ea1a	1616	/* Configure the DFSDM1 interface clock source */
NYX	0:85b3fd62ea1a	1617	__HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
NYX	0:85b3fd62ea1a	1618	}
NYX	0:85b3fd62ea1a	1619	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1620
NYX	0:85b3fd62ea1a	1621	/-------------------- DFSDM2 Audio clock source configuration -------------/
NYX	0:85b3fd62ea1a	1622	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO)
NYX	0:85b3fd62ea1a	1623	{
NYX	0:85b3fd62ea1a	1624	/* Check the parameters */
NYX	0:85b3fd62ea1a	1625	assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection));
NYX	0:85b3fd62ea1a	1626
NYX	0:85b3fd62ea1a	1627	/* Configure the DFSDM1 Audio interface clock source */
NYX	0:85b3fd62ea1a	1628	__HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection);
NYX	0:85b3fd62ea1a	1629	}
NYX	0:85b3fd62ea1a	1630	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1631
NYX	0:85b3fd62ea1a	1632	/---------------------------- LPTIM1 Configuration ------------------------/
NYX	0:85b3fd62ea1a	1633	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
NYX	0:85b3fd62ea1a	1634	{
NYX	0:85b3fd62ea1a	1635	/* Check the parameters */
NYX	0:85b3fd62ea1a	1636	assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
NYX	0:85b3fd62ea1a	1637
NYX	0:85b3fd62ea1a	1638	/* Configure the LPTIM1 clock source */
NYX	0:85b3fd62ea1a	1639	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
NYX	0:85b3fd62ea1a	1640	}
NYX	0:85b3fd62ea1a	1641	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	1642	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1643
NYX	0:85b3fd62ea1a	1644	return HAL_OK;
NYX	0:85b3fd62ea1a	1645	}
NYX	0:85b3fd62ea1a	1646
NYX	0:85b3fd62ea1a	1647	/**
NYX	0:85b3fd62ea1a	1648	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
NYX	0:85b3fd62ea1a	1649	* RCC configuration registers.
NYX	0:85b3fd62ea1a	1650	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	1651	* will be configured.
NYX	0:85b3fd62ea1a	1652	* @retval None
NYX	0:85b3fd62ea1a	1653	*/
NYX	0:85b3fd62ea1a	1654	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	1655	{
NYX	0:85b3fd62ea1a	1656	uint32_t tempreg;
NYX	0:85b3fd62ea1a	1657
NYX	0:85b3fd62ea1a	1658	/* Set all possible values for the extended clock type parameter------------*/
NYX	0:85b3fd62ea1a	1659	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1660	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
NYX	0:85b3fd62ea1a	1661	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
NYX	0:85b3fd62ea1a	1662	RCC_PERIPHCLK_FMPI2C1 \| RCC_PERIPHCLK_CLK48 \|\
NYX	0:85b3fd62ea1a	1663	RCC_PERIPHCLK_SDIO \| RCC_PERIPHCLK_DFSDM1 \|\
NYX	0:85b3fd62ea1a	1664	RCC_PERIPHCLK_DFSDM1_AUDIO \| RCC_PERIPHCLK_DFSDM2 \|\
NYX	0:85b3fd62ea1a	1665	RCC_PERIPHCLK_DFSDM2_AUDIO \| RCC_PERIPHCLK_LPTIM1 \|\
NYX	0:85b3fd62ea1a	1666	RCC_PERIPHCLK_SAIA \| RCC_PERIPHCLK_SAIB;
NYX	0:85b3fd62ea1a	1667	#else /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	1668	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
NYX	0:85b3fd62ea1a	1669	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
NYX	0:85b3fd62ea1a	1670	RCC_PERIPHCLK_FMPI2C1 \| RCC_PERIPHCLK_CLK48 \|\
NYX	0:85b3fd62ea1a	1671	RCC_PERIPHCLK_SDIO \| RCC_PERIPHCLK_DFSDM1 \|\
NYX	0:85b3fd62ea1a	1672	RCC_PERIPHCLK_DFSDM1_AUDIO;
NYX	0:85b3fd62ea1a	1673	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1674
NYX	0:85b3fd62ea1a	1675
NYX	0:85b3fd62ea1a	1676
NYX	0:85b3fd62ea1a	1677	/* Get the PLLI2S Clock configuration --------------------------------------*/
NYX	0:85b3fd62ea1a	1678	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	1679	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
NYX	0:85b3fd62ea1a	1680	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
NYX	0:85b3fd62ea1a	1681	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	1682	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1683	/* Get the PLL/PLLI2S division factors -------------------------------------*/
NYX	0:85b3fd62ea1a	1684	PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVR));
NYX	0:85b3fd62ea1a	1685	PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> POSITION_VAL(RCC_DCKCFGR_PLLDIVR));
NYX	0:85b3fd62ea1a	1686	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1687
NYX	0:85b3fd62ea1a	1688	/* Get the I2S APB1 clock configuration ------------------------------------*/
NYX	0:85b3fd62ea1a	1689	PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
NYX	0:85b3fd62ea1a	1690
NYX	0:85b3fd62ea1a	1691	/* Get the I2S APB2 clock configuration ------------------------------------*/
NYX	0:85b3fd62ea1a	1692	PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
NYX	0:85b3fd62ea1a	1693
NYX	0:85b3fd62ea1a	1694	/* Get the RTC Clock configuration -----------------------------------------*/
NYX	0:85b3fd62ea1a	1695	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
NYX	0:85b3fd62ea1a	1696	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	1697
NYX	0:85b3fd62ea1a	1698	/* Get the FMPI2C1 clock configuration -------------------------------------*/
NYX	0:85b3fd62ea1a	1699	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
NYX	0:85b3fd62ea1a	1700
NYX	0:85b3fd62ea1a	1701	/* Get the CLK48 clock configuration ---------------------------------------*/
NYX	0:85b3fd62ea1a	1702	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
NYX	0:85b3fd62ea1a	1703
NYX	0:85b3fd62ea1a	1704	/* Get the SDIO clock configuration ----------------------------------------*/
NYX	0:85b3fd62ea1a	1705	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
NYX	0:85b3fd62ea1a	1706
NYX	0:85b3fd62ea1a	1707	/* Get the DFSDM1 clock configuration --------------------------------------*/
NYX	0:85b3fd62ea1a	1708	PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
NYX	0:85b3fd62ea1a	1709
NYX	0:85b3fd62ea1a	1710	/* Get the DFSDM1 Audio clock configuration --------------------------------*/
NYX	0:85b3fd62ea1a	1711	PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
NYX	0:85b3fd62ea1a	1712
NYX	0:85b3fd62ea1a	1713	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1714	/* Get the DFSDM2 clock configuration --------------------------------------*/
NYX	0:85b3fd62ea1a	1715	PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
NYX	0:85b3fd62ea1a	1716
NYX	0:85b3fd62ea1a	1717	/* Get the DFSDM2 Audio clock configuration --------------------------------*/
NYX	0:85b3fd62ea1a	1718	PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE();
NYX	0:85b3fd62ea1a	1719
NYX	0:85b3fd62ea1a	1720	/* Get the LPTIM1 clock configuration --------------------------------------*/
NYX	0:85b3fd62ea1a	1721	PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
NYX	0:85b3fd62ea1a	1722
NYX	0:85b3fd62ea1a	1723	/* Get the SAI1 Block Aclock configuration ---------------------------------*/
NYX	0:85b3fd62ea1a	1724	PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE();
NYX	0:85b3fd62ea1a	1725
NYX	0:85b3fd62ea1a	1726	/* Get the SAI1 Block B clock configuration --------------------------------*/
NYX	0:85b3fd62ea1a	1727	PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE();
NYX	0:85b3fd62ea1a	1728	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1729
NYX	0:85b3fd62ea1a	1730	/* Get the TIM Prescaler configuration -------------------------------------*/
NYX	0:85b3fd62ea1a	1731	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
NYX	0:85b3fd62ea1a	1732	{
NYX	0:85b3fd62ea1a	1733	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
NYX	0:85b3fd62ea1a	1734	}
NYX	0:85b3fd62ea1a	1735	else
NYX	0:85b3fd62ea1a	1736	{
NYX	0:85b3fd62ea1a	1737	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
NYX	0:85b3fd62ea1a	1738	}
NYX	0:85b3fd62ea1a	1739	}
NYX	0:85b3fd62ea1a	1740
NYX	0:85b3fd62ea1a	1741	/**
NYX	0:85b3fd62ea1a	1742	* @brief Return the peripheral clock frequency for a given peripheral(I2S..)
NYX	0:85b3fd62ea1a	1743	* @note Return 0 if peripheral clock identifier not managed by this API
NYX	0:85b3fd62ea1a	1744	* @param PeriphClk: Peripheral clock identifier
NYX	0:85b3fd62ea1a	1745	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1746	* @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
NYX	0:85b3fd62ea1a	1747	* @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
NYX	0:85b3fd62ea1a	1748	* @retval Frequency in KHz
NYX	0:85b3fd62ea1a	1749	*/
NYX	0:85b3fd62ea1a	1750	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
NYX	0:85b3fd62ea1a	1751	{
NYX	0:85b3fd62ea1a	1752	/* This variable used to store the I2S clock frequency (value in Hz) */
NYX	0:85b3fd62ea1a	1753	uint32_t frequency = 0U;
NYX	0:85b3fd62ea1a	1754	/* This variable used to store the VCO Input (value in Hz) */
NYX	0:85b3fd62ea1a	1755	uint32_t vcoinput = 0U;
NYX	0:85b3fd62ea1a	1756	uint32_t srcclk = 0U;
NYX	0:85b3fd62ea1a	1757	/* This variable used to store the VCO Output (value in Hz) */
NYX	0:85b3fd62ea1a	1758	uint32_t vcooutput = 0U;
NYX	0:85b3fd62ea1a	1759	switch (PeriphClk)
NYX	0:85b3fd62ea1a	1760	{
NYX	0:85b3fd62ea1a	1761	case RCC_PERIPHCLK_I2S_APB1:
NYX	0:85b3fd62ea1a	1762	{
NYX	0:85b3fd62ea1a	1763	/* Get the current I2S source */
NYX	0:85b3fd62ea1a	1764	srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
NYX	0:85b3fd62ea1a	1765	switch (srcclk)
NYX	0:85b3fd62ea1a	1766	{
NYX	0:85b3fd62ea1a	1767	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
NYX	0:85b3fd62ea1a	1768	case RCC_I2SAPB1CLKSOURCE_EXT:
NYX	0:85b3fd62ea1a	1769	{
NYX	0:85b3fd62ea1a	1770	/* Set the I2S clock to the external clock value */
NYX	0:85b3fd62ea1a	1771	frequency = EXTERNAL_CLOCK_VALUE;
NYX	0:85b3fd62ea1a	1772	break;
NYX	0:85b3fd62ea1a	1773	}
NYX	0:85b3fd62ea1a	1774	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
NYX	0:85b3fd62ea1a	1775	case RCC_I2SAPB1CLKSOURCE_PLLI2S:
NYX	0:85b3fd62ea1a	1776	{
NYX	0:85b3fd62ea1a	1777	if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
NYX	0:85b3fd62ea1a	1778	{
NYX	0:85b3fd62ea1a	1779	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1780	vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	1781	}
NYX	0:85b3fd62ea1a	1782	else
NYX	0:85b3fd62ea1a	1783	{
NYX	0:85b3fd62ea1a	1784	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	1785	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
NYX	0:85b3fd62ea1a	1786	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	1787	{
NYX	0:85b3fd62ea1a	1788	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1789	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	1790	}
NYX	0:85b3fd62ea1a	1791	else
NYX	0:85b3fd62ea1a	1792	{
NYX	0:85b3fd62ea1a	1793	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1794	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	1795	}
NYX	0:85b3fd62ea1a	1796	}
NYX	0:85b3fd62ea1a	1797	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	1798	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
NYX	0:85b3fd62ea1a	1799	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
NYX	0:85b3fd62ea1a	1800	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
NYX	0:85b3fd62ea1a	1801	break;
NYX	0:85b3fd62ea1a	1802	}
NYX	0:85b3fd62ea1a	1803	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
NYX	0:85b3fd62ea1a	1804	case RCC_I2SAPB1CLKSOURCE_PLLR:
NYX	0:85b3fd62ea1a	1805	{
NYX	0:85b3fd62ea1a	1806	/* Configure the PLL division factor R */
NYX	0:85b3fd62ea1a	1807	/* PLL_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	1808	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	1809	{
NYX	0:85b3fd62ea1a	1810	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1811	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	1812	}
NYX	0:85b3fd62ea1a	1813	else
NYX	0:85b3fd62ea1a	1814	{
NYX	0:85b3fd62ea1a	1815	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1816	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	1817	}
NYX	0:85b3fd62ea1a	1818
NYX	0:85b3fd62ea1a	1819	/* PLL_VCO Output = PLL_VCO Input * PLLN */
NYX	0:85b3fd62ea1a	1820	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
NYX	0:85b3fd62ea1a	1821	/* I2S_CLK = PLL_VCO Output/PLLR */
NYX	0:85b3fd62ea1a	1822	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
NYX	0:85b3fd62ea1a	1823	break;
NYX	0:85b3fd62ea1a	1824	}
NYX	0:85b3fd62ea1a	1825	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
NYX	0:85b3fd62ea1a	1826	case RCC_I2SAPB1CLKSOURCE_PLLSRC:
NYX	0:85b3fd62ea1a	1827	{
NYX	0:85b3fd62ea1a	1828	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	1829	{
NYX	0:85b3fd62ea1a	1830	frequency = HSE_VALUE;
NYX	0:85b3fd62ea1a	1831	}
NYX	0:85b3fd62ea1a	1832	else
NYX	0:85b3fd62ea1a	1833	{
NYX	0:85b3fd62ea1a	1834	frequency = HSI_VALUE;
NYX	0:85b3fd62ea1a	1835	}
NYX	0:85b3fd62ea1a	1836	break;
NYX	0:85b3fd62ea1a	1837	}
NYX	0:85b3fd62ea1a	1838	/* Clock not enabled for I2S*/
NYX	0:85b3fd62ea1a	1839	default:
NYX	0:85b3fd62ea1a	1840	{
NYX	0:85b3fd62ea1a	1841	frequency = 0U;
NYX	0:85b3fd62ea1a	1842	break;
NYX	0:85b3fd62ea1a	1843	}
NYX	0:85b3fd62ea1a	1844	}
NYX	0:85b3fd62ea1a	1845	break;
NYX	0:85b3fd62ea1a	1846	}
NYX	0:85b3fd62ea1a	1847	case RCC_PERIPHCLK_I2S_APB2:
NYX	0:85b3fd62ea1a	1848	{
NYX	0:85b3fd62ea1a	1849	/* Get the current I2S source */
NYX	0:85b3fd62ea1a	1850	srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
NYX	0:85b3fd62ea1a	1851	switch (srcclk)
NYX	0:85b3fd62ea1a	1852	{
NYX	0:85b3fd62ea1a	1853	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
NYX	0:85b3fd62ea1a	1854	case RCC_I2SAPB2CLKSOURCE_EXT:
NYX	0:85b3fd62ea1a	1855	{
NYX	0:85b3fd62ea1a	1856	/* Set the I2S clock to the external clock value */
NYX	0:85b3fd62ea1a	1857	frequency = EXTERNAL_CLOCK_VALUE;
NYX	0:85b3fd62ea1a	1858	break;
NYX	0:85b3fd62ea1a	1859	}
NYX	0:85b3fd62ea1a	1860	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
NYX	0:85b3fd62ea1a	1861	case RCC_I2SAPB2CLKSOURCE_PLLI2S:
NYX	0:85b3fd62ea1a	1862	{
NYX	0:85b3fd62ea1a	1863	if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
NYX	0:85b3fd62ea1a	1864	{
NYX	0:85b3fd62ea1a	1865	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1866	vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	1867	}
NYX	0:85b3fd62ea1a	1868	else
NYX	0:85b3fd62ea1a	1869	{
NYX	0:85b3fd62ea1a	1870	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	1871	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
NYX	0:85b3fd62ea1a	1872	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	1873	{
NYX	0:85b3fd62ea1a	1874	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1875	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	1876	}
NYX	0:85b3fd62ea1a	1877	else
NYX	0:85b3fd62ea1a	1878	{
NYX	0:85b3fd62ea1a	1879	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1880	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	1881	}
NYX	0:85b3fd62ea1a	1882	}
NYX	0:85b3fd62ea1a	1883	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	1884	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
NYX	0:85b3fd62ea1a	1885	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
NYX	0:85b3fd62ea1a	1886	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
NYX	0:85b3fd62ea1a	1887	break;
NYX	0:85b3fd62ea1a	1888	}
NYX	0:85b3fd62ea1a	1889	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
NYX	0:85b3fd62ea1a	1890	case RCC_I2SAPB2CLKSOURCE_PLLR:
NYX	0:85b3fd62ea1a	1891	{
NYX	0:85b3fd62ea1a	1892	/* Configure the PLL division factor R */
NYX	0:85b3fd62ea1a	1893	/* PLL_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	1894	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	1895	{
NYX	0:85b3fd62ea1a	1896	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1897	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	1898	}
NYX	0:85b3fd62ea1a	1899	else
NYX	0:85b3fd62ea1a	1900	{
NYX	0:85b3fd62ea1a	1901	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	1902	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	1903	}
NYX	0:85b3fd62ea1a	1904
NYX	0:85b3fd62ea1a	1905	/* PLL_VCO Output = PLL_VCO Input * PLLN */
NYX	0:85b3fd62ea1a	1906	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
NYX	0:85b3fd62ea1a	1907	/* I2S_CLK = PLL_VCO Output/PLLR */
NYX	0:85b3fd62ea1a	1908	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
NYX	0:85b3fd62ea1a	1909	break;
NYX	0:85b3fd62ea1a	1910	}
NYX	0:85b3fd62ea1a	1911	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
NYX	0:85b3fd62ea1a	1912	case RCC_I2SAPB2CLKSOURCE_PLLSRC:
NYX	0:85b3fd62ea1a	1913	{
NYX	0:85b3fd62ea1a	1914	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	1915	{
NYX	0:85b3fd62ea1a	1916	frequency = HSE_VALUE;
NYX	0:85b3fd62ea1a	1917	}
NYX	0:85b3fd62ea1a	1918	else
NYX	0:85b3fd62ea1a	1919	{
NYX	0:85b3fd62ea1a	1920	frequency = HSI_VALUE;
NYX	0:85b3fd62ea1a	1921	}
NYX	0:85b3fd62ea1a	1922	break;
NYX	0:85b3fd62ea1a	1923	}
NYX	0:85b3fd62ea1a	1924	/* Clock not enabled for I2S*/
NYX	0:85b3fd62ea1a	1925	default:
NYX	0:85b3fd62ea1a	1926	{
NYX	0:85b3fd62ea1a	1927	frequency = 0U;
NYX	0:85b3fd62ea1a	1928	break;
NYX	0:85b3fd62ea1a	1929	}
NYX	0:85b3fd62ea1a	1930	}
NYX	0:85b3fd62ea1a	1931	break;
NYX	0:85b3fd62ea1a	1932	}
NYX	0:85b3fd62ea1a	1933	}
NYX	0:85b3fd62ea1a	1934	return frequency;
NYX	0:85b3fd62ea1a	1935	}
NYX	0:85b3fd62ea1a	1936	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1937
NYX	0:85b3fd62ea1a	1938	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	1939	/**
NYX	0:85b3fd62ea1a	1940	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
NYX	0:85b3fd62ea1a	1941	* RCC_PeriphCLKInitTypeDef.
NYX	0:85b3fd62ea1a	1942	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	1943	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
NYX	0:85b3fd62ea1a	1944	*
NYX	0:85b3fd62ea1a	1945	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
NYX	0:85b3fd62ea1a	1946	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
NYX	0:85b3fd62ea1a	1947	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
NYX	0:85b3fd62ea1a	1948	*
NYX	0:85b3fd62ea1a	1949	* @retval HAL status
NYX	0:85b3fd62ea1a	1950	*/
NYX	0:85b3fd62ea1a	1951	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	1952	{
NYX	0:85b3fd62ea1a	1953	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	1954	uint32_t tmpreg1 = 0U;
NYX	0:85b3fd62ea1a	1955
NYX	0:85b3fd62ea1a	1956	/* Check the parameters */
NYX	0:85b3fd62ea1a	1957	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
NYX	0:85b3fd62ea1a	1958
NYX	0:85b3fd62ea1a	1959	/---------------------------- RTC configuration ---------------------------/
NYX	0:85b3fd62ea1a	1960	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
NYX	0:85b3fd62ea1a	1961	{
NYX	0:85b3fd62ea1a	1962	/* Check for RTC Parameters used to output RTCCLK */
NYX	0:85b3fd62ea1a	1963	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
NYX	0:85b3fd62ea1a	1964
NYX	0:85b3fd62ea1a	1965	/* Enable Power Clock*/
NYX	0:85b3fd62ea1a	1966	__HAL_RCC_PWR_CLK_ENABLE();
NYX	0:85b3fd62ea1a	1967
NYX	0:85b3fd62ea1a	1968	/* Enable write access to Backup domain */
NYX	0:85b3fd62ea1a	1969	PWR->CR \|= PWR_CR_DBP;
NYX	0:85b3fd62ea1a	1970
NYX	0:85b3fd62ea1a	1971	/* Get tick */
NYX	0:85b3fd62ea1a	1972	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1973
NYX	0:85b3fd62ea1a	1974	while((PWR->CR & PWR_CR_DBP) == RESET)
NYX	0:85b3fd62ea1a	1975	{
NYX	0:85b3fd62ea1a	1976	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	1977	{
NYX	0:85b3fd62ea1a	1978	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1979	}
NYX	0:85b3fd62ea1a	1980	}
NYX	0:85b3fd62ea1a	1981	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
NYX	0:85b3fd62ea1a	1982	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
NYX	0:85b3fd62ea1a	1983	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
NYX	0:85b3fd62ea1a	1984	{
NYX	0:85b3fd62ea1a	1985	/* Store the content of BDCR register before the reset of Backup Domain */
NYX	0:85b3fd62ea1a	1986	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	1987	/* RTC Clock selection can be changed only if the Backup Domain is reset */
NYX	0:85b3fd62ea1a	1988	__HAL_RCC_BACKUPRESET_FORCE();
NYX	0:85b3fd62ea1a	1989	__HAL_RCC_BACKUPRESET_RELEASE();
NYX	0:85b3fd62ea1a	1990	/* Restore the Content of BDCR register */
NYX	0:85b3fd62ea1a	1991	RCC->BDCR = tmpreg1;
NYX	0:85b3fd62ea1a	1992
NYX	0:85b3fd62ea1a	1993	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
NYX	0:85b3fd62ea1a	1994	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
NYX	0:85b3fd62ea1a	1995	{
NYX	0:85b3fd62ea1a	1996	/* Get tick */
NYX	0:85b3fd62ea1a	1997	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1998
NYX	0:85b3fd62ea1a	1999	/* Wait till LSE is ready */
NYX	0:85b3fd62ea1a	2000	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
NYX	0:85b3fd62ea1a	2001	{
NYX	0:85b3fd62ea1a	2002	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2003	{
NYX	0:85b3fd62ea1a	2004	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2005	}
NYX	0:85b3fd62ea1a	2006	}
NYX	0:85b3fd62ea1a	2007	}
NYX	0:85b3fd62ea1a	2008	}
NYX	0:85b3fd62ea1a	2009	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
NYX	0:85b3fd62ea1a	2010	}
NYX	0:85b3fd62ea1a	2011	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	2012
NYX	0:85b3fd62ea1a	2013	/---------------------------- TIM configuration ---------------------------/
NYX	0:85b3fd62ea1a	2014	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
NYX	0:85b3fd62ea1a	2015	{
NYX	0:85b3fd62ea1a	2016	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
NYX	0:85b3fd62ea1a	2017	}
NYX	0:85b3fd62ea1a	2018	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	2019
NYX	0:85b3fd62ea1a	2020	/---------------------------- FMPI2C1 Configuration -----------------------/
NYX	0:85b3fd62ea1a	2021	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
NYX	0:85b3fd62ea1a	2022	{
NYX	0:85b3fd62ea1a	2023	/* Check the parameters */
NYX	0:85b3fd62ea1a	2024	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
NYX	0:85b3fd62ea1a	2025
NYX	0:85b3fd62ea1a	2026	/* Configure the FMPI2C1 clock source */
NYX	0:85b3fd62ea1a	2027	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
NYX	0:85b3fd62ea1a	2028	}
NYX	0:85b3fd62ea1a	2029	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	2030
NYX	0:85b3fd62ea1a	2031	/---------------------------- LPTIM1 Configuration ------------------------/
NYX	0:85b3fd62ea1a	2032	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
NYX	0:85b3fd62ea1a	2033	{
NYX	0:85b3fd62ea1a	2034	/* Check the parameters */
NYX	0:85b3fd62ea1a	2035	assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
NYX	0:85b3fd62ea1a	2036
NYX	0:85b3fd62ea1a	2037	/* Configure the LPTIM1 clock source */
NYX	0:85b3fd62ea1a	2038	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
NYX	0:85b3fd62ea1a	2039	}
NYX	0:85b3fd62ea1a	2040
NYX	0:85b3fd62ea1a	2041	/---------------------------- I2S Configuration ---------------------------/
NYX	0:85b3fd62ea1a	2042	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
NYX	0:85b3fd62ea1a	2043	{
NYX	0:85b3fd62ea1a	2044	/* Check the parameters */
NYX	0:85b3fd62ea1a	2045	assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
NYX	0:85b3fd62ea1a	2046
NYX	0:85b3fd62ea1a	2047	/* Configure the I2S clock source */
NYX	0:85b3fd62ea1a	2048	__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
NYX	0:85b3fd62ea1a	2049	}
NYX	0:85b3fd62ea1a	2050
NYX	0:85b3fd62ea1a	2051	return HAL_OK;
NYX	0:85b3fd62ea1a	2052	}
NYX	0:85b3fd62ea1a	2053
NYX	0:85b3fd62ea1a	2054	/**
NYX	0:85b3fd62ea1a	2055	* @brief Configures the RCC_OscInitStruct according to the internal
NYX	0:85b3fd62ea1a	2056	* RCC configuration registers.
NYX	0:85b3fd62ea1a	2057	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	2058	* will be configured.
NYX	0:85b3fd62ea1a	2059	* @retval None
NYX	0:85b3fd62ea1a	2060	*/
NYX	0:85b3fd62ea1a	2061	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	2062	{
NYX	0:85b3fd62ea1a	2063	uint32_t tempreg;
NYX	0:85b3fd62ea1a	2064
NYX	0:85b3fd62ea1a	2065	/* Set all possible values for the extended clock type parameter------------*/
NYX	0:85b3fd62ea1a	2066	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
NYX	0:85b3fd62ea1a	2067
NYX	0:85b3fd62ea1a	2068	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
NYX	0:85b3fd62ea1a	2069	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	2070
NYX	0:85b3fd62ea1a	2071	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
NYX	0:85b3fd62ea1a	2072	{
NYX	0:85b3fd62ea1a	2073	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
NYX	0:85b3fd62ea1a	2074	}
NYX	0:85b3fd62ea1a	2075	else
NYX	0:85b3fd62ea1a	2076	{
NYX	0:85b3fd62ea1a	2077	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
NYX	0:85b3fd62ea1a	2078	}
NYX	0:85b3fd62ea1a	2079	/* Get the FMPI2C1 clock configuration -------------------------------------*/
NYX	0:85b3fd62ea1a	2080	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
NYX	0:85b3fd62ea1a	2081
NYX	0:85b3fd62ea1a	2082	/* Get the I2S clock configuration -----------------------------------------*/
NYX	0:85b3fd62ea1a	2083	PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
NYX	0:85b3fd62ea1a	2084
NYX	0:85b3fd62ea1a	2085
NYX	0:85b3fd62ea1a	2086	}
NYX	0:85b3fd62ea1a	2087	/**
NYX	0:85b3fd62ea1a	2088	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
NYX	0:85b3fd62ea1a	2089	* @note Return 0 if peripheral clock identifier not managed by this API
NYX	0:85b3fd62ea1a	2090	* @param PeriphClk: Peripheral clock identifier
NYX	0:85b3fd62ea1a	2091	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2092	* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
NYX	0:85b3fd62ea1a	2093	* @retval Frequency in KHz
NYX	0:85b3fd62ea1a	2094	*/
NYX	0:85b3fd62ea1a	2095	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
NYX	0:85b3fd62ea1a	2096	{
NYX	0:85b3fd62ea1a	2097	/* This variable used to store the I2S clock frequency (value in Hz) */
NYX	0:85b3fd62ea1a	2098	uint32_t frequency = 0U;
NYX	0:85b3fd62ea1a	2099	/* This variable used to store the VCO Input (value in Hz) */
NYX	0:85b3fd62ea1a	2100	uint32_t vcoinput = 0U;
NYX	0:85b3fd62ea1a	2101	uint32_t srcclk = 0U;
NYX	0:85b3fd62ea1a	2102	/* This variable used to store the VCO Output (value in Hz) */
NYX	0:85b3fd62ea1a	2103	uint32_t vcooutput = 0U;
NYX	0:85b3fd62ea1a	2104	switch (PeriphClk)
NYX	0:85b3fd62ea1a	2105	{
NYX	0:85b3fd62ea1a	2106	case RCC_PERIPHCLK_I2S:
NYX	0:85b3fd62ea1a	2107	{
NYX	0:85b3fd62ea1a	2108	/* Get the current I2S source */
NYX	0:85b3fd62ea1a	2109	srcclk = __HAL_RCC_GET_I2S_SOURCE();
NYX	0:85b3fd62ea1a	2110	switch (srcclk)
NYX	0:85b3fd62ea1a	2111	{
NYX	0:85b3fd62ea1a	2112	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
NYX	0:85b3fd62ea1a	2113	case RCC_I2SAPBCLKSOURCE_EXT:
NYX	0:85b3fd62ea1a	2114	{
NYX	0:85b3fd62ea1a	2115	/* Set the I2S clock to the external clock value */
NYX	0:85b3fd62ea1a	2116	frequency = EXTERNAL_CLOCK_VALUE;
NYX	0:85b3fd62ea1a	2117	break;
NYX	0:85b3fd62ea1a	2118	}
NYX	0:85b3fd62ea1a	2119	/* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
NYX	0:85b3fd62ea1a	2120	case RCC_I2SAPBCLKSOURCE_PLLR:
NYX	0:85b3fd62ea1a	2121	{
NYX	0:85b3fd62ea1a	2122	/* Configure the PLL division factor R */
NYX	0:85b3fd62ea1a	2123	/* PLL_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	2124	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	2125	{
NYX	0:85b3fd62ea1a	2126	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	2127	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	2128	}
NYX	0:85b3fd62ea1a	2129	else
NYX	0:85b3fd62ea1a	2130	{
NYX	0:85b3fd62ea1a	2131	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	2132	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	2133	}
NYX	0:85b3fd62ea1a	2134
NYX	0:85b3fd62ea1a	2135	/* PLL_VCO Output = PLL_VCO Input * PLLN */
NYX	0:85b3fd62ea1a	2136	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
NYX	0:85b3fd62ea1a	2137	/* I2S_CLK = PLL_VCO Output/PLLR */
NYX	0:85b3fd62ea1a	2138	frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
NYX	0:85b3fd62ea1a	2139	break;
NYX	0:85b3fd62ea1a	2140	}
NYX	0:85b3fd62ea1a	2141	/* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
NYX	0:85b3fd62ea1a	2142	case RCC_I2SAPBCLKSOURCE_PLLSRC:
NYX	0:85b3fd62ea1a	2143	{
NYX	0:85b3fd62ea1a	2144	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	2145	{
NYX	0:85b3fd62ea1a	2146	frequency = HSE_VALUE;
NYX	0:85b3fd62ea1a	2147	}
NYX	0:85b3fd62ea1a	2148	else
NYX	0:85b3fd62ea1a	2149	{
NYX	0:85b3fd62ea1a	2150	frequency = HSI_VALUE;
NYX	0:85b3fd62ea1a	2151	}
NYX	0:85b3fd62ea1a	2152	break;
NYX	0:85b3fd62ea1a	2153	}
NYX	0:85b3fd62ea1a	2154	/* Clock not enabled for I2S*/
NYX	0:85b3fd62ea1a	2155	default:
NYX	0:85b3fd62ea1a	2156	{
NYX	0:85b3fd62ea1a	2157	frequency = 0U;
NYX	0:85b3fd62ea1a	2158	break;
NYX	0:85b3fd62ea1a	2159	}
NYX	0:85b3fd62ea1a	2160	}
NYX	0:85b3fd62ea1a	2161	break;
NYX	0:85b3fd62ea1a	2162	}
NYX	0:85b3fd62ea1a	2163	}
NYX	0:85b3fd62ea1a	2164	return frequency;
NYX	0:85b3fd62ea1a	2165	}
NYX	0:85b3fd62ea1a	2166	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	2167
NYX	0:85b3fd62ea1a	2168	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
NYX	0:85b3fd62ea1a	2169	/**
NYX	0:85b3fd62ea1a	2170	* @brief Initializes the RCC extended peripherals clocks according to the specified
NYX	0:85b3fd62ea1a	2171	* parameters in the RCC_PeriphCLKInitTypeDef.
NYX	0:85b3fd62ea1a	2172	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	2173	* contains the configuration information for the Extended Peripherals
NYX	0:85b3fd62ea1a	2174	* clocks(I2S, SAI, LTDC RTC and TIM).
NYX	0:85b3fd62ea1a	2175	*
NYX	0:85b3fd62ea1a	2176	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
NYX	0:85b3fd62ea1a	2177	* the RTC clock source; in this case the Backup domain will be reset in
NYX	0:85b3fd62ea1a	2178	* order to modify the RTC Clock source, as consequence RTC registers (including
NYX	0:85b3fd62ea1a	2179	* the backup registers) and RCC_BDCR register are set to their reset values.
NYX	0:85b3fd62ea1a	2180	*
NYX	0:85b3fd62ea1a	2181	* @retval HAL status
NYX	0:85b3fd62ea1a	2182	*/
NYX	0:85b3fd62ea1a	2183	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	2184	{
NYX	0:85b3fd62ea1a	2185	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	2186	uint32_t tmpreg1 = 0U;
NYX	0:85b3fd62ea1a	2187
NYX	0:85b3fd62ea1a	2188	/* Check the parameters */
NYX	0:85b3fd62ea1a	2189	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
NYX	0:85b3fd62ea1a	2190
NYX	0:85b3fd62ea1a	2191	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------/
NYX	0:85b3fd62ea1a	2192	/----------------------- Common configuration SAI/I2S ---------------------/
NYX	0:85b3fd62ea1a	2193	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
NYX	0:85b3fd62ea1a	2194	factor is common parameters for both peripherals */
NYX	0:85b3fd62ea1a	2195	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
NYX	0:85b3fd62ea1a	2196	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
NYX	0:85b3fd62ea1a	2197	{
NYX	0:85b3fd62ea1a	2198	/* check for Parameters */
NYX	0:85b3fd62ea1a	2199	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
NYX	0:85b3fd62ea1a	2200
NYX	0:85b3fd62ea1a	2201	/* Disable the PLLI2S */
NYX	0:85b3fd62ea1a	2202	__HAL_RCC_PLLI2S_DISABLE();
NYX	0:85b3fd62ea1a	2203	/* Get tick */
NYX	0:85b3fd62ea1a	2204	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2205	/* Wait till PLLI2S is disabled */
NYX	0:85b3fd62ea1a	2206	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
NYX	0:85b3fd62ea1a	2207	{
NYX	0:85b3fd62ea1a	2208	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2209	{
NYX	0:85b3fd62ea1a	2210	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	2211	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2212	}
NYX	0:85b3fd62ea1a	2213	}
NYX	0:85b3fd62ea1a	2214
NYX	0:85b3fd62ea1a	2215	/---------------------------- I2S configuration -------------------------/
NYX	0:85b3fd62ea1a	2216	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
NYX	0:85b3fd62ea1a	2217	only for I2S configuration */
NYX	0:85b3fd62ea1a	2218	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
NYX	0:85b3fd62ea1a	2219	{
NYX	0:85b3fd62ea1a	2220	/* check for Parameters */
NYX	0:85b3fd62ea1a	2221	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
NYX	0:85b3fd62ea1a	2222	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	2223	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
NYX	0:85b3fd62ea1a	2224	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
NYX	0:85b3fd62ea1a	2225	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	2226	}
NYX	0:85b3fd62ea1a	2227
NYX	0:85b3fd62ea1a	2228	/---------------------------- SAI configuration -------------------------/
NYX	0:85b3fd62ea1a	2229	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
NYX	0:85b3fd62ea1a	2230	be added only for SAI configuration */
NYX	0:85b3fd62ea1a	2231	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
NYX	0:85b3fd62ea1a	2232	{
NYX	0:85b3fd62ea1a	2233	/* Check the PLLI2S division factors */
NYX	0:85b3fd62ea1a	2234	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
NYX	0:85b3fd62ea1a	2235	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
NYX	0:85b3fd62ea1a	2236
NYX	0:85b3fd62ea1a	2237	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	2238	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	2239	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	2240	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	2241	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	2242	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
NYX	0:85b3fd62ea1a	2243	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
NYX	0:85b3fd62ea1a	2244	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	2245	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
NYX	0:85b3fd62ea1a	2246	}
NYX	0:85b3fd62ea1a	2247
NYX	0:85b3fd62ea1a	2248	/* Enable the PLLI2S */
NYX	0:85b3fd62ea1a	2249	__HAL_RCC_PLLI2S_ENABLE();
NYX	0:85b3fd62ea1a	2250	/* Get tick */
NYX	0:85b3fd62ea1a	2251	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2252	/* Wait till PLLI2S is ready */
NYX	0:85b3fd62ea1a	2253	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
NYX	0:85b3fd62ea1a	2254	{
NYX	0:85b3fd62ea1a	2255	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2256	{
NYX	0:85b3fd62ea1a	2257	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	2258	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2259	}
NYX	0:85b3fd62ea1a	2260	}
NYX	0:85b3fd62ea1a	2261	}
NYX	0:85b3fd62ea1a	2262	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	2263
NYX	0:85b3fd62ea1a	2264	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
NYX	0:85b3fd62ea1a	2265	/----------------------- Common configuration SAI/LTDC --------------------/
NYX	0:85b3fd62ea1a	2266	/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
NYX	0:85b3fd62ea1a	2267	factor is common parameters for both peripherals */
NYX	0:85b3fd62ea1a	2268	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
NYX	0:85b3fd62ea1a	2269	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
NYX	0:85b3fd62ea1a	2270	{
NYX	0:85b3fd62ea1a	2271	/* Check the PLLSAI division factors */
NYX	0:85b3fd62ea1a	2272	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
NYX	0:85b3fd62ea1a	2273
NYX	0:85b3fd62ea1a	2274	/* Disable PLLSAI Clock */
NYX	0:85b3fd62ea1a	2275	__HAL_RCC_PLLSAI_DISABLE();
NYX	0:85b3fd62ea1a	2276	/* Get tick */
NYX	0:85b3fd62ea1a	2277	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2278	/* Wait till PLLSAI is disabled */
NYX	0:85b3fd62ea1a	2279	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
NYX	0:85b3fd62ea1a	2280	{
NYX	0:85b3fd62ea1a	2281	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2282	{
NYX	0:85b3fd62ea1a	2283	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	2284	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2285	}
NYX	0:85b3fd62ea1a	2286	}
NYX	0:85b3fd62ea1a	2287
NYX	0:85b3fd62ea1a	2288	/---------------------------- SAI configuration -------------------------/
NYX	0:85b3fd62ea1a	2289	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
NYX	0:85b3fd62ea1a	2290	be added only for SAI configuration */
NYX	0:85b3fd62ea1a	2291	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
NYX	0:85b3fd62ea1a	2292	{
NYX	0:85b3fd62ea1a	2293	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
NYX	0:85b3fd62ea1a	2294	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
NYX	0:85b3fd62ea1a	2295
NYX	0:85b3fd62ea1a	2296	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	2297	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
NYX	0:85b3fd62ea1a	2298	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	2299	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
NYX	0:85b3fd62ea1a	2300	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
NYX	0:85b3fd62ea1a	2301	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
NYX	0:85b3fd62ea1a	2302	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
NYX	0:85b3fd62ea1a	2303	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
NYX	0:85b3fd62ea1a	2304	}
NYX	0:85b3fd62ea1a	2305
NYX	0:85b3fd62ea1a	2306	/---------------------------- LTDC configuration ------------------------/
NYX	0:85b3fd62ea1a	2307	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
NYX	0:85b3fd62ea1a	2308	{
NYX	0:85b3fd62ea1a	2309	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
NYX	0:85b3fd62ea1a	2310	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
NYX	0:85b3fd62ea1a	2311
NYX	0:85b3fd62ea1a	2312	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
NYX	0:85b3fd62ea1a	2313	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
NYX	0:85b3fd62ea1a	2314	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	2315	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
NYX	0:85b3fd62ea1a	2316	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
NYX	0:85b3fd62ea1a	2317	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
NYX	0:85b3fd62ea1a	2318	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
NYX	0:85b3fd62ea1a	2319	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
NYX	0:85b3fd62ea1a	2320	}
NYX	0:85b3fd62ea1a	2321	/* Enable PLLSAI Clock */
NYX	0:85b3fd62ea1a	2322	__HAL_RCC_PLLSAI_ENABLE();
NYX	0:85b3fd62ea1a	2323	/* Get tick */
NYX	0:85b3fd62ea1a	2324	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2325	/* Wait till PLLSAI is ready */
NYX	0:85b3fd62ea1a	2326	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
NYX	0:85b3fd62ea1a	2327	{
NYX	0:85b3fd62ea1a	2328	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2329	{
NYX	0:85b3fd62ea1a	2330	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	2331	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2332	}
NYX	0:85b3fd62ea1a	2333	}
NYX	0:85b3fd62ea1a	2334	}
NYX	0:85b3fd62ea1a	2335	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	2336
NYX	0:85b3fd62ea1a	2337	/---------------------------- RTC configuration ---------------------------/
NYX	0:85b3fd62ea1a	2338	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
NYX	0:85b3fd62ea1a	2339	{
NYX	0:85b3fd62ea1a	2340	/* Check for RTC Parameters used to output RTCCLK */
NYX	0:85b3fd62ea1a	2341	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
NYX	0:85b3fd62ea1a	2342
NYX	0:85b3fd62ea1a	2343	/* Enable Power Clock*/
NYX	0:85b3fd62ea1a	2344	__HAL_RCC_PWR_CLK_ENABLE();
NYX	0:85b3fd62ea1a	2345
NYX	0:85b3fd62ea1a	2346	/* Enable write access to Backup domain */
NYX	0:85b3fd62ea1a	2347	PWR->CR \|= PWR_CR_DBP;
NYX	0:85b3fd62ea1a	2348
NYX	0:85b3fd62ea1a	2349	/* Get tick */
NYX	0:85b3fd62ea1a	2350	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2351
NYX	0:85b3fd62ea1a	2352	while((PWR->CR & PWR_CR_DBP) == RESET)
NYX	0:85b3fd62ea1a	2353	{
NYX	0:85b3fd62ea1a	2354	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2355	{
NYX	0:85b3fd62ea1a	2356	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2357	}
NYX	0:85b3fd62ea1a	2358	}
NYX	0:85b3fd62ea1a	2359	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
NYX	0:85b3fd62ea1a	2360	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
NYX	0:85b3fd62ea1a	2361	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
NYX	0:85b3fd62ea1a	2362	{
NYX	0:85b3fd62ea1a	2363	/* Store the content of BDCR register before the reset of Backup Domain */
NYX	0:85b3fd62ea1a	2364	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	2365	/* RTC Clock selection can be changed only if the Backup Domain is reset */
NYX	0:85b3fd62ea1a	2366	__HAL_RCC_BACKUPRESET_FORCE();
NYX	0:85b3fd62ea1a	2367	__HAL_RCC_BACKUPRESET_RELEASE();
NYX	0:85b3fd62ea1a	2368	/* Restore the Content of BDCR register */
NYX	0:85b3fd62ea1a	2369	RCC->BDCR = tmpreg1;
NYX	0:85b3fd62ea1a	2370
NYX	0:85b3fd62ea1a	2371	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
NYX	0:85b3fd62ea1a	2372	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
NYX	0:85b3fd62ea1a	2373	{
NYX	0:85b3fd62ea1a	2374	/* Get tick */
NYX	0:85b3fd62ea1a	2375	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2376
NYX	0:85b3fd62ea1a	2377	/* Wait till LSE is ready */
NYX	0:85b3fd62ea1a	2378	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
NYX	0:85b3fd62ea1a	2379	{
NYX	0:85b3fd62ea1a	2380	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2381	{
NYX	0:85b3fd62ea1a	2382	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2383	}
NYX	0:85b3fd62ea1a	2384	}
NYX	0:85b3fd62ea1a	2385	}
NYX	0:85b3fd62ea1a	2386	}
NYX	0:85b3fd62ea1a	2387	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
NYX	0:85b3fd62ea1a	2388	}
NYX	0:85b3fd62ea1a	2389	/--------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	2390
NYX	0:85b3fd62ea1a	2391	/---------------------------- TIM configuration ---------------------------/
NYX	0:85b3fd62ea1a	2392	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
NYX	0:85b3fd62ea1a	2393	{
NYX	0:85b3fd62ea1a	2394	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
NYX	0:85b3fd62ea1a	2395	}
NYX	0:85b3fd62ea1a	2396	return HAL_OK;
NYX	0:85b3fd62ea1a	2397	}
NYX	0:85b3fd62ea1a	2398
NYX	0:85b3fd62ea1a	2399	/**
NYX	0:85b3fd62ea1a	2400	* @brief Configures the PeriphClkInit according to the internal
NYX	0:85b3fd62ea1a	2401	* RCC configuration registers.
NYX	0:85b3fd62ea1a	2402	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	2403	* will be configured.
NYX	0:85b3fd62ea1a	2404	* @retval None
NYX	0:85b3fd62ea1a	2405	*/
NYX	0:85b3fd62ea1a	2406	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	2407	{
NYX	0:85b3fd62ea1a	2408	uint32_t tempreg;
NYX	0:85b3fd62ea1a	2409
NYX	0:85b3fd62ea1a	2410	/* Set all possible values for the extended clock type parameter------------*/
NYX	0:85b3fd62ea1a	2411	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \| RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
NYX	0:85b3fd62ea1a	2412
NYX	0:85b3fd62ea1a	2413	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
NYX	0:85b3fd62ea1a	2414	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
NYX	0:85b3fd62ea1a	2415	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	2416	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
NYX	0:85b3fd62ea1a	2417	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
NYX	0:85b3fd62ea1a	2418	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
NYX	0:85b3fd62ea1a	2419	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
NYX	0:85b3fd62ea1a	2420	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
NYX	0:85b3fd62ea1a	2421	/* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
NYX	0:85b3fd62ea1a	2422	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
NYX	0:85b3fd62ea1a	2423	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
NYX	0:85b3fd62ea1a	2424	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
NYX	0:85b3fd62ea1a	2425	/* Get the RTC Clock configuration -----------------------------------------------*/
NYX	0:85b3fd62ea1a	2426	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
NYX	0:85b3fd62ea1a	2427	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	2428
NYX	0:85b3fd62ea1a	2429	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
NYX	0:85b3fd62ea1a	2430	{
NYX	0:85b3fd62ea1a	2431	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
NYX	0:85b3fd62ea1a	2432	}
NYX	0:85b3fd62ea1a	2433	else
NYX	0:85b3fd62ea1a	2434	{
NYX	0:85b3fd62ea1a	2435	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
NYX	0:85b3fd62ea1a	2436	}
NYX	0:85b3fd62ea1a	2437	}
NYX	0:85b3fd62ea1a	2438
NYX	0:85b3fd62ea1a	2439	/**
NYX	0:85b3fd62ea1a	2440	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
NYX	0:85b3fd62ea1a	2441	* @note Return 0 if peripheral clock identifier not managed by this API
NYX	0:85b3fd62ea1a	2442	* @param PeriphClk: Peripheral clock identifier
NYX	0:85b3fd62ea1a	2443	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2444	* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
NYX	0:85b3fd62ea1a	2445	* @retval Frequency in KHz
NYX	0:85b3fd62ea1a	2446	*/
NYX	0:85b3fd62ea1a	2447	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
NYX	0:85b3fd62ea1a	2448	{
NYX	0:85b3fd62ea1a	2449	/* This variable used to store the I2S clock frequency (value in Hz) */
NYX	0:85b3fd62ea1a	2450	uint32_t frequency = 0U;
NYX	0:85b3fd62ea1a	2451	/* This variable used to store the VCO Input (value in Hz) */
NYX	0:85b3fd62ea1a	2452	uint32_t vcoinput = 0U;
NYX	0:85b3fd62ea1a	2453	uint32_t srcclk = 0U;
NYX	0:85b3fd62ea1a	2454	/* This variable used to store the VCO Output (value in Hz) */
NYX	0:85b3fd62ea1a	2455	uint32_t vcooutput = 0U;
NYX	0:85b3fd62ea1a	2456	switch (PeriphClk)
NYX	0:85b3fd62ea1a	2457	{
NYX	0:85b3fd62ea1a	2458	case RCC_PERIPHCLK_I2S:
NYX	0:85b3fd62ea1a	2459	{
NYX	0:85b3fd62ea1a	2460	/* Get the current I2S source */
NYX	0:85b3fd62ea1a	2461	srcclk = __HAL_RCC_GET_I2S_SOURCE();
NYX	0:85b3fd62ea1a	2462	switch (srcclk)
NYX	0:85b3fd62ea1a	2463	{
NYX	0:85b3fd62ea1a	2464	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
NYX	0:85b3fd62ea1a	2465	case RCC_I2SCLKSOURCE_EXT:
NYX	0:85b3fd62ea1a	2466	{
NYX	0:85b3fd62ea1a	2467	/* Set the I2S clock to the external clock value */
NYX	0:85b3fd62ea1a	2468	frequency = EXTERNAL_CLOCK_VALUE;
NYX	0:85b3fd62ea1a	2469	break;
NYX	0:85b3fd62ea1a	2470	}
NYX	0:85b3fd62ea1a	2471	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
NYX	0:85b3fd62ea1a	2472	case RCC_I2SCLKSOURCE_PLLI2S:
NYX	0:85b3fd62ea1a	2473	{
NYX	0:85b3fd62ea1a	2474	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	2475	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	2476	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	2477	{
NYX	0:85b3fd62ea1a	2478	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	2479	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	2480	}
NYX	0:85b3fd62ea1a	2481	else
NYX	0:85b3fd62ea1a	2482	{
NYX	0:85b3fd62ea1a	2483	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	2484	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	2485	}
NYX	0:85b3fd62ea1a	2486
NYX	0:85b3fd62ea1a	2487	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	2488	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
NYX	0:85b3fd62ea1a	2489	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
NYX	0:85b3fd62ea1a	2490	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
NYX	0:85b3fd62ea1a	2491	break;
NYX	0:85b3fd62ea1a	2492	}
NYX	0:85b3fd62ea1a	2493	/* Clock not enabled for I2S */
NYX	0:85b3fd62ea1a	2494	default:
NYX	0:85b3fd62ea1a	2495	{
NYX	0:85b3fd62ea1a	2496	frequency = 0U;
NYX	0:85b3fd62ea1a	2497	break;
NYX	0:85b3fd62ea1a	2498	}
NYX	0:85b3fd62ea1a	2499	}
NYX	0:85b3fd62ea1a	2500	break;
NYX	0:85b3fd62ea1a	2501	}
NYX	0:85b3fd62ea1a	2502	}
NYX	0:85b3fd62ea1a	2503	return frequency;
NYX	0:85b3fd62ea1a	2504	}
NYX	0:85b3fd62ea1a	2505	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
NYX	0:85b3fd62ea1a	2506
NYX	0:85b3fd62ea1a	2507	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
NYX	0:85b3fd62ea1a	2508	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
NYX	0:85b3fd62ea1a	2509	/**
NYX	0:85b3fd62ea1a	2510	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
NYX	0:85b3fd62ea1a	2511	* RCC_PeriphCLKInitTypeDef.
NYX	0:85b3fd62ea1a	2512	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	2513	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
NYX	0:85b3fd62ea1a	2514	*
NYX	0:85b3fd62ea1a	2515	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
NYX	0:85b3fd62ea1a	2516	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
NYX	0:85b3fd62ea1a	2517	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
NYX	0:85b3fd62ea1a	2518	*
NYX	0:85b3fd62ea1a	2519	* @retval HAL status
NYX	0:85b3fd62ea1a	2520	*/
NYX	0:85b3fd62ea1a	2521	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	2522	{
NYX	0:85b3fd62ea1a	2523	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	2524	uint32_t tmpreg1 = 0U;
NYX	0:85b3fd62ea1a	2525
NYX	0:85b3fd62ea1a	2526	/* Check the parameters */
NYX	0:85b3fd62ea1a	2527	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
NYX	0:85b3fd62ea1a	2528
NYX	0:85b3fd62ea1a	2529	/---------------------------- I2S configuration ---------------------------/
NYX	0:85b3fd62ea1a	2530	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
NYX	0:85b3fd62ea1a	2531	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
NYX	0:85b3fd62ea1a	2532	{
NYX	0:85b3fd62ea1a	2533	/* check for Parameters */
NYX	0:85b3fd62ea1a	2534	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
NYX	0:85b3fd62ea1a	2535	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
NYX	0:85b3fd62ea1a	2536	#if defined(STM32F411xE)
NYX	0:85b3fd62ea1a	2537	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
NYX	0:85b3fd62ea1a	2538	#endif /* STM32F411xE */
NYX	0:85b3fd62ea1a	2539	/* Disable the PLLI2S */
NYX	0:85b3fd62ea1a	2540	__HAL_RCC_PLLI2S_DISABLE();
NYX	0:85b3fd62ea1a	2541	/* Get tick */
NYX	0:85b3fd62ea1a	2542	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2543	/* Wait till PLLI2S is disabled */
NYX	0:85b3fd62ea1a	2544	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
NYX	0:85b3fd62ea1a	2545	{
NYX	0:85b3fd62ea1a	2546	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2547	{
NYX	0:85b3fd62ea1a	2548	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	2549	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2550	}
NYX	0:85b3fd62ea1a	2551	}
NYX	0:85b3fd62ea1a	2552
NYX	0:85b3fd62ea1a	2553	#if defined(STM32F411xE)
NYX	0:85b3fd62ea1a	2554	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	2555	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
NYX	0:85b3fd62ea1a	2556	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
NYX	0:85b3fd62ea1a	2557	__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	2558	#else
NYX	0:85b3fd62ea1a	2559	/* Configure the PLLI2S division factors */
NYX	0:85b3fd62ea1a	2560	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
NYX	0:85b3fd62ea1a	2561	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
NYX	0:85b3fd62ea1a	2562	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
NYX	0:85b3fd62ea1a	2563	#endif /* STM32F411xE */
NYX	0:85b3fd62ea1a	2564
NYX	0:85b3fd62ea1a	2565	/* Enable the PLLI2S */
NYX	0:85b3fd62ea1a	2566	__HAL_RCC_PLLI2S_ENABLE();
NYX	0:85b3fd62ea1a	2567	/* Get tick */
NYX	0:85b3fd62ea1a	2568	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2569	/* Wait till PLLI2S is ready */
NYX	0:85b3fd62ea1a	2570	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
NYX	0:85b3fd62ea1a	2571	{
NYX	0:85b3fd62ea1a	2572	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2573	{
NYX	0:85b3fd62ea1a	2574	/* return in case of Timeout detected */
NYX	0:85b3fd62ea1a	2575	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2576	}
NYX	0:85b3fd62ea1a	2577	}
NYX	0:85b3fd62ea1a	2578	}
NYX	0:85b3fd62ea1a	2579
NYX	0:85b3fd62ea1a	2580	/---------------------------- RTC configuration ---------------------------/
NYX	0:85b3fd62ea1a	2581	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
NYX	0:85b3fd62ea1a	2582	{
NYX	0:85b3fd62ea1a	2583	/* Check for RTC Parameters used to output RTCCLK */
NYX	0:85b3fd62ea1a	2584	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
NYX	0:85b3fd62ea1a	2585
NYX	0:85b3fd62ea1a	2586	/* Enable Power Clock*/
NYX	0:85b3fd62ea1a	2587	__HAL_RCC_PWR_CLK_ENABLE();
NYX	0:85b3fd62ea1a	2588
NYX	0:85b3fd62ea1a	2589	/* Enable write access to Backup domain */
NYX	0:85b3fd62ea1a	2590	PWR->CR \|= PWR_CR_DBP;
NYX	0:85b3fd62ea1a	2591
NYX	0:85b3fd62ea1a	2592	/* Get tick */
NYX	0:85b3fd62ea1a	2593	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2594
NYX	0:85b3fd62ea1a	2595	while((PWR->CR & PWR_CR_DBP) == RESET)
NYX	0:85b3fd62ea1a	2596	{
NYX	0:85b3fd62ea1a	2597	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2598	{
NYX	0:85b3fd62ea1a	2599	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2600	}
NYX	0:85b3fd62ea1a	2601	}
NYX	0:85b3fd62ea1a	2602	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
NYX	0:85b3fd62ea1a	2603	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
NYX	0:85b3fd62ea1a	2604	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
NYX	0:85b3fd62ea1a	2605	{
NYX	0:85b3fd62ea1a	2606	/* Store the content of BDCR register before the reset of Backup Domain */
NYX	0:85b3fd62ea1a	2607	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	2608	/* RTC Clock selection can be changed only if the Backup Domain is reset */
NYX	0:85b3fd62ea1a	2609	__HAL_RCC_BACKUPRESET_FORCE();
NYX	0:85b3fd62ea1a	2610	__HAL_RCC_BACKUPRESET_RELEASE();
NYX	0:85b3fd62ea1a	2611	/* Restore the Content of BDCR register */
NYX	0:85b3fd62ea1a	2612	RCC->BDCR = tmpreg1;
NYX	0:85b3fd62ea1a	2613
NYX	0:85b3fd62ea1a	2614	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
NYX	0:85b3fd62ea1a	2615	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
NYX	0:85b3fd62ea1a	2616	{
NYX	0:85b3fd62ea1a	2617	/* Get tick */
NYX	0:85b3fd62ea1a	2618	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2619
NYX	0:85b3fd62ea1a	2620	/* Wait till LSE is ready */
NYX	0:85b3fd62ea1a	2621	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
NYX	0:85b3fd62ea1a	2622	{
NYX	0:85b3fd62ea1a	2623	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	2624	{
NYX	0:85b3fd62ea1a	2625	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2626	}
NYX	0:85b3fd62ea1a	2627	}
NYX	0:85b3fd62ea1a	2628	}
NYX	0:85b3fd62ea1a	2629	}
NYX	0:85b3fd62ea1a	2630	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
NYX	0:85b3fd62ea1a	2631	}
NYX	0:85b3fd62ea1a	2632	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
NYX	0:85b3fd62ea1a	2633	/---------------------------- TIM configuration ---------------------------/
NYX	0:85b3fd62ea1a	2634	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
NYX	0:85b3fd62ea1a	2635	{
NYX	0:85b3fd62ea1a	2636	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
NYX	0:85b3fd62ea1a	2637	}
NYX	0:85b3fd62ea1a	2638	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
NYX	0:85b3fd62ea1a	2639	return HAL_OK;
NYX	0:85b3fd62ea1a	2640	}
NYX	0:85b3fd62ea1a	2641
NYX	0:85b3fd62ea1a	2642	/**
NYX	0:85b3fd62ea1a	2643	* @brief Configures the RCC_OscInitStruct according to the internal
NYX	0:85b3fd62ea1a	2644	* RCC configuration registers.
NYX	0:85b3fd62ea1a	2645	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
NYX	0:85b3fd62ea1a	2646	* will be configured.
NYX	0:85b3fd62ea1a	2647	* @retval None
NYX	0:85b3fd62ea1a	2648	*/
NYX	0:85b3fd62ea1a	2649	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
NYX	0:85b3fd62ea1a	2650	{
NYX	0:85b3fd62ea1a	2651	uint32_t tempreg;
NYX	0:85b3fd62ea1a	2652
NYX	0:85b3fd62ea1a	2653	/* Set all possible values for the extended clock type parameter------------*/
NYX	0:85b3fd62ea1a	2654	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_RTC;
NYX	0:85b3fd62ea1a	2655
NYX	0:85b3fd62ea1a	2656	/* Get the PLLI2S Clock configuration --------------------------------------*/
NYX	0:85b3fd62ea1a	2657	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
NYX	0:85b3fd62ea1a	2658	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	2659	#if defined(STM32F411xE)
NYX	0:85b3fd62ea1a	2660	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
NYX	0:85b3fd62ea1a	2661	#endif /* STM32F411xE */
NYX	0:85b3fd62ea1a	2662	/* Get the RTC Clock configuration -----------------------------------------*/
NYX	0:85b3fd62ea1a	2663	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
NYX	0:85b3fd62ea1a	2664	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	2665
NYX	0:85b3fd62ea1a	2666	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
NYX	0:85b3fd62ea1a	2667	/* Get the TIM Prescaler configuration -------------------------------------*/
NYX	0:85b3fd62ea1a	2668	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
NYX	0:85b3fd62ea1a	2669	{
NYX	0:85b3fd62ea1a	2670	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
NYX	0:85b3fd62ea1a	2671	}
NYX	0:85b3fd62ea1a	2672	else
NYX	0:85b3fd62ea1a	2673	{
NYX	0:85b3fd62ea1a	2674	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
NYX	0:85b3fd62ea1a	2675	}
NYX	0:85b3fd62ea1a	2676	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
NYX	0:85b3fd62ea1a	2677	}
NYX	0:85b3fd62ea1a	2678
NYX	0:85b3fd62ea1a	2679	/**
NYX	0:85b3fd62ea1a	2680	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
NYX	0:85b3fd62ea1a	2681	* @note Return 0 if peripheral clock identifier not managed by this API
NYX	0:85b3fd62ea1a	2682	* @param PeriphClk: Peripheral clock identifier
NYX	0:85b3fd62ea1a	2683	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2684	* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
NYX	0:85b3fd62ea1a	2685	* @retval Frequency in KHz
NYX	0:85b3fd62ea1a	2686	*/
NYX	0:85b3fd62ea1a	2687	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
NYX	0:85b3fd62ea1a	2688	{
NYX	0:85b3fd62ea1a	2689	/* This variable used to store the I2S clock frequency (value in Hz) */
NYX	0:85b3fd62ea1a	2690	uint32_t frequency = 0U;
NYX	0:85b3fd62ea1a	2691	/* This variable used to store the VCO Input (value in Hz) */
NYX	0:85b3fd62ea1a	2692	uint32_t vcoinput = 0U;
NYX	0:85b3fd62ea1a	2693	uint32_t srcclk = 0U;
NYX	0:85b3fd62ea1a	2694	/* This variable used to store the VCO Output (value in Hz) */
NYX	0:85b3fd62ea1a	2695	uint32_t vcooutput = 0U;
NYX	0:85b3fd62ea1a	2696	switch (PeriphClk)
NYX	0:85b3fd62ea1a	2697	{
NYX	0:85b3fd62ea1a	2698	case RCC_PERIPHCLK_I2S:
NYX	0:85b3fd62ea1a	2699	{
NYX	0:85b3fd62ea1a	2700	/* Get the current I2S source */
NYX	0:85b3fd62ea1a	2701	srcclk = __HAL_RCC_GET_I2S_SOURCE();
NYX	0:85b3fd62ea1a	2702	switch (srcclk)
NYX	0:85b3fd62ea1a	2703	{
NYX	0:85b3fd62ea1a	2704	/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
NYX	0:85b3fd62ea1a	2705	case RCC_I2SCLKSOURCE_EXT:
NYX	0:85b3fd62ea1a	2706	{
NYX	0:85b3fd62ea1a	2707	/* Set the I2S clock to the external clock value */
NYX	0:85b3fd62ea1a	2708	frequency = EXTERNAL_CLOCK_VALUE;
NYX	0:85b3fd62ea1a	2709	break;
NYX	0:85b3fd62ea1a	2710	}
NYX	0:85b3fd62ea1a	2711	/* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
NYX	0:85b3fd62ea1a	2712	case RCC_I2SCLKSOURCE_PLLI2S:
NYX	0:85b3fd62ea1a	2713	{
NYX	0:85b3fd62ea1a	2714	#if defined(STM32F411xE)
NYX	0:85b3fd62ea1a	2715	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	2716	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
NYX	0:85b3fd62ea1a	2717	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	2718	{
NYX	0:85b3fd62ea1a	2719	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	2720	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	2721	}
NYX	0:85b3fd62ea1a	2722	else
NYX	0:85b3fd62ea1a	2723	{
NYX	0:85b3fd62ea1a	2724	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	2725	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	2726	}
NYX	0:85b3fd62ea1a	2727	#else
NYX	0:85b3fd62ea1a	2728	/* Configure the PLLI2S division factor */
NYX	0:85b3fd62ea1a	2729	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
NYX	0:85b3fd62ea1a	2730	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
NYX	0:85b3fd62ea1a	2731	{
NYX	0:85b3fd62ea1a	2732	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	2733	vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	2734	}
NYX	0:85b3fd62ea1a	2735	else
NYX	0:85b3fd62ea1a	2736	{
NYX	0:85b3fd62ea1a	2737	/* Get the I2S source clock value */
NYX	0:85b3fd62ea1a	2738	vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	2739	}
NYX	0:85b3fd62ea1a	2740	#endif /* STM32F411xE */
NYX	0:85b3fd62ea1a	2741	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
NYX	0:85b3fd62ea1a	2742	vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
NYX	0:85b3fd62ea1a	2743	/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
NYX	0:85b3fd62ea1a	2744	frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
NYX	0:85b3fd62ea1a	2745	break;
NYX	0:85b3fd62ea1a	2746	}
NYX	0:85b3fd62ea1a	2747	/* Clock not enabled for I2S*/
NYX	0:85b3fd62ea1a	2748	default:
NYX	0:85b3fd62ea1a	2749	{
NYX	0:85b3fd62ea1a	2750	frequency = 0U;
NYX	0:85b3fd62ea1a	2751	break;
NYX	0:85b3fd62ea1a	2752	}
NYX	0:85b3fd62ea1a	2753	}
NYX	0:85b3fd62ea1a	2754	break;
NYX	0:85b3fd62ea1a	2755	}
NYX	0:85b3fd62ea1a	2756	}
NYX	0:85b3fd62ea1a	2757	return frequency;
NYX	0:85b3fd62ea1a	2758	}
NYX	0:85b3fd62ea1a	2759	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
NYX	0:85b3fd62ea1a	2760
NYX	0:85b3fd62ea1a	2761	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	2762	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	2763	/**
NYX	0:85b3fd62ea1a	2764	* @brief Select LSE mode
NYX	0:85b3fd62ea1a	2765	*
NYX	0:85b3fd62ea1a	2766	* @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
NYX	0:85b3fd62ea1a	2767	*
NYX	0:85b3fd62ea1a	2768	* @param Mode: specifies the LSE mode.
NYX	0:85b3fd62ea1a	2769	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2770	* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
NYX	0:85b3fd62ea1a	2771	* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
NYX	0:85b3fd62ea1a	2772	* @retval None
NYX	0:85b3fd62ea1a	2773	*/
NYX	0:85b3fd62ea1a	2774	void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
NYX	0:85b3fd62ea1a	2775	{
NYX	0:85b3fd62ea1a	2776	/* Check the parameters */
NYX	0:85b3fd62ea1a	2777	assert_param(IS_RCC_LSE_MODE(Mode));
NYX	0:85b3fd62ea1a	2778	if(Mode == RCC_LSE_HIGHDRIVE_MODE)
NYX	0:85b3fd62ea1a	2779	{
NYX	0:85b3fd62ea1a	2780	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
NYX	0:85b3fd62ea1a	2781	}
NYX	0:85b3fd62ea1a	2782	else
NYX	0:85b3fd62ea1a	2783	{
NYX	0:85b3fd62ea1a	2784	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
NYX	0:85b3fd62ea1a	2785	}
NYX	0:85b3fd62ea1a	2786	}
NYX	0:85b3fd62ea1a	2787
NYX	0:85b3fd62ea1a	2788	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	2789
NYX	0:85b3fd62ea1a	2790	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	2791	/**
NYX	0:85b3fd62ea1a	2792	* @brief Returns the SYSCLK frequency
NYX	0:85b3fd62ea1a	2793	*
NYX	0:85b3fd62ea1a	2794	* @note This function implementation is valid only for STM32F446xx devices.
NYX	0:85b3fd62ea1a	2795	* @note This function add the PLL/PLLR System clock source
NYX	0:85b3fd62ea1a	2796	*
NYX	0:85b3fd62ea1a	2797	* @note The system frequency computed by this function is not the real
NYX	0:85b3fd62ea1a	2798	* frequency in the chip. It is calculated based on the predefined
NYX	0:85b3fd62ea1a	2799	* constant and the selected clock source:
NYX	0:85b3fd62ea1a	2800	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
NYX	0:85b3fd62ea1a	2801	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
NYX	0:85b3fd62ea1a	2802	* @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
NYX	0:85b3fd62ea1a	2803	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
NYX	0:85b3fd62ea1a	2804	* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
NYX	0:85b3fd62ea1a	2805	* 16 MHz) but the real value may vary depending on the variations
NYX	0:85b3fd62ea1a	2806	* in voltage and temperature.
NYX	0:85b3fd62ea1a	2807	* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
NYX	0:85b3fd62ea1a	2808	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
NYX	0:85b3fd62ea1a	2809	* frequency of the crystal used. Otherwise, this function may
NYX	0:85b3fd62ea1a	2810	* have wrong result.
NYX	0:85b3fd62ea1a	2811	*
NYX	0:85b3fd62ea1a	2812	* @note The result of this function could be not correct when using fractional
NYX	0:85b3fd62ea1a	2813	* value for HSE crystal.
NYX	0:85b3fd62ea1a	2814	*
NYX	0:85b3fd62ea1a	2815	* @note This function can be used by the user application to compute the
NYX	0:85b3fd62ea1a	2816	* baudrate for the communication peripherals or configure other parameters.
NYX	0:85b3fd62ea1a	2817	*
NYX	0:85b3fd62ea1a	2818	* @note Each time SYSCLK changes, this function must be called to update the
NYX	0:85b3fd62ea1a	2819	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
NYX	0:85b3fd62ea1a	2820	*
NYX	0:85b3fd62ea1a	2821	*
NYX	0:85b3fd62ea1a	2822	* @retval SYSCLK frequency
NYX	0:85b3fd62ea1a	2823	*/
NYX	0:85b3fd62ea1a	2824	uint32_t HAL_RCC_GetSysClockFreq(void)
NYX	0:85b3fd62ea1a	2825	{
NYX	0:85b3fd62ea1a	2826	uint32_t pllm = 0U;
NYX	0:85b3fd62ea1a	2827	uint32_t pllvco = 0U;
NYX	0:85b3fd62ea1a	2828	uint32_t pllp = 0U;
NYX	0:85b3fd62ea1a	2829	uint32_t pllr = 0U;
NYX	0:85b3fd62ea1a	2830	uint32_t sysclockfreq = 0U;
NYX	0:85b3fd62ea1a	2831
NYX	0:85b3fd62ea1a	2832	/* Get SYSCLK source -------------------------------------------------------*/
NYX	0:85b3fd62ea1a	2833	switch (RCC->CFGR & RCC_CFGR_SWS)
NYX	0:85b3fd62ea1a	2834	{
NYX	0:85b3fd62ea1a	2835	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
NYX	0:85b3fd62ea1a	2836	{
NYX	0:85b3fd62ea1a	2837	sysclockfreq = HSI_VALUE;
NYX	0:85b3fd62ea1a	2838	break;
NYX	0:85b3fd62ea1a	2839	}
NYX	0:85b3fd62ea1a	2840	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
NYX	0:85b3fd62ea1a	2841	{
NYX	0:85b3fd62ea1a	2842	sysclockfreq = HSE_VALUE;
NYX	0:85b3fd62ea1a	2843	break;
NYX	0:85b3fd62ea1a	2844	}
NYX	0:85b3fd62ea1a	2845	case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
NYX	0:85b3fd62ea1a	2846	{
NYX	0:85b3fd62ea1a	2847	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
NYX	0:85b3fd62ea1a	2848	SYSCLK = PLL_VCO / PLLP */
NYX	0:85b3fd62ea1a	2849	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
NYX	0:85b3fd62ea1a	2850	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
NYX	0:85b3fd62ea1a	2851	{
NYX	0:85b3fd62ea1a	2852	/* HSE used as PLL clock source */
NYX	0:85b3fd62ea1a	2853	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
NYX	0:85b3fd62ea1a	2854	}
NYX	0:85b3fd62ea1a	2855	else
NYX	0:85b3fd62ea1a	2856	{
NYX	0:85b3fd62ea1a	2857	/* HSI used as PLL clock source */
NYX	0:85b3fd62ea1a	2858	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
NYX	0:85b3fd62ea1a	2859	}
NYX	0:85b3fd62ea1a	2860	pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
NYX	0:85b3fd62ea1a	2861
NYX	0:85b3fd62ea1a	2862	sysclockfreq = pllvco/pllp;
NYX	0:85b3fd62ea1a	2863	break;
NYX	0:85b3fd62ea1a	2864	}
NYX	0:85b3fd62ea1a	2865	case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
NYX	0:85b3fd62ea1a	2866	{
NYX	0:85b3fd62ea1a	2867	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
NYX	0:85b3fd62ea1a	2868	SYSCLK = PLL_VCO / PLLR */
NYX	0:85b3fd62ea1a	2869	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
NYX	0:85b3fd62ea1a	2870	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
NYX	0:85b3fd62ea1a	2871	{
NYX	0:85b3fd62ea1a	2872	/* HSE used as PLL clock source */
NYX	0:85b3fd62ea1a	2873	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
NYX	0:85b3fd62ea1a	2874	}
NYX	0:85b3fd62ea1a	2875	else
NYX	0:85b3fd62ea1a	2876	{
NYX	0:85b3fd62ea1a	2877	/* HSI used as PLL clock source */
NYX	0:85b3fd62ea1a	2878	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
NYX	0:85b3fd62ea1a	2879	}
NYX	0:85b3fd62ea1a	2880	pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
NYX	0:85b3fd62ea1a	2881
NYX	0:85b3fd62ea1a	2882	sysclockfreq = pllvco/pllr;
NYX	0:85b3fd62ea1a	2883	break;
NYX	0:85b3fd62ea1a	2884	}
NYX	0:85b3fd62ea1a	2885	default:
NYX	0:85b3fd62ea1a	2886	{
NYX	0:85b3fd62ea1a	2887	sysclockfreq = HSI_VALUE;
NYX	0:85b3fd62ea1a	2888	break;
NYX	0:85b3fd62ea1a	2889	}
NYX	0:85b3fd62ea1a	2890	}
NYX	0:85b3fd62ea1a	2891	return sysclockfreq;
NYX	0:85b3fd62ea1a	2892	}
NYX	0:85b3fd62ea1a	2893	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	2894
NYX	0:85b3fd62ea1a	2895	/**
NYX	0:85b3fd62ea1a	2896	* @}
NYX	0:85b3fd62ea1a	2897	*/
NYX	0:85b3fd62ea1a	2898
NYX	0:85b3fd62ea1a	2899	/**
NYX	0:85b3fd62ea1a	2900	* @}
NYX	0:85b3fd62ea1a	2901	*/
NYX	0:85b3fd62ea1a	2902
NYX	0:85b3fd62ea1a	2903	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
NYX	0:85b3fd62ea1a	2904	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
NYX	0:85b3fd62ea1a	2905	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
NYX	0:85b3fd62ea1a	2906	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
NYX	0:85b3fd62ea1a	2907	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	2908	/**
NYX	0:85b3fd62ea1a	2909	* @brief Resets the RCC clock configuration to the default reset state.
NYX	0:85b3fd62ea1a	2910	* @note The default reset state of the clock configuration is given below:
NYX	0:85b3fd62ea1a	2911	* - HSI ON and used as system clock source
NYX	0:85b3fd62ea1a	2912	* - HSE, PLL, PLLI2S and PLLSAI OFF
NYX	0:85b3fd62ea1a	2913	* - AHB, APB1 and APB2 prescaler set to 1.
NYX	0:85b3fd62ea1a	2914	* - CSS, MCO1 and MCO2 OFF
NYX	0:85b3fd62ea1a	2915	* - All interrupts disabled
NYX	0:85b3fd62ea1a	2916	* @note This function doesn't modify the configuration of the
NYX	0:85b3fd62ea1a	2917	* - Peripheral clocks
NYX	0:85b3fd62ea1a	2918	* - LSI, LSE and RTC clocks
NYX	0:85b3fd62ea1a	2919	* @retval None
NYX	0:85b3fd62ea1a	2920	*/
NYX	0:85b3fd62ea1a	2921	void HAL_RCC_DeInit(void)
NYX	0:85b3fd62ea1a	2922	{
NYX	0:85b3fd62ea1a	2923	/* Set HSION bit */
NYX	0:85b3fd62ea1a	2924	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
NYX	0:85b3fd62ea1a	2925
NYX	0:85b3fd62ea1a	2926	/* Reset CFGR register */
NYX	0:85b3fd62ea1a	2927	CLEAR_REG(RCC->CFGR);
NYX	0:85b3fd62ea1a	2928
NYX	0:85b3fd62ea1a	2929	/* Reset HSEON, CSSON, PLLON, PLLI2S bits */
NYX	0:85b3fd62ea1a	2930	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_HSEBYP \| RCC_CR_CSSON \| RCC_CR_PLLON \| RCC_CR_PLLI2SON);
NYX	0:85b3fd62ea1a	2931
NYX	0:85b3fd62ea1a	2932	#if defined(STM32F427xx) \|\| defined(STM32F429xx) \|\| defined(STM32F437xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	2933	/* Reset PLLSAI bit */
NYX	0:85b3fd62ea1a	2934	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
NYX	0:85b3fd62ea1a	2935	#endif /* STM32F427xx \|\| STM32F429xx \|\| STM32F437xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	2936
NYX	0:85b3fd62ea1a	2937	/* Reset PLLCFGR register */
NYX	0:85b3fd62ea1a	2938	CLEAR_REG(RCC->PLLCFGR);
NYX	0:85b3fd62ea1a	2939	#if defined(STM32F412Cx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Zx) \|\| defined(STM32F413xx) \|\| \
NYX	0:85b3fd62ea1a	2940	defined(STM32F423xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	2941	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2 \| RCC_PLLCFGR_PLLR_1);
NYX	0:85b3fd62ea1a	2942	#else
NYX	0:85b3fd62ea1a	2943	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2);
NYX	0:85b3fd62ea1a	2944	#endif /* STM32F412Cx \|\| STM32F412Rx \|\| STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	2945
NYX	0:85b3fd62ea1a	2946	/* Reset PLLI2SCFGR register */
NYX	0:85b3fd62ea1a	2947	CLEAR_REG(RCC->PLLI2SCFGR);
NYX	0:85b3fd62ea1a	2948	#if defined(STM32F412Cx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Zx) \|\| defined(STM32F413xx) \|\| \
NYX	0:85b3fd62ea1a	2949	defined(STM32F423xx) \|\| defined(STM32F446xx)
NYX	0:85b3fd62ea1a	2950	SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SR_1);
NYX	0:85b3fd62ea1a	2951	#elif defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	2952	SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SR_1);
NYX	0:85b3fd62ea1a	2953	#elif defined(STM32F411xE)
NYX	0:85b3fd62ea1a	2954	SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SR_1);
NYX	0:85b3fd62ea1a	2955	#else
NYX	0:85b3fd62ea1a	2956	SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SR_1);
NYX	0:85b3fd62ea1a	2957	#endif /* STM32F412Cx \|\| STM32F412Rx \|\| STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx \|\| STM32F446xx */
NYX	0:85b3fd62ea1a	2958
NYX	0:85b3fd62ea1a	2959	/* Reset PLLSAICFGR register */
NYX	0:85b3fd62ea1a	2960	#if defined(STM32F427xx) \|\| defined(STM32F429xx) \|\| defined(STM32F437xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	2961	CLEAR_REG(RCC->PLLSAICFGR);
NYX	0:85b3fd62ea1a	2962	SET_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN_6 \| RCC_PLLSAICFGR_PLLSAIN_7 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIR_1);
NYX	0:85b3fd62ea1a	2963	#elif defined(STM32F446xx)
NYX	0:85b3fd62ea1a	2964	CLEAR_REG(RCC->PLLSAICFGR);
NYX	0:85b3fd62ea1a	2965	SET_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIN_6 \| RCC_PLLSAICFGR_PLLSAIN_7 \| RCC_PLLSAICFGR_PLLSAIQ_2);
NYX	0:85b3fd62ea1a	2966	#endif /* STM32F427xx \|\| STM32F429xx \|\| STM32F437xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	2967
NYX	0:85b3fd62ea1a	2968	/* Disable all interrupts */
NYX	0:85b3fd62ea1a	2969	CLEAR_REG(RCC->CIR);
NYX	0:85b3fd62ea1a	2970
NYX	0:85b3fd62ea1a	2971	/* Update the SystemCoreClock global variable */
NYX	0:85b3fd62ea1a	2972	SystemCoreClock = HSI_VALUE;
NYX	0:85b3fd62ea1a	2973	}
NYX	0:85b3fd62ea1a	2974	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
NYX	0:85b3fd62ea1a	2975	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
NYX	0:85b3fd62ea1a	2976	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	2977
NYX	0:85b3fd62ea1a	2978	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	2979	/**
NYX	0:85b3fd62ea1a	2980	* @brief Resets the RCC clock configuration to the default reset state.
NYX	0:85b3fd62ea1a	2981	* @note The default reset state of the clock configuration is given below:
NYX	0:85b3fd62ea1a	2982	* - HSI ON and used as system clock source
NYX	0:85b3fd62ea1a	2983	* - HSE and PLL OFF
NYX	0:85b3fd62ea1a	2984	* - AHB, APB1 and APB2 prescaler set to 1.
NYX	0:85b3fd62ea1a	2985	* - CSS, MCO1 and MCO2 OFF
NYX	0:85b3fd62ea1a	2986	* - All interrupts disabled
NYX	0:85b3fd62ea1a	2987	* @note This function doesn't modify the configuration of the
NYX	0:85b3fd62ea1a	2988	* - Peripheral clocks
NYX	0:85b3fd62ea1a	2989	* - LSI, LSE and RTC clocks
NYX	0:85b3fd62ea1a	2990	* @retval None
NYX	0:85b3fd62ea1a	2991	*/
NYX	0:85b3fd62ea1a	2992	void HAL_RCC_DeInit(void)
NYX	0:85b3fd62ea1a	2993	{
NYX	0:85b3fd62ea1a	2994	/* Set HSION bit */
NYX	0:85b3fd62ea1a	2995	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
NYX	0:85b3fd62ea1a	2996
NYX	0:85b3fd62ea1a	2997	/* Reset CFGR register */
NYX	0:85b3fd62ea1a	2998	CLEAR_REG(RCC->CFGR);
NYX	0:85b3fd62ea1a	2999
NYX	0:85b3fd62ea1a	3000	/* Reset HSEON, HSEBYP, CSSON, PLLON */
NYX	0:85b3fd62ea1a	3001	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_HSEBYP \| RCC_CR_CSSON \| RCC_CR_PLLON);
NYX	0:85b3fd62ea1a	3002
NYX	0:85b3fd62ea1a	3003	/* Reset PLLCFGR register */
NYX	0:85b3fd62ea1a	3004	CLEAR_REG(RCC->PLLCFGR);
NYX	0:85b3fd62ea1a	3005	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_0 \| RCC_PLLCFGR_PLLR_1 \| RCC_PLLCFGR_PLLR_2 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_0 \| RCC_PLLCFGR_PLLQ_1 \| RCC_PLLCFGR_PLLQ_2 \| RCC_PLLCFGR_PLLQ_3);
NYX	0:85b3fd62ea1a	3006
NYX	0:85b3fd62ea1a	3007	/* Disable all interrupts */
NYX	0:85b3fd62ea1a	3008	CLEAR_REG(RCC->CIR);
NYX	0:85b3fd62ea1a	3009
NYX	0:85b3fd62ea1a	3010	/* Update the SystemCoreClock global variable */
NYX	0:85b3fd62ea1a	3011	SystemCoreClock = HSI_VALUE;
NYX	0:85b3fd62ea1a	3012	}
NYX	0:85b3fd62ea1a	3013	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	3014
NYX	0:85b3fd62ea1a	3015	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	3016	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	3017	/**
NYX	0:85b3fd62ea1a	3018	* @brief Initializes the RCC Oscillators according to the specified parameters in the
NYX	0:85b3fd62ea1a	3019	* RCC_OscInitTypeDef.
NYX	0:85b3fd62ea1a	3020	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
NYX	0:85b3fd62ea1a	3021	* contains the configuration information for the RCC Oscillators.
NYX	0:85b3fd62ea1a	3022	* @note The PLL is not disabled when used as system clock.
NYX	0:85b3fd62ea1a	3023	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
NYX	0:85b3fd62ea1a	3024	* supported by this API. User should request a transition to LSE Off
NYX	0:85b3fd62ea1a	3025	* first and then LSE On or LSE Bypass.
NYX	0:85b3fd62ea1a	3026	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
NYX	0:85b3fd62ea1a	3027	* supported by this API. User should request a transition to HSE Off
NYX	0:85b3fd62ea1a	3028	* first and then HSE On or HSE Bypass.
NYX	0:85b3fd62ea1a	3029	* @note This function add the PLL/PLLR factor management during PLL configuration this feature
NYX	0:85b3fd62ea1a	3030	* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
NYX	0:85b3fd62ea1a	3031	* @retval HAL status
NYX	0:85b3fd62ea1a	3032	*/
NYX	0:85b3fd62ea1a	3033	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
NYX	0:85b3fd62ea1a	3034	{
NYX	0:85b3fd62ea1a	3035	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	3036
NYX	0:85b3fd62ea1a	3037	/* Check the parameters */
NYX	0:85b3fd62ea1a	3038	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
NYX	0:85b3fd62ea1a	3039	/------------------------------- HSE Configuration ------------------------/
NYX	0:85b3fd62ea1a	3040	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
NYX	0:85b3fd62ea1a	3041	{
NYX	0:85b3fd62ea1a	3042	/* Check the parameters */
NYX	0:85b3fd62ea1a	3043	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
NYX	0:85b3fd62ea1a	3044	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
NYX	0:85b3fd62ea1a	3045	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	3046	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
NYX	0:85b3fd62ea1a	3047	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) \|\|\
NYX	0:85b3fd62ea1a	3048	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
NYX	0:85b3fd62ea1a	3049	#else
NYX	0:85b3fd62ea1a	3050	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
NYX	0:85b3fd62ea1a	3051	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
NYX	0:85b3fd62ea1a	3052	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	3053	{
NYX	0:85b3fd62ea1a	3054	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
NYX	0:85b3fd62ea1a	3055	{
NYX	0:85b3fd62ea1a	3056	return HAL_ERROR;
NYX	0:85b3fd62ea1a	3057	}
NYX	0:85b3fd62ea1a	3058	}
NYX	0:85b3fd62ea1a	3059	else
NYX	0:85b3fd62ea1a	3060	{
NYX	0:85b3fd62ea1a	3061	/* Set the new HSE configuration ---------------------------------------*/
NYX	0:85b3fd62ea1a	3062	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
NYX	0:85b3fd62ea1a	3063
NYX	0:85b3fd62ea1a	3064	/* Check the HSE State */
NYX	0:85b3fd62ea1a	3065	if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
NYX	0:85b3fd62ea1a	3066	{
NYX	0:85b3fd62ea1a	3067	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3068	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3069
NYX	0:85b3fd62ea1a	3070	/* Wait till HSE is ready */
NYX	0:85b3fd62ea1a	3071	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
NYX	0:85b3fd62ea1a	3072	{
NYX	0:85b3fd62ea1a	3073	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3074	{
NYX	0:85b3fd62ea1a	3075	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3076	}
NYX	0:85b3fd62ea1a	3077	}
NYX	0:85b3fd62ea1a	3078	}
NYX	0:85b3fd62ea1a	3079	else
NYX	0:85b3fd62ea1a	3080	{
NYX	0:85b3fd62ea1a	3081	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3082	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3083
NYX	0:85b3fd62ea1a	3084	/* Wait till HSE is bypassed or disabled */
NYX	0:85b3fd62ea1a	3085	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
NYX	0:85b3fd62ea1a	3086	{
NYX	0:85b3fd62ea1a	3087	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3088	{
NYX	0:85b3fd62ea1a	3089	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3090	}
NYX	0:85b3fd62ea1a	3091	}
NYX	0:85b3fd62ea1a	3092	}
NYX	0:85b3fd62ea1a	3093	}
NYX	0:85b3fd62ea1a	3094	}
NYX	0:85b3fd62ea1a	3095	/----------------------------- HSI Configuration --------------------------/
NYX	0:85b3fd62ea1a	3096	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
NYX	0:85b3fd62ea1a	3097	{
NYX	0:85b3fd62ea1a	3098	/* Check the parameters */
NYX	0:85b3fd62ea1a	3099	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
NYX	0:85b3fd62ea1a	3100	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
NYX	0:85b3fd62ea1a	3101
NYX	0:85b3fd62ea1a	3102	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
NYX	0:85b3fd62ea1a	3103	#if defined(STM32F446xx)
NYX	0:85b3fd62ea1a	3104	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
NYX	0:85b3fd62ea1a	3105	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) \|\|\
NYX	0:85b3fd62ea1a	3106	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
NYX	0:85b3fd62ea1a	3107	#else
NYX	0:85b3fd62ea1a	3108	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
NYX	0:85b3fd62ea1a	3109	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
NYX	0:85b3fd62ea1a	3110	#endif /* STM32F446xx */
NYX	0:85b3fd62ea1a	3111	{
NYX	0:85b3fd62ea1a	3112	/* When HSI is used as system clock it will not disabled */
NYX	0:85b3fd62ea1a	3113	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
NYX	0:85b3fd62ea1a	3114	{
NYX	0:85b3fd62ea1a	3115	return HAL_ERROR;
NYX	0:85b3fd62ea1a	3116	}
NYX	0:85b3fd62ea1a	3117	/* Otherwise, just the calibration is allowed */
NYX	0:85b3fd62ea1a	3118	else
NYX	0:85b3fd62ea1a	3119	{
NYX	0:85b3fd62ea1a	3120	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
NYX	0:85b3fd62ea1a	3121	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
NYX	0:85b3fd62ea1a	3122	}
NYX	0:85b3fd62ea1a	3123	}
NYX	0:85b3fd62ea1a	3124	else
NYX	0:85b3fd62ea1a	3125	{
NYX	0:85b3fd62ea1a	3126	/* Check the HSI State */
NYX	0:85b3fd62ea1a	3127	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
NYX	0:85b3fd62ea1a	3128	{
NYX	0:85b3fd62ea1a	3129	/* Enable the Internal High Speed oscillator (HSI). */
NYX	0:85b3fd62ea1a	3130	__HAL_RCC_HSI_ENABLE();
NYX	0:85b3fd62ea1a	3131
NYX	0:85b3fd62ea1a	3132	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3133	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3134
NYX	0:85b3fd62ea1a	3135	/* Wait till HSI is ready */
NYX	0:85b3fd62ea1a	3136	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
NYX	0:85b3fd62ea1a	3137	{
NYX	0:85b3fd62ea1a	3138	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3139	{
NYX	0:85b3fd62ea1a	3140	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3141	}
NYX	0:85b3fd62ea1a	3142	}
NYX	0:85b3fd62ea1a	3143
NYX	0:85b3fd62ea1a	3144	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
NYX	0:85b3fd62ea1a	3145	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
NYX	0:85b3fd62ea1a	3146	}
NYX	0:85b3fd62ea1a	3147	else
NYX	0:85b3fd62ea1a	3148	{
NYX	0:85b3fd62ea1a	3149	/* Disable the Internal High Speed oscillator (HSI). */
NYX	0:85b3fd62ea1a	3150	__HAL_RCC_HSI_DISABLE();
NYX	0:85b3fd62ea1a	3151
NYX	0:85b3fd62ea1a	3152	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3153	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3154
NYX	0:85b3fd62ea1a	3155	/* Wait till HSI is ready */
NYX	0:85b3fd62ea1a	3156	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
NYX	0:85b3fd62ea1a	3157	{
NYX	0:85b3fd62ea1a	3158	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3159	{
NYX	0:85b3fd62ea1a	3160	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3161	}
NYX	0:85b3fd62ea1a	3162	}
NYX	0:85b3fd62ea1a	3163	}
NYX	0:85b3fd62ea1a	3164	}
NYX	0:85b3fd62ea1a	3165	}
NYX	0:85b3fd62ea1a	3166	/------------------------------ LSI Configuration -------------------------/
NYX	0:85b3fd62ea1a	3167	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
NYX	0:85b3fd62ea1a	3168	{
NYX	0:85b3fd62ea1a	3169	/* Check the parameters */
NYX	0:85b3fd62ea1a	3170	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
NYX	0:85b3fd62ea1a	3171
NYX	0:85b3fd62ea1a	3172	/* Check the LSI State */
NYX	0:85b3fd62ea1a	3173	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
NYX	0:85b3fd62ea1a	3174	{
NYX	0:85b3fd62ea1a	3175	/* Enable the Internal Low Speed oscillator (LSI). */
NYX	0:85b3fd62ea1a	3176	__HAL_RCC_LSI_ENABLE();
NYX	0:85b3fd62ea1a	3177
NYX	0:85b3fd62ea1a	3178	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3179	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3180
NYX	0:85b3fd62ea1a	3181	/* Wait till LSI is ready */
NYX	0:85b3fd62ea1a	3182	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
NYX	0:85b3fd62ea1a	3183	{
NYX	0:85b3fd62ea1a	3184	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3185	{
NYX	0:85b3fd62ea1a	3186	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3187	}
NYX	0:85b3fd62ea1a	3188	}
NYX	0:85b3fd62ea1a	3189	}
NYX	0:85b3fd62ea1a	3190	else
NYX	0:85b3fd62ea1a	3191	{
NYX	0:85b3fd62ea1a	3192	/* Disable the Internal Low Speed oscillator (LSI). */
NYX	0:85b3fd62ea1a	3193	__HAL_RCC_LSI_DISABLE();
NYX	0:85b3fd62ea1a	3194
NYX	0:85b3fd62ea1a	3195	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3196	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3197
NYX	0:85b3fd62ea1a	3198	/* Wait till LSI is ready */
NYX	0:85b3fd62ea1a	3199	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
NYX	0:85b3fd62ea1a	3200	{
NYX	0:85b3fd62ea1a	3201	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3202	{
NYX	0:85b3fd62ea1a	3203	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3204	}
NYX	0:85b3fd62ea1a	3205	}
NYX	0:85b3fd62ea1a	3206	}
NYX	0:85b3fd62ea1a	3207	}
NYX	0:85b3fd62ea1a	3208	/------------------------------ LSE Configuration -------------------------/
NYX	0:85b3fd62ea1a	3209	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
NYX	0:85b3fd62ea1a	3210	{
NYX	0:85b3fd62ea1a	3211	/* Check the parameters */
NYX	0:85b3fd62ea1a	3212	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
NYX	0:85b3fd62ea1a	3213
NYX	0:85b3fd62ea1a	3214	/* Enable Power Clock*/
NYX	0:85b3fd62ea1a	3215	__HAL_RCC_PWR_CLK_ENABLE();
NYX	0:85b3fd62ea1a	3216
NYX	0:85b3fd62ea1a	3217	/* Enable write access to Backup domain */
NYX	0:85b3fd62ea1a	3218	PWR->CR \|= PWR_CR_DBP;
NYX	0:85b3fd62ea1a	3219
NYX	0:85b3fd62ea1a	3220	/* Wait for Backup domain Write protection disable */
NYX	0:85b3fd62ea1a	3221	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3222
NYX	0:85b3fd62ea1a	3223	while((PWR->CR & PWR_CR_DBP) == RESET)
NYX	0:85b3fd62ea1a	3224	{
NYX	0:85b3fd62ea1a	3225	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3226	{
NYX	0:85b3fd62ea1a	3227	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3228	}
NYX	0:85b3fd62ea1a	3229	}
NYX	0:85b3fd62ea1a	3230
NYX	0:85b3fd62ea1a	3231	/* Set the new LSE configuration -----------------------------------------*/
NYX	0:85b3fd62ea1a	3232	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
NYX	0:85b3fd62ea1a	3233	/* Check the LSE State */
NYX	0:85b3fd62ea1a	3234	if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
NYX	0:85b3fd62ea1a	3235	{
NYX	0:85b3fd62ea1a	3236	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3237	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3238
NYX	0:85b3fd62ea1a	3239	/* Wait till LSE is ready */
NYX	0:85b3fd62ea1a	3240	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
NYX	0:85b3fd62ea1a	3241	{
NYX	0:85b3fd62ea1a	3242	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3243	{
NYX	0:85b3fd62ea1a	3244	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3245	}
NYX	0:85b3fd62ea1a	3246	}
NYX	0:85b3fd62ea1a	3247	}
NYX	0:85b3fd62ea1a	3248	else
NYX	0:85b3fd62ea1a	3249	{
NYX	0:85b3fd62ea1a	3250	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3251	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3252
NYX	0:85b3fd62ea1a	3253	/* Wait till LSE is ready */
NYX	0:85b3fd62ea1a	3254	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
NYX	0:85b3fd62ea1a	3255	{
NYX	0:85b3fd62ea1a	3256	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3257	{
NYX	0:85b3fd62ea1a	3258	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3259	}
NYX	0:85b3fd62ea1a	3260	}
NYX	0:85b3fd62ea1a	3261	}
NYX	0:85b3fd62ea1a	3262	}
NYX	0:85b3fd62ea1a	3263	/-------------------------------- PLL Configuration -----------------------/
NYX	0:85b3fd62ea1a	3264	/* Check the parameters */
NYX	0:85b3fd62ea1a	3265	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
NYX	0:85b3fd62ea1a	3266	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
NYX	0:85b3fd62ea1a	3267	{
NYX	0:85b3fd62ea1a	3268	/* Check if the PLL is used as system clock or not */
NYX	0:85b3fd62ea1a	3269	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
NYX	0:85b3fd62ea1a	3270	{
NYX	0:85b3fd62ea1a	3271	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
NYX	0:85b3fd62ea1a	3272	{
NYX	0:85b3fd62ea1a	3273	/* Check the parameters */
NYX	0:85b3fd62ea1a	3274	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
NYX	0:85b3fd62ea1a	3275	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
NYX	0:85b3fd62ea1a	3276	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
NYX	0:85b3fd62ea1a	3277	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
NYX	0:85b3fd62ea1a	3278	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
NYX	0:85b3fd62ea1a	3279	assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
NYX	0:85b3fd62ea1a	3280
NYX	0:85b3fd62ea1a	3281	/* Disable the main PLL. */
NYX	0:85b3fd62ea1a	3282	__HAL_RCC_PLL_DISABLE();
NYX	0:85b3fd62ea1a	3283
NYX	0:85b3fd62ea1a	3284	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3285	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3286
NYX	0:85b3fd62ea1a	3287	/* Wait till PLL is ready */
NYX	0:85b3fd62ea1a	3288	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
NYX	0:85b3fd62ea1a	3289	{
NYX	0:85b3fd62ea1a	3290	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3291	{
NYX	0:85b3fd62ea1a	3292	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3293	}
NYX	0:85b3fd62ea1a	3294	}
NYX	0:85b3fd62ea1a	3295
NYX	0:85b3fd62ea1a	3296	/* Configure the main PLL clock source, multiplication and division factors. */
NYX	0:85b3fd62ea1a	3297	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
NYX	0:85b3fd62ea1a	3298	RCC_OscInitStruct->PLL.PLLM,
NYX	0:85b3fd62ea1a	3299	RCC_OscInitStruct->PLL.PLLN,
NYX	0:85b3fd62ea1a	3300	RCC_OscInitStruct->PLL.PLLP,
NYX	0:85b3fd62ea1a	3301	RCC_OscInitStruct->PLL.PLLQ,
NYX	0:85b3fd62ea1a	3302	RCC_OscInitStruct->PLL.PLLR);
NYX	0:85b3fd62ea1a	3303
NYX	0:85b3fd62ea1a	3304	/* Enable the main PLL. */
NYX	0:85b3fd62ea1a	3305	__HAL_RCC_PLL_ENABLE();
NYX	0:85b3fd62ea1a	3306
NYX	0:85b3fd62ea1a	3307	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3308	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3309
NYX	0:85b3fd62ea1a	3310	/* Wait till PLL is ready */
NYX	0:85b3fd62ea1a	3311	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
NYX	0:85b3fd62ea1a	3312	{
NYX	0:85b3fd62ea1a	3313	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3314	{
NYX	0:85b3fd62ea1a	3315	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3316	}
NYX	0:85b3fd62ea1a	3317	}
NYX	0:85b3fd62ea1a	3318	}
NYX	0:85b3fd62ea1a	3319	else
NYX	0:85b3fd62ea1a	3320	{
NYX	0:85b3fd62ea1a	3321	/* Disable the main PLL. */
NYX	0:85b3fd62ea1a	3322	__HAL_RCC_PLL_DISABLE();
NYX	0:85b3fd62ea1a	3323
NYX	0:85b3fd62ea1a	3324	/* Get Start Tick*/
NYX	0:85b3fd62ea1a	3325	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3326
NYX	0:85b3fd62ea1a	3327	/* Wait till PLL is ready */
NYX	0:85b3fd62ea1a	3328	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
NYX	0:85b3fd62ea1a	3329	{
NYX	0:85b3fd62ea1a	3330	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
NYX	0:85b3fd62ea1a	3331	{
NYX	0:85b3fd62ea1a	3332	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3333	}
NYX	0:85b3fd62ea1a	3334	}
NYX	0:85b3fd62ea1a	3335	}
NYX	0:85b3fd62ea1a	3336	}
NYX	0:85b3fd62ea1a	3337	else
NYX	0:85b3fd62ea1a	3338	{
NYX	0:85b3fd62ea1a	3339	return HAL_ERROR;
NYX	0:85b3fd62ea1a	3340	}
NYX	0:85b3fd62ea1a	3341	}
NYX	0:85b3fd62ea1a	3342	return HAL_OK;
NYX	0:85b3fd62ea1a	3343	}
NYX	0:85b3fd62ea1a	3344
NYX	0:85b3fd62ea1a	3345	/**
NYX	0:85b3fd62ea1a	3346	* @brief Configures the RCC_OscInitStruct according to the internal
NYX	0:85b3fd62ea1a	3347	* RCC configuration registers.
NYX	0:85b3fd62ea1a	3348	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
NYX	0:85b3fd62ea1a	3349	*
NYX	0:85b3fd62ea1a	3350	* @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
NYX	0:85b3fd62ea1a	3351	* @note This function add the PLL/PLLR factor management
NYX	0:85b3fd62ea1a	3352	* @retval None
NYX	0:85b3fd62ea1a	3353	*/
NYX	0:85b3fd62ea1a	3354	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
NYX	0:85b3fd62ea1a	3355	{
NYX	0:85b3fd62ea1a	3356	/* Set all possible values for the Oscillator type parameter ---------------*/
NYX	0:85b3fd62ea1a	3357	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
NYX	0:85b3fd62ea1a	3358
NYX	0:85b3fd62ea1a	3359	/* Get the HSE configuration -----------------------------------------------*/
NYX	0:85b3fd62ea1a	3360	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
NYX	0:85b3fd62ea1a	3361	{
NYX	0:85b3fd62ea1a	3362	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
NYX	0:85b3fd62ea1a	3363	}
NYX	0:85b3fd62ea1a	3364	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
NYX	0:85b3fd62ea1a	3365	{
NYX	0:85b3fd62ea1a	3366	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
NYX	0:85b3fd62ea1a	3367	}
NYX	0:85b3fd62ea1a	3368	else
NYX	0:85b3fd62ea1a	3369	{
NYX	0:85b3fd62ea1a	3370	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
NYX	0:85b3fd62ea1a	3371	}
NYX	0:85b3fd62ea1a	3372
NYX	0:85b3fd62ea1a	3373	/* Get the HSI configuration -----------------------------------------------*/
NYX	0:85b3fd62ea1a	3374	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
NYX	0:85b3fd62ea1a	3375	{
NYX	0:85b3fd62ea1a	3376	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
NYX	0:85b3fd62ea1a	3377	}
NYX	0:85b3fd62ea1a	3378	else
NYX	0:85b3fd62ea1a	3379	{
NYX	0:85b3fd62ea1a	3380	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
NYX	0:85b3fd62ea1a	3381	}
NYX	0:85b3fd62ea1a	3382
NYX	0:85b3fd62ea1a	3383	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
NYX	0:85b3fd62ea1a	3384
NYX	0:85b3fd62ea1a	3385	/* Get the LSE configuration -----------------------------------------------*/
NYX	0:85b3fd62ea1a	3386	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
NYX	0:85b3fd62ea1a	3387	{
NYX	0:85b3fd62ea1a	3388	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
NYX	0:85b3fd62ea1a	3389	}
NYX	0:85b3fd62ea1a	3390	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
NYX	0:85b3fd62ea1a	3391	{
NYX	0:85b3fd62ea1a	3392	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
NYX	0:85b3fd62ea1a	3393	}
NYX	0:85b3fd62ea1a	3394	else
NYX	0:85b3fd62ea1a	3395	{
NYX	0:85b3fd62ea1a	3396	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
NYX	0:85b3fd62ea1a	3397	}
NYX	0:85b3fd62ea1a	3398
NYX	0:85b3fd62ea1a	3399	/* Get the LSI configuration -----------------------------------------------*/
NYX	0:85b3fd62ea1a	3400	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
NYX	0:85b3fd62ea1a	3401	{
NYX	0:85b3fd62ea1a	3402	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
NYX	0:85b3fd62ea1a	3403	}
NYX	0:85b3fd62ea1a	3404	else
NYX	0:85b3fd62ea1a	3405	{
NYX	0:85b3fd62ea1a	3406	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
NYX	0:85b3fd62ea1a	3407	}
NYX	0:85b3fd62ea1a	3408
NYX	0:85b3fd62ea1a	3409	/* Get the PLL configuration -----------------------------------------------*/
NYX	0:85b3fd62ea1a	3410	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
NYX	0:85b3fd62ea1a	3411	{
NYX	0:85b3fd62ea1a	3412	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
NYX	0:85b3fd62ea1a	3413	}
NYX	0:85b3fd62ea1a	3414	else
NYX	0:85b3fd62ea1a	3415	{
NYX	0:85b3fd62ea1a	3416	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
NYX	0:85b3fd62ea1a	3417	}
NYX	0:85b3fd62ea1a	3418	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
NYX	0:85b3fd62ea1a	3419	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
NYX	0:85b3fd62ea1a	3420	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
NYX	0:85b3fd62ea1a	3421	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
NYX	0:85b3fd62ea1a	3422	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
NYX	0:85b3fd62ea1a	3423	RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
NYX	0:85b3fd62ea1a	3424	}
NYX	0:85b3fd62ea1a	3425	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	3426
NYX	0:85b3fd62ea1a	3427	#endif /* HAL_RCC_MODULE_ENABLED */
NYX	0:85b3fd62ea1a	3428	/**
NYX	0:85b3fd62ea1a	3429	* @}
NYX	0:85b3fd62ea1a	3430	*/
NYX	0:85b3fd62ea1a	3431
NYX	0:85b3fd62ea1a	3432	/**
NYX	0:85b3fd62ea1a	3433	* @}
NYX	0:85b3fd62ea1a	3434	*/
NYX	0:85b3fd62ea1a	3435
NYX	0:85b3fd62ea1a	3436	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

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