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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

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NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_rcc.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of RCC HAL module.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 39 #ifndef __STM32F4xx_HAL_RCC_H
NYX 0:85b3fd62ea1a 40 #define __STM32F4xx_HAL_RCC_H
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 43 extern "C" {
NYX 0:85b3fd62ea1a 44 #endif
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 47 #include "stm32f4xx_hal_def.h"
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 /* Include RCC HAL Extended module */
NYX 0:85b3fd62ea1a 50 /* (include on top of file since RCC structures are defined in extended file) */
NYX 0:85b3fd62ea1a 51 #include "stm32f4xx_hal_rcc_ex.h"
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 54 * @{
NYX 0:85b3fd62ea1a 55 */
NYX 0:85b3fd62ea1a 56
NYX 0:85b3fd62ea1a 57 /** @addtogroup RCC
NYX 0:85b3fd62ea1a 58 * @{
NYX 0:85b3fd62ea1a 59 */
NYX 0:85b3fd62ea1a 60
NYX 0:85b3fd62ea1a 61 /* Exported types ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 62 /** @defgroup RCC_Exported_Types RCC Exported Types
NYX 0:85b3fd62ea1a 63 * @{
NYX 0:85b3fd62ea1a 64 */
NYX 0:85b3fd62ea1a 65
NYX 0:85b3fd62ea1a 66 /**
NYX 0:85b3fd62ea1a 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
NYX 0:85b3fd62ea1a 68 */
NYX 0:85b3fd62ea1a 69 typedef struct
NYX 0:85b3fd62ea1a 70 {
NYX 0:85b3fd62ea1a 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
NYX 0:85b3fd62ea1a 72 This parameter can be a value of @ref RCC_Oscillator_Type */
NYX 0:85b3fd62ea1a 73
NYX 0:85b3fd62ea1a 74 uint32_t HSEState; /*!< The new state of the HSE.
NYX 0:85b3fd62ea1a 75 This parameter can be a value of @ref RCC_HSE_Config */
NYX 0:85b3fd62ea1a 76
NYX 0:85b3fd62ea1a 77 uint32_t LSEState; /*!< The new state of the LSE.
NYX 0:85b3fd62ea1a 78 This parameter can be a value of @ref RCC_LSE_Config */
NYX 0:85b3fd62ea1a 79
NYX 0:85b3fd62ea1a 80 uint32_t HSIState; /*!< The new state of the HSI.
NYX 0:85b3fd62ea1a 81 This parameter can be a value of @ref RCC_HSI_Config */
NYX 0:85b3fd62ea1a 82
NYX 0:85b3fd62ea1a 83 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
NYX 0:85b3fd62ea1a 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
NYX 0:85b3fd62ea1a 85
NYX 0:85b3fd62ea1a 86 uint32_t LSIState; /*!< The new state of the LSI.
NYX 0:85b3fd62ea1a 87 This parameter can be a value of @ref RCC_LSI_Config */
NYX 0:85b3fd62ea1a 88
NYX 0:85b3fd62ea1a 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
NYX 0:85b3fd62ea1a 90 }RCC_OscInitTypeDef;
NYX 0:85b3fd62ea1a 91
NYX 0:85b3fd62ea1a 92 /**
NYX 0:85b3fd62ea1a 93 * @brief RCC System, AHB and APB busses clock configuration structure definition
NYX 0:85b3fd62ea1a 94 */
NYX 0:85b3fd62ea1a 95 typedef struct
NYX 0:85b3fd62ea1a 96 {
NYX 0:85b3fd62ea1a 97 uint32_t ClockType; /*!< The clock to be configured.
NYX 0:85b3fd62ea1a 98 This parameter can be a value of @ref RCC_System_Clock_Type */
NYX 0:85b3fd62ea1a 99
NYX 0:85b3fd62ea1a 100 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
NYX 0:85b3fd62ea1a 101 This parameter can be a value of @ref RCC_System_Clock_Source */
NYX 0:85b3fd62ea1a 102
NYX 0:85b3fd62ea1a 103 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
NYX 0:85b3fd62ea1a 104 This parameter can be a value of @ref RCC_AHB_Clock_Source */
NYX 0:85b3fd62ea1a 105
NYX 0:85b3fd62ea1a 106 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
NYX 0:85b3fd62ea1a 107 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
NYX 0:85b3fd62ea1a 108
NYX 0:85b3fd62ea1a 109 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
NYX 0:85b3fd62ea1a 110 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
NYX 0:85b3fd62ea1a 111
NYX 0:85b3fd62ea1a 112 }RCC_ClkInitTypeDef;
NYX 0:85b3fd62ea1a 113
NYX 0:85b3fd62ea1a 114 /**
NYX 0:85b3fd62ea1a 115 * @}
NYX 0:85b3fd62ea1a 116 */
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 119 /** @defgroup RCC_Exported_Constants RCC Exported Constants
NYX 0:85b3fd62ea1a 120 * @{
NYX 0:85b3fd62ea1a 121 */
NYX 0:85b3fd62ea1a 122
NYX 0:85b3fd62ea1a 123 /** @defgroup RCC_Oscillator_Type Oscillator Type
NYX 0:85b3fd62ea1a 124 * @{
NYX 0:85b3fd62ea1a 125 */
NYX 0:85b3fd62ea1a 126 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
NYX 0:85b3fd62ea1a 127 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
NYX 0:85b3fd62ea1a 128 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
NYX 0:85b3fd62ea1a 129 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
NYX 0:85b3fd62ea1a 130 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
NYX 0:85b3fd62ea1a 131 /**
NYX 0:85b3fd62ea1a 132 * @}
NYX 0:85b3fd62ea1a 133 */
NYX 0:85b3fd62ea1a 134
NYX 0:85b3fd62ea1a 135 /** @defgroup RCC_HSE_Config HSE Config
NYX 0:85b3fd62ea1a 136 * @{
NYX 0:85b3fd62ea1a 137 */
NYX 0:85b3fd62ea1a 138 #define RCC_HSE_OFF 0x00000000U
NYX 0:85b3fd62ea1a 139 #define RCC_HSE_ON RCC_CR_HSEON
NYX 0:85b3fd62ea1a 140 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
NYX 0:85b3fd62ea1a 141 /**
NYX 0:85b3fd62ea1a 142 * @}
NYX 0:85b3fd62ea1a 143 */
NYX 0:85b3fd62ea1a 144
NYX 0:85b3fd62ea1a 145 /** @defgroup RCC_LSE_Config LSE Config
NYX 0:85b3fd62ea1a 146 * @{
NYX 0:85b3fd62ea1a 147 */
NYX 0:85b3fd62ea1a 148 #define RCC_LSE_OFF 0x00000000U
NYX 0:85b3fd62ea1a 149 #define RCC_LSE_ON RCC_BDCR_LSEON
NYX 0:85b3fd62ea1a 150 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
NYX 0:85b3fd62ea1a 151 /**
NYX 0:85b3fd62ea1a 152 * @}
NYX 0:85b3fd62ea1a 153 */
NYX 0:85b3fd62ea1a 154
NYX 0:85b3fd62ea1a 155 /** @defgroup RCC_HSI_Config HSI Config
NYX 0:85b3fd62ea1a 156 * @{
NYX 0:85b3fd62ea1a 157 */
NYX 0:85b3fd62ea1a 158 #define RCC_HSI_OFF ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 159 #define RCC_HSI_ON ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 160
NYX 0:85b3fd62ea1a 161 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
NYX 0:85b3fd62ea1a 162 /**
NYX 0:85b3fd62ea1a 163 * @}
NYX 0:85b3fd62ea1a 164 */
NYX 0:85b3fd62ea1a 165
NYX 0:85b3fd62ea1a 166 /** @defgroup RCC_LSI_Config LSI Config
NYX 0:85b3fd62ea1a 167 * @{
NYX 0:85b3fd62ea1a 168 */
NYX 0:85b3fd62ea1a 169 #define RCC_LSI_OFF ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 170 #define RCC_LSI_ON ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 171 /**
NYX 0:85b3fd62ea1a 172 * @}
NYX 0:85b3fd62ea1a 173 */
NYX 0:85b3fd62ea1a 174
NYX 0:85b3fd62ea1a 175 /** @defgroup RCC_PLL_Config PLL Config
NYX 0:85b3fd62ea1a 176 * @{
NYX 0:85b3fd62ea1a 177 */
NYX 0:85b3fd62ea1a 178 #define RCC_PLL_NONE ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 179 #define RCC_PLL_OFF ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 180 #define RCC_PLL_ON ((uint8_t)0x02)
NYX 0:85b3fd62ea1a 181 /**
NYX 0:85b3fd62ea1a 182 * @}
NYX 0:85b3fd62ea1a 183 */
NYX 0:85b3fd62ea1a 184
NYX 0:85b3fd62ea1a 185 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
NYX 0:85b3fd62ea1a 186 * @{
NYX 0:85b3fd62ea1a 187 */
NYX 0:85b3fd62ea1a 188 #define RCC_PLLP_DIV2 0x00000002U
NYX 0:85b3fd62ea1a 189 #define RCC_PLLP_DIV4 0x00000004U
NYX 0:85b3fd62ea1a 190 #define RCC_PLLP_DIV6 0x00000006U
NYX 0:85b3fd62ea1a 191 #define RCC_PLLP_DIV8 0x00000008U
NYX 0:85b3fd62ea1a 192 /**
NYX 0:85b3fd62ea1a 193 * @}
NYX 0:85b3fd62ea1a 194 */
NYX 0:85b3fd62ea1a 195
NYX 0:85b3fd62ea1a 196 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
NYX 0:85b3fd62ea1a 197 * @{
NYX 0:85b3fd62ea1a 198 */
NYX 0:85b3fd62ea1a 199 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
NYX 0:85b3fd62ea1a 200 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
NYX 0:85b3fd62ea1a 201 /**
NYX 0:85b3fd62ea1a 202 * @}
NYX 0:85b3fd62ea1a 203 */
NYX 0:85b3fd62ea1a 204
NYX 0:85b3fd62ea1a 205 /** @defgroup RCC_System_Clock_Type System Clock Type
NYX 0:85b3fd62ea1a 206 * @{
NYX 0:85b3fd62ea1a 207 */
NYX 0:85b3fd62ea1a 208 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U
NYX 0:85b3fd62ea1a 209 #define RCC_CLOCKTYPE_HCLK 0x00000002U
NYX 0:85b3fd62ea1a 210 #define RCC_CLOCKTYPE_PCLK1 0x00000004U
NYX 0:85b3fd62ea1a 211 #define RCC_CLOCKTYPE_PCLK2 0x00000008U
NYX 0:85b3fd62ea1a 212 /**
NYX 0:85b3fd62ea1a 213 * @}
NYX 0:85b3fd62ea1a 214 */
NYX 0:85b3fd62ea1a 215
NYX 0:85b3fd62ea1a 216 /** @defgroup RCC_System_Clock_Source System Clock Source
NYX 0:85b3fd62ea1a 217 * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
NYX 0:85b3fd62ea1a 218 * STM32F446xx devices.
NYX 0:85b3fd62ea1a 219 * @{
NYX 0:85b3fd62ea1a 220 */
NYX 0:85b3fd62ea1a 221 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
NYX 0:85b3fd62ea1a 222 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
NYX 0:85b3fd62ea1a 223 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
NYX 0:85b3fd62ea1a 224 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
NYX 0:85b3fd62ea1a 225 /**
NYX 0:85b3fd62ea1a 226 * @}
NYX 0:85b3fd62ea1a 227 */
NYX 0:85b3fd62ea1a 228
NYX 0:85b3fd62ea1a 229 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
NYX 0:85b3fd62ea1a 230 * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
NYX 0:85b3fd62ea1a 231 * STM32F446xx devices.
NYX 0:85b3fd62ea1a 232 * @{
NYX 0:85b3fd62ea1a 233 */
NYX 0:85b3fd62ea1a 234 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
NYX 0:85b3fd62ea1a 235 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
NYX 0:85b3fd62ea1a 236 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
NYX 0:85b3fd62ea1a 237 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
NYX 0:85b3fd62ea1a 238 /**
NYX 0:85b3fd62ea1a 239 * @}
NYX 0:85b3fd62ea1a 240 */
NYX 0:85b3fd62ea1a 241
NYX 0:85b3fd62ea1a 242 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
NYX 0:85b3fd62ea1a 243 * @{
NYX 0:85b3fd62ea1a 244 */
NYX 0:85b3fd62ea1a 245 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
NYX 0:85b3fd62ea1a 246 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
NYX 0:85b3fd62ea1a 247 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
NYX 0:85b3fd62ea1a 248 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
NYX 0:85b3fd62ea1a 249 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
NYX 0:85b3fd62ea1a 250 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
NYX 0:85b3fd62ea1a 251 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
NYX 0:85b3fd62ea1a 252 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
NYX 0:85b3fd62ea1a 253 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
NYX 0:85b3fd62ea1a 254 /**
NYX 0:85b3fd62ea1a 255 * @}
NYX 0:85b3fd62ea1a 256 */
NYX 0:85b3fd62ea1a 257
NYX 0:85b3fd62ea1a 258 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
NYX 0:85b3fd62ea1a 259 * @{
NYX 0:85b3fd62ea1a 260 */
NYX 0:85b3fd62ea1a 261 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
NYX 0:85b3fd62ea1a 262 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
NYX 0:85b3fd62ea1a 263 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
NYX 0:85b3fd62ea1a 264 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
NYX 0:85b3fd62ea1a 265 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
NYX 0:85b3fd62ea1a 266 /**
NYX 0:85b3fd62ea1a 267 * @}
NYX 0:85b3fd62ea1a 268 */
NYX 0:85b3fd62ea1a 269
NYX 0:85b3fd62ea1a 270 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
NYX 0:85b3fd62ea1a 271 * @{
NYX 0:85b3fd62ea1a 272 */
NYX 0:85b3fd62ea1a 273 #define RCC_RTCCLKSOURCE_LSE 0x00000100U
NYX 0:85b3fd62ea1a 274 #define RCC_RTCCLKSOURCE_LSI 0x00000200U
NYX 0:85b3fd62ea1a 275 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
NYX 0:85b3fd62ea1a 276 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
NYX 0:85b3fd62ea1a 277 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
NYX 0:85b3fd62ea1a 278 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
NYX 0:85b3fd62ea1a 279 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
NYX 0:85b3fd62ea1a 280 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
NYX 0:85b3fd62ea1a 281 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
NYX 0:85b3fd62ea1a 282 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
NYX 0:85b3fd62ea1a 283 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
NYX 0:85b3fd62ea1a 284 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
NYX 0:85b3fd62ea1a 285 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
NYX 0:85b3fd62ea1a 286 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
NYX 0:85b3fd62ea1a 287 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
NYX 0:85b3fd62ea1a 288 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
NYX 0:85b3fd62ea1a 289 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
NYX 0:85b3fd62ea1a 290 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
NYX 0:85b3fd62ea1a 291 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
NYX 0:85b3fd62ea1a 292 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
NYX 0:85b3fd62ea1a 293 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
NYX 0:85b3fd62ea1a 294 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
NYX 0:85b3fd62ea1a 295 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
NYX 0:85b3fd62ea1a 296 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
NYX 0:85b3fd62ea1a 297 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
NYX 0:85b3fd62ea1a 298 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
NYX 0:85b3fd62ea1a 299 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
NYX 0:85b3fd62ea1a 300 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
NYX 0:85b3fd62ea1a 301 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
NYX 0:85b3fd62ea1a 302 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
NYX 0:85b3fd62ea1a 303 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
NYX 0:85b3fd62ea1a 304 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
NYX 0:85b3fd62ea1a 305 /**
NYX 0:85b3fd62ea1a 306 * @}
NYX 0:85b3fd62ea1a 307 */
NYX 0:85b3fd62ea1a 308
NYX 0:85b3fd62ea1a 309 /** @defgroup RCC_MCO_Index MCO Index
NYX 0:85b3fd62ea1a 310 * @{
NYX 0:85b3fd62ea1a 311 */
NYX 0:85b3fd62ea1a 312 #define RCC_MCO1 0x00000000U
NYX 0:85b3fd62ea1a 313 #define RCC_MCO2 0x00000001U
NYX 0:85b3fd62ea1a 314 /**
NYX 0:85b3fd62ea1a 315 * @}
NYX 0:85b3fd62ea1a 316 */
NYX 0:85b3fd62ea1a 317
NYX 0:85b3fd62ea1a 318 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
NYX 0:85b3fd62ea1a 319 * @{
NYX 0:85b3fd62ea1a 320 */
NYX 0:85b3fd62ea1a 321 #define RCC_MCO1SOURCE_HSI 0x00000000U
NYX 0:85b3fd62ea1a 322 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
NYX 0:85b3fd62ea1a 323 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
NYX 0:85b3fd62ea1a 324 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
NYX 0:85b3fd62ea1a 325 /**
NYX 0:85b3fd62ea1a 326 * @}
NYX 0:85b3fd62ea1a 327 */
NYX 0:85b3fd62ea1a 328
NYX 0:85b3fd62ea1a 329 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
NYX 0:85b3fd62ea1a 330 * @{
NYX 0:85b3fd62ea1a 331 */
NYX 0:85b3fd62ea1a 332 #define RCC_MCODIV_1 0x00000000U
NYX 0:85b3fd62ea1a 333 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
NYX 0:85b3fd62ea1a 334 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
NYX 0:85b3fd62ea1a 335 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
NYX 0:85b3fd62ea1a 336 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
NYX 0:85b3fd62ea1a 337 /**
NYX 0:85b3fd62ea1a 338 * @}
NYX 0:85b3fd62ea1a 339 */
NYX 0:85b3fd62ea1a 340
NYX 0:85b3fd62ea1a 341 /** @defgroup RCC_Interrupt Interrupts
NYX 0:85b3fd62ea1a 342 * @{
NYX 0:85b3fd62ea1a 343 */
NYX 0:85b3fd62ea1a 344 #define RCC_IT_LSIRDY ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 345 #define RCC_IT_LSERDY ((uint8_t)0x02)
NYX 0:85b3fd62ea1a 346 #define RCC_IT_HSIRDY ((uint8_t)0x04)
NYX 0:85b3fd62ea1a 347 #define RCC_IT_HSERDY ((uint8_t)0x08)
NYX 0:85b3fd62ea1a 348 #define RCC_IT_PLLRDY ((uint8_t)0x10)
NYX 0:85b3fd62ea1a 349 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
NYX 0:85b3fd62ea1a 350 #define RCC_IT_CSS ((uint8_t)0x80)
NYX 0:85b3fd62ea1a 351 /**
NYX 0:85b3fd62ea1a 352 * @}
NYX 0:85b3fd62ea1a 353 */
NYX 0:85b3fd62ea1a 354
NYX 0:85b3fd62ea1a 355 /** @defgroup RCC_Flag Flags
NYX 0:85b3fd62ea1a 356 * Elements values convention: 0XXYYYYYb
NYX 0:85b3fd62ea1a 357 * - YYYYY : Flag position in the register
NYX 0:85b3fd62ea1a 358 * - 0XX : Register index
NYX 0:85b3fd62ea1a 359 * - 01: CR register
NYX 0:85b3fd62ea1a 360 * - 10: BDCR register
NYX 0:85b3fd62ea1a 361 * - 11: CSR register
NYX 0:85b3fd62ea1a 362 * @{
NYX 0:85b3fd62ea1a 363 */
NYX 0:85b3fd62ea1a 364 /* Flags in the CR register */
NYX 0:85b3fd62ea1a 365 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
NYX 0:85b3fd62ea1a 366 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
NYX 0:85b3fd62ea1a 367 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
NYX 0:85b3fd62ea1a 368 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
NYX 0:85b3fd62ea1a 369
NYX 0:85b3fd62ea1a 370 /* Flags in the BDCR register */
NYX 0:85b3fd62ea1a 371 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
NYX 0:85b3fd62ea1a 372
NYX 0:85b3fd62ea1a 373 /* Flags in the CSR register */
NYX 0:85b3fd62ea1a 374 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
NYX 0:85b3fd62ea1a 375 #define RCC_FLAG_BORRST ((uint8_t)0x79)
NYX 0:85b3fd62ea1a 376 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
NYX 0:85b3fd62ea1a 377 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
NYX 0:85b3fd62ea1a 378 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
NYX 0:85b3fd62ea1a 379 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
NYX 0:85b3fd62ea1a 380 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
NYX 0:85b3fd62ea1a 381 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
NYX 0:85b3fd62ea1a 382 /**
NYX 0:85b3fd62ea1a 383 * @}
NYX 0:85b3fd62ea1a 384 */
NYX 0:85b3fd62ea1a 385
NYX 0:85b3fd62ea1a 386 /**
NYX 0:85b3fd62ea1a 387 * @}
NYX 0:85b3fd62ea1a 388 */
NYX 0:85b3fd62ea1a 389
NYX 0:85b3fd62ea1a 390 /* Exported macro ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 391 /** @defgroup RCC_Exported_Macros RCC Exported Macros
NYX 0:85b3fd62ea1a 392 * @{
NYX 0:85b3fd62ea1a 393 */
NYX 0:85b3fd62ea1a 394
NYX 0:85b3fd62ea1a 395 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
NYX 0:85b3fd62ea1a 396 * @brief Enable or disable the AHB1 peripheral clock.
NYX 0:85b3fd62ea1a 397 * @note After reset, the peripheral clock (used for registers read/write access)
NYX 0:85b3fd62ea1a 398 * is disabled and the application software has to enable this clock before
NYX 0:85b3fd62ea1a 399 * using it.
NYX 0:85b3fd62ea1a 400 * @{
NYX 0:85b3fd62ea1a 401 */
NYX 0:85b3fd62ea1a 402 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 403 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 404 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
NYX 0:85b3fd62ea1a 405 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 406 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
NYX 0:85b3fd62ea1a 407 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 408 } while(0U)
NYX 0:85b3fd62ea1a 409 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 410 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 411 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
NYX 0:85b3fd62ea1a 412 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 413 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
NYX 0:85b3fd62ea1a 414 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 415 } while(0U)
NYX 0:85b3fd62ea1a 416 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 417 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 418 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
NYX 0:85b3fd62ea1a 419 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 420 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
NYX 0:85b3fd62ea1a 421 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 422 } while(0U)
NYX 0:85b3fd62ea1a 423 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 424 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 425 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
NYX 0:85b3fd62ea1a 426 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 427 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
NYX 0:85b3fd62ea1a 428 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 429 } while(0U)
NYX 0:85b3fd62ea1a 430 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 431 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 432 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
NYX 0:85b3fd62ea1a 433 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 434 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
NYX 0:85b3fd62ea1a 435 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 436 } while(0U)
NYX 0:85b3fd62ea1a 437 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 438 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 439 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
NYX 0:85b3fd62ea1a 440 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 441 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
NYX 0:85b3fd62ea1a 442 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 443 } while(0U)
NYX 0:85b3fd62ea1a 444
NYX 0:85b3fd62ea1a 445 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
NYX 0:85b3fd62ea1a 446 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
NYX 0:85b3fd62ea1a 447 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
NYX 0:85b3fd62ea1a 448 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
NYX 0:85b3fd62ea1a 449 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
NYX 0:85b3fd62ea1a 450 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
NYX 0:85b3fd62ea1a 451 /**
NYX 0:85b3fd62ea1a 452 * @}
NYX 0:85b3fd62ea1a 453 */
NYX 0:85b3fd62ea1a 454
NYX 0:85b3fd62ea1a 455 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
NYX 0:85b3fd62ea1a 456 * @brief Get the enable or disable status of the AHB1 peripheral clock.
NYX 0:85b3fd62ea1a 457 * @note After reset, the peripheral clock (used for registers read/write access)
NYX 0:85b3fd62ea1a 458 * is disabled and the application software has to enable this clock before
NYX 0:85b3fd62ea1a 459 * using it.
NYX 0:85b3fd62ea1a 460 * @{
NYX 0:85b3fd62ea1a 461 */
NYX 0:85b3fd62ea1a 462 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
NYX 0:85b3fd62ea1a 463 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
NYX 0:85b3fd62ea1a 464 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
NYX 0:85b3fd62ea1a 465 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
NYX 0:85b3fd62ea1a 466 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
NYX 0:85b3fd62ea1a 467 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
NYX 0:85b3fd62ea1a 468
NYX 0:85b3fd62ea1a 469 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
NYX 0:85b3fd62ea1a 470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
NYX 0:85b3fd62ea1a 471 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
NYX 0:85b3fd62ea1a 472 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
NYX 0:85b3fd62ea1a 473 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
NYX 0:85b3fd62ea1a 474 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
NYX 0:85b3fd62ea1a 475 /**
NYX 0:85b3fd62ea1a 476 * @}
NYX 0:85b3fd62ea1a 477 */
NYX 0:85b3fd62ea1a 478
NYX 0:85b3fd62ea1a 479 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
NYX 0:85b3fd62ea1a 480 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
NYX 0:85b3fd62ea1a 481 * @note After reset, the peripheral clock (used for registers read/write access)
NYX 0:85b3fd62ea1a 482 * is disabled and the application software has to enable this clock before
NYX 0:85b3fd62ea1a 483 * using it.
NYX 0:85b3fd62ea1a 484 * @{
NYX 0:85b3fd62ea1a 485 */
NYX 0:85b3fd62ea1a 486 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 487 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
NYX 0:85b3fd62ea1a 489 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
NYX 0:85b3fd62ea1a 491 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 492 } while(0U)
NYX 0:85b3fd62ea1a 493 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 494 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
NYX 0:85b3fd62ea1a 496 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 497 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
NYX 0:85b3fd62ea1a 498 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 499 } while(0U)
NYX 0:85b3fd62ea1a 500 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 501 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 502 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
NYX 0:85b3fd62ea1a 503 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 504 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
NYX 0:85b3fd62ea1a 505 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 506 } while(0U)
NYX 0:85b3fd62ea1a 507 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 508 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 509 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
NYX 0:85b3fd62ea1a 510 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 511 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
NYX 0:85b3fd62ea1a 512 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 513 } while(0U)
NYX 0:85b3fd62ea1a 514 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 515 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 516 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
NYX 0:85b3fd62ea1a 517 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 518 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
NYX 0:85b3fd62ea1a 519 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 520 } while(0U)
NYX 0:85b3fd62ea1a 521 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 522 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 523 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
NYX 0:85b3fd62ea1a 524 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 525 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
NYX 0:85b3fd62ea1a 526 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 527 } while(0U)
NYX 0:85b3fd62ea1a 528 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 529 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 530 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
NYX 0:85b3fd62ea1a 531 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 532 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
NYX 0:85b3fd62ea1a 533 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 534 } while(0U)
NYX 0:85b3fd62ea1a 535
NYX 0:85b3fd62ea1a 536 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
NYX 0:85b3fd62ea1a 537 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
NYX 0:85b3fd62ea1a 538 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
NYX 0:85b3fd62ea1a 539 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
NYX 0:85b3fd62ea1a 540 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
NYX 0:85b3fd62ea1a 541 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
NYX 0:85b3fd62ea1a 542 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
NYX 0:85b3fd62ea1a 543 /**
NYX 0:85b3fd62ea1a 544 * @}
NYX 0:85b3fd62ea1a 545 */
NYX 0:85b3fd62ea1a 546
NYX 0:85b3fd62ea1a 547 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
NYX 0:85b3fd62ea1a 548 * @brief Get the enable or disable status of the APB1 peripheral clock.
NYX 0:85b3fd62ea1a 549 * @note After reset, the peripheral clock (used for registers read/write access)
NYX 0:85b3fd62ea1a 550 * is disabled and the application software has to enable this clock before
NYX 0:85b3fd62ea1a 551 * using it.
NYX 0:85b3fd62ea1a 552 * @{
NYX 0:85b3fd62ea1a 553 */
NYX 0:85b3fd62ea1a 554 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
NYX 0:85b3fd62ea1a 555 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
NYX 0:85b3fd62ea1a 556 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
NYX 0:85b3fd62ea1a 557 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
NYX 0:85b3fd62ea1a 558 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
NYX 0:85b3fd62ea1a 559 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
NYX 0:85b3fd62ea1a 560 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
NYX 0:85b3fd62ea1a 561
NYX 0:85b3fd62ea1a 562 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
NYX 0:85b3fd62ea1a 563 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
NYX 0:85b3fd62ea1a 564 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
NYX 0:85b3fd62ea1a 565 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
NYX 0:85b3fd62ea1a 566 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
NYX 0:85b3fd62ea1a 567 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
NYX 0:85b3fd62ea1a 568 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
NYX 0:85b3fd62ea1a 569 /**
NYX 0:85b3fd62ea1a 570 * @}
NYX 0:85b3fd62ea1a 571 */
NYX 0:85b3fd62ea1a 572
NYX 0:85b3fd62ea1a 573 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
NYX 0:85b3fd62ea1a 574 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
NYX 0:85b3fd62ea1a 575 * @note After reset, the peripheral clock (used for registers read/write access)
NYX 0:85b3fd62ea1a 576 * is disabled and the application software has to enable this clock before
NYX 0:85b3fd62ea1a 577 * using it.
NYX 0:85b3fd62ea1a 578 * @{
NYX 0:85b3fd62ea1a 579 */
NYX 0:85b3fd62ea1a 580 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 581 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
NYX 0:85b3fd62ea1a 583 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
NYX 0:85b3fd62ea1a 585 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 586 } while(0U)
NYX 0:85b3fd62ea1a 587 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 588 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 589 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
NYX 0:85b3fd62ea1a 590 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 591 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
NYX 0:85b3fd62ea1a 592 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 593 } while(0U)
NYX 0:85b3fd62ea1a 594 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 595 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 596 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
NYX 0:85b3fd62ea1a 597 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 598 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
NYX 0:85b3fd62ea1a 599 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 600 } while(0U)
NYX 0:85b3fd62ea1a 601 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 602 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 603 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
NYX 0:85b3fd62ea1a 604 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 605 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
NYX 0:85b3fd62ea1a 606 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 607 } while(0U)
NYX 0:85b3fd62ea1a 608 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 609 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 610 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
NYX 0:85b3fd62ea1a 611 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 612 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
NYX 0:85b3fd62ea1a 613 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 614 } while(0U)
NYX 0:85b3fd62ea1a 615 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 616 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 617 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
NYX 0:85b3fd62ea1a 618 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 619 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
NYX 0:85b3fd62ea1a 620 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 621 } while(0U)
NYX 0:85b3fd62ea1a 622 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 623 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 624 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
NYX 0:85b3fd62ea1a 625 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 626 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
NYX 0:85b3fd62ea1a 627 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 628 } while(0U)
NYX 0:85b3fd62ea1a 629 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
NYX 0:85b3fd62ea1a 630 __IO uint32_t tmpreg = 0x00U; \
NYX 0:85b3fd62ea1a 631 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
NYX 0:85b3fd62ea1a 632 /* Delay after an RCC peripheral clock enabling */ \
NYX 0:85b3fd62ea1a 633 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
NYX 0:85b3fd62ea1a 634 UNUSED(tmpreg); \
NYX 0:85b3fd62ea1a 635 } while(0U)
NYX 0:85b3fd62ea1a 636
NYX 0:85b3fd62ea1a 637 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
NYX 0:85b3fd62ea1a 638 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
NYX 0:85b3fd62ea1a 639 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
NYX 0:85b3fd62ea1a 640 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
NYX 0:85b3fd62ea1a 641 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
NYX 0:85b3fd62ea1a 642 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
NYX 0:85b3fd62ea1a 643 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
NYX 0:85b3fd62ea1a 644 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
NYX 0:85b3fd62ea1a 645 /**
NYX 0:85b3fd62ea1a 646 * @}
NYX 0:85b3fd62ea1a 647 */
NYX 0:85b3fd62ea1a 648
NYX 0:85b3fd62ea1a 649 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
NYX 0:85b3fd62ea1a 650 * @brief Get the enable or disable status of the APB2 peripheral clock.
NYX 0:85b3fd62ea1a 651 * @note After reset, the peripheral clock (used for registers read/write access)
NYX 0:85b3fd62ea1a 652 * is disabled and the application software has to enable this clock before
NYX 0:85b3fd62ea1a 653 * using it.
NYX 0:85b3fd62ea1a 654 * @{
NYX 0:85b3fd62ea1a 655 */
NYX 0:85b3fd62ea1a 656 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
NYX 0:85b3fd62ea1a 657 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
NYX 0:85b3fd62ea1a 658 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
NYX 0:85b3fd62ea1a 659 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
NYX 0:85b3fd62ea1a 660 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
NYX 0:85b3fd62ea1a 661 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
NYX 0:85b3fd62ea1a 662 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
NYX 0:85b3fd62ea1a 663 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
NYX 0:85b3fd62ea1a 664
NYX 0:85b3fd62ea1a 665 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
NYX 0:85b3fd62ea1a 666 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
NYX 0:85b3fd62ea1a 667 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
NYX 0:85b3fd62ea1a 668 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
NYX 0:85b3fd62ea1a 669 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
NYX 0:85b3fd62ea1a 670 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
NYX 0:85b3fd62ea1a 671 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
NYX 0:85b3fd62ea1a 672 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
NYX 0:85b3fd62ea1a 673 /**
NYX 0:85b3fd62ea1a 674 * @}
NYX 0:85b3fd62ea1a 675 */
NYX 0:85b3fd62ea1a 676
NYX 0:85b3fd62ea1a 677 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
NYX 0:85b3fd62ea1a 678 * @brief Force or release AHB1 peripheral reset.
NYX 0:85b3fd62ea1a 679 * @{
NYX 0:85b3fd62ea1a 680 */
NYX 0:85b3fd62ea1a 681 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
NYX 0:85b3fd62ea1a 682 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
NYX 0:85b3fd62ea1a 683 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
NYX 0:85b3fd62ea1a 684 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
NYX 0:85b3fd62ea1a 685 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
NYX 0:85b3fd62ea1a 686 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
NYX 0:85b3fd62ea1a 687 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
NYX 0:85b3fd62ea1a 688
NYX 0:85b3fd62ea1a 689 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
NYX 0:85b3fd62ea1a 690 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
NYX 0:85b3fd62ea1a 691 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
NYX 0:85b3fd62ea1a 692 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
NYX 0:85b3fd62ea1a 693 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
NYX 0:85b3fd62ea1a 694 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
NYX 0:85b3fd62ea1a 695 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
NYX 0:85b3fd62ea1a 696 /**
NYX 0:85b3fd62ea1a 697 * @}
NYX 0:85b3fd62ea1a 698 */
NYX 0:85b3fd62ea1a 699
NYX 0:85b3fd62ea1a 700 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
NYX 0:85b3fd62ea1a 701 * @brief Force or release APB1 peripheral reset.
NYX 0:85b3fd62ea1a 702 * @{
NYX 0:85b3fd62ea1a 703 */
NYX 0:85b3fd62ea1a 704 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
NYX 0:85b3fd62ea1a 705 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
NYX 0:85b3fd62ea1a 706 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
NYX 0:85b3fd62ea1a 707 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
NYX 0:85b3fd62ea1a 708 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
NYX 0:85b3fd62ea1a 709 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
NYX 0:85b3fd62ea1a 710 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
NYX 0:85b3fd62ea1a 711 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
NYX 0:85b3fd62ea1a 712
NYX 0:85b3fd62ea1a 713 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
NYX 0:85b3fd62ea1a 714 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
NYX 0:85b3fd62ea1a 715 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
NYX 0:85b3fd62ea1a 716 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
NYX 0:85b3fd62ea1a 717 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
NYX 0:85b3fd62ea1a 718 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
NYX 0:85b3fd62ea1a 719 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
NYX 0:85b3fd62ea1a 720 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
NYX 0:85b3fd62ea1a 721 /**
NYX 0:85b3fd62ea1a 722 * @}
NYX 0:85b3fd62ea1a 723 */
NYX 0:85b3fd62ea1a 724
NYX 0:85b3fd62ea1a 725 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
NYX 0:85b3fd62ea1a 726 * @brief Force or release APB2 peripheral reset.
NYX 0:85b3fd62ea1a 727 * @{
NYX 0:85b3fd62ea1a 728 */
NYX 0:85b3fd62ea1a 729 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
NYX 0:85b3fd62ea1a 730 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
NYX 0:85b3fd62ea1a 731 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
NYX 0:85b3fd62ea1a 732 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
NYX 0:85b3fd62ea1a 733 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
NYX 0:85b3fd62ea1a 734 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
NYX 0:85b3fd62ea1a 735 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
NYX 0:85b3fd62ea1a 736 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
NYX 0:85b3fd62ea1a 737 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
NYX 0:85b3fd62ea1a 738
NYX 0:85b3fd62ea1a 739 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
NYX 0:85b3fd62ea1a 740 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
NYX 0:85b3fd62ea1a 741 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
NYX 0:85b3fd62ea1a 742 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
NYX 0:85b3fd62ea1a 743 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
NYX 0:85b3fd62ea1a 744 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
NYX 0:85b3fd62ea1a 745 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
NYX 0:85b3fd62ea1a 746 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
NYX 0:85b3fd62ea1a 747 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
NYX 0:85b3fd62ea1a 748 /**
NYX 0:85b3fd62ea1a 749 * @}
NYX 0:85b3fd62ea1a 750 */
NYX 0:85b3fd62ea1a 751
NYX 0:85b3fd62ea1a 752 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
NYX 0:85b3fd62ea1a 753 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
NYX 0:85b3fd62ea1a 754 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX 0:85b3fd62ea1a 755 * power consumption.
NYX 0:85b3fd62ea1a 756 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX 0:85b3fd62ea1a 757 * @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX 0:85b3fd62ea1a 758 * @{
NYX 0:85b3fd62ea1a 759 */
NYX 0:85b3fd62ea1a 760 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
NYX 0:85b3fd62ea1a 761 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
NYX 0:85b3fd62ea1a 762 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
NYX 0:85b3fd62ea1a 763 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
NYX 0:85b3fd62ea1a 764 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
NYX 0:85b3fd62ea1a 765 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
NYX 0:85b3fd62ea1a 766
NYX 0:85b3fd62ea1a 767 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
NYX 0:85b3fd62ea1a 768 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
NYX 0:85b3fd62ea1a 769 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
NYX 0:85b3fd62ea1a 770 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
NYX 0:85b3fd62ea1a 771 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
NYX 0:85b3fd62ea1a 772 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
NYX 0:85b3fd62ea1a 773 /**
NYX 0:85b3fd62ea1a 774 * @}
NYX 0:85b3fd62ea1a 775 */
NYX 0:85b3fd62ea1a 776
NYX 0:85b3fd62ea1a 777 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
NYX 0:85b3fd62ea1a 778 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
NYX 0:85b3fd62ea1a 779 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX 0:85b3fd62ea1a 780 * power consumption.
NYX 0:85b3fd62ea1a 781 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX 0:85b3fd62ea1a 782 * @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX 0:85b3fd62ea1a 783 * @{
NYX 0:85b3fd62ea1a 784 */
NYX 0:85b3fd62ea1a 785 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
NYX 0:85b3fd62ea1a 786 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
NYX 0:85b3fd62ea1a 787 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
NYX 0:85b3fd62ea1a 788 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
NYX 0:85b3fd62ea1a 789 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
NYX 0:85b3fd62ea1a 790 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
NYX 0:85b3fd62ea1a 791 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
NYX 0:85b3fd62ea1a 792
NYX 0:85b3fd62ea1a 793 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
NYX 0:85b3fd62ea1a 794 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
NYX 0:85b3fd62ea1a 795 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
NYX 0:85b3fd62ea1a 796 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
NYX 0:85b3fd62ea1a 797 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
NYX 0:85b3fd62ea1a 798 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
NYX 0:85b3fd62ea1a 799 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
NYX 0:85b3fd62ea1a 800 /**
NYX 0:85b3fd62ea1a 801 * @}
NYX 0:85b3fd62ea1a 802 */
NYX 0:85b3fd62ea1a 803
NYX 0:85b3fd62ea1a 804 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
NYX 0:85b3fd62ea1a 805 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
NYX 0:85b3fd62ea1a 806 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
NYX 0:85b3fd62ea1a 807 * power consumption.
NYX 0:85b3fd62ea1a 808 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
NYX 0:85b3fd62ea1a 809 * @note By default, all peripheral clocks are enabled during SLEEP mode.
NYX 0:85b3fd62ea1a 810 * @{
NYX 0:85b3fd62ea1a 811 */
NYX 0:85b3fd62ea1a 812 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
NYX 0:85b3fd62ea1a 813 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
NYX 0:85b3fd62ea1a 814 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
NYX 0:85b3fd62ea1a 815 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
NYX 0:85b3fd62ea1a 816 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
NYX 0:85b3fd62ea1a 817 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
NYX 0:85b3fd62ea1a 818 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
NYX 0:85b3fd62ea1a 819 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
NYX 0:85b3fd62ea1a 820
NYX 0:85b3fd62ea1a 821 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
NYX 0:85b3fd62ea1a 822 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
NYX 0:85b3fd62ea1a 823 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
NYX 0:85b3fd62ea1a 824 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
NYX 0:85b3fd62ea1a 825 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
NYX 0:85b3fd62ea1a 826 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
NYX 0:85b3fd62ea1a 827 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
NYX 0:85b3fd62ea1a 828 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
NYX 0:85b3fd62ea1a 829 /**
NYX 0:85b3fd62ea1a 830 * @}
NYX 0:85b3fd62ea1a 831 */
NYX 0:85b3fd62ea1a 832
NYX 0:85b3fd62ea1a 833 /** @defgroup RCC_HSI_Configuration HSI Configuration
NYX 0:85b3fd62ea1a 834 * @{
NYX 0:85b3fd62ea1a 835 */
NYX 0:85b3fd62ea1a 836
NYX 0:85b3fd62ea1a 837 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
NYX 0:85b3fd62ea1a 838 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
NYX 0:85b3fd62ea1a 839 * It is used (enabled by hardware) as system clock source after startup
NYX 0:85b3fd62ea1a 840 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
NYX 0:85b3fd62ea1a 841 * of the HSE used directly or indirectly as system clock (if the Clock
NYX 0:85b3fd62ea1a 842 * Security System CSS is enabled).
NYX 0:85b3fd62ea1a 843 * @note HSI can not be stopped if it is used as system clock source. In this case,
NYX 0:85b3fd62ea1a 844 * you have to select another source of the system clock then stop the HSI.
NYX 0:85b3fd62ea1a 845 * @note After enabling the HSI, the application software should wait on HSIRDY
NYX 0:85b3fd62ea1a 846 * flag to be set indicating that HSI clock is stable and can be used as
NYX 0:85b3fd62ea1a 847 * system clock source.
NYX 0:85b3fd62ea1a 848 * This parameter can be: ENABLE or DISABLE.
NYX 0:85b3fd62ea1a 849 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
NYX 0:85b3fd62ea1a 850 * clock cycles.
NYX 0:85b3fd62ea1a 851 */
NYX 0:85b3fd62ea1a 852 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
NYX 0:85b3fd62ea1a 853 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
NYX 0:85b3fd62ea1a 854
NYX 0:85b3fd62ea1a 855 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
NYX 0:85b3fd62ea1a 856 * @note The calibration is used to compensate for the variations in voltage
NYX 0:85b3fd62ea1a 857 * and temperature that influence the frequency of the internal HSI RC.
NYX 0:85b3fd62ea1a 858 * @param __HSICalibrationValue__: specifies the calibration trimming value.
NYX 0:85b3fd62ea1a 859 * (default is RCC_HSICALIBRATION_DEFAULT).
NYX 0:85b3fd62ea1a 860 * This parameter must be a number between 0 and 0x1F.
NYX 0:85b3fd62ea1a 861 */
NYX 0:85b3fd62ea1a 862 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
NYX 0:85b3fd62ea1a 863 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
NYX 0:85b3fd62ea1a 864 /**
NYX 0:85b3fd62ea1a 865 * @}
NYX 0:85b3fd62ea1a 866 */
NYX 0:85b3fd62ea1a 867
NYX 0:85b3fd62ea1a 868 /** @defgroup RCC_LSI_Configuration LSI Configuration
NYX 0:85b3fd62ea1a 869 * @{
NYX 0:85b3fd62ea1a 870 */
NYX 0:85b3fd62ea1a 871
NYX 0:85b3fd62ea1a 872 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
NYX 0:85b3fd62ea1a 873 * @note After enabling the LSI, the application software should wait on
NYX 0:85b3fd62ea1a 874 * LSIRDY flag to be set indicating that LSI clock is stable and can
NYX 0:85b3fd62ea1a 875 * be used to clock the IWDG and/or the RTC.
NYX 0:85b3fd62ea1a 876 * @note LSI can not be disabled if the IWDG is running.
NYX 0:85b3fd62ea1a 877 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
NYX 0:85b3fd62ea1a 878 * clock cycles.
NYX 0:85b3fd62ea1a 879 */
NYX 0:85b3fd62ea1a 880 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
NYX 0:85b3fd62ea1a 881 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
NYX 0:85b3fd62ea1a 882 /**
NYX 0:85b3fd62ea1a 883 * @}
NYX 0:85b3fd62ea1a 884 */
NYX 0:85b3fd62ea1a 885
NYX 0:85b3fd62ea1a 886 /** @defgroup RCC_HSE_Configuration HSE Configuration
NYX 0:85b3fd62ea1a 887 * @{
NYX 0:85b3fd62ea1a 888 */
NYX 0:85b3fd62ea1a 889
NYX 0:85b3fd62ea1a 890 /**
NYX 0:85b3fd62ea1a 891 * @brief Macro to configure the External High Speed oscillator (HSE).
NYX 0:85b3fd62ea1a 892 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
NYX 0:85b3fd62ea1a 893 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
NYX 0:85b3fd62ea1a 894 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
NYX 0:85b3fd62ea1a 895 * software should wait on HSERDY flag to be set indicating that HSE clock
NYX 0:85b3fd62ea1a 896 * is stable and can be used to clock the PLL and/or system clock.
NYX 0:85b3fd62ea1a 897 * @note HSE state can not be changed if it is used directly or through the
NYX 0:85b3fd62ea1a 898 * PLL as system clock. In this case, you have to select another source
NYX 0:85b3fd62ea1a 899 * of the system clock then change the HSE state (ex. disable it).
NYX 0:85b3fd62ea1a 900 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
NYX 0:85b3fd62ea1a 901 * @note This function reset the CSSON bit, so if the clock security system(CSS)
NYX 0:85b3fd62ea1a 902 * was previously enabled you have to enable it again after calling this
NYX 0:85b3fd62ea1a 903 * function.
NYX 0:85b3fd62ea1a 904 * @param __STATE__: specifies the new state of the HSE.
NYX 0:85b3fd62ea1a 905 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 906 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
NYX 0:85b3fd62ea1a 907 * 6 HSE oscillator clock cycles.
NYX 0:85b3fd62ea1a 908 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
NYX 0:85b3fd62ea1a 909 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
NYX 0:85b3fd62ea1a 910 */
NYX 0:85b3fd62ea1a 911 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
NYX 0:85b3fd62ea1a 912 do { \
NYX 0:85b3fd62ea1a 913 if ((__STATE__) == RCC_HSE_ON) \
NYX 0:85b3fd62ea1a 914 { \
NYX 0:85b3fd62ea1a 915 SET_BIT(RCC->CR, RCC_CR_HSEON); \
NYX 0:85b3fd62ea1a 916 } \
NYX 0:85b3fd62ea1a 917 else if ((__STATE__) == RCC_HSE_BYPASS) \
NYX 0:85b3fd62ea1a 918 { \
NYX 0:85b3fd62ea1a 919 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
NYX 0:85b3fd62ea1a 920 SET_BIT(RCC->CR, RCC_CR_HSEON); \
NYX 0:85b3fd62ea1a 921 } \
NYX 0:85b3fd62ea1a 922 else \
NYX 0:85b3fd62ea1a 923 { \
NYX 0:85b3fd62ea1a 924 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
NYX 0:85b3fd62ea1a 925 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
NYX 0:85b3fd62ea1a 926 } \
NYX 0:85b3fd62ea1a 927 } while(0U)
NYX 0:85b3fd62ea1a 928 /**
NYX 0:85b3fd62ea1a 929 * @}
NYX 0:85b3fd62ea1a 930 */
NYX 0:85b3fd62ea1a 931
NYX 0:85b3fd62ea1a 932 /** @defgroup RCC_LSE_Configuration LSE Configuration
NYX 0:85b3fd62ea1a 933 * @{
NYX 0:85b3fd62ea1a 934 */
NYX 0:85b3fd62ea1a 935
NYX 0:85b3fd62ea1a 936 /**
NYX 0:85b3fd62ea1a 937 * @brief Macro to configure the External Low Speed oscillator (LSE).
NYX 0:85b3fd62ea1a 938 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
NYX 0:85b3fd62ea1a 939 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
NYX 0:85b3fd62ea1a 940 * @note As the LSE is in the Backup domain and write access is denied to
NYX 0:85b3fd62ea1a 941 * this domain after reset, you have to enable write access using
NYX 0:85b3fd62ea1a 942 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
NYX 0:85b3fd62ea1a 943 * (to be done once after reset).
NYX 0:85b3fd62ea1a 944 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
NYX 0:85b3fd62ea1a 945 * software should wait on LSERDY flag to be set indicating that LSE clock
NYX 0:85b3fd62ea1a 946 * is stable and can be used to clock the RTC.
NYX 0:85b3fd62ea1a 947 * @param __STATE__: specifies the new state of the LSE.
NYX 0:85b3fd62ea1a 948 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 949 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
NYX 0:85b3fd62ea1a 950 * 6 LSE oscillator clock cycles.
NYX 0:85b3fd62ea1a 951 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
NYX 0:85b3fd62ea1a 952 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
NYX 0:85b3fd62ea1a 953 */
NYX 0:85b3fd62ea1a 954 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
NYX 0:85b3fd62ea1a 955 do { \
NYX 0:85b3fd62ea1a 956 if((__STATE__) == RCC_LSE_ON) \
NYX 0:85b3fd62ea1a 957 { \
NYX 0:85b3fd62ea1a 958 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
NYX 0:85b3fd62ea1a 959 } \
NYX 0:85b3fd62ea1a 960 else if((__STATE__) == RCC_LSE_BYPASS) \
NYX 0:85b3fd62ea1a 961 { \
NYX 0:85b3fd62ea1a 962 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
NYX 0:85b3fd62ea1a 963 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
NYX 0:85b3fd62ea1a 964 } \
NYX 0:85b3fd62ea1a 965 else \
NYX 0:85b3fd62ea1a 966 { \
NYX 0:85b3fd62ea1a 967 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
NYX 0:85b3fd62ea1a 968 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
NYX 0:85b3fd62ea1a 969 } \
NYX 0:85b3fd62ea1a 970 } while(0U)
NYX 0:85b3fd62ea1a 971 /**
NYX 0:85b3fd62ea1a 972 * @}
NYX 0:85b3fd62ea1a 973 */
NYX 0:85b3fd62ea1a 974
NYX 0:85b3fd62ea1a 975 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
NYX 0:85b3fd62ea1a 976 * @{
NYX 0:85b3fd62ea1a 977 */
NYX 0:85b3fd62ea1a 978
NYX 0:85b3fd62ea1a 979 /** @brief Macros to enable or disable the RTC clock.
NYX 0:85b3fd62ea1a 980 * @note These macros must be used only after the RTC clock source was selected.
NYX 0:85b3fd62ea1a 981 */
NYX 0:85b3fd62ea1a 982 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
NYX 0:85b3fd62ea1a 983 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
NYX 0:85b3fd62ea1a 984
NYX 0:85b3fd62ea1a 985 /** @brief Macros to configure the RTC clock (RTCCLK).
NYX 0:85b3fd62ea1a 986 * @note As the RTC clock configuration bits are in the Backup domain and write
NYX 0:85b3fd62ea1a 987 * access is denied to this domain after reset, you have to enable write
NYX 0:85b3fd62ea1a 988 * access using the Power Backup Access macro before to configure
NYX 0:85b3fd62ea1a 989 * the RTC clock source (to be done once after reset).
NYX 0:85b3fd62ea1a 990 * @note Once the RTC clock is configured it can't be changed unless the
NYX 0:85b3fd62ea1a 991 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
NYX 0:85b3fd62ea1a 992 * a Power On Reset (POR).
NYX 0:85b3fd62ea1a 993 * @param __RTCCLKSource__: specifies the RTC clock source.
NYX 0:85b3fd62ea1a 994 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 995 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
NYX 0:85b3fd62ea1a 996 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
NYX 0:85b3fd62ea1a 997 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
NYX 0:85b3fd62ea1a 998 * as RTC clock, where x:[2,31]
NYX 0:85b3fd62ea1a 999 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
NYX 0:85b3fd62ea1a 1000 * work in STOP and STANDBY modes, and can be used as wake-up source.
NYX 0:85b3fd62ea1a 1001 * However, when the HSE clock is used as RTC clock source, the RTC
NYX 0:85b3fd62ea1a 1002 * cannot be used in STOP and STANDBY modes.
NYX 0:85b3fd62ea1a 1003 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
NYX 0:85b3fd62ea1a 1004 * RTC clock source).
NYX 0:85b3fd62ea1a 1005 */
NYX 0:85b3fd62ea1a 1006 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
NYX 0:85b3fd62ea1a 1007 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
NYX 0:85b3fd62ea1a 1008
NYX 0:85b3fd62ea1a 1009 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
NYX 0:85b3fd62ea1a 1010 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
NYX 0:85b3fd62ea1a 1011 } while(0U)
NYX 0:85b3fd62ea1a 1012
NYX 0:85b3fd62ea1a 1013 /** @brief Macros to force or release the Backup domain reset.
NYX 0:85b3fd62ea1a 1014 * @note This function resets the RTC peripheral (including the backup registers)
NYX 0:85b3fd62ea1a 1015 * and the RTC clock source selection in RCC_CSR register.
NYX 0:85b3fd62ea1a 1016 * @note The BKPSRAM is not affected by this reset.
NYX 0:85b3fd62ea1a 1017 */
NYX 0:85b3fd62ea1a 1018 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
NYX 0:85b3fd62ea1a 1019 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
NYX 0:85b3fd62ea1a 1020 /**
NYX 0:85b3fd62ea1a 1021 * @}
NYX 0:85b3fd62ea1a 1022 */
NYX 0:85b3fd62ea1a 1023
NYX 0:85b3fd62ea1a 1024 /** @defgroup RCC_PLL_Configuration PLL Configuration
NYX 0:85b3fd62ea1a 1025 * @{
NYX 0:85b3fd62ea1a 1026 */
NYX 0:85b3fd62ea1a 1027
NYX 0:85b3fd62ea1a 1028 /** @brief Macros to enable or disable the main PLL.
NYX 0:85b3fd62ea1a 1029 * @note After enabling the main PLL, the application software should wait on
NYX 0:85b3fd62ea1a 1030 * PLLRDY flag to be set indicating that PLL clock is stable and can
NYX 0:85b3fd62ea1a 1031 * be used as system clock source.
NYX 0:85b3fd62ea1a 1032 * @note The main PLL can not be disabled if it is used as system clock source
NYX 0:85b3fd62ea1a 1033 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
NYX 0:85b3fd62ea1a 1034 */
NYX 0:85b3fd62ea1a 1035 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
NYX 0:85b3fd62ea1a 1036 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
NYX 0:85b3fd62ea1a 1037
NYX 0:85b3fd62ea1a 1038 /** @brief Macro to configure the PLL clock source.
NYX 0:85b3fd62ea1a 1039 * @note This function must be used only when the main PLL is disabled.
NYX 0:85b3fd62ea1a 1040 * @param __PLLSOURCE__: specifies the PLL entry clock source.
NYX 0:85b3fd62ea1a 1041 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1042 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
NYX 0:85b3fd62ea1a 1043 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
NYX 0:85b3fd62ea1a 1044 *
NYX 0:85b3fd62ea1a 1045 */
NYX 0:85b3fd62ea1a 1046 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
NYX 0:85b3fd62ea1a 1047
NYX 0:85b3fd62ea1a 1048 /** @brief Macro to configure the PLL multiplication factor.
NYX 0:85b3fd62ea1a 1049 * @note This function must be used only when the main PLL is disabled.
NYX 0:85b3fd62ea1a 1050 * @param __PLLM__: specifies the division factor for PLL VCO input clock
NYX 0:85b3fd62ea1a 1051 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
NYX 0:85b3fd62ea1a 1052 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
NYX 0:85b3fd62ea1a 1053 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
NYX 0:85b3fd62ea1a 1054 * of 2 MHz to limit PLL jitter.
NYX 0:85b3fd62ea1a 1055 *
NYX 0:85b3fd62ea1a 1056 */
NYX 0:85b3fd62ea1a 1057 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
NYX 0:85b3fd62ea1a 1058 /**
NYX 0:85b3fd62ea1a 1059 * @}
NYX 0:85b3fd62ea1a 1060 */
NYX 0:85b3fd62ea1a 1061
NYX 0:85b3fd62ea1a 1062 /** @defgroup RCC_Get_Clock_source Get Clock source
NYX 0:85b3fd62ea1a 1063 * @{
NYX 0:85b3fd62ea1a 1064 */
NYX 0:85b3fd62ea1a 1065 /**
NYX 0:85b3fd62ea1a 1066 * @brief Macro to configure the system clock source.
NYX 0:85b3fd62ea1a 1067 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
NYX 0:85b3fd62ea1a 1068 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1069 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
NYX 0:85b3fd62ea1a 1070 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
NYX 0:85b3fd62ea1a 1071 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
NYX 0:85b3fd62ea1a 1072 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
NYX 0:85b3fd62ea1a 1073 * parameter is available only for STM32F446xx devices.
NYX 0:85b3fd62ea1a 1074 */
NYX 0:85b3fd62ea1a 1075 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
NYX 0:85b3fd62ea1a 1076
NYX 0:85b3fd62ea1a 1077 /** @brief Macro to get the clock source used as system clock.
NYX 0:85b3fd62ea1a 1078 * @retval The clock source used as system clock. The returned value can be one
NYX 0:85b3fd62ea1a 1079 * of the following:
NYX 0:85b3fd62ea1a 1080 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
NYX 0:85b3fd62ea1a 1081 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
NYX 0:85b3fd62ea1a 1082 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
NYX 0:85b3fd62ea1a 1083 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
NYX 0:85b3fd62ea1a 1084 * is available only for STM32F446xx devices.
NYX 0:85b3fd62ea1a 1085 */
NYX 0:85b3fd62ea1a 1086 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
NYX 0:85b3fd62ea1a 1087
NYX 0:85b3fd62ea1a 1088 /** @brief Macro to get the oscillator used as PLL clock source.
NYX 0:85b3fd62ea1a 1089 * @retval The oscillator used as PLL clock source. The returned value can be one
NYX 0:85b3fd62ea1a 1090 * of the following:
NYX 0:85b3fd62ea1a 1091 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
NYX 0:85b3fd62ea1a 1092 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
NYX 0:85b3fd62ea1a 1093 */
NYX 0:85b3fd62ea1a 1094 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
NYX 0:85b3fd62ea1a 1095 /**
NYX 0:85b3fd62ea1a 1096 * @}
NYX 0:85b3fd62ea1a 1097 */
NYX 0:85b3fd62ea1a 1098
NYX 0:85b3fd62ea1a 1099 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
NYX 0:85b3fd62ea1a 1100 * @{
NYX 0:85b3fd62ea1a 1101 */
NYX 0:85b3fd62ea1a 1102
NYX 0:85b3fd62ea1a 1103 /** @brief Macro to configure the MCO1 clock.
NYX 0:85b3fd62ea1a 1104 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
NYX 0:85b3fd62ea1a 1105 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1106 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
NYX 0:85b3fd62ea1a 1107 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
NYX 0:85b3fd62ea1a 1108 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
NYX 0:85b3fd62ea1a 1109 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
NYX 0:85b3fd62ea1a 1110 * @param __MCODIV__ specifies the MCO clock prescaler.
NYX 0:85b3fd62ea1a 1111 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1112 * @arg RCC_MCODIV_1: no division applied to MCOx clock
NYX 0:85b3fd62ea1a 1113 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
NYX 0:85b3fd62ea1a 1114 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
NYX 0:85b3fd62ea1a 1115 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
NYX 0:85b3fd62ea1a 1116 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
NYX 0:85b3fd62ea1a 1117 */
NYX 0:85b3fd62ea1a 1118 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
NYX 0:85b3fd62ea1a 1119 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
NYX 0:85b3fd62ea1a 1120
NYX 0:85b3fd62ea1a 1121 /** @brief Macro to configure the MCO2 clock.
NYX 0:85b3fd62ea1a 1122 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
NYX 0:85b3fd62ea1a 1123 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1124 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
NYX 0:85b3fd62ea1a 1125 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
NYX 0:85b3fd62ea1a 1126 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
NYX 0:85b3fd62ea1a 1127 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
NYX 0:85b3fd62ea1a 1128 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
NYX 0:85b3fd62ea1a 1129 * @param __MCODIV__ specifies the MCO clock prescaler.
NYX 0:85b3fd62ea1a 1130 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1131 * @arg RCC_MCODIV_1: no division applied to MCOx clock
NYX 0:85b3fd62ea1a 1132 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
NYX 0:85b3fd62ea1a 1133 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
NYX 0:85b3fd62ea1a 1134 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
NYX 0:85b3fd62ea1a 1135 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
NYX 0:85b3fd62ea1a 1136 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
NYX 0:85b3fd62ea1a 1137 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
NYX 0:85b3fd62ea1a 1138 */
NYX 0:85b3fd62ea1a 1139 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
NYX 0:85b3fd62ea1a 1140 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
NYX 0:85b3fd62ea1a 1141 /**
NYX 0:85b3fd62ea1a 1142 * @}
NYX 0:85b3fd62ea1a 1143 */
NYX 0:85b3fd62ea1a 1144
NYX 0:85b3fd62ea1a 1145 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
NYX 0:85b3fd62ea1a 1146 * @brief macros to manage the specified RCC Flags and interrupts.
NYX 0:85b3fd62ea1a 1147 * @{
NYX 0:85b3fd62ea1a 1148 */
NYX 0:85b3fd62ea1a 1149
NYX 0:85b3fd62ea1a 1150 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
NYX 0:85b3fd62ea1a 1151 * the selected interrupts).
NYX 0:85b3fd62ea1a 1152 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
NYX 0:85b3fd62ea1a 1153 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 1154 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
NYX 0:85b3fd62ea1a 1155 * @arg RCC_IT_LSERDY: LSE ready interrupt.
NYX 0:85b3fd62ea1a 1156 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
NYX 0:85b3fd62ea1a 1157 * @arg RCC_IT_HSERDY: HSE ready interrupt.
NYX 0:85b3fd62ea1a 1158 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
NYX 0:85b3fd62ea1a 1159 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
NYX 0:85b3fd62ea1a 1160 */
NYX 0:85b3fd62ea1a 1161 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
NYX 0:85b3fd62ea1a 1162
NYX 0:85b3fd62ea1a 1163 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
NYX 0:85b3fd62ea1a 1164 * the selected interrupts).
NYX 0:85b3fd62ea1a 1165 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
NYX 0:85b3fd62ea1a 1166 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 1167 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
NYX 0:85b3fd62ea1a 1168 * @arg RCC_IT_LSERDY: LSE ready interrupt.
NYX 0:85b3fd62ea1a 1169 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
NYX 0:85b3fd62ea1a 1170 * @arg RCC_IT_HSERDY: HSE ready interrupt.
NYX 0:85b3fd62ea1a 1171 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
NYX 0:85b3fd62ea1a 1172 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
NYX 0:85b3fd62ea1a 1173 */
NYX 0:85b3fd62ea1a 1174 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
NYX 0:85b3fd62ea1a 1175
NYX 0:85b3fd62ea1a 1176 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
NYX 0:85b3fd62ea1a 1177 * bits to clear the selected interrupt pending bits.
NYX 0:85b3fd62ea1a 1178 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
NYX 0:85b3fd62ea1a 1179 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 1180 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
NYX 0:85b3fd62ea1a 1181 * @arg RCC_IT_LSERDY: LSE ready interrupt.
NYX 0:85b3fd62ea1a 1182 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
NYX 0:85b3fd62ea1a 1183 * @arg RCC_IT_HSERDY: HSE ready interrupt.
NYX 0:85b3fd62ea1a 1184 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
NYX 0:85b3fd62ea1a 1185 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
NYX 0:85b3fd62ea1a 1186 * @arg RCC_IT_CSS: Clock Security System interrupt
NYX 0:85b3fd62ea1a 1187 */
NYX 0:85b3fd62ea1a 1188 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
NYX 0:85b3fd62ea1a 1189
NYX 0:85b3fd62ea1a 1190 /** @brief Check the RCC's interrupt has occurred or not.
NYX 0:85b3fd62ea1a 1191 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
NYX 0:85b3fd62ea1a 1192 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1193 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
NYX 0:85b3fd62ea1a 1194 * @arg RCC_IT_LSERDY: LSE ready interrupt.
NYX 0:85b3fd62ea1a 1195 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
NYX 0:85b3fd62ea1a 1196 * @arg RCC_IT_HSERDY: HSE ready interrupt.
NYX 0:85b3fd62ea1a 1197 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
NYX 0:85b3fd62ea1a 1198 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
NYX 0:85b3fd62ea1a 1199 * @arg RCC_IT_CSS: Clock Security System interrupt
NYX 0:85b3fd62ea1a 1200 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
NYX 0:85b3fd62ea1a 1201 */
NYX 0:85b3fd62ea1a 1202 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
NYX 0:85b3fd62ea1a 1203
NYX 0:85b3fd62ea1a 1204 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
NYX 0:85b3fd62ea1a 1205 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
NYX 0:85b3fd62ea1a 1206 */
NYX 0:85b3fd62ea1a 1207 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
NYX 0:85b3fd62ea1a 1208
NYX 0:85b3fd62ea1a 1209 /** @brief Check RCC flag is set or not.
NYX 0:85b3fd62ea1a 1210 * @param __FLAG__: specifies the flag to check.
NYX 0:85b3fd62ea1a 1211 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1212 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
NYX 0:85b3fd62ea1a 1213 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
NYX 0:85b3fd62ea1a 1214 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
NYX 0:85b3fd62ea1a 1215 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
NYX 0:85b3fd62ea1a 1216 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
NYX 0:85b3fd62ea1a 1217 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
NYX 0:85b3fd62ea1a 1218 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
NYX 0:85b3fd62ea1a 1219 * @arg RCC_FLAG_PINRST: Pin reset.
NYX 0:85b3fd62ea1a 1220 * @arg RCC_FLAG_PORRST: POR/PDR reset.
NYX 0:85b3fd62ea1a 1221 * @arg RCC_FLAG_SFTRST: Software reset.
NYX 0:85b3fd62ea1a 1222 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
NYX 0:85b3fd62ea1a 1223 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
NYX 0:85b3fd62ea1a 1224 * @arg RCC_FLAG_LPWRRST: Low Power reset.
NYX 0:85b3fd62ea1a 1225 * @retval The new state of __FLAG__ (TRUE or FALSE).
NYX 0:85b3fd62ea1a 1226 */
NYX 0:85b3fd62ea1a 1227 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
NYX 0:85b3fd62ea1a 1228 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
NYX 0:85b3fd62ea1a 1229
NYX 0:85b3fd62ea1a 1230 /**
NYX 0:85b3fd62ea1a 1231 * @}
NYX 0:85b3fd62ea1a 1232 */
NYX 0:85b3fd62ea1a 1233
NYX 0:85b3fd62ea1a 1234 /**
NYX 0:85b3fd62ea1a 1235 * @}
NYX 0:85b3fd62ea1a 1236 */
NYX 0:85b3fd62ea1a 1237
NYX 0:85b3fd62ea1a 1238 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1239 /** @addtogroup RCC_Exported_Functions
NYX 0:85b3fd62ea1a 1240 * @{
NYX 0:85b3fd62ea1a 1241 */
NYX 0:85b3fd62ea1a 1242
NYX 0:85b3fd62ea1a 1243 /** @addtogroup RCC_Exported_Functions_Group1
NYX 0:85b3fd62ea1a 1244 * @{
NYX 0:85b3fd62ea1a 1245 */
NYX 0:85b3fd62ea1a 1246 /* Initialization and de-initialization functions ******************************/
NYX 0:85b3fd62ea1a 1247 void HAL_RCC_DeInit(void);
NYX 0:85b3fd62ea1a 1248 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
NYX 0:85b3fd62ea1a 1249 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
NYX 0:85b3fd62ea1a 1250 /**
NYX 0:85b3fd62ea1a 1251 * @}
NYX 0:85b3fd62ea1a 1252 */
NYX 0:85b3fd62ea1a 1253
NYX 0:85b3fd62ea1a 1254 /** @addtogroup RCC_Exported_Functions_Group2
NYX 0:85b3fd62ea1a 1255 * @{
NYX 0:85b3fd62ea1a 1256 */
NYX 0:85b3fd62ea1a 1257 /* Peripheral Control functions ************************************************/
NYX 0:85b3fd62ea1a 1258 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
NYX 0:85b3fd62ea1a 1259 void HAL_RCC_EnableCSS(void);
NYX 0:85b3fd62ea1a 1260 void HAL_RCC_DisableCSS(void);
NYX 0:85b3fd62ea1a 1261 uint32_t HAL_RCC_GetSysClockFreq(void);
NYX 0:85b3fd62ea1a 1262 uint32_t HAL_RCC_GetHCLKFreq(void);
NYX 0:85b3fd62ea1a 1263 uint32_t HAL_RCC_GetPCLK1Freq(void);
NYX 0:85b3fd62ea1a 1264 uint32_t HAL_RCC_GetPCLK2Freq(void);
NYX 0:85b3fd62ea1a 1265 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
NYX 0:85b3fd62ea1a 1266 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
NYX 0:85b3fd62ea1a 1267
NYX 0:85b3fd62ea1a 1268 /* CSS NMI IRQ handler */
NYX 0:85b3fd62ea1a 1269 void HAL_RCC_NMI_IRQHandler(void);
NYX 0:85b3fd62ea1a 1270
NYX 0:85b3fd62ea1a 1271 /* User Callbacks in non blocking mode (IT mode) */
NYX 0:85b3fd62ea1a 1272 void HAL_RCC_CSSCallback(void);
NYX 0:85b3fd62ea1a 1273
NYX 0:85b3fd62ea1a 1274 /**
NYX 0:85b3fd62ea1a 1275 * @}
NYX 0:85b3fd62ea1a 1276 */
NYX 0:85b3fd62ea1a 1277
NYX 0:85b3fd62ea1a 1278 /**
NYX 0:85b3fd62ea1a 1279 * @}
NYX 0:85b3fd62ea1a 1280 */
NYX 0:85b3fd62ea1a 1281
NYX 0:85b3fd62ea1a 1282 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1283 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1284 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1285 /** @defgroup RCC_Private_Constants RCC Private Constants
NYX 0:85b3fd62ea1a 1286 * @{
NYX 0:85b3fd62ea1a 1287 */
NYX 0:85b3fd62ea1a 1288
NYX 0:85b3fd62ea1a 1289 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
NYX 0:85b3fd62ea1a 1290 * @brief RCC registers bit address in the alias region
NYX 0:85b3fd62ea1a 1291 * @{
NYX 0:85b3fd62ea1a 1292 */
NYX 0:85b3fd62ea1a 1293 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
NYX 0:85b3fd62ea1a 1294 /* --- CR Register ---*/
NYX 0:85b3fd62ea1a 1295 /* Alias word address of HSION bit */
NYX 0:85b3fd62ea1a 1296 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
NYX 0:85b3fd62ea1a 1297 #define RCC_HSION_BIT_NUMBER 0x00U
NYX 0:85b3fd62ea1a 1298 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 1299 /* Alias word address of CSSON bit */
NYX 0:85b3fd62ea1a 1300 #define RCC_CSSON_BIT_NUMBER 0x13U
NYX 0:85b3fd62ea1a 1301 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 1302 /* Alias word address of PLLON bit */
NYX 0:85b3fd62ea1a 1303 #define RCC_PLLON_BIT_NUMBER 0x18U
NYX 0:85b3fd62ea1a 1304 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 1305
NYX 0:85b3fd62ea1a 1306 /* --- BDCR Register ---*/
NYX 0:85b3fd62ea1a 1307 /* Alias word address of RTCEN bit */
NYX 0:85b3fd62ea1a 1308 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
NYX 0:85b3fd62ea1a 1309 #define RCC_RTCEN_BIT_NUMBER 0x0FU
NYX 0:85b3fd62ea1a 1310 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 1311 /* Alias word address of BDRST bit */
NYX 0:85b3fd62ea1a 1312 #define RCC_BDRST_BIT_NUMBER 0x10U
NYX 0:85b3fd62ea1a 1313 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 1314
NYX 0:85b3fd62ea1a 1315 /* --- CSR Register ---*/
NYX 0:85b3fd62ea1a 1316 /* Alias word address of LSION bit */
NYX 0:85b3fd62ea1a 1317 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
NYX 0:85b3fd62ea1a 1318 #define RCC_LSION_BIT_NUMBER 0x00U
NYX 0:85b3fd62ea1a 1319 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 1320
NYX 0:85b3fd62ea1a 1321 /* CR register byte 3 (Bits[23:16]) base address */
NYX 0:85b3fd62ea1a 1322 #define RCC_CR_BYTE2_ADDRESS 0x40023802U
NYX 0:85b3fd62ea1a 1323
NYX 0:85b3fd62ea1a 1324 /* CIR register byte 2 (Bits[15:8]) base address */
NYX 0:85b3fd62ea1a 1325 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
NYX 0:85b3fd62ea1a 1326
NYX 0:85b3fd62ea1a 1327 /* CIR register byte 3 (Bits[23:16]) base address */
NYX 0:85b3fd62ea1a 1328 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
NYX 0:85b3fd62ea1a 1329
NYX 0:85b3fd62ea1a 1330 /* BDCR register base address */
NYX 0:85b3fd62ea1a 1331 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
NYX 0:85b3fd62ea1a 1332
NYX 0:85b3fd62ea1a 1333 #define RCC_DBP_TIMEOUT_VALUE 2U
NYX 0:85b3fd62ea1a 1334 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
NYX 0:85b3fd62ea1a 1335
NYX 0:85b3fd62ea1a 1336 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
NYX 0:85b3fd62ea1a 1337 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */
NYX 0:85b3fd62ea1a 1338 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */
NYX 0:85b3fd62ea1a 1339
NYX 0:85b3fd62ea1a 1340 /**
NYX 0:85b3fd62ea1a 1341 * @}
NYX 0:85b3fd62ea1a 1342 */
NYX 0:85b3fd62ea1a 1343
NYX 0:85b3fd62ea1a 1344 /**
NYX 0:85b3fd62ea1a 1345 * @}
NYX 0:85b3fd62ea1a 1346 */
NYX 0:85b3fd62ea1a 1347
NYX 0:85b3fd62ea1a 1348 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1349 /** @defgroup RCC_Private_Macros RCC Private Macros
NYX 0:85b3fd62ea1a 1350 * @{
NYX 0:85b3fd62ea1a 1351 */
NYX 0:85b3fd62ea1a 1352
NYX 0:85b3fd62ea1a 1353 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
NYX 0:85b3fd62ea1a 1354 * @{
NYX 0:85b3fd62ea1a 1355 */
NYX 0:85b3fd62ea1a 1356 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
NYX 0:85b3fd62ea1a 1357
NYX 0:85b3fd62ea1a 1358 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
NYX 0:85b3fd62ea1a 1359 ((HSE) == RCC_HSE_BYPASS))
NYX 0:85b3fd62ea1a 1360
NYX 0:85b3fd62ea1a 1361 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
NYX 0:85b3fd62ea1a 1362 ((LSE) == RCC_LSE_BYPASS))
NYX 0:85b3fd62ea1a 1363
NYX 0:85b3fd62ea1a 1364 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
NYX 0:85b3fd62ea1a 1365
NYX 0:85b3fd62ea1a 1366 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
NYX 0:85b3fd62ea1a 1367
NYX 0:85b3fd62ea1a 1368 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
NYX 0:85b3fd62ea1a 1369
NYX 0:85b3fd62ea1a 1370 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
NYX 0:85b3fd62ea1a 1371 ((SOURCE) == RCC_PLLSOURCE_HSE))
NYX 0:85b3fd62ea1a 1372
NYX 0:85b3fd62ea1a 1373 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
NYX 0:85b3fd62ea1a 1374 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
NYX 0:85b3fd62ea1a 1375 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
NYX 0:85b3fd62ea1a 1376 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
NYX 0:85b3fd62ea1a 1377
NYX 0:85b3fd62ea1a 1378 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
NYX 0:85b3fd62ea1a 1379 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
NYX 0:85b3fd62ea1a 1380 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
NYX 0:85b3fd62ea1a 1381 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
NYX 0:85b3fd62ea1a 1382 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
NYX 0:85b3fd62ea1a 1383 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
NYX 0:85b3fd62ea1a 1384 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
NYX 0:85b3fd62ea1a 1385 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
NYX 0:85b3fd62ea1a 1386 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
NYX 0:85b3fd62ea1a 1387 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
NYX 0:85b3fd62ea1a 1388 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
NYX 0:85b3fd62ea1a 1389 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
NYX 0:85b3fd62ea1a 1390 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
NYX 0:85b3fd62ea1a 1391 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
NYX 0:85b3fd62ea1a 1392 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
NYX 0:85b3fd62ea1a 1393 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
NYX 0:85b3fd62ea1a 1394 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
NYX 0:85b3fd62ea1a 1395 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
NYX 0:85b3fd62ea1a 1396 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
NYX 0:85b3fd62ea1a 1397 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
NYX 0:85b3fd62ea1a 1398 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
NYX 0:85b3fd62ea1a 1399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
NYX 0:85b3fd62ea1a 1400 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
NYX 0:85b3fd62ea1a 1401 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
NYX 0:85b3fd62ea1a 1402 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
NYX 0:85b3fd62ea1a 1403 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
NYX 0:85b3fd62ea1a 1404 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
NYX 0:85b3fd62ea1a 1405 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
NYX 0:85b3fd62ea1a 1406 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
NYX 0:85b3fd62ea1a 1407 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
NYX 0:85b3fd62ea1a 1408 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
NYX 0:85b3fd62ea1a 1409 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
NYX 0:85b3fd62ea1a 1410
NYX 0:85b3fd62ea1a 1411 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
NYX 0:85b3fd62ea1a 1412
NYX 0:85b3fd62ea1a 1413 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
NYX 0:85b3fd62ea1a 1414
NYX 0:85b3fd62ea1a 1415 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
NYX 0:85b3fd62ea1a 1416
NYX 0:85b3fd62ea1a 1417 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
NYX 0:85b3fd62ea1a 1418 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
NYX 0:85b3fd62ea1a 1419 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
NYX 0:85b3fd62ea1a 1420 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
NYX 0:85b3fd62ea1a 1421 ((HCLK) == RCC_SYSCLK_DIV512))
NYX 0:85b3fd62ea1a 1422
NYX 0:85b3fd62ea1a 1423 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
NYX 0:85b3fd62ea1a 1424
NYX 0:85b3fd62ea1a 1425 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
NYX 0:85b3fd62ea1a 1426 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
NYX 0:85b3fd62ea1a 1427 ((PCLK) == RCC_HCLK_DIV16))
NYX 0:85b3fd62ea1a 1428
NYX 0:85b3fd62ea1a 1429 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
NYX 0:85b3fd62ea1a 1430
NYX 0:85b3fd62ea1a 1431 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
NYX 0:85b3fd62ea1a 1432 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
NYX 0:85b3fd62ea1a 1433
NYX 0:85b3fd62ea1a 1434 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
NYX 0:85b3fd62ea1a 1435 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
NYX 0:85b3fd62ea1a 1436 ((DIV) == RCC_MCODIV_5))
NYX 0:85b3fd62ea1a 1437 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
NYX 0:85b3fd62ea1a 1438
NYX 0:85b3fd62ea1a 1439 /**
NYX 0:85b3fd62ea1a 1440 * @}
NYX 0:85b3fd62ea1a 1441 */
NYX 0:85b3fd62ea1a 1442
NYX 0:85b3fd62ea1a 1443 /**
NYX 0:85b3fd62ea1a 1444 * @}
NYX 0:85b3fd62ea1a 1445 */
NYX 0:85b3fd62ea1a 1446
NYX 0:85b3fd62ea1a 1447 /**
NYX 0:85b3fd62ea1a 1448 * @}
NYX 0:85b3fd62ea1a 1449 */
NYX 0:85b3fd62ea1a 1450
NYX 0:85b3fd62ea1a 1451 /**
NYX 0:85b3fd62ea1a 1452 * @}
NYX 0:85b3fd62ea1a 1453 */
NYX 0:85b3fd62ea1a 1454
NYX 0:85b3fd62ea1a 1455 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 1456 }
NYX 0:85b3fd62ea1a 1457 #endif
NYX 0:85b3fd62ea1a 1458
NYX 0:85b3fd62ea1a 1459 #endif /* __STM32F4xx_HAL_RCC_H */
NYX 0:85b3fd62ea1a 1460
NYX 0:85b3fd62ea1a 1461 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/