Takaaki Numai / mbed-dev

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Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_rcc.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief RCC HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
NYX 0:85b3fd62ea1a 10 * + Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 11 * + Peripheral Control functions
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 @verbatim
NYX 0:85b3fd62ea1a 14 ==============================================================================
NYX 0:85b3fd62ea1a 15 ##### RCC specific features #####
NYX 0:85b3fd62ea1a 16 ==============================================================================
NYX 0:85b3fd62ea1a 17 [..]
NYX 0:85b3fd62ea1a 18 After reset the device is running from Internal High Speed oscillator
NYX 0:85b3fd62ea1a 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
NYX 0:85b3fd62ea1a 20 and I-Cache are disabled, and all peripherals are off except internal
NYX 0:85b3fd62ea1a 21 SRAM, Flash and JTAG.
NYX 0:85b3fd62ea1a 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
NYX 0:85b3fd62ea1a 23 all peripherals mapped on these busses are running at HSI speed.
NYX 0:85b3fd62ea1a 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
NYX 0:85b3fd62ea1a 25 (+) All GPIOs are in input floating state, except the JTAG pins which
NYX 0:85b3fd62ea1a 26 are assigned to be used for debug purpose.
NYX 0:85b3fd62ea1a 27
NYX 0:85b3fd62ea1a 28 [..]
NYX 0:85b3fd62ea1a 29 Once the device started from reset, the user application has to:
NYX 0:85b3fd62ea1a 30 (+) Configure the clock source to be used to drive the System clock
NYX 0:85b3fd62ea1a 31 (if the application needs higher frequency/performance)
NYX 0:85b3fd62ea1a 32 (+) Configure the System clock frequency and Flash settings
NYX 0:85b3fd62ea1a 33 (+) Configure the AHB and APB busses prescalers
NYX 0:85b3fd62ea1a 34 (+) Enable the clock for the peripheral(s) to be used
NYX 0:85b3fd62ea1a 35 (+) Configure the clock source(s) for peripherals which clocks are not
NYX 0:85b3fd62ea1a 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 ##### RCC Limitations #####
NYX 0:85b3fd62ea1a 39 ==============================================================================
NYX 0:85b3fd62ea1a 40 [..]
NYX 0:85b3fd62ea1a 41 A delay between an RCC peripheral clock enable and the effective peripheral
NYX 0:85b3fd62ea1a 42 enabling should be taken into account in order to manage the peripheral read/write
NYX 0:85b3fd62ea1a 43 from/to registers.
NYX 0:85b3fd62ea1a 44 (+) This delay depends on the peripheral mapping.
NYX 0:85b3fd62ea1a 45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
NYX 0:85b3fd62ea1a 46 after the clock enable bit is set on the hardware register
NYX 0:85b3fd62ea1a 47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
NYX 0:85b3fd62ea1a 48 after the clock enable bit is set on the hardware register
NYX 0:85b3fd62ea1a 49
NYX 0:85b3fd62ea1a 50 [..]
NYX 0:85b3fd62ea1a 51 Implemented Workaround:
NYX 0:85b3fd62ea1a 52 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
NYX 0:85b3fd62ea1a 53 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 @endverbatim
NYX 0:85b3fd62ea1a 56 ******************************************************************************
NYX 0:85b3fd62ea1a 57 * @attention
NYX 0:85b3fd62ea1a 58 *
NYX 0:85b3fd62ea1a 59 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 60 *
NYX 0:85b3fd62ea1a 61 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 62 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 63 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 64 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 65 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 66 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 67 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 68 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 69 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 70 * without specific prior written permission.
NYX 0:85b3fd62ea1a 71 *
NYX 0:85b3fd62ea1a 72 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 73 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 75 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 79 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 80 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 81 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 82 *
NYX 0:85b3fd62ea1a 83 ******************************************************************************
NYX 0:85b3fd62ea1a 84 */
NYX 0:85b3fd62ea1a 85
NYX 0:85b3fd62ea1a 86 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 87 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 88
NYX 0:85b3fd62ea1a 89 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 90 * @{
NYX 0:85b3fd62ea1a 91 */
NYX 0:85b3fd62ea1a 92
NYX 0:85b3fd62ea1a 93 /** @defgroup RCC RCC
NYX 0:85b3fd62ea1a 94 * @brief RCC HAL module driver
NYX 0:85b3fd62ea1a 95 * @{
NYX 0:85b3fd62ea1a 96 */
NYX 0:85b3fd62ea1a 97
NYX 0:85b3fd62ea1a 98 #ifdef HAL_RCC_MODULE_ENABLED
NYX 0:85b3fd62ea1a 99
NYX 0:85b3fd62ea1a 100 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 101 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 102 /** @addtogroup RCC_Private_Constants
NYX 0:85b3fd62ea1a 103 * @{
NYX 0:85b3fd62ea1a 104 */
NYX 0:85b3fd62ea1a 105 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
NYX 0:85b3fd62ea1a 106
NYX 0:85b3fd62ea1a 107 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 108 #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
NYX 0:85b3fd62ea1a 109 #define MCO1_GPIO_PORT GPIOA
NYX 0:85b3fd62ea1a 110 #define MCO1_PIN GPIO_PIN_8
NYX 0:85b3fd62ea1a 111
NYX 0:85b3fd62ea1a 112 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
NYX 0:85b3fd62ea1a 113 #define MCO2_GPIO_PORT GPIOC
NYX 0:85b3fd62ea1a 114 #define MCO2_PIN GPIO_PIN_9
NYX 0:85b3fd62ea1a 115 /**
NYX 0:85b3fd62ea1a 116 * @}
NYX 0:85b3fd62ea1a 117 */
NYX 0:85b3fd62ea1a 118
NYX 0:85b3fd62ea1a 119 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 120 /** @defgroup RCC_Private_Variables RCC Private Variables
NYX 0:85b3fd62ea1a 121 * @{
NYX 0:85b3fd62ea1a 122 */
NYX 0:85b3fd62ea1a 123 /**
NYX 0:85b3fd62ea1a 124 * @}
NYX 0:85b3fd62ea1a 125 */
NYX 0:85b3fd62ea1a 126 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 127 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 128
NYX 0:85b3fd62ea1a 129 /** @defgroup RCC_Exported_Functions RCC Exported Functions
NYX 0:85b3fd62ea1a 130 * @{
NYX 0:85b3fd62ea1a 131 */
NYX 0:85b3fd62ea1a 132
NYX 0:85b3fd62ea1a 133 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 134 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 135 *
NYX 0:85b3fd62ea1a 136 @verbatim
NYX 0:85b3fd62ea1a 137 ===============================================================================
NYX 0:85b3fd62ea1a 138 ##### Initialization and de-initialization functions #####
NYX 0:85b3fd62ea1a 139 ===============================================================================
NYX 0:85b3fd62ea1a 140 [..]
NYX 0:85b3fd62ea1a 141 This section provides functions allowing to configure the internal/external oscillators
NYX 0:85b3fd62ea1a 142 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
NYX 0:85b3fd62ea1a 143 and APB2).
NYX 0:85b3fd62ea1a 144
NYX 0:85b3fd62ea1a 145 [..] Internal/external clock and PLL configuration
NYX 0:85b3fd62ea1a 146 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
NYX 0:85b3fd62ea1a 147 the PLL as System clock source.
NYX 0:85b3fd62ea1a 148
NYX 0:85b3fd62ea1a 149 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
NYX 0:85b3fd62ea1a 150 clock source.
NYX 0:85b3fd62ea1a 151
NYX 0:85b3fd62ea1a 152 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
NYX 0:85b3fd62ea1a 153 through the PLL as System clock source. Can be used also as RTC clock source.
NYX 0:85b3fd62ea1a 154
NYX 0:85b3fd62ea1a 155 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
NYX 0:85b3fd62ea1a 156
NYX 0:85b3fd62ea1a 157 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
NYX 0:85b3fd62ea1a 158 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
NYX 0:85b3fd62ea1a 159 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
NYX 0:85b3fd62ea1a 160 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
NYX 0:85b3fd62ea1a 161
NYX 0:85b3fd62ea1a 162 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
NYX 0:85b3fd62ea1a 163 and if a HSE clock failure occurs(HSE used directly or through PLL as System
NYX 0:85b3fd62ea1a 164 clock source), the System clocks automatically switched to HSI and an interrupt
NYX 0:85b3fd62ea1a 165 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
NYX 0:85b3fd62ea1a 166 (Non-Maskable Interrupt) exception vector.
NYX 0:85b3fd62ea1a 167
NYX 0:85b3fd62ea1a 168 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
NYX 0:85b3fd62ea1a 169 clock (through a configurable prescaler) on PA8 pin.
NYX 0:85b3fd62ea1a 170
NYX 0:85b3fd62ea1a 171 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
NYX 0:85b3fd62ea1a 172 clock (through a configurable prescaler) on PC9 pin.
NYX 0:85b3fd62ea1a 173
NYX 0:85b3fd62ea1a 174 [..] System, AHB and APB busses clocks configuration
NYX 0:85b3fd62ea1a 175 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
NYX 0:85b3fd62ea1a 176 HSE and PLL.
NYX 0:85b3fd62ea1a 177 The AHB clock (HCLK) is derived from System clock through configurable
NYX 0:85b3fd62ea1a 178 prescaler and used to clock the CPU, memory and peripherals mapped
NYX 0:85b3fd62ea1a 179 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
NYX 0:85b3fd62ea1a 180 from AHB clock through configurable prescalers and used to clock
NYX 0:85b3fd62ea1a 181 the peripherals mapped on these busses. You can use
NYX 0:85b3fd62ea1a 182 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
NYX 0:85b3fd62ea1a 183
NYX 0:85b3fd62ea1a 184 (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
NYX 0:85b3fd62ea1a 185 frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
NYX 0:85b3fd62ea1a 186 Depending on the device voltage range, the maximum frequency should
NYX 0:85b3fd62ea1a 187 be adapted accordingly (refer to the product datasheets for more details).
NYX 0:85b3fd62ea1a 188
NYX 0:85b3fd62ea1a 189 (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
NYX 0:85b3fd62ea1a 190 the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
NYX 0:85b3fd62ea1a 191 Depending on the device voltage range, the maximum frequency should
NYX 0:85b3fd62ea1a 192 be adapted accordingly (refer to the product datasheets for more details).
NYX 0:85b3fd62ea1a 193
NYX 0:85b3fd62ea1a 194 (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
NYX 0:85b3fd62ea1a 195 PCLK2 84 MHz and PCLK1 42 MHz.
NYX 0:85b3fd62ea1a 196 Depending on the device voltage range, the maximum frequency should
NYX 0:85b3fd62ea1a 197 be adapted accordingly (refer to the product datasheets for more details).
NYX 0:85b3fd62ea1a 198
NYX 0:85b3fd62ea1a 199 (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
NYX 0:85b3fd62ea1a 200 PCLK2 100 MHz and PCLK1 50 MHz.
NYX 0:85b3fd62ea1a 201 Depending on the device voltage range, the maximum frequency should
NYX 0:85b3fd62ea1a 202 be adapted accordingly (refer to the product datasheets for more details).
NYX 0:85b3fd62ea1a 203
NYX 0:85b3fd62ea1a 204 @endverbatim
NYX 0:85b3fd62ea1a 205 * @{
NYX 0:85b3fd62ea1a 206 */
NYX 0:85b3fd62ea1a 207
NYX 0:85b3fd62ea1a 208 /**
NYX 0:85b3fd62ea1a 209 * @brief Resets the RCC clock configuration to the default reset state.
NYX 0:85b3fd62ea1a 210 * @note The default reset state of the clock configuration is given below:
NYX 0:85b3fd62ea1a 211 * - HSI ON and used as system clock source
NYX 0:85b3fd62ea1a 212 * - HSE and PLL OFF
NYX 0:85b3fd62ea1a 213 * - AHB, APB1 and APB2 prescaler set to 1.
NYX 0:85b3fd62ea1a 214 * - CSS, MCO1 and MCO2 OFF
NYX 0:85b3fd62ea1a 215 * - All interrupts disabled
NYX 0:85b3fd62ea1a 216 * @note This function doesn't modify the configuration of the
NYX 0:85b3fd62ea1a 217 * - Peripheral clocks
NYX 0:85b3fd62ea1a 218 * - LSI, LSE and RTC clocks
NYX 0:85b3fd62ea1a 219 * @retval None
NYX 0:85b3fd62ea1a 220 */
NYX 0:85b3fd62ea1a 221 __weak void HAL_RCC_DeInit(void)
NYX 0:85b3fd62ea1a 222 {}
NYX 0:85b3fd62ea1a 223
NYX 0:85b3fd62ea1a 224 /**
NYX 0:85b3fd62ea1a 225 * @brief Initializes the RCC Oscillators according to the specified parameters in the
NYX 0:85b3fd62ea1a 226 * RCC_OscInitTypeDef.
NYX 0:85b3fd62ea1a 227 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
NYX 0:85b3fd62ea1a 228 * contains the configuration information for the RCC Oscillators.
NYX 0:85b3fd62ea1a 229 * @note The PLL is not disabled when used as system clock.
NYX 0:85b3fd62ea1a 230 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
NYX 0:85b3fd62ea1a 231 * supported by this API. User should request a transition to LSE Off
NYX 0:85b3fd62ea1a 232 * first and then LSE On or LSE Bypass.
NYX 0:85b3fd62ea1a 233 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
NYX 0:85b3fd62ea1a 234 * supported by this API. User should request a transition to HSE Off
NYX 0:85b3fd62ea1a 235 * first and then HSE On or HSE Bypass.
NYX 0:85b3fd62ea1a 236 * @retval HAL status
NYX 0:85b3fd62ea1a 237 */
NYX 0:85b3fd62ea1a 238 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
NYX 0:85b3fd62ea1a 239 {
NYX 0:85b3fd62ea1a 240 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 241
NYX 0:85b3fd62ea1a 242 /* Check the parameters */
NYX 0:85b3fd62ea1a 243 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
NYX 0:85b3fd62ea1a 244 /*------------------------------- HSE Configuration ------------------------*/
NYX 0:85b3fd62ea1a 245 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
NYX 0:85b3fd62ea1a 246 {
NYX 0:85b3fd62ea1a 247 /* Check the parameters */
NYX 0:85b3fd62ea1a 248 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
NYX 0:85b3fd62ea1a 249 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
NYX 0:85b3fd62ea1a 250 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
NYX 0:85b3fd62ea1a 251 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
NYX 0:85b3fd62ea1a 252 {
NYX 0:85b3fd62ea1a 253 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
NYX 0:85b3fd62ea1a 254 {
NYX 0:85b3fd62ea1a 255 return HAL_ERROR;
NYX 0:85b3fd62ea1a 256 }
NYX 0:85b3fd62ea1a 257 }
NYX 0:85b3fd62ea1a 258 else
NYX 0:85b3fd62ea1a 259 {
NYX 0:85b3fd62ea1a 260 /* Set the new HSE configuration ---------------------------------------*/
NYX 0:85b3fd62ea1a 261 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
NYX 0:85b3fd62ea1a 262
NYX 0:85b3fd62ea1a 263 /* Check the HSE State */
NYX 0:85b3fd62ea1a 264 if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
NYX 0:85b3fd62ea1a 265 {
NYX 0:85b3fd62ea1a 266 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 267 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 268
NYX 0:85b3fd62ea1a 269 /* Wait till HSE is ready */
NYX 0:85b3fd62ea1a 270 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
NYX 0:85b3fd62ea1a 271 {
NYX 0:85b3fd62ea1a 272 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 273 {
NYX 0:85b3fd62ea1a 274 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 275 }
NYX 0:85b3fd62ea1a 276 }
NYX 0:85b3fd62ea1a 277 }
NYX 0:85b3fd62ea1a 278 else
NYX 0:85b3fd62ea1a 279 {
NYX 0:85b3fd62ea1a 280 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 281 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 282
NYX 0:85b3fd62ea1a 283 /* Wait till HSE is bypassed or disabled */
NYX 0:85b3fd62ea1a 284 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
NYX 0:85b3fd62ea1a 285 {
NYX 0:85b3fd62ea1a 286 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 287 {
NYX 0:85b3fd62ea1a 288 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 289 }
NYX 0:85b3fd62ea1a 290 }
NYX 0:85b3fd62ea1a 291 }
NYX 0:85b3fd62ea1a 292 }
NYX 0:85b3fd62ea1a 293 }
NYX 0:85b3fd62ea1a 294 /*----------------------------- HSI Configuration --------------------------*/
NYX 0:85b3fd62ea1a 295 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
NYX 0:85b3fd62ea1a 296 {
NYX 0:85b3fd62ea1a 297 /* Check the parameters */
NYX 0:85b3fd62ea1a 298 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
NYX 0:85b3fd62ea1a 299 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
NYX 0:85b3fd62ea1a 300
NYX 0:85b3fd62ea1a 301 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
NYX 0:85b3fd62ea1a 302 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
NYX 0:85b3fd62ea1a 303 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
NYX 0:85b3fd62ea1a 304 {
NYX 0:85b3fd62ea1a 305 /* When HSI is used as system clock it will not disabled */
NYX 0:85b3fd62ea1a 306 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
NYX 0:85b3fd62ea1a 307 {
NYX 0:85b3fd62ea1a 308 return HAL_ERROR;
NYX 0:85b3fd62ea1a 309 }
NYX 0:85b3fd62ea1a 310 /* Otherwise, just the calibration is allowed */
NYX 0:85b3fd62ea1a 311 else
NYX 0:85b3fd62ea1a 312 {
NYX 0:85b3fd62ea1a 313 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
NYX 0:85b3fd62ea1a 314 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
NYX 0:85b3fd62ea1a 315 }
NYX 0:85b3fd62ea1a 316 }
NYX 0:85b3fd62ea1a 317 else
NYX 0:85b3fd62ea1a 318 {
NYX 0:85b3fd62ea1a 319 /* Check the HSI State */
NYX 0:85b3fd62ea1a 320 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
NYX 0:85b3fd62ea1a 321 {
NYX 0:85b3fd62ea1a 322 /* Enable the Internal High Speed oscillator (HSI). */
NYX 0:85b3fd62ea1a 323 __HAL_RCC_HSI_ENABLE();
NYX 0:85b3fd62ea1a 324
NYX 0:85b3fd62ea1a 325 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 326 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 327
NYX 0:85b3fd62ea1a 328 /* Wait till HSI is ready */
NYX 0:85b3fd62ea1a 329 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
NYX 0:85b3fd62ea1a 330 {
NYX 0:85b3fd62ea1a 331 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 332 {
NYX 0:85b3fd62ea1a 333 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 334 }
NYX 0:85b3fd62ea1a 335 }
NYX 0:85b3fd62ea1a 336
NYX 0:85b3fd62ea1a 337 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
NYX 0:85b3fd62ea1a 338 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
NYX 0:85b3fd62ea1a 339 }
NYX 0:85b3fd62ea1a 340 else
NYX 0:85b3fd62ea1a 341 {
NYX 0:85b3fd62ea1a 342 /* Disable the Internal High Speed oscillator (HSI). */
NYX 0:85b3fd62ea1a 343 __HAL_RCC_HSI_DISABLE();
NYX 0:85b3fd62ea1a 344
NYX 0:85b3fd62ea1a 345 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 346 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 347
NYX 0:85b3fd62ea1a 348 /* Wait till HSI is ready */
NYX 0:85b3fd62ea1a 349 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
NYX 0:85b3fd62ea1a 350 {
NYX 0:85b3fd62ea1a 351 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 352 {
NYX 0:85b3fd62ea1a 353 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 354 }
NYX 0:85b3fd62ea1a 355 }
NYX 0:85b3fd62ea1a 356 }
NYX 0:85b3fd62ea1a 357 }
NYX 0:85b3fd62ea1a 358 }
NYX 0:85b3fd62ea1a 359 /*------------------------------ LSI Configuration -------------------------*/
NYX 0:85b3fd62ea1a 360 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
NYX 0:85b3fd62ea1a 361 {
NYX 0:85b3fd62ea1a 362 /* Check the parameters */
NYX 0:85b3fd62ea1a 363 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
NYX 0:85b3fd62ea1a 364
NYX 0:85b3fd62ea1a 365 /* Check the LSI State */
NYX 0:85b3fd62ea1a 366 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
NYX 0:85b3fd62ea1a 367 {
NYX 0:85b3fd62ea1a 368 /* Enable the Internal Low Speed oscillator (LSI). */
NYX 0:85b3fd62ea1a 369 __HAL_RCC_LSI_ENABLE();
NYX 0:85b3fd62ea1a 370
NYX 0:85b3fd62ea1a 371 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 372 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 373
NYX 0:85b3fd62ea1a 374 /* Wait till LSI is ready */
NYX 0:85b3fd62ea1a 375 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
NYX 0:85b3fd62ea1a 376 {
NYX 0:85b3fd62ea1a 377 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 378 {
NYX 0:85b3fd62ea1a 379 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 380 }
NYX 0:85b3fd62ea1a 381 }
NYX 0:85b3fd62ea1a 382 }
NYX 0:85b3fd62ea1a 383 else
NYX 0:85b3fd62ea1a 384 {
NYX 0:85b3fd62ea1a 385 /* Disable the Internal Low Speed oscillator (LSI). */
NYX 0:85b3fd62ea1a 386 __HAL_RCC_LSI_DISABLE();
NYX 0:85b3fd62ea1a 387
NYX 0:85b3fd62ea1a 388 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 389 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 390
NYX 0:85b3fd62ea1a 391 /* Wait till LSI is ready */
NYX 0:85b3fd62ea1a 392 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
NYX 0:85b3fd62ea1a 393 {
NYX 0:85b3fd62ea1a 394 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 395 {
NYX 0:85b3fd62ea1a 396 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 397 }
NYX 0:85b3fd62ea1a 398 }
NYX 0:85b3fd62ea1a 399 }
NYX 0:85b3fd62ea1a 400 }
NYX 0:85b3fd62ea1a 401 /*------------------------------ LSE Configuration -------------------------*/
NYX 0:85b3fd62ea1a 402 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
NYX 0:85b3fd62ea1a 403 {
NYX 0:85b3fd62ea1a 404 /* Check the parameters */
NYX 0:85b3fd62ea1a 405 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
NYX 0:85b3fd62ea1a 406
NYX 0:85b3fd62ea1a 407 /* Enable Power Clock*/
NYX 0:85b3fd62ea1a 408 __HAL_RCC_PWR_CLK_ENABLE();
NYX 0:85b3fd62ea1a 409
NYX 0:85b3fd62ea1a 410 /* Enable write access to Backup domain */
NYX 0:85b3fd62ea1a 411 PWR->CR |= PWR_CR_DBP;
NYX 0:85b3fd62ea1a 412
NYX 0:85b3fd62ea1a 413 /* Wait for Backup domain Write protection enable */
NYX 0:85b3fd62ea1a 414 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 415
NYX 0:85b3fd62ea1a 416 while((PWR->CR & PWR_CR_DBP) == RESET)
NYX 0:85b3fd62ea1a 417 {
NYX 0:85b3fd62ea1a 418 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 419 {
NYX 0:85b3fd62ea1a 420 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 421 }
NYX 0:85b3fd62ea1a 422 }
NYX 0:85b3fd62ea1a 423
NYX 0:85b3fd62ea1a 424 /* Set the new LSE configuration -----------------------------------------*/
NYX 0:85b3fd62ea1a 425 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
NYX 0:85b3fd62ea1a 426 /* Check the LSE State */
NYX 0:85b3fd62ea1a 427 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
NYX 0:85b3fd62ea1a 428 {
NYX 0:85b3fd62ea1a 429 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 430 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 431
NYX 0:85b3fd62ea1a 432 /* Wait till LSE is ready */
NYX 0:85b3fd62ea1a 433 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
NYX 0:85b3fd62ea1a 434 {
NYX 0:85b3fd62ea1a 435 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 436 {
NYX 0:85b3fd62ea1a 437 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 438 }
NYX 0:85b3fd62ea1a 439 }
NYX 0:85b3fd62ea1a 440 }
NYX 0:85b3fd62ea1a 441 else
NYX 0:85b3fd62ea1a 442 {
NYX 0:85b3fd62ea1a 443 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 444 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 445
NYX 0:85b3fd62ea1a 446 /* Wait till LSE is ready */
NYX 0:85b3fd62ea1a 447 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
NYX 0:85b3fd62ea1a 448 {
NYX 0:85b3fd62ea1a 449 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 450 {
NYX 0:85b3fd62ea1a 451 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 452 }
NYX 0:85b3fd62ea1a 453 }
NYX 0:85b3fd62ea1a 454 }
NYX 0:85b3fd62ea1a 455 }
NYX 0:85b3fd62ea1a 456 /*-------------------------------- PLL Configuration -----------------------*/
NYX 0:85b3fd62ea1a 457 /* Check the parameters */
NYX 0:85b3fd62ea1a 458 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
NYX 0:85b3fd62ea1a 459 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
NYX 0:85b3fd62ea1a 460 {
NYX 0:85b3fd62ea1a 461 /* Check if the PLL is used as system clock or not */
NYX 0:85b3fd62ea1a 462 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
NYX 0:85b3fd62ea1a 463 {
NYX 0:85b3fd62ea1a 464 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
NYX 0:85b3fd62ea1a 465 {
NYX 0:85b3fd62ea1a 466 /* Check the parameters */
NYX 0:85b3fd62ea1a 467 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
NYX 0:85b3fd62ea1a 468 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
NYX 0:85b3fd62ea1a 469 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
NYX 0:85b3fd62ea1a 470 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
NYX 0:85b3fd62ea1a 471 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
NYX 0:85b3fd62ea1a 472
NYX 0:85b3fd62ea1a 473 /* Disable the main PLL. */
NYX 0:85b3fd62ea1a 474 __HAL_RCC_PLL_DISABLE();
NYX 0:85b3fd62ea1a 475
NYX 0:85b3fd62ea1a 476 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 477 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 478
NYX 0:85b3fd62ea1a 479 /* Wait till PLL is ready */
NYX 0:85b3fd62ea1a 480 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
NYX 0:85b3fd62ea1a 481 {
NYX 0:85b3fd62ea1a 482 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 483 {
NYX 0:85b3fd62ea1a 484 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 485 }
NYX 0:85b3fd62ea1a 486 }
NYX 0:85b3fd62ea1a 487
NYX 0:85b3fd62ea1a 488 /* Configure the main PLL clock source, multiplication and division factors. */
NYX 0:85b3fd62ea1a 489 WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
NYX 0:85b3fd62ea1a 490 RCC_OscInitStruct->PLL.PLLM | \
NYX 0:85b3fd62ea1a 491 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
NYX 0:85b3fd62ea1a 492 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
NYX 0:85b3fd62ea1a 493 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
NYX 0:85b3fd62ea1a 494 /* Enable the main PLL. */
NYX 0:85b3fd62ea1a 495 __HAL_RCC_PLL_ENABLE();
NYX 0:85b3fd62ea1a 496
NYX 0:85b3fd62ea1a 497 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 498 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 499
NYX 0:85b3fd62ea1a 500 /* Wait till PLL is ready */
NYX 0:85b3fd62ea1a 501 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
NYX 0:85b3fd62ea1a 502 {
NYX 0:85b3fd62ea1a 503 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 504 {
NYX 0:85b3fd62ea1a 505 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 506 }
NYX 0:85b3fd62ea1a 507 }
NYX 0:85b3fd62ea1a 508 }
NYX 0:85b3fd62ea1a 509 else
NYX 0:85b3fd62ea1a 510 {
NYX 0:85b3fd62ea1a 511 /* Disable the main PLL. */
NYX 0:85b3fd62ea1a 512 __HAL_RCC_PLL_DISABLE();
NYX 0:85b3fd62ea1a 513
NYX 0:85b3fd62ea1a 514 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 515 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 516
NYX 0:85b3fd62ea1a 517 /* Wait till PLL is ready */
NYX 0:85b3fd62ea1a 518 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
NYX 0:85b3fd62ea1a 519 {
NYX 0:85b3fd62ea1a 520 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 521 {
NYX 0:85b3fd62ea1a 522 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 523 }
NYX 0:85b3fd62ea1a 524 }
NYX 0:85b3fd62ea1a 525 }
NYX 0:85b3fd62ea1a 526 }
NYX 0:85b3fd62ea1a 527 else
NYX 0:85b3fd62ea1a 528 {
NYX 0:85b3fd62ea1a 529 return HAL_ERROR;
NYX 0:85b3fd62ea1a 530 }
NYX 0:85b3fd62ea1a 531 }
NYX 0:85b3fd62ea1a 532 return HAL_OK;
NYX 0:85b3fd62ea1a 533 }
NYX 0:85b3fd62ea1a 534
NYX 0:85b3fd62ea1a 535 /**
NYX 0:85b3fd62ea1a 536 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
NYX 0:85b3fd62ea1a 537 * parameters in the RCC_ClkInitStruct.
NYX 0:85b3fd62ea1a 538 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
NYX 0:85b3fd62ea1a 539 * contains the configuration information for the RCC peripheral.
NYX 0:85b3fd62ea1a 540 * @param FLatency: FLASH Latency, this parameter depend on device selected
NYX 0:85b3fd62ea1a 541 *
NYX 0:85b3fd62ea1a 542 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
NYX 0:85b3fd62ea1a 543 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
NYX 0:85b3fd62ea1a 544 *
NYX 0:85b3fd62ea1a 545 * @note The HSI is used (enabled by hardware) as system clock source after
NYX 0:85b3fd62ea1a 546 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
NYX 0:85b3fd62ea1a 547 * of failure of the HSE used directly or indirectly as system clock
NYX 0:85b3fd62ea1a 548 * (if the Clock Security System CSS is enabled).
NYX 0:85b3fd62ea1a 549 *
NYX 0:85b3fd62ea1a 550 * @note A switch from one clock source to another occurs only if the target
NYX 0:85b3fd62ea1a 551 * clock source is ready (clock stable after startup delay or PLL locked).
NYX 0:85b3fd62ea1a 552 * If a clock source which is not yet ready is selected, the switch will
NYX 0:85b3fd62ea1a 553 * occur when the clock source will be ready.
NYX 0:85b3fd62ea1a 554 *
NYX 0:85b3fd62ea1a 555 * @note Depending on the device voltage range, the software has to set correctly
NYX 0:85b3fd62ea1a 556 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
NYX 0:85b3fd62ea1a 557 * (for more details refer to section above "Initialization/de-initialization functions")
NYX 0:85b3fd62ea1a 558 * @retval None
NYX 0:85b3fd62ea1a 559 */
NYX 0:85b3fd62ea1a 560 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
NYX 0:85b3fd62ea1a 561 {
NYX 0:85b3fd62ea1a 562 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 563
NYX 0:85b3fd62ea1a 564 /* Check the parameters */
NYX 0:85b3fd62ea1a 565 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
NYX 0:85b3fd62ea1a 566 assert_param(IS_FLASH_LATENCY(FLatency));
NYX 0:85b3fd62ea1a 567
NYX 0:85b3fd62ea1a 568 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
NYX 0:85b3fd62ea1a 569 must be correctly programmed according to the frequency of the CPU clock
NYX 0:85b3fd62ea1a 570 (HCLK) and the supply voltage of the device. */
NYX 0:85b3fd62ea1a 571
NYX 0:85b3fd62ea1a 572 /* Increasing the number of wait states because of higher CPU frequency */
NYX 0:85b3fd62ea1a 573 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
NYX 0:85b3fd62ea1a 574 {
NYX 0:85b3fd62ea1a 575 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
NYX 0:85b3fd62ea1a 576 __HAL_FLASH_SET_LATENCY(FLatency);
NYX 0:85b3fd62ea1a 577
NYX 0:85b3fd62ea1a 578 /* Check that the new number of wait states is taken into account to access the Flash
NYX 0:85b3fd62ea1a 579 memory by reading the FLASH_ACR register */
NYX 0:85b3fd62ea1a 580 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
NYX 0:85b3fd62ea1a 581 {
NYX 0:85b3fd62ea1a 582 return HAL_ERROR;
NYX 0:85b3fd62ea1a 583 }
NYX 0:85b3fd62ea1a 584 }
NYX 0:85b3fd62ea1a 585
NYX 0:85b3fd62ea1a 586 /*-------------------------- HCLK Configuration --------------------------*/
NYX 0:85b3fd62ea1a 587 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
NYX 0:85b3fd62ea1a 588 {
NYX 0:85b3fd62ea1a 589 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
NYX 0:85b3fd62ea1a 590 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
NYX 0:85b3fd62ea1a 591 }
NYX 0:85b3fd62ea1a 592
NYX 0:85b3fd62ea1a 593 /*------------------------- SYSCLK Configuration ---------------------------*/
NYX 0:85b3fd62ea1a 594 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
NYX 0:85b3fd62ea1a 595 {
NYX 0:85b3fd62ea1a 596 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
NYX 0:85b3fd62ea1a 597
NYX 0:85b3fd62ea1a 598 /* HSE is selected as System Clock Source */
NYX 0:85b3fd62ea1a 599 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
NYX 0:85b3fd62ea1a 600 {
NYX 0:85b3fd62ea1a 601 /* Check the HSE ready flag */
NYX 0:85b3fd62ea1a 602 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
NYX 0:85b3fd62ea1a 603 {
NYX 0:85b3fd62ea1a 604 return HAL_ERROR;
NYX 0:85b3fd62ea1a 605 }
NYX 0:85b3fd62ea1a 606 }
NYX 0:85b3fd62ea1a 607 /* PLL is selected as System Clock Source */
NYX 0:85b3fd62ea1a 608 else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
NYX 0:85b3fd62ea1a 609 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
NYX 0:85b3fd62ea1a 610 {
NYX 0:85b3fd62ea1a 611 /* Check the PLL ready flag */
NYX 0:85b3fd62ea1a 612 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
NYX 0:85b3fd62ea1a 613 {
NYX 0:85b3fd62ea1a 614 return HAL_ERROR;
NYX 0:85b3fd62ea1a 615 }
NYX 0:85b3fd62ea1a 616 }
NYX 0:85b3fd62ea1a 617 /* HSI is selected as System Clock Source */
NYX 0:85b3fd62ea1a 618 else
NYX 0:85b3fd62ea1a 619 {
NYX 0:85b3fd62ea1a 620 /* Check the HSI ready flag */
NYX 0:85b3fd62ea1a 621 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
NYX 0:85b3fd62ea1a 622 {
NYX 0:85b3fd62ea1a 623 return HAL_ERROR;
NYX 0:85b3fd62ea1a 624 }
NYX 0:85b3fd62ea1a 625 }
NYX 0:85b3fd62ea1a 626
NYX 0:85b3fd62ea1a 627 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
NYX 0:85b3fd62ea1a 628 /* Get Start Tick*/
NYX 0:85b3fd62ea1a 629 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 630
NYX 0:85b3fd62ea1a 631 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
NYX 0:85b3fd62ea1a 632 {
NYX 0:85b3fd62ea1a 633 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
NYX 0:85b3fd62ea1a 634 {
NYX 0:85b3fd62ea1a 635 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 636 {
NYX 0:85b3fd62ea1a 637 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 638 }
NYX 0:85b3fd62ea1a 639 }
NYX 0:85b3fd62ea1a 640 }
NYX 0:85b3fd62ea1a 641 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
NYX 0:85b3fd62ea1a 642 {
NYX 0:85b3fd62ea1a 643 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
NYX 0:85b3fd62ea1a 644 {
NYX 0:85b3fd62ea1a 645 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 646 {
NYX 0:85b3fd62ea1a 647 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 648 }
NYX 0:85b3fd62ea1a 649 }
NYX 0:85b3fd62ea1a 650 }
NYX 0:85b3fd62ea1a 651 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
NYX 0:85b3fd62ea1a 652 {
NYX 0:85b3fd62ea1a 653 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
NYX 0:85b3fd62ea1a 654 {
NYX 0:85b3fd62ea1a 655 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 656 {
NYX 0:85b3fd62ea1a 657 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 658 }
NYX 0:85b3fd62ea1a 659 }
NYX 0:85b3fd62ea1a 660 }
NYX 0:85b3fd62ea1a 661 else
NYX 0:85b3fd62ea1a 662 {
NYX 0:85b3fd62ea1a 663 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
NYX 0:85b3fd62ea1a 664 {
NYX 0:85b3fd62ea1a 665 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 666 {
NYX 0:85b3fd62ea1a 667 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 668 }
NYX 0:85b3fd62ea1a 669 }
NYX 0:85b3fd62ea1a 670 }
NYX 0:85b3fd62ea1a 671 }
NYX 0:85b3fd62ea1a 672
NYX 0:85b3fd62ea1a 673 /* Decreasing the number of wait states because of lower CPU frequency */
NYX 0:85b3fd62ea1a 674 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
NYX 0:85b3fd62ea1a 675 {
NYX 0:85b3fd62ea1a 676 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
NYX 0:85b3fd62ea1a 677 __HAL_FLASH_SET_LATENCY(FLatency);
NYX 0:85b3fd62ea1a 678
NYX 0:85b3fd62ea1a 679 /* Check that the new number of wait states is taken into account to access the Flash
NYX 0:85b3fd62ea1a 680 memory by reading the FLASH_ACR register */
NYX 0:85b3fd62ea1a 681 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
NYX 0:85b3fd62ea1a 682 {
NYX 0:85b3fd62ea1a 683 return HAL_ERROR;
NYX 0:85b3fd62ea1a 684 }
NYX 0:85b3fd62ea1a 685 }
NYX 0:85b3fd62ea1a 686
NYX 0:85b3fd62ea1a 687 /*-------------------------- PCLK1 Configuration ---------------------------*/
NYX 0:85b3fd62ea1a 688 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
NYX 0:85b3fd62ea1a 689 {
NYX 0:85b3fd62ea1a 690 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
NYX 0:85b3fd62ea1a 691 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
NYX 0:85b3fd62ea1a 692 }
NYX 0:85b3fd62ea1a 693
NYX 0:85b3fd62ea1a 694 /*-------------------------- PCLK2 Configuration ---------------------------*/
NYX 0:85b3fd62ea1a 695 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
NYX 0:85b3fd62ea1a 696 {
NYX 0:85b3fd62ea1a 697 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
NYX 0:85b3fd62ea1a 698 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
NYX 0:85b3fd62ea1a 699 }
NYX 0:85b3fd62ea1a 700
NYX 0:85b3fd62ea1a 701 /* Update the SystemCoreClock global variable */
NYX 0:85b3fd62ea1a 702 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
NYX 0:85b3fd62ea1a 703
NYX 0:85b3fd62ea1a 704 /* Configure the source of time base considering new system clocks settings*/
NYX 0:85b3fd62ea1a 705 HAL_InitTick (TICK_INT_PRIORITY);
NYX 0:85b3fd62ea1a 706
NYX 0:85b3fd62ea1a 707 return HAL_OK;
NYX 0:85b3fd62ea1a 708 }
NYX 0:85b3fd62ea1a 709
NYX 0:85b3fd62ea1a 710 /**
NYX 0:85b3fd62ea1a 711 * @}
NYX 0:85b3fd62ea1a 712 */
NYX 0:85b3fd62ea1a 713
NYX 0:85b3fd62ea1a 714 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
NYX 0:85b3fd62ea1a 715 * @brief RCC clocks control functions
NYX 0:85b3fd62ea1a 716 *
NYX 0:85b3fd62ea1a 717 @verbatim
NYX 0:85b3fd62ea1a 718 ===============================================================================
NYX 0:85b3fd62ea1a 719 ##### Peripheral Control functions #####
NYX 0:85b3fd62ea1a 720 ===============================================================================
NYX 0:85b3fd62ea1a 721 [..]
NYX 0:85b3fd62ea1a 722 This subsection provides a set of functions allowing to control the RCC Clocks
NYX 0:85b3fd62ea1a 723 frequencies.
NYX 0:85b3fd62ea1a 724
NYX 0:85b3fd62ea1a 725 @endverbatim
NYX 0:85b3fd62ea1a 726 * @{
NYX 0:85b3fd62ea1a 727 */
NYX 0:85b3fd62ea1a 728
NYX 0:85b3fd62ea1a 729 /**
NYX 0:85b3fd62ea1a 730 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
NYX 0:85b3fd62ea1a 731 * @note PA8/PC9 should be configured in alternate function mode.
NYX 0:85b3fd62ea1a 732 * @param RCC_MCOx: specifies the output direction for the clock source.
NYX 0:85b3fd62ea1a 733 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 734 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
NYX 0:85b3fd62ea1a 735 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
NYX 0:85b3fd62ea1a 736 * @param RCC_MCOSource: specifies the clock source to output.
NYX 0:85b3fd62ea1a 737 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 738 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
NYX 0:85b3fd62ea1a 739 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
NYX 0:85b3fd62ea1a 740 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
NYX 0:85b3fd62ea1a 741 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
NYX 0:85b3fd62ea1a 742 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
NYX 0:85b3fd62ea1a 743 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
NYX 0:85b3fd62ea1a 744 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
NYX 0:85b3fd62ea1a 745 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
NYX 0:85b3fd62ea1a 746 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
NYX 0:85b3fd62ea1a 747 * @param RCC_MCODiv: specifies the MCOx prescaler.
NYX 0:85b3fd62ea1a 748 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 749 * @arg RCC_MCODIV_1: no division applied to MCOx clock
NYX 0:85b3fd62ea1a 750 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
NYX 0:85b3fd62ea1a 751 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
NYX 0:85b3fd62ea1a 752 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
NYX 0:85b3fd62ea1a 753 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
NYX 0:85b3fd62ea1a 754 * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
NYX 0:85b3fd62ea1a 755 * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
NYX 0:85b3fd62ea1a 756 * @retval None
NYX 0:85b3fd62ea1a 757 */
NYX 0:85b3fd62ea1a 758 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
NYX 0:85b3fd62ea1a 759 {
NYX 0:85b3fd62ea1a 760 GPIO_InitTypeDef GPIO_InitStruct;
NYX 0:85b3fd62ea1a 761 /* Check the parameters */
NYX 0:85b3fd62ea1a 762 assert_param(IS_RCC_MCO(RCC_MCOx));
NYX 0:85b3fd62ea1a 763 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
NYX 0:85b3fd62ea1a 764 /* RCC_MCO1 */
NYX 0:85b3fd62ea1a 765 if(RCC_MCOx == RCC_MCO1)
NYX 0:85b3fd62ea1a 766 {
NYX 0:85b3fd62ea1a 767 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
NYX 0:85b3fd62ea1a 768
NYX 0:85b3fd62ea1a 769 /* MCO1 Clock Enable */
NYX 0:85b3fd62ea1a 770 __MCO1_CLK_ENABLE();
NYX 0:85b3fd62ea1a 771
NYX 0:85b3fd62ea1a 772 /* Configure the MCO1 pin in alternate function mode */
NYX 0:85b3fd62ea1a 773 GPIO_InitStruct.Pin = MCO1_PIN;
NYX 0:85b3fd62ea1a 774 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
NYX 0:85b3fd62ea1a 775 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
NYX 0:85b3fd62ea1a 776 GPIO_InitStruct.Pull = GPIO_NOPULL;
NYX 0:85b3fd62ea1a 777 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
NYX 0:85b3fd62ea1a 778 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
NYX 0:85b3fd62ea1a 779
NYX 0:85b3fd62ea1a 780 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
NYX 0:85b3fd62ea1a 781 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
NYX 0:85b3fd62ea1a 782
NYX 0:85b3fd62ea1a 783 /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
NYX 0:85b3fd62ea1a 784 #if defined(RCC_CFGR_MCO1EN)
NYX 0:85b3fd62ea1a 785 __HAL_RCC_MCO1_ENABLE();
NYX 0:85b3fd62ea1a 786 #endif /* RCC_CFGR_MCO1EN */
NYX 0:85b3fd62ea1a 787 }
NYX 0:85b3fd62ea1a 788 #if defined(RCC_CFGR_MCO2)
NYX 0:85b3fd62ea1a 789 else
NYX 0:85b3fd62ea1a 790 {
NYX 0:85b3fd62ea1a 791 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
NYX 0:85b3fd62ea1a 792
NYX 0:85b3fd62ea1a 793 /* MCO2 Clock Enable */
NYX 0:85b3fd62ea1a 794 __MCO2_CLK_ENABLE();
NYX 0:85b3fd62ea1a 795
NYX 0:85b3fd62ea1a 796 /* Configure the MCO2 pin in alternate function mode */
NYX 0:85b3fd62ea1a 797 GPIO_InitStruct.Pin = MCO2_PIN;
NYX 0:85b3fd62ea1a 798 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
NYX 0:85b3fd62ea1a 799 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
NYX 0:85b3fd62ea1a 800 GPIO_InitStruct.Pull = GPIO_NOPULL;
NYX 0:85b3fd62ea1a 801 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
NYX 0:85b3fd62ea1a 802 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
NYX 0:85b3fd62ea1a 803
NYX 0:85b3fd62ea1a 804 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
NYX 0:85b3fd62ea1a 805 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
NYX 0:85b3fd62ea1a 806
NYX 0:85b3fd62ea1a 807 /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
NYX 0:85b3fd62ea1a 808 #if defined(RCC_CFGR_MCO2EN)
NYX 0:85b3fd62ea1a 809 __HAL_RCC_MCO2_ENABLE();
NYX 0:85b3fd62ea1a 810 #endif /* RCC_CFGR_MCO2EN */
NYX 0:85b3fd62ea1a 811 }
NYX 0:85b3fd62ea1a 812 #endif /* RCC_CFGR_MCO2 */
NYX 0:85b3fd62ea1a 813 }
NYX 0:85b3fd62ea1a 814
NYX 0:85b3fd62ea1a 815 /**
NYX 0:85b3fd62ea1a 816 * @brief Enables the Clock Security System.
NYX 0:85b3fd62ea1a 817 * @note If a failure is detected on the HSE oscillator clock, this oscillator
NYX 0:85b3fd62ea1a 818 * is automatically disabled and an interrupt is generated to inform the
NYX 0:85b3fd62ea1a 819 * software about the failure (Clock Security System Interrupt, CSSI),
NYX 0:85b3fd62ea1a 820 * allowing the MCU to perform rescue operations. The CSSI is linked to
NYX 0:85b3fd62ea1a 821 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
NYX 0:85b3fd62ea1a 822 * @retval None
NYX 0:85b3fd62ea1a 823 */
NYX 0:85b3fd62ea1a 824 void HAL_RCC_EnableCSS(void)
NYX 0:85b3fd62ea1a 825 {
NYX 0:85b3fd62ea1a 826 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
NYX 0:85b3fd62ea1a 827 }
NYX 0:85b3fd62ea1a 828
NYX 0:85b3fd62ea1a 829 /**
NYX 0:85b3fd62ea1a 830 * @brief Disables the Clock Security System.
NYX 0:85b3fd62ea1a 831 * @retval None
NYX 0:85b3fd62ea1a 832 */
NYX 0:85b3fd62ea1a 833 void HAL_RCC_DisableCSS(void)
NYX 0:85b3fd62ea1a 834 {
NYX 0:85b3fd62ea1a 835 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
NYX 0:85b3fd62ea1a 836 }
NYX 0:85b3fd62ea1a 837
NYX 0:85b3fd62ea1a 838 /**
NYX 0:85b3fd62ea1a 839 * @brief Returns the SYSCLK frequency
NYX 0:85b3fd62ea1a 840 *
NYX 0:85b3fd62ea1a 841 * @note The system frequency computed by this function is not the real
NYX 0:85b3fd62ea1a 842 * frequency in the chip. It is calculated based on the predefined
NYX 0:85b3fd62ea1a 843 * constant and the selected clock source:
NYX 0:85b3fd62ea1a 844 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
NYX 0:85b3fd62ea1a 845 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
NYX 0:85b3fd62ea1a 846 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
NYX 0:85b3fd62ea1a 847 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
NYX 0:85b3fd62ea1a 848 * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
NYX 0:85b3fd62ea1a 849 * 16 MHz) but the real value may vary depending on the variations
NYX 0:85b3fd62ea1a 850 * in voltage and temperature.
NYX 0:85b3fd62ea1a 851 * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
NYX 0:85b3fd62ea1a 852 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
NYX 0:85b3fd62ea1a 853 * frequency of the crystal used. Otherwise, this function may
NYX 0:85b3fd62ea1a 854 * have wrong result.
NYX 0:85b3fd62ea1a 855 *
NYX 0:85b3fd62ea1a 856 * @note The result of this function could be not correct when using fractional
NYX 0:85b3fd62ea1a 857 * value for HSE crystal.
NYX 0:85b3fd62ea1a 858 *
NYX 0:85b3fd62ea1a 859 * @note This function can be used by the user application to compute the
NYX 0:85b3fd62ea1a 860 * baudrate for the communication peripherals or configure other parameters.
NYX 0:85b3fd62ea1a 861 *
NYX 0:85b3fd62ea1a 862 * @note Each time SYSCLK changes, this function must be called to update the
NYX 0:85b3fd62ea1a 863 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
NYX 0:85b3fd62ea1a 864 *
NYX 0:85b3fd62ea1a 865 *
NYX 0:85b3fd62ea1a 866 * @retval SYSCLK frequency
NYX 0:85b3fd62ea1a 867 */
NYX 0:85b3fd62ea1a 868 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
NYX 0:85b3fd62ea1a 869 {
NYX 0:85b3fd62ea1a 870 uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
NYX 0:85b3fd62ea1a 871 uint32_t sysclockfreq = 0U;
NYX 0:85b3fd62ea1a 872
NYX 0:85b3fd62ea1a 873 /* Get SYSCLK source -------------------------------------------------------*/
NYX 0:85b3fd62ea1a 874 switch (RCC->CFGR & RCC_CFGR_SWS)
NYX 0:85b3fd62ea1a 875 {
NYX 0:85b3fd62ea1a 876 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
NYX 0:85b3fd62ea1a 877 {
NYX 0:85b3fd62ea1a 878 sysclockfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 879 break;
NYX 0:85b3fd62ea1a 880 }
NYX 0:85b3fd62ea1a 881 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
NYX 0:85b3fd62ea1a 882 {
NYX 0:85b3fd62ea1a 883 sysclockfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 884 break;
NYX 0:85b3fd62ea1a 885 }
NYX 0:85b3fd62ea1a 886 case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
NYX 0:85b3fd62ea1a 887 {
NYX 0:85b3fd62ea1a 888 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
NYX 0:85b3fd62ea1a 889 SYSCLK = PLL_VCO / PLLP */
NYX 0:85b3fd62ea1a 890 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
NYX 0:85b3fd62ea1a 891 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
NYX 0:85b3fd62ea1a 892 {
NYX 0:85b3fd62ea1a 893 /* HSE used as PLL clock source */
NYX 0:85b3fd62ea1a 894 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
NYX 0:85b3fd62ea1a 895 }
NYX 0:85b3fd62ea1a 896 else
NYX 0:85b3fd62ea1a 897 {
NYX 0:85b3fd62ea1a 898 /* HSI used as PLL clock source */
NYX 0:85b3fd62ea1a 899 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
NYX 0:85b3fd62ea1a 900 }
NYX 0:85b3fd62ea1a 901 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
NYX 0:85b3fd62ea1a 902
NYX 0:85b3fd62ea1a 903 sysclockfreq = pllvco/pllp;
NYX 0:85b3fd62ea1a 904 break;
NYX 0:85b3fd62ea1a 905 }
NYX 0:85b3fd62ea1a 906 default:
NYX 0:85b3fd62ea1a 907 {
NYX 0:85b3fd62ea1a 908 sysclockfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 909 break;
NYX 0:85b3fd62ea1a 910 }
NYX 0:85b3fd62ea1a 911 }
NYX 0:85b3fd62ea1a 912 return sysclockfreq;
NYX 0:85b3fd62ea1a 913 }
NYX 0:85b3fd62ea1a 914
NYX 0:85b3fd62ea1a 915 /**
NYX 0:85b3fd62ea1a 916 * @brief Returns the HCLK frequency
NYX 0:85b3fd62ea1a 917 * @note Each time HCLK changes, this function must be called to update the
NYX 0:85b3fd62ea1a 918 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
NYX 0:85b3fd62ea1a 919 *
NYX 0:85b3fd62ea1a 920 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
NYX 0:85b3fd62ea1a 921 * and updated within this function
NYX 0:85b3fd62ea1a 922 * @retval HCLK frequency
NYX 0:85b3fd62ea1a 923 */
NYX 0:85b3fd62ea1a 924 uint32_t HAL_RCC_GetHCLKFreq(void)
NYX 0:85b3fd62ea1a 925 {
NYX 0:85b3fd62ea1a 926 return SystemCoreClock;
NYX 0:85b3fd62ea1a 927 }
NYX 0:85b3fd62ea1a 928
NYX 0:85b3fd62ea1a 929 /**
NYX 0:85b3fd62ea1a 930 * @brief Returns the PCLK1 frequency
NYX 0:85b3fd62ea1a 931 * @note Each time PCLK1 changes, this function must be called to update the
NYX 0:85b3fd62ea1a 932 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
NYX 0:85b3fd62ea1a 933 * @retval PCLK1 frequency
NYX 0:85b3fd62ea1a 934 */
NYX 0:85b3fd62ea1a 935 uint32_t HAL_RCC_GetPCLK1Freq(void)
NYX 0:85b3fd62ea1a 936 {
NYX 0:85b3fd62ea1a 937 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
NYX 0:85b3fd62ea1a 938 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
NYX 0:85b3fd62ea1a 939 }
NYX 0:85b3fd62ea1a 940
NYX 0:85b3fd62ea1a 941 /**
NYX 0:85b3fd62ea1a 942 * @brief Returns the PCLK2 frequency
NYX 0:85b3fd62ea1a 943 * @note Each time PCLK2 changes, this function must be called to update the
NYX 0:85b3fd62ea1a 944 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
NYX 0:85b3fd62ea1a 945 * @retval PCLK2 frequency
NYX 0:85b3fd62ea1a 946 */
NYX 0:85b3fd62ea1a 947 uint32_t HAL_RCC_GetPCLK2Freq(void)
NYX 0:85b3fd62ea1a 948 {
NYX 0:85b3fd62ea1a 949 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
NYX 0:85b3fd62ea1a 950 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
NYX 0:85b3fd62ea1a 951 }
NYX 0:85b3fd62ea1a 952
NYX 0:85b3fd62ea1a 953 /**
NYX 0:85b3fd62ea1a 954 * @brief Configures the RCC_OscInitStruct according to the internal
NYX 0:85b3fd62ea1a 955 * RCC configuration registers.
NYX 0:85b3fd62ea1a 956 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
NYX 0:85b3fd62ea1a 957 * will be configured.
NYX 0:85b3fd62ea1a 958 * @retval None
NYX 0:85b3fd62ea1a 959 */
NYX 0:85b3fd62ea1a 960 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
NYX 0:85b3fd62ea1a 961 {
NYX 0:85b3fd62ea1a 962 /* Set all possible values for the Oscillator type parameter ---------------*/
NYX 0:85b3fd62ea1a 963 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
NYX 0:85b3fd62ea1a 964
NYX 0:85b3fd62ea1a 965 /* Get the HSE configuration -----------------------------------------------*/
NYX 0:85b3fd62ea1a 966 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
NYX 0:85b3fd62ea1a 967 {
NYX 0:85b3fd62ea1a 968 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
NYX 0:85b3fd62ea1a 969 }
NYX 0:85b3fd62ea1a 970 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
NYX 0:85b3fd62ea1a 971 {
NYX 0:85b3fd62ea1a 972 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
NYX 0:85b3fd62ea1a 973 }
NYX 0:85b3fd62ea1a 974 else
NYX 0:85b3fd62ea1a 975 {
NYX 0:85b3fd62ea1a 976 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
NYX 0:85b3fd62ea1a 977 }
NYX 0:85b3fd62ea1a 978
NYX 0:85b3fd62ea1a 979 /* Get the HSI configuration -----------------------------------------------*/
NYX 0:85b3fd62ea1a 980 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
NYX 0:85b3fd62ea1a 981 {
NYX 0:85b3fd62ea1a 982 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
NYX 0:85b3fd62ea1a 983 }
NYX 0:85b3fd62ea1a 984 else
NYX 0:85b3fd62ea1a 985 {
NYX 0:85b3fd62ea1a 986 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
NYX 0:85b3fd62ea1a 987 }
NYX 0:85b3fd62ea1a 988
NYX 0:85b3fd62ea1a 989 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
NYX 0:85b3fd62ea1a 990
NYX 0:85b3fd62ea1a 991 /* Get the LSE configuration -----------------------------------------------*/
NYX 0:85b3fd62ea1a 992 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
NYX 0:85b3fd62ea1a 993 {
NYX 0:85b3fd62ea1a 994 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
NYX 0:85b3fd62ea1a 995 }
NYX 0:85b3fd62ea1a 996 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
NYX 0:85b3fd62ea1a 997 {
NYX 0:85b3fd62ea1a 998 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
NYX 0:85b3fd62ea1a 999 }
NYX 0:85b3fd62ea1a 1000 else
NYX 0:85b3fd62ea1a 1001 {
NYX 0:85b3fd62ea1a 1002 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
NYX 0:85b3fd62ea1a 1003 }
NYX 0:85b3fd62ea1a 1004
NYX 0:85b3fd62ea1a 1005 /* Get the LSI configuration -----------------------------------------------*/
NYX 0:85b3fd62ea1a 1006 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
NYX 0:85b3fd62ea1a 1007 {
NYX 0:85b3fd62ea1a 1008 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
NYX 0:85b3fd62ea1a 1009 }
NYX 0:85b3fd62ea1a 1010 else
NYX 0:85b3fd62ea1a 1011 {
NYX 0:85b3fd62ea1a 1012 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
NYX 0:85b3fd62ea1a 1013 }
NYX 0:85b3fd62ea1a 1014
NYX 0:85b3fd62ea1a 1015 /* Get the PLL configuration -----------------------------------------------*/
NYX 0:85b3fd62ea1a 1016 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
NYX 0:85b3fd62ea1a 1017 {
NYX 0:85b3fd62ea1a 1018 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
NYX 0:85b3fd62ea1a 1019 }
NYX 0:85b3fd62ea1a 1020 else
NYX 0:85b3fd62ea1a 1021 {
NYX 0:85b3fd62ea1a 1022 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
NYX 0:85b3fd62ea1a 1023 }
NYX 0:85b3fd62ea1a 1024 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
NYX 0:85b3fd62ea1a 1025 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
NYX 0:85b3fd62ea1a 1026 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
NYX 0:85b3fd62ea1a 1027 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
NYX 0:85b3fd62ea1a 1028 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
NYX 0:85b3fd62ea1a 1029 }
NYX 0:85b3fd62ea1a 1030
NYX 0:85b3fd62ea1a 1031 /**
NYX 0:85b3fd62ea1a 1032 * @brief Configures the RCC_ClkInitStruct according to the internal
NYX 0:85b3fd62ea1a 1033 * RCC configuration registers.
NYX 0:85b3fd62ea1a 1034 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
NYX 0:85b3fd62ea1a 1035 * will be configured.
NYX 0:85b3fd62ea1a 1036 * @param pFLatency: Pointer on the Flash Latency.
NYX 0:85b3fd62ea1a 1037 * @retval None
NYX 0:85b3fd62ea1a 1038 */
NYX 0:85b3fd62ea1a 1039 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
NYX 0:85b3fd62ea1a 1040 {
NYX 0:85b3fd62ea1a 1041 /* Set all possible values for the Clock type parameter --------------------*/
NYX 0:85b3fd62ea1a 1042 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
NYX 0:85b3fd62ea1a 1043
NYX 0:85b3fd62ea1a 1044 /* Get the SYSCLK configuration --------------------------------------------*/
NYX 0:85b3fd62ea1a 1045 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
NYX 0:85b3fd62ea1a 1046
NYX 0:85b3fd62ea1a 1047 /* Get the HCLK configuration ----------------------------------------------*/
NYX 0:85b3fd62ea1a 1048 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
NYX 0:85b3fd62ea1a 1049
NYX 0:85b3fd62ea1a 1050 /* Get the APB1 configuration ----------------------------------------------*/
NYX 0:85b3fd62ea1a 1051 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
NYX 0:85b3fd62ea1a 1052
NYX 0:85b3fd62ea1a 1053 /* Get the APB2 configuration ----------------------------------------------*/
NYX 0:85b3fd62ea1a 1054 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
NYX 0:85b3fd62ea1a 1055
NYX 0:85b3fd62ea1a 1056 /* Get the Flash Wait State (Latency) configuration ------------------------*/
NYX 0:85b3fd62ea1a 1057 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
NYX 0:85b3fd62ea1a 1058 }
NYX 0:85b3fd62ea1a 1059
NYX 0:85b3fd62ea1a 1060 /**
NYX 0:85b3fd62ea1a 1061 * @brief This function handles the RCC CSS interrupt request.
NYX 0:85b3fd62ea1a 1062 * @note This API should be called under the NMI_Handler().
NYX 0:85b3fd62ea1a 1063 * @retval None
NYX 0:85b3fd62ea1a 1064 */
NYX 0:85b3fd62ea1a 1065 void HAL_RCC_NMI_IRQHandler(void)
NYX 0:85b3fd62ea1a 1066 {
NYX 0:85b3fd62ea1a 1067 /* Check RCC CSSF flag */
NYX 0:85b3fd62ea1a 1068 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
NYX 0:85b3fd62ea1a 1069 {
NYX 0:85b3fd62ea1a 1070 /* RCC Clock Security System interrupt user callback */
NYX 0:85b3fd62ea1a 1071 HAL_RCC_CSSCallback();
NYX 0:85b3fd62ea1a 1072
NYX 0:85b3fd62ea1a 1073 /* Clear RCC CSS pending bit */
NYX 0:85b3fd62ea1a 1074 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
NYX 0:85b3fd62ea1a 1075 }
NYX 0:85b3fd62ea1a 1076 }
NYX 0:85b3fd62ea1a 1077
NYX 0:85b3fd62ea1a 1078 /**
NYX 0:85b3fd62ea1a 1079 * @brief RCC Clock Security System interrupt callback
NYX 0:85b3fd62ea1a 1080 * @retval None
NYX 0:85b3fd62ea1a 1081 */
NYX 0:85b3fd62ea1a 1082 __weak void HAL_RCC_CSSCallback(void)
NYX 0:85b3fd62ea1a 1083 {
NYX 0:85b3fd62ea1a 1084 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1085 the HAL_RCC_CSSCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 1086 */
NYX 0:85b3fd62ea1a 1087 }
NYX 0:85b3fd62ea1a 1088
NYX 0:85b3fd62ea1a 1089 /**
NYX 0:85b3fd62ea1a 1090 * @}
NYX 0:85b3fd62ea1a 1091 */
NYX 0:85b3fd62ea1a 1092
NYX 0:85b3fd62ea1a 1093 /**
NYX 0:85b3fd62ea1a 1094 * @}
NYX 0:85b3fd62ea1a 1095 */
NYX 0:85b3fd62ea1a 1096
NYX 0:85b3fd62ea1a 1097 #endif /* HAL_RCC_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 1098 /**
NYX 0:85b3fd62ea1a 1099 * @}
NYX 0:85b3fd62ea1a 1100 */
NYX 0:85b3fd62ea1a 1101
NYX 0:85b3fd62ea1a 1102 /**
NYX 0:85b3fd62ea1a 1103 * @}
NYX 0:85b3fd62ea1a 1104 */
NYX 0:85b3fd62ea1a 1105
NYX 0:85b3fd62ea1a 1106 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/