Takaaki Numai
inport from local
Dependents: Hobbyking_Cheetah_0511
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h@0:85b3fd62ea1a, 2020-03-16 (annotated)
- Committer:
- NYX
- Date:
- Mon Mar 16 06:35:48 2020 +0000
- Revision:
- 0:85b3fd62ea1a
reinport to mbed;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| NYX | 0:85b3fd62ea1a | 1 | /** |
| NYX | 0:85b3fd62ea1a | 2 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 3 | * @file stm32f4xx_hal_qspi.h |
| NYX | 0:85b3fd62ea1a | 4 | * @author MCD Application Team |
| NYX | 0:85b3fd62ea1a | 5 | * @version V1.7.1 |
| NYX | 0:85b3fd62ea1a | 6 | * @date 14-April-2017 |
| NYX | 0:85b3fd62ea1a | 7 | * @brief Header file of QSPI HAL module. |
| NYX | 0:85b3fd62ea1a | 8 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 9 | * @attention |
| NYX | 0:85b3fd62ea1a | 10 | * |
| NYX | 0:85b3fd62ea1a | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| NYX | 0:85b3fd62ea1a | 12 | * |
| NYX | 0:85b3fd62ea1a | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| NYX | 0:85b3fd62ea1a | 14 | * are permitted provided that the following conditions are met: |
| NYX | 0:85b3fd62ea1a | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| NYX | 0:85b3fd62ea1a | 16 | * this list of conditions and the following disclaimer. |
| NYX | 0:85b3fd62ea1a | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| NYX | 0:85b3fd62ea1a | 18 | * this list of conditions and the following disclaimer in the documentation |
| NYX | 0:85b3fd62ea1a | 19 | * and/or other materials provided with the distribution. |
| NYX | 0:85b3fd62ea1a | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| NYX | 0:85b3fd62ea1a | 21 | * may be used to endorse or promote products derived from this software |
| NYX | 0:85b3fd62ea1a | 22 | * without specific prior written permission. |
| NYX | 0:85b3fd62ea1a | 23 | * |
| NYX | 0:85b3fd62ea1a | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| NYX | 0:85b3fd62ea1a | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| NYX | 0:85b3fd62ea1a | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| NYX | 0:85b3fd62ea1a | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| NYX | 0:85b3fd62ea1a | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| NYX | 0:85b3fd62ea1a | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| NYX | 0:85b3fd62ea1a | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| NYX | 0:85b3fd62ea1a | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| NYX | 0:85b3fd62ea1a | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| NYX | 0:85b3fd62ea1a | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| NYX | 0:85b3fd62ea1a | 34 | * |
| NYX | 0:85b3fd62ea1a | 35 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 36 | */ |
| NYX | 0:85b3fd62ea1a | 37 | |
| NYX | 0:85b3fd62ea1a | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 39 | #ifndef __STM32F4xx_HAL_QSPI_H |
| NYX | 0:85b3fd62ea1a | 40 | #define __STM32F4xx_HAL_QSPI_H |
| NYX | 0:85b3fd62ea1a | 41 | |
| NYX | 0:85b3fd62ea1a | 42 | #ifdef __cplusplus |
| NYX | 0:85b3fd62ea1a | 43 | extern "C" { |
| NYX | 0:85b3fd62ea1a | 44 | #endif |
| NYX | 0:85b3fd62ea1a | 45 | |
| NYX | 0:85b3fd62ea1a | 46 | #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ |
| NYX | 0:85b3fd62ea1a | 47 | defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) |
| NYX | 0:85b3fd62ea1a | 48 | /* Includes ------------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 49 | #include "stm32f4xx_hal_def.h" |
| NYX | 0:85b3fd62ea1a | 50 | |
| NYX | 0:85b3fd62ea1a | 51 | /** @addtogroup STM32F4xx_HAL_Driver |
| NYX | 0:85b3fd62ea1a | 52 | * @{ |
| NYX | 0:85b3fd62ea1a | 53 | */ |
| NYX | 0:85b3fd62ea1a | 54 | |
| NYX | 0:85b3fd62ea1a | 55 | /** @addtogroup QSPI |
| NYX | 0:85b3fd62ea1a | 56 | * @{ |
| NYX | 0:85b3fd62ea1a | 57 | */ |
| NYX | 0:85b3fd62ea1a | 58 | |
| NYX | 0:85b3fd62ea1a | 59 | /* Exported types ------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 60 | /** @defgroup QSPI_Exported_Types QSPI Exported Types |
| NYX | 0:85b3fd62ea1a | 61 | * @{ |
| NYX | 0:85b3fd62ea1a | 62 | */ |
| NYX | 0:85b3fd62ea1a | 63 | |
| NYX | 0:85b3fd62ea1a | 64 | /** |
| NYX | 0:85b3fd62ea1a | 65 | * @brief QSPI Init structure definition |
| NYX | 0:85b3fd62ea1a | 66 | */ |
| NYX | 0:85b3fd62ea1a | 67 | |
| NYX | 0:85b3fd62ea1a | 68 | typedef struct |
| NYX | 0:85b3fd62ea1a | 69 | { |
| NYX | 0:85b3fd62ea1a | 70 | uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. |
| NYX | 0:85b3fd62ea1a | 71 | This parameter can be a number between 0 and 255 */ |
| NYX | 0:85b3fd62ea1a | 72 | |
| NYX | 0:85b3fd62ea1a | 73 | uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) |
| NYX | 0:85b3fd62ea1a | 74 | This parameter can be a value between 1 and 32 */ |
| NYX | 0:85b3fd62ea1a | 75 | |
| NYX | 0:85b3fd62ea1a | 76 | uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to |
| NYX | 0:85b3fd62ea1a | 77 | take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) |
| NYX | 0:85b3fd62ea1a | 78 | This parameter can be a value of @ref QSPI_SampleShifting */ |
| NYX | 0:85b3fd62ea1a | 79 | |
| NYX | 0:85b3fd62ea1a | 80 | uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits |
| NYX | 0:85b3fd62ea1a | 81 | required to address the flash memory. The flash capacity can be up to 4GB |
| NYX | 0:85b3fd62ea1a | 82 | (addressed using 32 bits) in indirect mode, but the addressable space in |
| NYX | 0:85b3fd62ea1a | 83 | memory-mapped mode is limited to 256MB |
| NYX | 0:85b3fd62ea1a | 84 | This parameter can be a number between 0 and 31 */ |
| NYX | 0:85b3fd62ea1a | 85 | |
| NYX | 0:85b3fd62ea1a | 86 | uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number |
| NYX | 0:85b3fd62ea1a | 87 | of clock cycles which the chip select must remain high between commands. |
| NYX | 0:85b3fd62ea1a | 88 | This parameter can be a value of @ref QSPI_ChipSelectHighTime */ |
| NYX | 0:85b3fd62ea1a | 89 | |
| NYX | 0:85b3fd62ea1a | 90 | uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. |
| NYX | 0:85b3fd62ea1a | 91 | This parameter can be a value of @ref QSPI_ClockMode */ |
| NYX | 0:85b3fd62ea1a | 92 | |
| NYX | 0:85b3fd62ea1a | 93 | uint32_t FlashID; /* Specifies the Flash which will be used, |
| NYX | 0:85b3fd62ea1a | 94 | This parameter can be a value of @ref QSPI_Flash_Select */ |
| NYX | 0:85b3fd62ea1a | 95 | |
| NYX | 0:85b3fd62ea1a | 96 | uint32_t DualFlash; /* Specifies the Dual Flash Mode State |
| NYX | 0:85b3fd62ea1a | 97 | This parameter can be a value of @ref QSPI_DualFlash_Mode */ |
| NYX | 0:85b3fd62ea1a | 98 | }QSPI_InitTypeDef; |
| NYX | 0:85b3fd62ea1a | 99 | |
| NYX | 0:85b3fd62ea1a | 100 | /** |
| NYX | 0:85b3fd62ea1a | 101 | * @brief HAL QSPI State structures definition |
| NYX | 0:85b3fd62ea1a | 102 | */ |
| NYX | 0:85b3fd62ea1a | 103 | typedef enum |
| NYX | 0:85b3fd62ea1a | 104 | { |
| NYX | 0:85b3fd62ea1a | 105 | HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ |
| NYX | 0:85b3fd62ea1a | 106 | HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ |
| NYX | 0:85b3fd62ea1a | 107 | HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ |
| NYX | 0:85b3fd62ea1a | 108 | HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ |
| NYX | 0:85b3fd62ea1a | 109 | HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ |
| NYX | 0:85b3fd62ea1a | 110 | HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ |
| NYX | 0:85b3fd62ea1a | 111 | HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ |
| NYX | 0:85b3fd62ea1a | 112 | HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ |
| NYX | 0:85b3fd62ea1a | 113 | HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ |
| NYX | 0:85b3fd62ea1a | 114 | }HAL_QSPI_StateTypeDef; |
| NYX | 0:85b3fd62ea1a | 115 | |
| NYX | 0:85b3fd62ea1a | 116 | /** |
| NYX | 0:85b3fd62ea1a | 117 | * @brief QSPI Handle Structure definition |
| NYX | 0:85b3fd62ea1a | 118 | */ |
| NYX | 0:85b3fd62ea1a | 119 | typedef struct |
| NYX | 0:85b3fd62ea1a | 120 | { |
| NYX | 0:85b3fd62ea1a | 121 | QUADSPI_TypeDef *Instance; /* QSPI registers base address */ |
| NYX | 0:85b3fd62ea1a | 122 | QSPI_InitTypeDef Init; /* QSPI communication parameters */ |
| NYX | 0:85b3fd62ea1a | 123 | uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ |
| NYX | 0:85b3fd62ea1a | 124 | __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ |
| NYX | 0:85b3fd62ea1a | 125 | __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ |
| NYX | 0:85b3fd62ea1a | 126 | uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ |
| NYX | 0:85b3fd62ea1a | 127 | __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ |
| NYX | 0:85b3fd62ea1a | 128 | __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ |
| NYX | 0:85b3fd62ea1a | 129 | DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ |
| NYX | 0:85b3fd62ea1a | 130 | __IO HAL_LockTypeDef Lock; /* Locking object */ |
| NYX | 0:85b3fd62ea1a | 131 | __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ |
| NYX | 0:85b3fd62ea1a | 132 | __IO uint32_t ErrorCode; /* QSPI Error code */ |
| NYX | 0:85b3fd62ea1a | 133 | uint32_t Timeout; /* Timeout for the QSPI memory access */ |
| NYX | 0:85b3fd62ea1a | 134 | }QSPI_HandleTypeDef; |
| NYX | 0:85b3fd62ea1a | 135 | |
| NYX | 0:85b3fd62ea1a | 136 | /** |
| NYX | 0:85b3fd62ea1a | 137 | * @brief QSPI Command structure definition |
| NYX | 0:85b3fd62ea1a | 138 | */ |
| NYX | 0:85b3fd62ea1a | 139 | typedef struct |
| NYX | 0:85b3fd62ea1a | 140 | { |
| NYX | 0:85b3fd62ea1a | 141 | uint32_t Instruction; /* Specifies the Instruction to be sent |
| NYX | 0:85b3fd62ea1a | 142 | This parameter can be a value (8-bit) between 0x00 and 0xFF */ |
| NYX | 0:85b3fd62ea1a | 143 | uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) |
| NYX | 0:85b3fd62ea1a | 144 | This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ |
| NYX | 0:85b3fd62ea1a | 145 | uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) |
| NYX | 0:85b3fd62ea1a | 146 | This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ |
| NYX | 0:85b3fd62ea1a | 147 | uint32_t AddressSize; /* Specifies the Address Size |
| NYX | 0:85b3fd62ea1a | 148 | This parameter can be a value of @ref QSPI_AddressSize */ |
| NYX | 0:85b3fd62ea1a | 149 | uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size |
| NYX | 0:85b3fd62ea1a | 150 | This parameter can be a value of @ref QSPI_AlternateBytesSize */ |
| NYX | 0:85b3fd62ea1a | 151 | uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. |
| NYX | 0:85b3fd62ea1a | 152 | This parameter can be a number between 0 and 31 */ |
| NYX | 0:85b3fd62ea1a | 153 | uint32_t InstructionMode; /* Specifies the Instruction Mode |
| NYX | 0:85b3fd62ea1a | 154 | This parameter can be a value of @ref QSPI_InstructionMode */ |
| NYX | 0:85b3fd62ea1a | 155 | uint32_t AddressMode; /* Specifies the Address Mode |
| NYX | 0:85b3fd62ea1a | 156 | This parameter can be a value of @ref QSPI_AddressMode */ |
| NYX | 0:85b3fd62ea1a | 157 | uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode |
| NYX | 0:85b3fd62ea1a | 158 | This parameter can be a value of @ref QSPI_AlternateBytesMode */ |
| NYX | 0:85b3fd62ea1a | 159 | uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) |
| NYX | 0:85b3fd62ea1a | 160 | This parameter can be a value of @ref QSPI_DataMode */ |
| NYX | 0:85b3fd62ea1a | 161 | uint32_t NbData; /* Specifies the number of data to transfer. |
| NYX | 0:85b3fd62ea1a | 162 | This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length |
| NYX | 0:85b3fd62ea1a | 163 | until end of memory)*/ |
| NYX | 0:85b3fd62ea1a | 164 | uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase |
| NYX | 0:85b3fd62ea1a | 165 | This parameter can be a value of @ref QSPI_DdrMode */ |
| NYX | 0:85b3fd62ea1a | 166 | uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of |
| NYX | 0:85b3fd62ea1a | 167 | system clock in DDR mode. |
| NYX | 0:85b3fd62ea1a | 168 | This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ |
| NYX | 0:85b3fd62ea1a | 169 | uint32_t SIOOMode; /* Specifies the send instruction only once mode |
| NYX | 0:85b3fd62ea1a | 170 | This parameter can be a value of @ref QSPI_SIOOMode */ |
| NYX | 0:85b3fd62ea1a | 171 | }QSPI_CommandTypeDef; |
| NYX | 0:85b3fd62ea1a | 172 | |
| NYX | 0:85b3fd62ea1a | 173 | /** |
| NYX | 0:85b3fd62ea1a | 174 | * @brief QSPI Auto Polling mode configuration structure definition |
| NYX | 0:85b3fd62ea1a | 175 | */ |
| NYX | 0:85b3fd62ea1a | 176 | typedef struct |
| NYX | 0:85b3fd62ea1a | 177 | { |
| NYX | 0:85b3fd62ea1a | 178 | uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. |
| NYX | 0:85b3fd62ea1a | 179 | This parameter can be any value between 0 and 0xFFFFFFFFU */ |
| NYX | 0:85b3fd62ea1a | 180 | uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. |
| NYX | 0:85b3fd62ea1a | 181 | This parameter can be any value between 0 and 0xFFFFFFFFU */ |
| NYX | 0:85b3fd62ea1a | 182 | uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. |
| NYX | 0:85b3fd62ea1a | 183 | This parameter can be any value between 0 and 0xFFFFU */ |
| NYX | 0:85b3fd62ea1a | 184 | uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. |
| NYX | 0:85b3fd62ea1a | 185 | This parameter can be any value between 1 and 4 */ |
| NYX | 0:85b3fd62ea1a | 186 | uint32_t MatchMode; /* Specifies the method used for determining a match. |
| NYX | 0:85b3fd62ea1a | 187 | This parameter can be a value of @ref QSPI_MatchMode */ |
| NYX | 0:85b3fd62ea1a | 188 | uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. |
| NYX | 0:85b3fd62ea1a | 189 | This parameter can be a value of @ref QSPI_AutomaticStop */ |
| NYX | 0:85b3fd62ea1a | 190 | }QSPI_AutoPollingTypeDef; |
| NYX | 0:85b3fd62ea1a | 191 | |
| NYX | 0:85b3fd62ea1a | 192 | /** |
| NYX | 0:85b3fd62ea1a | 193 | * @brief QSPI Memory Mapped mode configuration structure definition |
| NYX | 0:85b3fd62ea1a | 194 | */ |
| NYX | 0:85b3fd62ea1a | 195 | typedef struct |
| NYX | 0:85b3fd62ea1a | 196 | { |
| NYX | 0:85b3fd62ea1a | 197 | uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. |
| NYX | 0:85b3fd62ea1a | 198 | This parameter can be any value between 0 and 0xFFFFU */ |
| NYX | 0:85b3fd62ea1a | 199 | uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. |
| NYX | 0:85b3fd62ea1a | 200 | This parameter can be a value of @ref QSPI_TimeOutActivation */ |
| NYX | 0:85b3fd62ea1a | 201 | }QSPI_MemoryMappedTypeDef; |
| NYX | 0:85b3fd62ea1a | 202 | /** |
| NYX | 0:85b3fd62ea1a | 203 | * @} |
| NYX | 0:85b3fd62ea1a | 204 | */ |
| NYX | 0:85b3fd62ea1a | 205 | |
| NYX | 0:85b3fd62ea1a | 206 | /* Exported constants --------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 207 | /** @defgroup QSPI_Exported_Constants QSPI Exported Constants |
| NYX | 0:85b3fd62ea1a | 208 | * @{ |
| NYX | 0:85b3fd62ea1a | 209 | */ |
| NYX | 0:85b3fd62ea1a | 210 | /** @defgroup QSPI_ErrorCode QSPI Error Code |
| NYX | 0:85b3fd62ea1a | 211 | * @{ |
| NYX | 0:85b3fd62ea1a | 212 | */ |
| NYX | 0:85b3fd62ea1a | 213 | #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ |
| NYX | 0:85b3fd62ea1a | 214 | #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ |
| NYX | 0:85b3fd62ea1a | 215 | #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ |
| NYX | 0:85b3fd62ea1a | 216 | #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ |
| NYX | 0:85b3fd62ea1a | 217 | #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ |
| NYX | 0:85b3fd62ea1a | 218 | /** |
| NYX | 0:85b3fd62ea1a | 219 | * @} |
| NYX | 0:85b3fd62ea1a | 220 | */ |
| NYX | 0:85b3fd62ea1a | 221 | |
| NYX | 0:85b3fd62ea1a | 222 | /** @defgroup QSPI_SampleShifting QSPI Sample Shifting |
| NYX | 0:85b3fd62ea1a | 223 | * @{ |
| NYX | 0:85b3fd62ea1a | 224 | */ |
| NYX | 0:85b3fd62ea1a | 225 | #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ |
| NYX | 0:85b3fd62ea1a | 226 | #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ |
| NYX | 0:85b3fd62ea1a | 227 | /** |
| NYX | 0:85b3fd62ea1a | 228 | * @} |
| NYX | 0:85b3fd62ea1a | 229 | */ |
| NYX | 0:85b3fd62ea1a | 230 | |
| NYX | 0:85b3fd62ea1a | 231 | /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time |
| NYX | 0:85b3fd62ea1a | 232 | * @{ |
| NYX | 0:85b3fd62ea1a | 233 | */ |
| NYX | 0:85b3fd62ea1a | 234 | #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ |
| NYX | 0:85b3fd62ea1a | 235 | #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ |
| NYX | 0:85b3fd62ea1a | 236 | #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ |
| NYX | 0:85b3fd62ea1a | 237 | #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ |
| NYX | 0:85b3fd62ea1a | 238 | #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ |
| NYX | 0:85b3fd62ea1a | 239 | #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ |
| NYX | 0:85b3fd62ea1a | 240 | #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ |
| NYX | 0:85b3fd62ea1a | 241 | #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ |
| NYX | 0:85b3fd62ea1a | 242 | /** |
| NYX | 0:85b3fd62ea1a | 243 | * @} |
| NYX | 0:85b3fd62ea1a | 244 | */ |
| NYX | 0:85b3fd62ea1a | 245 | |
| NYX | 0:85b3fd62ea1a | 246 | /** @defgroup QSPI_ClockMode QSPI Clock Mode |
| NYX | 0:85b3fd62ea1a | 247 | * @{ |
| NYX | 0:85b3fd62ea1a | 248 | */ |
| NYX | 0:85b3fd62ea1a | 249 | #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ |
| NYX | 0:85b3fd62ea1a | 250 | #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ |
| NYX | 0:85b3fd62ea1a | 251 | /** |
| NYX | 0:85b3fd62ea1a | 252 | * @} |
| NYX | 0:85b3fd62ea1a | 253 | */ |
| NYX | 0:85b3fd62ea1a | 254 | |
| NYX | 0:85b3fd62ea1a | 255 | /** @defgroup QSPI_Flash_Select QSPI Flash Select |
| NYX | 0:85b3fd62ea1a | 256 | * @{ |
| NYX | 0:85b3fd62ea1a | 257 | */ |
| NYX | 0:85b3fd62ea1a | 258 | #define QSPI_FLASH_ID_1 0x00000000U |
| NYX | 0:85b3fd62ea1a | 259 | #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) |
| NYX | 0:85b3fd62ea1a | 260 | /** |
| NYX | 0:85b3fd62ea1a | 261 | * @} |
| NYX | 0:85b3fd62ea1a | 262 | */ |
| NYX | 0:85b3fd62ea1a | 263 | |
| NYX | 0:85b3fd62ea1a | 264 | /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode |
| NYX | 0:85b3fd62ea1a | 265 | * @{ |
| NYX | 0:85b3fd62ea1a | 266 | */ |
| NYX | 0:85b3fd62ea1a | 267 | #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) |
| NYX | 0:85b3fd62ea1a | 268 | #define QSPI_DUALFLASH_DISABLE 0x00000000U |
| NYX | 0:85b3fd62ea1a | 269 | /** |
| NYX | 0:85b3fd62ea1a | 270 | * @} |
| NYX | 0:85b3fd62ea1a | 271 | */ |
| NYX | 0:85b3fd62ea1a | 272 | |
| NYX | 0:85b3fd62ea1a | 273 | /** @defgroup QSPI_AddressSize QSPI Address Size |
| NYX | 0:85b3fd62ea1a | 274 | * @{ |
| NYX | 0:85b3fd62ea1a | 275 | */ |
| NYX | 0:85b3fd62ea1a | 276 | #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ |
| NYX | 0:85b3fd62ea1a | 277 | #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ |
| NYX | 0:85b3fd62ea1a | 278 | #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ |
| NYX | 0:85b3fd62ea1a | 279 | #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ |
| NYX | 0:85b3fd62ea1a | 280 | /** |
| NYX | 0:85b3fd62ea1a | 281 | * @} |
| NYX | 0:85b3fd62ea1a | 282 | */ |
| NYX | 0:85b3fd62ea1a | 283 | |
| NYX | 0:85b3fd62ea1a | 284 | /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size |
| NYX | 0:85b3fd62ea1a | 285 | * @{ |
| NYX | 0:85b3fd62ea1a | 286 | */ |
| NYX | 0:85b3fd62ea1a | 287 | #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ |
| NYX | 0:85b3fd62ea1a | 288 | #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ |
| NYX | 0:85b3fd62ea1a | 289 | #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ |
| NYX | 0:85b3fd62ea1a | 290 | #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ |
| NYX | 0:85b3fd62ea1a | 291 | /** |
| NYX | 0:85b3fd62ea1a | 292 | * @} |
| NYX | 0:85b3fd62ea1a | 293 | */ |
| NYX | 0:85b3fd62ea1a | 294 | |
| NYX | 0:85b3fd62ea1a | 295 | /** @defgroup QSPI_InstructionMode QSPI Instruction Mode |
| NYX | 0:85b3fd62ea1a | 296 | * @{ |
| NYX | 0:85b3fd62ea1a | 297 | */ |
| NYX | 0:85b3fd62ea1a | 298 | #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ |
| NYX | 0:85b3fd62ea1a | 299 | #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ |
| NYX | 0:85b3fd62ea1a | 300 | #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ |
| NYX | 0:85b3fd62ea1a | 301 | #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ |
| NYX | 0:85b3fd62ea1a | 302 | /** |
| NYX | 0:85b3fd62ea1a | 303 | * @} |
| NYX | 0:85b3fd62ea1a | 304 | */ |
| NYX | 0:85b3fd62ea1a | 305 | |
| NYX | 0:85b3fd62ea1a | 306 | /** @defgroup QSPI_AddressMode QSPI Address Mode |
| NYX | 0:85b3fd62ea1a | 307 | * @{ |
| NYX | 0:85b3fd62ea1a | 308 | */ |
| NYX | 0:85b3fd62ea1a | 309 | #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ |
| NYX | 0:85b3fd62ea1a | 310 | #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ |
| NYX | 0:85b3fd62ea1a | 311 | #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ |
| NYX | 0:85b3fd62ea1a | 312 | #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ |
| NYX | 0:85b3fd62ea1a | 313 | /** |
| NYX | 0:85b3fd62ea1a | 314 | * @} |
| NYX | 0:85b3fd62ea1a | 315 | */ |
| NYX | 0:85b3fd62ea1a | 316 | |
| NYX | 0:85b3fd62ea1a | 317 | /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode |
| NYX | 0:85b3fd62ea1a | 318 | * @{ |
| NYX | 0:85b3fd62ea1a | 319 | */ |
| NYX | 0:85b3fd62ea1a | 320 | #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ |
| NYX | 0:85b3fd62ea1a | 321 | #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ |
| NYX | 0:85b3fd62ea1a | 322 | #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ |
| NYX | 0:85b3fd62ea1a | 323 | #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ |
| NYX | 0:85b3fd62ea1a | 324 | /** |
| NYX | 0:85b3fd62ea1a | 325 | * @} |
| NYX | 0:85b3fd62ea1a | 326 | */ |
| NYX | 0:85b3fd62ea1a | 327 | |
| NYX | 0:85b3fd62ea1a | 328 | /** @defgroup QSPI_DataMode QSPI Data Mode |
| NYX | 0:85b3fd62ea1a | 329 | * @{ |
| NYX | 0:85b3fd62ea1a | 330 | */ |
| NYX | 0:85b3fd62ea1a | 331 | #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ |
| NYX | 0:85b3fd62ea1a | 332 | #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ |
| NYX | 0:85b3fd62ea1a | 333 | #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ |
| NYX | 0:85b3fd62ea1a | 334 | #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ |
| NYX | 0:85b3fd62ea1a | 335 | /** |
| NYX | 0:85b3fd62ea1a | 336 | * @} |
| NYX | 0:85b3fd62ea1a | 337 | */ |
| NYX | 0:85b3fd62ea1a | 338 | |
| NYX | 0:85b3fd62ea1a | 339 | /** @defgroup QSPI_DdrMode QSPI Ddr Mode |
| NYX | 0:85b3fd62ea1a | 340 | * @{ |
| NYX | 0:85b3fd62ea1a | 341 | */ |
| NYX | 0:85b3fd62ea1a | 342 | #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ |
| NYX | 0:85b3fd62ea1a | 343 | #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ |
| NYX | 0:85b3fd62ea1a | 344 | /** |
| NYX | 0:85b3fd62ea1a | 345 | * @} |
| NYX | 0:85b3fd62ea1a | 346 | */ |
| NYX | 0:85b3fd62ea1a | 347 | |
| NYX | 0:85b3fd62ea1a | 348 | /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle |
| NYX | 0:85b3fd62ea1a | 349 | * @{ |
| NYX | 0:85b3fd62ea1a | 350 | */ |
| NYX | 0:85b3fd62ea1a | 351 | #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ |
| NYX | 0:85b3fd62ea1a | 352 | #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/ |
| NYX | 0:85b3fd62ea1a | 353 | /** |
| NYX | 0:85b3fd62ea1a | 354 | * @} |
| NYX | 0:85b3fd62ea1a | 355 | */ |
| NYX | 0:85b3fd62ea1a | 356 | |
| NYX | 0:85b3fd62ea1a | 357 | /** @defgroup QSPI_SIOOMode QSPI SIOO Mode |
| NYX | 0:85b3fd62ea1a | 358 | * @{ |
| NYX | 0:85b3fd62ea1a | 359 | */ |
| NYX | 0:85b3fd62ea1a | 360 | #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ |
| NYX | 0:85b3fd62ea1a | 361 | #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ |
| NYX | 0:85b3fd62ea1a | 362 | /** |
| NYX | 0:85b3fd62ea1a | 363 | * @} |
| NYX | 0:85b3fd62ea1a | 364 | */ |
| NYX | 0:85b3fd62ea1a | 365 | |
| NYX | 0:85b3fd62ea1a | 366 | /** @defgroup QSPI_MatchMode QSPI Match Mode |
| NYX | 0:85b3fd62ea1a | 367 | * @{ |
| NYX | 0:85b3fd62ea1a | 368 | */ |
| NYX | 0:85b3fd62ea1a | 369 | #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ |
| NYX | 0:85b3fd62ea1a | 370 | #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ |
| NYX | 0:85b3fd62ea1a | 371 | /** |
| NYX | 0:85b3fd62ea1a | 372 | * @} |
| NYX | 0:85b3fd62ea1a | 373 | */ |
| NYX | 0:85b3fd62ea1a | 374 | |
| NYX | 0:85b3fd62ea1a | 375 | /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop |
| NYX | 0:85b3fd62ea1a | 376 | * @{ |
| NYX | 0:85b3fd62ea1a | 377 | */ |
| NYX | 0:85b3fd62ea1a | 378 | #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ |
| NYX | 0:85b3fd62ea1a | 379 | #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ |
| NYX | 0:85b3fd62ea1a | 380 | /** |
| NYX | 0:85b3fd62ea1a | 381 | * @} |
| NYX | 0:85b3fd62ea1a | 382 | */ |
| NYX | 0:85b3fd62ea1a | 383 | |
| NYX | 0:85b3fd62ea1a | 384 | /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation |
| NYX | 0:85b3fd62ea1a | 385 | * @{ |
| NYX | 0:85b3fd62ea1a | 386 | */ |
| NYX | 0:85b3fd62ea1a | 387 | #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ |
| NYX | 0:85b3fd62ea1a | 388 | #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ |
| NYX | 0:85b3fd62ea1a | 389 | /** |
| NYX | 0:85b3fd62ea1a | 390 | * @} |
| NYX | 0:85b3fd62ea1a | 391 | */ |
| NYX | 0:85b3fd62ea1a | 392 | |
| NYX | 0:85b3fd62ea1a | 393 | /** @defgroup QSPI_Flags QSPI Flags |
| NYX | 0:85b3fd62ea1a | 394 | * @{ |
| NYX | 0:85b3fd62ea1a | 395 | */ |
| NYX | 0:85b3fd62ea1a | 396 | #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ |
| NYX | 0:85b3fd62ea1a | 397 | #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ |
| NYX | 0:85b3fd62ea1a | 398 | #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ |
| NYX | 0:85b3fd62ea1a | 399 | #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ |
| NYX | 0:85b3fd62ea1a | 400 | #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ |
| NYX | 0:85b3fd62ea1a | 401 | #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ |
| NYX | 0:85b3fd62ea1a | 402 | /** |
| NYX | 0:85b3fd62ea1a | 403 | * @} |
| NYX | 0:85b3fd62ea1a | 404 | */ |
| NYX | 0:85b3fd62ea1a | 405 | |
| NYX | 0:85b3fd62ea1a | 406 | /** @defgroup QSPI_Interrupts QSPI Interrupts |
| NYX | 0:85b3fd62ea1a | 407 | * @{ |
| NYX | 0:85b3fd62ea1a | 408 | */ |
| NYX | 0:85b3fd62ea1a | 409 | #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ |
| NYX | 0:85b3fd62ea1a | 410 | #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ |
| NYX | 0:85b3fd62ea1a | 411 | #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ |
| NYX | 0:85b3fd62ea1a | 412 | #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ |
| NYX | 0:85b3fd62ea1a | 413 | #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ |
| NYX | 0:85b3fd62ea1a | 414 | /** |
| NYX | 0:85b3fd62ea1a | 415 | * @} |
| NYX | 0:85b3fd62ea1a | 416 | */ |
| NYX | 0:85b3fd62ea1a | 417 | |
| NYX | 0:85b3fd62ea1a | 418 | /** @defgroup QSPI_Timeout_definition QSPI Timeout definition |
| NYX | 0:85b3fd62ea1a | 419 | * @{ |
| NYX | 0:85b3fd62ea1a | 420 | */ |
| NYX | 0:85b3fd62ea1a | 421 | #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ |
| NYX | 0:85b3fd62ea1a | 422 | /** |
| NYX | 0:85b3fd62ea1a | 423 | * @} |
| NYX | 0:85b3fd62ea1a | 424 | */ |
| NYX | 0:85b3fd62ea1a | 425 | |
| NYX | 0:85b3fd62ea1a | 426 | /** |
| NYX | 0:85b3fd62ea1a | 427 | * @} |
| NYX | 0:85b3fd62ea1a | 428 | */ |
| NYX | 0:85b3fd62ea1a | 429 | |
| NYX | 0:85b3fd62ea1a | 430 | /* Exported macros -----------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 431 | /** @defgroup QSPI_Exported_Macros QSPI Exported Macros |
| NYX | 0:85b3fd62ea1a | 432 | * @{ |
| NYX | 0:85b3fd62ea1a | 433 | */ |
| NYX | 0:85b3fd62ea1a | 434 | |
| NYX | 0:85b3fd62ea1a | 435 | /** @brief Reset QSPI handle state |
| NYX | 0:85b3fd62ea1a | 436 | * @param __HANDLE__: QSPI handle. |
| NYX | 0:85b3fd62ea1a | 437 | * @retval None |
| NYX | 0:85b3fd62ea1a | 438 | */ |
| NYX | 0:85b3fd62ea1a | 439 | #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) |
| NYX | 0:85b3fd62ea1a | 440 | |
| NYX | 0:85b3fd62ea1a | 441 | /** @brief Enable QSPI |
| NYX | 0:85b3fd62ea1a | 442 | * @param __HANDLE__: specifies the QSPI Handle. |
| NYX | 0:85b3fd62ea1a | 443 | * @retval None |
| NYX | 0:85b3fd62ea1a | 444 | */ |
| NYX | 0:85b3fd62ea1a | 445 | #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
| NYX | 0:85b3fd62ea1a | 446 | |
| NYX | 0:85b3fd62ea1a | 447 | /** @brief Disable QSPI |
| NYX | 0:85b3fd62ea1a | 448 | * @param __HANDLE__: specifies the QSPI Handle. |
| NYX | 0:85b3fd62ea1a | 449 | * @retval None |
| NYX | 0:85b3fd62ea1a | 450 | */ |
| NYX | 0:85b3fd62ea1a | 451 | #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
| NYX | 0:85b3fd62ea1a | 452 | |
| NYX | 0:85b3fd62ea1a | 453 | /** @brief Enables the specified QSPI interrupt. |
| NYX | 0:85b3fd62ea1a | 454 | * @param __HANDLE__: specifies the QSPI Handle. |
| NYX | 0:85b3fd62ea1a | 455 | * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. |
| NYX | 0:85b3fd62ea1a | 456 | * This parameter can be one of the following values: |
| NYX | 0:85b3fd62ea1a | 457 | * @arg QSPI_IT_TO: QSPI Time out interrupt |
| NYX | 0:85b3fd62ea1a | 458 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
| NYX | 0:85b3fd62ea1a | 459 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
| NYX | 0:85b3fd62ea1a | 460 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
| NYX | 0:85b3fd62ea1a | 461 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
| NYX | 0:85b3fd62ea1a | 462 | * @retval None |
| NYX | 0:85b3fd62ea1a | 463 | */ |
| NYX | 0:85b3fd62ea1a | 464 | #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
| NYX | 0:85b3fd62ea1a | 465 | |
| NYX | 0:85b3fd62ea1a | 466 | |
| NYX | 0:85b3fd62ea1a | 467 | /** @brief Disables the specified QSPI interrupt. |
| NYX | 0:85b3fd62ea1a | 468 | * @param __HANDLE__: specifies the QSPI Handle. |
| NYX | 0:85b3fd62ea1a | 469 | * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. |
| NYX | 0:85b3fd62ea1a | 470 | * This parameter can be one of the following values: |
| NYX | 0:85b3fd62ea1a | 471 | * @arg QSPI_IT_TO: QSPI Timeout interrupt |
| NYX | 0:85b3fd62ea1a | 472 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
| NYX | 0:85b3fd62ea1a | 473 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
| NYX | 0:85b3fd62ea1a | 474 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
| NYX | 0:85b3fd62ea1a | 475 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
| NYX | 0:85b3fd62ea1a | 476 | * @retval None |
| NYX | 0:85b3fd62ea1a | 477 | */ |
| NYX | 0:85b3fd62ea1a | 478 | #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
| NYX | 0:85b3fd62ea1a | 479 | |
| NYX | 0:85b3fd62ea1a | 480 | /** @brief Checks whether the specified QSPI interrupt source is enabled. |
| NYX | 0:85b3fd62ea1a | 481 | * @param __HANDLE__: specifies the QSPI Handle. |
| NYX | 0:85b3fd62ea1a | 482 | * @param __INTERRUPT__: specifies the QSPI interrupt source to check. |
| NYX | 0:85b3fd62ea1a | 483 | * This parameter can be one of the following values: |
| NYX | 0:85b3fd62ea1a | 484 | * @arg QSPI_IT_TO: QSPI Time out interrupt |
| NYX | 0:85b3fd62ea1a | 485 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
| NYX | 0:85b3fd62ea1a | 486 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
| NYX | 0:85b3fd62ea1a | 487 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
| NYX | 0:85b3fd62ea1a | 488 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
| NYX | 0:85b3fd62ea1a | 489 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
| NYX | 0:85b3fd62ea1a | 490 | */ |
| NYX | 0:85b3fd62ea1a | 491 | #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) |
| NYX | 0:85b3fd62ea1a | 492 | |
| NYX | 0:85b3fd62ea1a | 493 | /** |
| NYX | 0:85b3fd62ea1a | 494 | * @brief Get the selected QSPI's flag status. |
| NYX | 0:85b3fd62ea1a | 495 | * @param __HANDLE__: specifies the QSPI Handle. |
| NYX | 0:85b3fd62ea1a | 496 | * @param __FLAG__: specifies the QSPI flag to check. |
| NYX | 0:85b3fd62ea1a | 497 | * This parameter can be one of the following values: |
| NYX | 0:85b3fd62ea1a | 498 | * @arg QSPI_FLAG_BUSY: QSPI Busy flag |
| NYX | 0:85b3fd62ea1a | 499 | * @arg QSPI_FLAG_TO: QSPI Time out flag |
| NYX | 0:85b3fd62ea1a | 500 | * @arg QSPI_FLAG_SM: QSPI Status match flag |
| NYX | 0:85b3fd62ea1a | 501 | * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag |
| NYX | 0:85b3fd62ea1a | 502 | * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
| NYX | 0:85b3fd62ea1a | 503 | * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
| NYX | 0:85b3fd62ea1a | 504 | * @retval None |
| NYX | 0:85b3fd62ea1a | 505 | */ |
| NYX | 0:85b3fd62ea1a | 506 | #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) |
| NYX | 0:85b3fd62ea1a | 507 | |
| NYX | 0:85b3fd62ea1a | 508 | /** @brief Clears the specified QSPI's flag status. |
| NYX | 0:85b3fd62ea1a | 509 | * @param __HANDLE__: specifies the QSPI Handle. |
| NYX | 0:85b3fd62ea1a | 510 | * @param __FLAG__: specifies the QSPI clear register flag that needs to be set |
| NYX | 0:85b3fd62ea1a | 511 | * This parameter can be one of the following values: |
| NYX | 0:85b3fd62ea1a | 512 | * @arg QSPI_FLAG_TO: QSPI Time out flag |
| NYX | 0:85b3fd62ea1a | 513 | * @arg QSPI_FLAG_SM: QSPI Status match flag |
| NYX | 0:85b3fd62ea1a | 514 | * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
| NYX | 0:85b3fd62ea1a | 515 | * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
| NYX | 0:85b3fd62ea1a | 516 | * @retval None |
| NYX | 0:85b3fd62ea1a | 517 | */ |
| NYX | 0:85b3fd62ea1a | 518 | #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) |
| NYX | 0:85b3fd62ea1a | 519 | /** |
| NYX | 0:85b3fd62ea1a | 520 | * @} |
| NYX | 0:85b3fd62ea1a | 521 | */ |
| NYX | 0:85b3fd62ea1a | 522 | |
| NYX | 0:85b3fd62ea1a | 523 | /* Exported functions --------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 524 | /** @addtogroup QSPI_Exported_Functions |
| NYX | 0:85b3fd62ea1a | 525 | * @{ |
| NYX | 0:85b3fd62ea1a | 526 | */ |
| NYX | 0:85b3fd62ea1a | 527 | |
| NYX | 0:85b3fd62ea1a | 528 | /** @addtogroup QSPI_Exported_Functions_Group1 |
| NYX | 0:85b3fd62ea1a | 529 | * @{ |
| NYX | 0:85b3fd62ea1a | 530 | */ |
| NYX | 0:85b3fd62ea1a | 531 | /* Initialization/de-initialization functions ********************************/ |
| NYX | 0:85b3fd62ea1a | 532 | HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 533 | HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 534 | void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 535 | void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 536 | /** |
| NYX | 0:85b3fd62ea1a | 537 | * @} |
| NYX | 0:85b3fd62ea1a | 538 | */ |
| NYX | 0:85b3fd62ea1a | 539 | |
| NYX | 0:85b3fd62ea1a | 540 | /** @addtogroup QSPI_Exported_Functions_Group2 |
| NYX | 0:85b3fd62ea1a | 541 | * @{ |
| NYX | 0:85b3fd62ea1a | 542 | */ |
| NYX | 0:85b3fd62ea1a | 543 | /* IO operation functions *****************************************************/ |
| NYX | 0:85b3fd62ea1a | 544 | /* QSPI IRQ handler method */ |
| NYX | 0:85b3fd62ea1a | 545 | void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 546 | |
| NYX | 0:85b3fd62ea1a | 547 | /* QSPI indirect mode */ |
| NYX | 0:85b3fd62ea1a | 548 | HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); |
| NYX | 0:85b3fd62ea1a | 549 | HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
| NYX | 0:85b3fd62ea1a | 550 | HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
| NYX | 0:85b3fd62ea1a | 551 | HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); |
| NYX | 0:85b3fd62ea1a | 552 | HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| NYX | 0:85b3fd62ea1a | 553 | HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| NYX | 0:85b3fd62ea1a | 554 | HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| NYX | 0:85b3fd62ea1a | 555 | HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
| NYX | 0:85b3fd62ea1a | 556 | |
| NYX | 0:85b3fd62ea1a | 557 | /* QSPI status flag polling mode */ |
| NYX | 0:85b3fd62ea1a | 558 | HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); |
| NYX | 0:85b3fd62ea1a | 559 | HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); |
| NYX | 0:85b3fd62ea1a | 560 | |
| NYX | 0:85b3fd62ea1a | 561 | /* QSPI memory-mapped mode */ |
| NYX | 0:85b3fd62ea1a | 562 | HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); |
| NYX | 0:85b3fd62ea1a | 563 | /** |
| NYX | 0:85b3fd62ea1a | 564 | * @} |
| NYX | 0:85b3fd62ea1a | 565 | */ |
| NYX | 0:85b3fd62ea1a | 566 | |
| NYX | 0:85b3fd62ea1a | 567 | /** @addtogroup QSPI_Exported_Functions_Group3 |
| NYX | 0:85b3fd62ea1a | 568 | * @{ |
| NYX | 0:85b3fd62ea1a | 569 | */ |
| NYX | 0:85b3fd62ea1a | 570 | /* Callback functions in non-blocking modes ***********************************/ |
| NYX | 0:85b3fd62ea1a | 571 | void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 572 | void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 573 | void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 574 | |
| NYX | 0:85b3fd62ea1a | 575 | /* QSPI indirect mode */ |
| NYX | 0:85b3fd62ea1a | 576 | void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 577 | void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 578 | void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 579 | void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 580 | void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 581 | |
| NYX | 0:85b3fd62ea1a | 582 | /* QSPI status flag polling mode */ |
| NYX | 0:85b3fd62ea1a | 583 | void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 584 | |
| NYX | 0:85b3fd62ea1a | 585 | /* QSPI memory-mapped mode */ |
| NYX | 0:85b3fd62ea1a | 586 | void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 587 | /** |
| NYX | 0:85b3fd62ea1a | 588 | * @} |
| NYX | 0:85b3fd62ea1a | 589 | */ |
| NYX | 0:85b3fd62ea1a | 590 | |
| NYX | 0:85b3fd62ea1a | 591 | /** @addtogroup QSPI_Exported_Functions_Group4 |
| NYX | 0:85b3fd62ea1a | 592 | * @{ |
| NYX | 0:85b3fd62ea1a | 593 | */ |
| NYX | 0:85b3fd62ea1a | 594 | /* Peripheral Control and State functions ************************************/ |
| NYX | 0:85b3fd62ea1a | 595 | HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 596 | uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 597 | HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 598 | HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 599 | void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); |
| NYX | 0:85b3fd62ea1a | 600 | HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); |
| NYX | 0:85b3fd62ea1a | 601 | uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); |
| NYX | 0:85b3fd62ea1a | 602 | /** |
| NYX | 0:85b3fd62ea1a | 603 | * @} |
| NYX | 0:85b3fd62ea1a | 604 | */ |
| NYX | 0:85b3fd62ea1a | 605 | |
| NYX | 0:85b3fd62ea1a | 606 | /* Private macros ------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 607 | /** @defgroup QSPI_Private_Macros QSPI Private Macros |
| NYX | 0:85b3fd62ea1a | 608 | * @{ |
| NYX | 0:85b3fd62ea1a | 609 | */ |
| NYX | 0:85b3fd62ea1a | 610 | /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler |
| NYX | 0:85b3fd62ea1a | 611 | * @{ |
| NYX | 0:85b3fd62ea1a | 612 | */ |
| NYX | 0:85b3fd62ea1a | 613 | #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) |
| NYX | 0:85b3fd62ea1a | 614 | /** |
| NYX | 0:85b3fd62ea1a | 615 | * @} |
| NYX | 0:85b3fd62ea1a | 616 | */ |
| NYX | 0:85b3fd62ea1a | 617 | |
| NYX | 0:85b3fd62ea1a | 618 | /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold |
| NYX | 0:85b3fd62ea1a | 619 | * @{ |
| NYX | 0:85b3fd62ea1a | 620 | */ |
| NYX | 0:85b3fd62ea1a | 621 | #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) |
| NYX | 0:85b3fd62ea1a | 622 | /** |
| NYX | 0:85b3fd62ea1a | 623 | * @} |
| NYX | 0:85b3fd62ea1a | 624 | */ |
| NYX | 0:85b3fd62ea1a | 625 | |
| NYX | 0:85b3fd62ea1a | 626 | #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ |
| NYX | 0:85b3fd62ea1a | 627 | ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) |
| NYX | 0:85b3fd62ea1a | 628 | |
| NYX | 0:85b3fd62ea1a | 629 | /** @defgroup QSPI_FlashSize QSPI Flash Size |
| NYX | 0:85b3fd62ea1a | 630 | * @{ |
| NYX | 0:85b3fd62ea1a | 631 | */ |
| NYX | 0:85b3fd62ea1a | 632 | #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) |
| NYX | 0:85b3fd62ea1a | 633 | /** |
| NYX | 0:85b3fd62ea1a | 634 | * @} |
| NYX | 0:85b3fd62ea1a | 635 | */ |
| NYX | 0:85b3fd62ea1a | 636 | |
| NYX | 0:85b3fd62ea1a | 637 | #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ |
| NYX | 0:85b3fd62ea1a | 638 | ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ |
| NYX | 0:85b3fd62ea1a | 639 | ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ |
| NYX | 0:85b3fd62ea1a | 640 | ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ |
| NYX | 0:85b3fd62ea1a | 641 | ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ |
| NYX | 0:85b3fd62ea1a | 642 | ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ |
| NYX | 0:85b3fd62ea1a | 643 | ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ |
| NYX | 0:85b3fd62ea1a | 644 | ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) |
| NYX | 0:85b3fd62ea1a | 645 | |
| NYX | 0:85b3fd62ea1a | 646 | #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ |
| NYX | 0:85b3fd62ea1a | 647 | ((CLKMODE) == QSPI_CLOCK_MODE_3)) |
| NYX | 0:85b3fd62ea1a | 648 | |
| NYX | 0:85b3fd62ea1a | 649 | #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \ |
| NYX | 0:85b3fd62ea1a | 650 | ((FLA) == QSPI_FLASH_ID_2)) |
| NYX | 0:85b3fd62ea1a | 651 | |
| NYX | 0:85b3fd62ea1a | 652 | #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ |
| NYX | 0:85b3fd62ea1a | 653 | ((MODE) == QSPI_DUALFLASH_DISABLE)) |
| NYX | 0:85b3fd62ea1a | 654 | |
| NYX | 0:85b3fd62ea1a | 655 | |
| NYX | 0:85b3fd62ea1a | 656 | /** @defgroup QSPI_Instruction QSPI Instruction |
| NYX | 0:85b3fd62ea1a | 657 | * @{ |
| NYX | 0:85b3fd62ea1a | 658 | */ |
| NYX | 0:85b3fd62ea1a | 659 | #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) |
| NYX | 0:85b3fd62ea1a | 660 | /** |
| NYX | 0:85b3fd62ea1a | 661 | * @} |
| NYX | 0:85b3fd62ea1a | 662 | */ |
| NYX | 0:85b3fd62ea1a | 663 | |
| NYX | 0:85b3fd62ea1a | 664 | #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ |
| NYX | 0:85b3fd62ea1a | 665 | ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ |
| NYX | 0:85b3fd62ea1a | 666 | ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ |
| NYX | 0:85b3fd62ea1a | 667 | ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) |
| NYX | 0:85b3fd62ea1a | 668 | |
| NYX | 0:85b3fd62ea1a | 669 | #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ |
| NYX | 0:85b3fd62ea1a | 670 | ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ |
| NYX | 0:85b3fd62ea1a | 671 | ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ |
| NYX | 0:85b3fd62ea1a | 672 | ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) |
| NYX | 0:85b3fd62ea1a | 673 | |
| NYX | 0:85b3fd62ea1a | 674 | |
| NYX | 0:85b3fd62ea1a | 675 | /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles |
| NYX | 0:85b3fd62ea1a | 676 | * @{ |
| NYX | 0:85b3fd62ea1a | 677 | */ |
| NYX | 0:85b3fd62ea1a | 678 | #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) |
| NYX | 0:85b3fd62ea1a | 679 | /** |
| NYX | 0:85b3fd62ea1a | 680 | * @} |
| NYX | 0:85b3fd62ea1a | 681 | */ |
| NYX | 0:85b3fd62ea1a | 682 | |
| NYX | 0:85b3fd62ea1a | 683 | #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ |
| NYX | 0:85b3fd62ea1a | 684 | ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ |
| NYX | 0:85b3fd62ea1a | 685 | ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ |
| NYX | 0:85b3fd62ea1a | 686 | ((MODE) == QSPI_INSTRUCTION_4_LINES)) |
| NYX | 0:85b3fd62ea1a | 687 | |
| NYX | 0:85b3fd62ea1a | 688 | #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ |
| NYX | 0:85b3fd62ea1a | 689 | ((MODE) == QSPI_ADDRESS_1_LINE) || \ |
| NYX | 0:85b3fd62ea1a | 690 | ((MODE) == QSPI_ADDRESS_2_LINES) || \ |
| NYX | 0:85b3fd62ea1a | 691 | ((MODE) == QSPI_ADDRESS_4_LINES)) |
| NYX | 0:85b3fd62ea1a | 692 | |
| NYX | 0:85b3fd62ea1a | 693 | #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ |
| NYX | 0:85b3fd62ea1a | 694 | ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ |
| NYX | 0:85b3fd62ea1a | 695 | ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ |
| NYX | 0:85b3fd62ea1a | 696 | ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) |
| NYX | 0:85b3fd62ea1a | 697 | |
| NYX | 0:85b3fd62ea1a | 698 | #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ |
| NYX | 0:85b3fd62ea1a | 699 | ((MODE) == QSPI_DATA_1_LINE) || \ |
| NYX | 0:85b3fd62ea1a | 700 | ((MODE) == QSPI_DATA_2_LINES) || \ |
| NYX | 0:85b3fd62ea1a | 701 | ((MODE) == QSPI_DATA_4_LINES)) |
| NYX | 0:85b3fd62ea1a | 702 | |
| NYX | 0:85b3fd62ea1a | 703 | #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ |
| NYX | 0:85b3fd62ea1a | 704 | ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) |
| NYX | 0:85b3fd62ea1a | 705 | |
| NYX | 0:85b3fd62ea1a | 706 | #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ |
| NYX | 0:85b3fd62ea1a | 707 | ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) |
| NYX | 0:85b3fd62ea1a | 708 | |
| NYX | 0:85b3fd62ea1a | 709 | #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ |
| NYX | 0:85b3fd62ea1a | 710 | ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) |
| NYX | 0:85b3fd62ea1a | 711 | |
| NYX | 0:85b3fd62ea1a | 712 | /** @defgroup QSPI_Interval QSPI Interval |
| NYX | 0:85b3fd62ea1a | 713 | * @{ |
| NYX | 0:85b3fd62ea1a | 714 | */ |
| NYX | 0:85b3fd62ea1a | 715 | #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) |
| NYX | 0:85b3fd62ea1a | 716 | /** |
| NYX | 0:85b3fd62ea1a | 717 | * @} |
| NYX | 0:85b3fd62ea1a | 718 | */ |
| NYX | 0:85b3fd62ea1a | 719 | |
| NYX | 0:85b3fd62ea1a | 720 | /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size |
| NYX | 0:85b3fd62ea1a | 721 | * @{ |
| NYX | 0:85b3fd62ea1a | 722 | */ |
| NYX | 0:85b3fd62ea1a | 723 | #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) |
| NYX | 0:85b3fd62ea1a | 724 | /** |
| NYX | 0:85b3fd62ea1a | 725 | * @} |
| NYX | 0:85b3fd62ea1a | 726 | */ |
| NYX | 0:85b3fd62ea1a | 727 | #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ |
| NYX | 0:85b3fd62ea1a | 728 | ((MODE) == QSPI_MATCH_MODE_OR)) |
| NYX | 0:85b3fd62ea1a | 729 | |
| NYX | 0:85b3fd62ea1a | 730 | #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ |
| NYX | 0:85b3fd62ea1a | 731 | ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) |
| NYX | 0:85b3fd62ea1a | 732 | |
| NYX | 0:85b3fd62ea1a | 733 | #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ |
| NYX | 0:85b3fd62ea1a | 734 | ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) |
| NYX | 0:85b3fd62ea1a | 735 | |
| NYX | 0:85b3fd62ea1a | 736 | /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period |
| NYX | 0:85b3fd62ea1a | 737 | * @{ |
| NYX | 0:85b3fd62ea1a | 738 | */ |
| NYX | 0:85b3fd62ea1a | 739 | #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) |
| NYX | 0:85b3fd62ea1a | 740 | /** |
| NYX | 0:85b3fd62ea1a | 741 | * @} |
| NYX | 0:85b3fd62ea1a | 742 | */ |
| NYX | 0:85b3fd62ea1a | 743 | |
| NYX | 0:85b3fd62ea1a | 744 | #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \ |
| NYX | 0:85b3fd62ea1a | 745 | ((FLAG) == QSPI_FLAG_TO) || \ |
| NYX | 0:85b3fd62ea1a | 746 | ((FLAG) == QSPI_FLAG_SM) || \ |
| NYX | 0:85b3fd62ea1a | 747 | ((FLAG) == QSPI_FLAG_FT) || \ |
| NYX | 0:85b3fd62ea1a | 748 | ((FLAG) == QSPI_FLAG_TC) || \ |
| NYX | 0:85b3fd62ea1a | 749 | ((FLAG) == QSPI_FLAG_TE)) |
| NYX | 0:85b3fd62ea1a | 750 | |
| NYX | 0:85b3fd62ea1a | 751 | #define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U)) |
| NYX | 0:85b3fd62ea1a | 752 | /** |
| NYX | 0:85b3fd62ea1a | 753 | * @} |
| NYX | 0:85b3fd62ea1a | 754 | */ |
| NYX | 0:85b3fd62ea1a | 755 | |
| NYX | 0:85b3fd62ea1a | 756 | /* Private functions ---------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 757 | /** @defgroup QSPI_Private_Functions QSPI Private Functions |
| NYX | 0:85b3fd62ea1a | 758 | * @{ |
| NYX | 0:85b3fd62ea1a | 759 | */ |
| NYX | 0:85b3fd62ea1a | 760 | |
| NYX | 0:85b3fd62ea1a | 761 | /** |
| NYX | 0:85b3fd62ea1a | 762 | * @} |
| NYX | 0:85b3fd62ea1a | 763 | */ |
| NYX | 0:85b3fd62ea1a | 764 | |
| NYX | 0:85b3fd62ea1a | 765 | /** |
| NYX | 0:85b3fd62ea1a | 766 | * @} |
| NYX | 0:85b3fd62ea1a | 767 | */ |
| NYX | 0:85b3fd62ea1a | 768 | |
| NYX | 0:85b3fd62ea1a | 769 | /** |
| NYX | 0:85b3fd62ea1a | 770 | * @} |
| NYX | 0:85b3fd62ea1a | 771 | */ |
| NYX | 0:85b3fd62ea1a | 772 | |
| NYX | 0:85b3fd62ea1a | 773 | /** |
| NYX | 0:85b3fd62ea1a | 774 | * @} |
| NYX | 0:85b3fd62ea1a | 775 | */ |
| NYX | 0:85b3fd62ea1a | 776 | #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || |
| NYX | 0:85b3fd62ea1a | 777 | STM32F413xx || STM32F423xx */ |
| NYX | 0:85b3fd62ea1a | 778 | |
| NYX | 0:85b3fd62ea1a | 779 | #ifdef __cplusplus |
| NYX | 0:85b3fd62ea1a | 780 | } |
| NYX | 0:85b3fd62ea1a | 781 | #endif |
| NYX | 0:85b3fd62ea1a | 782 | |
| NYX | 0:85b3fd62ea1a | 783 | #endif /* __STM32F4xx_HAL_QSPI_H */ |
| NYX | 0:85b3fd62ea1a | 784 | |
| NYX | 0:85b3fd62ea1a | 785 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |