mbed-dev - inport from local

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inport from local

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_hal_qspi.c
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief QSPI HAL module driver.
NYX	0:85b3fd62ea1a	8	* This file provides firmware functions to manage the following
NYX	0:85b3fd62ea1a	9	* functionalities of the QuadSPI interface (QSPI).
NYX	0:85b3fd62ea1a	10	* + Initialization and de-initialization functions
NYX	0:85b3fd62ea1a	11	* + Indirect functional mode management
NYX	0:85b3fd62ea1a	12	* + Memory-mapped functional mode management
NYX	0:85b3fd62ea1a	13	* + Auto-polling functional mode management
NYX	0:85b3fd62ea1a	14	* + Interrupts and flags management
NYX	0:85b3fd62ea1a	15	* + DMA channel configuration for indirect functional mode
NYX	0:85b3fd62ea1a	16	* + Errors management and abort functionality
NYX	0:85b3fd62ea1a	17	*
NYX	0:85b3fd62ea1a	18	*
NYX	0:85b3fd62ea1a	19	@verbatim
NYX	0:85b3fd62ea1a	20	===============================================================================
NYX	0:85b3fd62ea1a	21	##### How to use this driver #####
NYX	0:85b3fd62ea1a	22	===============================================================================
NYX	0:85b3fd62ea1a	23	[..]
NYX	0:85b3fd62ea1a	24	* Initialization *
NYX	0:85b3fd62ea1a	25	======================
NYX	0:85b3fd62ea1a	26	[..]
NYX	0:85b3fd62ea1a	27	(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
NYX	0:85b3fd62ea1a	28	(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
NYX	0:85b3fd62ea1a	29	(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
NYX	0:85b3fd62ea1a	30	(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
NYX	0:85b3fd62ea1a	31	(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
NYX	0:85b3fd62ea1a	32	(++) If interrupt mode is used, enable and configure QuadSPI global
NYX	0:85b3fd62ea1a	33	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
NYX	0:85b3fd62ea1a	34	(++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
NYX	0:85b3fd62ea1a	35	with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
NYX	0:85b3fd62ea1a	36	link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
NYX	0:85b3fd62ea1a	37	DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
NYX	0:85b3fd62ea1a	38	(#) Configure the flash size, the clock prescaler, the fifo threshold, the
NYX	0:85b3fd62ea1a	39	clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
NYX	0:85b3fd62ea1a	40
NYX	0:85b3fd62ea1a	41	* Indirect functional mode *
NYX	0:85b3fd62ea1a	42	================================
NYX	0:85b3fd62ea1a	43	[..]
NYX	0:85b3fd62ea1a	44	(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
NYX	0:85b3fd62ea1a	45	functions :
NYX	0:85b3fd62ea1a	46	(++) Instruction phase : the mode used and if present the instruction opcode.
NYX	0:85b3fd62ea1a	47	(++) Address phase : the mode used and if present the size and the address value.
NYX	0:85b3fd62ea1a	48	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
NYX	0:85b3fd62ea1a	49	bytes values.
NYX	0:85b3fd62ea1a	50	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
NYX	0:85b3fd62ea1a	51	(++) Data phase : the mode used and if present the number of bytes.
NYX	0:85b3fd62ea1a	52	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
NYX	0:85b3fd62ea1a	53	if activated.
NYX	0:85b3fd62ea1a	54	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
NYX	0:85b3fd62ea1a	55	(#) If no data is required for the command, it is sent directly to the memory :
NYX	0:85b3fd62ea1a	56	(++) In polling mode, the output of the function is done when the transfer is complete.
NYX	0:85b3fd62ea1a	57	(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
NYX	0:85b3fd62ea1a	58	(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
NYX	0:85b3fd62ea1a	59	HAL_QSPI_Transmit_IT() after the command configuration :
NYX	0:85b3fd62ea1a	60	(++) In polling mode, the output of the function is done when the transfer is complete.
NYX	0:85b3fd62ea1a	61	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
NYX	0:85b3fd62ea1a	62	is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
NYX	0:85b3fd62ea1a	63	(++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
NYX	0:85b3fd62ea1a	64	HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
NYX	0:85b3fd62ea1a	65	(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
NYX	0:85b3fd62ea1a	66	HAL_QSPI_Receive_IT() after the command configuration :
NYX	0:85b3fd62ea1a	67	(++) In polling mode, the output of the function is done when the transfer is complete.
NYX	0:85b3fd62ea1a	68	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
NYX	0:85b3fd62ea1a	69	is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
NYX	0:85b3fd62ea1a	70	(++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
NYX	0:85b3fd62ea1a	71	HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
NYX	0:85b3fd62ea1a	72
NYX	0:85b3fd62ea1a	73	* Auto-polling functional mode *
NYX	0:85b3fd62ea1a	74	====================================
NYX	0:85b3fd62ea1a	75	[..]
NYX	0:85b3fd62ea1a	76	(#) Configure the command sequence and the auto-polling functional mode using the
NYX	0:85b3fd62ea1a	77	HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
NYX	0:85b3fd62ea1a	78	(++) Instruction phase : the mode used and if present the instruction opcode.
NYX	0:85b3fd62ea1a	79	(++) Address phase : the mode used and if present the size and the address value.
NYX	0:85b3fd62ea1a	80	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
NYX	0:85b3fd62ea1a	81	bytes values.
NYX	0:85b3fd62ea1a	82	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
NYX	0:85b3fd62ea1a	83	(++) Data phase : the mode used.
NYX	0:85b3fd62ea1a	84	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
NYX	0:85b3fd62ea1a	85	if activated.
NYX	0:85b3fd62ea1a	86	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
NYX	0:85b3fd62ea1a	87	(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
NYX	0:85b3fd62ea1a	88	the polling interval and the automatic stop activation.
NYX	0:85b3fd62ea1a	89	(#) After the configuration :
NYX	0:85b3fd62ea1a	90	(++) In polling mode, the output of the function is done when the status match is reached. The
NYX	0:85b3fd62ea1a	91	automatic stop is activated to avoid an infinite loop.
NYX	0:85b3fd62ea1a	92	(++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
NYX	0:85b3fd62ea1a	93
NYX	0:85b3fd62ea1a	94	* Memory-mapped functional mode *
NYX	0:85b3fd62ea1a	95	=====================================
NYX	0:85b3fd62ea1a	96	[..]
NYX	0:85b3fd62ea1a	97	(#) Configure the command sequence and the memory-mapped functional mode using the
NYX	0:85b3fd62ea1a	98	HAL_QSPI_MemoryMapped() functions :
NYX	0:85b3fd62ea1a	99	(++) Instruction phase : the mode used and if present the instruction opcode.
NYX	0:85b3fd62ea1a	100	(++) Address phase : the mode used and the size.
NYX	0:85b3fd62ea1a	101	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
NYX	0:85b3fd62ea1a	102	bytes values.
NYX	0:85b3fd62ea1a	103	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
NYX	0:85b3fd62ea1a	104	(++) Data phase : the mode used.
NYX	0:85b3fd62ea1a	105	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
NYX	0:85b3fd62ea1a	106	if activated.
NYX	0:85b3fd62ea1a	107	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
NYX	0:85b3fd62ea1a	108	(++) The timeout activation and the timeout period.
NYX	0:85b3fd62ea1a	109	(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
NYX	0:85b3fd62ea1a	110	the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
NYX	0:85b3fd62ea1a	111
NYX	0:85b3fd62ea1a	112	* Errors management and abort functionality *
NYX	0:85b3fd62ea1a	113	==================================================
NYX	0:85b3fd62ea1a	114	[..]
NYX	0:85b3fd62ea1a	115	(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
NYX	0:85b3fd62ea1a	116	(#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
NYX	0:85b3fd62ea1a	117	flushes the fifo :
NYX	0:85b3fd62ea1a	118	(++) In polling mode, the output of the function is done when the transfer
NYX	0:85b3fd62ea1a	119	complete bit is set and the busy bit cleared.
NYX	0:85b3fd62ea1a	120	(++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
NYX	0:85b3fd62ea1a	121	the transfer complete bi is set.
NYX	0:85b3fd62ea1a	122
NYX	0:85b3fd62ea1a	123	* Control functions *
NYX	0:85b3fd62ea1a	124	=========================
NYX	0:85b3fd62ea1a	125	[..]
NYX	0:85b3fd62ea1a	126	(#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
NYX	0:85b3fd62ea1a	127	(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
NYX	0:85b3fd62ea1a	128	(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
NYX	0:85b3fd62ea1a	129	(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
NYX	0:85b3fd62ea1a	130
NYX	0:85b3fd62ea1a	131	* Workarounds linked to Silicon Limitation *
NYX	0:85b3fd62ea1a	132	====================================================
NYX	0:85b3fd62ea1a	133	[..]
NYX	0:85b3fd62ea1a	134	(#) Workarounds Implemented inside HAL Driver
NYX	0:85b3fd62ea1a	135	(++) Extra data written in the FIFO at the end of a read transfer
NYX	0:85b3fd62ea1a	136
NYX	0:85b3fd62ea1a	137	@endverbatim
NYX	0:85b3fd62ea1a	138	******************************************************************************
NYX	0:85b3fd62ea1a	139	* @attention
NYX	0:85b3fd62ea1a	140	*
NYX	0:85b3fd62ea1a	141	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	142	*
NYX	0:85b3fd62ea1a	143	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	144	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	145	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	146	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	147	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	148	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	149	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	150	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	151	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	152	* without specific prior written permission.
NYX	0:85b3fd62ea1a	153	*
NYX	0:85b3fd62ea1a	154	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	155	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	156	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	157	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	158	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	159	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	160	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	161	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	162	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	163	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	164	*
NYX	0:85b3fd62ea1a	165	******************************************************************************
NYX	0:85b3fd62ea1a	166	*/
NYX	0:85b3fd62ea1a	167
NYX	0:85b3fd62ea1a	168	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	169	#include "stm32f4xx_hal.h"
NYX	0:85b3fd62ea1a	170
NYX	0:85b3fd62ea1a	171	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	172	* @{
NYX	0:85b3fd62ea1a	173	*/
NYX	0:85b3fd62ea1a	174
NYX	0:85b3fd62ea1a	175	/** @defgroup QSPI QSPI
NYX	0:85b3fd62ea1a	176	* @brief QSPI HAL module driver
NYX	0:85b3fd62ea1a	177	* @{
NYX	0:85b3fd62ea1a	178	*/
NYX	0:85b3fd62ea1a	179	#ifdef HAL_QSPI_MODULE_ENABLED
NYX	0:85b3fd62ea1a	180
NYX	0:85b3fd62ea1a	181	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
NYX	0:85b3fd62ea1a	182	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	183
NYX	0:85b3fd62ea1a	184	/* Private typedef -----------------------------------------------------------*/
NYX	0:85b3fd62ea1a	185	/* Private define ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	186	/** @addtogroup QSPI_Private_Constants
NYX	0:85b3fd62ea1a	187	* @{
NYX	0:85b3fd62ea1a	188	*/
NYX	0:85b3fd62ea1a	189	#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /!<Indirect write mode/
NYX	0:85b3fd62ea1a	190	#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /!<Indirect read mode/
NYX	0:85b3fd62ea1a	191	#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /!<Automatic polling mode/
NYX	0:85b3fd62ea1a	192	#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /!<Memory-mapped mode/
NYX	0:85b3fd62ea1a	193	/**
NYX	0:85b3fd62ea1a	194	* @}
NYX	0:85b3fd62ea1a	195	*/
NYX	0:85b3fd62ea1a	196
NYX	0:85b3fd62ea1a	197	/* Private macro -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	198	/** @addtogroup QSPI_Private_Macros QSPI Private Macros
NYX	0:85b3fd62ea1a	199	* @{
NYX	0:85b3fd62ea1a	200	*/
NYX	0:85b3fd62ea1a	201	#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \|\| \
NYX	0:85b3fd62ea1a	202	((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) \|\| \
NYX	0:85b3fd62ea1a	203	((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) \|\| \
NYX	0:85b3fd62ea1a	204	((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
NYX	0:85b3fd62ea1a	205	/**
NYX	0:85b3fd62ea1a	206	* @}
NYX	0:85b3fd62ea1a	207	*/
NYX	0:85b3fd62ea1a	208
NYX	0:85b3fd62ea1a	209	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	210	/* Private function prototypes -----------------------------------------------*/
NYX	0:85b3fd62ea1a	211	/** @addtogroup QSPI_Private_Functions QSPI Private Functions
NYX	0:85b3fd62ea1a	212	* @{
NYX	0:85b3fd62ea1a	213	*/
NYX	0:85b3fd62ea1a	214	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	215	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	216	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	217	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	218	static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	219	static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	220	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
NYX	0:85b3fd62ea1a	221	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode);
NYX	0:85b3fd62ea1a	222	/**
NYX	0:85b3fd62ea1a	223	* @}
NYX	0:85b3fd62ea1a	224	*/
NYX	0:85b3fd62ea1a	225
NYX	0:85b3fd62ea1a	226	/* Exported functions ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	227
NYX	0:85b3fd62ea1a	228	/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
NYX	0:85b3fd62ea1a	229	* @{
NYX	0:85b3fd62ea1a	230	*/
NYX	0:85b3fd62ea1a	231
NYX	0:85b3fd62ea1a	232	/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
NYX	0:85b3fd62ea1a	233	* @brief Initialization and Configuration functions
NYX	0:85b3fd62ea1a	234	*
NYX	0:85b3fd62ea1a	235	@verbatim
NYX	0:85b3fd62ea1a	236	===============================================================================
NYX	0:85b3fd62ea1a	237	##### Initialization and Configuration functions #####
NYX	0:85b3fd62ea1a	238	===============================================================================
NYX	0:85b3fd62ea1a	239	[..]
NYX	0:85b3fd62ea1a	240	This subsection provides a set of functions allowing to :
NYX	0:85b3fd62ea1a	241	(+) Initialize the QuadSPI.
NYX	0:85b3fd62ea1a	242	(+) De-initialize the QuadSPI.
NYX	0:85b3fd62ea1a	243
NYX	0:85b3fd62ea1a	244	@endverbatim
NYX	0:85b3fd62ea1a	245	* @{
NYX	0:85b3fd62ea1a	246	*/
NYX	0:85b3fd62ea1a	247
NYX	0:85b3fd62ea1a	248	/**
NYX	0:85b3fd62ea1a	249	* @brief Initializes the QSPI mode according to the specified parameters
NYX	0:85b3fd62ea1a	250	* in the QSPI_InitTypeDef and creates the associated handle.
NYX	0:85b3fd62ea1a	251	* @param hqspi: qspi handle
NYX	0:85b3fd62ea1a	252	* @retval HAL status
NYX	0:85b3fd62ea1a	253	*/
NYX	0:85b3fd62ea1a	254	HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	255	{
NYX	0:85b3fd62ea1a	256	HAL_StatusTypeDef status = HAL_ERROR;
NYX	0:85b3fd62ea1a	257	uint32_t tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	258
NYX	0:85b3fd62ea1a	259	/* Check the QSPI handle allocation */
NYX	0:85b3fd62ea1a	260	if(hqspi == NULL)
NYX	0:85b3fd62ea1a	261	{
NYX	0:85b3fd62ea1a	262	return HAL_ERROR;
NYX	0:85b3fd62ea1a	263	}
NYX	0:85b3fd62ea1a	264
NYX	0:85b3fd62ea1a	265	/* Check the parameters */
NYX	0:85b3fd62ea1a	266	assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
NYX	0:85b3fd62ea1a	267	assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
NYX	0:85b3fd62ea1a	268	assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
NYX	0:85b3fd62ea1a	269	assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
NYX	0:85b3fd62ea1a	270	assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
NYX	0:85b3fd62ea1a	271	assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
NYX	0:85b3fd62ea1a	272	assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
NYX	0:85b3fd62ea1a	273	assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
NYX	0:85b3fd62ea1a	274
NYX	0:85b3fd62ea1a	275	if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
NYX	0:85b3fd62ea1a	276	{
NYX	0:85b3fd62ea1a	277	assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
NYX	0:85b3fd62ea1a	278	}
NYX	0:85b3fd62ea1a	279
NYX	0:85b3fd62ea1a	280	/* Process locked */
NYX	0:85b3fd62ea1a	281	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	282
NYX	0:85b3fd62ea1a	283	if(hqspi->State == HAL_QSPI_STATE_RESET)
NYX	0:85b3fd62ea1a	284	{
NYX	0:85b3fd62ea1a	285	/* Allocate lock resource and initialize it */
NYX	0:85b3fd62ea1a	286	hqspi->Lock = HAL_UNLOCKED;
NYX	0:85b3fd62ea1a	287
NYX	0:85b3fd62ea1a	288	/* Init the low level hardware : GPIO, CLOCK */
NYX	0:85b3fd62ea1a	289	HAL_QSPI_MspInit(hqspi);
NYX	0:85b3fd62ea1a	290
NYX	0:85b3fd62ea1a	291	/* Configure the default timeout for the QSPI memory access */
NYX	0:85b3fd62ea1a	292	HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
NYX	0:85b3fd62ea1a	293	}
NYX	0:85b3fd62ea1a	294
NYX	0:85b3fd62ea1a	295	/* Configure QSPI FIFO Threshold */
NYX	0:85b3fd62ea1a	296	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1U) << 8U));
NYX	0:85b3fd62ea1a	297
NYX	0:85b3fd62ea1a	298	/* Wait till BUSY flag reset */
NYX	0:85b3fd62ea1a	299	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
NYX	0:85b3fd62ea1a	300
NYX	0:85b3fd62ea1a	301	if(status == HAL_OK)
NYX	0:85b3fd62ea1a	302	{
NYX	0:85b3fd62ea1a	303
NYX	0:85b3fd62ea1a	304	/* Configure QSPI Clock Prescaler and Sample Shift */
NYX	0:85b3fd62ea1a	305	MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT \| QUADSPI_CR_FSEL \| QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24U)\| hqspi->Init.SampleShifting \| hqspi->Init.FlashID\| hqspi->Init.DualFlash ));
NYX	0:85b3fd62ea1a	306
NYX	0:85b3fd62ea1a	307	/* Configure QSPI Flash Size, CS High Time and Clock Mode */
NYX	0:85b3fd62ea1a	308	MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE \| QUADSPI_DCR_CSHT \| QUADSPI_DCR_CKMODE),
NYX	0:85b3fd62ea1a	309	((hqspi->Init.FlashSize << 16U) \| hqspi->Init.ChipSelectHighTime \| hqspi->Init.ClockMode));
NYX	0:85b3fd62ea1a	310
NYX	0:85b3fd62ea1a	311	/* Enable the QSPI peripheral */
NYX	0:85b3fd62ea1a	312	__HAL_QSPI_ENABLE(hqspi);
NYX	0:85b3fd62ea1a	313
NYX	0:85b3fd62ea1a	314	/* Set QSPI error code to none */
NYX	0:85b3fd62ea1a	315	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	316
NYX	0:85b3fd62ea1a	317	/* Initialize the QSPI state */
NYX	0:85b3fd62ea1a	318	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	319	}
NYX	0:85b3fd62ea1a	320
NYX	0:85b3fd62ea1a	321	/* Release Lock */
NYX	0:85b3fd62ea1a	322	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	323
NYX	0:85b3fd62ea1a	324	/* Return function status */
NYX	0:85b3fd62ea1a	325	return status;
NYX	0:85b3fd62ea1a	326	}
NYX	0:85b3fd62ea1a	327
NYX	0:85b3fd62ea1a	328	/**
NYX	0:85b3fd62ea1a	329	* @brief DeInitializes the QSPI peripheral
NYX	0:85b3fd62ea1a	330	* @param hqspi: qspi handle
NYX	0:85b3fd62ea1a	331	* @retval HAL status
NYX	0:85b3fd62ea1a	332	*/
NYX	0:85b3fd62ea1a	333	HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	334	{
NYX	0:85b3fd62ea1a	335	/* Check the QSPI handle allocation */
NYX	0:85b3fd62ea1a	336	if(hqspi == NULL)
NYX	0:85b3fd62ea1a	337	{
NYX	0:85b3fd62ea1a	338	return HAL_ERROR;
NYX	0:85b3fd62ea1a	339	}
NYX	0:85b3fd62ea1a	340
NYX	0:85b3fd62ea1a	341	/* Process locked */
NYX	0:85b3fd62ea1a	342	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	343
NYX	0:85b3fd62ea1a	344	/* Disable the QSPI Peripheral Clock */
NYX	0:85b3fd62ea1a	345	__HAL_QSPI_DISABLE(hqspi);
NYX	0:85b3fd62ea1a	346
NYX	0:85b3fd62ea1a	347	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
NYX	0:85b3fd62ea1a	348	HAL_QSPI_MspDeInit(hqspi);
NYX	0:85b3fd62ea1a	349
NYX	0:85b3fd62ea1a	350	/* Set QSPI error code to none */
NYX	0:85b3fd62ea1a	351	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	352
NYX	0:85b3fd62ea1a	353	/* Initialize the QSPI state */
NYX	0:85b3fd62ea1a	354	hqspi->State = HAL_QSPI_STATE_RESET;
NYX	0:85b3fd62ea1a	355
NYX	0:85b3fd62ea1a	356	/* Release Lock */
NYX	0:85b3fd62ea1a	357	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	358
NYX	0:85b3fd62ea1a	359	return HAL_OK;
NYX	0:85b3fd62ea1a	360	}
NYX	0:85b3fd62ea1a	361
NYX	0:85b3fd62ea1a	362	/**
NYX	0:85b3fd62ea1a	363	* @brief QSPI MSP Init
NYX	0:85b3fd62ea1a	364	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	365	* @retval None
NYX	0:85b3fd62ea1a	366	*/
NYX	0:85b3fd62ea1a	367	__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	368	{
NYX	0:85b3fd62ea1a	369	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	370	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	371
NYX	0:85b3fd62ea1a	372	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	373	the HAL_QSPI_MspInit can be implemented in the user file
NYX	0:85b3fd62ea1a	374	*/
NYX	0:85b3fd62ea1a	375	}
NYX	0:85b3fd62ea1a	376
NYX	0:85b3fd62ea1a	377	/**
NYX	0:85b3fd62ea1a	378	* @brief QSPI MSP DeInit
NYX	0:85b3fd62ea1a	379	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	380	* @retval None
NYX	0:85b3fd62ea1a	381	*/
NYX	0:85b3fd62ea1a	382	__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	383	{
NYX	0:85b3fd62ea1a	384	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	385	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	386
NYX	0:85b3fd62ea1a	387	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	388	the HAL_QSPI_MspDeInit can be implemented in the user file
NYX	0:85b3fd62ea1a	389	*/
NYX	0:85b3fd62ea1a	390	}
NYX	0:85b3fd62ea1a	391
NYX	0:85b3fd62ea1a	392	/**
NYX	0:85b3fd62ea1a	393	* @}
NYX	0:85b3fd62ea1a	394	*/
NYX	0:85b3fd62ea1a	395
NYX	0:85b3fd62ea1a	396	/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
NYX	0:85b3fd62ea1a	397	* @brief QSPI Transmit/Receive functions
NYX	0:85b3fd62ea1a	398	*
NYX	0:85b3fd62ea1a	399	@verbatim
NYX	0:85b3fd62ea1a	400	===============================================================================
NYX	0:85b3fd62ea1a	401	##### IO operation functions #####
NYX	0:85b3fd62ea1a	402	===============================================================================
NYX	0:85b3fd62ea1a	403	[..]
NYX	0:85b3fd62ea1a	404	This subsection provides a set of functions allowing to :
NYX	0:85b3fd62ea1a	405	(+) Handle the interrupts.
NYX	0:85b3fd62ea1a	406	(+) Handle the command sequence.
NYX	0:85b3fd62ea1a	407	(+) Transmit data in blocking, interrupt or DMA mode.
NYX	0:85b3fd62ea1a	408	(+) Receive data in blocking, interrupt or DMA mode.
NYX	0:85b3fd62ea1a	409	(+) Manage the auto-polling functional mode.
NYX	0:85b3fd62ea1a	410	(+) Manage the memory-mapped functional mode.
NYX	0:85b3fd62ea1a	411
NYX	0:85b3fd62ea1a	412	@endverbatim
NYX	0:85b3fd62ea1a	413	* @{
NYX	0:85b3fd62ea1a	414	*/
NYX	0:85b3fd62ea1a	415
NYX	0:85b3fd62ea1a	416	/**
NYX	0:85b3fd62ea1a	417	* @brief This function handles QSPI interrupt request.
NYX	0:85b3fd62ea1a	418	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	419	* @retval None.
NYX	0:85b3fd62ea1a	420	*/
NYX	0:85b3fd62ea1a	421	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	422	{
NYX	0:85b3fd62ea1a	423	__IO uint32_t *data_reg;
NYX	0:85b3fd62ea1a	424	uint32_t flag = READ_REG(hqspi->Instance->SR);
NYX	0:85b3fd62ea1a	425	uint32_t itsource = READ_REG(hqspi->Instance->CR);
NYX	0:85b3fd62ea1a	426
NYX	0:85b3fd62ea1a	427	/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
NYX	0:85b3fd62ea1a	428	if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
NYX	0:85b3fd62ea1a	429	{
NYX	0:85b3fd62ea1a	430	data_reg = &hqspi->Instance->DR;
NYX	0:85b3fd62ea1a	431
NYX	0:85b3fd62ea1a	432	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
NYX	0:85b3fd62ea1a	433	{
NYX	0:85b3fd62ea1a	434	/* Transmission process */
NYX	0:85b3fd62ea1a	435	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
NYX	0:85b3fd62ea1a	436	{
NYX	0:85b3fd62ea1a	437	if (hqspi->TxXferCount > 0U)
NYX	0:85b3fd62ea1a	438	{
NYX	0:85b3fd62ea1a	439	/* Fill the FIFO until it is full */
NYX	0:85b3fd62ea1a	440	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
NYX	0:85b3fd62ea1a	441	hqspi->TxXferCount--;
NYX	0:85b3fd62ea1a	442	}
NYX	0:85b3fd62ea1a	443	else
NYX	0:85b3fd62ea1a	444	{
NYX	0:85b3fd62ea1a	445	/* No more data available for the transfer */
NYX	0:85b3fd62ea1a	446	/* Disable the QSPI FIFO Threshold Interrupt */
NYX	0:85b3fd62ea1a	447	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
NYX	0:85b3fd62ea1a	448	break;
NYX	0:85b3fd62ea1a	449	}
NYX	0:85b3fd62ea1a	450	}
NYX	0:85b3fd62ea1a	451	}
NYX	0:85b3fd62ea1a	452	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
NYX	0:85b3fd62ea1a	453	{
NYX	0:85b3fd62ea1a	454	/* Receiving Process */
NYX	0:85b3fd62ea1a	455	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
NYX	0:85b3fd62ea1a	456	{
NYX	0:85b3fd62ea1a	457	if (hqspi->RxXferCount > 0U)
NYX	0:85b3fd62ea1a	458	{
NYX	0:85b3fd62ea1a	459	/* Read the FIFO until it is empty */
NYX	0:85b3fd62ea1a	460	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
NYX	0:85b3fd62ea1a	461	hqspi->RxXferCount--;
NYX	0:85b3fd62ea1a	462	}
NYX	0:85b3fd62ea1a	463	else
NYX	0:85b3fd62ea1a	464	{
NYX	0:85b3fd62ea1a	465	/* All data have been received for the transfer */
NYX	0:85b3fd62ea1a	466	/* Disable the QSPI FIFO Threshold Interrupt */
NYX	0:85b3fd62ea1a	467	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
NYX	0:85b3fd62ea1a	468	break;
NYX	0:85b3fd62ea1a	469	}
NYX	0:85b3fd62ea1a	470	}
NYX	0:85b3fd62ea1a	471	}
NYX	0:85b3fd62ea1a	472
NYX	0:85b3fd62ea1a	473	/* FIFO Threshold callback */
NYX	0:85b3fd62ea1a	474	HAL_QSPI_FifoThresholdCallback(hqspi);
NYX	0:85b3fd62ea1a	475	}
NYX	0:85b3fd62ea1a	476
NYX	0:85b3fd62ea1a	477	/* QSPI Transfer Complete interrupt occurred -------------------------------*/
NYX	0:85b3fd62ea1a	478	else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
NYX	0:85b3fd62ea1a	479	{
NYX	0:85b3fd62ea1a	480	/* Clear interrupt */
NYX	0:85b3fd62ea1a	481	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	482
NYX	0:85b3fd62ea1a	483	/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
NYX	0:85b3fd62ea1a	484	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
NYX	0:85b3fd62ea1a	485
NYX	0:85b3fd62ea1a	486	/* Transfer complete callback */
NYX	0:85b3fd62ea1a	487	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
NYX	0:85b3fd62ea1a	488	{
NYX	0:85b3fd62ea1a	489	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
NYX	0:85b3fd62ea1a	490	{
NYX	0:85b3fd62ea1a	491	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
NYX	0:85b3fd62ea1a	492	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
NYX	0:85b3fd62ea1a	493
NYX	0:85b3fd62ea1a	494	/* Disable the DMA channel */
NYX	0:85b3fd62ea1a	495	__HAL_DMA_DISABLE(hqspi->hdma);
NYX	0:85b3fd62ea1a	496	}
NYX	0:85b3fd62ea1a	497
NYX	0:85b3fd62ea1a	498	/* Clear Busy bit */
NYX	0:85b3fd62ea1a	499	HAL_QSPI_Abort_IT(hqspi);
NYX	0:85b3fd62ea1a	500
NYX	0:85b3fd62ea1a	501	/* Change state of QSPI */
NYX	0:85b3fd62ea1a	502	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	503
NYX	0:85b3fd62ea1a	504	/* TX Complete callback */
NYX	0:85b3fd62ea1a	505	HAL_QSPI_TxCpltCallback(hqspi);
NYX	0:85b3fd62ea1a	506	}
NYX	0:85b3fd62ea1a	507	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
NYX	0:85b3fd62ea1a	508	{
NYX	0:85b3fd62ea1a	509	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
NYX	0:85b3fd62ea1a	510	{
NYX	0:85b3fd62ea1a	511	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
NYX	0:85b3fd62ea1a	512	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
NYX	0:85b3fd62ea1a	513
NYX	0:85b3fd62ea1a	514	/* Disable the DMA channel */
NYX	0:85b3fd62ea1a	515	__HAL_DMA_DISABLE(hqspi->hdma);
NYX	0:85b3fd62ea1a	516	}
NYX	0:85b3fd62ea1a	517	else
NYX	0:85b3fd62ea1a	518	{
NYX	0:85b3fd62ea1a	519	data_reg = &hqspi->Instance->DR;
NYX	0:85b3fd62ea1a	520	while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
NYX	0:85b3fd62ea1a	521	{
NYX	0:85b3fd62ea1a	522	if (hqspi->RxXferCount > 0U)
NYX	0:85b3fd62ea1a	523	{
NYX	0:85b3fd62ea1a	524	/* Read the last data received in the FIFO until it is empty */
NYX	0:85b3fd62ea1a	525	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
NYX	0:85b3fd62ea1a	526	hqspi->RxXferCount--;
NYX	0:85b3fd62ea1a	527	}
NYX	0:85b3fd62ea1a	528	else
NYX	0:85b3fd62ea1a	529	{
NYX	0:85b3fd62ea1a	530	/* All data have been received for the transfer */
NYX	0:85b3fd62ea1a	531	break;
NYX	0:85b3fd62ea1a	532	}
NYX	0:85b3fd62ea1a	533	}
NYX	0:85b3fd62ea1a	534	}
NYX	0:85b3fd62ea1a	535	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
NYX	0:85b3fd62ea1a	536	HAL_QSPI_Abort_IT(hqspi);
NYX	0:85b3fd62ea1a	537
NYX	0:85b3fd62ea1a	538	/* Change state of QSPI */
NYX	0:85b3fd62ea1a	539	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	540
NYX	0:85b3fd62ea1a	541	/* RX Complete callback */
NYX	0:85b3fd62ea1a	542	HAL_QSPI_RxCpltCallback(hqspi);
NYX	0:85b3fd62ea1a	543	}
NYX	0:85b3fd62ea1a	544	else if(hqspi->State == HAL_QSPI_STATE_BUSY)
NYX	0:85b3fd62ea1a	545	{
NYX	0:85b3fd62ea1a	546	/* Change state of QSPI */
NYX	0:85b3fd62ea1a	547	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	548
NYX	0:85b3fd62ea1a	549	/* Command Complete callback */
NYX	0:85b3fd62ea1a	550	HAL_QSPI_CmdCpltCallback(hqspi);
NYX	0:85b3fd62ea1a	551	}
NYX	0:85b3fd62ea1a	552	else if(hqspi->State == HAL_QSPI_STATE_ABORT)
NYX	0:85b3fd62ea1a	553	{
NYX	0:85b3fd62ea1a	554	/* Change state of QSPI */
NYX	0:85b3fd62ea1a	555	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	556
NYX	0:85b3fd62ea1a	557	if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	558	{
NYX	0:85b3fd62ea1a	559	/* Abort called by the user */
NYX	0:85b3fd62ea1a	560
NYX	0:85b3fd62ea1a	561	/* Abort Complete callback */
NYX	0:85b3fd62ea1a	562	HAL_QSPI_AbortCpltCallback(hqspi);
NYX	0:85b3fd62ea1a	563	}
NYX	0:85b3fd62ea1a	564	else
NYX	0:85b3fd62ea1a	565	{
NYX	0:85b3fd62ea1a	566	/* Abort due to an error (eg : DMA error) */
NYX	0:85b3fd62ea1a	567
NYX	0:85b3fd62ea1a	568	/* Error callback */
NYX	0:85b3fd62ea1a	569	HAL_QSPI_ErrorCallback(hqspi);
NYX	0:85b3fd62ea1a	570	}
NYX	0:85b3fd62ea1a	571	}
NYX	0:85b3fd62ea1a	572	}
NYX	0:85b3fd62ea1a	573
NYX	0:85b3fd62ea1a	574	/* QSPI Status Match interrupt occurred ------------------------------------*/
NYX	0:85b3fd62ea1a	575	else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
NYX	0:85b3fd62ea1a	576	{
NYX	0:85b3fd62ea1a	577	/* Clear interrupt */
NYX	0:85b3fd62ea1a	578	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
NYX	0:85b3fd62ea1a	579
NYX	0:85b3fd62ea1a	580	/* Check if the automatic poll mode stop is activated */
NYX	0:85b3fd62ea1a	581	if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
NYX	0:85b3fd62ea1a	582	{
NYX	0:85b3fd62ea1a	583	/* Disable the QSPI Transfer Error and Status Match Interrupts */
NYX	0:85b3fd62ea1a	584	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
NYX	0:85b3fd62ea1a	585
NYX	0:85b3fd62ea1a	586	/* Change state of QSPI */
NYX	0:85b3fd62ea1a	587	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	588	}
NYX	0:85b3fd62ea1a	589
NYX	0:85b3fd62ea1a	590	/* Status match callback */
NYX	0:85b3fd62ea1a	591	HAL_QSPI_StatusMatchCallback(hqspi);
NYX	0:85b3fd62ea1a	592	}
NYX	0:85b3fd62ea1a	593
NYX	0:85b3fd62ea1a	594	/* QSPI Transfer Error interrupt occurred ----------------------------------*/
NYX	0:85b3fd62ea1a	595	else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
NYX	0:85b3fd62ea1a	596	{
NYX	0:85b3fd62ea1a	597	/* Clear interrupt */
NYX	0:85b3fd62ea1a	598	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
NYX	0:85b3fd62ea1a	599
NYX	0:85b3fd62ea1a	600	/* Disable all the QSPI Interrupts */
NYX	0:85b3fd62ea1a	601	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
NYX	0:85b3fd62ea1a	602
NYX	0:85b3fd62ea1a	603	/* Set error code */
NYX	0:85b3fd62ea1a	604	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TRANSFER;
NYX	0:85b3fd62ea1a	605
NYX	0:85b3fd62ea1a	606	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
NYX	0:85b3fd62ea1a	607	{
NYX	0:85b3fd62ea1a	608	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
NYX	0:85b3fd62ea1a	609	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
NYX	0:85b3fd62ea1a	610
NYX	0:85b3fd62ea1a	611	/* Disable the DMA channel */
NYX	0:85b3fd62ea1a	612	hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
NYX	0:85b3fd62ea1a	613	HAL_DMA_Abort_IT(hqspi->hdma);
NYX	0:85b3fd62ea1a	614	}
NYX	0:85b3fd62ea1a	615	else
NYX	0:85b3fd62ea1a	616	{
NYX	0:85b3fd62ea1a	617	/* Change state of QSPI */
NYX	0:85b3fd62ea1a	618	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	619
NYX	0:85b3fd62ea1a	620	/* Error callback */
NYX	0:85b3fd62ea1a	621	HAL_QSPI_ErrorCallback(hqspi);
NYX	0:85b3fd62ea1a	622	}
NYX	0:85b3fd62ea1a	623	}
NYX	0:85b3fd62ea1a	624
NYX	0:85b3fd62ea1a	625	/* QSPI Timeout interrupt occurred -----------------------------------------*/
NYX	0:85b3fd62ea1a	626	else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
NYX	0:85b3fd62ea1a	627	{
NYX	0:85b3fd62ea1a	628	/* Clear interrupt */
NYX	0:85b3fd62ea1a	629	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
NYX	0:85b3fd62ea1a	630
NYX	0:85b3fd62ea1a	631	/* Time out callback */
NYX	0:85b3fd62ea1a	632	HAL_QSPI_TimeOutCallback(hqspi);
NYX	0:85b3fd62ea1a	633	}
NYX	0:85b3fd62ea1a	634	}
NYX	0:85b3fd62ea1a	635
NYX	0:85b3fd62ea1a	636	/**
NYX	0:85b3fd62ea1a	637	* @brief Sets the command configuration.
NYX	0:85b3fd62ea1a	638	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	639	* @param cmd : structure that contains the command configuration information
NYX	0:85b3fd62ea1a	640	* @param Timeout : Time out duration
NYX	0:85b3fd62ea1a	641	* @note This function is used only in Indirect Read or Write Modes
NYX	0:85b3fd62ea1a	642	* @retval HAL status
NYX	0:85b3fd62ea1a	643	*/
NYX	0:85b3fd62ea1a	644	HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout)
NYX	0:85b3fd62ea1a	645	{
NYX	0:85b3fd62ea1a	646	HAL_StatusTypeDef status = HAL_ERROR;
NYX	0:85b3fd62ea1a	647	uint32_t tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	648
NYX	0:85b3fd62ea1a	649	/* Check the parameters */
NYX	0:85b3fd62ea1a	650	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
NYX	0:85b3fd62ea1a	651	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
NYX	0:85b3fd62ea1a	652	{
NYX	0:85b3fd62ea1a	653	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
NYX	0:85b3fd62ea1a	654	}
NYX	0:85b3fd62ea1a	655
NYX	0:85b3fd62ea1a	656	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
NYX	0:85b3fd62ea1a	657	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
NYX	0:85b3fd62ea1a	658	{
NYX	0:85b3fd62ea1a	659	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
NYX	0:85b3fd62ea1a	660	}
NYX	0:85b3fd62ea1a	661
NYX	0:85b3fd62ea1a	662	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
NYX	0:85b3fd62ea1a	663	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
NYX	0:85b3fd62ea1a	664	{
NYX	0:85b3fd62ea1a	665	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
NYX	0:85b3fd62ea1a	666	}
NYX	0:85b3fd62ea1a	667
NYX	0:85b3fd62ea1a	668	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
NYX	0:85b3fd62ea1a	669	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
NYX	0:85b3fd62ea1a	670
NYX	0:85b3fd62ea1a	671	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
NYX	0:85b3fd62ea1a	672	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
NYX	0:85b3fd62ea1a	673	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
NYX	0:85b3fd62ea1a	674
NYX	0:85b3fd62ea1a	675	/* Process locked */
NYX	0:85b3fd62ea1a	676	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	677
NYX	0:85b3fd62ea1a	678	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	679	{
NYX	0:85b3fd62ea1a	680	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	681
NYX	0:85b3fd62ea1a	682	/* Update QSPI state */
NYX	0:85b3fd62ea1a	683	hqspi->State = HAL_QSPI_STATE_BUSY;
NYX	0:85b3fd62ea1a	684
NYX	0:85b3fd62ea1a	685	/* Wait till BUSY flag reset */
NYX	0:85b3fd62ea1a	686	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
NYX	0:85b3fd62ea1a	687
NYX	0:85b3fd62ea1a	688	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	689	{
NYX	0:85b3fd62ea1a	690	/* Call the configuration function */
NYX	0:85b3fd62ea1a	691	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
NYX	0:85b3fd62ea1a	692
NYX	0:85b3fd62ea1a	693	if (cmd->DataMode == QSPI_DATA_NONE)
NYX	0:85b3fd62ea1a	694	{
NYX	0:85b3fd62ea1a	695	/* When there is no data phase, the transfer start as soon as the configuration is done
NYX	0:85b3fd62ea1a	696	so wait until TC flag is set to go back in idle state */
NYX	0:85b3fd62ea1a	697	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
NYX	0:85b3fd62ea1a	698
NYX	0:85b3fd62ea1a	699	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	700	{
NYX	0:85b3fd62ea1a	701	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	702
NYX	0:85b3fd62ea1a	703	/* Update QSPI state */
NYX	0:85b3fd62ea1a	704	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	705	}
NYX	0:85b3fd62ea1a	706
NYX	0:85b3fd62ea1a	707	}
NYX	0:85b3fd62ea1a	708	else
NYX	0:85b3fd62ea1a	709	{
NYX	0:85b3fd62ea1a	710	/* Update QSPI state */
NYX	0:85b3fd62ea1a	711	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	712	}
NYX	0:85b3fd62ea1a	713	}
NYX	0:85b3fd62ea1a	714	}
NYX	0:85b3fd62ea1a	715	else
NYX	0:85b3fd62ea1a	716	{
NYX	0:85b3fd62ea1a	717	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	718	}
NYX	0:85b3fd62ea1a	719
NYX	0:85b3fd62ea1a	720	/* Process unlocked */
NYX	0:85b3fd62ea1a	721	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	722
NYX	0:85b3fd62ea1a	723	/* Return function status */
NYX	0:85b3fd62ea1a	724	return status;
NYX	0:85b3fd62ea1a	725	}
NYX	0:85b3fd62ea1a	726
NYX	0:85b3fd62ea1a	727	/**
NYX	0:85b3fd62ea1a	728	* @brief Sets the command configuration in interrupt mode.
NYX	0:85b3fd62ea1a	729	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	730	* @param cmd : structure that contains the command configuration information
NYX	0:85b3fd62ea1a	731	* @note This function is used only in Indirect Read or Write Modes
NYX	0:85b3fd62ea1a	732	* @retval HAL status
NYX	0:85b3fd62ea1a	733	*/
NYX	0:85b3fd62ea1a	734	HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd)
NYX	0:85b3fd62ea1a	735	{
NYX	0:85b3fd62ea1a	736	__IO uint32_t count = 0U;
NYX	0:85b3fd62ea1a	737	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	738
NYX	0:85b3fd62ea1a	739	/* Check the parameters */
NYX	0:85b3fd62ea1a	740	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
NYX	0:85b3fd62ea1a	741	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
NYX	0:85b3fd62ea1a	742	{
NYX	0:85b3fd62ea1a	743	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
NYX	0:85b3fd62ea1a	744	}
NYX	0:85b3fd62ea1a	745
NYX	0:85b3fd62ea1a	746	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
NYX	0:85b3fd62ea1a	747	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
NYX	0:85b3fd62ea1a	748	{
NYX	0:85b3fd62ea1a	749	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
NYX	0:85b3fd62ea1a	750	}
NYX	0:85b3fd62ea1a	751
NYX	0:85b3fd62ea1a	752	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
NYX	0:85b3fd62ea1a	753	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
NYX	0:85b3fd62ea1a	754	{
NYX	0:85b3fd62ea1a	755	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
NYX	0:85b3fd62ea1a	756	}
NYX	0:85b3fd62ea1a	757
NYX	0:85b3fd62ea1a	758	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
NYX	0:85b3fd62ea1a	759	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
NYX	0:85b3fd62ea1a	760
NYX	0:85b3fd62ea1a	761	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
NYX	0:85b3fd62ea1a	762	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
NYX	0:85b3fd62ea1a	763	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
NYX	0:85b3fd62ea1a	764
NYX	0:85b3fd62ea1a	765	/* Process locked */
NYX	0:85b3fd62ea1a	766	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	767
NYX	0:85b3fd62ea1a	768	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	769	{
NYX	0:85b3fd62ea1a	770	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	771
NYX	0:85b3fd62ea1a	772	/* Update QSPI state */
NYX	0:85b3fd62ea1a	773	hqspi->State = HAL_QSPI_STATE_BUSY;
NYX	0:85b3fd62ea1a	774
NYX	0:85b3fd62ea1a	775	/* Wait till BUSY flag reset */
NYX	0:85b3fd62ea1a	776	count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
NYX	0:85b3fd62ea1a	777	do
NYX	0:85b3fd62ea1a	778	{
NYX	0:85b3fd62ea1a	779	if (count-- == 0U)
NYX	0:85b3fd62ea1a	780	{
NYX	0:85b3fd62ea1a	781	hqspi->State = HAL_QSPI_STATE_ERROR;
NYX	0:85b3fd62ea1a	782	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
NYX	0:85b3fd62ea1a	783	status = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	784	}
NYX	0:85b3fd62ea1a	785	}
NYX	0:85b3fd62ea1a	786	while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
NYX	0:85b3fd62ea1a	787
NYX	0:85b3fd62ea1a	788	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	789	{
NYX	0:85b3fd62ea1a	790	if (cmd->DataMode == QSPI_DATA_NONE)
NYX	0:85b3fd62ea1a	791	{
NYX	0:85b3fd62ea1a	792	/* Clear interrupt */
NYX	0:85b3fd62ea1a	793	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	794	}
NYX	0:85b3fd62ea1a	795
NYX	0:85b3fd62ea1a	796	/* Call the configuration function */
NYX	0:85b3fd62ea1a	797	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
NYX	0:85b3fd62ea1a	798
NYX	0:85b3fd62ea1a	799	if (cmd->DataMode == QSPI_DATA_NONE)
NYX	0:85b3fd62ea1a	800	{
NYX	0:85b3fd62ea1a	801	/* When there is no data phase, the transfer start as soon as the configuration is done
NYX	0:85b3fd62ea1a	802	so activate TC and TE interrupts */
NYX	0:85b3fd62ea1a	803	/* Process unlocked */
NYX	0:85b3fd62ea1a	804	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	805
NYX	0:85b3fd62ea1a	806	/* Enable the QSPI Transfer Error Interrupt */
NYX	0:85b3fd62ea1a	807	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_TC);
NYX	0:85b3fd62ea1a	808	}
NYX	0:85b3fd62ea1a	809	else
NYX	0:85b3fd62ea1a	810	{
NYX	0:85b3fd62ea1a	811	/* Update QSPI state */
NYX	0:85b3fd62ea1a	812	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	813
NYX	0:85b3fd62ea1a	814	/* Process unlocked */
NYX	0:85b3fd62ea1a	815	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	816	}
NYX	0:85b3fd62ea1a	817	}
NYX	0:85b3fd62ea1a	818	else
NYX	0:85b3fd62ea1a	819	{
NYX	0:85b3fd62ea1a	820	/* Process unlocked */
NYX	0:85b3fd62ea1a	821	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	822	}
NYX	0:85b3fd62ea1a	823	}
NYX	0:85b3fd62ea1a	824	else
NYX	0:85b3fd62ea1a	825	{
NYX	0:85b3fd62ea1a	826	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	827
NYX	0:85b3fd62ea1a	828	/* Process unlocked */
NYX	0:85b3fd62ea1a	829	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	830	}
NYX	0:85b3fd62ea1a	831
NYX	0:85b3fd62ea1a	832	/* Return function status */
NYX	0:85b3fd62ea1a	833	return status;
NYX	0:85b3fd62ea1a	834	}
NYX	0:85b3fd62ea1a	835
NYX	0:85b3fd62ea1a	836	/**
NYX	0:85b3fd62ea1a	837	* @brief Transmit an amount of data in blocking mode.
NYX	0:85b3fd62ea1a	838	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	839	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	840	* @param Timeout : Time out duration
NYX	0:85b3fd62ea1a	841	* @note This function is used only in Indirect Write Mode
NYX	0:85b3fd62ea1a	842	* @retval HAL status
NYX	0:85b3fd62ea1a	843	*/
NYX	0:85b3fd62ea1a	844	HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
NYX	0:85b3fd62ea1a	845	{
NYX	0:85b3fd62ea1a	846	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	847	uint32_t tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	848	__IO uint32_t *data_reg = &hqspi->Instance->DR;
NYX	0:85b3fd62ea1a	849
NYX	0:85b3fd62ea1a	850	/* Process locked */
NYX	0:85b3fd62ea1a	851	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	852
NYX	0:85b3fd62ea1a	853	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	854	{
NYX	0:85b3fd62ea1a	855	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	856
NYX	0:85b3fd62ea1a	857	if(pData != NULL )
NYX	0:85b3fd62ea1a	858	{
NYX	0:85b3fd62ea1a	859	/* Update state */
NYX	0:85b3fd62ea1a	860	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
NYX	0:85b3fd62ea1a	861
NYX	0:85b3fd62ea1a	862	/* Configure counters and size of the handle */
NYX	0:85b3fd62ea1a	863	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
NYX	0:85b3fd62ea1a	864	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
NYX	0:85b3fd62ea1a	865	hqspi->pTxBuffPtr = pData;
NYX	0:85b3fd62ea1a	866
NYX	0:85b3fd62ea1a	867	/* Configure QSPI: CCR register with functional as indirect write */
NYX	0:85b3fd62ea1a	868	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
NYX	0:85b3fd62ea1a	869
NYX	0:85b3fd62ea1a	870	while(hqspi->TxXferCount > 0U)
NYX	0:85b3fd62ea1a	871	{
NYX	0:85b3fd62ea1a	872	/* Wait until FT flag is set to send data */
NYX	0:85b3fd62ea1a	873	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
NYX	0:85b3fd62ea1a	874
NYX	0:85b3fd62ea1a	875	if (status != HAL_OK)
NYX	0:85b3fd62ea1a	876	{
NYX	0:85b3fd62ea1a	877	break;
NYX	0:85b3fd62ea1a	878	}
NYX	0:85b3fd62ea1a	879
NYX	0:85b3fd62ea1a	880	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
NYX	0:85b3fd62ea1a	881	hqspi->TxXferCount--;
NYX	0:85b3fd62ea1a	882	}
NYX	0:85b3fd62ea1a	883
NYX	0:85b3fd62ea1a	884	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	885	{
NYX	0:85b3fd62ea1a	886	/* Wait until TC flag is set to go back in idle state */
NYX	0:85b3fd62ea1a	887	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
NYX	0:85b3fd62ea1a	888
NYX	0:85b3fd62ea1a	889	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	890	{
NYX	0:85b3fd62ea1a	891	/* Clear Transfer Complete bit */
NYX	0:85b3fd62ea1a	892	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	893
NYX	0:85b3fd62ea1a	894	/* Clear Busy bit */
NYX	0:85b3fd62ea1a	895	status = HAL_QSPI_Abort(hqspi);
NYX	0:85b3fd62ea1a	896	}
NYX	0:85b3fd62ea1a	897	}
NYX	0:85b3fd62ea1a	898
NYX	0:85b3fd62ea1a	899	/* Update QSPI state */
NYX	0:85b3fd62ea1a	900	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	901	}
NYX	0:85b3fd62ea1a	902	else
NYX	0:85b3fd62ea1a	903	{
NYX	0:85b3fd62ea1a	904	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	905	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	906	}
NYX	0:85b3fd62ea1a	907	}
NYX	0:85b3fd62ea1a	908	else
NYX	0:85b3fd62ea1a	909	{
NYX	0:85b3fd62ea1a	910	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	911	}
NYX	0:85b3fd62ea1a	912
NYX	0:85b3fd62ea1a	913	/* Process unlocked */
NYX	0:85b3fd62ea1a	914	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	915
NYX	0:85b3fd62ea1a	916	return status;
NYX	0:85b3fd62ea1a	917	}
NYX	0:85b3fd62ea1a	918
NYX	0:85b3fd62ea1a	919
NYX	0:85b3fd62ea1a	920	/**
NYX	0:85b3fd62ea1a	921	* @brief Receive an amount of data in blocking mode
NYX	0:85b3fd62ea1a	922	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	923	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	924	* @param Timeout : Time out duration
NYX	0:85b3fd62ea1a	925	* @note This function is used only in Indirect Read Mode
NYX	0:85b3fd62ea1a	926	* @retval HAL status
NYX	0:85b3fd62ea1a	927	*/
NYX	0:85b3fd62ea1a	928	HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
NYX	0:85b3fd62ea1a	929	{
NYX	0:85b3fd62ea1a	930	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	931	uint32_t tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	932	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
NYX	0:85b3fd62ea1a	933	__IO uint32_t *data_reg = &hqspi->Instance->DR;
NYX	0:85b3fd62ea1a	934
NYX	0:85b3fd62ea1a	935	/* Process locked */
NYX	0:85b3fd62ea1a	936	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	937
NYX	0:85b3fd62ea1a	938	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	939	{
NYX	0:85b3fd62ea1a	940	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	941	if(pData != NULL )
NYX	0:85b3fd62ea1a	942	{
NYX	0:85b3fd62ea1a	943	/* Update state */
NYX	0:85b3fd62ea1a	944	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
NYX	0:85b3fd62ea1a	945
NYX	0:85b3fd62ea1a	946	/* Configure counters and size of the handle */
NYX	0:85b3fd62ea1a	947	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
NYX	0:85b3fd62ea1a	948	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
NYX	0:85b3fd62ea1a	949	hqspi->pRxBuffPtr = pData;
NYX	0:85b3fd62ea1a	950
NYX	0:85b3fd62ea1a	951	/* Configure QSPI: CCR register with functional as indirect read */
NYX	0:85b3fd62ea1a	952	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
NYX	0:85b3fd62ea1a	953
NYX	0:85b3fd62ea1a	954	/* Start the transfer by re-writing the address in AR register */
NYX	0:85b3fd62ea1a	955	WRITE_REG(hqspi->Instance->AR, addr_reg);
NYX	0:85b3fd62ea1a	956
NYX	0:85b3fd62ea1a	957	while(hqspi->RxXferCount > 0U)
NYX	0:85b3fd62ea1a	958	{
NYX	0:85b3fd62ea1a	959	/* Wait until FT or TC flag is set to read received data */
NYX	0:85b3fd62ea1a	960	status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT \| QSPI_FLAG_TC), SET, tickstart, Timeout);
NYX	0:85b3fd62ea1a	961
NYX	0:85b3fd62ea1a	962	if (status != HAL_OK)
NYX	0:85b3fd62ea1a	963	{
NYX	0:85b3fd62ea1a	964	break;
NYX	0:85b3fd62ea1a	965	}
NYX	0:85b3fd62ea1a	966
NYX	0:85b3fd62ea1a	967	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
NYX	0:85b3fd62ea1a	968	hqspi->RxXferCount--;
NYX	0:85b3fd62ea1a	969	}
NYX	0:85b3fd62ea1a	970
NYX	0:85b3fd62ea1a	971	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	972	{
NYX	0:85b3fd62ea1a	973	/* Wait until TC flag is set to go back in idle state */
NYX	0:85b3fd62ea1a	974	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
NYX	0:85b3fd62ea1a	975
NYX	0:85b3fd62ea1a	976	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	977	{
NYX	0:85b3fd62ea1a	978	/* Clear Transfer Complete bit */
NYX	0:85b3fd62ea1a	979	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	980
NYX	0:85b3fd62ea1a	981	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
NYX	0:85b3fd62ea1a	982	status = HAL_QSPI_Abort(hqspi);
NYX	0:85b3fd62ea1a	983	}
NYX	0:85b3fd62ea1a	984	}
NYX	0:85b3fd62ea1a	985
NYX	0:85b3fd62ea1a	986	/* Update QSPI state */
NYX	0:85b3fd62ea1a	987	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	988	}
NYX	0:85b3fd62ea1a	989	else
NYX	0:85b3fd62ea1a	990	{
NYX	0:85b3fd62ea1a	991	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	992	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	993	}
NYX	0:85b3fd62ea1a	994	}
NYX	0:85b3fd62ea1a	995	else
NYX	0:85b3fd62ea1a	996	{
NYX	0:85b3fd62ea1a	997	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	998	}
NYX	0:85b3fd62ea1a	999
NYX	0:85b3fd62ea1a	1000	/* Process unlocked */
NYX	0:85b3fd62ea1a	1001	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1002
NYX	0:85b3fd62ea1a	1003	return status;
NYX	0:85b3fd62ea1a	1004	}
NYX	0:85b3fd62ea1a	1005
NYX	0:85b3fd62ea1a	1006	/**
NYX	0:85b3fd62ea1a	1007	* @brief Send an amount of data in interrupt mode
NYX	0:85b3fd62ea1a	1008	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1009	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	1010	* @note This function is used only in Indirect Write Mode
NYX	0:85b3fd62ea1a	1011	* @retval HAL status
NYX	0:85b3fd62ea1a	1012	*/
NYX	0:85b3fd62ea1a	1013	HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
NYX	0:85b3fd62ea1a	1014	{
NYX	0:85b3fd62ea1a	1015	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	1016
NYX	0:85b3fd62ea1a	1017	/* Process locked */
NYX	0:85b3fd62ea1a	1018	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	1019
NYX	0:85b3fd62ea1a	1020	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	1021	{
NYX	0:85b3fd62ea1a	1022	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1023	if(pData != NULL )
NYX	0:85b3fd62ea1a	1024	{
NYX	0:85b3fd62ea1a	1025	/* Update state */
NYX	0:85b3fd62ea1a	1026	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
NYX	0:85b3fd62ea1a	1027
NYX	0:85b3fd62ea1a	1028	/* Configure counters and size of the handle */
NYX	0:85b3fd62ea1a	1029	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
NYX	0:85b3fd62ea1a	1030	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
NYX	0:85b3fd62ea1a	1031	hqspi->pTxBuffPtr = pData;
NYX	0:85b3fd62ea1a	1032
NYX	0:85b3fd62ea1a	1033	/* Configure QSPI: CCR register with functional as indirect write */
NYX	0:85b3fd62ea1a	1034	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
NYX	0:85b3fd62ea1a	1035
NYX	0:85b3fd62ea1a	1036	/* Clear interrupt */
NYX	0:85b3fd62ea1a	1037	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	1038
NYX	0:85b3fd62ea1a	1039	/* Process unlocked */
NYX	0:85b3fd62ea1a	1040	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1041
NYX	0:85b3fd62ea1a	1042	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
NYX	0:85b3fd62ea1a	1043	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
NYX	0:85b3fd62ea1a	1044
NYX	0:85b3fd62ea1a	1045	}
NYX	0:85b3fd62ea1a	1046	else
NYX	0:85b3fd62ea1a	1047	{
NYX	0:85b3fd62ea1a	1048	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	1049	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1050
NYX	0:85b3fd62ea1a	1051	/* Process unlocked */
NYX	0:85b3fd62ea1a	1052	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1053	}
NYX	0:85b3fd62ea1a	1054	}
NYX	0:85b3fd62ea1a	1055	else
NYX	0:85b3fd62ea1a	1056	{
NYX	0:85b3fd62ea1a	1057	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	1058
NYX	0:85b3fd62ea1a	1059	/* Process unlocked */
NYX	0:85b3fd62ea1a	1060	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1061	}
NYX	0:85b3fd62ea1a	1062
NYX	0:85b3fd62ea1a	1063	return status;
NYX	0:85b3fd62ea1a	1064	}
NYX	0:85b3fd62ea1a	1065
NYX	0:85b3fd62ea1a	1066	/**
NYX	0:85b3fd62ea1a	1067	* @brief Receive an amount of data in no-blocking mode with Interrupt
NYX	0:85b3fd62ea1a	1068	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1069	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	1070	* @note This function is used only in Indirect Read Mode
NYX	0:85b3fd62ea1a	1071	* @retval HAL status
NYX	0:85b3fd62ea1a	1072	*/
NYX	0:85b3fd62ea1a	1073	HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
NYX	0:85b3fd62ea1a	1074	{
NYX	0:85b3fd62ea1a	1075	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	1076	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
NYX	0:85b3fd62ea1a	1077
NYX	0:85b3fd62ea1a	1078	/* Process locked */
NYX	0:85b3fd62ea1a	1079	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	1080
NYX	0:85b3fd62ea1a	1081	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	1082	{
NYX	0:85b3fd62ea1a	1083	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1084
NYX	0:85b3fd62ea1a	1085	if(pData != NULL )
NYX	0:85b3fd62ea1a	1086	{
NYX	0:85b3fd62ea1a	1087	/* Update state */
NYX	0:85b3fd62ea1a	1088	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
NYX	0:85b3fd62ea1a	1089
NYX	0:85b3fd62ea1a	1090	/* Configure counters and size of the handle */
NYX	0:85b3fd62ea1a	1091	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
NYX	0:85b3fd62ea1a	1092	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
NYX	0:85b3fd62ea1a	1093	hqspi->pRxBuffPtr = pData;
NYX	0:85b3fd62ea1a	1094
NYX	0:85b3fd62ea1a	1095	/* Configure QSPI: CCR register with functional as indirect read */
NYX	0:85b3fd62ea1a	1096	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
NYX	0:85b3fd62ea1a	1097
NYX	0:85b3fd62ea1a	1098	/* Start the transfer by re-writing the address in AR register */
NYX	0:85b3fd62ea1a	1099	WRITE_REG(hqspi->Instance->AR, addr_reg);
NYX	0:85b3fd62ea1a	1100
NYX	0:85b3fd62ea1a	1101	/* Clear interrupt */
NYX	0:85b3fd62ea1a	1102	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	1103
NYX	0:85b3fd62ea1a	1104	/* Process unlocked */
NYX	0:85b3fd62ea1a	1105	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1106
NYX	0:85b3fd62ea1a	1107	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
NYX	0:85b3fd62ea1a	1108	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
NYX	0:85b3fd62ea1a	1109	}
NYX	0:85b3fd62ea1a	1110	else
NYX	0:85b3fd62ea1a	1111	{
NYX	0:85b3fd62ea1a	1112	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	1113	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1114
NYX	0:85b3fd62ea1a	1115	/* Process unlocked */
NYX	0:85b3fd62ea1a	1116	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1117	}
NYX	0:85b3fd62ea1a	1118	}
NYX	0:85b3fd62ea1a	1119	else
NYX	0:85b3fd62ea1a	1120	{
NYX	0:85b3fd62ea1a	1121	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	1122
NYX	0:85b3fd62ea1a	1123	/* Process unlocked */
NYX	0:85b3fd62ea1a	1124	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1125	}
NYX	0:85b3fd62ea1a	1126
NYX	0:85b3fd62ea1a	1127	return status;
NYX	0:85b3fd62ea1a	1128	}
NYX	0:85b3fd62ea1a	1129
NYX	0:85b3fd62ea1a	1130	/**
NYX	0:85b3fd62ea1a	1131	* @brief Sends an amount of data in non blocking mode with DMA.
NYX	0:85b3fd62ea1a	1132	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1133	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	1134	* @note This function is used only in Indirect Write Mode
NYX	0:85b3fd62ea1a	1135	* @note If DMA peripheral access is configured as halfword, the number
NYX	0:85b3fd62ea1a	1136	* of data and the fifo threshold should be aligned on halfword
NYX	0:85b3fd62ea1a	1137	* @note If DMA peripheral access is configured as word, the number
NYX	0:85b3fd62ea1a	1138	* of data and the fifo threshold should be aligned on word
NYX	0:85b3fd62ea1a	1139	* @retval HAL status
NYX	0:85b3fd62ea1a	1140	*/
NYX	0:85b3fd62ea1a	1141	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
NYX	0:85b3fd62ea1a	1142	{
NYX	0:85b3fd62ea1a	1143	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	1144	uint32_t *tmp;
NYX	0:85b3fd62ea1a	1145	uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
NYX	0:85b3fd62ea1a	1146
NYX	0:85b3fd62ea1a	1147	/* Process locked */
NYX	0:85b3fd62ea1a	1148	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	1149
NYX	0:85b3fd62ea1a	1150	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	1151	{
NYX	0:85b3fd62ea1a	1152	/* Clear the error code */
NYX	0:85b3fd62ea1a	1153	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1154
NYX	0:85b3fd62ea1a	1155	if(pData != NULL )
NYX	0:85b3fd62ea1a	1156	{
NYX	0:85b3fd62ea1a	1157	/* Configure counters of the handle */
NYX	0:85b3fd62ea1a	1158	if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
NYX	0:85b3fd62ea1a	1159	{
NYX	0:85b3fd62ea1a	1160	hqspi->TxXferCount = data_size;
NYX	0:85b3fd62ea1a	1161	}
NYX	0:85b3fd62ea1a	1162	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
NYX	0:85b3fd62ea1a	1163	{
NYX	0:85b3fd62ea1a	1164	if (((data_size % 2U) != 0U) \|\| ((hqspi->Init.FifoThreshold % 2U) != 0U))
NYX	0:85b3fd62ea1a	1165	{
NYX	0:85b3fd62ea1a	1166	/* The number of data or the fifo threshold is not aligned on halfword
NYX	0:85b3fd62ea1a	1167	=> no transfer possible with DMA peripheral access configured as halfword */
NYX	0:85b3fd62ea1a	1168	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	1169	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1170
NYX	0:85b3fd62ea1a	1171	/* Process unlocked */
NYX	0:85b3fd62ea1a	1172	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1173	}
NYX	0:85b3fd62ea1a	1174	else
NYX	0:85b3fd62ea1a	1175	{
NYX	0:85b3fd62ea1a	1176	hqspi->TxXferCount = (data_size >> 1);
NYX	0:85b3fd62ea1a	1177	}
NYX	0:85b3fd62ea1a	1178	}
NYX	0:85b3fd62ea1a	1179	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
NYX	0:85b3fd62ea1a	1180	{
NYX	0:85b3fd62ea1a	1181	if (((data_size % 4U) != 0U) \|\| ((hqspi->Init.FifoThreshold % 4U) != 0U))
NYX	0:85b3fd62ea1a	1182	{
NYX	0:85b3fd62ea1a	1183	/* The number of data or the fifo threshold is not aligned on word
NYX	0:85b3fd62ea1a	1184	=> no transfer possible with DMA peripheral access configured as word */
NYX	0:85b3fd62ea1a	1185	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	1186	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1187
NYX	0:85b3fd62ea1a	1188	/* Process unlocked */
NYX	0:85b3fd62ea1a	1189	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1190	}
NYX	0:85b3fd62ea1a	1191	else
NYX	0:85b3fd62ea1a	1192	{
NYX	0:85b3fd62ea1a	1193	hqspi->TxXferCount = (data_size >> 2U);
NYX	0:85b3fd62ea1a	1194	}
NYX	0:85b3fd62ea1a	1195	}
NYX	0:85b3fd62ea1a	1196
NYX	0:85b3fd62ea1a	1197	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	1198	{
NYX	0:85b3fd62ea1a	1199	/* Update state */
NYX	0:85b3fd62ea1a	1200	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
NYX	0:85b3fd62ea1a	1201
NYX	0:85b3fd62ea1a	1202	/* Clear interrupt */
NYX	0:85b3fd62ea1a	1203	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
NYX	0:85b3fd62ea1a	1204
NYX	0:85b3fd62ea1a	1205	/* Configure size and pointer of the handle */
NYX	0:85b3fd62ea1a	1206	hqspi->TxXferSize = hqspi->TxXferCount;
NYX	0:85b3fd62ea1a	1207	hqspi->pTxBuffPtr = pData;
NYX	0:85b3fd62ea1a	1208
NYX	0:85b3fd62ea1a	1209	/* Configure QSPI: CCR register with functional mode as indirect write */
NYX	0:85b3fd62ea1a	1210	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
NYX	0:85b3fd62ea1a	1211
NYX	0:85b3fd62ea1a	1212	/* Set the QSPI DMA transfer complete callback */
NYX	0:85b3fd62ea1a	1213	hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
NYX	0:85b3fd62ea1a	1214
NYX	0:85b3fd62ea1a	1215	/* Set the QSPI DMA Half transfer complete callback */
NYX	0:85b3fd62ea1a	1216	hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
NYX	0:85b3fd62ea1a	1217
NYX	0:85b3fd62ea1a	1218	/* Set the DMA error callback */
NYX	0:85b3fd62ea1a	1219	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
NYX	0:85b3fd62ea1a	1220
NYX	0:85b3fd62ea1a	1221	/* Clear the DMA abort callback */
NYX	0:85b3fd62ea1a	1222	hqspi->hdma->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1223
NYX	0:85b3fd62ea1a	1224	#if defined (QSPI1_V2_1L)
NYX	0:85b3fd62ea1a	1225	/* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
NYX	0:85b3fd62ea1a	1226	AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
NYX	0:85b3fd62ea1a	1227	Change the following configuration of DMA peripheral
NYX	0:85b3fd62ea1a	1228	- Enable peripheral increment
NYX	0:85b3fd62ea1a	1229	- Disable memory increment
NYX	0:85b3fd62ea1a	1230	- Set DMA direction as peripheral to memory mode */
NYX	0:85b3fd62ea1a	1231
NYX	0:85b3fd62ea1a	1232	/* Enable peripheral increment mode of the DMA */
NYX	0:85b3fd62ea1a	1233	hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
NYX	0:85b3fd62ea1a	1234
NYX	0:85b3fd62ea1a	1235	/* Disable memory increment mode of the DMA */
NYX	0:85b3fd62ea1a	1236	hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
NYX	0:85b3fd62ea1a	1237
NYX	0:85b3fd62ea1a	1238	/* Update peripheral/memory increment mode bits */
NYX	0:85b3fd62ea1a	1239	MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC \| DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc \| hqspi->hdma->Init.PeriphInc));
NYX	0:85b3fd62ea1a	1240
NYX	0:85b3fd62ea1a	1241	/* Configure the direction of the DMA */
NYX	0:85b3fd62ea1a	1242	hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
NYX	0:85b3fd62ea1a	1243	#else
NYX	0:85b3fd62ea1a	1244	/* Configure the direction of the DMA */
NYX	0:85b3fd62ea1a	1245	hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
NYX	0:85b3fd62ea1a	1246	#endif /* QSPI1_V2_1L */
NYX	0:85b3fd62ea1a	1247
NYX	0:85b3fd62ea1a	1248	/* Update direction mode bit */
NYX	0:85b3fd62ea1a	1249	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
NYX	0:85b3fd62ea1a	1250
NYX	0:85b3fd62ea1a	1251	/* Enable the QSPI transmit DMA Channel */
NYX	0:85b3fd62ea1a	1252	tmp = (uint32_t*)&pData;
NYX	0:85b3fd62ea1a	1253	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
NYX	0:85b3fd62ea1a	1254
NYX	0:85b3fd62ea1a	1255	/* Process unlocked */
NYX	0:85b3fd62ea1a	1256	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1257
NYX	0:85b3fd62ea1a	1258	/* Enable the QSPI transfer error Interrupt */
NYX	0:85b3fd62ea1a	1259	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
NYX	0:85b3fd62ea1a	1260
NYX	0:85b3fd62ea1a	1261	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
NYX	0:85b3fd62ea1a	1262	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
NYX	0:85b3fd62ea1a	1263	}
NYX	0:85b3fd62ea1a	1264	}
NYX	0:85b3fd62ea1a	1265	else
NYX	0:85b3fd62ea1a	1266	{
NYX	0:85b3fd62ea1a	1267	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	1268
NYX	0:85b3fd62ea1a	1269	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1270
NYX	0:85b3fd62ea1a	1271	/* Process unlocked */
NYX	0:85b3fd62ea1a	1272	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1273	}
NYX	0:85b3fd62ea1a	1274	}
NYX	0:85b3fd62ea1a	1275	else
NYX	0:85b3fd62ea1a	1276	{
NYX	0:85b3fd62ea1a	1277	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	1278
NYX	0:85b3fd62ea1a	1279	/* Process unlocked */
NYX	0:85b3fd62ea1a	1280	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1281	}
NYX	0:85b3fd62ea1a	1282
NYX	0:85b3fd62ea1a	1283	return status;
NYX	0:85b3fd62ea1a	1284	}
NYX	0:85b3fd62ea1a	1285
NYX	0:85b3fd62ea1a	1286	/**
NYX	0:85b3fd62ea1a	1287	* @brief Receives an amount of data in non blocking mode with DMA.
NYX	0:85b3fd62ea1a	1288	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1289	* @param pData: pointer to data buffer.
NYX	0:85b3fd62ea1a	1290	* @note This function is used only in Indirect Read Mode
NYX	0:85b3fd62ea1a	1291	* @note If DMA peripheral access is configured as halfword, the number
NYX	0:85b3fd62ea1a	1292	* of data and the fifo threshold should be aligned on halfword
NYX	0:85b3fd62ea1a	1293	* @note If DMA peripheral access is configured as word, the number
NYX	0:85b3fd62ea1a	1294	* of data and the fifo threshold should be aligned on word
NYX	0:85b3fd62ea1a	1295	* @retval HAL status
NYX	0:85b3fd62ea1a	1296	*/
NYX	0:85b3fd62ea1a	1297	HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
NYX	0:85b3fd62ea1a	1298	{
NYX	0:85b3fd62ea1a	1299	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	1300	uint32_t *tmp;
NYX	0:85b3fd62ea1a	1301	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
NYX	0:85b3fd62ea1a	1302	uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
NYX	0:85b3fd62ea1a	1303
NYX	0:85b3fd62ea1a	1304	/* Process locked */
NYX	0:85b3fd62ea1a	1305	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	1306
NYX	0:85b3fd62ea1a	1307	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	1308	{
NYX	0:85b3fd62ea1a	1309	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1310
NYX	0:85b3fd62ea1a	1311	if(pData != NULL )
NYX	0:85b3fd62ea1a	1312	{
NYX	0:85b3fd62ea1a	1313	/* Configure counters of the handle */
NYX	0:85b3fd62ea1a	1314	if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
NYX	0:85b3fd62ea1a	1315	{
NYX	0:85b3fd62ea1a	1316	hqspi->RxXferCount = data_size;
NYX	0:85b3fd62ea1a	1317	}
NYX	0:85b3fd62ea1a	1318	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
NYX	0:85b3fd62ea1a	1319	{
NYX	0:85b3fd62ea1a	1320	if (((data_size % 2U) != 0U) \|\| ((hqspi->Init.FifoThreshold % 2U) != 0U))
NYX	0:85b3fd62ea1a	1321	{
NYX	0:85b3fd62ea1a	1322	/* The number of data or the fifo threshold is not aligned on halfword
NYX	0:85b3fd62ea1a	1323	=> no transfer possible with DMA peripheral access configured as halfword */
NYX	0:85b3fd62ea1a	1324	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	1325	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1326
NYX	0:85b3fd62ea1a	1327	/* Process unlocked */
NYX	0:85b3fd62ea1a	1328	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1329	}
NYX	0:85b3fd62ea1a	1330	else
NYX	0:85b3fd62ea1a	1331	{
NYX	0:85b3fd62ea1a	1332	hqspi->RxXferCount = (data_size >> 1U);
NYX	0:85b3fd62ea1a	1333	}
NYX	0:85b3fd62ea1a	1334	}
NYX	0:85b3fd62ea1a	1335	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
NYX	0:85b3fd62ea1a	1336	{
NYX	0:85b3fd62ea1a	1337	if (((data_size % 4U) != 0U) \|\| ((hqspi->Init.FifoThreshold % 4U) != 0U))
NYX	0:85b3fd62ea1a	1338	{
NYX	0:85b3fd62ea1a	1339	/* The number of data or the fifo threshold is not aligned on word
NYX	0:85b3fd62ea1a	1340	=> no transfer possible with DMA peripheral access configured as word */
NYX	0:85b3fd62ea1a	1341	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	1342	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1343
NYX	0:85b3fd62ea1a	1344	/* Process unlocked */
NYX	0:85b3fd62ea1a	1345	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1346	}
NYX	0:85b3fd62ea1a	1347	else
NYX	0:85b3fd62ea1a	1348	{
NYX	0:85b3fd62ea1a	1349	hqspi->RxXferCount = (data_size >> 2U);
NYX	0:85b3fd62ea1a	1350	}
NYX	0:85b3fd62ea1a	1351	}
NYX	0:85b3fd62ea1a	1352
NYX	0:85b3fd62ea1a	1353	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	1354	{
NYX	0:85b3fd62ea1a	1355	/* Update state */
NYX	0:85b3fd62ea1a	1356	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
NYX	0:85b3fd62ea1a	1357
NYX	0:85b3fd62ea1a	1358	/* Clear interrupt */
NYX	0:85b3fd62ea1a	1359	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
NYX	0:85b3fd62ea1a	1360
NYX	0:85b3fd62ea1a	1361	/* Configure size and pointer of the handle */
NYX	0:85b3fd62ea1a	1362	hqspi->RxXferSize = hqspi->RxXferCount;
NYX	0:85b3fd62ea1a	1363	hqspi->pRxBuffPtr = pData;
NYX	0:85b3fd62ea1a	1364
NYX	0:85b3fd62ea1a	1365	/* Set the QSPI DMA transfer complete callback */
NYX	0:85b3fd62ea1a	1366	hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
NYX	0:85b3fd62ea1a	1367
NYX	0:85b3fd62ea1a	1368	/* Set the QSPI DMA Half transfer complete callback */
NYX	0:85b3fd62ea1a	1369	hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
NYX	0:85b3fd62ea1a	1370
NYX	0:85b3fd62ea1a	1371	/* Set the DMA error callback */
NYX	0:85b3fd62ea1a	1372	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
NYX	0:85b3fd62ea1a	1373
NYX	0:85b3fd62ea1a	1374	/* Clear the DMA abort callback */
NYX	0:85b3fd62ea1a	1375	hqspi->hdma->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1376
NYX	0:85b3fd62ea1a	1377	#if defined (QSPI1_V2_1L)
NYX	0:85b3fd62ea1a	1378	/* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
NYX	0:85b3fd62ea1a	1379	AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
NYX	0:85b3fd62ea1a	1380	Change the following configuration of DMA peripheral
NYX	0:85b3fd62ea1a	1381	- Enable peripheral increment
NYX	0:85b3fd62ea1a	1382	- Disable memory increment
NYX	0:85b3fd62ea1a	1383	- Set DMA direction as memory to peripheral mode
NYX	0:85b3fd62ea1a	1384	- 4 Extra words (32-bits) are added for read operation to guarantee
NYX	0:85b3fd62ea1a	1385	the last data is transferred from DMA FIFO to RAM memory */
NYX	0:85b3fd62ea1a	1386
NYX	0:85b3fd62ea1a	1387	/* Enable peripheral increment of the DMA */
NYX	0:85b3fd62ea1a	1388	hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
NYX	0:85b3fd62ea1a	1389
NYX	0:85b3fd62ea1a	1390	/* Disable memory increment of the DMA */
NYX	0:85b3fd62ea1a	1391	hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
NYX	0:85b3fd62ea1a	1392
NYX	0:85b3fd62ea1a	1393	/* Update peripheral/memory increment mode bits */
NYX	0:85b3fd62ea1a	1394	MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC \| DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc \| hqspi->hdma->Init.PeriphInc));
NYX	0:85b3fd62ea1a	1395
NYX	0:85b3fd62ea1a	1396	/* Configure the direction of the DMA */
NYX	0:85b3fd62ea1a	1397	hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
NYX	0:85b3fd62ea1a	1398
NYX	0:85b3fd62ea1a	1399	/* 4 Extra words (32-bits) are needed for read operation to guarantee
NYX	0:85b3fd62ea1a	1400	the last data is transferred from DMA FIFO to RAM memory */
NYX	0:85b3fd62ea1a	1401	WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U));
NYX	0:85b3fd62ea1a	1402
NYX	0:85b3fd62ea1a	1403	/* Update direction mode bit */
NYX	0:85b3fd62ea1a	1404	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
NYX	0:85b3fd62ea1a	1405
NYX	0:85b3fd62ea1a	1406	/* Configure QSPI: CCR register with functional as indirect read */
NYX	0:85b3fd62ea1a	1407	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
NYX	0:85b3fd62ea1a	1408
NYX	0:85b3fd62ea1a	1409	/* Start the transfer by re-writing the address in AR register */
NYX	0:85b3fd62ea1a	1410	WRITE_REG(hqspi->Instance->AR, addr_reg);
NYX	0:85b3fd62ea1a	1411
NYX	0:85b3fd62ea1a	1412	/* Enable the DMA Channel */
NYX	0:85b3fd62ea1a	1413	tmp = (uint32_t*)&pData;
NYX	0:85b3fd62ea1a	1414	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)tmp, hqspi->RxXferSize);
NYX	0:85b3fd62ea1a	1415
NYX	0:85b3fd62ea1a	1416	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
NYX	0:85b3fd62ea1a	1417	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
NYX	0:85b3fd62ea1a	1418
NYX	0:85b3fd62ea1a	1419	/* Process unlocked */
NYX	0:85b3fd62ea1a	1420	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1421
NYX	0:85b3fd62ea1a	1422	/* Enable the QSPI transfer error Interrupt */
NYX	0:85b3fd62ea1a	1423	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
NYX	0:85b3fd62ea1a	1424	#else
NYX	0:85b3fd62ea1a	1425	/* Configure the direction of the DMA */
NYX	0:85b3fd62ea1a	1426	hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
NYX	0:85b3fd62ea1a	1427
NYX	0:85b3fd62ea1a	1428	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
NYX	0:85b3fd62ea1a	1429
NYX	0:85b3fd62ea1a	1430	/* Enable the DMA Channel */
NYX	0:85b3fd62ea1a	1431	tmp = (uint32_t*)&pData;
NYX	0:85b3fd62ea1a	1432	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)tmp, hqspi->RxXferSize);
NYX	0:85b3fd62ea1a	1433
NYX	0:85b3fd62ea1a	1434	/* Configure QSPI: CCR register with functional as indirect read */
NYX	0:85b3fd62ea1a	1435	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
NYX	0:85b3fd62ea1a	1436
NYX	0:85b3fd62ea1a	1437	/* Start the transfer by re-writing the address in AR register */
NYX	0:85b3fd62ea1a	1438	WRITE_REG(hqspi->Instance->AR, addr_reg);
NYX	0:85b3fd62ea1a	1439
NYX	0:85b3fd62ea1a	1440	/* Process unlocked */
NYX	0:85b3fd62ea1a	1441	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1442
NYX	0:85b3fd62ea1a	1443	/* Enable the QSPI transfer error Interrupt */
NYX	0:85b3fd62ea1a	1444	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
NYX	0:85b3fd62ea1a	1445
NYX	0:85b3fd62ea1a	1446	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
NYX	0:85b3fd62ea1a	1447	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
NYX	0:85b3fd62ea1a	1448	#endif /* QSPI1_V2_1L */
NYX	0:85b3fd62ea1a	1449	}
NYX	0:85b3fd62ea1a	1450	}
NYX	0:85b3fd62ea1a	1451	else
NYX	0:85b3fd62ea1a	1452	{
NYX	0:85b3fd62ea1a	1453	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
NYX	0:85b3fd62ea1a	1454	status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1455
NYX	0:85b3fd62ea1a	1456	/* Process unlocked */
NYX	0:85b3fd62ea1a	1457	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1458	}
NYX	0:85b3fd62ea1a	1459	}
NYX	0:85b3fd62ea1a	1460	else
NYX	0:85b3fd62ea1a	1461	{
NYX	0:85b3fd62ea1a	1462	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	1463
NYX	0:85b3fd62ea1a	1464	/* Process unlocked */
NYX	0:85b3fd62ea1a	1465	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1466	}
NYX	0:85b3fd62ea1a	1467
NYX	0:85b3fd62ea1a	1468	return status;
NYX	0:85b3fd62ea1a	1469	}
NYX	0:85b3fd62ea1a	1470
NYX	0:85b3fd62ea1a	1471	/**
NYX	0:85b3fd62ea1a	1472	* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
NYX	0:85b3fd62ea1a	1473	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1474	* @param cmd: structure that contains the command configuration information.
NYX	0:85b3fd62ea1a	1475	* @param cfg: structure that contains the polling configuration information.
NYX	0:85b3fd62ea1a	1476	* @param Timeout : Time out duration
NYX	0:85b3fd62ea1a	1477	* @note This function is used only in Automatic Polling Mode
NYX	0:85b3fd62ea1a	1478	* @retval HAL status
NYX	0:85b3fd62ea1a	1479	*/
NYX	0:85b3fd62ea1a	1480	HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
NYX	0:85b3fd62ea1a	1481	{
NYX	0:85b3fd62ea1a	1482	HAL_StatusTypeDef status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1483	uint32_t tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1484
NYX	0:85b3fd62ea1a	1485	/* Check the parameters */
NYX	0:85b3fd62ea1a	1486	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
NYX	0:85b3fd62ea1a	1487	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
NYX	0:85b3fd62ea1a	1488	{
NYX	0:85b3fd62ea1a	1489	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
NYX	0:85b3fd62ea1a	1490	}
NYX	0:85b3fd62ea1a	1491
NYX	0:85b3fd62ea1a	1492	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
NYX	0:85b3fd62ea1a	1493	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
NYX	0:85b3fd62ea1a	1494	{
NYX	0:85b3fd62ea1a	1495	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
NYX	0:85b3fd62ea1a	1496	}
NYX	0:85b3fd62ea1a	1497
NYX	0:85b3fd62ea1a	1498	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
NYX	0:85b3fd62ea1a	1499	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
NYX	0:85b3fd62ea1a	1500	{
NYX	0:85b3fd62ea1a	1501	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
NYX	0:85b3fd62ea1a	1502	}
NYX	0:85b3fd62ea1a	1503
NYX	0:85b3fd62ea1a	1504	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
NYX	0:85b3fd62ea1a	1505	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
NYX	0:85b3fd62ea1a	1506
NYX	0:85b3fd62ea1a	1507	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
NYX	0:85b3fd62ea1a	1508	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
NYX	0:85b3fd62ea1a	1509	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
NYX	0:85b3fd62ea1a	1510
NYX	0:85b3fd62ea1a	1511	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
NYX	0:85b3fd62ea1a	1512	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
NYX	0:85b3fd62ea1a	1513	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
NYX	0:85b3fd62ea1a	1514
NYX	0:85b3fd62ea1a	1515	/* Process locked */
NYX	0:85b3fd62ea1a	1516	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	1517
NYX	0:85b3fd62ea1a	1518	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	1519	{
NYX	0:85b3fd62ea1a	1520
NYX	0:85b3fd62ea1a	1521	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1522
NYX	0:85b3fd62ea1a	1523	/* Update state */
NYX	0:85b3fd62ea1a	1524	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
NYX	0:85b3fd62ea1a	1525
NYX	0:85b3fd62ea1a	1526	/* Wait till BUSY flag reset */
NYX	0:85b3fd62ea1a	1527	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
NYX	0:85b3fd62ea1a	1528
NYX	0:85b3fd62ea1a	1529	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	1530	{
NYX	0:85b3fd62ea1a	1531	/* Configure QSPI: PSMAR register with the status match value */
NYX	0:85b3fd62ea1a	1532	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
NYX	0:85b3fd62ea1a	1533
NYX	0:85b3fd62ea1a	1534	/* Configure QSPI: PSMKR register with the status mask value */
NYX	0:85b3fd62ea1a	1535	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
NYX	0:85b3fd62ea1a	1536
NYX	0:85b3fd62ea1a	1537	/* Configure QSPI: PIR register with the interval value */
NYX	0:85b3fd62ea1a	1538	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
NYX	0:85b3fd62ea1a	1539
NYX	0:85b3fd62ea1a	1540	/* Configure QSPI: CR register with Match mode and Automatic stop enabled
NYX	0:85b3fd62ea1a	1541	(otherwise there will be an infinite loop in blocking mode) */
NYX	0:85b3fd62ea1a	1542	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
NYX	0:85b3fd62ea1a	1543	(cfg->MatchMode \| QSPI_AUTOMATIC_STOP_ENABLE));
NYX	0:85b3fd62ea1a	1544
NYX	0:85b3fd62ea1a	1545	/* Call the configuration function */
NYX	0:85b3fd62ea1a	1546	cmd->NbData = cfg->StatusBytesSize;
NYX	0:85b3fd62ea1a	1547	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
NYX	0:85b3fd62ea1a	1548
NYX	0:85b3fd62ea1a	1549	/* Wait until SM flag is set to go back in idle state */
NYX	0:85b3fd62ea1a	1550	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
NYX	0:85b3fd62ea1a	1551
NYX	0:85b3fd62ea1a	1552	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	1553	{
NYX	0:85b3fd62ea1a	1554	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
NYX	0:85b3fd62ea1a	1555
NYX	0:85b3fd62ea1a	1556	/* Update state */
NYX	0:85b3fd62ea1a	1557	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	1558	}
NYX	0:85b3fd62ea1a	1559	}
NYX	0:85b3fd62ea1a	1560	}
NYX	0:85b3fd62ea1a	1561	else
NYX	0:85b3fd62ea1a	1562	{
NYX	0:85b3fd62ea1a	1563	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	1564	}
NYX	0:85b3fd62ea1a	1565	/* Process unlocked */
NYX	0:85b3fd62ea1a	1566	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1567
NYX	0:85b3fd62ea1a	1568	/* Return function status */
NYX	0:85b3fd62ea1a	1569	return status;
NYX	0:85b3fd62ea1a	1570	}
NYX	0:85b3fd62ea1a	1571
NYX	0:85b3fd62ea1a	1572	/**
NYX	0:85b3fd62ea1a	1573	* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
NYX	0:85b3fd62ea1a	1574	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1575	* @param cmd: structure that contains the command configuration information.
NYX	0:85b3fd62ea1a	1576	* @param cfg: structure that contains the polling configuration information.
NYX	0:85b3fd62ea1a	1577	* @note This function is used only in Automatic Polling Mode
NYX	0:85b3fd62ea1a	1578	* @retval HAL status
NYX	0:85b3fd62ea1a	1579	*/
NYX	0:85b3fd62ea1a	1580	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg)
NYX	0:85b3fd62ea1a	1581	{
NYX	0:85b3fd62ea1a	1582	__IO uint32_t count = 0U;
NYX	0:85b3fd62ea1a	1583	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	1584
NYX	0:85b3fd62ea1a	1585	/* Check the parameters */
NYX	0:85b3fd62ea1a	1586	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
NYX	0:85b3fd62ea1a	1587	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
NYX	0:85b3fd62ea1a	1588	{
NYX	0:85b3fd62ea1a	1589	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
NYX	0:85b3fd62ea1a	1590	}
NYX	0:85b3fd62ea1a	1591
NYX	0:85b3fd62ea1a	1592	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
NYX	0:85b3fd62ea1a	1593	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
NYX	0:85b3fd62ea1a	1594	{
NYX	0:85b3fd62ea1a	1595	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
NYX	0:85b3fd62ea1a	1596	}
NYX	0:85b3fd62ea1a	1597
NYX	0:85b3fd62ea1a	1598	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
NYX	0:85b3fd62ea1a	1599	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
NYX	0:85b3fd62ea1a	1600	{
NYX	0:85b3fd62ea1a	1601	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
NYX	0:85b3fd62ea1a	1602	}
NYX	0:85b3fd62ea1a	1603
NYX	0:85b3fd62ea1a	1604	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
NYX	0:85b3fd62ea1a	1605	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
NYX	0:85b3fd62ea1a	1606
NYX	0:85b3fd62ea1a	1607	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
NYX	0:85b3fd62ea1a	1608	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
NYX	0:85b3fd62ea1a	1609	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
NYX	0:85b3fd62ea1a	1610
NYX	0:85b3fd62ea1a	1611	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
NYX	0:85b3fd62ea1a	1612	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
NYX	0:85b3fd62ea1a	1613	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
NYX	0:85b3fd62ea1a	1614	assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
NYX	0:85b3fd62ea1a	1615
NYX	0:85b3fd62ea1a	1616	/* Process locked */
NYX	0:85b3fd62ea1a	1617	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	1618
NYX	0:85b3fd62ea1a	1619	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	1620	{
NYX	0:85b3fd62ea1a	1621	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1622
NYX	0:85b3fd62ea1a	1623	/* Update state */
NYX	0:85b3fd62ea1a	1624	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
NYX	0:85b3fd62ea1a	1625
NYX	0:85b3fd62ea1a	1626	/* Wait till BUSY flag reset */
NYX	0:85b3fd62ea1a	1627	count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
NYX	0:85b3fd62ea1a	1628	do
NYX	0:85b3fd62ea1a	1629	{
NYX	0:85b3fd62ea1a	1630	if (count-- == 0U)
NYX	0:85b3fd62ea1a	1631	{
NYX	0:85b3fd62ea1a	1632	hqspi->State = HAL_QSPI_STATE_ERROR;
NYX	0:85b3fd62ea1a	1633	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
NYX	0:85b3fd62ea1a	1634	status = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1635	}
NYX	0:85b3fd62ea1a	1636	}
NYX	0:85b3fd62ea1a	1637	while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
NYX	0:85b3fd62ea1a	1638
NYX	0:85b3fd62ea1a	1639	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	1640	{
NYX	0:85b3fd62ea1a	1641	/* Configure QSPI: PSMAR register with the status match value */
NYX	0:85b3fd62ea1a	1642	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
NYX	0:85b3fd62ea1a	1643
NYX	0:85b3fd62ea1a	1644	/* Configure QSPI: PSMKR register with the status mask value */
NYX	0:85b3fd62ea1a	1645	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
NYX	0:85b3fd62ea1a	1646
NYX	0:85b3fd62ea1a	1647	/* Configure QSPI: PIR register with the interval value */
NYX	0:85b3fd62ea1a	1648	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
NYX	0:85b3fd62ea1a	1649
NYX	0:85b3fd62ea1a	1650	/* Configure QSPI: CR register with Match mode and Automatic stop mode */
NYX	0:85b3fd62ea1a	1651	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
NYX	0:85b3fd62ea1a	1652	(cfg->MatchMode \| cfg->AutomaticStop));
NYX	0:85b3fd62ea1a	1653
NYX	0:85b3fd62ea1a	1654	/* Clear interrupt */
NYX	0:85b3fd62ea1a	1655	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_SM);
NYX	0:85b3fd62ea1a	1656
NYX	0:85b3fd62ea1a	1657	/* Call the configuration function */
NYX	0:85b3fd62ea1a	1658	cmd->NbData = cfg->StatusBytesSize;
NYX	0:85b3fd62ea1a	1659	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
NYX	0:85b3fd62ea1a	1660
NYX	0:85b3fd62ea1a	1661	/* Process unlocked */
NYX	0:85b3fd62ea1a	1662	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1663
NYX	0:85b3fd62ea1a	1664	/* Enable the QSPI Transfer Error and status match Interrupt */
NYX	0:85b3fd62ea1a	1665	__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
NYX	0:85b3fd62ea1a	1666
NYX	0:85b3fd62ea1a	1667	}
NYX	0:85b3fd62ea1a	1668	else
NYX	0:85b3fd62ea1a	1669	{
NYX	0:85b3fd62ea1a	1670	/* Process unlocked */
NYX	0:85b3fd62ea1a	1671	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1672	}
NYX	0:85b3fd62ea1a	1673	}
NYX	0:85b3fd62ea1a	1674	else
NYX	0:85b3fd62ea1a	1675	{
NYX	0:85b3fd62ea1a	1676	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	1677
NYX	0:85b3fd62ea1a	1678	/* Process unlocked */
NYX	0:85b3fd62ea1a	1679	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1680	}
NYX	0:85b3fd62ea1a	1681
NYX	0:85b3fd62ea1a	1682	/* Return function status */
NYX	0:85b3fd62ea1a	1683	return status;
NYX	0:85b3fd62ea1a	1684	}
NYX	0:85b3fd62ea1a	1685
NYX	0:85b3fd62ea1a	1686	/**
NYX	0:85b3fd62ea1a	1687	* @brief Configure the Memory Mapped mode.
NYX	0:85b3fd62ea1a	1688	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1689	* @param cmd: structure that contains the command configuration information.
NYX	0:85b3fd62ea1a	1690	* @param cfg: structure that contains the memory mapped configuration information.
NYX	0:85b3fd62ea1a	1691	* @note This function is used only in Memory mapped Mode
NYX	0:85b3fd62ea1a	1692	* @retval HAL status
NYX	0:85b3fd62ea1a	1693	*/
NYX	0:85b3fd62ea1a	1694	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg)
NYX	0:85b3fd62ea1a	1695	{
NYX	0:85b3fd62ea1a	1696	HAL_StatusTypeDef status = HAL_ERROR;
NYX	0:85b3fd62ea1a	1697	uint32_t tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1698
NYX	0:85b3fd62ea1a	1699	/* Check the parameters */
NYX	0:85b3fd62ea1a	1700	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
NYX	0:85b3fd62ea1a	1701	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
NYX	0:85b3fd62ea1a	1702	{
NYX	0:85b3fd62ea1a	1703	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
NYX	0:85b3fd62ea1a	1704	}
NYX	0:85b3fd62ea1a	1705
NYX	0:85b3fd62ea1a	1706	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
NYX	0:85b3fd62ea1a	1707	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
NYX	0:85b3fd62ea1a	1708	{
NYX	0:85b3fd62ea1a	1709	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
NYX	0:85b3fd62ea1a	1710	}
NYX	0:85b3fd62ea1a	1711
NYX	0:85b3fd62ea1a	1712	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
NYX	0:85b3fd62ea1a	1713	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
NYX	0:85b3fd62ea1a	1714	{
NYX	0:85b3fd62ea1a	1715	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
NYX	0:85b3fd62ea1a	1716	}
NYX	0:85b3fd62ea1a	1717
NYX	0:85b3fd62ea1a	1718	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
NYX	0:85b3fd62ea1a	1719	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
NYX	0:85b3fd62ea1a	1720
NYX	0:85b3fd62ea1a	1721	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
NYX	0:85b3fd62ea1a	1722	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
NYX	0:85b3fd62ea1a	1723	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
NYX	0:85b3fd62ea1a	1724
NYX	0:85b3fd62ea1a	1725	assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
NYX	0:85b3fd62ea1a	1726
NYX	0:85b3fd62ea1a	1727	/* Process locked */
NYX	0:85b3fd62ea1a	1728	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	1729
NYX	0:85b3fd62ea1a	1730	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	1731	{
NYX	0:85b3fd62ea1a	1732	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1733
NYX	0:85b3fd62ea1a	1734	/* Update state */
NYX	0:85b3fd62ea1a	1735	hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
NYX	0:85b3fd62ea1a	1736
NYX	0:85b3fd62ea1a	1737	/* Wait till BUSY flag reset */
NYX	0:85b3fd62ea1a	1738	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
NYX	0:85b3fd62ea1a	1739
NYX	0:85b3fd62ea1a	1740	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	1741	{
NYX	0:85b3fd62ea1a	1742	/* Configure QSPI: CR register with timeout counter enable */
NYX	0:85b3fd62ea1a	1743	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
NYX	0:85b3fd62ea1a	1744
NYX	0:85b3fd62ea1a	1745	if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
NYX	0:85b3fd62ea1a	1746	{
NYX	0:85b3fd62ea1a	1747	assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
NYX	0:85b3fd62ea1a	1748
NYX	0:85b3fd62ea1a	1749	/* Configure QSPI: LPTR register with the low-power timeout value */
NYX	0:85b3fd62ea1a	1750	WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
NYX	0:85b3fd62ea1a	1751
NYX	0:85b3fd62ea1a	1752	/* Clear interrupt */
NYX	0:85b3fd62ea1a	1753	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
NYX	0:85b3fd62ea1a	1754
NYX	0:85b3fd62ea1a	1755	/* Enable the QSPI TimeOut Interrupt */
NYX	0:85b3fd62ea1a	1756	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
NYX	0:85b3fd62ea1a	1757	}
NYX	0:85b3fd62ea1a	1758
NYX	0:85b3fd62ea1a	1759	/* Call the configuration function */
NYX	0:85b3fd62ea1a	1760	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
NYX	0:85b3fd62ea1a	1761	}
NYX	0:85b3fd62ea1a	1762	}
NYX	0:85b3fd62ea1a	1763	else
NYX	0:85b3fd62ea1a	1764	{
NYX	0:85b3fd62ea1a	1765	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	1766	}
NYX	0:85b3fd62ea1a	1767
NYX	0:85b3fd62ea1a	1768	/* Process unlocked */
NYX	0:85b3fd62ea1a	1769	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1770
NYX	0:85b3fd62ea1a	1771	/* Return function status */
NYX	0:85b3fd62ea1a	1772	return status;
NYX	0:85b3fd62ea1a	1773	}
NYX	0:85b3fd62ea1a	1774
NYX	0:85b3fd62ea1a	1775	/**
NYX	0:85b3fd62ea1a	1776	* @brief Transfer Error callbacks
NYX	0:85b3fd62ea1a	1777	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1778	* @retval None
NYX	0:85b3fd62ea1a	1779	*/
NYX	0:85b3fd62ea1a	1780	__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1781	{
NYX	0:85b3fd62ea1a	1782	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1783	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1784
NYX	0:85b3fd62ea1a	1785	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1786	the HAL_QSPI_ErrorCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1787	*/
NYX	0:85b3fd62ea1a	1788	}
NYX	0:85b3fd62ea1a	1789
NYX	0:85b3fd62ea1a	1790	/**
NYX	0:85b3fd62ea1a	1791	* @brief Abort completed callback.
NYX	0:85b3fd62ea1a	1792	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1793	* @retval None
NYX	0:85b3fd62ea1a	1794	*/
NYX	0:85b3fd62ea1a	1795	__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1796	{
NYX	0:85b3fd62ea1a	1797	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1798	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1799
NYX	0:85b3fd62ea1a	1800	/* NOTE: This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1801	the HAL_QSPI_AbortCpltCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1802	*/
NYX	0:85b3fd62ea1a	1803	}
NYX	0:85b3fd62ea1a	1804
NYX	0:85b3fd62ea1a	1805	/**
NYX	0:85b3fd62ea1a	1806	* @brief Command completed callback.
NYX	0:85b3fd62ea1a	1807	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1808	* @retval None
NYX	0:85b3fd62ea1a	1809	*/
NYX	0:85b3fd62ea1a	1810	__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1811	{
NYX	0:85b3fd62ea1a	1812	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1813	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1814
NYX	0:85b3fd62ea1a	1815	/* NOTE: This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1816	the HAL_QSPI_CmdCpltCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1817	*/
NYX	0:85b3fd62ea1a	1818	}
NYX	0:85b3fd62ea1a	1819
NYX	0:85b3fd62ea1a	1820	/**
NYX	0:85b3fd62ea1a	1821	* @brief Rx Transfer completed callbacks.
NYX	0:85b3fd62ea1a	1822	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1823	* @retval None
NYX	0:85b3fd62ea1a	1824	*/
NYX	0:85b3fd62ea1a	1825	__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1826	{
NYX	0:85b3fd62ea1a	1827	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1828	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1829
NYX	0:85b3fd62ea1a	1830	/* NOTE: This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1831	the HAL_QSPI_RxCpltCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1832	*/
NYX	0:85b3fd62ea1a	1833	}
NYX	0:85b3fd62ea1a	1834
NYX	0:85b3fd62ea1a	1835	/**
NYX	0:85b3fd62ea1a	1836	* @brief Tx Transfer completed callbacks.
NYX	0:85b3fd62ea1a	1837	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1838	* @retval None
NYX	0:85b3fd62ea1a	1839	*/
NYX	0:85b3fd62ea1a	1840	__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1841	{
NYX	0:85b3fd62ea1a	1842	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1843	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1844
NYX	0:85b3fd62ea1a	1845	/* NOTE: This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1846	the HAL_QSPI_TxCpltCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1847	*/
NYX	0:85b3fd62ea1a	1848	}
NYX	0:85b3fd62ea1a	1849
NYX	0:85b3fd62ea1a	1850	/**
NYX	0:85b3fd62ea1a	1851	* @brief Rx Half Transfer completed callbacks.
NYX	0:85b3fd62ea1a	1852	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1853	* @retval None
NYX	0:85b3fd62ea1a	1854	*/
NYX	0:85b3fd62ea1a	1855	__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1856	{
NYX	0:85b3fd62ea1a	1857	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1858	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1859
NYX	0:85b3fd62ea1a	1860	/* NOTE: This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1861	the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1862	*/
NYX	0:85b3fd62ea1a	1863	}
NYX	0:85b3fd62ea1a	1864
NYX	0:85b3fd62ea1a	1865	/**
NYX	0:85b3fd62ea1a	1866	* @brief Tx Half Transfer completed callbacks.
NYX	0:85b3fd62ea1a	1867	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1868	* @retval None
NYX	0:85b3fd62ea1a	1869	*/
NYX	0:85b3fd62ea1a	1870	__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1871	{
NYX	0:85b3fd62ea1a	1872	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1873	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1874
NYX	0:85b3fd62ea1a	1875	/* NOTE: This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1876	the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1877	*/
NYX	0:85b3fd62ea1a	1878	}
NYX	0:85b3fd62ea1a	1879
NYX	0:85b3fd62ea1a	1880	/**
NYX	0:85b3fd62ea1a	1881	* @brief FIFO Threshold callbacks
NYX	0:85b3fd62ea1a	1882	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1883	* @retval None
NYX	0:85b3fd62ea1a	1884	*/
NYX	0:85b3fd62ea1a	1885	__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1886	{
NYX	0:85b3fd62ea1a	1887	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1888	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1889
NYX	0:85b3fd62ea1a	1890	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1891	the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1892	*/
NYX	0:85b3fd62ea1a	1893	}
NYX	0:85b3fd62ea1a	1894
NYX	0:85b3fd62ea1a	1895	/**
NYX	0:85b3fd62ea1a	1896	* @brief Status Match callbacks
NYX	0:85b3fd62ea1a	1897	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1898	* @retval None
NYX	0:85b3fd62ea1a	1899	*/
NYX	0:85b3fd62ea1a	1900	__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1901	{
NYX	0:85b3fd62ea1a	1902	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1903	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1904
NYX	0:85b3fd62ea1a	1905	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1906	the HAL_QSPI_StatusMatchCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1907	*/
NYX	0:85b3fd62ea1a	1908	}
NYX	0:85b3fd62ea1a	1909
NYX	0:85b3fd62ea1a	1910	/**
NYX	0:85b3fd62ea1a	1911	* @brief Timeout callbacks
NYX	0:85b3fd62ea1a	1912	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1913	* @retval None
NYX	0:85b3fd62ea1a	1914	*/
NYX	0:85b3fd62ea1a	1915	__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1916	{
NYX	0:85b3fd62ea1a	1917	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1918	UNUSED(hqspi);
NYX	0:85b3fd62ea1a	1919
NYX	0:85b3fd62ea1a	1920	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1921	the HAL_QSPI_TimeOutCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1922	*/
NYX	0:85b3fd62ea1a	1923	}
NYX	0:85b3fd62ea1a	1924
NYX	0:85b3fd62ea1a	1925	/**
NYX	0:85b3fd62ea1a	1926	* @}
NYX	0:85b3fd62ea1a	1927	*/
NYX	0:85b3fd62ea1a	1928
NYX	0:85b3fd62ea1a	1929	/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
NYX	0:85b3fd62ea1a	1930	* @brief QSPI control and State functions
NYX	0:85b3fd62ea1a	1931	*
NYX	0:85b3fd62ea1a	1932	@verbatim
NYX	0:85b3fd62ea1a	1933	===============================================================================
NYX	0:85b3fd62ea1a	1934	##### Peripheral Control and State functions #####
NYX	0:85b3fd62ea1a	1935	===============================================================================
NYX	0:85b3fd62ea1a	1936	[..]
NYX	0:85b3fd62ea1a	1937	This subsection provides a set of functions allowing to :
NYX	0:85b3fd62ea1a	1938	(+) Check in run-time the state of the driver.
NYX	0:85b3fd62ea1a	1939	(+) Check the error code set during last operation.
NYX	0:85b3fd62ea1a	1940	(+) Abort any operation.
NYX	0:85b3fd62ea1a	1941
NYX	0:85b3fd62ea1a	1942	@endverbatim
NYX	0:85b3fd62ea1a	1943	* @{
NYX	0:85b3fd62ea1a	1944	*/
NYX	0:85b3fd62ea1a	1945
NYX	0:85b3fd62ea1a	1946	/**
NYX	0:85b3fd62ea1a	1947	* @brief Return the QSPI handle state.
NYX	0:85b3fd62ea1a	1948	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1949	* @retval HAL state
NYX	0:85b3fd62ea1a	1950	*/
NYX	0:85b3fd62ea1a	1951	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1952	{
NYX	0:85b3fd62ea1a	1953	/* Return QSPI handle state */
NYX	0:85b3fd62ea1a	1954	return hqspi->State;
NYX	0:85b3fd62ea1a	1955	}
NYX	0:85b3fd62ea1a	1956
NYX	0:85b3fd62ea1a	1957	/**
NYX	0:85b3fd62ea1a	1958	* @brief Return the QSPI error code
NYX	0:85b3fd62ea1a	1959	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1960	* @retval QSPI Error Code
NYX	0:85b3fd62ea1a	1961	*/
NYX	0:85b3fd62ea1a	1962	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1963	{
NYX	0:85b3fd62ea1a	1964	return hqspi->ErrorCode;
NYX	0:85b3fd62ea1a	1965	}
NYX	0:85b3fd62ea1a	1966
NYX	0:85b3fd62ea1a	1967	/**
NYX	0:85b3fd62ea1a	1968	* @brief Abort the current transmission
NYX	0:85b3fd62ea1a	1969	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	1970	* @retval HAL status
NYX	0:85b3fd62ea1a	1971	*/
NYX	0:85b3fd62ea1a	1972	HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	1973	{
NYX	0:85b3fd62ea1a	1974	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	1975	uint32_t tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	1976
NYX	0:85b3fd62ea1a	1977	/* Check if the state is in one of the busy states */
NYX	0:85b3fd62ea1a	1978	if ((hqspi->State & 0x2U) != 0U)
NYX	0:85b3fd62ea1a	1979	{
NYX	0:85b3fd62ea1a	1980	/* Process unlocked */
NYX	0:85b3fd62ea1a	1981	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	1982
NYX	0:85b3fd62ea1a	1983	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
NYX	0:85b3fd62ea1a	1984	{
NYX	0:85b3fd62ea1a	1985	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
NYX	0:85b3fd62ea1a	1986	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
NYX	0:85b3fd62ea1a	1987
NYX	0:85b3fd62ea1a	1988	/* Abort DMA channel */
NYX	0:85b3fd62ea1a	1989	status = HAL_DMA_Abort(hqspi->hdma);
NYX	0:85b3fd62ea1a	1990	if(status != HAL_OK)
NYX	0:85b3fd62ea1a	1991	{
NYX	0:85b3fd62ea1a	1992	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
NYX	0:85b3fd62ea1a	1993	}
NYX	0:85b3fd62ea1a	1994	}
NYX	0:85b3fd62ea1a	1995
NYX	0:85b3fd62ea1a	1996	/* Configure QSPI: CR register with Abort request */
NYX	0:85b3fd62ea1a	1997	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
NYX	0:85b3fd62ea1a	1998
NYX	0:85b3fd62ea1a	1999	/* Wait until TC flag is set to go back in idle state */
NYX	0:85b3fd62ea1a	2000	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
NYX	0:85b3fd62ea1a	2001
NYX	0:85b3fd62ea1a	2002	if(status == HAL_OK)
NYX	0:85b3fd62ea1a	2003	{
NYX	0:85b3fd62ea1a	2004	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	2005
NYX	0:85b3fd62ea1a	2006	/* Wait until BUSY flag is reset */
NYX	0:85b3fd62ea1a	2007	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
NYX	0:85b3fd62ea1a	2008	}
NYX	0:85b3fd62ea1a	2009
NYX	0:85b3fd62ea1a	2010	if (status == HAL_OK)
NYX	0:85b3fd62ea1a	2011	{
NYX	0:85b3fd62ea1a	2012	/* Update state */
NYX	0:85b3fd62ea1a	2013	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	2014	}
NYX	0:85b3fd62ea1a	2015	}
NYX	0:85b3fd62ea1a	2016
NYX	0:85b3fd62ea1a	2017	return status;
NYX	0:85b3fd62ea1a	2018	}
NYX	0:85b3fd62ea1a	2019
NYX	0:85b3fd62ea1a	2020	/**
NYX	0:85b3fd62ea1a	2021	* @brief Abort the current transmission (non-blocking function)
NYX	0:85b3fd62ea1a	2022	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	2023	* @retval HAL status
NYX	0:85b3fd62ea1a	2024	*/
NYX	0:85b3fd62ea1a	2025	HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	2026	{
NYX	0:85b3fd62ea1a	2027	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	2028
NYX	0:85b3fd62ea1a	2029	/* Check if the state is in one of the busy states */
NYX	0:85b3fd62ea1a	2030	if ((hqspi->State & 0x2U) != 0U)
NYX	0:85b3fd62ea1a	2031	{
NYX	0:85b3fd62ea1a	2032	/* Process unlocked */
NYX	0:85b3fd62ea1a	2033	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	2034
NYX	0:85b3fd62ea1a	2035	/* Update QSPI state */
NYX	0:85b3fd62ea1a	2036	hqspi->State = HAL_QSPI_STATE_ABORT;
NYX	0:85b3fd62ea1a	2037
NYX	0:85b3fd62ea1a	2038	/* Disable all interrupts */
NYX	0:85b3fd62ea1a	2039	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO \| QSPI_IT_SM \| QSPI_IT_FT \| QSPI_IT_TC \| QSPI_IT_TE));
NYX	0:85b3fd62ea1a	2040
NYX	0:85b3fd62ea1a	2041	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
NYX	0:85b3fd62ea1a	2042	{
NYX	0:85b3fd62ea1a	2043	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
NYX	0:85b3fd62ea1a	2044	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
NYX	0:85b3fd62ea1a	2045
NYX	0:85b3fd62ea1a	2046	/* Abort DMA channel */
NYX	0:85b3fd62ea1a	2047	hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
NYX	0:85b3fd62ea1a	2048	HAL_DMA_Abort_IT(hqspi->hdma);
NYX	0:85b3fd62ea1a	2049	}
NYX	0:85b3fd62ea1a	2050	else
NYX	0:85b3fd62ea1a	2051	{
NYX	0:85b3fd62ea1a	2052	/* Clear interrupt */
NYX	0:85b3fd62ea1a	2053	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	2054
NYX	0:85b3fd62ea1a	2055	/* Enable the QSPI Transfer Complete Interrupt */
NYX	0:85b3fd62ea1a	2056	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
NYX	0:85b3fd62ea1a	2057
NYX	0:85b3fd62ea1a	2058	/* Configure QSPI: CR register with Abort request */
NYX	0:85b3fd62ea1a	2059	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
NYX	0:85b3fd62ea1a	2060	}
NYX	0:85b3fd62ea1a	2061	}
NYX	0:85b3fd62ea1a	2062
NYX	0:85b3fd62ea1a	2063	return status;
NYX	0:85b3fd62ea1a	2064	}
NYX	0:85b3fd62ea1a	2065
NYX	0:85b3fd62ea1a	2066	/** @brief Set QSPI timeout
NYX	0:85b3fd62ea1a	2067	* @param hqspi: QSPI handle.
NYX	0:85b3fd62ea1a	2068	* @param Timeout: Timeout for the QSPI memory access.
NYX	0:85b3fd62ea1a	2069	* @retval None
NYX	0:85b3fd62ea1a	2070	*/
NYX	0:85b3fd62ea1a	2071	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
NYX	0:85b3fd62ea1a	2072	{
NYX	0:85b3fd62ea1a	2073	hqspi->Timeout = Timeout;
NYX	0:85b3fd62ea1a	2074	}
NYX	0:85b3fd62ea1a	2075
NYX	0:85b3fd62ea1a	2076	/** @brief Set QSPI Fifo threshold.
NYX	0:85b3fd62ea1a	2077	* @param hqspi: QSPI handle.
NYX	0:85b3fd62ea1a	2078	* @param Threshold: Threshold of the Fifo (value between 1 and 16).
NYX	0:85b3fd62ea1a	2079	* @retval HAL status
NYX	0:85b3fd62ea1a	2080	*/
NYX	0:85b3fd62ea1a	2081	HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
NYX	0:85b3fd62ea1a	2082	{
NYX	0:85b3fd62ea1a	2083	HAL_StatusTypeDef status = HAL_OK;
NYX	0:85b3fd62ea1a	2084
NYX	0:85b3fd62ea1a	2085	/* Process locked */
NYX	0:85b3fd62ea1a	2086	__HAL_LOCK(hqspi);
NYX	0:85b3fd62ea1a	2087
NYX	0:85b3fd62ea1a	2088	if(hqspi->State == HAL_QSPI_STATE_READY)
NYX	0:85b3fd62ea1a	2089	{
NYX	0:85b3fd62ea1a	2090	/* Synchronize init structure with new FIFO threshold value */
NYX	0:85b3fd62ea1a	2091	hqspi->Init.FifoThreshold = Threshold;
NYX	0:85b3fd62ea1a	2092
NYX	0:85b3fd62ea1a	2093	/* Configure QSPI FIFO Threshold */
NYX	0:85b3fd62ea1a	2094	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
NYX	0:85b3fd62ea1a	2095	((hqspi->Init.FifoThreshold - 1U) << POSITION_VAL(QUADSPI_CR_FTHRES)));
NYX	0:85b3fd62ea1a	2096	}
NYX	0:85b3fd62ea1a	2097	else
NYX	0:85b3fd62ea1a	2098	{
NYX	0:85b3fd62ea1a	2099	status = HAL_BUSY;
NYX	0:85b3fd62ea1a	2100	}
NYX	0:85b3fd62ea1a	2101
NYX	0:85b3fd62ea1a	2102	/* Process unlocked */
NYX	0:85b3fd62ea1a	2103	__HAL_UNLOCK(hqspi);
NYX	0:85b3fd62ea1a	2104
NYX	0:85b3fd62ea1a	2105	/* Return function status */
NYX	0:85b3fd62ea1a	2106	return status;
NYX	0:85b3fd62ea1a	2107	}
NYX	0:85b3fd62ea1a	2108
NYX	0:85b3fd62ea1a	2109	/** @brief Get QSPI Fifo threshold.
NYX	0:85b3fd62ea1a	2110	* @param hqspi: QSPI handle.
NYX	0:85b3fd62ea1a	2111	* @retval Fifo threshold (value between 1 and 16)
NYX	0:85b3fd62ea1a	2112	*/
NYX	0:85b3fd62ea1a	2113	uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
NYX	0:85b3fd62ea1a	2114	{
NYX	0:85b3fd62ea1a	2115	return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1U);
NYX	0:85b3fd62ea1a	2116	}
NYX	0:85b3fd62ea1a	2117
NYX	0:85b3fd62ea1a	2118	/**
NYX	0:85b3fd62ea1a	2119	* @}
NYX	0:85b3fd62ea1a	2120	*/
NYX	0:85b3fd62ea1a	2121
NYX	0:85b3fd62ea1a	2122	/* Private functions ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	2123
NYX	0:85b3fd62ea1a	2124	/**
NYX	0:85b3fd62ea1a	2125	* @brief DMA QSPI receive process complete callback.
NYX	0:85b3fd62ea1a	2126	* @param hdma: DMA handle
NYX	0:85b3fd62ea1a	2127	* @retval None
NYX	0:85b3fd62ea1a	2128	*/
NYX	0:85b3fd62ea1a	2129	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2130	{
NYX	0:85b3fd62ea1a	2131	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2132	hqspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	2133
NYX	0:85b3fd62ea1a	2134	/* Enable the QSPI transfer complete Interrupt */
NYX	0:85b3fd62ea1a	2135	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
NYX	0:85b3fd62ea1a	2136	}
NYX	0:85b3fd62ea1a	2137
NYX	0:85b3fd62ea1a	2138	/**
NYX	0:85b3fd62ea1a	2139	* @brief DMA QSPI transmit process complete callback.
NYX	0:85b3fd62ea1a	2140	* @param hdma: DMA handle
NYX	0:85b3fd62ea1a	2141	* @retval None
NYX	0:85b3fd62ea1a	2142	*/
NYX	0:85b3fd62ea1a	2143	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2144	{
NYX	0:85b3fd62ea1a	2145	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2146	hqspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	2147
NYX	0:85b3fd62ea1a	2148	/* Enable the QSPI transfer complete Interrupt */
NYX	0:85b3fd62ea1a	2149	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
NYX	0:85b3fd62ea1a	2150	}
NYX	0:85b3fd62ea1a	2151
NYX	0:85b3fd62ea1a	2152	/**
NYX	0:85b3fd62ea1a	2153	* @brief DMA QSPI receive process half complete callback
NYX	0:85b3fd62ea1a	2154	* @param hdma : DMA handle
NYX	0:85b3fd62ea1a	2155	* @retval None
NYX	0:85b3fd62ea1a	2156	*/
NYX	0:85b3fd62ea1a	2157	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2158	{
NYX	0:85b3fd62ea1a	2159	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
NYX	0:85b3fd62ea1a	2160
NYX	0:85b3fd62ea1a	2161	HAL_QSPI_RxHalfCpltCallback(hqspi);
NYX	0:85b3fd62ea1a	2162	}
NYX	0:85b3fd62ea1a	2163
NYX	0:85b3fd62ea1a	2164	/**
NYX	0:85b3fd62ea1a	2165	* @brief DMA QSPI transmit process half complete callback
NYX	0:85b3fd62ea1a	2166	* @param hdma : DMA handle
NYX	0:85b3fd62ea1a	2167	* @retval None
NYX	0:85b3fd62ea1a	2168	*/
NYX	0:85b3fd62ea1a	2169	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2170	{
NYX	0:85b3fd62ea1a	2171	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
NYX	0:85b3fd62ea1a	2172
NYX	0:85b3fd62ea1a	2173	HAL_QSPI_TxHalfCpltCallback(hqspi);
NYX	0:85b3fd62ea1a	2174	}
NYX	0:85b3fd62ea1a	2175
NYX	0:85b3fd62ea1a	2176	/**
NYX	0:85b3fd62ea1a	2177	* @brief DMA QSPI communication error callback.
NYX	0:85b3fd62ea1a	2178	* @param hdma: DMA handle
NYX	0:85b3fd62ea1a	2179	* @retval None
NYX	0:85b3fd62ea1a	2180	*/
NYX	0:85b3fd62ea1a	2181	static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2182	{
NYX	0:85b3fd62ea1a	2183	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2184
NYX	0:85b3fd62ea1a	2185	/* if DMA error is FIFO error ignore it */
NYX	0:85b3fd62ea1a	2186	if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
NYX	0:85b3fd62ea1a	2187	{
NYX	0:85b3fd62ea1a	2188	hqspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	2189	hqspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	2190	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
NYX	0:85b3fd62ea1a	2191
NYX	0:85b3fd62ea1a	2192	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
NYX	0:85b3fd62ea1a	2193	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
NYX	0:85b3fd62ea1a	2194
NYX	0:85b3fd62ea1a	2195	/* Abort the QSPI */
NYX	0:85b3fd62ea1a	2196	HAL_QSPI_Abort_IT(hqspi);
NYX	0:85b3fd62ea1a	2197	}
NYX	0:85b3fd62ea1a	2198	}
NYX	0:85b3fd62ea1a	2199
NYX	0:85b3fd62ea1a	2200	/**
NYX	0:85b3fd62ea1a	2201	* @brief DMA QSPI abort complete callback.
NYX	0:85b3fd62ea1a	2202	* @param hdma: DMA handle
NYX	0:85b3fd62ea1a	2203	* @retval None
NYX	0:85b3fd62ea1a	2204	*/
NYX	0:85b3fd62ea1a	2205	static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2206	{
NYX	0:85b3fd62ea1a	2207	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2208
NYX	0:85b3fd62ea1a	2209	hqspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	2210	hqspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	2211
NYX	0:85b3fd62ea1a	2212	if(hqspi->State == HAL_QSPI_STATE_ABORT)
NYX	0:85b3fd62ea1a	2213	{
NYX	0:85b3fd62ea1a	2214	/* DMA Abort called by QSPI abort */
NYX	0:85b3fd62ea1a	2215	/* Clear interrupt */
NYX	0:85b3fd62ea1a	2216	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
NYX	0:85b3fd62ea1a	2217
NYX	0:85b3fd62ea1a	2218	/* Enable the QSPI Transfer Complete Interrupt */
NYX	0:85b3fd62ea1a	2219	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
NYX	0:85b3fd62ea1a	2220
NYX	0:85b3fd62ea1a	2221	/* Configure QSPI: CR register with Abort request */
NYX	0:85b3fd62ea1a	2222	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
NYX	0:85b3fd62ea1a	2223	}
NYX	0:85b3fd62ea1a	2224	else
NYX	0:85b3fd62ea1a	2225	{
NYX	0:85b3fd62ea1a	2226	/* DMA Abort called due to a transfer error interrupt */
NYX	0:85b3fd62ea1a	2227	/* Change state of QSPI */
NYX	0:85b3fd62ea1a	2228	hqspi->State = HAL_QSPI_STATE_READY;
NYX	0:85b3fd62ea1a	2229
NYX	0:85b3fd62ea1a	2230	/* Error callback */
NYX	0:85b3fd62ea1a	2231	HAL_QSPI_ErrorCallback(hqspi);
NYX	0:85b3fd62ea1a	2232	}
NYX	0:85b3fd62ea1a	2233	}
NYX	0:85b3fd62ea1a	2234	/**
NYX	0:85b3fd62ea1a	2235	* @brief Wait for a flag state until timeout.
NYX	0:85b3fd62ea1a	2236	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	2237	* @param Flag: Flag checked
NYX	0:85b3fd62ea1a	2238	* @param State: Value of the flag expected
NYX	0:85b3fd62ea1a	2239	* @param Timeout: Duration of the time out
NYX	0:85b3fd62ea1a	2240	* @param tickstart: tick start value
NYX	0:85b3fd62ea1a	2241	* @retval HAL status
NYX	0:85b3fd62ea1a	2242	*/
NYX	0:85b3fd62ea1a	2243	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
NYX	0:85b3fd62ea1a	2244	FlagStatus State, uint32_t tickstart, uint32_t Timeout)
NYX	0:85b3fd62ea1a	2245	{
NYX	0:85b3fd62ea1a	2246	/* Wait until flag is in expected state */
NYX	0:85b3fd62ea1a	2247	while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
NYX	0:85b3fd62ea1a	2248	{
NYX	0:85b3fd62ea1a	2249	/* Check for the Timeout */
NYX	0:85b3fd62ea1a	2250	if (Timeout != HAL_MAX_DELAY)
NYX	0:85b3fd62ea1a	2251	{
NYX	0:85b3fd62ea1a	2252	if((Timeout == 0U) \|\| ((HAL_GetTick() - tickstart) > Timeout))
NYX	0:85b3fd62ea1a	2253	{
NYX	0:85b3fd62ea1a	2254	hqspi->State = HAL_QSPI_STATE_ERROR;
NYX	0:85b3fd62ea1a	2255	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
NYX	0:85b3fd62ea1a	2256
NYX	0:85b3fd62ea1a	2257	return HAL_ERROR;
NYX	0:85b3fd62ea1a	2258	}
NYX	0:85b3fd62ea1a	2259	}
NYX	0:85b3fd62ea1a	2260	}
NYX	0:85b3fd62ea1a	2261	return HAL_OK;
NYX	0:85b3fd62ea1a	2262	}
NYX	0:85b3fd62ea1a	2263
NYX	0:85b3fd62ea1a	2264	/**
NYX	0:85b3fd62ea1a	2265	* @brief Configure the communication registers.
NYX	0:85b3fd62ea1a	2266	* @param hqspi: QSPI handle
NYX	0:85b3fd62ea1a	2267	* @param cmd: structure that contains the command configuration information
NYX	0:85b3fd62ea1a	2268	* @param FunctionalMode: functional mode to configured
NYX	0:85b3fd62ea1a	2269	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2270	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
NYX	0:85b3fd62ea1a	2271	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
NYX	0:85b3fd62ea1a	2272	* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
NYX	0:85b3fd62ea1a	2273	* @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
NYX	0:85b3fd62ea1a	2274	* @retval None
NYX	0:85b3fd62ea1a	2275	*/
NYX	0:85b3fd62ea1a	2276	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode)
NYX	0:85b3fd62ea1a	2277	{
NYX	0:85b3fd62ea1a	2278	assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
NYX	0:85b3fd62ea1a	2279
NYX	0:85b3fd62ea1a	2280	if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
NYX	0:85b3fd62ea1a	2281	{
NYX	0:85b3fd62ea1a	2282	/* Configure QSPI: DLR register with the number of data to read or write */
NYX	0:85b3fd62ea1a	2283	WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
NYX	0:85b3fd62ea1a	2284	}
NYX	0:85b3fd62ea1a	2285
NYX	0:85b3fd62ea1a	2286	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
NYX	0:85b3fd62ea1a	2287	{
NYX	0:85b3fd62ea1a	2288	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
NYX	0:85b3fd62ea1a	2289	{
NYX	0:85b3fd62ea1a	2290	/* Configure QSPI: ABR register with alternate bytes value */
NYX	0:85b3fd62ea1a	2291	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
NYX	0:85b3fd62ea1a	2292
NYX	0:85b3fd62ea1a	2293	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
NYX	0:85b3fd62ea1a	2294	{
NYX	0:85b3fd62ea1a	2295	/---- Command with instruction, address and alternate bytes ----/
NYX	0:85b3fd62ea1a	2296	/* Configure QSPI: CCR register with all communications parameters */
NYX	0:85b3fd62ea1a	2297	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
NYX	0:85b3fd62ea1a	2298	cmd->DataMode \| (cmd->DummyCycles << 18U) \| cmd->AlternateBytesSize \|
NYX	0:85b3fd62ea1a	2299	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
NYX	0:85b3fd62ea1a	2300	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
NYX	0:85b3fd62ea1a	2301
NYX	0:85b3fd62ea1a	2302	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
NYX	0:85b3fd62ea1a	2303	{
NYX	0:85b3fd62ea1a	2304	/* Configure QSPI: AR register with address value */
NYX	0:85b3fd62ea1a	2305	WRITE_REG(hqspi->Instance->AR, cmd->Address);
NYX	0:85b3fd62ea1a	2306	}
NYX	0:85b3fd62ea1a	2307	}
NYX	0:85b3fd62ea1a	2308	else
NYX	0:85b3fd62ea1a	2309	{
NYX	0:85b3fd62ea1a	2310	/---- Command with instruction and alternate bytes ----/
NYX	0:85b3fd62ea1a	2311	/* Configure QSPI: CCR register with all communications parameters */
NYX	0:85b3fd62ea1a	2312	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
NYX	0:85b3fd62ea1a	2313	cmd->DataMode \| (cmd->DummyCycles << 18U) \| cmd->AlternateBytesSize \|
NYX	0:85b3fd62ea1a	2314	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
NYX	0:85b3fd62ea1a	2315	cmd->Instruction \| FunctionalMode));
NYX	0:85b3fd62ea1a	2316	}
NYX	0:85b3fd62ea1a	2317	}
NYX	0:85b3fd62ea1a	2318	else
NYX	0:85b3fd62ea1a	2319	{
NYX	0:85b3fd62ea1a	2320	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
NYX	0:85b3fd62ea1a	2321	{
NYX	0:85b3fd62ea1a	2322	/---- Command with instruction and address ----/
NYX	0:85b3fd62ea1a	2323	/* Configure QSPI: CCR register with all communications parameters */
NYX	0:85b3fd62ea1a	2324	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
NYX	0:85b3fd62ea1a	2325	cmd->DataMode \| (cmd->DummyCycles << 18U) \| cmd->AlternateByteMode \|
NYX	0:85b3fd62ea1a	2326	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
NYX	0:85b3fd62ea1a	2327	cmd->Instruction \| FunctionalMode));
NYX	0:85b3fd62ea1a	2328
NYX	0:85b3fd62ea1a	2329	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
NYX	0:85b3fd62ea1a	2330	{
NYX	0:85b3fd62ea1a	2331	/* Configure QSPI: AR register with address value */
NYX	0:85b3fd62ea1a	2332	WRITE_REG(hqspi->Instance->AR, cmd->Address);
NYX	0:85b3fd62ea1a	2333	}
NYX	0:85b3fd62ea1a	2334	}
NYX	0:85b3fd62ea1a	2335	else
NYX	0:85b3fd62ea1a	2336	{
NYX	0:85b3fd62ea1a	2337	/---- Command with only instruction ----/
NYX	0:85b3fd62ea1a	2338	/* Configure QSPI: CCR register with all communications parameters */
NYX	0:85b3fd62ea1a	2339	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
NYX	0:85b3fd62ea1a	2340	cmd->DataMode \| (cmd->DummyCycles << 18U) \| cmd->AlternateByteMode \|
NYX	0:85b3fd62ea1a	2341	cmd->AddressMode \| cmd->InstructionMode \| cmd->Instruction \|
NYX	0:85b3fd62ea1a	2342	FunctionalMode));
NYX	0:85b3fd62ea1a	2343	}
NYX	0:85b3fd62ea1a	2344	}
NYX	0:85b3fd62ea1a	2345	}
NYX	0:85b3fd62ea1a	2346	else
NYX	0:85b3fd62ea1a	2347	{
NYX	0:85b3fd62ea1a	2348	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
NYX	0:85b3fd62ea1a	2349	{
NYX	0:85b3fd62ea1a	2350	/* Configure QSPI: ABR register with alternate bytes value */
NYX	0:85b3fd62ea1a	2351	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
NYX	0:85b3fd62ea1a	2352
NYX	0:85b3fd62ea1a	2353	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
NYX	0:85b3fd62ea1a	2354	{
NYX	0:85b3fd62ea1a	2355	/---- Command with address and alternate bytes ----/
NYX	0:85b3fd62ea1a	2356	/* Configure QSPI: CCR register with all communications parameters */
NYX	0:85b3fd62ea1a	2357	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
NYX	0:85b3fd62ea1a	2358	cmd->DataMode \| (cmd->DummyCycles << 18U) \| cmd->AlternateBytesSize \|
NYX	0:85b3fd62ea1a	2359	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
NYX	0:85b3fd62ea1a	2360	cmd->InstructionMode \| FunctionalMode));
NYX	0:85b3fd62ea1a	2361
NYX	0:85b3fd62ea1a	2362	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
NYX	0:85b3fd62ea1a	2363	{
NYX	0:85b3fd62ea1a	2364	/* Configure QSPI: AR register with address value */
NYX	0:85b3fd62ea1a	2365	WRITE_REG(hqspi->Instance->AR, cmd->Address);
NYX	0:85b3fd62ea1a	2366	}
NYX	0:85b3fd62ea1a	2367	}
NYX	0:85b3fd62ea1a	2368	else
NYX	0:85b3fd62ea1a	2369	{
NYX	0:85b3fd62ea1a	2370	/---- Command with only alternate bytes ----/
NYX	0:85b3fd62ea1a	2371	/* Configure QSPI: CCR register with all communications parameters */
NYX	0:85b3fd62ea1a	2372	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
NYX	0:85b3fd62ea1a	2373	cmd->DataMode \| (cmd->DummyCycles << 18U) \| cmd->AlternateBytesSize \|
NYX	0:85b3fd62ea1a	2374	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
NYX	0:85b3fd62ea1a	2375	FunctionalMode));
NYX	0:85b3fd62ea1a	2376	}
NYX	0:85b3fd62ea1a	2377	}
NYX	0:85b3fd62ea1a	2378	else
NYX	0:85b3fd62ea1a	2379	{
NYX	0:85b3fd62ea1a	2380	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
NYX	0:85b3fd62ea1a	2381	{
NYX	0:85b3fd62ea1a	2382	/---- Command with only address ----/
NYX	0:85b3fd62ea1a	2383	/* Configure QSPI: CCR register with all communications parameters */
NYX	0:85b3fd62ea1a	2384	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
NYX	0:85b3fd62ea1a	2385	cmd->DataMode \| (cmd->DummyCycles << 18U) \| cmd->AlternateByteMode \|
NYX	0:85b3fd62ea1a	2386	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
NYX	0:85b3fd62ea1a	2387	FunctionalMode));
NYX	0:85b3fd62ea1a	2388
NYX	0:85b3fd62ea1a	2389	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
NYX	0:85b3fd62ea1a	2390	{
NYX	0:85b3fd62ea1a	2391	/* Configure QSPI: AR register with address value */
NYX	0:85b3fd62ea1a	2392	WRITE_REG(hqspi->Instance->AR, cmd->Address);
NYX	0:85b3fd62ea1a	2393	}
NYX	0:85b3fd62ea1a	2394	}
NYX	0:85b3fd62ea1a	2395	else
NYX	0:85b3fd62ea1a	2396	{
NYX	0:85b3fd62ea1a	2397	/---- Command with only data phase ----/
NYX	0:85b3fd62ea1a	2398	if (cmd->DataMode != QSPI_DATA_NONE)
NYX	0:85b3fd62ea1a	2399	{
NYX	0:85b3fd62ea1a	2400	/* Configure QSPI: CCR register with all communications parameters */
NYX	0:85b3fd62ea1a	2401	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
NYX	0:85b3fd62ea1a	2402	cmd->DataMode \| (cmd->DummyCycles << 18U) \| cmd->AlternateByteMode \|
NYX	0:85b3fd62ea1a	2403	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
NYX	0:85b3fd62ea1a	2404	}
NYX	0:85b3fd62ea1a	2405	}
NYX	0:85b3fd62ea1a	2406	}
NYX	0:85b3fd62ea1a	2407	}
NYX	0:85b3fd62ea1a	2408	}
NYX	0:85b3fd62ea1a	2409	/**
NYX	0:85b3fd62ea1a	2410	* @}
NYX	0:85b3fd62ea1a	2411	*/
NYX	0:85b3fd62ea1a	2412	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx
NYX	0:85b3fd62ea1a	2413	STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	2414
NYX	0:85b3fd62ea1a	2415	#endif /* HAL_QSPI_MODULE_ENABLED */
NYX	0:85b3fd62ea1a	2416	/**
NYX	0:85b3fd62ea1a	2417	* @}
NYX	0:85b3fd62ea1a	2418	*/
NYX	0:85b3fd62ea1a	2419
NYX	0:85b3fd62ea1a	2420	/**
NYX	0:85b3fd62ea1a	2421	* @}
NYX	0:85b3fd62ea1a	2422	*/
NYX	0:85b3fd62ea1a	2423
NYX	0:85b3fd62ea1a	2424	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

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