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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

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NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_pwr.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of PWR HAL module.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 39 #ifndef __STM32F4xx_HAL_PWR_H
NYX 0:85b3fd62ea1a 40 #define __STM32F4xx_HAL_PWR_H
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 43 extern "C" {
NYX 0:85b3fd62ea1a 44 #endif
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 47 #include "stm32f4xx_hal_def.h"
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 50 * @{
NYX 0:85b3fd62ea1a 51 */
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 /** @addtogroup PWR
NYX 0:85b3fd62ea1a 54 * @{
NYX 0:85b3fd62ea1a 55 */
NYX 0:85b3fd62ea1a 56
NYX 0:85b3fd62ea1a 57 /* Exported types ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 /** @defgroup PWR_Exported_Types PWR Exported Types
NYX 0:85b3fd62ea1a 60 * @{
NYX 0:85b3fd62ea1a 61 */
NYX 0:85b3fd62ea1a 62
NYX 0:85b3fd62ea1a 63 /**
NYX 0:85b3fd62ea1a 64 * @brief PWR PVD configuration structure definition
NYX 0:85b3fd62ea1a 65 */
NYX 0:85b3fd62ea1a 66 typedef struct
NYX 0:85b3fd62ea1a 67 {
NYX 0:85b3fd62ea1a 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
NYX 0:85b3fd62ea1a 69 This parameter can be a value of @ref PWR_PVD_detection_level */
NYX 0:85b3fd62ea1a 70
NYX 0:85b3fd62ea1a 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
NYX 0:85b3fd62ea1a 72 This parameter can be a value of @ref PWR_PVD_Mode */
NYX 0:85b3fd62ea1a 73 }PWR_PVDTypeDef;
NYX 0:85b3fd62ea1a 74
NYX 0:85b3fd62ea1a 75 /**
NYX 0:85b3fd62ea1a 76 * @}
NYX 0:85b3fd62ea1a 77 */
NYX 0:85b3fd62ea1a 78
NYX 0:85b3fd62ea1a 79 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 80 /** @defgroup PWR_Exported_Constants PWR Exported Constants
NYX 0:85b3fd62ea1a 81 * @{
NYX 0:85b3fd62ea1a 82 */
NYX 0:85b3fd62ea1a 83
NYX 0:85b3fd62ea1a 84 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
NYX 0:85b3fd62ea1a 85 * @{
NYX 0:85b3fd62ea1a 86 */
NYX 0:85b3fd62ea1a 87 #define PWR_WAKEUP_PIN1 0x00000100U
NYX 0:85b3fd62ea1a 88 /**
NYX 0:85b3fd62ea1a 89 * @}
NYX 0:85b3fd62ea1a 90 */
NYX 0:85b3fd62ea1a 91
NYX 0:85b3fd62ea1a 92 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
NYX 0:85b3fd62ea1a 93 * @{
NYX 0:85b3fd62ea1a 94 */
NYX 0:85b3fd62ea1a 95 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
NYX 0:85b3fd62ea1a 96 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
NYX 0:85b3fd62ea1a 97 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
NYX 0:85b3fd62ea1a 98 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
NYX 0:85b3fd62ea1a 99 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
NYX 0:85b3fd62ea1a 100 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
NYX 0:85b3fd62ea1a 101 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
NYX 0:85b3fd62ea1a 102 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
NYX 0:85b3fd62ea1a 103 (Compare internally to VREFINT) */
NYX 0:85b3fd62ea1a 104 /**
NYX 0:85b3fd62ea1a 105 * @}
NYX 0:85b3fd62ea1a 106 */
NYX 0:85b3fd62ea1a 107
NYX 0:85b3fd62ea1a 108 /** @defgroup PWR_PVD_Mode PWR PVD Mode
NYX 0:85b3fd62ea1a 109 * @{
NYX 0:85b3fd62ea1a 110 */
NYX 0:85b3fd62ea1a 111 #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
NYX 0:85b3fd62ea1a 112 #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
NYX 0:85b3fd62ea1a 113 #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
NYX 0:85b3fd62ea1a 114 #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
NYX 0:85b3fd62ea1a 115 #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
NYX 0:85b3fd62ea1a 116 #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
NYX 0:85b3fd62ea1a 117 #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
NYX 0:85b3fd62ea1a 118 /**
NYX 0:85b3fd62ea1a 119 * @}
NYX 0:85b3fd62ea1a 120 */
NYX 0:85b3fd62ea1a 121
NYX 0:85b3fd62ea1a 122
NYX 0:85b3fd62ea1a 123 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
NYX 0:85b3fd62ea1a 124 * @{
NYX 0:85b3fd62ea1a 125 */
NYX 0:85b3fd62ea1a 126 #define PWR_MAINREGULATOR_ON 0x00000000U
NYX 0:85b3fd62ea1a 127 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
NYX 0:85b3fd62ea1a 128 /**
NYX 0:85b3fd62ea1a 129 * @}
NYX 0:85b3fd62ea1a 130 */
NYX 0:85b3fd62ea1a 131
NYX 0:85b3fd62ea1a 132 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
NYX 0:85b3fd62ea1a 133 * @{
NYX 0:85b3fd62ea1a 134 */
NYX 0:85b3fd62ea1a 135 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 136 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
NYX 0:85b3fd62ea1a 137 /**
NYX 0:85b3fd62ea1a 138 * @}
NYX 0:85b3fd62ea1a 139 */
NYX 0:85b3fd62ea1a 140
NYX 0:85b3fd62ea1a 141 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
NYX 0:85b3fd62ea1a 142 * @{
NYX 0:85b3fd62ea1a 143 */
NYX 0:85b3fd62ea1a 144 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 145 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
NYX 0:85b3fd62ea1a 146 /**
NYX 0:85b3fd62ea1a 147 * @}
NYX 0:85b3fd62ea1a 148 */
NYX 0:85b3fd62ea1a 149
NYX 0:85b3fd62ea1a 150 /** @defgroup PWR_Flag PWR Flag
NYX 0:85b3fd62ea1a 151 * @{
NYX 0:85b3fd62ea1a 152 */
NYX 0:85b3fd62ea1a 153 #define PWR_FLAG_WU PWR_CSR_WUF
NYX 0:85b3fd62ea1a 154 #define PWR_FLAG_SB PWR_CSR_SBF
NYX 0:85b3fd62ea1a 155 #define PWR_FLAG_PVDO PWR_CSR_PVDO
NYX 0:85b3fd62ea1a 156 #define PWR_FLAG_BRR PWR_CSR_BRR
NYX 0:85b3fd62ea1a 157 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
NYX 0:85b3fd62ea1a 158 /**
NYX 0:85b3fd62ea1a 159 * @}
NYX 0:85b3fd62ea1a 160 */
NYX 0:85b3fd62ea1a 161
NYX 0:85b3fd62ea1a 162 /**
NYX 0:85b3fd62ea1a 163 * @}
NYX 0:85b3fd62ea1a 164 */
NYX 0:85b3fd62ea1a 165
NYX 0:85b3fd62ea1a 166 /* Exported macro ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 167 /** @defgroup PWR_Exported_Macro PWR Exported Macro
NYX 0:85b3fd62ea1a 168 * @{
NYX 0:85b3fd62ea1a 169 */
NYX 0:85b3fd62ea1a 170
NYX 0:85b3fd62ea1a 171 /** @brief Check PWR flag is set or not.
NYX 0:85b3fd62ea1a 172 * @param __FLAG__: specifies the flag to check.
NYX 0:85b3fd62ea1a 173 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 174 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
NYX 0:85b3fd62ea1a 175 * was received from the WKUP pin or from the RTC alarm (Alarm A
NYX 0:85b3fd62ea1a 176 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
NYX 0:85b3fd62ea1a 177 * An additional wakeup event is detected if the WKUP pin is enabled
NYX 0:85b3fd62ea1a 178 * (by setting the EWUP bit) when the WKUP pin level is already high.
NYX 0:85b3fd62ea1a 179 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
NYX 0:85b3fd62ea1a 180 * resumed from StandBy mode.
NYX 0:85b3fd62ea1a 181 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
NYX 0:85b3fd62ea1a 182 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
NYX 0:85b3fd62ea1a 183 * For this reason, this bit is equal to 0 after Standby or reset
NYX 0:85b3fd62ea1a 184 * until the PVDE bit is set.
NYX 0:85b3fd62ea1a 185 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
NYX 0:85b3fd62ea1a 186 * when the device wakes up from Standby mode or by a system reset
NYX 0:85b3fd62ea1a 187 * or power reset.
NYX 0:85b3fd62ea1a 188 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
NYX 0:85b3fd62ea1a 189 * scaling output selection is ready.
NYX 0:85b3fd62ea1a 190 * @retval The new state of __FLAG__ (TRUE or FALSE).
NYX 0:85b3fd62ea1a 191 */
NYX 0:85b3fd62ea1a 192 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
NYX 0:85b3fd62ea1a 193
NYX 0:85b3fd62ea1a 194 /** @brief Clear the PWR's pending flags.
NYX 0:85b3fd62ea1a 195 * @param __FLAG__: specifies the flag to clear.
NYX 0:85b3fd62ea1a 196 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 197 * @arg PWR_FLAG_WU: Wake Up flag
NYX 0:85b3fd62ea1a 198 * @arg PWR_FLAG_SB: StandBy flag
NYX 0:85b3fd62ea1a 199 */
NYX 0:85b3fd62ea1a 200 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
NYX 0:85b3fd62ea1a 201
NYX 0:85b3fd62ea1a 202 /**
NYX 0:85b3fd62ea1a 203 * @brief Enable the PVD Exti Line 16.
NYX 0:85b3fd62ea1a 204 * @retval None.
NYX 0:85b3fd62ea1a 205 */
NYX 0:85b3fd62ea1a 206 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
NYX 0:85b3fd62ea1a 207
NYX 0:85b3fd62ea1a 208 /**
NYX 0:85b3fd62ea1a 209 * @brief Disable the PVD EXTI Line 16.
NYX 0:85b3fd62ea1a 210 * @retval None.
NYX 0:85b3fd62ea1a 211 */
NYX 0:85b3fd62ea1a 212 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
NYX 0:85b3fd62ea1a 213
NYX 0:85b3fd62ea1a 214 /**
NYX 0:85b3fd62ea1a 215 * @brief Enable event on PVD Exti Line 16.
NYX 0:85b3fd62ea1a 216 * @retval None.
NYX 0:85b3fd62ea1a 217 */
NYX 0:85b3fd62ea1a 218 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
NYX 0:85b3fd62ea1a 219
NYX 0:85b3fd62ea1a 220 /**
NYX 0:85b3fd62ea1a 221 * @brief Disable event on PVD Exti Line 16.
NYX 0:85b3fd62ea1a 222 * @retval None.
NYX 0:85b3fd62ea1a 223 */
NYX 0:85b3fd62ea1a 224 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
NYX 0:85b3fd62ea1a 225
NYX 0:85b3fd62ea1a 226 /**
NYX 0:85b3fd62ea1a 227 * @brief Enable the PVD Extended Interrupt Rising Trigger.
NYX 0:85b3fd62ea1a 228 * @retval None.
NYX 0:85b3fd62ea1a 229 */
NYX 0:85b3fd62ea1a 230 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
NYX 0:85b3fd62ea1a 231
NYX 0:85b3fd62ea1a 232 /**
NYX 0:85b3fd62ea1a 233 * @brief Disable the PVD Extended Interrupt Rising Trigger.
NYX 0:85b3fd62ea1a 234 * @retval None.
NYX 0:85b3fd62ea1a 235 */
NYX 0:85b3fd62ea1a 236 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
NYX 0:85b3fd62ea1a 237
NYX 0:85b3fd62ea1a 238 /**
NYX 0:85b3fd62ea1a 239 * @brief Enable the PVD Extended Interrupt Falling Trigger.
NYX 0:85b3fd62ea1a 240 * @retval None.
NYX 0:85b3fd62ea1a 241 */
NYX 0:85b3fd62ea1a 242 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
NYX 0:85b3fd62ea1a 243
NYX 0:85b3fd62ea1a 244
NYX 0:85b3fd62ea1a 245 /**
NYX 0:85b3fd62ea1a 246 * @brief Disable the PVD Extended Interrupt Falling Trigger.
NYX 0:85b3fd62ea1a 247 * @retval None.
NYX 0:85b3fd62ea1a 248 */
NYX 0:85b3fd62ea1a 249 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
NYX 0:85b3fd62ea1a 250
NYX 0:85b3fd62ea1a 251
NYX 0:85b3fd62ea1a 252 /**
NYX 0:85b3fd62ea1a 253 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
NYX 0:85b3fd62ea1a 254 * @retval None.
NYX 0:85b3fd62ea1a 255 */
NYX 0:85b3fd62ea1a 256 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
NYX 0:85b3fd62ea1a 257 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
NYX 0:85b3fd62ea1a 258 }while(0U)
NYX 0:85b3fd62ea1a 259
NYX 0:85b3fd62ea1a 260 /**
NYX 0:85b3fd62ea1a 261 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
NYX 0:85b3fd62ea1a 262 * This parameter can be:
NYX 0:85b3fd62ea1a 263 * @retval None.
NYX 0:85b3fd62ea1a 264 */
NYX 0:85b3fd62ea1a 265 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
NYX 0:85b3fd62ea1a 266 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
NYX 0:85b3fd62ea1a 267 }while(0U)
NYX 0:85b3fd62ea1a 268
NYX 0:85b3fd62ea1a 269 /**
NYX 0:85b3fd62ea1a 270 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
NYX 0:85b3fd62ea1a 271 * @retval EXTI PVD Line Status.
NYX 0:85b3fd62ea1a 272 */
NYX 0:85b3fd62ea1a 273 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
NYX 0:85b3fd62ea1a 274
NYX 0:85b3fd62ea1a 275 /**
NYX 0:85b3fd62ea1a 276 * @brief Clear the PVD Exti flag.
NYX 0:85b3fd62ea1a 277 * @retval None.
NYX 0:85b3fd62ea1a 278 */
NYX 0:85b3fd62ea1a 279 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
NYX 0:85b3fd62ea1a 280
NYX 0:85b3fd62ea1a 281 /**
NYX 0:85b3fd62ea1a 282 * @brief Generates a Software interrupt on PVD EXTI line.
NYX 0:85b3fd62ea1a 283 * @retval None
NYX 0:85b3fd62ea1a 284 */
NYX 0:85b3fd62ea1a 285 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
NYX 0:85b3fd62ea1a 286
NYX 0:85b3fd62ea1a 287 /**
NYX 0:85b3fd62ea1a 288 * @}
NYX 0:85b3fd62ea1a 289 */
NYX 0:85b3fd62ea1a 290
NYX 0:85b3fd62ea1a 291 /* Include PWR HAL Extension module */
NYX 0:85b3fd62ea1a 292 #include "stm32f4xx_hal_pwr_ex.h"
NYX 0:85b3fd62ea1a 293
NYX 0:85b3fd62ea1a 294 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 295 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
NYX 0:85b3fd62ea1a 296 * @{
NYX 0:85b3fd62ea1a 297 */
NYX 0:85b3fd62ea1a 298
NYX 0:85b3fd62ea1a 299 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 300 * @{
NYX 0:85b3fd62ea1a 301 */
NYX 0:85b3fd62ea1a 302 /* Initialization and de-initialization functions *****************************/
NYX 0:85b3fd62ea1a 303 void HAL_PWR_DeInit(void);
NYX 0:85b3fd62ea1a 304 void HAL_PWR_EnableBkUpAccess(void);
NYX 0:85b3fd62ea1a 305 void HAL_PWR_DisableBkUpAccess(void);
NYX 0:85b3fd62ea1a 306 /**
NYX 0:85b3fd62ea1a 307 * @}
NYX 0:85b3fd62ea1a 308 */
NYX 0:85b3fd62ea1a 309
NYX 0:85b3fd62ea1a 310 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
NYX 0:85b3fd62ea1a 311 * @{
NYX 0:85b3fd62ea1a 312 */
NYX 0:85b3fd62ea1a 313 /* Peripheral Control functions **********************************************/
NYX 0:85b3fd62ea1a 314 /* PVD configuration */
NYX 0:85b3fd62ea1a 315 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
NYX 0:85b3fd62ea1a 316 void HAL_PWR_EnablePVD(void);
NYX 0:85b3fd62ea1a 317 void HAL_PWR_DisablePVD(void);
NYX 0:85b3fd62ea1a 318
NYX 0:85b3fd62ea1a 319 /* WakeUp pins configuration */
NYX 0:85b3fd62ea1a 320 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
NYX 0:85b3fd62ea1a 321 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
NYX 0:85b3fd62ea1a 322
NYX 0:85b3fd62ea1a 323 /* Low Power modes entry */
NYX 0:85b3fd62ea1a 324 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
NYX 0:85b3fd62ea1a 325 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
NYX 0:85b3fd62ea1a 326 void HAL_PWR_EnterSTANDBYMode(void);
NYX 0:85b3fd62ea1a 327
NYX 0:85b3fd62ea1a 328 /* Power PVD IRQ Handler */
NYX 0:85b3fd62ea1a 329 void HAL_PWR_PVD_IRQHandler(void);
NYX 0:85b3fd62ea1a 330 void HAL_PWR_PVDCallback(void);
NYX 0:85b3fd62ea1a 331
NYX 0:85b3fd62ea1a 332 /* Cortex System Control functions *******************************************/
NYX 0:85b3fd62ea1a 333 void HAL_PWR_EnableSleepOnExit(void);
NYX 0:85b3fd62ea1a 334 void HAL_PWR_DisableSleepOnExit(void);
NYX 0:85b3fd62ea1a 335 void HAL_PWR_EnableSEVOnPend(void);
NYX 0:85b3fd62ea1a 336 void HAL_PWR_DisableSEVOnPend(void);
NYX 0:85b3fd62ea1a 337 /**
NYX 0:85b3fd62ea1a 338 * @}
NYX 0:85b3fd62ea1a 339 */
NYX 0:85b3fd62ea1a 340
NYX 0:85b3fd62ea1a 341 /**
NYX 0:85b3fd62ea1a 342 * @}
NYX 0:85b3fd62ea1a 343 */
NYX 0:85b3fd62ea1a 344
NYX 0:85b3fd62ea1a 345 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 346 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 347 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 348 /** @defgroup PWR_Private_Constants PWR Private Constants
NYX 0:85b3fd62ea1a 349 * @{
NYX 0:85b3fd62ea1a 350 */
NYX 0:85b3fd62ea1a 351
NYX 0:85b3fd62ea1a 352 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
NYX 0:85b3fd62ea1a 353 * @{
NYX 0:85b3fd62ea1a 354 */
NYX 0:85b3fd62ea1a 355 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
NYX 0:85b3fd62ea1a 356 /**
NYX 0:85b3fd62ea1a 357 * @}
NYX 0:85b3fd62ea1a 358 */
NYX 0:85b3fd62ea1a 359
NYX 0:85b3fd62ea1a 360 /** @defgroup PWR_register_alias_address PWR Register alias address
NYX 0:85b3fd62ea1a 361 * @{
NYX 0:85b3fd62ea1a 362 */
NYX 0:85b3fd62ea1a 363 /* ------------- PWR registers bit address in the alias region ---------------*/
NYX 0:85b3fd62ea1a 364 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
NYX 0:85b3fd62ea1a 365 #define PWR_CR_OFFSET 0x00U
NYX 0:85b3fd62ea1a 366 #define PWR_CSR_OFFSET 0x04U
NYX 0:85b3fd62ea1a 367 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
NYX 0:85b3fd62ea1a 368 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
NYX 0:85b3fd62ea1a 369 /**
NYX 0:85b3fd62ea1a 370 * @}
NYX 0:85b3fd62ea1a 371 */
NYX 0:85b3fd62ea1a 372
NYX 0:85b3fd62ea1a 373 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
NYX 0:85b3fd62ea1a 374 * @{
NYX 0:85b3fd62ea1a 375 */
NYX 0:85b3fd62ea1a 376 /* --- CR Register ---*/
NYX 0:85b3fd62ea1a 377 /* Alias word address of DBP bit */
NYX 0:85b3fd62ea1a 378 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
NYX 0:85b3fd62ea1a 379 #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 380
NYX 0:85b3fd62ea1a 381 /* Alias word address of PVDE bit */
NYX 0:85b3fd62ea1a 382 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
NYX 0:85b3fd62ea1a 383 #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 384
NYX 0:85b3fd62ea1a 385 /* Alias word address of PMODE bit */
NYX 0:85b3fd62ea1a 386 #define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
NYX 0:85b3fd62ea1a 387 #define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 388 /**
NYX 0:85b3fd62ea1a 389 * @}
NYX 0:85b3fd62ea1a 390 */
NYX 0:85b3fd62ea1a 391
NYX 0:85b3fd62ea1a 392 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
NYX 0:85b3fd62ea1a 393 * @{
NYX 0:85b3fd62ea1a 394 */
NYX 0:85b3fd62ea1a 395 /* --- CSR Register ---*/
NYX 0:85b3fd62ea1a 396 /* Alias word address of EWUP bit */
NYX 0:85b3fd62ea1a 397 #define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
NYX 0:85b3fd62ea1a 398 #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
NYX 0:85b3fd62ea1a 399 /**
NYX 0:85b3fd62ea1a 400 * @}
NYX 0:85b3fd62ea1a 401 */
NYX 0:85b3fd62ea1a 402
NYX 0:85b3fd62ea1a 403 /**
NYX 0:85b3fd62ea1a 404 * @}
NYX 0:85b3fd62ea1a 405 */
NYX 0:85b3fd62ea1a 406 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 407 /** @defgroup PWR_Private_Macros PWR Private Macros
NYX 0:85b3fd62ea1a 408 * @{
NYX 0:85b3fd62ea1a 409 */
NYX 0:85b3fd62ea1a 410
NYX 0:85b3fd62ea1a 411 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
NYX 0:85b3fd62ea1a 412 * @{
NYX 0:85b3fd62ea1a 413 */
NYX 0:85b3fd62ea1a 414 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
NYX 0:85b3fd62ea1a 415 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
NYX 0:85b3fd62ea1a 416 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
NYX 0:85b3fd62ea1a 417 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
NYX 0:85b3fd62ea1a 418 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
NYX 0:85b3fd62ea1a 419 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
NYX 0:85b3fd62ea1a 420 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
NYX 0:85b3fd62ea1a 421 ((MODE) == PWR_PVD_MODE_NORMAL))
NYX 0:85b3fd62ea1a 422 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
NYX 0:85b3fd62ea1a 423 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
NYX 0:85b3fd62ea1a 424 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
NYX 0:85b3fd62ea1a 425 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
NYX 0:85b3fd62ea1a 426 /**
NYX 0:85b3fd62ea1a 427 * @}
NYX 0:85b3fd62ea1a 428 */
NYX 0:85b3fd62ea1a 429
NYX 0:85b3fd62ea1a 430 /**
NYX 0:85b3fd62ea1a 431 * @}
NYX 0:85b3fd62ea1a 432 */
NYX 0:85b3fd62ea1a 433
NYX 0:85b3fd62ea1a 434 /**
NYX 0:85b3fd62ea1a 435 * @}
NYX 0:85b3fd62ea1a 436 */
NYX 0:85b3fd62ea1a 437
NYX 0:85b3fd62ea1a 438 /**
NYX 0:85b3fd62ea1a 439 * @}
NYX 0:85b3fd62ea1a 440 */
NYX 0:85b3fd62ea1a 441
NYX 0:85b3fd62ea1a 442 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 443 }
NYX 0:85b3fd62ea1a 444 #endif
NYX 0:85b3fd62ea1a 445
NYX 0:85b3fd62ea1a 446
NYX 0:85b3fd62ea1a 447 #endif /* __STM32F4xx_HAL_PWR_H */
NYX 0:85b3fd62ea1a 448
NYX 0:85b3fd62ea1a 449 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/