Takaaki Numai / mbed-dev

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_nor.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief NOR HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides a generic firmware to drive NOR memories mounted
NYX 0:85b3fd62ea1a 9 * as external device.
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 @verbatim
NYX 0:85b3fd62ea1a 12 ==============================================================================
NYX 0:85b3fd62ea1a 13 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 14 ==============================================================================
NYX 0:85b3fd62ea1a 15 [..]
NYX 0:85b3fd62ea1a 16 This driver is a generic layered driver which contains a set of APIs used to
NYX 0:85b3fd62ea1a 17 control NOR flash memories. It uses the FMC/FSMC layer functions to interface
NYX 0:85b3fd62ea1a 18 with NOR devices. This driver is used as follows:
NYX 0:85b3fd62ea1a 19
NYX 0:85b3fd62ea1a 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
NYX 0:85b3fd62ea1a 21 with control and timing parameters for both normal and extended mode.
NYX 0:85b3fd62ea1a 22
NYX 0:85b3fd62ea1a 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
NYX 0:85b3fd62ea1a 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
NYX 0:85b3fd62ea1a 25 structure declared by the function caller.
NYX 0:85b3fd62ea1a 26
NYX 0:85b3fd62ea1a 27 (+) Access NOR flash memory by read/write data unit operations using the functions
NYX 0:85b3fd62ea1a 28 HAL_NOR_Read(), HAL_NOR_Program().
NYX 0:85b3fd62ea1a 29
NYX 0:85b3fd62ea1a 30 (+) Perform NOR flash erase block/chip operations using the functions
NYX 0:85b3fd62ea1a 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
NYX 0:85b3fd62ea1a 32
NYX 0:85b3fd62ea1a 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
NYX 0:85b3fd62ea1a 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
NYX 0:85b3fd62ea1a 35 structure declared by the function caller.
NYX 0:85b3fd62ea1a 36
NYX 0:85b3fd62ea1a 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
NYX 0:85b3fd62ea1a 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
NYX 0:85b3fd62ea1a 39
NYX 0:85b3fd62ea1a 40 (+) You can monitor the NOR device HAL state by calling the function
NYX 0:85b3fd62ea1a 41 HAL_NOR_GetState()
NYX 0:85b3fd62ea1a 42 [..]
NYX 0:85b3fd62ea1a 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
NYX 0:85b3fd62ea1a 44 If a NOR flash device contains different operations and/or implementations,
NYX 0:85b3fd62ea1a 45 it should be implemented separately.
NYX 0:85b3fd62ea1a 46
NYX 0:85b3fd62ea1a 47 *** NOR HAL driver macros list ***
NYX 0:85b3fd62ea1a 48 =============================================
NYX 0:85b3fd62ea1a 49 [..]
NYX 0:85b3fd62ea1a 50 Below the list of most used macros in NOR HAL driver.
NYX 0:85b3fd62ea1a 51
NYX 0:85b3fd62ea1a 52 (+) NOR_WRITE : NOR memory write data to specified address
NYX 0:85b3fd62ea1a 53
NYX 0:85b3fd62ea1a 54 @endverbatim
NYX 0:85b3fd62ea1a 55 ******************************************************************************
NYX 0:85b3fd62ea1a 56 * @attention
NYX 0:85b3fd62ea1a 57 *
NYX 0:85b3fd62ea1a 58 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 59 *
NYX 0:85b3fd62ea1a 60 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 61 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 62 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 63 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 65 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 66 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 68 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 69 * without specific prior written permission.
NYX 0:85b3fd62ea1a 70 *
NYX 0:85b3fd62ea1a 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 81 *
NYX 0:85b3fd62ea1a 82 ******************************************************************************
NYX 0:85b3fd62ea1a 83 */
NYX 0:85b3fd62ea1a 84
NYX 0:85b3fd62ea1a 85 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 86 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 87
NYX 0:85b3fd62ea1a 88 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 89 * @{
NYX 0:85b3fd62ea1a 90 */
NYX 0:85b3fd62ea1a 91
NYX 0:85b3fd62ea1a 92 /** @defgroup NOR NOR
NYX 0:85b3fd62ea1a 93 * @brief NOR driver modules
NYX 0:85b3fd62ea1a 94 * @{
NYX 0:85b3fd62ea1a 95 */
NYX 0:85b3fd62ea1a 96 #ifdef HAL_NOR_MODULE_ENABLED
NYX 0:85b3fd62ea1a 97 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
NYX 0:85b3fd62ea1a 98 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
NYX 0:85b3fd62ea1a 99 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
NYX 0:85b3fd62ea1a 100 defined(STM32F412Vx) || defined(STM32F413xx) || defined(STM32F423xx)
NYX 0:85b3fd62ea1a 101 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 102 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 103
NYX 0:85b3fd62ea1a 104 /** @defgroup NOR_Private_Defines NOR Private Defines
NYX 0:85b3fd62ea1a 105 * @{
NYX 0:85b3fd62ea1a 106 */
NYX 0:85b3fd62ea1a 107
NYX 0:85b3fd62ea1a 108 /* Constants to define address to set to write a command */
NYX 0:85b3fd62ea1a 109 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
NYX 0:85b3fd62ea1a 110 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
NYX 0:85b3fd62ea1a 111 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
NYX 0:85b3fd62ea1a 112 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
NYX 0:85b3fd62ea1a 113 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
NYX 0:85b3fd62ea1a 114 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
NYX 0:85b3fd62ea1a 115 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
NYX 0:85b3fd62ea1a 116
NYX 0:85b3fd62ea1a 117 /* Constants to define data to program a command */
NYX 0:85b3fd62ea1a 118 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
NYX 0:85b3fd62ea1a 119 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
NYX 0:85b3fd62ea1a 120 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
NYX 0:85b3fd62ea1a 121 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
NYX 0:85b3fd62ea1a 122 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
NYX 0:85b3fd62ea1a 123 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
NYX 0:85b3fd62ea1a 124 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
NYX 0:85b3fd62ea1a 125 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
NYX 0:85b3fd62ea1a 126 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
NYX 0:85b3fd62ea1a 127 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
NYX 0:85b3fd62ea1a 128
NYX 0:85b3fd62ea1a 129 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
NYX 0:85b3fd62ea1a 130 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
NYX 0:85b3fd62ea1a 131 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
NYX 0:85b3fd62ea1a 132
NYX 0:85b3fd62ea1a 133 /* Mask on NOR STATUS REGISTER */
NYX 0:85b3fd62ea1a 134 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
NYX 0:85b3fd62ea1a 135 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
NYX 0:85b3fd62ea1a 136
NYX 0:85b3fd62ea1a 137 /**
NYX 0:85b3fd62ea1a 138 * @}
NYX 0:85b3fd62ea1a 139 */
NYX 0:85b3fd62ea1a 140
NYX 0:85b3fd62ea1a 141 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 142 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 143 /** @defgroup NOR_Private_Variables NOR Private Variables
NYX 0:85b3fd62ea1a 144 * @{
NYX 0:85b3fd62ea1a 145 */
NYX 0:85b3fd62ea1a 146
NYX 0:85b3fd62ea1a 147 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
NYX 0:85b3fd62ea1a 148
NYX 0:85b3fd62ea1a 149 /**
NYX 0:85b3fd62ea1a 150 * @}
NYX 0:85b3fd62ea1a 151 */
NYX 0:85b3fd62ea1a 152
NYX 0:85b3fd62ea1a 153 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 154 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 155 /** @defgroup NOR_Exported_Functions NOR Exported Functions
NYX 0:85b3fd62ea1a 156 * @{
NYX 0:85b3fd62ea1a 157 */
NYX 0:85b3fd62ea1a 158
NYX 0:85b3fd62ea1a 159 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 160 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 161 *
NYX 0:85b3fd62ea1a 162 @verbatim
NYX 0:85b3fd62ea1a 163 ==============================================================================
NYX 0:85b3fd62ea1a 164 ##### NOR Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 165 ==============================================================================
NYX 0:85b3fd62ea1a 166 [..]
NYX 0:85b3fd62ea1a 167 This section provides functions allowing to initialize/de-initialize
NYX 0:85b3fd62ea1a 168 the NOR memory
NYX 0:85b3fd62ea1a 169
NYX 0:85b3fd62ea1a 170 @endverbatim
NYX 0:85b3fd62ea1a 171 * @{
NYX 0:85b3fd62ea1a 172 */
NYX 0:85b3fd62ea1a 173
NYX 0:85b3fd62ea1a 174 /**
NYX 0:85b3fd62ea1a 175 * @brief Perform the NOR memory Initialization sequence
NYX 0:85b3fd62ea1a 176 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 177 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 178 * @param Timing: pointer to NOR control timing structure
NYX 0:85b3fd62ea1a 179 * @param ExtTiming: pointer to NOR extended mode timing structure
NYX 0:85b3fd62ea1a 180 * @retval HAL status
NYX 0:85b3fd62ea1a 181 */
NYX 0:85b3fd62ea1a 182 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
NYX 0:85b3fd62ea1a 183 {
NYX 0:85b3fd62ea1a 184 /* Check the NOR handle parameter */
NYX 0:85b3fd62ea1a 185 if(hnor == NULL)
NYX 0:85b3fd62ea1a 186 {
NYX 0:85b3fd62ea1a 187 return HAL_ERROR;
NYX 0:85b3fd62ea1a 188 }
NYX 0:85b3fd62ea1a 189
NYX 0:85b3fd62ea1a 190 if(hnor->State == HAL_NOR_STATE_RESET)
NYX 0:85b3fd62ea1a 191 {
NYX 0:85b3fd62ea1a 192 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 193 hnor->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 194 /* Initialize the low level hardware (MSP) */
NYX 0:85b3fd62ea1a 195 HAL_NOR_MspInit(hnor);
NYX 0:85b3fd62ea1a 196 }
NYX 0:85b3fd62ea1a 197
NYX 0:85b3fd62ea1a 198 /* Initialize NOR control Interface */
NYX 0:85b3fd62ea1a 199 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
NYX 0:85b3fd62ea1a 200
NYX 0:85b3fd62ea1a 201 /* Initialize NOR timing Interface */
NYX 0:85b3fd62ea1a 202 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
NYX 0:85b3fd62ea1a 203
NYX 0:85b3fd62ea1a 204 /* Initialize NOR extended mode timing Interface */
NYX 0:85b3fd62ea1a 205 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
NYX 0:85b3fd62ea1a 206
NYX 0:85b3fd62ea1a 207 /* Enable the NORSRAM device */
NYX 0:85b3fd62ea1a 208 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
NYX 0:85b3fd62ea1a 209
NYX 0:85b3fd62ea1a 210 /* Initialize NOR Memory Data Width*/
NYX 0:85b3fd62ea1a 211 if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
NYX 0:85b3fd62ea1a 212 {
NYX 0:85b3fd62ea1a 213 uwNORMemoryDataWidth = NOR_MEMORY_8B;
NYX 0:85b3fd62ea1a 214 }
NYX 0:85b3fd62ea1a 215 else
NYX 0:85b3fd62ea1a 216 {
NYX 0:85b3fd62ea1a 217 uwNORMemoryDataWidth = NOR_MEMORY_16B;
NYX 0:85b3fd62ea1a 218 }
NYX 0:85b3fd62ea1a 219
NYX 0:85b3fd62ea1a 220 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 221 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 222
NYX 0:85b3fd62ea1a 223 return HAL_OK;
NYX 0:85b3fd62ea1a 224 }
NYX 0:85b3fd62ea1a 225
NYX 0:85b3fd62ea1a 226 /**
NYX 0:85b3fd62ea1a 227 * @brief Perform NOR memory De-Initialization sequence
NYX 0:85b3fd62ea1a 228 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 229 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 230 * @retval HAL status
NYX 0:85b3fd62ea1a 231 */
NYX 0:85b3fd62ea1a 232 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
NYX 0:85b3fd62ea1a 233 {
NYX 0:85b3fd62ea1a 234 /* De-Initialize the low level hardware (MSP) */
NYX 0:85b3fd62ea1a 235 HAL_NOR_MspDeInit(hnor);
NYX 0:85b3fd62ea1a 236
NYX 0:85b3fd62ea1a 237 /* Configure the NOR registers with their reset values */
NYX 0:85b3fd62ea1a 238 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
NYX 0:85b3fd62ea1a 239
NYX 0:85b3fd62ea1a 240 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 241 hnor->State = HAL_NOR_STATE_RESET;
NYX 0:85b3fd62ea1a 242
NYX 0:85b3fd62ea1a 243 /* Release Lock */
NYX 0:85b3fd62ea1a 244 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 245
NYX 0:85b3fd62ea1a 246 return HAL_OK;
NYX 0:85b3fd62ea1a 247 }
NYX 0:85b3fd62ea1a 248
NYX 0:85b3fd62ea1a 249 /**
NYX 0:85b3fd62ea1a 250 * @brief NOR MSP Init
NYX 0:85b3fd62ea1a 251 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 252 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 253 * @retval None
NYX 0:85b3fd62ea1a 254 */
NYX 0:85b3fd62ea1a 255 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
NYX 0:85b3fd62ea1a 256 {
NYX 0:85b3fd62ea1a 257 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 258 UNUSED(hnor);
NYX 0:85b3fd62ea1a 259 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 260 the HAL_NOR_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 261 */
NYX 0:85b3fd62ea1a 262 }
NYX 0:85b3fd62ea1a 263
NYX 0:85b3fd62ea1a 264 /**
NYX 0:85b3fd62ea1a 265 * @brief NOR MSP DeInit
NYX 0:85b3fd62ea1a 266 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 267 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 268 * @retval None
NYX 0:85b3fd62ea1a 269 */
NYX 0:85b3fd62ea1a 270 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
NYX 0:85b3fd62ea1a 271 {
NYX 0:85b3fd62ea1a 272 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 273 UNUSED(hnor);
NYX 0:85b3fd62ea1a 274 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 275 the HAL_NOR_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 276 */
NYX 0:85b3fd62ea1a 277 }
NYX 0:85b3fd62ea1a 278
NYX 0:85b3fd62ea1a 279 /**
NYX 0:85b3fd62ea1a 280 * @brief NOR MSP Wait for Ready/Busy signal
NYX 0:85b3fd62ea1a 281 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 282 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 283 * @param Timeout: Maximum timeout value
NYX 0:85b3fd62ea1a 284 * @retval None
NYX 0:85b3fd62ea1a 285 */
NYX 0:85b3fd62ea1a 286 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
NYX 0:85b3fd62ea1a 287 {
NYX 0:85b3fd62ea1a 288 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 289 UNUSED(hnor);
NYX 0:85b3fd62ea1a 290 UNUSED(Timeout);
NYX 0:85b3fd62ea1a 291
NYX 0:85b3fd62ea1a 292 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 293 the HAL_NOR_MspWait could be implemented in the user file
NYX 0:85b3fd62ea1a 294 */
NYX 0:85b3fd62ea1a 295 }
NYX 0:85b3fd62ea1a 296
NYX 0:85b3fd62ea1a 297 /**
NYX 0:85b3fd62ea1a 298 * @}
NYX 0:85b3fd62ea1a 299 */
NYX 0:85b3fd62ea1a 300
NYX 0:85b3fd62ea1a 301 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
NYX 0:85b3fd62ea1a 302 * @brief Input Output and memory control functions
NYX 0:85b3fd62ea1a 303 *
NYX 0:85b3fd62ea1a 304 @verbatim
NYX 0:85b3fd62ea1a 305 ==============================================================================
NYX 0:85b3fd62ea1a 306 ##### NOR Input and Output functions #####
NYX 0:85b3fd62ea1a 307 ==============================================================================
NYX 0:85b3fd62ea1a 308 [..]
NYX 0:85b3fd62ea1a 309 This section provides functions allowing to use and control the NOR memory
NYX 0:85b3fd62ea1a 310
NYX 0:85b3fd62ea1a 311 @endverbatim
NYX 0:85b3fd62ea1a 312 * @{
NYX 0:85b3fd62ea1a 313 */
NYX 0:85b3fd62ea1a 314
NYX 0:85b3fd62ea1a 315 /**
NYX 0:85b3fd62ea1a 316 * @brief Read NOR flash IDs
NYX 0:85b3fd62ea1a 317 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 318 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 319 * @param pNOR_ID : pointer to NOR ID structure
NYX 0:85b3fd62ea1a 320 * @retval HAL status
NYX 0:85b3fd62ea1a 321 */
NYX 0:85b3fd62ea1a 322 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
NYX 0:85b3fd62ea1a 323 {
NYX 0:85b3fd62ea1a 324 uint32_t deviceaddress = 0U;
NYX 0:85b3fd62ea1a 325
NYX 0:85b3fd62ea1a 326 /* Process Locked */
NYX 0:85b3fd62ea1a 327 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 328
NYX 0:85b3fd62ea1a 329 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 330 if(hnor->State == HAL_NOR_STATE_BUSY)
NYX 0:85b3fd62ea1a 331 {
NYX 0:85b3fd62ea1a 332 return HAL_BUSY;
NYX 0:85b3fd62ea1a 333 }
NYX 0:85b3fd62ea1a 334
NYX 0:85b3fd62ea1a 335 /* Select the NOR device address */
NYX 0:85b3fd62ea1a 336 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 337 {
NYX 0:85b3fd62ea1a 338 deviceaddress = NOR_MEMORY_ADRESS1;
NYX 0:85b3fd62ea1a 339 }
NYX 0:85b3fd62ea1a 340 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
NYX 0:85b3fd62ea1a 341 {
NYX 0:85b3fd62ea1a 342 deviceaddress = NOR_MEMORY_ADRESS2;
NYX 0:85b3fd62ea1a 343 }
NYX 0:85b3fd62ea1a 344 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
NYX 0:85b3fd62ea1a 345 {
NYX 0:85b3fd62ea1a 346 deviceaddress = NOR_MEMORY_ADRESS3;
NYX 0:85b3fd62ea1a 347 }
NYX 0:85b3fd62ea1a 348 else /* FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 349 {
NYX 0:85b3fd62ea1a 350 deviceaddress = NOR_MEMORY_ADRESS4;
NYX 0:85b3fd62ea1a 351 }
NYX 0:85b3fd62ea1a 352
NYX 0:85b3fd62ea1a 353 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 354 hnor->State = HAL_NOR_STATE_BUSY;
NYX 0:85b3fd62ea1a 355
NYX 0:85b3fd62ea1a 356 /* Send read ID command */
NYX 0:85b3fd62ea1a 357 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NYX 0:85b3fd62ea1a 358 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NYX 0:85b3fd62ea1a 359 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
NYX 0:85b3fd62ea1a 360
NYX 0:85b3fd62ea1a 361 /* Read the NOR IDs */
NYX 0:85b3fd62ea1a 362 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
NYX 0:85b3fd62ea1a 363 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
NYX 0:85b3fd62ea1a 364 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
NYX 0:85b3fd62ea1a 365 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
NYX 0:85b3fd62ea1a 366
NYX 0:85b3fd62ea1a 367 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 368 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 369
NYX 0:85b3fd62ea1a 370 /* Process unlocked */
NYX 0:85b3fd62ea1a 371 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 372
NYX 0:85b3fd62ea1a 373 return HAL_OK;
NYX 0:85b3fd62ea1a 374 }
NYX 0:85b3fd62ea1a 375
NYX 0:85b3fd62ea1a 376 /**
NYX 0:85b3fd62ea1a 377 * @brief Returns the NOR memory to Read mode.
NYX 0:85b3fd62ea1a 378 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 379 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 380 * @retval HAL status
NYX 0:85b3fd62ea1a 381 */
NYX 0:85b3fd62ea1a 382 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
NYX 0:85b3fd62ea1a 383 {
NYX 0:85b3fd62ea1a 384 uint32_t deviceaddress = 0U;
NYX 0:85b3fd62ea1a 385
NYX 0:85b3fd62ea1a 386 /* Process Locked */
NYX 0:85b3fd62ea1a 387 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 388
NYX 0:85b3fd62ea1a 389 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 390 if(hnor->State == HAL_NOR_STATE_BUSY)
NYX 0:85b3fd62ea1a 391 {
NYX 0:85b3fd62ea1a 392 return HAL_BUSY;
NYX 0:85b3fd62ea1a 393 }
NYX 0:85b3fd62ea1a 394
NYX 0:85b3fd62ea1a 395 /* Select the NOR device address */
NYX 0:85b3fd62ea1a 396 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 397 {
NYX 0:85b3fd62ea1a 398 deviceaddress = NOR_MEMORY_ADRESS1;
NYX 0:85b3fd62ea1a 399 }
NYX 0:85b3fd62ea1a 400 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
NYX 0:85b3fd62ea1a 401 {
NYX 0:85b3fd62ea1a 402 deviceaddress = NOR_MEMORY_ADRESS2;
NYX 0:85b3fd62ea1a 403 }
NYX 0:85b3fd62ea1a 404 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
NYX 0:85b3fd62ea1a 405 {
NYX 0:85b3fd62ea1a 406 deviceaddress = NOR_MEMORY_ADRESS3;
NYX 0:85b3fd62ea1a 407 }
NYX 0:85b3fd62ea1a 408 else /* FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 409 {
NYX 0:85b3fd62ea1a 410 deviceaddress = NOR_MEMORY_ADRESS4;
NYX 0:85b3fd62ea1a 411 }
NYX 0:85b3fd62ea1a 412
NYX 0:85b3fd62ea1a 413 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
NYX 0:85b3fd62ea1a 414
NYX 0:85b3fd62ea1a 415 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 416 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 417
NYX 0:85b3fd62ea1a 418 /* Process unlocked */
NYX 0:85b3fd62ea1a 419 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 420
NYX 0:85b3fd62ea1a 421 return HAL_OK;
NYX 0:85b3fd62ea1a 422 }
NYX 0:85b3fd62ea1a 423
NYX 0:85b3fd62ea1a 424 /**
NYX 0:85b3fd62ea1a 425 * @brief Read data from NOR memory
NYX 0:85b3fd62ea1a 426 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 427 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 428 * @param pAddress: pointer to Device address
NYX 0:85b3fd62ea1a 429 * @param pData : pointer to read data
NYX 0:85b3fd62ea1a 430 * @retval HAL status
NYX 0:85b3fd62ea1a 431 */
NYX 0:85b3fd62ea1a 432 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
NYX 0:85b3fd62ea1a 433 {
NYX 0:85b3fd62ea1a 434 uint32_t deviceaddress = 0U;
NYX 0:85b3fd62ea1a 435
NYX 0:85b3fd62ea1a 436 /* Process Locked */
NYX 0:85b3fd62ea1a 437 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 438
NYX 0:85b3fd62ea1a 439 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 440 if(hnor->State == HAL_NOR_STATE_BUSY)
NYX 0:85b3fd62ea1a 441 {
NYX 0:85b3fd62ea1a 442 return HAL_BUSY;
NYX 0:85b3fd62ea1a 443 }
NYX 0:85b3fd62ea1a 444
NYX 0:85b3fd62ea1a 445 /* Select the NOR device address */
NYX 0:85b3fd62ea1a 446 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 447 {
NYX 0:85b3fd62ea1a 448 deviceaddress = NOR_MEMORY_ADRESS1;
NYX 0:85b3fd62ea1a 449 }
NYX 0:85b3fd62ea1a 450 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
NYX 0:85b3fd62ea1a 451 {
NYX 0:85b3fd62ea1a 452 deviceaddress = NOR_MEMORY_ADRESS2;
NYX 0:85b3fd62ea1a 453 }
NYX 0:85b3fd62ea1a 454 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
NYX 0:85b3fd62ea1a 455 {
NYX 0:85b3fd62ea1a 456 deviceaddress = NOR_MEMORY_ADRESS3;
NYX 0:85b3fd62ea1a 457 }
NYX 0:85b3fd62ea1a 458 else /* FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 459 {
NYX 0:85b3fd62ea1a 460 deviceaddress = NOR_MEMORY_ADRESS4;
NYX 0:85b3fd62ea1a 461 }
NYX 0:85b3fd62ea1a 462
NYX 0:85b3fd62ea1a 463 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 464 hnor->State = HAL_NOR_STATE_BUSY;
NYX 0:85b3fd62ea1a 465
NYX 0:85b3fd62ea1a 466 /* Send read data command */
NYX 0:85b3fd62ea1a 467 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NYX 0:85b3fd62ea1a 468 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NYX 0:85b3fd62ea1a 469 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
NYX 0:85b3fd62ea1a 470
NYX 0:85b3fd62ea1a 471 /* Read the data */
NYX 0:85b3fd62ea1a 472 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
NYX 0:85b3fd62ea1a 473
NYX 0:85b3fd62ea1a 474 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 475 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 476
NYX 0:85b3fd62ea1a 477 /* Process unlocked */
NYX 0:85b3fd62ea1a 478 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 479
NYX 0:85b3fd62ea1a 480 return HAL_OK;
NYX 0:85b3fd62ea1a 481 }
NYX 0:85b3fd62ea1a 482
NYX 0:85b3fd62ea1a 483 /**
NYX 0:85b3fd62ea1a 484 * @brief Program data to NOR memory
NYX 0:85b3fd62ea1a 485 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 486 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 487 * @param pAddress: Device address
NYX 0:85b3fd62ea1a 488 * @param pData : pointer to the data to write
NYX 0:85b3fd62ea1a 489 * @retval HAL status
NYX 0:85b3fd62ea1a 490 */
NYX 0:85b3fd62ea1a 491 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
NYX 0:85b3fd62ea1a 492 {
NYX 0:85b3fd62ea1a 493 uint32_t deviceaddress = 0U;
NYX 0:85b3fd62ea1a 494
NYX 0:85b3fd62ea1a 495 /* Process Locked */
NYX 0:85b3fd62ea1a 496 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 497
NYX 0:85b3fd62ea1a 498 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 499 if(hnor->State == HAL_NOR_STATE_BUSY)
NYX 0:85b3fd62ea1a 500 {
NYX 0:85b3fd62ea1a 501 return HAL_BUSY;
NYX 0:85b3fd62ea1a 502 }
NYX 0:85b3fd62ea1a 503
NYX 0:85b3fd62ea1a 504 /* Select the NOR device address */
NYX 0:85b3fd62ea1a 505 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 506 {
NYX 0:85b3fd62ea1a 507 deviceaddress = NOR_MEMORY_ADRESS1;
NYX 0:85b3fd62ea1a 508 }
NYX 0:85b3fd62ea1a 509 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
NYX 0:85b3fd62ea1a 510 {
NYX 0:85b3fd62ea1a 511 deviceaddress = NOR_MEMORY_ADRESS2;
NYX 0:85b3fd62ea1a 512 }
NYX 0:85b3fd62ea1a 513 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
NYX 0:85b3fd62ea1a 514 {
NYX 0:85b3fd62ea1a 515 deviceaddress = NOR_MEMORY_ADRESS3;
NYX 0:85b3fd62ea1a 516 }
NYX 0:85b3fd62ea1a 517 else /* FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 518 {
NYX 0:85b3fd62ea1a 519 deviceaddress = NOR_MEMORY_ADRESS4;
NYX 0:85b3fd62ea1a 520 }
NYX 0:85b3fd62ea1a 521
NYX 0:85b3fd62ea1a 522 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 523 hnor->State = HAL_NOR_STATE_BUSY;
NYX 0:85b3fd62ea1a 524
NYX 0:85b3fd62ea1a 525 /* Send program data command */
NYX 0:85b3fd62ea1a 526 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NYX 0:85b3fd62ea1a 527 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NYX 0:85b3fd62ea1a 528 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
NYX 0:85b3fd62ea1a 529
NYX 0:85b3fd62ea1a 530 /* Write the data */
NYX 0:85b3fd62ea1a 531 NOR_WRITE(pAddress, *pData);
NYX 0:85b3fd62ea1a 532
NYX 0:85b3fd62ea1a 533 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 534 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 535
NYX 0:85b3fd62ea1a 536 /* Process unlocked */
NYX 0:85b3fd62ea1a 537 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 return HAL_OK;
NYX 0:85b3fd62ea1a 540 }
NYX 0:85b3fd62ea1a 541
NYX 0:85b3fd62ea1a 542 /**
NYX 0:85b3fd62ea1a 543 * @brief Reads a half-word buffer from the NOR memory.
NYX 0:85b3fd62ea1a 544 * @param hnor: pointer to the NOR handle
NYX 0:85b3fd62ea1a 545 * @param uwAddress: NOR memory internal address to read from.
NYX 0:85b3fd62ea1a 546 * @param pData: pointer to the buffer that receives the data read from the
NYX 0:85b3fd62ea1a 547 * NOR memory.
NYX 0:85b3fd62ea1a 548 * @param uwBufferSize : number of Half word to read.
NYX 0:85b3fd62ea1a 549 * @retval HAL status
NYX 0:85b3fd62ea1a 550 */
NYX 0:85b3fd62ea1a 551 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
NYX 0:85b3fd62ea1a 552 {
NYX 0:85b3fd62ea1a 553 uint32_t deviceaddress = 0U;
NYX 0:85b3fd62ea1a 554
NYX 0:85b3fd62ea1a 555 /* Process Locked */
NYX 0:85b3fd62ea1a 556 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 557
NYX 0:85b3fd62ea1a 558 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 559 if(hnor->State == HAL_NOR_STATE_BUSY)
NYX 0:85b3fd62ea1a 560 {
NYX 0:85b3fd62ea1a 561 return HAL_BUSY;
NYX 0:85b3fd62ea1a 562 }
NYX 0:85b3fd62ea1a 563
NYX 0:85b3fd62ea1a 564 /* Select the NOR device address */
NYX 0:85b3fd62ea1a 565 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 566 {
NYX 0:85b3fd62ea1a 567 deviceaddress = NOR_MEMORY_ADRESS1;
NYX 0:85b3fd62ea1a 568 }
NYX 0:85b3fd62ea1a 569 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
NYX 0:85b3fd62ea1a 570 {
NYX 0:85b3fd62ea1a 571 deviceaddress = NOR_MEMORY_ADRESS2;
NYX 0:85b3fd62ea1a 572 }
NYX 0:85b3fd62ea1a 573 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
NYX 0:85b3fd62ea1a 574 {
NYX 0:85b3fd62ea1a 575 deviceaddress = NOR_MEMORY_ADRESS3;
NYX 0:85b3fd62ea1a 576 }
NYX 0:85b3fd62ea1a 577 else /* FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 578 {
NYX 0:85b3fd62ea1a 579 deviceaddress = NOR_MEMORY_ADRESS4;
NYX 0:85b3fd62ea1a 580 }
NYX 0:85b3fd62ea1a 581
NYX 0:85b3fd62ea1a 582 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 583 hnor->State = HAL_NOR_STATE_BUSY;
NYX 0:85b3fd62ea1a 584
NYX 0:85b3fd62ea1a 585 /* Send read data command */
NYX 0:85b3fd62ea1a 586 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NYX 0:85b3fd62ea1a 587 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NYX 0:85b3fd62ea1a 588 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
NYX 0:85b3fd62ea1a 589
NYX 0:85b3fd62ea1a 590 /* Read buffer */
NYX 0:85b3fd62ea1a 591 while( uwBufferSize > 0U)
NYX 0:85b3fd62ea1a 592 {
NYX 0:85b3fd62ea1a 593 *pData++ = *(__IO uint16_t *)uwAddress;
NYX 0:85b3fd62ea1a 594 uwAddress += 2U;
NYX 0:85b3fd62ea1a 595 uwBufferSize--;
NYX 0:85b3fd62ea1a 596 }
NYX 0:85b3fd62ea1a 597
NYX 0:85b3fd62ea1a 598 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 599 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 600
NYX 0:85b3fd62ea1a 601 /* Process unlocked */
NYX 0:85b3fd62ea1a 602 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 603
NYX 0:85b3fd62ea1a 604 return HAL_OK;
NYX 0:85b3fd62ea1a 605 }
NYX 0:85b3fd62ea1a 606
NYX 0:85b3fd62ea1a 607 /**
NYX 0:85b3fd62ea1a 608 * @brief Writes a half-word buffer to the NOR memory. This function must be used
NYX 0:85b3fd62ea1a 609 only with S29GL128P NOR memory.
NYX 0:85b3fd62ea1a 610 * @param hnor: pointer to the NOR handle
NYX 0:85b3fd62ea1a 611 * @param uwAddress: NOR memory internal start write address
NYX 0:85b3fd62ea1a 612 * @param pData: pointer to source data buffer.
NYX 0:85b3fd62ea1a 613 * @param uwBufferSize: Size of the buffer to write
NYX 0:85b3fd62ea1a 614 * @retval HAL status
NYX 0:85b3fd62ea1a 615 */
NYX 0:85b3fd62ea1a 616 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
NYX 0:85b3fd62ea1a 617 {
NYX 0:85b3fd62ea1a 618 uint16_t * p_currentaddress = (uint16_t *)NULL;
NYX 0:85b3fd62ea1a 619 uint16_t * p_endaddress = (uint16_t *)NULL;
NYX 0:85b3fd62ea1a 620 uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
NYX 0:85b3fd62ea1a 621
NYX 0:85b3fd62ea1a 622 /* Process Locked */
NYX 0:85b3fd62ea1a 623 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 624
NYX 0:85b3fd62ea1a 625 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 626 if(hnor->State == HAL_NOR_STATE_BUSY)
NYX 0:85b3fd62ea1a 627 {
NYX 0:85b3fd62ea1a 628 return HAL_BUSY;
NYX 0:85b3fd62ea1a 629 }
NYX 0:85b3fd62ea1a 630
NYX 0:85b3fd62ea1a 631 /* Select the NOR device address */
NYX 0:85b3fd62ea1a 632 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 633 {
NYX 0:85b3fd62ea1a 634 deviceaddress = NOR_MEMORY_ADRESS1;
NYX 0:85b3fd62ea1a 635 }
NYX 0:85b3fd62ea1a 636 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
NYX 0:85b3fd62ea1a 637 {
NYX 0:85b3fd62ea1a 638 deviceaddress = NOR_MEMORY_ADRESS2;
NYX 0:85b3fd62ea1a 639 }
NYX 0:85b3fd62ea1a 640 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
NYX 0:85b3fd62ea1a 641 {
NYX 0:85b3fd62ea1a 642 deviceaddress = NOR_MEMORY_ADRESS3;
NYX 0:85b3fd62ea1a 643 }
NYX 0:85b3fd62ea1a 644 else /* FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 645 {
NYX 0:85b3fd62ea1a 646 deviceaddress = NOR_MEMORY_ADRESS4;
NYX 0:85b3fd62ea1a 647 }
NYX 0:85b3fd62ea1a 648
NYX 0:85b3fd62ea1a 649 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 650 hnor->State = HAL_NOR_STATE_BUSY;
NYX 0:85b3fd62ea1a 651
NYX 0:85b3fd62ea1a 652 /* Initialize variables */
NYX 0:85b3fd62ea1a 653 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
NYX 0:85b3fd62ea1a 654 p_endaddress = p_currentaddress + (uwBufferSize-1U);
NYX 0:85b3fd62ea1a 655 lastloadedaddress = (uint32_t)(uwAddress);
NYX 0:85b3fd62ea1a 656
NYX 0:85b3fd62ea1a 657 /* Issue unlock command sequence */
NYX 0:85b3fd62ea1a 658 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NYX 0:85b3fd62ea1a 659 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NYX 0:85b3fd62ea1a 660
NYX 0:85b3fd62ea1a 661 /* Write Buffer Load Command */
NYX 0:85b3fd62ea1a 662 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NYX 0:85b3fd62ea1a 663 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U));
NYX 0:85b3fd62ea1a 664
NYX 0:85b3fd62ea1a 665 /* Load Data into NOR Buffer */
NYX 0:85b3fd62ea1a 666 while(p_currentaddress <= p_endaddress)
NYX 0:85b3fd62ea1a 667 {
NYX 0:85b3fd62ea1a 668 /* Store last loaded address & data value (for polling) */
NYX 0:85b3fd62ea1a 669 lastloadedaddress = (uint32_t)p_currentaddress;
NYX 0:85b3fd62ea1a 670
NYX 0:85b3fd62ea1a 671 NOR_WRITE(p_currentaddress, *pData++);
NYX 0:85b3fd62ea1a 672
NYX 0:85b3fd62ea1a 673 p_currentaddress ++;
NYX 0:85b3fd62ea1a 674 }
NYX 0:85b3fd62ea1a 675
NYX 0:85b3fd62ea1a 676 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
NYX 0:85b3fd62ea1a 677
NYX 0:85b3fd62ea1a 678 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 679 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 680
NYX 0:85b3fd62ea1a 681 /* Process unlocked */
NYX 0:85b3fd62ea1a 682 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 683
NYX 0:85b3fd62ea1a 684 return HAL_OK;
NYX 0:85b3fd62ea1a 685
NYX 0:85b3fd62ea1a 686 }
NYX 0:85b3fd62ea1a 687
NYX 0:85b3fd62ea1a 688 /**
NYX 0:85b3fd62ea1a 689 * @brief Erase the specified block of the NOR memory
NYX 0:85b3fd62ea1a 690 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 691 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 692 * @param BlockAddress : Block to erase address
NYX 0:85b3fd62ea1a 693 * @param Address: Device address
NYX 0:85b3fd62ea1a 694 * @retval HAL status
NYX 0:85b3fd62ea1a 695 */
NYX 0:85b3fd62ea1a 696 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
NYX 0:85b3fd62ea1a 697 {
NYX 0:85b3fd62ea1a 698 uint32_t deviceaddress = 0U;
NYX 0:85b3fd62ea1a 699
NYX 0:85b3fd62ea1a 700 /* Process Locked */
NYX 0:85b3fd62ea1a 701 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 702
NYX 0:85b3fd62ea1a 703 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 704 if(hnor->State == HAL_NOR_STATE_BUSY)
NYX 0:85b3fd62ea1a 705 {
NYX 0:85b3fd62ea1a 706 return HAL_BUSY;
NYX 0:85b3fd62ea1a 707 }
NYX 0:85b3fd62ea1a 708
NYX 0:85b3fd62ea1a 709 /* Select the NOR device address */
NYX 0:85b3fd62ea1a 710 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 711 {
NYX 0:85b3fd62ea1a 712 deviceaddress = NOR_MEMORY_ADRESS1;
NYX 0:85b3fd62ea1a 713 }
NYX 0:85b3fd62ea1a 714 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
NYX 0:85b3fd62ea1a 715 {
NYX 0:85b3fd62ea1a 716 deviceaddress = NOR_MEMORY_ADRESS2;
NYX 0:85b3fd62ea1a 717 }
NYX 0:85b3fd62ea1a 718 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
NYX 0:85b3fd62ea1a 719 {
NYX 0:85b3fd62ea1a 720 deviceaddress = NOR_MEMORY_ADRESS3;
NYX 0:85b3fd62ea1a 721 }
NYX 0:85b3fd62ea1a 722 else /* FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 723 {
NYX 0:85b3fd62ea1a 724 deviceaddress = NOR_MEMORY_ADRESS4;
NYX 0:85b3fd62ea1a 725 }
NYX 0:85b3fd62ea1a 726
NYX 0:85b3fd62ea1a 727 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 728 hnor->State = HAL_NOR_STATE_BUSY;
NYX 0:85b3fd62ea1a 729
NYX 0:85b3fd62ea1a 730 /* Send block erase command sequence */
NYX 0:85b3fd62ea1a 731 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NYX 0:85b3fd62ea1a 732 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NYX 0:85b3fd62ea1a 733 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NYX 0:85b3fd62ea1a 734 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NYX 0:85b3fd62ea1a 735 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NYX 0:85b3fd62ea1a 736 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
NYX 0:85b3fd62ea1a 737
NYX 0:85b3fd62ea1a 738 /* Check the NOR memory status and update the controller state */
NYX 0:85b3fd62ea1a 739 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 740
NYX 0:85b3fd62ea1a 741 /* Process unlocked */
NYX 0:85b3fd62ea1a 742 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 743
NYX 0:85b3fd62ea1a 744 return HAL_OK;
NYX 0:85b3fd62ea1a 745
NYX 0:85b3fd62ea1a 746 }
NYX 0:85b3fd62ea1a 747
NYX 0:85b3fd62ea1a 748 /**
NYX 0:85b3fd62ea1a 749 * @brief Erase the entire NOR chip.
NYX 0:85b3fd62ea1a 750 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 751 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 752 * @param Address : Device address
NYX 0:85b3fd62ea1a 753 * @retval HAL status
NYX 0:85b3fd62ea1a 754 */
NYX 0:85b3fd62ea1a 755 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
NYX 0:85b3fd62ea1a 756 {
NYX 0:85b3fd62ea1a 757 uint32_t deviceaddress = 0U;
NYX 0:85b3fd62ea1a 758
NYX 0:85b3fd62ea1a 759 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 760 UNUSED(Address);
NYX 0:85b3fd62ea1a 761
NYX 0:85b3fd62ea1a 762 /* Process Locked */
NYX 0:85b3fd62ea1a 763 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 764
NYX 0:85b3fd62ea1a 765 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 766 if(hnor->State == HAL_NOR_STATE_BUSY)
NYX 0:85b3fd62ea1a 767 {
NYX 0:85b3fd62ea1a 768 return HAL_BUSY;
NYX 0:85b3fd62ea1a 769 }
NYX 0:85b3fd62ea1a 770
NYX 0:85b3fd62ea1a 771 /* Select the NOR device address */
NYX 0:85b3fd62ea1a 772 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 773 {
NYX 0:85b3fd62ea1a 774 deviceaddress = NOR_MEMORY_ADRESS1;
NYX 0:85b3fd62ea1a 775 }
NYX 0:85b3fd62ea1a 776 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
NYX 0:85b3fd62ea1a 777 {
NYX 0:85b3fd62ea1a 778 deviceaddress = NOR_MEMORY_ADRESS2;
NYX 0:85b3fd62ea1a 779 }
NYX 0:85b3fd62ea1a 780 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
NYX 0:85b3fd62ea1a 781 {
NYX 0:85b3fd62ea1a 782 deviceaddress = NOR_MEMORY_ADRESS3;
NYX 0:85b3fd62ea1a 783 }
NYX 0:85b3fd62ea1a 784 else /* FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 785 {
NYX 0:85b3fd62ea1a 786 deviceaddress = NOR_MEMORY_ADRESS4;
NYX 0:85b3fd62ea1a 787 }
NYX 0:85b3fd62ea1a 788
NYX 0:85b3fd62ea1a 789 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 790 hnor->State = HAL_NOR_STATE_BUSY;
NYX 0:85b3fd62ea1a 791
NYX 0:85b3fd62ea1a 792 /* Send NOR chip erase command sequence */
NYX 0:85b3fd62ea1a 793 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NYX 0:85b3fd62ea1a 794 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NYX 0:85b3fd62ea1a 795 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NYX 0:85b3fd62ea1a 796 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NYX 0:85b3fd62ea1a 797 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NYX 0:85b3fd62ea1a 798 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
NYX 0:85b3fd62ea1a 799
NYX 0:85b3fd62ea1a 800 /* Check the NOR memory status and update the controller state */
NYX 0:85b3fd62ea1a 801 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 802
NYX 0:85b3fd62ea1a 803 /* Process unlocked */
NYX 0:85b3fd62ea1a 804 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 805
NYX 0:85b3fd62ea1a 806 return HAL_OK;
NYX 0:85b3fd62ea1a 807 }
NYX 0:85b3fd62ea1a 808
NYX 0:85b3fd62ea1a 809 /**
NYX 0:85b3fd62ea1a 810 * @brief Read NOR flash CFI IDs
NYX 0:85b3fd62ea1a 811 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 812 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 813 * @param pNOR_CFI : pointer to NOR CFI IDs structure
NYX 0:85b3fd62ea1a 814 * @retval HAL status
NYX 0:85b3fd62ea1a 815 */
NYX 0:85b3fd62ea1a 816 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
NYX 0:85b3fd62ea1a 817 {
NYX 0:85b3fd62ea1a 818 uint32_t deviceaddress = 0U;
NYX 0:85b3fd62ea1a 819
NYX 0:85b3fd62ea1a 820 /* Process Locked */
NYX 0:85b3fd62ea1a 821 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 822
NYX 0:85b3fd62ea1a 823 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 824 if(hnor->State == HAL_NOR_STATE_BUSY)
NYX 0:85b3fd62ea1a 825 {
NYX 0:85b3fd62ea1a 826 return HAL_BUSY;
NYX 0:85b3fd62ea1a 827 }
NYX 0:85b3fd62ea1a 828
NYX 0:85b3fd62ea1a 829 /* Select the NOR device address */
NYX 0:85b3fd62ea1a 830 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 831 {
NYX 0:85b3fd62ea1a 832 deviceaddress = NOR_MEMORY_ADRESS1;
NYX 0:85b3fd62ea1a 833 }
NYX 0:85b3fd62ea1a 834 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
NYX 0:85b3fd62ea1a 835 {
NYX 0:85b3fd62ea1a 836 deviceaddress = NOR_MEMORY_ADRESS2;
NYX 0:85b3fd62ea1a 837 }
NYX 0:85b3fd62ea1a 838 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
NYX 0:85b3fd62ea1a 839 {
NYX 0:85b3fd62ea1a 840 deviceaddress = NOR_MEMORY_ADRESS3;
NYX 0:85b3fd62ea1a 841 }
NYX 0:85b3fd62ea1a 842 else /* FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 843 {
NYX 0:85b3fd62ea1a 844 deviceaddress = NOR_MEMORY_ADRESS4;
NYX 0:85b3fd62ea1a 845 }
NYX 0:85b3fd62ea1a 846
NYX 0:85b3fd62ea1a 847 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 848 hnor->State = HAL_NOR_STATE_BUSY;
NYX 0:85b3fd62ea1a 849
NYX 0:85b3fd62ea1a 850 /* Send read CFI query command */
NYX 0:85b3fd62ea1a 851 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
NYX 0:85b3fd62ea1a 852
NYX 0:85b3fd62ea1a 853 /* read the NOR CFI information */
NYX 0:85b3fd62ea1a 854 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
NYX 0:85b3fd62ea1a 855 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
NYX 0:85b3fd62ea1a 856 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
NYX 0:85b3fd62ea1a 857 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
NYX 0:85b3fd62ea1a 858
NYX 0:85b3fd62ea1a 859 /* Check the NOR controller state */
NYX 0:85b3fd62ea1a 860 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 861
NYX 0:85b3fd62ea1a 862 /* Process unlocked */
NYX 0:85b3fd62ea1a 863 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 864
NYX 0:85b3fd62ea1a 865 return HAL_OK;
NYX 0:85b3fd62ea1a 866 }
NYX 0:85b3fd62ea1a 867
NYX 0:85b3fd62ea1a 868 /**
NYX 0:85b3fd62ea1a 869 * @}
NYX 0:85b3fd62ea1a 870 */
NYX 0:85b3fd62ea1a 871
NYX 0:85b3fd62ea1a 872 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
NYX 0:85b3fd62ea1a 873 * @brief management functions
NYX 0:85b3fd62ea1a 874 *
NYX 0:85b3fd62ea1a 875 @verbatim
NYX 0:85b3fd62ea1a 876 ==============================================================================
NYX 0:85b3fd62ea1a 877 ##### NOR Control functions #####
NYX 0:85b3fd62ea1a 878 ==============================================================================
NYX 0:85b3fd62ea1a 879 [..]
NYX 0:85b3fd62ea1a 880 This subsection provides a set of functions allowing to control dynamically
NYX 0:85b3fd62ea1a 881 the NOR interface.
NYX 0:85b3fd62ea1a 882
NYX 0:85b3fd62ea1a 883 @endverbatim
NYX 0:85b3fd62ea1a 884 * @{
NYX 0:85b3fd62ea1a 885 */
NYX 0:85b3fd62ea1a 886
NYX 0:85b3fd62ea1a 887 /**
NYX 0:85b3fd62ea1a 888 * @brief Enables dynamically NOR write operation.
NYX 0:85b3fd62ea1a 889 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 890 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 891 * @retval HAL status
NYX 0:85b3fd62ea1a 892 */
NYX 0:85b3fd62ea1a 893 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
NYX 0:85b3fd62ea1a 894 {
NYX 0:85b3fd62ea1a 895 /* Process Locked */
NYX 0:85b3fd62ea1a 896 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 897
NYX 0:85b3fd62ea1a 898 /* Enable write operation */
NYX 0:85b3fd62ea1a 899 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
NYX 0:85b3fd62ea1a 900
NYX 0:85b3fd62ea1a 901 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 902 hnor->State = HAL_NOR_STATE_READY;
NYX 0:85b3fd62ea1a 903
NYX 0:85b3fd62ea1a 904 /* Process unlocked */
NYX 0:85b3fd62ea1a 905 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 906
NYX 0:85b3fd62ea1a 907 return HAL_OK;
NYX 0:85b3fd62ea1a 908 }
NYX 0:85b3fd62ea1a 909
NYX 0:85b3fd62ea1a 910 /**
NYX 0:85b3fd62ea1a 911 * @brief Disables dynamically NOR write operation.
NYX 0:85b3fd62ea1a 912 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 913 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 914 * @retval HAL status
NYX 0:85b3fd62ea1a 915 */
NYX 0:85b3fd62ea1a 916 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
NYX 0:85b3fd62ea1a 917 {
NYX 0:85b3fd62ea1a 918 /* Process Locked */
NYX 0:85b3fd62ea1a 919 __HAL_LOCK(hnor);
NYX 0:85b3fd62ea1a 920
NYX 0:85b3fd62ea1a 921 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 922 hnor->State = HAL_NOR_STATE_BUSY;
NYX 0:85b3fd62ea1a 923
NYX 0:85b3fd62ea1a 924 /* Disable write operation */
NYX 0:85b3fd62ea1a 925 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
NYX 0:85b3fd62ea1a 926
NYX 0:85b3fd62ea1a 927 /* Update the NOR controller state */
NYX 0:85b3fd62ea1a 928 hnor->State = HAL_NOR_STATE_PROTECTED;
NYX 0:85b3fd62ea1a 929
NYX 0:85b3fd62ea1a 930 /* Process unlocked */
NYX 0:85b3fd62ea1a 931 __HAL_UNLOCK(hnor);
NYX 0:85b3fd62ea1a 932
NYX 0:85b3fd62ea1a 933 return HAL_OK;
NYX 0:85b3fd62ea1a 934 }
NYX 0:85b3fd62ea1a 935
NYX 0:85b3fd62ea1a 936 /**
NYX 0:85b3fd62ea1a 937 * @}
NYX 0:85b3fd62ea1a 938 */
NYX 0:85b3fd62ea1a 939
NYX 0:85b3fd62ea1a 940 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
NYX 0:85b3fd62ea1a 941 * @brief Peripheral State functions
NYX 0:85b3fd62ea1a 942 *
NYX 0:85b3fd62ea1a 943 @verbatim
NYX 0:85b3fd62ea1a 944 ==============================================================================
NYX 0:85b3fd62ea1a 945 ##### NOR State functions #####
NYX 0:85b3fd62ea1a 946 ==============================================================================
NYX 0:85b3fd62ea1a 947 [..]
NYX 0:85b3fd62ea1a 948 This subsection permits to get in run-time the status of the NOR controller
NYX 0:85b3fd62ea1a 949 and the data flow.
NYX 0:85b3fd62ea1a 950
NYX 0:85b3fd62ea1a 951 @endverbatim
NYX 0:85b3fd62ea1a 952 * @{
NYX 0:85b3fd62ea1a 953 */
NYX 0:85b3fd62ea1a 954
NYX 0:85b3fd62ea1a 955 /**
NYX 0:85b3fd62ea1a 956 * @brief return the NOR controller state
NYX 0:85b3fd62ea1a 957 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 958 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 959 * @retval NOR controller state
NYX 0:85b3fd62ea1a 960 */
NYX 0:85b3fd62ea1a 961 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
NYX 0:85b3fd62ea1a 962 {
NYX 0:85b3fd62ea1a 963 return hnor->State;
NYX 0:85b3fd62ea1a 964 }
NYX 0:85b3fd62ea1a 965
NYX 0:85b3fd62ea1a 966 /**
NYX 0:85b3fd62ea1a 967 * @brief Returns the NOR operation status.
NYX 0:85b3fd62ea1a 968 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 969 * the configuration information for NOR module.
NYX 0:85b3fd62ea1a 970 * @param Address: Device address
NYX 0:85b3fd62ea1a 971 * @param Timeout: NOR programming Timeout
NYX 0:85b3fd62ea1a 972 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
NYX 0:85b3fd62ea1a 973 * or HAL_NOR_STATUS_TIMEOUT
NYX 0:85b3fd62ea1a 974 */
NYX 0:85b3fd62ea1a 975 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
NYX 0:85b3fd62ea1a 976 {
NYX 0:85b3fd62ea1a 977 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
NYX 0:85b3fd62ea1a 978 uint16_t tmpSR1 = 0, tmpSR2 = 0;
NYX 0:85b3fd62ea1a 979 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 980
NYX 0:85b3fd62ea1a 981 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
NYX 0:85b3fd62ea1a 982 HAL_NOR_MspWait(hnor, Timeout);
NYX 0:85b3fd62ea1a 983
NYX 0:85b3fd62ea1a 984 /* Get the NOR memory operation status -------------------------------------*/
NYX 0:85b3fd62ea1a 985
NYX 0:85b3fd62ea1a 986 /* Get tick */
NYX 0:85b3fd62ea1a 987 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 988 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
NYX 0:85b3fd62ea1a 989 {
NYX 0:85b3fd62ea1a 990 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 991 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 992 {
NYX 0:85b3fd62ea1a 993 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
NYX 0:85b3fd62ea1a 994 {
NYX 0:85b3fd62ea1a 995 status = HAL_NOR_STATUS_TIMEOUT;
NYX 0:85b3fd62ea1a 996 }
NYX 0:85b3fd62ea1a 997 }
NYX 0:85b3fd62ea1a 998
NYX 0:85b3fd62ea1a 999 /* Read NOR status register (DQ6 and DQ5) */
NYX 0:85b3fd62ea1a 1000 tmpSR1 = *(__IO uint16_t *)Address;
NYX 0:85b3fd62ea1a 1001 tmpSR2 = *(__IO uint16_t *)Address;
NYX 0:85b3fd62ea1a 1002
NYX 0:85b3fd62ea1a 1003 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
NYX 0:85b3fd62ea1a 1004 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
NYX 0:85b3fd62ea1a 1005 {
NYX 0:85b3fd62ea1a 1006 return HAL_NOR_STATUS_SUCCESS ;
NYX 0:85b3fd62ea1a 1007 }
NYX 0:85b3fd62ea1a 1008
NYX 0:85b3fd62ea1a 1009 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
NYX 0:85b3fd62ea1a 1010 {
NYX 0:85b3fd62ea1a 1011 status = HAL_NOR_STATUS_ONGOING;
NYX 0:85b3fd62ea1a 1012 }
NYX 0:85b3fd62ea1a 1013
NYX 0:85b3fd62ea1a 1014 tmpSR1 = *(__IO uint16_t *)Address;
NYX 0:85b3fd62ea1a 1015 tmpSR2 = *(__IO uint16_t *)Address;
NYX 0:85b3fd62ea1a 1016
NYX 0:85b3fd62ea1a 1017 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
NYX 0:85b3fd62ea1a 1018 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
NYX 0:85b3fd62ea1a 1019 {
NYX 0:85b3fd62ea1a 1020 return HAL_NOR_STATUS_SUCCESS;
NYX 0:85b3fd62ea1a 1021 }
NYX 0:85b3fd62ea1a 1022 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
NYX 0:85b3fd62ea1a 1023 {
NYX 0:85b3fd62ea1a 1024 return HAL_NOR_STATUS_ERROR;
NYX 0:85b3fd62ea1a 1025 }
NYX 0:85b3fd62ea1a 1026 }
NYX 0:85b3fd62ea1a 1027
NYX 0:85b3fd62ea1a 1028 /* Return the operation status */
NYX 0:85b3fd62ea1a 1029 return status;
NYX 0:85b3fd62ea1a 1030 }
NYX 0:85b3fd62ea1a 1031
NYX 0:85b3fd62ea1a 1032 /**
NYX 0:85b3fd62ea1a 1033 * @}
NYX 0:85b3fd62ea1a 1034 */
NYX 0:85b3fd62ea1a 1035
NYX 0:85b3fd62ea1a 1036 /**
NYX 0:85b3fd62ea1a 1037 * @}
NYX 0:85b3fd62ea1a 1038 */
NYX 0:85b3fd62ea1a 1039 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
NYX 0:85b3fd62ea1a 1040 STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
NYX 0:85b3fd62ea1a 1041 STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 1042 #endif /* HAL_NOR_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 1043 /**
NYX 0:85b3fd62ea1a 1044 * @}
NYX 0:85b3fd62ea1a 1045 */
NYX 0:85b3fd62ea1a 1046
NYX 0:85b3fd62ea1a 1047 /**
NYX 0:85b3fd62ea1a 1048 * @}
NYX 0:85b3fd62ea1a 1049 */
NYX 0:85b3fd62ea1a 1050
NYX 0:85b3fd62ea1a 1051 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/