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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_nand.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of NAND HAL module.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 39 #ifndef __STM32F4xx_HAL_NAND_H
NYX 0:85b3fd62ea1a 40 #define __STM32F4xx_HAL_NAND_H
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 43 extern "C" {
NYX 0:85b3fd62ea1a 44 #endif
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 48 #include "stm32f4xx_ll_fsmc.h"
NYX 0:85b3fd62ea1a 49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 50
NYX 0:85b3fd62ea1a 51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
NYX 0:85b3fd62ea1a 52 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 53 #include "stm32f4xx_ll_fmc.h"
NYX 0:85b3fd62ea1a 54 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
NYX 0:85b3fd62ea1a 55 STM32F479xx */
NYX 0:85b3fd62ea1a 56
NYX 0:85b3fd62ea1a 57 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 58 * @{
NYX 0:85b3fd62ea1a 59 */
NYX 0:85b3fd62ea1a 60
NYX 0:85b3fd62ea1a 61 /** @addtogroup NAND
NYX 0:85b3fd62ea1a 62 * @{
NYX 0:85b3fd62ea1a 63 */
NYX 0:85b3fd62ea1a 64
NYX 0:85b3fd62ea1a 65 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
NYX 0:85b3fd62ea1a 66 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
NYX 0:85b3fd62ea1a 67 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 68
NYX 0:85b3fd62ea1a 69 /* Exported typedef ----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 70 /* Exported types ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 71 /** @defgroup NAND_Exported_Types NAND Exported Types
NYX 0:85b3fd62ea1a 72 * @{
NYX 0:85b3fd62ea1a 73 */
NYX 0:85b3fd62ea1a 74
NYX 0:85b3fd62ea1a 75 /**
NYX 0:85b3fd62ea1a 76 * @brief HAL NAND State structures definition
NYX 0:85b3fd62ea1a 77 */
NYX 0:85b3fd62ea1a 78 typedef enum
NYX 0:85b3fd62ea1a 79 {
NYX 0:85b3fd62ea1a 80 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
NYX 0:85b3fd62ea1a 81 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
NYX 0:85b3fd62ea1a 82 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
NYX 0:85b3fd62ea1a 83 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
NYX 0:85b3fd62ea1a 84 }HAL_NAND_StateTypeDef;
NYX 0:85b3fd62ea1a 85
NYX 0:85b3fd62ea1a 86 /**
NYX 0:85b3fd62ea1a 87 * @brief NAND Memory electronic signature Structure definition
NYX 0:85b3fd62ea1a 88 */
NYX 0:85b3fd62ea1a 89 typedef struct
NYX 0:85b3fd62ea1a 90 {
NYX 0:85b3fd62ea1a 91 /*<! NAND memory electronic signature maker and device IDs */
NYX 0:85b3fd62ea1a 92
NYX 0:85b3fd62ea1a 93 uint8_t Maker_Id;
NYX 0:85b3fd62ea1a 94
NYX 0:85b3fd62ea1a 95 uint8_t Device_Id;
NYX 0:85b3fd62ea1a 96
NYX 0:85b3fd62ea1a 97 uint8_t Third_Id;
NYX 0:85b3fd62ea1a 98
NYX 0:85b3fd62ea1a 99 uint8_t Fourth_Id;
NYX 0:85b3fd62ea1a 100 }NAND_IDTypeDef;
NYX 0:85b3fd62ea1a 101
NYX 0:85b3fd62ea1a 102 /**
NYX 0:85b3fd62ea1a 103 * @brief NAND Memory address Structure definition
NYX 0:85b3fd62ea1a 104 */
NYX 0:85b3fd62ea1a 105 typedef struct
NYX 0:85b3fd62ea1a 106 {
NYX 0:85b3fd62ea1a 107 uint16_t Page; /*!< NAND memory Page address */
NYX 0:85b3fd62ea1a 108
NYX 0:85b3fd62ea1a 109 uint16_t Plane; /*!< NAND memory Plane address */
NYX 0:85b3fd62ea1a 110
NYX 0:85b3fd62ea1a 111 uint16_t Block; /*!< NAND memory Block address */
NYX 0:85b3fd62ea1a 112
NYX 0:85b3fd62ea1a 113 }NAND_AddressTypeDef;
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115 /**
NYX 0:85b3fd62ea1a 116 * @brief NAND Memory info Structure definition
NYX 0:85b3fd62ea1a 117 */
NYX 0:85b3fd62ea1a 118 typedef struct
NYX 0:85b3fd62ea1a 119 {
NYX 0:85b3fd62ea1a 120 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
NYX 0:85b3fd62ea1a 121 for 8 bits adressing or words for 16 bits addressing */
NYX 0:85b3fd62ea1a 122
NYX 0:85b3fd62ea1a 123 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
NYX 0:85b3fd62ea1a 124 for 8 bits adressing or words for 16 bits addressing */
NYX 0:85b3fd62ea1a 125
NYX 0:85b3fd62ea1a 126 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
NYX 0:85b3fd62ea1a 127
NYX 0:85b3fd62ea1a 128 uint32_t BlockNbr; /*!< NAND memory number of total blocks */
NYX 0:85b3fd62ea1a 129
NYX 0:85b3fd62ea1a 130 uint32_t PlaneNbr; /*!< NAND memory number of planes */
NYX 0:85b3fd62ea1a 131
NYX 0:85b3fd62ea1a 132 uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */
NYX 0:85b3fd62ea1a 133
NYX 0:85b3fd62ea1a 134 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
NYX 0:85b3fd62ea1a 135 parameter is mandatory for some NAND parts after the read
NYX 0:85b3fd62ea1a 136 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
NYX 0:85b3fd62ea1a 137 Example: Toshiba THTH58BYG3S0HBAI6.
NYX 0:85b3fd62ea1a 138 This parameter could be ENABLE or DISABLE
NYX 0:85b3fd62ea1a 139 Please check the Read Mode sequnece in the NAND device datasheet */
NYX 0:85b3fd62ea1a 140 }NAND_DeviceConfigTypeDef;
NYX 0:85b3fd62ea1a 141
NYX 0:85b3fd62ea1a 142 /**
NYX 0:85b3fd62ea1a 143 * @brief NAND handle Structure definition
NYX 0:85b3fd62ea1a 144 */
NYX 0:85b3fd62ea1a 145 typedef struct
NYX 0:85b3fd62ea1a 146 {
NYX 0:85b3fd62ea1a 147 FMC_NAND_TypeDef *Instance; /*!< Register base address */
NYX 0:85b3fd62ea1a 148
NYX 0:85b3fd62ea1a 149 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
NYX 0:85b3fd62ea1a 150
NYX 0:85b3fd62ea1a 151 HAL_LockTypeDef Lock; /*!< NAND locking object */
NYX 0:85b3fd62ea1a 152
NYX 0:85b3fd62ea1a 153 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
NYX 0:85b3fd62ea1a 154
NYX 0:85b3fd62ea1a 155 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
NYX 0:85b3fd62ea1a 156
NYX 0:85b3fd62ea1a 157 }NAND_HandleTypeDef;
NYX 0:85b3fd62ea1a 158 /**
NYX 0:85b3fd62ea1a 159 * @}
NYX 0:85b3fd62ea1a 160 */
NYX 0:85b3fd62ea1a 161
NYX 0:85b3fd62ea1a 162 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 163 /* Exported macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 164 /** @defgroup NAND_Exported_Macros NAND Exported Macros
NYX 0:85b3fd62ea1a 165 * @{
NYX 0:85b3fd62ea1a 166 */
NYX 0:85b3fd62ea1a 167
NYX 0:85b3fd62ea1a 168 /** @brief Reset NAND handle state
NYX 0:85b3fd62ea1a 169 * @param __HANDLE__: specifies the NAND handle.
NYX 0:85b3fd62ea1a 170 * @retval None
NYX 0:85b3fd62ea1a 171 */
NYX 0:85b3fd62ea1a 172 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
NYX 0:85b3fd62ea1a 173
NYX 0:85b3fd62ea1a 174 /**
NYX 0:85b3fd62ea1a 175 * @}
NYX 0:85b3fd62ea1a 176 */
NYX 0:85b3fd62ea1a 177
NYX 0:85b3fd62ea1a 178 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 179 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
NYX 0:85b3fd62ea1a 180 * @{
NYX 0:85b3fd62ea1a 181 */
NYX 0:85b3fd62ea1a 182
NYX 0:85b3fd62ea1a 183 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 184 * @{
NYX 0:85b3fd62ea1a 185 */
NYX 0:85b3fd62ea1a 186
NYX 0:85b3fd62ea1a 187 /* Initialization/de-initialization functions ********************************/
NYX 0:85b3fd62ea1a 188 /* Initialization/de-initialization functions ********************************/
NYX 0:85b3fd62ea1a 189 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
NYX 0:85b3fd62ea1a 190 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 191
NYX 0:85b3fd62ea1a 192 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
NYX 0:85b3fd62ea1a 193
NYX 0:85b3fd62ea1a 194 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
NYX 0:85b3fd62ea1a 195
NYX 0:85b3fd62ea1a 196 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 197 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 198 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 199 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 200
NYX 0:85b3fd62ea1a 201 /**
NYX 0:85b3fd62ea1a 202 * @}
NYX 0:85b3fd62ea1a 203 */
NYX 0:85b3fd62ea1a 204
NYX 0:85b3fd62ea1a 205 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
NYX 0:85b3fd62ea1a 206 * @{
NYX 0:85b3fd62ea1a 207 */
NYX 0:85b3fd62ea1a 208
NYX 0:85b3fd62ea1a 209 /* IO operation functions ****************************************************/
NYX 0:85b3fd62ea1a 210 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 211
NYX 0:85b3fd62ea1a 212 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
NYX 0:85b3fd62ea1a 213 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
NYX 0:85b3fd62ea1a 214 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
NYX 0:85b3fd62ea1a 215 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
NYX 0:85b3fd62ea1a 216
NYX 0:85b3fd62ea1a 217 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
NYX 0:85b3fd62ea1a 218 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
NYX 0:85b3fd62ea1a 219 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
NYX 0:85b3fd62ea1a 220 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
NYX 0:85b3fd62ea1a 221
NYX 0:85b3fd62ea1a 222 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
NYX 0:85b3fd62ea1a 223
NYX 0:85b3fd62ea1a 224 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 225 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
NYX 0:85b3fd62ea1a 226
NYX 0:85b3fd62ea1a 227 /**
NYX 0:85b3fd62ea1a 228 * @}
NYX 0:85b3fd62ea1a 229 */
NYX 0:85b3fd62ea1a 230
NYX 0:85b3fd62ea1a 231 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
NYX 0:85b3fd62ea1a 232 * @{
NYX 0:85b3fd62ea1a 233 */
NYX 0:85b3fd62ea1a 234
NYX 0:85b3fd62ea1a 235 /* NAND Control functions ****************************************************/
NYX 0:85b3fd62ea1a 236 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 237 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 238 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
NYX 0:85b3fd62ea1a 239
NYX 0:85b3fd62ea1a 240 /**
NYX 0:85b3fd62ea1a 241 * @}
NYX 0:85b3fd62ea1a 242 */
NYX 0:85b3fd62ea1a 243
NYX 0:85b3fd62ea1a 244 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
NYX 0:85b3fd62ea1a 245 * @{
NYX 0:85b3fd62ea1a 246 */
NYX 0:85b3fd62ea1a 247 /* NAND State functions *******************************************************/
NYX 0:85b3fd62ea1a 248 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
NYX 0:85b3fd62ea1a 249 /**
NYX 0:85b3fd62ea1a 250 * @}
NYX 0:85b3fd62ea1a 251 */
NYX 0:85b3fd62ea1a 252
NYX 0:85b3fd62ea1a 253 /**
NYX 0:85b3fd62ea1a 254 * @}
NYX 0:85b3fd62ea1a 255 */
NYX 0:85b3fd62ea1a 256
NYX 0:85b3fd62ea1a 257 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 258 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 259 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 260 /** @defgroup NAND_Private_Constants NAND Private Constants
NYX 0:85b3fd62ea1a 261 * @{
NYX 0:85b3fd62ea1a 262 */
NYX 0:85b3fd62ea1a 263 #define NAND_DEVICE1 0x70000000U
NYX 0:85b3fd62ea1a 264 #define NAND_DEVICE2 0x80000000U
NYX 0:85b3fd62ea1a 265 #define NAND_WRITE_TIMEOUT 0x01000000U
NYX 0:85b3fd62ea1a 266
NYX 0:85b3fd62ea1a 267 #define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
NYX 0:85b3fd62ea1a 268 #define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
NYX 0:85b3fd62ea1a 269
NYX 0:85b3fd62ea1a 270 #define NAND_CMD_AREA_A ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 271 #define NAND_CMD_AREA_B ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 272 #define NAND_CMD_AREA_C ((uint8_t)0x50)
NYX 0:85b3fd62ea1a 273 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
NYX 0:85b3fd62ea1a 274
NYX 0:85b3fd62ea1a 275 #define NAND_CMD_WRITE0 ((uint8_t)0x80)
NYX 0:85b3fd62ea1a 276 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
NYX 0:85b3fd62ea1a 277 #define NAND_CMD_ERASE0 ((uint8_t)0x60)
NYX 0:85b3fd62ea1a 278 #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
NYX 0:85b3fd62ea1a 279 #define NAND_CMD_READID ((uint8_t)0x90)
NYX 0:85b3fd62ea1a 280 #define NAND_CMD_STATUS ((uint8_t)0x70)
NYX 0:85b3fd62ea1a 281 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
NYX 0:85b3fd62ea1a 282 #define NAND_CMD_RESET ((uint8_t)0xFF)
NYX 0:85b3fd62ea1a 283
NYX 0:85b3fd62ea1a 284 /* NAND memory status */
NYX 0:85b3fd62ea1a 285 #define NAND_VALID_ADDRESS 0x00000100U
NYX 0:85b3fd62ea1a 286 #define NAND_INVALID_ADDRESS 0x00000200U
NYX 0:85b3fd62ea1a 287 #define NAND_TIMEOUT_ERROR 0x00000400U
NYX 0:85b3fd62ea1a 288 #define NAND_BUSY 0x00000000U
NYX 0:85b3fd62ea1a 289 #define NAND_ERROR 0x00000001U
NYX 0:85b3fd62ea1a 290 #define NAND_READY 0x00000040U
NYX 0:85b3fd62ea1a 291 /**
NYX 0:85b3fd62ea1a 292 * @}
NYX 0:85b3fd62ea1a 293 */
NYX 0:85b3fd62ea1a 294
NYX 0:85b3fd62ea1a 295 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 296 /** @defgroup NAND_Private_Macros NAND Private Macros
NYX 0:85b3fd62ea1a 297 * @{
NYX 0:85b3fd62ea1a 298 */
NYX 0:85b3fd62ea1a 299
NYX 0:85b3fd62ea1a 300 /**
NYX 0:85b3fd62ea1a 301 * @brief NAND memory address computation.
NYX 0:85b3fd62ea1a 302 * @param __ADDRESS__: NAND memory address.
NYX 0:85b3fd62ea1a 303 * @param __HANDLE__: NAND handle.
NYX 0:85b3fd62ea1a 304 * @retval NAND Raw address value
NYX 0:85b3fd62ea1a 305 */
NYX 0:85b3fd62ea1a 306 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
NYX 0:85b3fd62ea1a 307 (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
NYX 0:85b3fd62ea1a 308
NYX 0:85b3fd62ea1a 309 /**
NYX 0:85b3fd62ea1a 310 * @brief NAND memory Column address computation.
NYX 0:85b3fd62ea1a 311 * @param __HANDLE__: NAND handle.
NYX 0:85b3fd62ea1a 312 * @retval NAND Raw address value
NYX 0:85b3fd62ea1a 313 */
NYX 0:85b3fd62ea1a 314 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
NYX 0:85b3fd62ea1a 315
NYX 0:85b3fd62ea1a 316 /**
NYX 0:85b3fd62ea1a 317 * @brief NAND memory address cycling.
NYX 0:85b3fd62ea1a 318 * @param __ADDRESS__: NAND memory address.
NYX 0:85b3fd62ea1a 319 * @retval NAND address cycling value.
NYX 0:85b3fd62ea1a 320 */
NYX 0:85b3fd62ea1a 321 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
NYX 0:85b3fd62ea1a 322 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
NYX 0:85b3fd62ea1a 323 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
NYX 0:85b3fd62ea1a 324 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
NYX 0:85b3fd62ea1a 325
NYX 0:85b3fd62ea1a 326 /**
NYX 0:85b3fd62ea1a 327 * @brief NAND memory Columns cycling.
NYX 0:85b3fd62ea1a 328 * @param __ADDRESS__: NAND memory address.
NYX 0:85b3fd62ea1a 329 * @retval NAND Column address cycling value.
NYX 0:85b3fd62ea1a 330 */
NYX 0:85b3fd62ea1a 331 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
NYX 0:85b3fd62ea1a 332 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
NYX 0:85b3fd62ea1a 333
NYX 0:85b3fd62ea1a 334 /**
NYX 0:85b3fd62ea1a 335 * @}
NYX 0:85b3fd62ea1a 336 */
NYX 0:85b3fd62ea1a 337 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
NYX 0:85b3fd62ea1a 338 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
NYX 0:85b3fd62ea1a 339 STM32F446xx || STM32F469xx || STM32F479xx */
NYX 0:85b3fd62ea1a 340
NYX 0:85b3fd62ea1a 341 /**
NYX 0:85b3fd62ea1a 342 * @}
NYX 0:85b3fd62ea1a 343 */
NYX 0:85b3fd62ea1a 344 /**
NYX 0:85b3fd62ea1a 345 * @}
NYX 0:85b3fd62ea1a 346 */
NYX 0:85b3fd62ea1a 347
NYX 0:85b3fd62ea1a 348 /**
NYX 0:85b3fd62ea1a 349 * @}
NYX 0:85b3fd62ea1a 350 */
NYX 0:85b3fd62ea1a 351
NYX 0:85b3fd62ea1a 352 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 353 }
NYX 0:85b3fd62ea1a 354 #endif
NYX 0:85b3fd62ea1a 355
NYX 0:85b3fd62ea1a 356 #endif /* __STM32F4xx_HAL_NAND_H */
NYX 0:85b3fd62ea1a 357
NYX 0:85b3fd62ea1a 358 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/