Takaaki Numai / mbed-dev

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Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_i2s_ex.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief I2S HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 9 * functionalities of I2S extension peripheral:
NYX 0:85b3fd62ea1a 10 * + Extension features Functions
NYX 0:85b3fd62ea1a 11 *
NYX 0:85b3fd62ea1a 12 @verbatim
NYX 0:85b3fd62ea1a 13 ==============================================================================
NYX 0:85b3fd62ea1a 14 ##### I2S Extension features #####
NYX 0:85b3fd62ea1a 15 ==============================================================================
NYX 0:85b3fd62ea1a 16 [..]
NYX 0:85b3fd62ea1a 17 (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
NYX 0:85b3fd62ea1a 18 data simultaneously using two data lines. Each SPI peripheral has an extended block
NYX 0:85b3fd62ea1a 19 called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
NYX 0:85b3fd62ea1a 20 (#) The extension block is not a full SPI IP, it is used only as I2S slave to
NYX 0:85b3fd62ea1a 21 implement full duplex mode. The extension block uses the same clock sources
NYX 0:85b3fd62ea1a 22 as its master.
NYX 0:85b3fd62ea1a 23
NYX 0:85b3fd62ea1a 24 (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
NYX 0:85b3fd62ea1a 25
NYX 0:85b3fd62ea1a 26 [..]
NYX 0:85b3fd62ea1a 27 (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
NYX 0:85b3fd62ea1a 28 I2Sx can be I2S2 or I2S3.
NYX 0:85b3fd62ea1a 29
NYX 0:85b3fd62ea1a 30 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 31 ===============================================================================
NYX 0:85b3fd62ea1a 32 [..]
NYX 0:85b3fd62ea1a 33 Three operation modes are available within this driver :
NYX 0:85b3fd62ea1a 34
NYX 0:85b3fd62ea1a 35 *** Polling mode IO operation ***
NYX 0:85b3fd62ea1a 36 =================================
NYX 0:85b3fd62ea1a 37 [..]
NYX 0:85b3fd62ea1a 38 (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive()
NYX 0:85b3fd62ea1a 39
NYX 0:85b3fd62ea1a 40 *** Interrupt mode IO operation ***
NYX 0:85b3fd62ea1a 41 ===================================
NYX 0:85b3fd62ea1a 42 [..]
NYX 0:85b3fd62ea1a 43 (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT()
NYX 0:85b3fd62ea1a 44 (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 45 add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback
NYX 0:85b3fd62ea1a 46 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
NYX 0:85b3fd62ea1a 47 add his own code by customization of function pointer HAL_I2S_ErrorCallback
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 *** DMA mode IO operation ***
NYX 0:85b3fd62ea1a 50 ==============================
NYX 0:85b3fd62ea1a 51 [..]
NYX 0:85b3fd62ea1a 52 (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA()
NYX 0:85b3fd62ea1a 53 (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 54 add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback
NYX 0:85b3fd62ea1a 55 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
NYX 0:85b3fd62ea1a 56 add his own code by customization of function pointer HAL_I2S_ErrorCallback
NYX 0:85b3fd62ea1a 57 @endverbatim
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 Additional Figure: The Extended block uses the same clock sources as its master.
NYX 0:85b3fd62ea1a 60
NYX 0:85b3fd62ea1a 61 +-----------------------+
NYX 0:85b3fd62ea1a 62 I2Sx_SCK | |
NYX 0:85b3fd62ea1a 63 ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
NYX 0:85b3fd62ea1a 64 +--|-->| |
NYX 0:85b3fd62ea1a 65 | | +-----------------------+
NYX 0:85b3fd62ea1a 66 | |
NYX 0:85b3fd62ea1a 67 I2S_WS | |
NYX 0:85b3fd62ea1a 68 ------>| |
NYX 0:85b3fd62ea1a 69 | | +-----------------------+
NYX 0:85b3fd62ea1a 70 | +-->| |
NYX 0:85b3fd62ea1a 71 | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
NYX 0:85b3fd62ea1a 72 +----->| |
NYX 0:85b3fd62ea1a 73 +-----------------------+
NYX 0:85b3fd62ea1a 74 ******************************************************************************
NYX 0:85b3fd62ea1a 75 * @attention
NYX 0:85b3fd62ea1a 76 *
NYX 0:85b3fd62ea1a 77 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 78 *
NYX 0:85b3fd62ea1a 79 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 80 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 81 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 82 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 83 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 84 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 85 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 86 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 87 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 88 * without specific prior written permission.
NYX 0:85b3fd62ea1a 89 *
NYX 0:85b3fd62ea1a 90 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 91 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 92 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 93 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 94 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 95 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 96 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 97 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 98 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 99 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 100 *
NYX 0:85b3fd62ea1a 101 ******************************************************************************
NYX 0:85b3fd62ea1a 102 */
NYX 0:85b3fd62ea1a 103
NYX 0:85b3fd62ea1a 104 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 105 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 106
NYX 0:85b3fd62ea1a 107 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 108 * @{
NYX 0:85b3fd62ea1a 109 */
NYX 0:85b3fd62ea1a 110
NYX 0:85b3fd62ea1a 111 #ifdef HAL_I2S_MODULE_ENABLED
NYX 0:85b3fd62ea1a 112
NYX 0:85b3fd62ea1a 113 /** @defgroup I2SEx I2SEx
NYX 0:85b3fd62ea1a 114 * @brief I2S Extended HAL module driver
NYX 0:85b3fd62ea1a 115 * @{
NYX 0:85b3fd62ea1a 116 */
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
NYX 0:85b3fd62ea1a 119
NYX 0:85b3fd62ea1a 120 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 121 /** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
NYX 0:85b3fd62ea1a 122 * @{
NYX 0:85b3fd62ea1a 123 */
NYX 0:85b3fd62ea1a 124 typedef enum
NYX 0:85b3fd62ea1a 125 {
NYX 0:85b3fd62ea1a 126 I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */
NYX 0:85b3fd62ea1a 127 I2S_USE_I2SEXT = 0x01U, /*!< I2Sx_ext should be used */
NYX 0:85b3fd62ea1a 128 }I2S_UseTypeDef;
NYX 0:85b3fd62ea1a 129 /**
NYX 0:85b3fd62ea1a 130 * @}
NYX 0:85b3fd62ea1a 131 */
NYX 0:85b3fd62ea1a 132 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 133 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 134 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 135 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 136 /** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
NYX 0:85b3fd62ea1a 137 * @{
NYX 0:85b3fd62ea1a 138 */
NYX 0:85b3fd62ea1a 139 static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 140 static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 141 static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
NYX 0:85b3fd62ea1a 142 static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
NYX 0:85b3fd62ea1a 143 static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
NYX 0:85b3fd62ea1a 144 uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
NYX 0:85b3fd62ea1a 145 /**
NYX 0:85b3fd62ea1a 146 * @}
NYX 0:85b3fd62ea1a 147 */
NYX 0:85b3fd62ea1a 148
NYX 0:85b3fd62ea1a 149 /**
NYX 0:85b3fd62ea1a 150 * @}
NYX 0:85b3fd62ea1a 151 */
NYX 0:85b3fd62ea1a 152
NYX 0:85b3fd62ea1a 153 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 154 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 155
NYX 0:85b3fd62ea1a 156 /** @addtogroup I2SEx I2SEx
NYX 0:85b3fd62ea1a 157 * @{
NYX 0:85b3fd62ea1a 158 */
NYX 0:85b3fd62ea1a 159
NYX 0:85b3fd62ea1a 160 /** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
NYX 0:85b3fd62ea1a 161 * @{
NYX 0:85b3fd62ea1a 162 */
NYX 0:85b3fd62ea1a 163
NYX 0:85b3fd62ea1a 164 /** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
NYX 0:85b3fd62ea1a 165 * @brief I2SEx IO operation functions
NYX 0:85b3fd62ea1a 166 *
NYX 0:85b3fd62ea1a 167 @verbatim
NYX 0:85b3fd62ea1a 168 ===============================================================================
NYX 0:85b3fd62ea1a 169 ##### IO operation functions#####
NYX 0:85b3fd62ea1a 170 ===============================================================================
NYX 0:85b3fd62ea1a 171 [..]
NYX 0:85b3fd62ea1a 172 This subsection provides a set of functions allowing to manage the I2S data
NYX 0:85b3fd62ea1a 173 transfers.
NYX 0:85b3fd62ea1a 174
NYX 0:85b3fd62ea1a 175 (#) There are two modes of transfer:
NYX 0:85b3fd62ea1a 176 (++) Blocking mode : The communication is performed in the polling mode.
NYX 0:85b3fd62ea1a 177 The status of all data processing is returned by the same function
NYX 0:85b3fd62ea1a 178 after finishing transfer.
NYX 0:85b3fd62ea1a 179 (++) No-Blocking mode : The communication is performed using Interrupts
NYX 0:85b3fd62ea1a 180 or DMA. These functions return the status of the transfer startup.
NYX 0:85b3fd62ea1a 181 The end of the data processing will be indicated through the
NYX 0:85b3fd62ea1a 182 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
NYX 0:85b3fd62ea1a 183 using DMA mode.
NYX 0:85b3fd62ea1a 184
NYX 0:85b3fd62ea1a 185 (#) Blocking mode functions are :
NYX 0:85b3fd62ea1a 186 (++) HAL_I2SEx_TransmitReceive()
NYX 0:85b3fd62ea1a 187
NYX 0:85b3fd62ea1a 188 (#) No-Blocking mode functions with Interrupt are :
NYX 0:85b3fd62ea1a 189 (++) HAL_I2SEx_TransmitReceive_IT()
NYX 0:85b3fd62ea1a 190 (++) HAL_I2SEx_FullDuplex_IRQHandler()
NYX 0:85b3fd62ea1a 191
NYX 0:85b3fd62ea1a 192 (#) No-Blocking mode functions with DMA are :
NYX 0:85b3fd62ea1a 193 (++) HAL_I2SEx_TransmitReceive_DMA()
NYX 0:85b3fd62ea1a 194
NYX 0:85b3fd62ea1a 195 (#) A set of Transfer Complete Callback are provided in non Blocking mode:
NYX 0:85b3fd62ea1a 196 (++) HAL_I2SEx_TxRxCpltCallback()
NYX 0:85b3fd62ea1a 197 @endverbatim
NYX 0:85b3fd62ea1a 198 * @{
NYX 0:85b3fd62ea1a 199 */
NYX 0:85b3fd62ea1a 200 /**
NYX 0:85b3fd62ea1a 201 * @brief Full-Duplex Transmit/Receive data in blocking mode.
NYX 0:85b3fd62ea1a 202 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 203 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 204 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
NYX 0:85b3fd62ea1a 205 * @param pRxData: a 16-bit pointer to the Receive data buffer.
NYX 0:85b3fd62ea1a 206 * @param Size: number of data sample to be sent:
NYX 0:85b3fd62ea1a 207 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
NYX 0:85b3fd62ea1a 208 * configuration phase, the Size parameter means the number of 16-bit data length
NYX 0:85b3fd62ea1a 209 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
NYX 0:85b3fd62ea1a 210 * the Size parameter means the number of 16-bit data length.
NYX 0:85b3fd62ea1a 211 * @param Timeout: Timeout duration
NYX 0:85b3fd62ea1a 212 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
NYX 0:85b3fd62ea1a 213 * between Master and Slave(example: audio streaming).
NYX 0:85b3fd62ea1a 214 * @retval HAL status
NYX 0:85b3fd62ea1a 215 */
NYX 0:85b3fd62ea1a 216 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
NYX 0:85b3fd62ea1a 217 uint16_t Size, uint32_t Timeout)
NYX 0:85b3fd62ea1a 218 {
NYX 0:85b3fd62ea1a 219 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 220
NYX 0:85b3fd62ea1a 221 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
NYX 0:85b3fd62ea1a 222 {
NYX 0:85b3fd62ea1a 223 return HAL_ERROR;
NYX 0:85b3fd62ea1a 224 }
NYX 0:85b3fd62ea1a 225
NYX 0:85b3fd62ea1a 226 /* Check the I2S State */
NYX 0:85b3fd62ea1a 227 if(hi2s->State == HAL_I2S_STATE_READY)
NYX 0:85b3fd62ea1a 228 {
NYX 0:85b3fd62ea1a 229 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
NYX 0:85b3fd62ea1a 230 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
NYX 0:85b3fd62ea1a 231 is selected during the I2S configuration phase, the Size parameter means the number
NYX 0:85b3fd62ea1a 232 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
NYX 0:85b3fd62ea1a 233 frame is selected the Size parameter means the number of 16-bit data length. */
NYX 0:85b3fd62ea1a 234 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
NYX 0:85b3fd62ea1a 235 {
NYX 0:85b3fd62ea1a 236 hi2s->TxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 237 hi2s->TxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 238 hi2s->RxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 239 hi2s->RxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 240 }
NYX 0:85b3fd62ea1a 241 else
NYX 0:85b3fd62ea1a 242 {
NYX 0:85b3fd62ea1a 243 hi2s->TxXferSize = Size;
NYX 0:85b3fd62ea1a 244 hi2s->TxXferCount = Size;
NYX 0:85b3fd62ea1a 245 hi2s->RxXferSize = Size;
NYX 0:85b3fd62ea1a 246 hi2s->RxXferCount = Size;
NYX 0:85b3fd62ea1a 247 }
NYX 0:85b3fd62ea1a 248
NYX 0:85b3fd62ea1a 249 /* Process Locked */
NYX 0:85b3fd62ea1a 250 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 251
NYX 0:85b3fd62ea1a 252 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 253
NYX 0:85b3fd62ea1a 254 /* Set the I2S State busy TX/RX */
NYX 0:85b3fd62ea1a 255 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
NYX 0:85b3fd62ea1a 256
NYX 0:85b3fd62ea1a 257 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
NYX 0:85b3fd62ea1a 258 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
NYX 0:85b3fd62ea1a 259 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
NYX 0:85b3fd62ea1a 260 {
NYX 0:85b3fd62ea1a 261 /* Prepare the First Data before enabling the I2S */
NYX 0:85b3fd62ea1a 262 hi2s->Instance->DR = (*pTxData++);
NYX 0:85b3fd62ea1a 263 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 264
NYX 0:85b3fd62ea1a 265 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
NYX 0:85b3fd62ea1a 266 __HAL_I2SEXT_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 267
NYX 0:85b3fd62ea1a 268 /* Enable I2Sx peripheral */
NYX 0:85b3fd62ea1a 269 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 270
NYX 0:85b3fd62ea1a 271 /* Check if Master Receiver mode is selected */
NYX 0:85b3fd62ea1a 272 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
NYX 0:85b3fd62ea1a 273 {
NYX 0:85b3fd62ea1a 274 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
NYX 0:85b3fd62ea1a 275 access to the SPI_SR register. */
NYX 0:85b3fd62ea1a 276 __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 277 }
NYX 0:85b3fd62ea1a 278
NYX 0:85b3fd62ea1a 279 while((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
NYX 0:85b3fd62ea1a 280 {
NYX 0:85b3fd62ea1a 281 if(hi2s->TxXferCount > 0U)
NYX 0:85b3fd62ea1a 282 {
NYX 0:85b3fd62ea1a 283 /* Wait until TXE flag is set */
NYX 0:85b3fd62ea1a 284 if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
NYX 0:85b3fd62ea1a 285 {
NYX 0:85b3fd62ea1a 286 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 287 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
NYX 0:85b3fd62ea1a 288 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 289 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 290 }
NYX 0:85b3fd62ea1a 291 /* Write Data on DR register */
NYX 0:85b3fd62ea1a 292 hi2s->Instance->DR = (*pTxData++);
NYX 0:85b3fd62ea1a 293 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 294
NYX 0:85b3fd62ea1a 295 /* Check if an underrun occurs */
NYX 0:85b3fd62ea1a 296 if((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_TX))
NYX 0:85b3fd62ea1a 297 {
NYX 0:85b3fd62ea1a 298 /* Clear Underrun flag */
NYX 0:85b3fd62ea1a 299 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
NYX 0:85b3fd62ea1a 300
NYX 0:85b3fd62ea1a 301 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 302 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 303
NYX 0:85b3fd62ea1a 304 /* Process Unlocked */
NYX 0:85b3fd62ea1a 305 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 306
NYX 0:85b3fd62ea1a 307 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 308 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
NYX 0:85b3fd62ea1a 309 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 310
NYX 0:85b3fd62ea1a 311 return HAL_ERROR;
NYX 0:85b3fd62ea1a 312 }
NYX 0:85b3fd62ea1a 313 }
NYX 0:85b3fd62ea1a 314 if(hi2s->RxXferCount > 0U)
NYX 0:85b3fd62ea1a 315 {
NYX 0:85b3fd62ea1a 316 /* Wait until RXNE flag is set */
NYX 0:85b3fd62ea1a 317 if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
NYX 0:85b3fd62ea1a 318 {
NYX 0:85b3fd62ea1a 319 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 320 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
NYX 0:85b3fd62ea1a 321 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 322 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 323 }
NYX 0:85b3fd62ea1a 324 /* Read Data from DR register */
NYX 0:85b3fd62ea1a 325 (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
NYX 0:85b3fd62ea1a 326 hi2s->RxXferCount--;
NYX 0:85b3fd62ea1a 327
NYX 0:85b3fd62ea1a 328 /* Check if an overrun occurs */
NYX 0:85b3fd62ea1a 329 if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
NYX 0:85b3fd62ea1a 330 {
NYX 0:85b3fd62ea1a 331 /* Clear Overrun flag */
NYX 0:85b3fd62ea1a 332 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 333
NYX 0:85b3fd62ea1a 334 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 335 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 336
NYX 0:85b3fd62ea1a 337 /* Process Unlocked */
NYX 0:85b3fd62ea1a 338 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 339
NYX 0:85b3fd62ea1a 340 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 341 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
NYX 0:85b3fd62ea1a 342 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 343
NYX 0:85b3fd62ea1a 344 return HAL_ERROR;
NYX 0:85b3fd62ea1a 345 }
NYX 0:85b3fd62ea1a 346 }
NYX 0:85b3fd62ea1a 347 }
NYX 0:85b3fd62ea1a 348 }
NYX 0:85b3fd62ea1a 349 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
NYX 0:85b3fd62ea1a 350 else
NYX 0:85b3fd62ea1a 351 {
NYX 0:85b3fd62ea1a 352 /* Prepare the First Data before enabling the I2S */
NYX 0:85b3fd62ea1a 353 I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
NYX 0:85b3fd62ea1a 354 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 355
NYX 0:85b3fd62ea1a 356 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
NYX 0:85b3fd62ea1a 357 __HAL_I2SEXT_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 358
NYX 0:85b3fd62ea1a 359 /* Enable I2S peripheral before the I2Sext*/
NYX 0:85b3fd62ea1a 360 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 361
NYX 0:85b3fd62ea1a 362 /* Check if Master Receiver mode is selected */
NYX 0:85b3fd62ea1a 363 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
NYX 0:85b3fd62ea1a 364 {
NYX 0:85b3fd62ea1a 365 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
NYX 0:85b3fd62ea1a 366 access to the SPI_SR register. */
NYX 0:85b3fd62ea1a 367 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 368 }
NYX 0:85b3fd62ea1a 369
NYX 0:85b3fd62ea1a 370 while((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
NYX 0:85b3fd62ea1a 371 {
NYX 0:85b3fd62ea1a 372 if(hi2s->TxXferCount > 0U)
NYX 0:85b3fd62ea1a 373 {
NYX 0:85b3fd62ea1a 374 /* Wait until TXE flag is set */
NYX 0:85b3fd62ea1a 375 if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
NYX 0:85b3fd62ea1a 376 {
NYX 0:85b3fd62ea1a 377 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 378 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
NYX 0:85b3fd62ea1a 379 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 380 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 381 }
NYX 0:85b3fd62ea1a 382 /* Write Data on DR register */
NYX 0:85b3fd62ea1a 383 I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
NYX 0:85b3fd62ea1a 384 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 385
NYX 0:85b3fd62ea1a 386 /* Check if an underrun occurs */
NYX 0:85b3fd62ea1a 387 if((__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_RX))
NYX 0:85b3fd62ea1a 388 {
NYX 0:85b3fd62ea1a 389 /* Clear Underrun flag */
NYX 0:85b3fd62ea1a 390 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
NYX 0:85b3fd62ea1a 391
NYX 0:85b3fd62ea1a 392 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 393 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 394
NYX 0:85b3fd62ea1a 395 /* Process Unlocked */
NYX 0:85b3fd62ea1a 396 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 397
NYX 0:85b3fd62ea1a 398 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 399 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
NYX 0:85b3fd62ea1a 400 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 401
NYX 0:85b3fd62ea1a 402 return HAL_ERROR;
NYX 0:85b3fd62ea1a 403 }
NYX 0:85b3fd62ea1a 404 }
NYX 0:85b3fd62ea1a 405 if(hi2s->RxXferCount > 0U)
NYX 0:85b3fd62ea1a 406 {
NYX 0:85b3fd62ea1a 407 /* Wait until RXNE flag is set */
NYX 0:85b3fd62ea1a 408 if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
NYX 0:85b3fd62ea1a 409 {
NYX 0:85b3fd62ea1a 410 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 411 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
NYX 0:85b3fd62ea1a 412 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 413 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 414 }
NYX 0:85b3fd62ea1a 415 /* Read Data from DR register */
NYX 0:85b3fd62ea1a 416 (*pRxData++) = hi2s->Instance->DR;
NYX 0:85b3fd62ea1a 417 hi2s->RxXferCount--;
NYX 0:85b3fd62ea1a 418
NYX 0:85b3fd62ea1a 419 /* Check if an overrun occurs */
NYX 0:85b3fd62ea1a 420 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
NYX 0:85b3fd62ea1a 421 {
NYX 0:85b3fd62ea1a 422 /* Clear Overrun flag */
NYX 0:85b3fd62ea1a 423 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 424
NYX 0:85b3fd62ea1a 425 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 426 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428 /* Process Unlocked */
NYX 0:85b3fd62ea1a 429 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 430
NYX 0:85b3fd62ea1a 431 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 432 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
NYX 0:85b3fd62ea1a 433 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 434
NYX 0:85b3fd62ea1a 435 return HAL_ERROR;
NYX 0:85b3fd62ea1a 436 }
NYX 0:85b3fd62ea1a 437 }
NYX 0:85b3fd62ea1a 438 }
NYX 0:85b3fd62ea1a 439 }
NYX 0:85b3fd62ea1a 440
NYX 0:85b3fd62ea1a 441 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 442 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 443
NYX 0:85b3fd62ea1a 444 /* Process Unlocked */
NYX 0:85b3fd62ea1a 445 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 446
NYX 0:85b3fd62ea1a 447 return HAL_OK;
NYX 0:85b3fd62ea1a 448 }
NYX 0:85b3fd62ea1a 449 else
NYX 0:85b3fd62ea1a 450 {
NYX 0:85b3fd62ea1a 451 return HAL_BUSY;
NYX 0:85b3fd62ea1a 452 }
NYX 0:85b3fd62ea1a 453 }
NYX 0:85b3fd62ea1a 454
NYX 0:85b3fd62ea1a 455 /**
NYX 0:85b3fd62ea1a 456 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
NYX 0:85b3fd62ea1a 457 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 458 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 459 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
NYX 0:85b3fd62ea1a 460 * @param pRxData: a 16-bit pointer to the Receive data buffer.
NYX 0:85b3fd62ea1a 461 * @param Size: number of data sample to be sent:
NYX 0:85b3fd62ea1a 462 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
NYX 0:85b3fd62ea1a 463 * configuration phase, the Size parameter means the number of 16-bit data length
NYX 0:85b3fd62ea1a 464 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
NYX 0:85b3fd62ea1a 465 * the Size parameter means the number of 16-bit data length.
NYX 0:85b3fd62ea1a 466 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
NYX 0:85b3fd62ea1a 467 * between Master and Slave(example: audio streaming).
NYX 0:85b3fd62ea1a 468 * @retval HAL status
NYX 0:85b3fd62ea1a 469 */
NYX 0:85b3fd62ea1a 470 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
NYX 0:85b3fd62ea1a 471 uint16_t Size)
NYX 0:85b3fd62ea1a 472 {
NYX 0:85b3fd62ea1a 473 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 474
NYX 0:85b3fd62ea1a 475 if(hi2s->State == HAL_I2S_STATE_READY)
NYX 0:85b3fd62ea1a 476 {
NYX 0:85b3fd62ea1a 477 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
NYX 0:85b3fd62ea1a 478 {
NYX 0:85b3fd62ea1a 479 return HAL_ERROR;
NYX 0:85b3fd62ea1a 480 }
NYX 0:85b3fd62ea1a 481
NYX 0:85b3fd62ea1a 482 hi2s->pTxBuffPtr = pTxData;
NYX 0:85b3fd62ea1a 483 hi2s->pRxBuffPtr = pRxData;
NYX 0:85b3fd62ea1a 484
NYX 0:85b3fd62ea1a 485 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
NYX 0:85b3fd62ea1a 486 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
NYX 0:85b3fd62ea1a 487 is selected during the I2S configuration phase, the Size parameter means the number
NYX 0:85b3fd62ea1a 488 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
NYX 0:85b3fd62ea1a 489 frame is selected the Size parameter means the number of 16-bit data length. */
NYX 0:85b3fd62ea1a 490 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
NYX 0:85b3fd62ea1a 491 {
NYX 0:85b3fd62ea1a 492 hi2s->TxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 493 hi2s->TxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 494 hi2s->RxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 495 hi2s->RxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 496 }
NYX 0:85b3fd62ea1a 497 else
NYX 0:85b3fd62ea1a 498 {
NYX 0:85b3fd62ea1a 499 hi2s->TxXferSize = Size;
NYX 0:85b3fd62ea1a 500 hi2s->TxXferCount = Size;
NYX 0:85b3fd62ea1a 501 hi2s->RxXferSize = Size;
NYX 0:85b3fd62ea1a 502 hi2s->RxXferCount = Size;
NYX 0:85b3fd62ea1a 503 }
NYX 0:85b3fd62ea1a 504
NYX 0:85b3fd62ea1a 505 /* Process Locked */
NYX 0:85b3fd62ea1a 506 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 507
NYX 0:85b3fd62ea1a 508 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 509 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
NYX 0:85b3fd62ea1a 510
NYX 0:85b3fd62ea1a 511 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
NYX 0:85b3fd62ea1a 512 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
NYX 0:85b3fd62ea1a 513 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
NYX 0:85b3fd62ea1a 514 {
NYX 0:85b3fd62ea1a 515 /* Enable I2Sext RXNE and ERR interrupts */
NYX 0:85b3fd62ea1a 516 __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 517
NYX 0:85b3fd62ea1a 518 /* Enable I2Sx TXE and ERR interrupts */
NYX 0:85b3fd62ea1a 519 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 520
NYX 0:85b3fd62ea1a 521 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 522 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 523 {
NYX 0:85b3fd62ea1a 524 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
NYX 0:85b3fd62ea1a 525 {
NYX 0:85b3fd62ea1a 526 /* Prepare the First Data before enabling the I2S */
NYX 0:85b3fd62ea1a 527 if(hi2s->TxXferCount != 0U)
NYX 0:85b3fd62ea1a 528 {
NYX 0:85b3fd62ea1a 529 /* Transmit First data */
NYX 0:85b3fd62ea1a 530 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
NYX 0:85b3fd62ea1a 531 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 532
NYX 0:85b3fd62ea1a 533 if(hi2s->TxXferCount == 0U)
NYX 0:85b3fd62ea1a 534 {
NYX 0:85b3fd62ea1a 535 /* Disable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 536 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 537
NYX 0:85b3fd62ea1a 538 if(hi2s->RxXferCount == 0U)
NYX 0:85b3fd62ea1a 539 {
NYX 0:85b3fd62ea1a 540 /* Disable I2Sext RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 541 __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
NYX 0:85b3fd62ea1a 542
NYX 0:85b3fd62ea1a 543 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 544 HAL_I2SEx_TxRxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 545 }
NYX 0:85b3fd62ea1a 546 }
NYX 0:85b3fd62ea1a 547 }
NYX 0:85b3fd62ea1a 548 }
NYX 0:85b3fd62ea1a 549 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
NYX 0:85b3fd62ea1a 550 __HAL_I2SEXT_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 551
NYX 0:85b3fd62ea1a 552 /* Enable I2Sx peripheral */
NYX 0:85b3fd62ea1a 553 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 554 }
NYX 0:85b3fd62ea1a 555 }
NYX 0:85b3fd62ea1a 556 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
NYX 0:85b3fd62ea1a 557 else
NYX 0:85b3fd62ea1a 558 {
NYX 0:85b3fd62ea1a 559 /* Enable I2Sext TXE and ERR interrupts */
NYX 0:85b3fd62ea1a 560 __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 561
NYX 0:85b3fd62ea1a 562 /* Enable I2Sext RXNE and ERR interrupts */
NYX 0:85b3fd62ea1a 563 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 564
NYX 0:85b3fd62ea1a 565 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 566 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 567 {
NYX 0:85b3fd62ea1a 568 /* Check if the I2S_MODE_MASTER_RX is selected */
NYX 0:85b3fd62ea1a 569 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
NYX 0:85b3fd62ea1a 570 {
NYX 0:85b3fd62ea1a 571 /* Prepare the First Data before enabling the I2S */
NYX 0:85b3fd62ea1a 572 if(hi2s->TxXferCount != 0U)
NYX 0:85b3fd62ea1a 573 {
NYX 0:85b3fd62ea1a 574 /* Transmit First data */
NYX 0:85b3fd62ea1a 575 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
NYX 0:85b3fd62ea1a 576 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 577
NYX 0:85b3fd62ea1a 578 if(hi2s->TxXferCount == 0U)
NYX 0:85b3fd62ea1a 579 {
NYX 0:85b3fd62ea1a 580 /* Disable I2Sext TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 581 __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 582 if(hi2s->RxXferCount == 0U)
NYX 0:85b3fd62ea1a 583 {
NYX 0:85b3fd62ea1a 584 /* Disable RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 585 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
NYX 0:85b3fd62ea1a 586
NYX 0:85b3fd62ea1a 587 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 588 HAL_I2SEx_TxRxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 589 }
NYX 0:85b3fd62ea1a 590 }
NYX 0:85b3fd62ea1a 591 }
NYX 0:85b3fd62ea1a 592 }
NYX 0:85b3fd62ea1a 593 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
NYX 0:85b3fd62ea1a 594 __HAL_I2SEXT_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 595
NYX 0:85b3fd62ea1a 596 /* Enable I2S peripheral */
NYX 0:85b3fd62ea1a 597 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 598 }
NYX 0:85b3fd62ea1a 599 }
NYX 0:85b3fd62ea1a 600 /* Process Unlocked */
NYX 0:85b3fd62ea1a 601 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 602
NYX 0:85b3fd62ea1a 603 return HAL_OK;
NYX 0:85b3fd62ea1a 604 }
NYX 0:85b3fd62ea1a 605 else
NYX 0:85b3fd62ea1a 606 {
NYX 0:85b3fd62ea1a 607 return HAL_BUSY;
NYX 0:85b3fd62ea1a 608 }
NYX 0:85b3fd62ea1a 609 }
NYX 0:85b3fd62ea1a 610
NYX 0:85b3fd62ea1a 611 /**
NYX 0:85b3fd62ea1a 612 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
NYX 0:85b3fd62ea1a 613 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 614 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 615 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
NYX 0:85b3fd62ea1a 616 * @param pRxData: a 16-bit pointer to the Receive data buffer.
NYX 0:85b3fd62ea1a 617 * @param Size: number of data sample to be sent:
NYX 0:85b3fd62ea1a 618 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
NYX 0:85b3fd62ea1a 619 * configuration phase, the Size parameter means the number of 16-bit data length
NYX 0:85b3fd62ea1a 620 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
NYX 0:85b3fd62ea1a 621 * the Size parameter means the number of 16-bit data length.
NYX 0:85b3fd62ea1a 622 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
NYX 0:85b3fd62ea1a 623 * between Master and Slave(example: audio streaming).
NYX 0:85b3fd62ea1a 624 * @retval HAL status
NYX 0:85b3fd62ea1a 625 */
NYX 0:85b3fd62ea1a 626 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
NYX 0:85b3fd62ea1a 627 uint16_t Size)
NYX 0:85b3fd62ea1a 628 {
NYX 0:85b3fd62ea1a 629 uint32_t *tmp = NULL;
NYX 0:85b3fd62ea1a 630 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 631
NYX 0:85b3fd62ea1a 632 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
NYX 0:85b3fd62ea1a 633 {
NYX 0:85b3fd62ea1a 634 return HAL_ERROR;
NYX 0:85b3fd62ea1a 635 }
NYX 0:85b3fd62ea1a 636
NYX 0:85b3fd62ea1a 637 if(hi2s->State == HAL_I2S_STATE_READY)
NYX 0:85b3fd62ea1a 638 {
NYX 0:85b3fd62ea1a 639 hi2s->pTxBuffPtr = pTxData;
NYX 0:85b3fd62ea1a 640 hi2s->pRxBuffPtr = pRxData;
NYX 0:85b3fd62ea1a 641
NYX 0:85b3fd62ea1a 642 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
NYX 0:85b3fd62ea1a 643 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
NYX 0:85b3fd62ea1a 644 is selected during the I2S configuration phase, the Size parameter means the number
NYX 0:85b3fd62ea1a 645 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
NYX 0:85b3fd62ea1a 646 frame is selected the Size parameter means the number of 16-bit data length. */
NYX 0:85b3fd62ea1a 647 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
NYX 0:85b3fd62ea1a 648 {
NYX 0:85b3fd62ea1a 649 hi2s->TxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 650 hi2s->TxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 651 hi2s->RxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 652 hi2s->RxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 653 }
NYX 0:85b3fd62ea1a 654 else
NYX 0:85b3fd62ea1a 655 {
NYX 0:85b3fd62ea1a 656 hi2s->TxXferSize = Size;
NYX 0:85b3fd62ea1a 657 hi2s->TxXferCount = Size;
NYX 0:85b3fd62ea1a 658 hi2s->RxXferSize = Size;
NYX 0:85b3fd62ea1a 659 hi2s->RxXferCount = Size;
NYX 0:85b3fd62ea1a 660 }
NYX 0:85b3fd62ea1a 661
NYX 0:85b3fd62ea1a 662 /* Process Locked */
NYX 0:85b3fd62ea1a 663 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 664
NYX 0:85b3fd62ea1a 665 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 666 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
NYX 0:85b3fd62ea1a 667
NYX 0:85b3fd62ea1a 668 /* Set the I2S Rx DMA transfer complete callback */
NYX 0:85b3fd62ea1a 669 hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt;
NYX 0:85b3fd62ea1a 670
NYX 0:85b3fd62ea1a 671 /* Set the I2S Rx DMA error callback */
NYX 0:85b3fd62ea1a 672 hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
NYX 0:85b3fd62ea1a 673
NYX 0:85b3fd62ea1a 674 /* Set the I2S Tx DMA transfer complete callback */
NYX 0:85b3fd62ea1a 675 hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt;
NYX 0:85b3fd62ea1a 676
NYX 0:85b3fd62ea1a 677 /* Set the I2S Tx DMA error callback */
NYX 0:85b3fd62ea1a 678 hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError;
NYX 0:85b3fd62ea1a 679
NYX 0:85b3fd62ea1a 680 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
NYX 0:85b3fd62ea1a 681 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
NYX 0:85b3fd62ea1a 682 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
NYX 0:85b3fd62ea1a 683 {
NYX 0:85b3fd62ea1a 684 /* Enable the Rx DMA Stream */
NYX 0:85b3fd62ea1a 685 tmp = (uint32_t*)&pRxData;
NYX 0:85b3fd62ea1a 686 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
NYX 0:85b3fd62ea1a 687
NYX 0:85b3fd62ea1a 688 /* Enable Rx DMA Request */
NYX 0:85b3fd62ea1a 689 SET_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 690
NYX 0:85b3fd62ea1a 691 /* Enable the Tx DMA Stream */
NYX 0:85b3fd62ea1a 692 tmp = (uint32_t*)&pTxData;
NYX 0:85b3fd62ea1a 693 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
NYX 0:85b3fd62ea1a 694
NYX 0:85b3fd62ea1a 695 /* Enable Tx DMA Request */
NYX 0:85b3fd62ea1a 696 SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 697
NYX 0:85b3fd62ea1a 698 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 699 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 700 {
NYX 0:85b3fd62ea1a 701 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
NYX 0:85b3fd62ea1a 702 __HAL_I2SEXT_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 703
NYX 0:85b3fd62ea1a 704 /* Enable I2S peripheral after the I2Sext */
NYX 0:85b3fd62ea1a 705 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 706 }
NYX 0:85b3fd62ea1a 707 }
NYX 0:85b3fd62ea1a 708 else
NYX 0:85b3fd62ea1a 709 {
NYX 0:85b3fd62ea1a 710 /* Check if Master Receiver mode is selected */
NYX 0:85b3fd62ea1a 711 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
NYX 0:85b3fd62ea1a 712 {
NYX 0:85b3fd62ea1a 713 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
NYX 0:85b3fd62ea1a 714 access to the SPI_SR register. */
NYX 0:85b3fd62ea1a 715 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 716 }
NYX 0:85b3fd62ea1a 717 /* Enable the Tx DMA Stream */
NYX 0:85b3fd62ea1a 718 tmp = (uint32_t*)&pTxData;
NYX 0:85b3fd62ea1a 719 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
NYX 0:85b3fd62ea1a 720
NYX 0:85b3fd62ea1a 721 /* Enable Tx DMA Request */
NYX 0:85b3fd62ea1a 722 SET_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 723
NYX 0:85b3fd62ea1a 724 /* Enable the Rx DMA Stream */
NYX 0:85b3fd62ea1a 725 tmp = (uint32_t*)&pRxData;
NYX 0:85b3fd62ea1a 726 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
NYX 0:85b3fd62ea1a 727
NYX 0:85b3fd62ea1a 728 /* Enable Rx DMA Request */
NYX 0:85b3fd62ea1a 729 SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 730
NYX 0:85b3fd62ea1a 731 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 732 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 733 {
NYX 0:85b3fd62ea1a 734 /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
NYX 0:85b3fd62ea1a 735 __HAL_I2SEXT_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 736 /* Enable I2S peripheral before the I2Sext */
NYX 0:85b3fd62ea1a 737 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 738 }
NYX 0:85b3fd62ea1a 739 }
NYX 0:85b3fd62ea1a 740
NYX 0:85b3fd62ea1a 741 /* Process Unlocked */
NYX 0:85b3fd62ea1a 742 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 743
NYX 0:85b3fd62ea1a 744 return HAL_OK;
NYX 0:85b3fd62ea1a 745 }
NYX 0:85b3fd62ea1a 746 else
NYX 0:85b3fd62ea1a 747 {
NYX 0:85b3fd62ea1a 748 return HAL_BUSY;
NYX 0:85b3fd62ea1a 749 }
NYX 0:85b3fd62ea1a 750 }
NYX 0:85b3fd62ea1a 751
NYX 0:85b3fd62ea1a 752 /**
NYX 0:85b3fd62ea1a 753 * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
NYX 0:85b3fd62ea1a 754 * @param hi2s: I2S handle
NYX 0:85b3fd62ea1a 755 * @retval HAL status
NYX 0:85b3fd62ea1a 756 */
NYX 0:85b3fd62ea1a 757 void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 758 {
NYX 0:85b3fd62ea1a 759 __IO uint32_t i2ssr = hi2s->Instance->SR ;
NYX 0:85b3fd62ea1a 760 __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
NYX 0:85b3fd62ea1a 761
NYX 0:85b3fd62ea1a 762 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
NYX 0:85b3fd62ea1a 763 if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
NYX 0:85b3fd62ea1a 764 || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
NYX 0:85b3fd62ea1a 765 {
NYX 0:85b3fd62ea1a 766 /* I2S in mode Transmitter -------------------------------------------------*/
NYX 0:85b3fd62ea1a 767 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
NYX 0:85b3fd62ea1a 768 {
NYX 0:85b3fd62ea1a 769 /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
NYX 0:85b3fd62ea1a 770 the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
NYX 0:85b3fd62ea1a 771 I2SEx_FullDuplexTx_IT(hi2s, I2S_USE_I2S);
NYX 0:85b3fd62ea1a 772 }
NYX 0:85b3fd62ea1a 773
NYX 0:85b3fd62ea1a 774 /* I2Sext in mode Receiver -----------------------------------------------*/
NYX 0:85b3fd62ea1a 775 if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
NYX 0:85b3fd62ea1a 776 {
NYX 0:85b3fd62ea1a 777 /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
NYX 0:85b3fd62ea1a 778 the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
NYX 0:85b3fd62ea1a 779 I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT);
NYX 0:85b3fd62ea1a 780 }
NYX 0:85b3fd62ea1a 781
NYX 0:85b3fd62ea1a 782 /* I2Sext Overrun error interrupt occured --------------------------------*/
NYX 0:85b3fd62ea1a 783 if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
NYX 0:85b3fd62ea1a 784 {
NYX 0:85b3fd62ea1a 785 /* Disable RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 786 __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 787
NYX 0:85b3fd62ea1a 788 /* Disable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 789 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 790
NYX 0:85b3fd62ea1a 791 /* Clear Overrun flag */
NYX 0:85b3fd62ea1a 792 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 793
NYX 0:85b3fd62ea1a 794 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 795 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 796
NYX 0:85b3fd62ea1a 797 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 798 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
NYX 0:85b3fd62ea1a 799 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 800 }
NYX 0:85b3fd62ea1a 801
NYX 0:85b3fd62ea1a 802 /* I2S Underrun error interrupt occured ----------------------------------*/
NYX 0:85b3fd62ea1a 803 if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
NYX 0:85b3fd62ea1a 804 {
NYX 0:85b3fd62ea1a 805 /* Disable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 806 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 807
NYX 0:85b3fd62ea1a 808 /* Disable RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 809 __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 810
NYX 0:85b3fd62ea1a 811 /* Clear underrun flag */
NYX 0:85b3fd62ea1a 812 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
NYX 0:85b3fd62ea1a 813
NYX 0:85b3fd62ea1a 814 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 815 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 816
NYX 0:85b3fd62ea1a 817 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 818 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
NYX 0:85b3fd62ea1a 819 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 820 }
NYX 0:85b3fd62ea1a 821 }
NYX 0:85b3fd62ea1a 822 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
NYX 0:85b3fd62ea1a 823 else
NYX 0:85b3fd62ea1a 824 {
NYX 0:85b3fd62ea1a 825 /* I2Sext in mode Transmitter ----------------------------------------------*/
NYX 0:85b3fd62ea1a 826 if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
NYX 0:85b3fd62ea1a 827 {
NYX 0:85b3fd62ea1a 828 /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
NYX 0:85b3fd62ea1a 829 the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
NYX 0:85b3fd62ea1a 830 I2SEx_FullDuplexTx_IT(hi2s, I2S_USE_I2SEXT);
NYX 0:85b3fd62ea1a 831 }
NYX 0:85b3fd62ea1a 832
NYX 0:85b3fd62ea1a 833 /* I2S in mode Receiver --------------------------------------------------*/
NYX 0:85b3fd62ea1a 834 if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
NYX 0:85b3fd62ea1a 835 {
NYX 0:85b3fd62ea1a 836 /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
NYX 0:85b3fd62ea1a 837 the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
NYX 0:85b3fd62ea1a 838 I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2S);
NYX 0:85b3fd62ea1a 839 }
NYX 0:85b3fd62ea1a 840
NYX 0:85b3fd62ea1a 841 /* I2S Overrun error interrupt occured -------------------------------------*/
NYX 0:85b3fd62ea1a 842 if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
NYX 0:85b3fd62ea1a 843 {
NYX 0:85b3fd62ea1a 844 /* Disable RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 845 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 846
NYX 0:85b3fd62ea1a 847 /* Disable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 848 __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 849
NYX 0:85b3fd62ea1a 850 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 851 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 852
NYX 0:85b3fd62ea1a 853 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 854 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
NYX 0:85b3fd62ea1a 855 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 856 }
NYX 0:85b3fd62ea1a 857
NYX 0:85b3fd62ea1a 858 /* I2Sext Underrun error interrupt occured -------------------------------*/
NYX 0:85b3fd62ea1a 859 if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
NYX 0:85b3fd62ea1a 860 {
NYX 0:85b3fd62ea1a 861 /* Disable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 862 __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 863
NYX 0:85b3fd62ea1a 864 /* Disable RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 865 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 866
NYX 0:85b3fd62ea1a 867 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 868 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 869
NYX 0:85b3fd62ea1a 870 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 871 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
NYX 0:85b3fd62ea1a 872 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 873 }
NYX 0:85b3fd62ea1a 874 }
NYX 0:85b3fd62ea1a 875 }
NYX 0:85b3fd62ea1a 876
NYX 0:85b3fd62ea1a 877 /**
NYX 0:85b3fd62ea1a 878 * @brief Tx and Rx Transfer completed callback
NYX 0:85b3fd62ea1a 879 * @param hi2s: I2S handle
NYX 0:85b3fd62ea1a 880 * @retval None
NYX 0:85b3fd62ea1a 881 */
NYX 0:85b3fd62ea1a 882 __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 883 {
NYX 0:85b3fd62ea1a 884 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 885 UNUSED(hi2s);
NYX 0:85b3fd62ea1a 886
NYX 0:85b3fd62ea1a 887 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 888 the HAL_I2SEx_TxRxCpltCallback could be implenetd in the user file
NYX 0:85b3fd62ea1a 889 */
NYX 0:85b3fd62ea1a 890 }
NYX 0:85b3fd62ea1a 891
NYX 0:85b3fd62ea1a 892 /**
NYX 0:85b3fd62ea1a 893 * @}
NYX 0:85b3fd62ea1a 894 */
NYX 0:85b3fd62ea1a 895
NYX 0:85b3fd62ea1a 896 /**
NYX 0:85b3fd62ea1a 897 * @}
NYX 0:85b3fd62ea1a 898 */
NYX 0:85b3fd62ea1a 899
NYX 0:85b3fd62ea1a 900 /** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
NYX 0:85b3fd62ea1a 901 * @{
NYX 0:85b3fd62ea1a 902 */
NYX 0:85b3fd62ea1a 903
NYX 0:85b3fd62ea1a 904 /**
NYX 0:85b3fd62ea1a 905 * @brief DMA I2S transmit receive process complete callback
NYX 0:85b3fd62ea1a 906 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 907 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 908 * @retval None
NYX 0:85b3fd62ea1a 909 */
NYX 0:85b3fd62ea1a 910 static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 911 {
NYX 0:85b3fd62ea1a 912 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
NYX 0:85b3fd62ea1a 913
NYX 0:85b3fd62ea1a 914 /* if DMA is not configured in DMA_CIRCULAR mode */
NYX 0:85b3fd62ea1a 915 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
NYX 0:85b3fd62ea1a 916 {
NYX 0:85b3fd62ea1a 917 if (hi2s->hdmarx == hdma)
NYX 0:85b3fd62ea1a 918 {
NYX 0:85b3fd62ea1a 919 /* Disable Rx DMA Request */
NYX 0:85b3fd62ea1a 920 if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) ||\
NYX 0:85b3fd62ea1a 921 ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
NYX 0:85b3fd62ea1a 922 {
NYX 0:85b3fd62ea1a 923 CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 924 }
NYX 0:85b3fd62ea1a 925 else
NYX 0:85b3fd62ea1a 926 {
NYX 0:85b3fd62ea1a 927 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 928 }
NYX 0:85b3fd62ea1a 929
NYX 0:85b3fd62ea1a 930 hi2s->RxXferCount = 0U;
NYX 0:85b3fd62ea1a 931
NYX 0:85b3fd62ea1a 932 if (hi2s->TxXferCount == 0U)
NYX 0:85b3fd62ea1a 933 {
NYX 0:85b3fd62ea1a 934 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 935
NYX 0:85b3fd62ea1a 936 HAL_I2SEx_TxRxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 937 }
NYX 0:85b3fd62ea1a 938 }
NYX 0:85b3fd62ea1a 939
NYX 0:85b3fd62ea1a 940 if (hi2s->hdmatx == hdma)
NYX 0:85b3fd62ea1a 941 {
NYX 0:85b3fd62ea1a 942 /* Disable Tx DMA Request */
NYX 0:85b3fd62ea1a 943 if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) ||\
NYX 0:85b3fd62ea1a 944 ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
NYX 0:85b3fd62ea1a 945 {
NYX 0:85b3fd62ea1a 946 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 947 }
NYX 0:85b3fd62ea1a 948 else
NYX 0:85b3fd62ea1a 949 {
NYX 0:85b3fd62ea1a 950 CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 951 }
NYX 0:85b3fd62ea1a 952
NYX 0:85b3fd62ea1a 953 hi2s->TxXferCount = 0U;
NYX 0:85b3fd62ea1a 954
NYX 0:85b3fd62ea1a 955 if (hi2s->RxXferCount == 0U)
NYX 0:85b3fd62ea1a 956 {
NYX 0:85b3fd62ea1a 957 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 958
NYX 0:85b3fd62ea1a 959 HAL_I2SEx_TxRxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 960 }
NYX 0:85b3fd62ea1a 961 }
NYX 0:85b3fd62ea1a 962 }
NYX 0:85b3fd62ea1a 963 }
NYX 0:85b3fd62ea1a 964
NYX 0:85b3fd62ea1a 965 /**
NYX 0:85b3fd62ea1a 966 * @brief DMA I2S communication error callback
NYX 0:85b3fd62ea1a 967 * @param hdma : DMA handle
NYX 0:85b3fd62ea1a 968 * @retval None
NYX 0:85b3fd62ea1a 969 */
NYX 0:85b3fd62ea1a 970 static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 971 {
NYX 0:85b3fd62ea1a 972 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX 0:85b3fd62ea1a 973
NYX 0:85b3fd62ea1a 974 /* Disable Rx and Tx DMA Request */
NYX 0:85b3fd62ea1a 975 CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
NYX 0:85b3fd62ea1a 976 CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
NYX 0:85b3fd62ea1a 977
NYX 0:85b3fd62ea1a 978 hi2s->TxXferCount = 0U;
NYX 0:85b3fd62ea1a 979 hi2s->RxXferCount = 0U;
NYX 0:85b3fd62ea1a 980
NYX 0:85b3fd62ea1a 981 hi2s->State= HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 982
NYX 0:85b3fd62ea1a 983 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 984 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
NYX 0:85b3fd62ea1a 985 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 986 }
NYX 0:85b3fd62ea1a 987
NYX 0:85b3fd62ea1a 988 /**
NYX 0:85b3fd62ea1a 989 * @brief Full-Duplex IT handler transmit function
NYX 0:85b3fd62ea1a 990 * @param hi2s: I2S handle
NYX 0:85b3fd62ea1a 991 * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
NYX 0:85b3fd62ea1a 992 * @retval None
NYX 0:85b3fd62ea1a 993 */
NYX 0:85b3fd62ea1a 994 static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
NYX 0:85b3fd62ea1a 995 {
NYX 0:85b3fd62ea1a 996 if(i2sUsed == I2S_USE_I2S)
NYX 0:85b3fd62ea1a 997 {
NYX 0:85b3fd62ea1a 998 /* Write Data on DR register */
NYX 0:85b3fd62ea1a 999 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
NYX 0:85b3fd62ea1a 1000 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 1001
NYX 0:85b3fd62ea1a 1002 if(hi2s->TxXferCount == 0U)
NYX 0:85b3fd62ea1a 1003 {
NYX 0:85b3fd62ea1a 1004 /* Disable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 1005 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 1006
NYX 0:85b3fd62ea1a 1007 if(hi2s->RxXferCount == 0U)
NYX 0:85b3fd62ea1a 1008 {
NYX 0:85b3fd62ea1a 1009 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1010 HAL_I2SEx_TxRxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1011 }
NYX 0:85b3fd62ea1a 1012 }
NYX 0:85b3fd62ea1a 1013 }
NYX 0:85b3fd62ea1a 1014 else
NYX 0:85b3fd62ea1a 1015 {
NYX 0:85b3fd62ea1a 1016 /* Write Data on DR register */
NYX 0:85b3fd62ea1a 1017 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
NYX 0:85b3fd62ea1a 1018 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 1019
NYX 0:85b3fd62ea1a 1020 if(hi2s->TxXferCount == 0U)
NYX 0:85b3fd62ea1a 1021 {
NYX 0:85b3fd62ea1a 1022 /* Disable I2Sext TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 1023 __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 1024
NYX 0:85b3fd62ea1a 1025 if(hi2s->RxXferCount == 0U)
NYX 0:85b3fd62ea1a 1026 {
NYX 0:85b3fd62ea1a 1027 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1028 HAL_I2SEx_TxRxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1029 }
NYX 0:85b3fd62ea1a 1030 }
NYX 0:85b3fd62ea1a 1031 }
NYX 0:85b3fd62ea1a 1032 }
NYX 0:85b3fd62ea1a 1033
NYX 0:85b3fd62ea1a 1034 /**
NYX 0:85b3fd62ea1a 1035 * @brief Full-Duplex IT handler receive function
NYX 0:85b3fd62ea1a 1036 * @param hi2s: I2S handle
NYX 0:85b3fd62ea1a 1037 * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
NYX 0:85b3fd62ea1a 1038 * @retval None
NYX 0:85b3fd62ea1a 1039 */
NYX 0:85b3fd62ea1a 1040 static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
NYX 0:85b3fd62ea1a 1041 {
NYX 0:85b3fd62ea1a 1042 if(i2sUsed == I2S_USE_I2S)
NYX 0:85b3fd62ea1a 1043 {
NYX 0:85b3fd62ea1a 1044 /* Read Data from DR register */
NYX 0:85b3fd62ea1a 1045 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
NYX 0:85b3fd62ea1a 1046 hi2s->RxXferCount--;
NYX 0:85b3fd62ea1a 1047
NYX 0:85b3fd62ea1a 1048 if(hi2s->RxXferCount == 0U)
NYX 0:85b3fd62ea1a 1049 {
NYX 0:85b3fd62ea1a 1050 /* Disable RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 1051 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 1052
NYX 0:85b3fd62ea1a 1053 if(hi2s->TxXferCount == 0U)
NYX 0:85b3fd62ea1a 1054 {
NYX 0:85b3fd62ea1a 1055 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1056 HAL_I2SEx_TxRxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1057 }
NYX 0:85b3fd62ea1a 1058 }
NYX 0:85b3fd62ea1a 1059 }
NYX 0:85b3fd62ea1a 1060 else
NYX 0:85b3fd62ea1a 1061 {
NYX 0:85b3fd62ea1a 1062 /* Read Data from DR register */
NYX 0:85b3fd62ea1a 1063 (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
NYX 0:85b3fd62ea1a 1064 hi2s->RxXferCount--;
NYX 0:85b3fd62ea1a 1065
NYX 0:85b3fd62ea1a 1066 if(hi2s->RxXferCount == 0U)
NYX 0:85b3fd62ea1a 1067 {
NYX 0:85b3fd62ea1a 1068 /* Disable I2Sext RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 1069 __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 1070
NYX 0:85b3fd62ea1a 1071 if(hi2s->TxXferCount == 0U)
NYX 0:85b3fd62ea1a 1072 {
NYX 0:85b3fd62ea1a 1073 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1074 HAL_I2SEx_TxRxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1075 }
NYX 0:85b3fd62ea1a 1076 }
NYX 0:85b3fd62ea1a 1077 }
NYX 0:85b3fd62ea1a 1078 }
NYX 0:85b3fd62ea1a 1079
NYX 0:85b3fd62ea1a 1080 /**
NYX 0:85b3fd62ea1a 1081 * @brief This function handles I2S Communication Timeout.
NYX 0:85b3fd62ea1a 1082 * @param hi2s: I2S handle
NYX 0:85b3fd62ea1a 1083 * @param Flag: Flag checked
NYX 0:85b3fd62ea1a 1084 * @param State: Value of the flag expected
NYX 0:85b3fd62ea1a 1085 * @param Timeout: Duration of the timeout
NYX 0:85b3fd62ea1a 1086 * @param i2sUsed: I2S instance reference
NYX 0:85b3fd62ea1a 1087 * @retval HAL status
NYX 0:85b3fd62ea1a 1088 */
NYX 0:85b3fd62ea1a 1089 static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
NYX 0:85b3fd62ea1a 1090 uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
NYX 0:85b3fd62ea1a 1091 {
NYX 0:85b3fd62ea1a 1092 uint32_t tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1093
NYX 0:85b3fd62ea1a 1094 if(i2sUsed == I2S_USE_I2S)
NYX 0:85b3fd62ea1a 1095 {
NYX 0:85b3fd62ea1a 1096 /* Wait until flag is reset */
NYX 0:85b3fd62ea1a 1097 while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
NYX 0:85b3fd62ea1a 1098 {
NYX 0:85b3fd62ea1a 1099 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 1100 {
NYX 0:85b3fd62ea1a 1101 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
NYX 0:85b3fd62ea1a 1102 {
NYX 0:85b3fd62ea1a 1103 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 1104 hi2s->State= HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1105
NYX 0:85b3fd62ea1a 1106 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1107 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 1108
NYX 0:85b3fd62ea1a 1109 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1110 }
NYX 0:85b3fd62ea1a 1111 }
NYX 0:85b3fd62ea1a 1112 }
NYX 0:85b3fd62ea1a 1113 }
NYX 0:85b3fd62ea1a 1114 else /* i2sUsed == I2S_USE_I2SEXT */
NYX 0:85b3fd62ea1a 1115 {
NYX 0:85b3fd62ea1a 1116 /* Wait until flag is reset */
NYX 0:85b3fd62ea1a 1117 while(((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
NYX 0:85b3fd62ea1a 1118 {
NYX 0:85b3fd62ea1a 1119 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 1120 {
NYX 0:85b3fd62ea1a 1121 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
NYX 0:85b3fd62ea1a 1122 {
NYX 0:85b3fd62ea1a 1123 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 1124 hi2s->State= HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1125
NYX 0:85b3fd62ea1a 1126 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1127 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 1128
NYX 0:85b3fd62ea1a 1129 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1130 }
NYX 0:85b3fd62ea1a 1131 }
NYX 0:85b3fd62ea1a 1132 }
NYX 0:85b3fd62ea1a 1133 }
NYX 0:85b3fd62ea1a 1134 return HAL_OK;
NYX 0:85b3fd62ea1a 1135 }
NYX 0:85b3fd62ea1a 1136
NYX 0:85b3fd62ea1a 1137 /**
NYX 0:85b3fd62ea1a 1138 * @}
NYX 0:85b3fd62ea1a 1139 */
NYX 0:85b3fd62ea1a 1140 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
NYX 0:85b3fd62ea1a 1141
NYX 0:85b3fd62ea1a 1142 /**
NYX 0:85b3fd62ea1a 1143 * @}
NYX 0:85b3fd62ea1a 1144 */
NYX 0:85b3fd62ea1a 1145 #endif /* HAL_I2S_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 1146
NYX 0:85b3fd62ea1a 1147 /**
NYX 0:85b3fd62ea1a 1148 * @}
NYX 0:85b3fd62ea1a 1149 */
NYX 0:85b3fd62ea1a 1150
NYX 0:85b3fd62ea1a 1151 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/