Takaaki Numai / mbed-dev

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Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_i2s.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief I2S HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
NYX 0:85b3fd62ea1a 10 * + Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 11 * + IO operation functions
NYX 0:85b3fd62ea1a 12 * + Peripheral State and Errors functions
NYX 0:85b3fd62ea1a 13 @verbatim
NYX 0:85b3fd62ea1a 14 ===============================================================================
NYX 0:85b3fd62ea1a 15 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 16 ===============================================================================
NYX 0:85b3fd62ea1a 17 [..]
NYX 0:85b3fd62ea1a 18 The I2S HAL driver can be used as follow:
NYX 0:85b3fd62ea1a 19
NYX 0:85b3fd62ea1a 20 (#) Declare a I2S_HandleTypeDef handle structure.
NYX 0:85b3fd62ea1a 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
NYX 0:85b3fd62ea1a 22 (##) Enable the SPIx interface clock.
NYX 0:85b3fd62ea1a 23 (##) I2S pins configuration:
NYX 0:85b3fd62ea1a 24 (+++) Enable the clock for the I2S GPIOs.
NYX 0:85b3fd62ea1a 25 (+++) Configure these I2S pins as alternate function pull-up.
NYX 0:85b3fd62ea1a 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
NYX 0:85b3fd62ea1a 27 and HAL_I2S_Receive_IT() APIs).
NYX 0:85b3fd62ea1a 28 (+++) Configure the I2Sx interrupt priority.
NYX 0:85b3fd62ea1a 29 (+++) Enable the NVIC I2S IRQ handle.
NYX 0:85b3fd62ea1a 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
NYX 0:85b3fd62ea1a 31 and HAL_I2S_Receive_DMA() APIs:
NYX 0:85b3fd62ea1a 32 (+++) Declare a DMA handle structure for the Tx/Rx stream.
NYX 0:85b3fd62ea1a 33 (+++) Enable the DMAx interface clock.
NYX 0:85b3fd62ea1a 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
NYX 0:85b3fd62ea1a 35 (+++) Configure the DMA Tx/Rx Stream.
NYX 0:85b3fd62ea1a 36 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
NYX 0:85b3fd62ea1a 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
NYX 0:85b3fd62ea1a 38 DMA Tx/Rx Stream.
NYX 0:85b3fd62ea1a 39
NYX 0:85b3fd62ea1a 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
NYX 0:85b3fd62ea1a 41 using HAL_I2S_Init() function.
NYX 0:85b3fd62ea1a 42
NYX 0:85b3fd62ea1a 43 -@- The specific I2S interrupts (Transmission complete interrupt,
NYX 0:85b3fd62ea1a 44 RXNE interrupt and Error Interrupts) will be managed using the macros
NYX 0:85b3fd62ea1a 45 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
NYX 0:85b3fd62ea1a 46 -@- Make sure that either:
NYX 0:85b3fd62ea1a 47 (+@) I2S PLL is configured or
NYX 0:85b3fd62ea1a 48 (+@) External clock source is configured after setting correctly
NYX 0:85b3fd62ea1a 49 the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
NYX 0:85b3fd62ea1a 50
NYX 0:85b3fd62ea1a 51 (#) Three operation modes are available within this driver :
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 *** Polling mode IO operation ***
NYX 0:85b3fd62ea1a 54 =================================
NYX 0:85b3fd62ea1a 55 [..]
NYX 0:85b3fd62ea1a 56 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
NYX 0:85b3fd62ea1a 57 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 *** Interrupt mode IO operation ***
NYX 0:85b3fd62ea1a 60 ===================================
NYX 0:85b3fd62ea1a 61 [..]
NYX 0:85b3fd62ea1a 62 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
NYX 0:85b3fd62ea1a 63 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 64 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
NYX 0:85b3fd62ea1a 65 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 66 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
NYX 0:85b3fd62ea1a 67 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
NYX 0:85b3fd62ea1a 68 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 69 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
NYX 0:85b3fd62ea1a 70 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 71 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
NYX 0:85b3fd62ea1a 72 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
NYX 0:85b3fd62ea1a 73 add his own code by customization of function pointer HAL_I2S_ErrorCallback
NYX 0:85b3fd62ea1a 74
NYX 0:85b3fd62ea1a 75 *** DMA mode IO operation ***
NYX 0:85b3fd62ea1a 76 ==============================
NYX 0:85b3fd62ea1a 77 [..]
NYX 0:85b3fd62ea1a 78 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
NYX 0:85b3fd62ea1a 79 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 80 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
NYX 0:85b3fd62ea1a 81 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 82 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
NYX 0:85b3fd62ea1a 83 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
NYX 0:85b3fd62ea1a 84 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 85 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
NYX 0:85b3fd62ea1a 86 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
NYX 0:85b3fd62ea1a 87 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
NYX 0:85b3fd62ea1a 88 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
NYX 0:85b3fd62ea1a 89 add his own code by customization of function pointer HAL_I2S_ErrorCallback
NYX 0:85b3fd62ea1a 90 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
NYX 0:85b3fd62ea1a 91 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
NYX 0:85b3fd62ea1a 92 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
NYX 0:85b3fd62ea1a 93
NYX 0:85b3fd62ea1a 94 *** I2S HAL driver macros list ***
NYX 0:85b3fd62ea1a 95 =============================================
NYX 0:85b3fd62ea1a 96 [..]
NYX 0:85b3fd62ea1a 97 Below the list of most used macros in I2S HAL driver.
NYX 0:85b3fd62ea1a 98
NYX 0:85b3fd62ea1a 99 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
NYX 0:85b3fd62ea1a 100 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
NYX 0:85b3fd62ea1a 101 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
NYX 0:85b3fd62ea1a 102 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
NYX 0:85b3fd62ea1a 103 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
NYX 0:85b3fd62ea1a 104
NYX 0:85b3fd62ea1a 105 [..]
NYX 0:85b3fd62ea1a 106 (@) You can refer to the I2S HAL driver header file for more useful macros
NYX 0:85b3fd62ea1a 107
NYX 0:85b3fd62ea1a 108 @endverbatim
NYX 0:85b3fd62ea1a 109 ******************************************************************************
NYX 0:85b3fd62ea1a 110 * @attention
NYX 0:85b3fd62ea1a 111 *
NYX 0:85b3fd62ea1a 112 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 113 *
NYX 0:85b3fd62ea1a 114 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 115 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 116 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 117 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 118 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 119 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 120 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 121 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 122 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 123 * without specific prior written permission.
NYX 0:85b3fd62ea1a 124 *
NYX 0:85b3fd62ea1a 125 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 126 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 127 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 128 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 129 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 130 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 131 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 132 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 133 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 134 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 135 *
NYX 0:85b3fd62ea1a 136 ******************************************************************************
NYX 0:85b3fd62ea1a 137 */
NYX 0:85b3fd62ea1a 138
NYX 0:85b3fd62ea1a 139 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 140 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 141
NYX 0:85b3fd62ea1a 142 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 143 * @{
NYX 0:85b3fd62ea1a 144 */
NYX 0:85b3fd62ea1a 145
NYX 0:85b3fd62ea1a 146 #ifdef HAL_I2S_MODULE_ENABLED
NYX 0:85b3fd62ea1a 147
NYX 0:85b3fd62ea1a 148 /** @defgroup I2S I2S
NYX 0:85b3fd62ea1a 149 * @brief I2S HAL module driver
NYX 0:85b3fd62ea1a 150 * @{
NYX 0:85b3fd62ea1a 151 */
NYX 0:85b3fd62ea1a 152
NYX 0:85b3fd62ea1a 153 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 154 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 155 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 156 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 157 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 158
NYX 0:85b3fd62ea1a 159 /** @addtogroup I2S_Private_Functions
NYX 0:85b3fd62ea1a 160 * @{
NYX 0:85b3fd62ea1a 161 */
NYX 0:85b3fd62ea1a 162 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 163 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 164 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 165 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 166 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 167 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
NYX 0:85b3fd62ea1a 168 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
NYX 0:85b3fd62ea1a 169 static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
NYX 0:85b3fd62ea1a 170 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
NYX 0:85b3fd62ea1a 171 uint32_t Timeout);
NYX 0:85b3fd62ea1a 172 /**
NYX 0:85b3fd62ea1a 173 * @}
NYX 0:85b3fd62ea1a 174 */
NYX 0:85b3fd62ea1a 175
NYX 0:85b3fd62ea1a 176 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 177 /** @addtogroup I2S_Exported_Functions I2S Exported Functions
NYX 0:85b3fd62ea1a 178 * @{
NYX 0:85b3fd62ea1a 179 */
NYX 0:85b3fd62ea1a 180
NYX 0:85b3fd62ea1a 181 /** @addtogroup I2S_Exported_Functions_Group1
NYX 0:85b3fd62ea1a 182 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 183 *
NYX 0:85b3fd62ea1a 184 @verbatim
NYX 0:85b3fd62ea1a 185 ===============================================================================
NYX 0:85b3fd62ea1a 186 ##### Initialization and de-initialization functions #####
NYX 0:85b3fd62ea1a 187 ===============================================================================
NYX 0:85b3fd62ea1a 188 [..] This subsection provides a set of functions allowing to initialize and
NYX 0:85b3fd62ea1a 189 de-initialize the I2Sx peripheral in simplex mode:
NYX 0:85b3fd62ea1a 190
NYX 0:85b3fd62ea1a 191 (+) User must Implement HAL_I2S_MspInit() function in which he configures
NYX 0:85b3fd62ea1a 192 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
NYX 0:85b3fd62ea1a 193
NYX 0:85b3fd62ea1a 194 (+) Call the function HAL_I2S_Init() to configure the selected device with
NYX 0:85b3fd62ea1a 195 the selected configuration:
NYX 0:85b3fd62ea1a 196 (++) Mode
NYX 0:85b3fd62ea1a 197 (++) Standard
NYX 0:85b3fd62ea1a 198 (++) Data Format
NYX 0:85b3fd62ea1a 199 (++) MCLK Output
NYX 0:85b3fd62ea1a 200 (++) Audio frequency
NYX 0:85b3fd62ea1a 201 (++) Polarity
NYX 0:85b3fd62ea1a 202 (++) Full duplex mode
NYX 0:85b3fd62ea1a 203
NYX 0:85b3fd62ea1a 204 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
NYX 0:85b3fd62ea1a 205 of the selected I2Sx peripheral.
NYX 0:85b3fd62ea1a 206 @endverbatim
NYX 0:85b3fd62ea1a 207 * @{
NYX 0:85b3fd62ea1a 208 */
NYX 0:85b3fd62ea1a 209
NYX 0:85b3fd62ea1a 210 /**
NYX 0:85b3fd62ea1a 211 * @brief Initializes the I2S according to the specified parameters
NYX 0:85b3fd62ea1a 212 * in the I2S_InitTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 213 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 214 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 215 * @retval HAL status
NYX 0:85b3fd62ea1a 216 */
NYX 0:85b3fd62ea1a 217 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 218 {
NYX 0:85b3fd62ea1a 219 uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U;
NYX 0:85b3fd62ea1a 220 uint32_t tmp = 0U, i2sclk = 0U;
NYX 0:85b3fd62ea1a 221
NYX 0:85b3fd62ea1a 222 /* Check the I2S handle allocation */
NYX 0:85b3fd62ea1a 223 if(hi2s == NULL)
NYX 0:85b3fd62ea1a 224 {
NYX 0:85b3fd62ea1a 225 return HAL_ERROR;
NYX 0:85b3fd62ea1a 226 }
NYX 0:85b3fd62ea1a 227
NYX 0:85b3fd62ea1a 228 /* Check the I2S parameters */
NYX 0:85b3fd62ea1a 229 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
NYX 0:85b3fd62ea1a 230 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
NYX 0:85b3fd62ea1a 231 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
NYX 0:85b3fd62ea1a 232 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
NYX 0:85b3fd62ea1a 233 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
NYX 0:85b3fd62ea1a 234 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
NYX 0:85b3fd62ea1a 235 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
NYX 0:85b3fd62ea1a 236 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
NYX 0:85b3fd62ea1a 237
NYX 0:85b3fd62ea1a 238 hi2s->State = HAL_I2S_STATE_BUSY;
NYX 0:85b3fd62ea1a 239
NYX 0:85b3fd62ea1a 240 /* Initialize Default I2S IrqHandler ISR */
NYX 0:85b3fd62ea1a 241 hi2s->IrqHandlerISR = I2S_IRQHandler;
NYX 0:85b3fd62ea1a 242
NYX 0:85b3fd62ea1a 243 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
NYX 0:85b3fd62ea1a 244 HAL_I2S_MspInit(hi2s);
NYX 0:85b3fd62ea1a 245
NYX 0:85b3fd62ea1a 246 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
NYX 0:85b3fd62ea1a 247 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
NYX 0:85b3fd62ea1a 248 CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
NYX 0:85b3fd62ea1a 249 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
NYX 0:85b3fd62ea1a 250 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
NYX 0:85b3fd62ea1a 251 hi2s->Instance->I2SPR = 0x0002U;
NYX 0:85b3fd62ea1a 252
NYX 0:85b3fd62ea1a 253 /* Get the I2SCFGR register value */
NYX 0:85b3fd62ea1a 254 tmpreg = hi2s->Instance->I2SCFGR;
NYX 0:85b3fd62ea1a 255
NYX 0:85b3fd62ea1a 256 /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
NYX 0:85b3fd62ea1a 257 /* If the requested audio frequency is not the default, compute the prescaler */
NYX 0:85b3fd62ea1a 258 if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
NYX 0:85b3fd62ea1a 259 {
NYX 0:85b3fd62ea1a 260 /* Check the frame length (For the Prescaler computing) *******************/
NYX 0:85b3fd62ea1a 261 /* Set I2S Packet Length value*/
NYX 0:85b3fd62ea1a 262 if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
NYX 0:85b3fd62ea1a 263 {
NYX 0:85b3fd62ea1a 264 /* Packet length is 32 bits */
NYX 0:85b3fd62ea1a 265 packetlength = 32U;
NYX 0:85b3fd62ea1a 266 }
NYX 0:85b3fd62ea1a 267 else
NYX 0:85b3fd62ea1a 268 {
NYX 0:85b3fd62ea1a 269 /* Packet length is 16 bits */
NYX 0:85b3fd62ea1a 270 packetlength = 16U;
NYX 0:85b3fd62ea1a 271 }
NYX 0:85b3fd62ea1a 272
NYX 0:85b3fd62ea1a 273 /* I2S standard */
NYX 0:85b3fd62ea1a 274 if(hi2s->Init.Standard <= I2S_STANDARD_LSB)
NYX 0:85b3fd62ea1a 275 {
NYX 0:85b3fd62ea1a 276 /* In I2S standard packet lenght is multiplied by 2 */
NYX 0:85b3fd62ea1a 277 packetlength = packetlength * 2U;
NYX 0:85b3fd62ea1a 278 }
NYX 0:85b3fd62ea1a 279
NYX 0:85b3fd62ea1a 280 /* Get I2S source Clock frequency from RCC ********************************/
NYX 0:85b3fd62ea1a 281 #if defined(I2S_APB1_APB2_FEATURE)
NYX 0:85b3fd62ea1a 282 if(IS_I2S_APB1_INSTANCE(hi2s->Instance))
NYX 0:85b3fd62ea1a 283 {
NYX 0:85b3fd62ea1a 284 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB1);
NYX 0:85b3fd62ea1a 285 }
NYX 0:85b3fd62ea1a 286 else
NYX 0:85b3fd62ea1a 287 {
NYX 0:85b3fd62ea1a 288 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB2);
NYX 0:85b3fd62ea1a 289 }
NYX 0:85b3fd62ea1a 290 #else
NYX 0:85b3fd62ea1a 291 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S);
NYX 0:85b3fd62ea1a 292 #endif
NYX 0:85b3fd62ea1a 293
NYX 0:85b3fd62ea1a 294 /* Compute the Real divider depending on the MCLK output state, with a floating point */
NYX 0:85b3fd62ea1a 295 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
NYX 0:85b3fd62ea1a 296 {
NYX 0:85b3fd62ea1a 297 /* MCLK output is enabled */
NYX 0:85b3fd62ea1a 298 if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
NYX 0:85b3fd62ea1a 299 {
NYX 0:85b3fd62ea1a 300 tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5);
NYX 0:85b3fd62ea1a 301 }
NYX 0:85b3fd62ea1a 302 else
NYX 0:85b3fd62ea1a 303 {
NYX 0:85b3fd62ea1a 304 tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5);
NYX 0:85b3fd62ea1a 305 }
NYX 0:85b3fd62ea1a 306 }
NYX 0:85b3fd62ea1a 307 else
NYX 0:85b3fd62ea1a 308 {
NYX 0:85b3fd62ea1a 309 /* MCLK output is disabled */
NYX 0:85b3fd62ea1a 310 tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5);
NYX 0:85b3fd62ea1a 311 }
NYX 0:85b3fd62ea1a 312
NYX 0:85b3fd62ea1a 313 /* Remove the flatting point */
NYX 0:85b3fd62ea1a 314 tmp = tmp / 10U;
NYX 0:85b3fd62ea1a 315
NYX 0:85b3fd62ea1a 316 /* Check the parity of the divider */
NYX 0:85b3fd62ea1a 317 i2sodd = (uint16_t)(tmp & (uint16_t)1U);
NYX 0:85b3fd62ea1a 318
NYX 0:85b3fd62ea1a 319 /* Compute the i2sdiv prescaler */
NYX 0:85b3fd62ea1a 320 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
NYX 0:85b3fd62ea1a 321
NYX 0:85b3fd62ea1a 322 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
NYX 0:85b3fd62ea1a 323 i2sodd = (uint32_t) (i2sodd << 8U);
NYX 0:85b3fd62ea1a 324 }
NYX 0:85b3fd62ea1a 325
NYX 0:85b3fd62ea1a 326 /* Test if the divider is 1 or 0 or greater than 0xFF */
NYX 0:85b3fd62ea1a 327 if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
NYX 0:85b3fd62ea1a 328 {
NYX 0:85b3fd62ea1a 329 /* Set the default values */
NYX 0:85b3fd62ea1a 330 i2sdiv = 2U;
NYX 0:85b3fd62ea1a 331 i2sodd = 0U;
NYX 0:85b3fd62ea1a 332
NYX 0:85b3fd62ea1a 333 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 334 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
NYX 0:85b3fd62ea1a 335 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 336 return HAL_ERROR;
NYX 0:85b3fd62ea1a 337 }
NYX 0:85b3fd62ea1a 338
NYX 0:85b3fd62ea1a 339 /* Write to SPIx I2SPR register the computed value */
NYX 0:85b3fd62ea1a 340 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
NYX 0:85b3fd62ea1a 341
NYX 0:85b3fd62ea1a 342 /* Configure the I2S with the I2S_InitStruct values */
NYX 0:85b3fd62ea1a 343 tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
NYX 0:85b3fd62ea1a 344 (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
NYX 0:85b3fd62ea1a 345 (uint16_t)hi2s->Init.CPOL))));
NYX 0:85b3fd62ea1a 346
NYX 0:85b3fd62ea1a 347 #if defined(SPI_I2SCFGR_ASTRTEN)
NYX 0:85b3fd62ea1a 348 if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||(hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))
NYX 0:85b3fd62ea1a 349 {
NYX 0:85b3fd62ea1a 350 /* Write to SPIx I2SCFGR */
NYX 0:85b3fd62ea1a 351 WRITE_REG(hi2s->Instance->I2SCFGR,(tmpreg | SPI_I2SCFGR_ASTRTEN));
NYX 0:85b3fd62ea1a 352 }
NYX 0:85b3fd62ea1a 353 else
NYX 0:85b3fd62ea1a 354 {
NYX 0:85b3fd62ea1a 355 /* Write to SPIx I2SCFGR */
NYX 0:85b3fd62ea1a 356 WRITE_REG(hi2s->Instance->I2SCFGR,tmpreg);
NYX 0:85b3fd62ea1a 357 }
NYX 0:85b3fd62ea1a 358 #else
NYX 0:85b3fd62ea1a 359 /* Write to SPIx I2SCFGR */
NYX 0:85b3fd62ea1a 360 WRITE_REG(hi2s->Instance->I2SCFGR, tmpreg);
NYX 0:85b3fd62ea1a 361 #endif
NYX 0:85b3fd62ea1a 362
NYX 0:85b3fd62ea1a 363 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
NYX 0:85b3fd62ea1a 364
NYX 0:85b3fd62ea1a 365 /* Configure the I2S extended if the full duplex mode is enabled */
NYX 0:85b3fd62ea1a 366 assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
NYX 0:85b3fd62ea1a 367
NYX 0:85b3fd62ea1a 368 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
NYX 0:85b3fd62ea1a 369 {
NYX 0:85b3fd62ea1a 370 /* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */
NYX 0:85b3fd62ea1a 371 hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler;
NYX 0:85b3fd62ea1a 372
NYX 0:85b3fd62ea1a 373 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
NYX 0:85b3fd62ea1a 374 CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
NYX 0:85b3fd62ea1a 375 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
NYX 0:85b3fd62ea1a 376 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
NYX 0:85b3fd62ea1a 377 I2SxEXT(hi2s->Instance)->I2SPR = 2U;
NYX 0:85b3fd62ea1a 378
NYX 0:85b3fd62ea1a 379 /* Get the I2SCFGR register value */
NYX 0:85b3fd62ea1a 380 tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
NYX 0:85b3fd62ea1a 381
NYX 0:85b3fd62ea1a 382 /* Get the mode to be configured for the extended I2S */
NYX 0:85b3fd62ea1a 383 if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
NYX 0:85b3fd62ea1a 384 {
NYX 0:85b3fd62ea1a 385 tmp = I2S_MODE_SLAVE_RX;
NYX 0:85b3fd62ea1a 386 }
NYX 0:85b3fd62ea1a 387 else /* I2S_MODE_MASTER_RX || I2S_MODE_SLAVE_RX */
NYX 0:85b3fd62ea1a 388 {
NYX 0:85b3fd62ea1a 389 tmp = I2S_MODE_SLAVE_TX;
NYX 0:85b3fd62ea1a 390 }
NYX 0:85b3fd62ea1a 391
NYX 0:85b3fd62ea1a 392 /* Configure the I2S Slave with the I2S Master parameter values */
NYX 0:85b3fd62ea1a 393 tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
NYX 0:85b3fd62ea1a 394 (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
NYX 0:85b3fd62ea1a 395 (uint16_t)hi2s->Init.CPOL))));
NYX 0:85b3fd62ea1a 396
NYX 0:85b3fd62ea1a 397 /* Write to SPIx I2SCFGR */
NYX 0:85b3fd62ea1a 398 WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR,tmpreg);
NYX 0:85b3fd62ea1a 399 }
NYX 0:85b3fd62ea1a 400 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
NYX 0:85b3fd62ea1a 401
NYX 0:85b3fd62ea1a 402 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 403 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 404
NYX 0:85b3fd62ea1a 405 return HAL_OK;
NYX 0:85b3fd62ea1a 406 }
NYX 0:85b3fd62ea1a 407
NYX 0:85b3fd62ea1a 408 /**
NYX 0:85b3fd62ea1a 409 * @brief DeInitializes the I2S peripheral
NYX 0:85b3fd62ea1a 410 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 411 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 412 * @retval HAL status
NYX 0:85b3fd62ea1a 413 */
NYX 0:85b3fd62ea1a 414 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 415 {
NYX 0:85b3fd62ea1a 416 /* Check the I2S handle allocation */
NYX 0:85b3fd62ea1a 417 if(hi2s == NULL)
NYX 0:85b3fd62ea1a 418 {
NYX 0:85b3fd62ea1a 419 return HAL_ERROR;
NYX 0:85b3fd62ea1a 420 }
NYX 0:85b3fd62ea1a 421
NYX 0:85b3fd62ea1a 422 hi2s->State = HAL_I2S_STATE_BUSY;
NYX 0:85b3fd62ea1a 423
NYX 0:85b3fd62ea1a 424 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
NYX 0:85b3fd62ea1a 425 HAL_I2S_MspDeInit(hi2s);
NYX 0:85b3fd62ea1a 426
NYX 0:85b3fd62ea1a 427 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 428 hi2s->State = HAL_I2S_STATE_RESET;
NYX 0:85b3fd62ea1a 429
NYX 0:85b3fd62ea1a 430 /* Release Lock */
NYX 0:85b3fd62ea1a 431 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 432
NYX 0:85b3fd62ea1a 433 return HAL_OK;
NYX 0:85b3fd62ea1a 434 }
NYX 0:85b3fd62ea1a 435
NYX 0:85b3fd62ea1a 436 /**
NYX 0:85b3fd62ea1a 437 * @brief I2S MSP Init
NYX 0:85b3fd62ea1a 438 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 439 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 440 * @retval None
NYX 0:85b3fd62ea1a 441 */
NYX 0:85b3fd62ea1a 442 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 443 {
NYX 0:85b3fd62ea1a 444 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 445 UNUSED(hi2s);
NYX 0:85b3fd62ea1a 446 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 447 the HAL_I2S_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 448 */
NYX 0:85b3fd62ea1a 449 }
NYX 0:85b3fd62ea1a 450
NYX 0:85b3fd62ea1a 451 /**
NYX 0:85b3fd62ea1a 452 * @brief I2S MSP DeInit
NYX 0:85b3fd62ea1a 453 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 454 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 455 * @retval None
NYX 0:85b3fd62ea1a 456 */
NYX 0:85b3fd62ea1a 457 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 458 {
NYX 0:85b3fd62ea1a 459 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 460 UNUSED(hi2s);
NYX 0:85b3fd62ea1a 461 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 462 the HAL_I2S_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 463 */
NYX 0:85b3fd62ea1a 464 }
NYX 0:85b3fd62ea1a 465 /**
NYX 0:85b3fd62ea1a 466 * @}
NYX 0:85b3fd62ea1a 467 */
NYX 0:85b3fd62ea1a 468
NYX 0:85b3fd62ea1a 469 /** @addtogroup I2S_Exported_Functions_Group2
NYX 0:85b3fd62ea1a 470 * @brief Data transfers functions
NYX 0:85b3fd62ea1a 471 *
NYX 0:85b3fd62ea1a 472 @verbatim
NYX 0:85b3fd62ea1a 473 ===============================================================================
NYX 0:85b3fd62ea1a 474 ##### IO operation functions #####
NYX 0:85b3fd62ea1a 475 ===============================================================================
NYX 0:85b3fd62ea1a 476 [..]
NYX 0:85b3fd62ea1a 477 This subsection provides a set of functions allowing to manage the I2S data
NYX 0:85b3fd62ea1a 478 transfers.
NYX 0:85b3fd62ea1a 479
NYX 0:85b3fd62ea1a 480 (#) There are two modes of transfer:
NYX 0:85b3fd62ea1a 481 (++) Blocking mode : The communication is performed in the polling mode.
NYX 0:85b3fd62ea1a 482 The status of all data processing is returned by the same function
NYX 0:85b3fd62ea1a 483 after finishing transfer.
NYX 0:85b3fd62ea1a 484 (++) No-Blocking mode : The communication is performed using Interrupts
NYX 0:85b3fd62ea1a 485 or DMA. These functions return the status of the transfer startup.
NYX 0:85b3fd62ea1a 486 The end of the data processing will be indicated through the
NYX 0:85b3fd62ea1a 487 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
NYX 0:85b3fd62ea1a 488 using DMA mode.
NYX 0:85b3fd62ea1a 489
NYX 0:85b3fd62ea1a 490 (#) Blocking mode functions are :
NYX 0:85b3fd62ea1a 491 (++) HAL_I2S_Transmit()
NYX 0:85b3fd62ea1a 492 (++) HAL_I2S_Receive()
NYX 0:85b3fd62ea1a 493
NYX 0:85b3fd62ea1a 494 (#) No-Blocking mode functions with Interrupt are :
NYX 0:85b3fd62ea1a 495 (++) HAL_I2S_Transmit_IT()
NYX 0:85b3fd62ea1a 496 (++) HAL_I2S_Receive_IT()
NYX 0:85b3fd62ea1a 497
NYX 0:85b3fd62ea1a 498 (#) No-Blocking mode functions with DMA are :
NYX 0:85b3fd62ea1a 499 (++) HAL_I2S_Transmit_DMA()
NYX 0:85b3fd62ea1a 500 (++) HAL_I2S_Receive_DMA()
NYX 0:85b3fd62ea1a 501
NYX 0:85b3fd62ea1a 502 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
NYX 0:85b3fd62ea1a 503 (++) HAL_I2S_TxCpltCallback()
NYX 0:85b3fd62ea1a 504 (++) HAL_I2S_RxCpltCallback()
NYX 0:85b3fd62ea1a 505 (++) HAL_I2S_ErrorCallback()
NYX 0:85b3fd62ea1a 506
NYX 0:85b3fd62ea1a 507 @endverbatim
NYX 0:85b3fd62ea1a 508 * @{
NYX 0:85b3fd62ea1a 509 */
NYX 0:85b3fd62ea1a 510
NYX 0:85b3fd62ea1a 511 /**
NYX 0:85b3fd62ea1a 512 * @brief Transmit an amount of data in blocking mode
NYX 0:85b3fd62ea1a 513 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 514 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 515 * @param pData: a 16-bit pointer to data buffer.
NYX 0:85b3fd62ea1a 516 * @param Size: number of data sample to be sent:
NYX 0:85b3fd62ea1a 517 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
NYX 0:85b3fd62ea1a 518 * configuration phase, the Size parameter means the number of 16-bit data length
NYX 0:85b3fd62ea1a 519 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
NYX 0:85b3fd62ea1a 520 * the Size parameter means the number of 16-bit data length.
NYX 0:85b3fd62ea1a 521 * @param Timeout: Timeout duration
NYX 0:85b3fd62ea1a 522 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
NYX 0:85b3fd62ea1a 523 * between Master and Slave(example: audio streaming).
NYX 0:85b3fd62ea1a 524 * @retval HAL status
NYX 0:85b3fd62ea1a 525 */
NYX 0:85b3fd62ea1a 526 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
NYX 0:85b3fd62ea1a 527 {
NYX 0:85b3fd62ea1a 528 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 529
NYX 0:85b3fd62ea1a 530 if((pData == NULL ) || (Size == 0U))
NYX 0:85b3fd62ea1a 531 {
NYX 0:85b3fd62ea1a 532 return HAL_ERROR;
NYX 0:85b3fd62ea1a 533 }
NYX 0:85b3fd62ea1a 534
NYX 0:85b3fd62ea1a 535 if(hi2s->State == HAL_I2S_STATE_READY)
NYX 0:85b3fd62ea1a 536 {
NYX 0:85b3fd62ea1a 537 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
NYX 0:85b3fd62ea1a 540 {
NYX 0:85b3fd62ea1a 541 hi2s->TxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 542 hi2s->TxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 543 }
NYX 0:85b3fd62ea1a 544 else
NYX 0:85b3fd62ea1a 545 {
NYX 0:85b3fd62ea1a 546 hi2s->TxXferSize = Size;
NYX 0:85b3fd62ea1a 547 hi2s->TxXferCount = Size;
NYX 0:85b3fd62ea1a 548 }
NYX 0:85b3fd62ea1a 549
NYX 0:85b3fd62ea1a 550 /* Process Locked */
NYX 0:85b3fd62ea1a 551 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 552
NYX 0:85b3fd62ea1a 553 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 554 hi2s->State = HAL_I2S_STATE_BUSY_TX;
NYX 0:85b3fd62ea1a 555
NYX 0:85b3fd62ea1a 556 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 557 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 558 {
NYX 0:85b3fd62ea1a 559 /* Enable I2S peripheral */
NYX 0:85b3fd62ea1a 560 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 561 }
NYX 0:85b3fd62ea1a 562
NYX 0:85b3fd62ea1a 563 while(hi2s->TxXferCount > 0U)
NYX 0:85b3fd62ea1a 564 {
NYX 0:85b3fd62ea1a 565 hi2s->Instance->DR = (*pData++);
NYX 0:85b3fd62ea1a 566 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 567
NYX 0:85b3fd62ea1a 568 /* Wait until TXE flag is set */
NYX 0:85b3fd62ea1a 569 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
NYX 0:85b3fd62ea1a 570 {
NYX 0:85b3fd62ea1a 571 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 572 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
NYX 0:85b3fd62ea1a 573 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 574 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 575 }
NYX 0:85b3fd62ea1a 576
NYX 0:85b3fd62ea1a 577 /* Check if an underrun occurs */
NYX 0:85b3fd62ea1a 578 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
NYX 0:85b3fd62ea1a 579 {
NYX 0:85b3fd62ea1a 580 /* Clear underrun flag */
NYX 0:85b3fd62ea1a 581 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
NYX 0:85b3fd62ea1a 582 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 583 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 584
NYX 0:85b3fd62ea1a 585 /* Process Unlocked */
NYX 0:85b3fd62ea1a 586 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 587
NYX 0:85b3fd62ea1a 588 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 589 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
NYX 0:85b3fd62ea1a 590 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 591
NYX 0:85b3fd62ea1a 592 return HAL_ERROR;
NYX 0:85b3fd62ea1a 593 }
NYX 0:85b3fd62ea1a 594 }
NYX 0:85b3fd62ea1a 595 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 596
NYX 0:85b3fd62ea1a 597 /* Process Unlocked */
NYX 0:85b3fd62ea1a 598 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 599
NYX 0:85b3fd62ea1a 600 return HAL_OK;
NYX 0:85b3fd62ea1a 601 }
NYX 0:85b3fd62ea1a 602 else
NYX 0:85b3fd62ea1a 603 {
NYX 0:85b3fd62ea1a 604 return HAL_BUSY;
NYX 0:85b3fd62ea1a 605 }
NYX 0:85b3fd62ea1a 606 }
NYX 0:85b3fd62ea1a 607
NYX 0:85b3fd62ea1a 608 /**
NYX 0:85b3fd62ea1a 609 * @brief Receive an amount of data in blocking mode
NYX 0:85b3fd62ea1a 610 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 611 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 612 * @param pData: a 16-bit pointer to data buffer
NYX 0:85b3fd62ea1a 613 * @param Size: number of data sample to be sent:
NYX 0:85b3fd62ea1a 614 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
NYX 0:85b3fd62ea1a 615 * configuration phase, the Size parameter means the number of 16-bit data length
NYX 0:85b3fd62ea1a 616 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
NYX 0:85b3fd62ea1a 617 * the Size parameter means the number of 16-bit data length.
NYX 0:85b3fd62ea1a 618 * @param Timeout: Timeout duration
NYX 0:85b3fd62ea1a 619 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
NYX 0:85b3fd62ea1a 620 * between Master and Slave(example: audio streaming)
NYX 0:85b3fd62ea1a 621 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
NYX 0:85b3fd62ea1a 622 * in continuous way and as the I2S is not disabled at the end of the I2S transaction
NYX 0:85b3fd62ea1a 623 * @retval HAL status
NYX 0:85b3fd62ea1a 624 */
NYX 0:85b3fd62ea1a 625 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
NYX 0:85b3fd62ea1a 626 {
NYX 0:85b3fd62ea1a 627 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 628
NYX 0:85b3fd62ea1a 629 if((pData == NULL ) || (Size == 0U))
NYX 0:85b3fd62ea1a 630 {
NYX 0:85b3fd62ea1a 631 return HAL_ERROR;
NYX 0:85b3fd62ea1a 632 }
NYX 0:85b3fd62ea1a 633
NYX 0:85b3fd62ea1a 634 if(hi2s->State == HAL_I2S_STATE_READY)
NYX 0:85b3fd62ea1a 635 {
NYX 0:85b3fd62ea1a 636 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
NYX 0:85b3fd62ea1a 637 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
NYX 0:85b3fd62ea1a 638 {
NYX 0:85b3fd62ea1a 639 hi2s->RxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 640 hi2s->RxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 641 }
NYX 0:85b3fd62ea1a 642 else
NYX 0:85b3fd62ea1a 643 {
NYX 0:85b3fd62ea1a 644 hi2s->RxXferSize = Size;
NYX 0:85b3fd62ea1a 645 hi2s->RxXferCount = Size;
NYX 0:85b3fd62ea1a 646 }
NYX 0:85b3fd62ea1a 647 /* Process Locked */
NYX 0:85b3fd62ea1a 648 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 649
NYX 0:85b3fd62ea1a 650 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 651 hi2s->State = HAL_I2S_STATE_BUSY_RX;
NYX 0:85b3fd62ea1a 652
NYX 0:85b3fd62ea1a 653 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 654 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 655 {
NYX 0:85b3fd62ea1a 656 /* Enable I2S peripheral */
NYX 0:85b3fd62ea1a 657 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 658 }
NYX 0:85b3fd62ea1a 659
NYX 0:85b3fd62ea1a 660 /* Check if Master Receiver mode is selected */
NYX 0:85b3fd62ea1a 661 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
NYX 0:85b3fd62ea1a 662 {
NYX 0:85b3fd62ea1a 663 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
NYX 0:85b3fd62ea1a 664 access to the SPI_SR register. */
NYX 0:85b3fd62ea1a 665 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 666 }
NYX 0:85b3fd62ea1a 667
NYX 0:85b3fd62ea1a 668 /* Receive data */
NYX 0:85b3fd62ea1a 669 while(hi2s->RxXferCount > 0U)
NYX 0:85b3fd62ea1a 670 {
NYX 0:85b3fd62ea1a 671 /* Wait until RXNE flag is set */
NYX 0:85b3fd62ea1a 672 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
NYX 0:85b3fd62ea1a 673 {
NYX 0:85b3fd62ea1a 674 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 675 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
NYX 0:85b3fd62ea1a 676 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 677 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 678 }
NYX 0:85b3fd62ea1a 679
NYX 0:85b3fd62ea1a 680 /* Check if an overrun occurs */
NYX 0:85b3fd62ea1a 681 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
NYX 0:85b3fd62ea1a 682 {
NYX 0:85b3fd62ea1a 683 /* Clear overrun flag */
NYX 0:85b3fd62ea1a 684 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 685
NYX 0:85b3fd62ea1a 686 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 687 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 688
NYX 0:85b3fd62ea1a 689 /* Process Unlocked */
NYX 0:85b3fd62ea1a 690 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 691
NYX 0:85b3fd62ea1a 692 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 693 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
NYX 0:85b3fd62ea1a 694 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 695
NYX 0:85b3fd62ea1a 696 return HAL_ERROR;
NYX 0:85b3fd62ea1a 697 }
NYX 0:85b3fd62ea1a 698
NYX 0:85b3fd62ea1a 699 (*pData++) = hi2s->Instance->DR;
NYX 0:85b3fd62ea1a 700 hi2s->RxXferCount--;
NYX 0:85b3fd62ea1a 701 }
NYX 0:85b3fd62ea1a 702
NYX 0:85b3fd62ea1a 703 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 704
NYX 0:85b3fd62ea1a 705 /* Process Unlocked */
NYX 0:85b3fd62ea1a 706 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 707
NYX 0:85b3fd62ea1a 708 return HAL_OK;
NYX 0:85b3fd62ea1a 709 }
NYX 0:85b3fd62ea1a 710 else
NYX 0:85b3fd62ea1a 711 {
NYX 0:85b3fd62ea1a 712 return HAL_BUSY;
NYX 0:85b3fd62ea1a 713 }
NYX 0:85b3fd62ea1a 714 }
NYX 0:85b3fd62ea1a 715
NYX 0:85b3fd62ea1a 716 /**
NYX 0:85b3fd62ea1a 717 * @brief Transmit an amount of data in non-blocking mode with Interrupt
NYX 0:85b3fd62ea1a 718 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 719 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 720 * @param pData: a 16-bit pointer to data buffer.
NYX 0:85b3fd62ea1a 721 * @param Size: number of data sample to be sent:
NYX 0:85b3fd62ea1a 722 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
NYX 0:85b3fd62ea1a 723 * configuration phase, the Size parameter means the number of 16-bit data length
NYX 0:85b3fd62ea1a 724 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
NYX 0:85b3fd62ea1a 725 * the Size parameter means the number of 16-bit data length.
NYX 0:85b3fd62ea1a 726 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
NYX 0:85b3fd62ea1a 727 * between Master and Slave(example: audio streaming).
NYX 0:85b3fd62ea1a 728 * @retval HAL status
NYX 0:85b3fd62ea1a 729 */
NYX 0:85b3fd62ea1a 730 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
NYX 0:85b3fd62ea1a 731 {
NYX 0:85b3fd62ea1a 732 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 733
NYX 0:85b3fd62ea1a 734 if(hi2s->State == HAL_I2S_STATE_READY)
NYX 0:85b3fd62ea1a 735 {
NYX 0:85b3fd62ea1a 736 if((pData == NULL) || (Size == 0U))
NYX 0:85b3fd62ea1a 737 {
NYX 0:85b3fd62ea1a 738 return HAL_ERROR;
NYX 0:85b3fd62ea1a 739 }
NYX 0:85b3fd62ea1a 740
NYX 0:85b3fd62ea1a 741 hi2s->pTxBuffPtr = pData;
NYX 0:85b3fd62ea1a 742 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
NYX 0:85b3fd62ea1a 743 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
NYX 0:85b3fd62ea1a 744 {
NYX 0:85b3fd62ea1a 745 hi2s->TxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 746 hi2s->TxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 747 }
NYX 0:85b3fd62ea1a 748 else
NYX 0:85b3fd62ea1a 749 {
NYX 0:85b3fd62ea1a 750 hi2s->TxXferSize = Size;
NYX 0:85b3fd62ea1a 751 hi2s->TxXferCount = Size;
NYX 0:85b3fd62ea1a 752 }
NYX 0:85b3fd62ea1a 753
NYX 0:85b3fd62ea1a 754 /* Process Locked */
NYX 0:85b3fd62ea1a 755 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 756
NYX 0:85b3fd62ea1a 757 hi2s->State = HAL_I2S_STATE_BUSY_TX;
NYX 0:85b3fd62ea1a 758 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 759
NYX 0:85b3fd62ea1a 760 /* Enable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 761 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 762
NYX 0:85b3fd62ea1a 763 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 764 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 765 {
NYX 0:85b3fd62ea1a 766 /* Enable I2S peripheral */
NYX 0:85b3fd62ea1a 767 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 768 }
NYX 0:85b3fd62ea1a 769
NYX 0:85b3fd62ea1a 770 /* Process Unlocked */
NYX 0:85b3fd62ea1a 771 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 772
NYX 0:85b3fd62ea1a 773 return HAL_OK;
NYX 0:85b3fd62ea1a 774 }
NYX 0:85b3fd62ea1a 775 else
NYX 0:85b3fd62ea1a 776 {
NYX 0:85b3fd62ea1a 777 return HAL_BUSY;
NYX 0:85b3fd62ea1a 778 }
NYX 0:85b3fd62ea1a 779 }
NYX 0:85b3fd62ea1a 780
NYX 0:85b3fd62ea1a 781 /**
NYX 0:85b3fd62ea1a 782 * @brief Receive an amount of data in non-blocking mode with Interrupt
NYX 0:85b3fd62ea1a 783 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 784 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 785 * @param pData: a 16-bit pointer to the Receive data buffer.
NYX 0:85b3fd62ea1a 786 * @param Size: number of data sample to be sent:
NYX 0:85b3fd62ea1a 787 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
NYX 0:85b3fd62ea1a 788 * configuration phase, the Size parameter means the number of 16-bit data length
NYX 0:85b3fd62ea1a 789 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
NYX 0:85b3fd62ea1a 790 * the Size parameter means the number of 16-bit data length.
NYX 0:85b3fd62ea1a 791 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
NYX 0:85b3fd62ea1a 792 * between Master and Slave(example: audio streaming).
NYX 0:85b3fd62ea1a 793 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
NYX 0:85b3fd62ea1a 794 * between Master and Slave otherwise the I2S interrupt should be optimized.
NYX 0:85b3fd62ea1a 795 * @retval HAL status
NYX 0:85b3fd62ea1a 796 */
NYX 0:85b3fd62ea1a 797 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
NYX 0:85b3fd62ea1a 798 {
NYX 0:85b3fd62ea1a 799 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 800
NYX 0:85b3fd62ea1a 801 if(hi2s->State == HAL_I2S_STATE_READY)
NYX 0:85b3fd62ea1a 802 {
NYX 0:85b3fd62ea1a 803 if((pData == NULL) || (Size == 0U))
NYX 0:85b3fd62ea1a 804 {
NYX 0:85b3fd62ea1a 805 return HAL_ERROR;
NYX 0:85b3fd62ea1a 806 }
NYX 0:85b3fd62ea1a 807
NYX 0:85b3fd62ea1a 808 hi2s->pRxBuffPtr = pData;
NYX 0:85b3fd62ea1a 809 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
NYX 0:85b3fd62ea1a 810 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
NYX 0:85b3fd62ea1a 811 {
NYX 0:85b3fd62ea1a 812 hi2s->RxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 813 hi2s->RxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 814 }
NYX 0:85b3fd62ea1a 815 else
NYX 0:85b3fd62ea1a 816 {
NYX 0:85b3fd62ea1a 817 hi2s->RxXferSize = Size;
NYX 0:85b3fd62ea1a 818 hi2s->RxXferCount = Size;
NYX 0:85b3fd62ea1a 819 }
NYX 0:85b3fd62ea1a 820 /* Process Locked */
NYX 0:85b3fd62ea1a 821 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 822
NYX 0:85b3fd62ea1a 823 hi2s->State = HAL_I2S_STATE_BUSY_RX;
NYX 0:85b3fd62ea1a 824 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 825
NYX 0:85b3fd62ea1a 826 /* Enable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 827 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 828
NYX 0:85b3fd62ea1a 829 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 830 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 831 {
NYX 0:85b3fd62ea1a 832 /* Enable I2S peripheral */
NYX 0:85b3fd62ea1a 833 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 834 }
NYX 0:85b3fd62ea1a 835
NYX 0:85b3fd62ea1a 836 /* Process Unlocked */
NYX 0:85b3fd62ea1a 837 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 838
NYX 0:85b3fd62ea1a 839 return HAL_OK;
NYX 0:85b3fd62ea1a 840 }
NYX 0:85b3fd62ea1a 841
NYX 0:85b3fd62ea1a 842 else
NYX 0:85b3fd62ea1a 843 {
NYX 0:85b3fd62ea1a 844 return HAL_BUSY;
NYX 0:85b3fd62ea1a 845 }
NYX 0:85b3fd62ea1a 846 }
NYX 0:85b3fd62ea1a 847
NYX 0:85b3fd62ea1a 848 /**
NYX 0:85b3fd62ea1a 849 * @brief Transmit an amount of data in non-blocking mode with DMA
NYX 0:85b3fd62ea1a 850 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 851 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 852 * @param pData: a 16-bit pointer to the Transmit data buffer.
NYX 0:85b3fd62ea1a 853 * @param Size: number of data sample to be sent:
NYX 0:85b3fd62ea1a 854 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
NYX 0:85b3fd62ea1a 855 * configuration phase, the Size parameter means the number of 16-bit data length
NYX 0:85b3fd62ea1a 856 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
NYX 0:85b3fd62ea1a 857 * the Size parameter means the number of 16-bit data length.
NYX 0:85b3fd62ea1a 858 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
NYX 0:85b3fd62ea1a 859 * between Master and Slave(example: audio streaming).
NYX 0:85b3fd62ea1a 860 * @retval HAL status
NYX 0:85b3fd62ea1a 861 */
NYX 0:85b3fd62ea1a 862 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
NYX 0:85b3fd62ea1a 863 {
NYX 0:85b3fd62ea1a 864 uint32_t *tmp = NULL;
NYX 0:85b3fd62ea1a 865 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 866
NYX 0:85b3fd62ea1a 867 if((pData == NULL) || (Size == 0U))
NYX 0:85b3fd62ea1a 868 {
NYX 0:85b3fd62ea1a 869 return HAL_ERROR;
NYX 0:85b3fd62ea1a 870 }
NYX 0:85b3fd62ea1a 871
NYX 0:85b3fd62ea1a 872 if(hi2s->State == HAL_I2S_STATE_READY)
NYX 0:85b3fd62ea1a 873 {
NYX 0:85b3fd62ea1a 874 hi2s->pTxBuffPtr = pData;
NYX 0:85b3fd62ea1a 875 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
NYX 0:85b3fd62ea1a 876 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
NYX 0:85b3fd62ea1a 877 {
NYX 0:85b3fd62ea1a 878 hi2s->TxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 879 hi2s->TxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 880 }
NYX 0:85b3fd62ea1a 881 else
NYX 0:85b3fd62ea1a 882 {
NYX 0:85b3fd62ea1a 883 hi2s->TxXferSize = Size;
NYX 0:85b3fd62ea1a 884 hi2s->TxXferCount = Size;
NYX 0:85b3fd62ea1a 885 }
NYX 0:85b3fd62ea1a 886
NYX 0:85b3fd62ea1a 887 /* Process Locked */
NYX 0:85b3fd62ea1a 888 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 889
NYX 0:85b3fd62ea1a 890 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 891 hi2s->State = HAL_I2S_STATE_BUSY_TX;
NYX 0:85b3fd62ea1a 892
NYX 0:85b3fd62ea1a 893 /* Set the I2S Tx DMA Half transfer complete callback */
NYX 0:85b3fd62ea1a 894 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
NYX 0:85b3fd62ea1a 895
NYX 0:85b3fd62ea1a 896 /* Set the I2S Tx DMA transfer complete callback */
NYX 0:85b3fd62ea1a 897 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
NYX 0:85b3fd62ea1a 898
NYX 0:85b3fd62ea1a 899 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 900 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
NYX 0:85b3fd62ea1a 901
NYX 0:85b3fd62ea1a 902 /* Enable the Tx DMA Stream */
NYX 0:85b3fd62ea1a 903 tmp = (uint32_t*)&pData;
NYX 0:85b3fd62ea1a 904 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
NYX 0:85b3fd62ea1a 905
NYX 0:85b3fd62ea1a 906 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 907 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 908 {
NYX 0:85b3fd62ea1a 909 /* Enable I2S peripheral */
NYX 0:85b3fd62ea1a 910 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 911 }
NYX 0:85b3fd62ea1a 912
NYX 0:85b3fd62ea1a 913 /* Check if the I2S Tx request is already enabled */
NYX 0:85b3fd62ea1a 914 if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
NYX 0:85b3fd62ea1a 915 {
NYX 0:85b3fd62ea1a 916 /* Enable Tx DMA Request */
NYX 0:85b3fd62ea1a 917 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 918 }
NYX 0:85b3fd62ea1a 919
NYX 0:85b3fd62ea1a 920 /* Process Unlocked */
NYX 0:85b3fd62ea1a 921 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 922
NYX 0:85b3fd62ea1a 923 return HAL_OK;
NYX 0:85b3fd62ea1a 924 }
NYX 0:85b3fd62ea1a 925 else
NYX 0:85b3fd62ea1a 926 {
NYX 0:85b3fd62ea1a 927 return HAL_BUSY;
NYX 0:85b3fd62ea1a 928 }
NYX 0:85b3fd62ea1a 929 }
NYX 0:85b3fd62ea1a 930
NYX 0:85b3fd62ea1a 931 /**
NYX 0:85b3fd62ea1a 932 * @brief Receive an amount of data in non-blocking mode with DMA
NYX 0:85b3fd62ea1a 933 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 934 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 935 * @param pData: a 16-bit pointer to the Receive data buffer.
NYX 0:85b3fd62ea1a 936 * @param Size: number of data sample to be sent:
NYX 0:85b3fd62ea1a 937 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
NYX 0:85b3fd62ea1a 938 * configuration phase, the Size parameter means the number of 16-bit data length
NYX 0:85b3fd62ea1a 939 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
NYX 0:85b3fd62ea1a 940 * the Size parameter means the number of 16-bit data length.
NYX 0:85b3fd62ea1a 941 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
NYX 0:85b3fd62ea1a 942 * between Master and Slave(example: audio streaming).
NYX 0:85b3fd62ea1a 943 * @retval HAL status
NYX 0:85b3fd62ea1a 944 */
NYX 0:85b3fd62ea1a 945 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
NYX 0:85b3fd62ea1a 946 {
NYX 0:85b3fd62ea1a 947 uint32_t *tmp = NULL;
NYX 0:85b3fd62ea1a 948 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 949
NYX 0:85b3fd62ea1a 950 if((pData == NULL) || (Size == 0U))
NYX 0:85b3fd62ea1a 951 {
NYX 0:85b3fd62ea1a 952 return HAL_ERROR;
NYX 0:85b3fd62ea1a 953 }
NYX 0:85b3fd62ea1a 954
NYX 0:85b3fd62ea1a 955 if(hi2s->State == HAL_I2S_STATE_READY)
NYX 0:85b3fd62ea1a 956 {
NYX 0:85b3fd62ea1a 957 hi2s->pRxBuffPtr = pData;
NYX 0:85b3fd62ea1a 958 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
NYX 0:85b3fd62ea1a 959 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
NYX 0:85b3fd62ea1a 960 {
NYX 0:85b3fd62ea1a 961 hi2s->RxXferSize = (Size << 1U);
NYX 0:85b3fd62ea1a 962 hi2s->RxXferCount = (Size << 1U);
NYX 0:85b3fd62ea1a 963 }
NYX 0:85b3fd62ea1a 964 else
NYX 0:85b3fd62ea1a 965 {
NYX 0:85b3fd62ea1a 966 hi2s->RxXferSize = Size;
NYX 0:85b3fd62ea1a 967 hi2s->RxXferCount = Size;
NYX 0:85b3fd62ea1a 968 }
NYX 0:85b3fd62ea1a 969 /* Process Locked */
NYX 0:85b3fd62ea1a 970 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 971
NYX 0:85b3fd62ea1a 972 hi2s->State = HAL_I2S_STATE_BUSY_RX;
NYX 0:85b3fd62ea1a 973 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
NYX 0:85b3fd62ea1a 974
NYX 0:85b3fd62ea1a 975 /* Set the I2S Rx DMA Half transfer complete callback */
NYX 0:85b3fd62ea1a 976 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
NYX 0:85b3fd62ea1a 977
NYX 0:85b3fd62ea1a 978 /* Set the I2S Rx DMA transfer complete callback */
NYX 0:85b3fd62ea1a 979 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
NYX 0:85b3fd62ea1a 980
NYX 0:85b3fd62ea1a 981 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 982 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
NYX 0:85b3fd62ea1a 983
NYX 0:85b3fd62ea1a 984 /* Check if Master Receiver mode is selected */
NYX 0:85b3fd62ea1a 985 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
NYX 0:85b3fd62ea1a 986 {
NYX 0:85b3fd62ea1a 987 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
NYX 0:85b3fd62ea1a 988 access to the SPI_SR register. */
NYX 0:85b3fd62ea1a 989 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 990 }
NYX 0:85b3fd62ea1a 991
NYX 0:85b3fd62ea1a 992 /* Enable the Rx DMA Stream */
NYX 0:85b3fd62ea1a 993 tmp = (uint32_t*)&pData;
NYX 0:85b3fd62ea1a 994 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
NYX 0:85b3fd62ea1a 995
NYX 0:85b3fd62ea1a 996 /* Check if the I2S is already enabled */
NYX 0:85b3fd62ea1a 997 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
NYX 0:85b3fd62ea1a 998 {
NYX 0:85b3fd62ea1a 999 /* Enable I2S peripheral */
NYX 0:85b3fd62ea1a 1000 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 1001 }
NYX 0:85b3fd62ea1a 1002
NYX 0:85b3fd62ea1a 1003 /* Check if the I2S Rx request is already enabled */
NYX 0:85b3fd62ea1a 1004 if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
NYX 0:85b3fd62ea1a 1005 {
NYX 0:85b3fd62ea1a 1006 /* Enable Rx DMA Request */
NYX 0:85b3fd62ea1a 1007 SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 1008 }
NYX 0:85b3fd62ea1a 1009
NYX 0:85b3fd62ea1a 1010 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1011 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 1012
NYX 0:85b3fd62ea1a 1013 return HAL_OK;
NYX 0:85b3fd62ea1a 1014 }
NYX 0:85b3fd62ea1a 1015 else
NYX 0:85b3fd62ea1a 1016 {
NYX 0:85b3fd62ea1a 1017 return HAL_BUSY;
NYX 0:85b3fd62ea1a 1018 }
NYX 0:85b3fd62ea1a 1019 }
NYX 0:85b3fd62ea1a 1020
NYX 0:85b3fd62ea1a 1021 /**
NYX 0:85b3fd62ea1a 1022 * @brief Pauses the audio stream playing from the Media.
NYX 0:85b3fd62ea1a 1023 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1024 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1025 * @retval HAL status
NYX 0:85b3fd62ea1a 1026 */
NYX 0:85b3fd62ea1a 1027 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1028 {
NYX 0:85b3fd62ea1a 1029 /* Process Locked */
NYX 0:85b3fd62ea1a 1030 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 1031
NYX 0:85b3fd62ea1a 1032 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
NYX 0:85b3fd62ea1a 1033 {
NYX 0:85b3fd62ea1a 1034 /* Disable the I2S DMA Tx request */
NYX 0:85b3fd62ea1a 1035 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 1036 }
NYX 0:85b3fd62ea1a 1037 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
NYX 0:85b3fd62ea1a 1038 {
NYX 0:85b3fd62ea1a 1039 /* Disable the I2S DMA Rx request */
NYX 0:85b3fd62ea1a 1040 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 1041 }
NYX 0:85b3fd62ea1a 1042 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
NYX 0:85b3fd62ea1a 1043 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
NYX 0:85b3fd62ea1a 1044 {
NYX 0:85b3fd62ea1a 1045 /* Pause the audio file playing by disabling the I2S DMA request */
NYX 0:85b3fd62ea1a 1046 CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_TXDMAEN|SPI_CR2_RXDMAEN));
NYX 0:85b3fd62ea1a 1047 CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_TXDMAEN|SPI_CR2_RXDMAEN));
NYX 0:85b3fd62ea1a 1048 }
NYX 0:85b3fd62ea1a 1049 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
NYX 0:85b3fd62ea1a 1050
NYX 0:85b3fd62ea1a 1051 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1052 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 1053
NYX 0:85b3fd62ea1a 1054 return HAL_OK;
NYX 0:85b3fd62ea1a 1055 }
NYX 0:85b3fd62ea1a 1056
NYX 0:85b3fd62ea1a 1057 /**
NYX 0:85b3fd62ea1a 1058 * @brief Resumes the audio stream playing from the Media.
NYX 0:85b3fd62ea1a 1059 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1060 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1061 * @retval HAL status
NYX 0:85b3fd62ea1a 1062 */
NYX 0:85b3fd62ea1a 1063 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1064 {
NYX 0:85b3fd62ea1a 1065 /* Process Locked */
NYX 0:85b3fd62ea1a 1066 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 1067
NYX 0:85b3fd62ea1a 1068 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
NYX 0:85b3fd62ea1a 1069 {
NYX 0:85b3fd62ea1a 1070 /* Enable the I2S DMA Tx request */
NYX 0:85b3fd62ea1a 1071 SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 1072 }
NYX 0:85b3fd62ea1a 1073 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
NYX 0:85b3fd62ea1a 1074 {
NYX 0:85b3fd62ea1a 1075 /* Enable the I2S DMA Rx request */
NYX 0:85b3fd62ea1a 1076 SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 1077 }
NYX 0:85b3fd62ea1a 1078 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
NYX 0:85b3fd62ea1a 1079 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
NYX 0:85b3fd62ea1a 1080 {
NYX 0:85b3fd62ea1a 1081 /* Pause the audio file playing by disabling the I2S DMA request */
NYX 0:85b3fd62ea1a 1082 SET_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
NYX 0:85b3fd62ea1a 1083 SET_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
NYX 0:85b3fd62ea1a 1084
NYX 0:85b3fd62ea1a 1085 /* If the I2Sext peripheral is still not enabled, enable it */
NYX 0:85b3fd62ea1a 1086 if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
NYX 0:85b3fd62ea1a 1087 {
NYX 0:85b3fd62ea1a 1088 /* Enable I2Sext peripheral */
NYX 0:85b3fd62ea1a 1089 __HAL_I2SEXT_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 1090 }
NYX 0:85b3fd62ea1a 1091 }
NYX 0:85b3fd62ea1a 1092 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
NYX 0:85b3fd62ea1a 1093
NYX 0:85b3fd62ea1a 1094 /* If the I2S peripheral is still not enabled, enable it */
NYX 0:85b3fd62ea1a 1095 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
NYX 0:85b3fd62ea1a 1096 {
NYX 0:85b3fd62ea1a 1097 /* Enable I2S peripheral */
NYX 0:85b3fd62ea1a 1098 __HAL_I2S_ENABLE(hi2s);
NYX 0:85b3fd62ea1a 1099 }
NYX 0:85b3fd62ea1a 1100
NYX 0:85b3fd62ea1a 1101 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1102 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 1103
NYX 0:85b3fd62ea1a 1104 return HAL_OK;
NYX 0:85b3fd62ea1a 1105 }
NYX 0:85b3fd62ea1a 1106
NYX 0:85b3fd62ea1a 1107 /**
NYX 0:85b3fd62ea1a 1108 * @brief Resumes the audio stream playing from the Media.
NYX 0:85b3fd62ea1a 1109 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1110 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1111 * @retval HAL status
NYX 0:85b3fd62ea1a 1112 */
NYX 0:85b3fd62ea1a 1113 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1114 {
NYX 0:85b3fd62ea1a 1115 /* Process Locked */
NYX 0:85b3fd62ea1a 1116 __HAL_LOCK(hi2s);
NYX 0:85b3fd62ea1a 1117
NYX 0:85b3fd62ea1a 1118 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
NYX 0:85b3fd62ea1a 1119 {
NYX 0:85b3fd62ea1a 1120 /* Disable the I2S DMA requests */
NYX 0:85b3fd62ea1a 1121 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 1122
NYX 0:85b3fd62ea1a 1123 /* Disable the I2S DMA Channel */
NYX 0:85b3fd62ea1a 1124 HAL_DMA_Abort(hi2s->hdmatx);
NYX 0:85b3fd62ea1a 1125 }
NYX 0:85b3fd62ea1a 1126 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
NYX 0:85b3fd62ea1a 1127 {
NYX 0:85b3fd62ea1a 1128 /* Disable the I2S DMA requests */
NYX 0:85b3fd62ea1a 1129 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 1130
NYX 0:85b3fd62ea1a 1131 /* Disable the I2S DMA Channel */
NYX 0:85b3fd62ea1a 1132 HAL_DMA_Abort(hi2s->hdmarx);
NYX 0:85b3fd62ea1a 1133 }
NYX 0:85b3fd62ea1a 1134 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
NYX 0:85b3fd62ea1a 1135 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
NYX 0:85b3fd62ea1a 1136 {
NYX 0:85b3fd62ea1a 1137 /* Disable the I2S DMA requests */
NYX 0:85b3fd62ea1a 1138 CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
NYX 0:85b3fd62ea1a 1139 CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
NYX 0:85b3fd62ea1a 1140
NYX 0:85b3fd62ea1a 1141 /* Disable the I2S DMA Channels */
NYX 0:85b3fd62ea1a 1142 HAL_DMA_Abort(hi2s->hdmatx);
NYX 0:85b3fd62ea1a 1143 HAL_DMA_Abort(hi2s->hdmarx);
NYX 0:85b3fd62ea1a 1144
NYX 0:85b3fd62ea1a 1145 /* Disable I2Sext peripheral */
NYX 0:85b3fd62ea1a 1146 __HAL_I2SEXT_DISABLE(hi2s);
NYX 0:85b3fd62ea1a 1147 }
NYX 0:85b3fd62ea1a 1148 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
NYX 0:85b3fd62ea1a 1149
NYX 0:85b3fd62ea1a 1150 /* Disable I2S peripheral */
NYX 0:85b3fd62ea1a 1151 __HAL_I2S_DISABLE(hi2s);
NYX 0:85b3fd62ea1a 1152
NYX 0:85b3fd62ea1a 1153 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1154
NYX 0:85b3fd62ea1a 1155 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1156 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 1157
NYX 0:85b3fd62ea1a 1158 return HAL_OK;
NYX 0:85b3fd62ea1a 1159 }
NYX 0:85b3fd62ea1a 1160
NYX 0:85b3fd62ea1a 1161 /**
NYX 0:85b3fd62ea1a 1162 * @brief This function handles I2S interrupt request.
NYX 0:85b3fd62ea1a 1163 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1164 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1165 * @retval None
NYX 0:85b3fd62ea1a 1166 */
NYX 0:85b3fd62ea1a 1167 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1168 {
NYX 0:85b3fd62ea1a 1169 /* Call the IrqHandler ISR set during HAL_I2S_INIT */
NYX 0:85b3fd62ea1a 1170 hi2s->IrqHandlerISR(hi2s);
NYX 0:85b3fd62ea1a 1171 }
NYX 0:85b3fd62ea1a 1172
NYX 0:85b3fd62ea1a 1173 /**
NYX 0:85b3fd62ea1a 1174 * @brief Tx Transfer Half completed callbacks
NYX 0:85b3fd62ea1a 1175 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1176 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1177 * @retval None
NYX 0:85b3fd62ea1a 1178 */
NYX 0:85b3fd62ea1a 1179 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1180 {
NYX 0:85b3fd62ea1a 1181 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1182 UNUSED(hi2s);
NYX 0:85b3fd62ea1a 1183 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1184 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 1185 */
NYX 0:85b3fd62ea1a 1186 }
NYX 0:85b3fd62ea1a 1187
NYX 0:85b3fd62ea1a 1188 /**
NYX 0:85b3fd62ea1a 1189 * @brief Tx Transfer completed callbacks
NYX 0:85b3fd62ea1a 1190 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1191 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1192 * @retval None
NYX 0:85b3fd62ea1a 1193 */
NYX 0:85b3fd62ea1a 1194 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1195 {
NYX 0:85b3fd62ea1a 1196 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1197 UNUSED(hi2s);
NYX 0:85b3fd62ea1a 1198 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1199 the HAL_I2S_TxCpltCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 1200 */
NYX 0:85b3fd62ea1a 1201 }
NYX 0:85b3fd62ea1a 1202
NYX 0:85b3fd62ea1a 1203 /**
NYX 0:85b3fd62ea1a 1204 * @brief Rx Transfer half completed callbacks
NYX 0:85b3fd62ea1a 1205 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1206 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1207 * @retval None
NYX 0:85b3fd62ea1a 1208 */
NYX 0:85b3fd62ea1a 1209 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1210 {
NYX 0:85b3fd62ea1a 1211 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1212 UNUSED(hi2s);
NYX 0:85b3fd62ea1a 1213 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1214 the HAL_I2S_RxCpltCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 1215 */
NYX 0:85b3fd62ea1a 1216 }
NYX 0:85b3fd62ea1a 1217
NYX 0:85b3fd62ea1a 1218 /**
NYX 0:85b3fd62ea1a 1219 * @brief Rx Transfer completed callbacks
NYX 0:85b3fd62ea1a 1220 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1221 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1222 * @retval None
NYX 0:85b3fd62ea1a 1223 */
NYX 0:85b3fd62ea1a 1224 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1225 {
NYX 0:85b3fd62ea1a 1226 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1227 UNUSED(hi2s);
NYX 0:85b3fd62ea1a 1228 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1229 the HAL_I2S_RxCpltCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 1230 */
NYX 0:85b3fd62ea1a 1231 }
NYX 0:85b3fd62ea1a 1232
NYX 0:85b3fd62ea1a 1233 /**
NYX 0:85b3fd62ea1a 1234 * @brief I2S error callbacks
NYX 0:85b3fd62ea1a 1235 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1236 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1237 * @retval None
NYX 0:85b3fd62ea1a 1238 */
NYX 0:85b3fd62ea1a 1239 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1240 {
NYX 0:85b3fd62ea1a 1241 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1242 UNUSED(hi2s);
NYX 0:85b3fd62ea1a 1243 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1244 the HAL_I2S_ErrorCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 1245 */
NYX 0:85b3fd62ea1a 1246 }
NYX 0:85b3fd62ea1a 1247
NYX 0:85b3fd62ea1a 1248 /**
NYX 0:85b3fd62ea1a 1249 * @}
NYX 0:85b3fd62ea1a 1250 */
NYX 0:85b3fd62ea1a 1251
NYX 0:85b3fd62ea1a 1252 /** @addtogroup I2S_Exported_Functions_Group3
NYX 0:85b3fd62ea1a 1253 * @brief Peripheral State functions
NYX 0:85b3fd62ea1a 1254 *
NYX 0:85b3fd62ea1a 1255 @verbatim
NYX 0:85b3fd62ea1a 1256 ===============================================================================
NYX 0:85b3fd62ea1a 1257 ##### Peripheral State and Errors functions #####
NYX 0:85b3fd62ea1a 1258 ===============================================================================
NYX 0:85b3fd62ea1a 1259 [..]
NYX 0:85b3fd62ea1a 1260 This subsection permits to get in run-time the status of the peripheral
NYX 0:85b3fd62ea1a 1261 and the data flow.
NYX 0:85b3fd62ea1a 1262
NYX 0:85b3fd62ea1a 1263 @endverbatim
NYX 0:85b3fd62ea1a 1264 * @{
NYX 0:85b3fd62ea1a 1265 */
NYX 0:85b3fd62ea1a 1266
NYX 0:85b3fd62ea1a 1267 /**
NYX 0:85b3fd62ea1a 1268 * @brief Return the I2S state
NYX 0:85b3fd62ea1a 1269 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1270 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1271 * @retval HAL state
NYX 0:85b3fd62ea1a 1272 */
NYX 0:85b3fd62ea1a 1273 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1274 {
NYX 0:85b3fd62ea1a 1275 return hi2s->State;
NYX 0:85b3fd62ea1a 1276 }
NYX 0:85b3fd62ea1a 1277
NYX 0:85b3fd62ea1a 1278 /**
NYX 0:85b3fd62ea1a 1279 * @brief Return the I2S error code
NYX 0:85b3fd62ea1a 1280 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1281 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1282 * @retval I2S Error Code
NYX 0:85b3fd62ea1a 1283 */
NYX 0:85b3fd62ea1a 1284 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1285 {
NYX 0:85b3fd62ea1a 1286 return hi2s->ErrorCode;
NYX 0:85b3fd62ea1a 1287 }
NYX 0:85b3fd62ea1a 1288 /**
NYX 0:85b3fd62ea1a 1289 * @}
NYX 0:85b3fd62ea1a 1290 */
NYX 0:85b3fd62ea1a 1291
NYX 0:85b3fd62ea1a 1292 /**
NYX 0:85b3fd62ea1a 1293 * @}
NYX 0:85b3fd62ea1a 1294 */
NYX 0:85b3fd62ea1a 1295
NYX 0:85b3fd62ea1a 1296 /** @addtogroup I2S_Private_Functions I2S Private Functions
NYX 0:85b3fd62ea1a 1297 * @{
NYX 0:85b3fd62ea1a 1298 */
NYX 0:85b3fd62ea1a 1299 /**
NYX 0:85b3fd62ea1a 1300 * @brief DMA I2S transmit process complete callback
NYX 0:85b3fd62ea1a 1301 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1302 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 1303 * @retval None
NYX 0:85b3fd62ea1a 1304 */
NYX 0:85b3fd62ea1a 1305 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 1306 {
NYX 0:85b3fd62ea1a 1307 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX 0:85b3fd62ea1a 1308
NYX 0:85b3fd62ea1a 1309 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
NYX 0:85b3fd62ea1a 1310 {
NYX 0:85b3fd62ea1a 1311 /* Disable Tx DMA Request */
NYX 0:85b3fd62ea1a 1312 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 1313
NYX 0:85b3fd62ea1a 1314 hi2s->TxXferCount = 0U;
NYX 0:85b3fd62ea1a 1315 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1316 }
NYX 0:85b3fd62ea1a 1317 HAL_I2S_TxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1318 }
NYX 0:85b3fd62ea1a 1319 /**
NYX 0:85b3fd62ea1a 1320 * @brief DMA I2S transmit process half complete callback
NYX 0:85b3fd62ea1a 1321 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1322 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 1323 * @retval None
NYX 0:85b3fd62ea1a 1324 */
NYX 0:85b3fd62ea1a 1325 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 1326 {
NYX 0:85b3fd62ea1a 1327 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
NYX 0:85b3fd62ea1a 1328
NYX 0:85b3fd62ea1a 1329 HAL_I2S_TxHalfCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1330 }
NYX 0:85b3fd62ea1a 1331
NYX 0:85b3fd62ea1a 1332 /**
NYX 0:85b3fd62ea1a 1333 * @brief DMA I2S receive process complete callback
NYX 0:85b3fd62ea1a 1334 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1335 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 1336 * @retval None
NYX 0:85b3fd62ea1a 1337 */
NYX 0:85b3fd62ea1a 1338 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 1339 {
NYX 0:85b3fd62ea1a 1340 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX 0:85b3fd62ea1a 1341
NYX 0:85b3fd62ea1a 1342 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
NYX 0:85b3fd62ea1a 1343 {
NYX 0:85b3fd62ea1a 1344 /* Disable Rx DMA Request */
NYX 0:85b3fd62ea1a 1345 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 1346 hi2s->RxXferCount = 0U;
NYX 0:85b3fd62ea1a 1347 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1348 }
NYX 0:85b3fd62ea1a 1349 HAL_I2S_RxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1350 }
NYX 0:85b3fd62ea1a 1351
NYX 0:85b3fd62ea1a 1352 /**
NYX 0:85b3fd62ea1a 1353 * @brief DMA I2S receive process half complete callback
NYX 0:85b3fd62ea1a 1354 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1355 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 1356 * @retval None
NYX 0:85b3fd62ea1a 1357 */
NYX 0:85b3fd62ea1a 1358 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 1359 {
NYX 0:85b3fd62ea1a 1360 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
NYX 0:85b3fd62ea1a 1361
NYX 0:85b3fd62ea1a 1362 HAL_I2S_RxHalfCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1363 }
NYX 0:85b3fd62ea1a 1364
NYX 0:85b3fd62ea1a 1365 /**
NYX 0:85b3fd62ea1a 1366 * @brief DMA I2S communication error callback
NYX 0:85b3fd62ea1a 1367 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1368 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 1369 * @retval None
NYX 0:85b3fd62ea1a 1370 */
NYX 0:85b3fd62ea1a 1371 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 1372 {
NYX 0:85b3fd62ea1a 1373 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
NYX 0:85b3fd62ea1a 1374
NYX 0:85b3fd62ea1a 1375 /* Disable Rx and Tx DMA Request */
NYX 0:85b3fd62ea1a 1376 CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
NYX 0:85b3fd62ea1a 1377 hi2s->TxXferCount = 0U;
NYX 0:85b3fd62ea1a 1378 hi2s->RxXferCount = 0U;
NYX 0:85b3fd62ea1a 1379
NYX 0:85b3fd62ea1a 1380 hi2s->State= HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1381
NYX 0:85b3fd62ea1a 1382 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
NYX 0:85b3fd62ea1a 1383 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 1384 }
NYX 0:85b3fd62ea1a 1385
NYX 0:85b3fd62ea1a 1386 /**
NYX 0:85b3fd62ea1a 1387 * @brief Transmit an amount of data in non-blocking mode with Interrupt
NYX 0:85b3fd62ea1a 1388 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1389 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1390 * @retval HAL status
NYX 0:85b3fd62ea1a 1391 */
NYX 0:85b3fd62ea1a 1392 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1393 {
NYX 0:85b3fd62ea1a 1394 /* Transmit data */
NYX 0:85b3fd62ea1a 1395 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
NYX 0:85b3fd62ea1a 1396 hi2s->TxXferCount--;
NYX 0:85b3fd62ea1a 1397
NYX 0:85b3fd62ea1a 1398 if(hi2s->TxXferCount == 0U)
NYX 0:85b3fd62ea1a 1399 {
NYX 0:85b3fd62ea1a 1400 /* Disable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 1401 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 1402
NYX 0:85b3fd62ea1a 1403 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1404 HAL_I2S_TxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1405 }
NYX 0:85b3fd62ea1a 1406 }
NYX 0:85b3fd62ea1a 1407
NYX 0:85b3fd62ea1a 1408 /**
NYX 0:85b3fd62ea1a 1409 * @brief Receive an amount of data in non-blocking mode with Interrupt
NYX 0:85b3fd62ea1a 1410 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1411 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1412 * @retval HAL status
NYX 0:85b3fd62ea1a 1413 */
NYX 0:85b3fd62ea1a 1414 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1415 {
NYX 0:85b3fd62ea1a 1416 /* Receive data */
NYX 0:85b3fd62ea1a 1417 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
NYX 0:85b3fd62ea1a 1418 hi2s->RxXferCount--;
NYX 0:85b3fd62ea1a 1419
NYX 0:85b3fd62ea1a 1420 if(hi2s->RxXferCount == 0U)
NYX 0:85b3fd62ea1a 1421 {
NYX 0:85b3fd62ea1a 1422 /* Disable RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 1423 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 1424
NYX 0:85b3fd62ea1a 1425 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1426 HAL_I2S_RxCpltCallback(hi2s);
NYX 0:85b3fd62ea1a 1427 }
NYX 0:85b3fd62ea1a 1428 }
NYX 0:85b3fd62ea1a 1429
NYX 0:85b3fd62ea1a 1430 /**
NYX 0:85b3fd62ea1a 1431 * @brief This function handles I2S interrupt request.
NYX 0:85b3fd62ea1a 1432 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1433 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1434 * @retval None
NYX 0:85b3fd62ea1a 1435 */
NYX 0:85b3fd62ea1a 1436 static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
NYX 0:85b3fd62ea1a 1437 {
NYX 0:85b3fd62ea1a 1438 __IO uint32_t i2ssr = hi2s->Instance->SR;
NYX 0:85b3fd62ea1a 1439
NYX 0:85b3fd62ea1a 1440 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
NYX 0:85b3fd62ea1a 1441 {
NYX 0:85b3fd62ea1a 1442 /* I2S in mode Receiver ------------------------------------------------*/
NYX 0:85b3fd62ea1a 1443 if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
NYX 0:85b3fd62ea1a 1444 {
NYX 0:85b3fd62ea1a 1445 I2S_Receive_IT(hi2s);
NYX 0:85b3fd62ea1a 1446 }
NYX 0:85b3fd62ea1a 1447
NYX 0:85b3fd62ea1a 1448 /* I2S Overrun error interrupt occured -------------------------------------*/
NYX 0:85b3fd62ea1a 1449 if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
NYX 0:85b3fd62ea1a 1450 {
NYX 0:85b3fd62ea1a 1451 /* Disable RXNE and ERR interrupt */
NYX 0:85b3fd62ea1a 1452 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 1453
NYX 0:85b3fd62ea1a 1454 /* Clear Overrun flag */
NYX 0:85b3fd62ea1a 1455 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
NYX 0:85b3fd62ea1a 1456
NYX 0:85b3fd62ea1a 1457 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 1458 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1459
NYX 0:85b3fd62ea1a 1460
NYX 0:85b3fd62ea1a 1461 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 1462 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
NYX 0:85b3fd62ea1a 1463 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 1464 }
NYX 0:85b3fd62ea1a 1465 }
NYX 0:85b3fd62ea1a 1466
NYX 0:85b3fd62ea1a 1467 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
NYX 0:85b3fd62ea1a 1468 {
NYX 0:85b3fd62ea1a 1469 /* I2S in mode Transmitter -----------------------------------------------*/
NYX 0:85b3fd62ea1a 1470 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
NYX 0:85b3fd62ea1a 1471 {
NYX 0:85b3fd62ea1a 1472 I2S_Transmit_IT(hi2s);
NYX 0:85b3fd62ea1a 1473 }
NYX 0:85b3fd62ea1a 1474
NYX 0:85b3fd62ea1a 1475 /* I2S Underrun error interrupt occurred --------------------------------*/
NYX 0:85b3fd62ea1a 1476 if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
NYX 0:85b3fd62ea1a 1477 {
NYX 0:85b3fd62ea1a 1478 /* Disable TXE and ERR interrupt */
NYX 0:85b3fd62ea1a 1479 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
NYX 0:85b3fd62ea1a 1480
NYX 0:85b3fd62ea1a 1481 /* Clear Underrun flag */
NYX 0:85b3fd62ea1a 1482 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
NYX 0:85b3fd62ea1a 1483
NYX 0:85b3fd62ea1a 1484 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 1485 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1486
NYX 0:85b3fd62ea1a 1487 /* Set the error code and execute error callback*/
NYX 0:85b3fd62ea1a 1488 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
NYX 0:85b3fd62ea1a 1489 HAL_I2S_ErrorCallback(hi2s);
NYX 0:85b3fd62ea1a 1490 }
NYX 0:85b3fd62ea1a 1491 }
NYX 0:85b3fd62ea1a 1492 }
NYX 0:85b3fd62ea1a 1493
NYX 0:85b3fd62ea1a 1494 /**
NYX 0:85b3fd62ea1a 1495 * @brief This function handles I2S Communication Timeout.
NYX 0:85b3fd62ea1a 1496 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1497 * the configuration information for I2S module
NYX 0:85b3fd62ea1a 1498 * @param Flag: Flag checked
NYX 0:85b3fd62ea1a 1499 * @param State: Value of the flag expected
NYX 0:85b3fd62ea1a 1500 * @param Timeout: Duration of the timeout
NYX 0:85b3fd62ea1a 1501 * @retval HAL status
NYX 0:85b3fd62ea1a 1502 */
NYX 0:85b3fd62ea1a 1503 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
NYX 0:85b3fd62ea1a 1504 uint32_t Timeout)
NYX 0:85b3fd62ea1a 1505 {
NYX 0:85b3fd62ea1a 1506 uint32_t tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1507
NYX 0:85b3fd62ea1a 1508 /* Wait until flag is set to status*/
NYX 0:85b3fd62ea1a 1509 while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
NYX 0:85b3fd62ea1a 1510 {
NYX 0:85b3fd62ea1a 1511 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 1512 {
NYX 0:85b3fd62ea1a 1513 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
NYX 0:85b3fd62ea1a 1514 {
NYX 0:85b3fd62ea1a 1515 /* Set the I2S State ready */
NYX 0:85b3fd62ea1a 1516 hi2s->State = HAL_I2S_STATE_READY;
NYX 0:85b3fd62ea1a 1517
NYX 0:85b3fd62ea1a 1518 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1519 __HAL_UNLOCK(hi2s);
NYX 0:85b3fd62ea1a 1520
NYX 0:85b3fd62ea1a 1521 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1522 }
NYX 0:85b3fd62ea1a 1523 }
NYX 0:85b3fd62ea1a 1524 }
NYX 0:85b3fd62ea1a 1525 return HAL_OK;
NYX 0:85b3fd62ea1a 1526 }
NYX 0:85b3fd62ea1a 1527
NYX 0:85b3fd62ea1a 1528 /**
NYX 0:85b3fd62ea1a 1529 * @}
NYX 0:85b3fd62ea1a 1530 */
NYX 0:85b3fd62ea1a 1531
NYX 0:85b3fd62ea1a 1532 /**
NYX 0:85b3fd62ea1a 1533 * @}
NYX 0:85b3fd62ea1a 1534 */
NYX 0:85b3fd62ea1a 1535
NYX 0:85b3fd62ea1a 1536 #endif /* HAL_I2S_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 1537 /**
NYX 0:85b3fd62ea1a 1538 * @}
NYX 0:85b3fd62ea1a 1539 */
NYX 0:85b3fd62ea1a 1540
NYX 0:85b3fd62ea1a 1541 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/