mbed-dev - inport from local

Users » NYX » Code » mbed-dev

inport from local

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_hal_flash_ex.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of FLASH HAL Extension module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_HAL_FLASH_EX_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_HAL_FLASH_EX_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	47	#include "stm32f4xx_hal_def.h"
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	50	* @{
NYX	0:85b3fd62ea1a	51	*/
NYX	0:85b3fd62ea1a	52
NYX	0:85b3fd62ea1a	53	/** @addtogroup FLASHEx
NYX	0:85b3fd62ea1a	54	* @{
NYX	0:85b3fd62ea1a	55	*/
NYX	0:85b3fd62ea1a	56
NYX	0:85b3fd62ea1a	57	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	58	/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
NYX	0:85b3fd62ea1a	59	* @{
NYX	0:85b3fd62ea1a	60	*/
NYX	0:85b3fd62ea1a	61
NYX	0:85b3fd62ea1a	62	/**
NYX	0:85b3fd62ea1a	63	* @brief FLASH Erase structure definition
NYX	0:85b3fd62ea1a	64	*/
NYX	0:85b3fd62ea1a	65	typedef struct
NYX	0:85b3fd62ea1a	66	{
NYX	0:85b3fd62ea1a	67	uint32_t TypeErase; /*!< Mass erase or sector Erase.
NYX	0:85b3fd62ea1a	68	This parameter can be a value of @ref FLASHEx_Type_Erase */
NYX	0:85b3fd62ea1a	69
NYX	0:85b3fd62ea1a	70	uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
NYX	0:85b3fd62ea1a	71	This parameter must be a value of @ref FLASHEx_Banks */
NYX	0:85b3fd62ea1a	72
NYX	0:85b3fd62ea1a	73	uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
NYX	0:85b3fd62ea1a	74	This parameter must be a value of @ref FLASHEx_Sectors */
NYX	0:85b3fd62ea1a	75
NYX	0:85b3fd62ea1a	76	uint32_t NbSectors; /*!< Number of sectors to be erased.
NYX	0:85b3fd62ea1a	77	This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
NYX	0:85b3fd62ea1a	78
NYX	0:85b3fd62ea1a	79	uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
NYX	0:85b3fd62ea1a	80	This parameter must be a value of @ref FLASHEx_Voltage_Range */
NYX	0:85b3fd62ea1a	81
NYX	0:85b3fd62ea1a	82	} FLASH_EraseInitTypeDef;
NYX	0:85b3fd62ea1a	83
NYX	0:85b3fd62ea1a	84	/**
NYX	0:85b3fd62ea1a	85	* @brief FLASH Option Bytes Program structure definition
NYX	0:85b3fd62ea1a	86	*/
NYX	0:85b3fd62ea1a	87	typedef struct
NYX	0:85b3fd62ea1a	88	{
NYX	0:85b3fd62ea1a	89	uint32_t OptionType; /*!< Option byte to be configured.
NYX	0:85b3fd62ea1a	90	This parameter can be a value of @ref FLASHEx_Option_Type */
NYX	0:85b3fd62ea1a	91
NYX	0:85b3fd62ea1a	92	uint32_t WRPState; /*!< Write protection activation or deactivation.
NYX	0:85b3fd62ea1a	93	This parameter can be a value of @ref FLASHEx_WRP_State */
NYX	0:85b3fd62ea1a	94
NYX	0:85b3fd62ea1a	95	uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
NYX	0:85b3fd62ea1a	96	The value of this parameter depend on device used within the same series */
NYX	0:85b3fd62ea1a	97
NYX	0:85b3fd62ea1a	98	uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
NYX	0:85b3fd62ea1a	99	This parameter must be a value of @ref FLASHEx_Banks */
NYX	0:85b3fd62ea1a	100
NYX	0:85b3fd62ea1a	101	uint32_t RDPLevel; /*!< Set the read protection level.
NYX	0:85b3fd62ea1a	102	This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
NYX	0:85b3fd62ea1a	103
NYX	0:85b3fd62ea1a	104	uint32_t BORLevel; /*!< Set the BOR Level.
NYX	0:85b3fd62ea1a	105	This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
NYX	0:85b3fd62ea1a	106
NYX	0:85b3fd62ea1a	107	uint8_t USERConfig; /!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. /
NYX	0:85b3fd62ea1a	108
NYX	0:85b3fd62ea1a	109	} FLASH_OBProgramInitTypeDef;
NYX	0:85b3fd62ea1a	110
NYX	0:85b3fd62ea1a	111	/**
NYX	0:85b3fd62ea1a	112	* @brief FLASH Advanced Option Bytes Program structure definition
NYX	0:85b3fd62ea1a	113	*/
NYX	0:85b3fd62ea1a	114	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	115	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	116	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	117	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
NYX	0:85b3fd62ea1a	118	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	119	typedef struct
NYX	0:85b3fd62ea1a	120	{
NYX	0:85b3fd62ea1a	121	uint32_t OptionType; /*!< Option byte to be configured for extension.
NYX	0:85b3fd62ea1a	122	This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
NYX	0:85b3fd62ea1a	123
NYX	0:85b3fd62ea1a	124	uint32_t PCROPState; /*!< PCROP activation or deactivation.
NYX	0:85b3fd62ea1a	125	This parameter can be a value of @ref FLASHEx_PCROP_State */
NYX	0:85b3fd62ea1a	126
NYX	0:85b3fd62ea1a	127	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	128	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	129	uint16_t Sectors; /*!< specifies the sector(s) set for PCROP.
NYX	0:85b3fd62ea1a	130	This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
NYX	0:85b3fd62ea1a	131	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\|\
NYX	0:85b3fd62ea1a	132	STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	133
NYX	0:85b3fd62ea1a	134	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	135	uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors.
NYX	0:85b3fd62ea1a	136	This parameter must be a value of @ref FLASHEx_Banks */
NYX	0:85b3fd62ea1a	137
NYX	0:85b3fd62ea1a	138	uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1.
NYX	0:85b3fd62ea1a	139	This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
NYX	0:85b3fd62ea1a	140
NYX	0:85b3fd62ea1a	141	uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2.
NYX	0:85b3fd62ea1a	142	This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
NYX	0:85b3fd62ea1a	143
NYX	0:85b3fd62ea1a	144	uint8_t BootConfig; /*!< Specifies Option bytes for boot config.
NYX	0:85b3fd62ea1a	145	This parameter can be a value of @ref FLASHEx_Dual_Boot */
NYX	0:85b3fd62ea1a	146
NYX	0:85b3fd62ea1a	147	#endif /STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx /
NYX	0:85b3fd62ea1a	148	}FLASH_AdvOBProgramInitTypeDef;
NYX	0:85b3fd62ea1a	149	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\|
NYX	0:85b3fd62ea1a	150	STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	151	/**
NYX	0:85b3fd62ea1a	152	* @}
NYX	0:85b3fd62ea1a	153	*/
NYX	0:85b3fd62ea1a	154
NYX	0:85b3fd62ea1a	155	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	156
NYX	0:85b3fd62ea1a	157	/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
NYX	0:85b3fd62ea1a	158	* @{
NYX	0:85b3fd62ea1a	159	*/
NYX	0:85b3fd62ea1a	160
NYX	0:85b3fd62ea1a	161	/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
NYX	0:85b3fd62ea1a	162	* @{
NYX	0:85b3fd62ea1a	163	*/
NYX	0:85b3fd62ea1a	164	#define FLASH_TYPEERASE_SECTORS 0x00000000U /!< Sectors erase only /
NYX	0:85b3fd62ea1a	165	#define FLASH_TYPEERASE_MASSERASE 0x00000001U /!< Flash Mass erase activation /
NYX	0:85b3fd62ea1a	166	/**
NYX	0:85b3fd62ea1a	167	* @}
NYX	0:85b3fd62ea1a	168	*/
NYX	0:85b3fd62ea1a	169
NYX	0:85b3fd62ea1a	170	/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
NYX	0:85b3fd62ea1a	171	* @{
NYX	0:85b3fd62ea1a	172	*/
NYX	0:85b3fd62ea1a	173	#define FLASH_VOLTAGE_RANGE_1 0x00000000U /!< Device operating range: 1.8V to 2.1V /
NYX	0:85b3fd62ea1a	174	#define FLASH_VOLTAGE_RANGE_2 0x00000001U /!< Device operating range: 2.1V to 2.7V /
NYX	0:85b3fd62ea1a	175	#define FLASH_VOLTAGE_RANGE_3 0x00000002U /!< Device operating range: 2.7V to 3.6V /
NYX	0:85b3fd62ea1a	176	#define FLASH_VOLTAGE_RANGE_4 0x00000003U /!< Device operating range: 2.7V to 3.6V + External Vpp /
NYX	0:85b3fd62ea1a	177	/**
NYX	0:85b3fd62ea1a	178	* @}
NYX	0:85b3fd62ea1a	179	*/
NYX	0:85b3fd62ea1a	180
NYX	0:85b3fd62ea1a	181	/** @defgroup FLASHEx_WRP_State FLASH WRP State
NYX	0:85b3fd62ea1a	182	* @{
NYX	0:85b3fd62ea1a	183	*/
NYX	0:85b3fd62ea1a	184	#define OB_WRPSTATE_DISABLE 0x00000000U /!< Disable the write protection of the desired bank 1 sectors /
NYX	0:85b3fd62ea1a	185	#define OB_WRPSTATE_ENABLE 0x00000001U /!< Enable the write protection of the desired bank 1 sectors /
NYX	0:85b3fd62ea1a	186	/**
NYX	0:85b3fd62ea1a	187	* @}
NYX	0:85b3fd62ea1a	188	*/
NYX	0:85b3fd62ea1a	189
NYX	0:85b3fd62ea1a	190	/** @defgroup FLASHEx_Option_Type FLASH Option Type
NYX	0:85b3fd62ea1a	191	* @{
NYX	0:85b3fd62ea1a	192	*/
NYX	0:85b3fd62ea1a	193	#define OPTIONBYTE_WRP 0x00000001U /!< WRP option byte configuration /
NYX	0:85b3fd62ea1a	194	#define OPTIONBYTE_RDP 0x00000002U /!< RDP option byte configuration /
NYX	0:85b3fd62ea1a	195	#define OPTIONBYTE_USER 0x00000004U /!< USER option byte configuration /
NYX	0:85b3fd62ea1a	196	#define OPTIONBYTE_BOR 0x00000008U /!< BOR option byte configuration /
NYX	0:85b3fd62ea1a	197	/**
NYX	0:85b3fd62ea1a	198	* @}
NYX	0:85b3fd62ea1a	199	*/
NYX	0:85b3fd62ea1a	200
NYX	0:85b3fd62ea1a	201	/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
NYX	0:85b3fd62ea1a	202	* @{
NYX	0:85b3fd62ea1a	203	*/
NYX	0:85b3fd62ea1a	204	#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
NYX	0:85b3fd62ea1a	205	#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
NYX	0:85b3fd62ea1a	206	#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
NYX	0:85b3fd62ea1a	207	it s no more possible to go back to level 1 or 0 */
NYX	0:85b3fd62ea1a	208	/**
NYX	0:85b3fd62ea1a	209	* @}
NYX	0:85b3fd62ea1a	210	*/
NYX	0:85b3fd62ea1a	211
NYX	0:85b3fd62ea1a	212	/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
NYX	0:85b3fd62ea1a	213	* @{
NYX	0:85b3fd62ea1a	214	*/
NYX	0:85b3fd62ea1a	215	#define OB_IWDG_SW ((uint8_t)0x20) /!< Software IWDG selected /
NYX	0:85b3fd62ea1a	216	#define OB_IWDG_HW ((uint8_t)0x00) /!< Hardware IWDG selected /
NYX	0:85b3fd62ea1a	217	/**
NYX	0:85b3fd62ea1a	218	* @}
NYX	0:85b3fd62ea1a	219	*/
NYX	0:85b3fd62ea1a	220
NYX	0:85b3fd62ea1a	221	/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
NYX	0:85b3fd62ea1a	222	* @{
NYX	0:85b3fd62ea1a	223	*/
NYX	0:85b3fd62ea1a	224	#define OB_STOP_NO_RST ((uint8_t)0x40) /!< No reset generated when entering in STOP /
NYX	0:85b3fd62ea1a	225	#define OB_STOP_RST ((uint8_t)0x00) /!< Reset generated when entering in STOP /
NYX	0:85b3fd62ea1a	226	/**
NYX	0:85b3fd62ea1a	227	* @}
NYX	0:85b3fd62ea1a	228	*/
NYX	0:85b3fd62ea1a	229
NYX	0:85b3fd62ea1a	230
NYX	0:85b3fd62ea1a	231	/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
NYX	0:85b3fd62ea1a	232	* @{
NYX	0:85b3fd62ea1a	233	*/
NYX	0:85b3fd62ea1a	234	#define OB_STDBY_NO_RST ((uint8_t)0x80) /!< No reset generated when entering in STANDBY /
NYX	0:85b3fd62ea1a	235	#define OB_STDBY_RST ((uint8_t)0x00) /!< Reset generated when entering in STANDBY /
NYX	0:85b3fd62ea1a	236	/**
NYX	0:85b3fd62ea1a	237	* @}
NYX	0:85b3fd62ea1a	238	*/
NYX	0:85b3fd62ea1a	239
NYX	0:85b3fd62ea1a	240	/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
NYX	0:85b3fd62ea1a	241	* @{
NYX	0:85b3fd62ea1a	242	*/
NYX	0:85b3fd62ea1a	243	#define OB_BOR_LEVEL3 ((uint8_t)0x00) /!< Supply voltage ranges from 2.70 to 3.60 V /
NYX	0:85b3fd62ea1a	244	#define OB_BOR_LEVEL2 ((uint8_t)0x04) /!< Supply voltage ranges from 2.40 to 2.70 V /
NYX	0:85b3fd62ea1a	245	#define OB_BOR_LEVEL1 ((uint8_t)0x08) /!< Supply voltage ranges from 2.10 to 2.40 V /
NYX	0:85b3fd62ea1a	246	#define OB_BOR_OFF ((uint8_t)0x0C) /!< Supply voltage ranges from 1.62 to 2.10 V /
NYX	0:85b3fd62ea1a	247	/**
NYX	0:85b3fd62ea1a	248	* @}
NYX	0:85b3fd62ea1a	249	*/
NYX	0:85b3fd62ea1a	250
NYX	0:85b3fd62ea1a	251	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	252	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	253	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	254	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
NYX	0:85b3fd62ea1a	255	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	256	/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
NYX	0:85b3fd62ea1a	257	* @{
NYX	0:85b3fd62ea1a	258	*/
NYX	0:85b3fd62ea1a	259	#define OB_PCROP_STATE_DISABLE 0x00000000U /!< Disable PCROP /
NYX	0:85b3fd62ea1a	260	#define OB_PCROP_STATE_ENABLE 0x00000001U /!< Enable PCROP /
NYX	0:85b3fd62ea1a	261	/**
NYX	0:85b3fd62ea1a	262	* @}
NYX	0:85b3fd62ea1a	263	*/
NYX	0:85b3fd62ea1a	264	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
NYX	0:85b3fd62ea1a	265	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
NYX	0:85b3fd62ea1a	266	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	267
NYX	0:85b3fd62ea1a	268	/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
NYX	0:85b3fd62ea1a	269	* @{
NYX	0:85b3fd62ea1a	270	*/
NYX	0:85b3fd62ea1a	271	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	272	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	273	#define OPTIONBYTE_PCROP 0x00000001U /!< PCROP option byte configuration /
NYX	0:85b3fd62ea1a	274	#define OPTIONBYTE_BOOTCONFIG 0x00000002U /!< BOOTConfig option byte configuration /
NYX	0:85b3fd62ea1a	275	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	276
NYX	0:85b3fd62ea1a	277	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	278	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	279	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
NYX	0:85b3fd62ea1a	280	defined(STM32F423xx)
NYX	0:85b3fd62ea1a	281	#define OPTIONBYTE_PCROP 0x00000001U /!<PCROP option byte configuration /
NYX	0:85b3fd62ea1a	282	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\|
NYX	0:85b3fd62ea1a	283	STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	284	/**
NYX	0:85b3fd62ea1a	285	* @}
NYX	0:85b3fd62ea1a	286	*/
NYX	0:85b3fd62ea1a	287
NYX	0:85b3fd62ea1a	288	/** @defgroup FLASH_Latency FLASH Latency
NYX	0:85b3fd62ea1a	289	* @{
NYX	0:85b3fd62ea1a	290	*/
NYX	0:85b3fd62ea1a	291	/------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------/
NYX	0:85b3fd62ea1a	292	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	293	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	294	#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero Latency cycle /
NYX	0:85b3fd62ea1a	295	#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One Latency cycle /
NYX	0:85b3fd62ea1a	296	#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two Latency cycles /
NYX	0:85b3fd62ea1a	297	#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three Latency cycles /
NYX	0:85b3fd62ea1a	298	#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four Latency cycles /
NYX	0:85b3fd62ea1a	299	#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH Five Latency cycles /
NYX	0:85b3fd62ea1a	300	#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH Six Latency cycles /
NYX	0:85b3fd62ea1a	301	#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH Seven Latency cycles /
NYX	0:85b3fd62ea1a	302	#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /!< FLASH Eight Latency cycles /
NYX	0:85b3fd62ea1a	303	#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /!< FLASH Nine Latency cycles /
NYX	0:85b3fd62ea1a	304	#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /!< FLASH Ten Latency cycles /
NYX	0:85b3fd62ea1a	305	#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /!< FLASH Eleven Latency cycles /
NYX	0:85b3fd62ea1a	306	#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /!< FLASH Twelve Latency cycles /
NYX	0:85b3fd62ea1a	307	#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /!< FLASH Thirteen Latency cycles /
NYX	0:85b3fd62ea1a	308	#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /!< FLASH Fourteen Latency cycles /
NYX	0:85b3fd62ea1a	309	#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /!< FLASH Fifteen Latency cycles /
NYX	0:85b3fd62ea1a	310	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	311	/--------------------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	312
NYX	0:85b3fd62ea1a	313	/-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx/STM32F423xx -----------------------/
NYX	0:85b3fd62ea1a	314	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
NYX	0:85b3fd62ea1a	315	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	316	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\|\
NYX	0:85b3fd62ea1a	317	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	318
NYX	0:85b3fd62ea1a	319	#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero Latency cycle /
NYX	0:85b3fd62ea1a	320	#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One Latency cycle /
NYX	0:85b3fd62ea1a	321	#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two Latency cycles /
NYX	0:85b3fd62ea1a	322	#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three Latency cycles /
NYX	0:85b3fd62ea1a	323	#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four Latency cycles /
NYX	0:85b3fd62ea1a	324	#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH Five Latency cycles /
NYX	0:85b3fd62ea1a	325	#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH Six Latency cycles /
NYX	0:85b3fd62ea1a	326	#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH Seven Latency cycles /
NYX	0:85b3fd62ea1a	327	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F401xx \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\|
NYX	0:85b3fd62ea1a	328	STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	329	/--------------------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	330
NYX	0:85b3fd62ea1a	331	/**
NYX	0:85b3fd62ea1a	332	* @}
NYX	0:85b3fd62ea1a	333	*/
NYX	0:85b3fd62ea1a	334
NYX	0:85b3fd62ea1a	335
NYX	0:85b3fd62ea1a	336	/** @defgroup FLASHEx_Banks FLASH Banks
NYX	0:85b3fd62ea1a	337	* @{
NYX	0:85b3fd62ea1a	338	*/
NYX	0:85b3fd62ea1a	339	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	340	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	341	#define FLASH_BANK_1 1U /!< Bank 1 /
NYX	0:85b3fd62ea1a	342	#define FLASH_BANK_2 2U /!< Bank 2 /
NYX	0:85b3fd62ea1a	343	#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 \| FLASH_BANK_2) /!< Bank1 and Bank2 /
NYX	0:85b3fd62ea1a	344	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	345
NYX	0:85b3fd62ea1a	346	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
NYX	0:85b3fd62ea1a	347	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	348	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	349	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
NYX	0:85b3fd62ea1a	350	defined(STM32F423xx)
NYX	0:85b3fd62ea1a	351	#define FLASH_BANK_1 1U /!< Bank 1 /
NYX	0:85b3fd62ea1a	352	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F401xx \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx
NYX	0:85b3fd62ea1a	353	STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	354	/**
NYX	0:85b3fd62ea1a	355	* @}
NYX	0:85b3fd62ea1a	356	*/
NYX	0:85b3fd62ea1a	357
NYX	0:85b3fd62ea1a	358	/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
NYX	0:85b3fd62ea1a	359	* @{
NYX	0:85b3fd62ea1a	360	*/
NYX	0:85b3fd62ea1a	361	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	362	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	363	#define FLASH_MER_BIT (FLASH_CR_MER1 \| FLASH_CR_MER2) /!< 2 MER bits here to clear /
NYX	0:85b3fd62ea1a	364	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	365
NYX	0:85b3fd62ea1a	366	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
NYX	0:85b3fd62ea1a	367	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	368	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	369	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
NYX	0:85b3fd62ea1a	370	defined(STM32F423xx)
NYX	0:85b3fd62ea1a	371	#define FLASH_MER_BIT (FLASH_CR_MER) /!< only 1 MER Bit /
NYX	0:85b3fd62ea1a	372	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F401xx \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx
NYX	0:85b3fd62ea1a	373	STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	374	/**
NYX	0:85b3fd62ea1a	375	* @}
NYX	0:85b3fd62ea1a	376	*/
NYX	0:85b3fd62ea1a	377
NYX	0:85b3fd62ea1a	378	/** @defgroup FLASHEx_Sectors FLASH Sectors
NYX	0:85b3fd62ea1a	379	* @{
NYX	0:85b3fd62ea1a	380	*/
NYX	0:85b3fd62ea1a	381	/-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------/
NYX	0:85b3fd62ea1a	382	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	383	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	384	#define FLASH_SECTOR_0 0U /!< Sector Number 0 /
NYX	0:85b3fd62ea1a	385	#define FLASH_SECTOR_1 1U /!< Sector Number 1 /
NYX	0:85b3fd62ea1a	386	#define FLASH_SECTOR_2 2U /!< Sector Number 2 /
NYX	0:85b3fd62ea1a	387	#define FLASH_SECTOR_3 3U /!< Sector Number 3 /
NYX	0:85b3fd62ea1a	388	#define FLASH_SECTOR_4 4U /!< Sector Number 4 /
NYX	0:85b3fd62ea1a	389	#define FLASH_SECTOR_5 5U /!< Sector Number 5 /
NYX	0:85b3fd62ea1a	390	#define FLASH_SECTOR_6 6U /!< Sector Number 6 /
NYX	0:85b3fd62ea1a	391	#define FLASH_SECTOR_7 7U /!< Sector Number 7 /
NYX	0:85b3fd62ea1a	392	#define FLASH_SECTOR_8 8U /!< Sector Number 8 /
NYX	0:85b3fd62ea1a	393	#define FLASH_SECTOR_9 9U /!< Sector Number 9 /
NYX	0:85b3fd62ea1a	394	#define FLASH_SECTOR_10 10U /!< Sector Number 10 /
NYX	0:85b3fd62ea1a	395	#define FLASH_SECTOR_11 11U /!< Sector Number 11 /
NYX	0:85b3fd62ea1a	396	#define FLASH_SECTOR_12 12U /!< Sector Number 12 /
NYX	0:85b3fd62ea1a	397	#define FLASH_SECTOR_13 13U /!< Sector Number 13 /
NYX	0:85b3fd62ea1a	398	#define FLASH_SECTOR_14 14U /!< Sector Number 14 /
NYX	0:85b3fd62ea1a	399	#define FLASH_SECTOR_15 15U /!< Sector Number 15 /
NYX	0:85b3fd62ea1a	400	#define FLASH_SECTOR_16 16U /!< Sector Number 16 /
NYX	0:85b3fd62ea1a	401	#define FLASH_SECTOR_17 17U /!< Sector Number 17 /
NYX	0:85b3fd62ea1a	402	#define FLASH_SECTOR_18 18U /!< Sector Number 18 /
NYX	0:85b3fd62ea1a	403	#define FLASH_SECTOR_19 19U /!< Sector Number 19 /
NYX	0:85b3fd62ea1a	404	#define FLASH_SECTOR_20 20U /!< Sector Number 20 /
NYX	0:85b3fd62ea1a	405	#define FLASH_SECTOR_21 21U /!< Sector Number 21 /
NYX	0:85b3fd62ea1a	406	#define FLASH_SECTOR_22 22U /!< Sector Number 22 /
NYX	0:85b3fd62ea1a	407	#define FLASH_SECTOR_23 23U /!< Sector Number 23 /
NYX	0:85b3fd62ea1a	408	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	409	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	410
NYX	0:85b3fd62ea1a	411	/-------------------------------------- STM32F413xx/STM32F423xx --------------------------------------/
NYX	0:85b3fd62ea1a	412	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	413	#define FLASH_SECTOR_0 0U /!< Sector Number 0 /
NYX	0:85b3fd62ea1a	414	#define FLASH_SECTOR_1 1U /!< Sector Number 1 /
NYX	0:85b3fd62ea1a	415	#define FLASH_SECTOR_2 2U /!< Sector Number 2 /
NYX	0:85b3fd62ea1a	416	#define FLASH_SECTOR_3 3U /!< Sector Number 3 /
NYX	0:85b3fd62ea1a	417	#define FLASH_SECTOR_4 4U /!< Sector Number 4 /
NYX	0:85b3fd62ea1a	418	#define FLASH_SECTOR_5 5U /!< Sector Number 5 /
NYX	0:85b3fd62ea1a	419	#define FLASH_SECTOR_6 6U /!< Sector Number 6 /
NYX	0:85b3fd62ea1a	420	#define FLASH_SECTOR_7 7U /!< Sector Number 7 /
NYX	0:85b3fd62ea1a	421	#define FLASH_SECTOR_8 8U /!< Sector Number 8 /
NYX	0:85b3fd62ea1a	422	#define FLASH_SECTOR_9 9U /!< Sector Number 9 /
NYX	0:85b3fd62ea1a	423	#define FLASH_SECTOR_10 10U /!< Sector Number 10 /
NYX	0:85b3fd62ea1a	424	#define FLASH_SECTOR_11 11U /!< Sector Number 11 /
NYX	0:85b3fd62ea1a	425	#define FLASH_SECTOR_12 12U /!< Sector Number 12 /
NYX	0:85b3fd62ea1a	426	#define FLASH_SECTOR_13 13U /!< Sector Number 13 /
NYX	0:85b3fd62ea1a	427	#define FLASH_SECTOR_14 14U /!< Sector Number 14 /
NYX	0:85b3fd62ea1a	428	#define FLASH_SECTOR_15 15U /!< Sector Number 15 /
NYX	0:85b3fd62ea1a	429	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	430	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	431
NYX	0:85b3fd62ea1a	432	/--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------/
NYX	0:85b3fd62ea1a	433	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	434	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	435	#define FLASH_SECTOR_0 0U /!< Sector Number 0 /
NYX	0:85b3fd62ea1a	436	#define FLASH_SECTOR_1 1U /!< Sector Number 1 /
NYX	0:85b3fd62ea1a	437	#define FLASH_SECTOR_2 2U /!< Sector Number 2 /
NYX	0:85b3fd62ea1a	438	#define FLASH_SECTOR_3 3U /!< Sector Number 3 /
NYX	0:85b3fd62ea1a	439	#define FLASH_SECTOR_4 4U /!< Sector Number 4 /
NYX	0:85b3fd62ea1a	440	#define FLASH_SECTOR_5 5U /!< Sector Number 5 /
NYX	0:85b3fd62ea1a	441	#define FLASH_SECTOR_6 6U /!< Sector Number 6 /
NYX	0:85b3fd62ea1a	442	#define FLASH_SECTOR_7 7U /!< Sector Number 7 /
NYX	0:85b3fd62ea1a	443	#define FLASH_SECTOR_8 8U /!< Sector Number 8 /
NYX	0:85b3fd62ea1a	444	#define FLASH_SECTOR_9 9U /!< Sector Number 9 /
NYX	0:85b3fd62ea1a	445	#define FLASH_SECTOR_10 10U /!< Sector Number 10 /
NYX	0:85b3fd62ea1a	446	#define FLASH_SECTOR_11 11U /!< Sector Number 11 /
NYX	0:85b3fd62ea1a	447	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	448	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	449
NYX	0:85b3fd62ea1a	450	/--------------------------------------------- STM32F401xC -------------------------------------------/
NYX	0:85b3fd62ea1a	451	#if defined(STM32F401xC)
NYX	0:85b3fd62ea1a	452	#define FLASH_SECTOR_0 0U /!< Sector Number 0 /
NYX	0:85b3fd62ea1a	453	#define FLASH_SECTOR_1 1U /!< Sector Number 1 /
NYX	0:85b3fd62ea1a	454	#define FLASH_SECTOR_2 2U /!< Sector Number 2 /
NYX	0:85b3fd62ea1a	455	#define FLASH_SECTOR_3 3U /!< Sector Number 3 /
NYX	0:85b3fd62ea1a	456	#define FLASH_SECTOR_4 4U /!< Sector Number 4 /
NYX	0:85b3fd62ea1a	457	#define FLASH_SECTOR_5 5U /!< Sector Number 5 /
NYX	0:85b3fd62ea1a	458	#endif /* STM32F401xC */
NYX	0:85b3fd62ea1a	459	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	460
NYX	0:85b3fd62ea1a	461	/--------------------------------------------- STM32F410xx -------------------------------------------/
NYX	0:85b3fd62ea1a	462	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	463	#define FLASH_SECTOR_0 0U /!< Sector Number 0 /
NYX	0:85b3fd62ea1a	464	#define FLASH_SECTOR_1 1U /!< Sector Number 1 /
NYX	0:85b3fd62ea1a	465	#define FLASH_SECTOR_2 2U /!< Sector Number 2 /
NYX	0:85b3fd62ea1a	466	#define FLASH_SECTOR_3 3U /!< Sector Number 3 /
NYX	0:85b3fd62ea1a	467	#define FLASH_SECTOR_4 4U /!< Sector Number 4 /
NYX	0:85b3fd62ea1a	468	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	469	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	470
NYX	0:85b3fd62ea1a	471	/---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------/
NYX	0:85b3fd62ea1a	472	#if defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
NYX	0:85b3fd62ea1a	473	#define FLASH_SECTOR_0 0U /!< Sector Number 0 /
NYX	0:85b3fd62ea1a	474	#define FLASH_SECTOR_1 1U /!< Sector Number 1 /
NYX	0:85b3fd62ea1a	475	#define FLASH_SECTOR_2 2U /!< Sector Number 2 /
NYX	0:85b3fd62ea1a	476	#define FLASH_SECTOR_3 3U /!< Sector Number 3 /
NYX	0:85b3fd62ea1a	477	#define FLASH_SECTOR_4 4U /!< Sector Number 4 /
NYX	0:85b3fd62ea1a	478	#define FLASH_SECTOR_5 5U /!< Sector Number 5 /
NYX	0:85b3fd62ea1a	479	#define FLASH_SECTOR_6 6U /!< Sector Number 6 /
NYX	0:85b3fd62ea1a	480	#define FLASH_SECTOR_7 7U /!< Sector Number 7 /
NYX	0:85b3fd62ea1a	481	#endif /* STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
NYX	0:85b3fd62ea1a	482	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	483
NYX	0:85b3fd62ea1a	484	/**
NYX	0:85b3fd62ea1a	485	* @}
NYX	0:85b3fd62ea1a	486	*/
NYX	0:85b3fd62ea1a	487
NYX	0:85b3fd62ea1a	488	/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
NYX	0:85b3fd62ea1a	489	* @{
NYX	0:85b3fd62ea1a	490	*/
NYX	0:85b3fd62ea1a	491	/--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------/
NYX	0:85b3fd62ea1a	492	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	493	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	494	#define OB_WRP_SECTOR_0 0x00000001U /!< Write protection of Sector0 /
NYX	0:85b3fd62ea1a	495	#define OB_WRP_SECTOR_1 0x00000002U /!< Write protection of Sector1 /
NYX	0:85b3fd62ea1a	496	#define OB_WRP_SECTOR_2 0x00000004U /!< Write protection of Sector2 /
NYX	0:85b3fd62ea1a	497	#define OB_WRP_SECTOR_3 0x00000008U /!< Write protection of Sector3 /
NYX	0:85b3fd62ea1a	498	#define OB_WRP_SECTOR_4 0x00000010U /!< Write protection of Sector4 /
NYX	0:85b3fd62ea1a	499	#define OB_WRP_SECTOR_5 0x00000020U /!< Write protection of Sector5 /
NYX	0:85b3fd62ea1a	500	#define OB_WRP_SECTOR_6 0x00000040U /!< Write protection of Sector6 /
NYX	0:85b3fd62ea1a	501	#define OB_WRP_SECTOR_7 0x00000080U /!< Write protection of Sector7 /
NYX	0:85b3fd62ea1a	502	#define OB_WRP_SECTOR_8 0x00000100U /!< Write protection of Sector8 /
NYX	0:85b3fd62ea1a	503	#define OB_WRP_SECTOR_9 0x00000200U /!< Write protection of Sector9 /
NYX	0:85b3fd62ea1a	504	#define OB_WRP_SECTOR_10 0x00000400U /!< Write protection of Sector10 /
NYX	0:85b3fd62ea1a	505	#define OB_WRP_SECTOR_11 0x00000800U /!< Write protection of Sector11 /
NYX	0:85b3fd62ea1a	506	#define OB_WRP_SECTOR_12 0x00000001U << 12U /!< Write protection of Sector12 /
NYX	0:85b3fd62ea1a	507	#define OB_WRP_SECTOR_13 0x00000002U << 12U /!< Write protection of Sector13 /
NYX	0:85b3fd62ea1a	508	#define OB_WRP_SECTOR_14 0x00000004U << 12U /!< Write protection of Sector14 /
NYX	0:85b3fd62ea1a	509	#define OB_WRP_SECTOR_15 0x00000008U << 12U /!< Write protection of Sector15 /
NYX	0:85b3fd62ea1a	510	#define OB_WRP_SECTOR_16 0x00000010U << 12U /!< Write protection of Sector16 /
NYX	0:85b3fd62ea1a	511	#define OB_WRP_SECTOR_17 0x00000020U << 12U /!< Write protection of Sector17 /
NYX	0:85b3fd62ea1a	512	#define OB_WRP_SECTOR_18 0x00000040U << 12U /!< Write protection of Sector18 /
NYX	0:85b3fd62ea1a	513	#define OB_WRP_SECTOR_19 0x00000080U << 12U /!< Write protection of Sector19 /
NYX	0:85b3fd62ea1a	514	#define OB_WRP_SECTOR_20 0x00000100U << 12U /!< Write protection of Sector20 /
NYX	0:85b3fd62ea1a	515	#define OB_WRP_SECTOR_21 0x00000200U << 12U /!< Write protection of Sector21 /
NYX	0:85b3fd62ea1a	516	#define OB_WRP_SECTOR_22 0x00000400U << 12U /!< Write protection of Sector22 /
NYX	0:85b3fd62ea1a	517	#define OB_WRP_SECTOR_23 0x00000800U << 12U /!< Write protection of Sector23 /
NYX	0:85b3fd62ea1a	518	#define OB_WRP_SECTOR_All 0x00000FFFU << 12U /!< Write protection of all Sectors /
NYX	0:85b3fd62ea1a	519	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	520	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	521
NYX	0:85b3fd62ea1a	522	/--------------------------------------- STM32F413xx/STM32F423xx -------------------------------------/
NYX	0:85b3fd62ea1a	523	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	524	#define OB_WRP_SECTOR_0 0x00000001U /!< Write protection of Sector0 /
NYX	0:85b3fd62ea1a	525	#define OB_WRP_SECTOR_1 0x00000002U /!< Write protection of Sector1 /
NYX	0:85b3fd62ea1a	526	#define OB_WRP_SECTOR_2 0x00000004U /!< Write protection of Sector2 /
NYX	0:85b3fd62ea1a	527	#define OB_WRP_SECTOR_3 0x00000008U /!< Write protection of Sector3 /
NYX	0:85b3fd62ea1a	528	#define OB_WRP_SECTOR_4 0x00000010U /!< Write protection of Sector4 /
NYX	0:85b3fd62ea1a	529	#define OB_WRP_SECTOR_5 0x00000020U /!< Write protection of Sector5 /
NYX	0:85b3fd62ea1a	530	#define OB_WRP_SECTOR_6 0x00000040U /!< Write protection of Sector6 /
NYX	0:85b3fd62ea1a	531	#define OB_WRP_SECTOR_7 0x00000080U /!< Write protection of Sector7 /
NYX	0:85b3fd62ea1a	532	#define OB_WRP_SECTOR_8 0x00000100U /!< Write protection of Sector8 /
NYX	0:85b3fd62ea1a	533	#define OB_WRP_SECTOR_9 0x00000200U /!< Write protection of Sector9 /
NYX	0:85b3fd62ea1a	534	#define OB_WRP_SECTOR_10 0x00000400U /!< Write protection of Sector10 /
NYX	0:85b3fd62ea1a	535	#define OB_WRP_SECTOR_11 0x00000800U /!< Write protection of Sector11 /
NYX	0:85b3fd62ea1a	536	#define OB_WRP_SECTOR_12 0x00001000U /!< Write protection of Sector12 /
NYX	0:85b3fd62ea1a	537	#define OB_WRP_SECTOR_13 0x00002000U /!< Write protection of Sector13 /
NYX	0:85b3fd62ea1a	538	#define OB_WRP_SECTOR_14 0x00004000U /!< Write protection of Sector14 /
NYX	0:85b3fd62ea1a	539	#define OB_WRP_SECTOR_15 0x00004000U /!< Write protection of Sector15 /
NYX	0:85b3fd62ea1a	540	#define OB_WRP_SECTOR_All 0x00007FFFU /!< Write protection of all Sectors /
NYX	0:85b3fd62ea1a	541	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	542	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	543
NYX	0:85b3fd62ea1a	544	/--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------/
NYX	0:85b3fd62ea1a	545	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	546	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	547	#define OB_WRP_SECTOR_0 0x00000001U /!< Write protection of Sector0 /
NYX	0:85b3fd62ea1a	548	#define OB_WRP_SECTOR_1 0x00000002U /!< Write protection of Sector1 /
NYX	0:85b3fd62ea1a	549	#define OB_WRP_SECTOR_2 0x00000004U /!< Write protection of Sector2 /
NYX	0:85b3fd62ea1a	550	#define OB_WRP_SECTOR_3 0x00000008U /!< Write protection of Sector3 /
NYX	0:85b3fd62ea1a	551	#define OB_WRP_SECTOR_4 0x00000010U /!< Write protection of Sector4 /
NYX	0:85b3fd62ea1a	552	#define OB_WRP_SECTOR_5 0x00000020U /!< Write protection of Sector5 /
NYX	0:85b3fd62ea1a	553	#define OB_WRP_SECTOR_6 0x00000040U /!< Write protection of Sector6 /
NYX	0:85b3fd62ea1a	554	#define OB_WRP_SECTOR_7 0x00000080U /!< Write protection of Sector7 /
NYX	0:85b3fd62ea1a	555	#define OB_WRP_SECTOR_8 0x00000100U /!< Write protection of Sector8 /
NYX	0:85b3fd62ea1a	556	#define OB_WRP_SECTOR_9 0x00000200U /!< Write protection of Sector9 /
NYX	0:85b3fd62ea1a	557	#define OB_WRP_SECTOR_10 0x00000400U /!< Write protection of Sector10 /
NYX	0:85b3fd62ea1a	558	#define OB_WRP_SECTOR_11 0x00000800U /!< Write protection of Sector11 /
NYX	0:85b3fd62ea1a	559	#define OB_WRP_SECTOR_All 0x00000FFFU /!< Write protection of all Sectors /
NYX	0:85b3fd62ea1a	560	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	561	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	562
NYX	0:85b3fd62ea1a	563	/--------------------------------------------- STM32F401xC -------------------------------------------/
NYX	0:85b3fd62ea1a	564	#if defined(STM32F401xC)
NYX	0:85b3fd62ea1a	565	#define OB_WRP_SECTOR_0 0x00000001U /!< Write protection of Sector0 /
NYX	0:85b3fd62ea1a	566	#define OB_WRP_SECTOR_1 0x00000002U /!< Write protection of Sector1 /
NYX	0:85b3fd62ea1a	567	#define OB_WRP_SECTOR_2 0x00000004U /!< Write protection of Sector2 /
NYX	0:85b3fd62ea1a	568	#define OB_WRP_SECTOR_3 0x00000008U /!< Write protection of Sector3 /
NYX	0:85b3fd62ea1a	569	#define OB_WRP_SECTOR_4 0x00000010U /!< Write protection of Sector4 /
NYX	0:85b3fd62ea1a	570	#define OB_WRP_SECTOR_5 0x00000020U /!< Write protection of Sector5 /
NYX	0:85b3fd62ea1a	571	#define OB_WRP_SECTOR_All 0x00000FFFU /!< Write protection of all Sectors /
NYX	0:85b3fd62ea1a	572	#endif /* STM32F401xC */
NYX	0:85b3fd62ea1a	573	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	574
NYX	0:85b3fd62ea1a	575	/--------------------------------------------- STM32F410xx -------------------------------------------/
NYX	0:85b3fd62ea1a	576	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	577	#define OB_WRP_SECTOR_0 0x00000001U /!< Write protection of Sector0 /
NYX	0:85b3fd62ea1a	578	#define OB_WRP_SECTOR_1 0x00000002U /!< Write protection of Sector1 /
NYX	0:85b3fd62ea1a	579	#define OB_WRP_SECTOR_2 0x00000004U /!< Write protection of Sector2 /
NYX	0:85b3fd62ea1a	580	#define OB_WRP_SECTOR_3 0x00000008U /!< Write protection of Sector3 /
NYX	0:85b3fd62ea1a	581	#define OB_WRP_SECTOR_4 0x00000010U /!< Write protection of Sector4 /
NYX	0:85b3fd62ea1a	582	#define OB_WRP_SECTOR_All 0x00000FFFU /!< Write protection of all Sectors /
NYX	0:85b3fd62ea1a	583	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	584	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	585
NYX	0:85b3fd62ea1a	586	/---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------/
NYX	0:85b3fd62ea1a	587	#if defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
NYX	0:85b3fd62ea1a	588	#define OB_WRP_SECTOR_0 0x00000001U /!< Write protection of Sector0 /
NYX	0:85b3fd62ea1a	589	#define OB_WRP_SECTOR_1 0x00000002U /!< Write protection of Sector1 /
NYX	0:85b3fd62ea1a	590	#define OB_WRP_SECTOR_2 0x00000004U /!< Write protection of Sector2 /
NYX	0:85b3fd62ea1a	591	#define OB_WRP_SECTOR_3 0x00000008U /!< Write protection of Sector3 /
NYX	0:85b3fd62ea1a	592	#define OB_WRP_SECTOR_4 0x00000010U /!< Write protection of Sector4 /
NYX	0:85b3fd62ea1a	593	#define OB_WRP_SECTOR_5 0x00000020U /!< Write protection of Sector5 /
NYX	0:85b3fd62ea1a	594	#define OB_WRP_SECTOR_6 0x00000040U /!< Write protection of Sector6 /
NYX	0:85b3fd62ea1a	595	#define OB_WRP_SECTOR_7 0x00000080U /!< Write protection of Sector7 /
NYX	0:85b3fd62ea1a	596	#define OB_WRP_SECTOR_All 0x00000FFFU /!< Write protection of all Sectors /
NYX	0:85b3fd62ea1a	597	#endif /* STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
NYX	0:85b3fd62ea1a	598	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	599	/**
NYX	0:85b3fd62ea1a	600	* @}
NYX	0:85b3fd62ea1a	601	*/
NYX	0:85b3fd62ea1a	602
NYX	0:85b3fd62ea1a	603	/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
NYX	0:85b3fd62ea1a	604	* @{
NYX	0:85b3fd62ea1a	605	*/
NYX	0:85b3fd62ea1a	606	/-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------/
NYX	0:85b3fd62ea1a	607	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	608	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	609	#define OB_PCROP_SECTOR_0 0x00000001U /!< PC Read/Write protection of Sector0 /
NYX	0:85b3fd62ea1a	610	#define OB_PCROP_SECTOR_1 0x00000002U /!< PC Read/Write protection of Sector1 /
NYX	0:85b3fd62ea1a	611	#define OB_PCROP_SECTOR_2 0x00000004U /!< PC Read/Write protection of Sector2 /
NYX	0:85b3fd62ea1a	612	#define OB_PCROP_SECTOR_3 0x00000008U /!< PC Read/Write protection of Sector3 /
NYX	0:85b3fd62ea1a	613	#define OB_PCROP_SECTOR_4 0x00000010U /!< PC Read/Write protection of Sector4 /
NYX	0:85b3fd62ea1a	614	#define OB_PCROP_SECTOR_5 0x00000020U /!< PC Read/Write protection of Sector5 /
NYX	0:85b3fd62ea1a	615	#define OB_PCROP_SECTOR_6 0x00000040U /!< PC Read/Write protection of Sector6 /
NYX	0:85b3fd62ea1a	616	#define OB_PCROP_SECTOR_7 0x00000080U /!< PC Read/Write protection of Sector7 /
NYX	0:85b3fd62ea1a	617	#define OB_PCROP_SECTOR_8 0x00000100U /!< PC Read/Write protection of Sector8 /
NYX	0:85b3fd62ea1a	618	#define OB_PCROP_SECTOR_9 0x00000200U /!< PC Read/Write protection of Sector9 /
NYX	0:85b3fd62ea1a	619	#define OB_PCROP_SECTOR_10 0x00000400U /!< PC Read/Write protection of Sector10 /
NYX	0:85b3fd62ea1a	620	#define OB_PCROP_SECTOR_11 0x00000800U /!< PC Read/Write protection of Sector11 /
NYX	0:85b3fd62ea1a	621	#define OB_PCROP_SECTOR_12 0x00000001U /!< PC Read/Write protection of Sector12 /
NYX	0:85b3fd62ea1a	622	#define OB_PCROP_SECTOR_13 0x00000002U /!< PC Read/Write protection of Sector13 /
NYX	0:85b3fd62ea1a	623	#define OB_PCROP_SECTOR_14 0x00000004U /!< PC Read/Write protection of Sector14 /
NYX	0:85b3fd62ea1a	624	#define OB_PCROP_SECTOR_15 0x00000008U /!< PC Read/Write protection of Sector15 /
NYX	0:85b3fd62ea1a	625	#define OB_PCROP_SECTOR_16 0x00000010U /!< PC Read/Write protection of Sector16 /
NYX	0:85b3fd62ea1a	626	#define OB_PCROP_SECTOR_17 0x00000020U /!< PC Read/Write protection of Sector17 /
NYX	0:85b3fd62ea1a	627	#define OB_PCROP_SECTOR_18 0x00000040U /!< PC Read/Write protection of Sector18 /
NYX	0:85b3fd62ea1a	628	#define OB_PCROP_SECTOR_19 0x00000080U /!< PC Read/Write protection of Sector19 /
NYX	0:85b3fd62ea1a	629	#define OB_PCROP_SECTOR_20 0x00000100U /!< PC Read/Write protection of Sector20 /
NYX	0:85b3fd62ea1a	630	#define OB_PCROP_SECTOR_21 0x00000200U /!< PC Read/Write protection of Sector21 /
NYX	0:85b3fd62ea1a	631	#define OB_PCROP_SECTOR_22 0x00000400U /!< PC Read/Write protection of Sector22 /
NYX	0:85b3fd62ea1a	632	#define OB_PCROP_SECTOR_23 0x00000800U /!< PC Read/Write protection of Sector23 /
NYX	0:85b3fd62ea1a	633	#define OB_PCROP_SECTOR_All 0x00000FFFU /!< PC Read/Write protection of all Sectors /
NYX	0:85b3fd62ea1a	634	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	635	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	636
NYX	0:85b3fd62ea1a	637	/------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------/
NYX	0:85b3fd62ea1a	638	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	639	#define OB_PCROP_SECTOR_0 0x00000001U /!< PC Read/Write protection of Sector0 /
NYX	0:85b3fd62ea1a	640	#define OB_PCROP_SECTOR_1 0x00000002U /!< PC Read/Write protection of Sector1 /
NYX	0:85b3fd62ea1a	641	#define OB_PCROP_SECTOR_2 0x00000004U /!< PC Read/Write protection of Sector2 /
NYX	0:85b3fd62ea1a	642	#define OB_PCROP_SECTOR_3 0x00000008U /!< PC Read/Write protection of Sector3 /
NYX	0:85b3fd62ea1a	643	#define OB_PCROP_SECTOR_4 0x00000010U /!< PC Read/Write protection of Sector4 /
NYX	0:85b3fd62ea1a	644	#define OB_PCROP_SECTOR_5 0x00000020U /!< PC Read/Write protection of Sector5 /
NYX	0:85b3fd62ea1a	645	#define OB_PCROP_SECTOR_6 0x00000040U /!< PC Read/Write protection of Sector6 /
NYX	0:85b3fd62ea1a	646	#define OB_PCROP_SECTOR_7 0x00000080U /!< PC Read/Write protection of Sector7 /
NYX	0:85b3fd62ea1a	647	#define OB_PCROP_SECTOR_8 0x00000100U /!< PC Read/Write protection of Sector8 /
NYX	0:85b3fd62ea1a	648	#define OB_PCROP_SECTOR_9 0x00000200U /!< PC Read/Write protection of Sector9 /
NYX	0:85b3fd62ea1a	649	#define OB_PCROP_SECTOR_10 0x00000400U /!< PC Read/Write protection of Sector10 /
NYX	0:85b3fd62ea1a	650	#define OB_PCROP_SECTOR_11 0x00000800U /!< PC Read/Write protection of Sector11 /
NYX	0:85b3fd62ea1a	651	#define OB_PCROP_SECTOR_12 0x00001000U /!< PC Read/Write protection of Sector12 /
NYX	0:85b3fd62ea1a	652	#define OB_PCROP_SECTOR_13 0x00002000U /!< PC Read/Write protection of Sector13 /
NYX	0:85b3fd62ea1a	653	#define OB_PCROP_SECTOR_14 0x00004000U /!< PC Read/Write protection of Sector14 /
NYX	0:85b3fd62ea1a	654	#define OB_PCROP_SECTOR_15 0x00004000U /!< PC Read/Write protection of Sector15 /
NYX	0:85b3fd62ea1a	655	#define OB_PCROP_SECTOR_All 0x00007FFFU /!< PC Read/Write protection of all Sectors /
NYX	0:85b3fd62ea1a	656	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	657	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	658
NYX	0:85b3fd62ea1a	659	/--------------------------------------------- STM32F401xC -------------------------------------------/
NYX	0:85b3fd62ea1a	660	#if defined(STM32F401xC)
NYX	0:85b3fd62ea1a	661	#define OB_PCROP_SECTOR_0 0x00000001U /!< PC Read/Write protection of Sector0 /
NYX	0:85b3fd62ea1a	662	#define OB_PCROP_SECTOR_1 0x00000002U /!< PC Read/Write protection of Sector1 /
NYX	0:85b3fd62ea1a	663	#define OB_PCROP_SECTOR_2 0x00000004U /!< PC Read/Write protection of Sector2 /
NYX	0:85b3fd62ea1a	664	#define OB_PCROP_SECTOR_3 0x00000008U /!< PC Read/Write protection of Sector3 /
NYX	0:85b3fd62ea1a	665	#define OB_PCROP_SECTOR_4 0x00000010U /!< PC Read/Write protection of Sector4 /
NYX	0:85b3fd62ea1a	666	#define OB_PCROP_SECTOR_5 0x00000020U /!< PC Read/Write protection of Sector5 /
NYX	0:85b3fd62ea1a	667	#define OB_PCROP_SECTOR_All 0x00000FFFU /!< PC Read/Write protection of all Sectors /
NYX	0:85b3fd62ea1a	668	#endif /* STM32F401xC */
NYX	0:85b3fd62ea1a	669	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	670
NYX	0:85b3fd62ea1a	671	/--------------------------------------------- STM32F410xx -------------------------------------------/
NYX	0:85b3fd62ea1a	672	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	673	#define OB_PCROP_SECTOR_0 0x00000001U /!< PC Read/Write protection of Sector0 /
NYX	0:85b3fd62ea1a	674	#define OB_PCROP_SECTOR_1 0x00000002U /!< PC Read/Write protection of Sector1 /
NYX	0:85b3fd62ea1a	675	#define OB_PCROP_SECTOR_2 0x00000004U /!< PC Read/Write protection of Sector2 /
NYX	0:85b3fd62ea1a	676	#define OB_PCROP_SECTOR_3 0x00000008U /!< PC Read/Write protection of Sector3 /
NYX	0:85b3fd62ea1a	677	#define OB_PCROP_SECTOR_4 0x00000010U /!< PC Read/Write protection of Sector4 /
NYX	0:85b3fd62ea1a	678	#define OB_PCROP_SECTOR_All 0x00000FFFU /!< PC Read/Write protection of all Sectors /
NYX	0:85b3fd62ea1a	679	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	680	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	681
NYX	0:85b3fd62ea1a	682	/-------------- STM32F401xE/STM32F411xE/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F446xx --/
NYX	0:85b3fd62ea1a	683	#if defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	684	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	685	#define OB_PCROP_SECTOR_0 0x00000001U /!< PC Read/Write protection of Sector0 /
NYX	0:85b3fd62ea1a	686	#define OB_PCROP_SECTOR_1 0x00000002U /!< PC Read/Write protection of Sector1 /
NYX	0:85b3fd62ea1a	687	#define OB_PCROP_SECTOR_2 0x00000004U /!< PC Read/Write protection of Sector2 /
NYX	0:85b3fd62ea1a	688	#define OB_PCROP_SECTOR_3 0x00000008U /!< PC Read/Write protection of Sector3 /
NYX	0:85b3fd62ea1a	689	#define OB_PCROP_SECTOR_4 0x00000010U /!< PC Read/Write protection of Sector4 /
NYX	0:85b3fd62ea1a	690	#define OB_PCROP_SECTOR_5 0x00000020U /!< PC Read/Write protection of Sector5 /
NYX	0:85b3fd62ea1a	691	#define OB_PCROP_SECTOR_6 0x00000040U /!< PC Read/Write protection of Sector6 /
NYX	0:85b3fd62ea1a	692	#define OB_PCROP_SECTOR_7 0x00000080U /!< PC Read/Write protection of Sector7 /
NYX	0:85b3fd62ea1a	693	#define OB_PCROP_SECTOR_All 0x00000FFFU /!< PC Read/Write protection of all Sectors /
NYX	0:85b3fd62ea1a	694	#endif /* STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	695	/-----------------------------------------------------------------------------------------------------/
NYX	0:85b3fd62ea1a	696
NYX	0:85b3fd62ea1a	697	/**
NYX	0:85b3fd62ea1a	698	* @}
NYX	0:85b3fd62ea1a	699	*/
NYX	0:85b3fd62ea1a	700
NYX	0:85b3fd62ea1a	701	/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
NYX	0:85b3fd62ea1a	702	* @{
NYX	0:85b3fd62ea1a	703	*/
NYX	0:85b3fd62ea1a	704	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	705	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	706	#define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /!< Dual Bank Boot Enable /
NYX	0:85b3fd62ea1a	707	#define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /!< Dual Bank Boot Disable, always boot on User Flash /
NYX	0:85b3fd62ea1a	708	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	709	/**
NYX	0:85b3fd62ea1a	710	* @}
NYX	0:85b3fd62ea1a	711	*/
NYX	0:85b3fd62ea1a	712
NYX	0:85b3fd62ea1a	713	/** @defgroup FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
NYX	0:85b3fd62ea1a	714	* @{
NYX	0:85b3fd62ea1a	715	*/
NYX	0:85b3fd62ea1a	716	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	717	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	718	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	719	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
NYX	0:85b3fd62ea1a	720	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	721	#define OB_PCROP_DESELECTED ((uint8_t)0x00) /!< Disabled PcROP, nWPRi bits used for Write Protection on sector i /
NYX	0:85b3fd62ea1a	722	#define OB_PCROP_SELECTED ((uint8_t)0x80) /!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i /
NYX	0:85b3fd62ea1a	723	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
NYX	0:85b3fd62ea1a	724	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
NYX	0:85b3fd62ea1a	725	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	726	/**
NYX	0:85b3fd62ea1a	727	* @}
NYX	0:85b3fd62ea1a	728	*/
NYX	0:85b3fd62ea1a	729
NYX	0:85b3fd62ea1a	730	/**
NYX	0:85b3fd62ea1a	731	* @}
NYX	0:85b3fd62ea1a	732	*/
NYX	0:85b3fd62ea1a	733
NYX	0:85b3fd62ea1a	734	/* Exported macro ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	735
NYX	0:85b3fd62ea1a	736	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	737	/** @addtogroup FLASHEx_Exported_Functions
NYX	0:85b3fd62ea1a	738	* @{
NYX	0:85b3fd62ea1a	739	*/
NYX	0:85b3fd62ea1a	740
NYX	0:85b3fd62ea1a	741	/** @addtogroup FLASHEx_Exported_Functions_Group1
NYX	0:85b3fd62ea1a	742	* @{
NYX	0:85b3fd62ea1a	743	*/
NYX	0:85b3fd62ea1a	744	/* Extension Program operation functions *************************************/
NYX	0:85b3fd62ea1a	745	HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef pEraseInit, uint32_t SectorError);
NYX	0:85b3fd62ea1a	746	HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
NYX	0:85b3fd62ea1a	747	HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
NYX	0:85b3fd62ea1a	748	void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
NYX	0:85b3fd62ea1a	749
NYX	0:85b3fd62ea1a	750	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	751	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	752	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	753	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
NYX	0:85b3fd62ea1a	754	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	755	HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
NYX	0:85b3fd62ea1a	756	void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
NYX	0:85b3fd62ea1a	757	HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
NYX	0:85b3fd62ea1a	758	HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
NYX	0:85b3fd62ea1a	759	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
NYX	0:85b3fd62ea1a	760	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
NYX	0:85b3fd62ea1a	761	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	762
NYX	0:85b3fd62ea1a	763	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	764	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	765	uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
NYX	0:85b3fd62ea1a	766	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	767	/**
NYX	0:85b3fd62ea1a	768	* @}
NYX	0:85b3fd62ea1a	769	*/
NYX	0:85b3fd62ea1a	770
NYX	0:85b3fd62ea1a	771	/**
NYX	0:85b3fd62ea1a	772	* @}
NYX	0:85b3fd62ea1a	773	*/
NYX	0:85b3fd62ea1a	774	/* Private types -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	775	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	776	/* Private constants ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	777	/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
NYX	0:85b3fd62ea1a	778	* @{
NYX	0:85b3fd62ea1a	779	*/
NYX	0:85b3fd62ea1a	780	/--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------/
NYX	0:85b3fd62ea1a	781	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	782	#define FLASH_SECTOR_TOTAL 24U
NYX	0:85b3fd62ea1a	783	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	784
NYX	0:85b3fd62ea1a	785	/-------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------/
NYX	0:85b3fd62ea1a	786	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	787	#define FLASH_SECTOR_TOTAL 16U
NYX	0:85b3fd62ea1a	788	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	789
NYX	0:85b3fd62ea1a	790	/--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------/
NYX	0:85b3fd62ea1a	791	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	792	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	793	#define FLASH_SECTOR_TOTAL 12U
NYX	0:85b3fd62ea1a	794	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	795
NYX	0:85b3fd62ea1a	796	/--------------------------------------------- STM32F401xC -------------------------------------------/
NYX	0:85b3fd62ea1a	797	#if defined(STM32F401xC)
NYX	0:85b3fd62ea1a	798	#define FLASH_SECTOR_TOTAL 6U
NYX	0:85b3fd62ea1a	799	#endif /* STM32F401xC */
NYX	0:85b3fd62ea1a	800
NYX	0:85b3fd62ea1a	801	/--------------------------------------------- STM32F410xx -------------------------------------------/
NYX	0:85b3fd62ea1a	802	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	803	#define FLASH_SECTOR_TOTAL 5U
NYX	0:85b3fd62ea1a	804	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	805
NYX	0:85b3fd62ea1a	806	/--------------------------------- STM32F401xE/STM32F411xE/STM32F412xG/STM32F446xx -------------------/
NYX	0:85b3fd62ea1a	807	#if defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
NYX	0:85b3fd62ea1a	808	#define FLASH_SECTOR_TOTAL 8U
NYX	0:85b3fd62ea1a	809	#endif /* STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
NYX	0:85b3fd62ea1a	810
NYX	0:85b3fd62ea1a	811	/**
NYX	0:85b3fd62ea1a	812	* @brief OPTCR1 register byte 2 (Bits[23:16]) base address
NYX	0:85b3fd62ea1a	813	*/
NYX	0:85b3fd62ea1a	814	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	815	#define OPTCR1_BYTE2_ADDRESS 0x40023C1AU
NYX	0:85b3fd62ea1a	816	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	817
NYX	0:85b3fd62ea1a	818	/**
NYX	0:85b3fd62ea1a	819	* @}
NYX	0:85b3fd62ea1a	820	*/
NYX	0:85b3fd62ea1a	821
NYX	0:85b3fd62ea1a	822	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	823	/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
NYX	0:85b3fd62ea1a	824	* @{
NYX	0:85b3fd62ea1a	825	*/
NYX	0:85b3fd62ea1a	826
NYX	0:85b3fd62ea1a	827	/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
NYX	0:85b3fd62ea1a	828	* @{
NYX	0:85b3fd62ea1a	829	*/
NYX	0:85b3fd62ea1a	830
NYX	0:85b3fd62ea1a	831	#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) \|\| \
NYX	0:85b3fd62ea1a	832	((VALUE) == FLASH_TYPEERASE_MASSERASE))
NYX	0:85b3fd62ea1a	833
NYX	0:85b3fd62ea1a	834	#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) \|\| \
NYX	0:85b3fd62ea1a	835	((RANGE) == FLASH_VOLTAGE_RANGE_2) \|\| \
NYX	0:85b3fd62ea1a	836	((RANGE) == FLASH_VOLTAGE_RANGE_3) \|\| \
NYX	0:85b3fd62ea1a	837	((RANGE) == FLASH_VOLTAGE_RANGE_4))
NYX	0:85b3fd62ea1a	838
NYX	0:85b3fd62ea1a	839	#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	840	((VALUE) == OB_WRPSTATE_ENABLE))
NYX	0:85b3fd62ea1a	841
NYX	0:85b3fd62ea1a	842	#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP\|OPTIONBYTE_RDP\|OPTIONBYTE_USER\|OPTIONBYTE_BOR)))
NYX	0:85b3fd62ea1a	843
NYX	0:85b3fd62ea1a	844	#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) \|\|\
NYX	0:85b3fd62ea1a	845	((LEVEL) == OB_RDP_LEVEL_1) \|\|\
NYX	0:85b3fd62ea1a	846	((LEVEL) == OB_RDP_LEVEL_2))
NYX	0:85b3fd62ea1a	847
NYX	0:85b3fd62ea1a	848	#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) \|\| ((SOURCE) == OB_IWDG_HW))
NYX	0:85b3fd62ea1a	849
NYX	0:85b3fd62ea1a	850	#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) \|\| ((SOURCE) == OB_STOP_RST))
NYX	0:85b3fd62ea1a	851
NYX	0:85b3fd62ea1a	852	#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) \|\| ((SOURCE) == OB_STDBY_RST))
NYX	0:85b3fd62ea1a	853
NYX	0:85b3fd62ea1a	854	#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) \|\| ((LEVEL) == OB_BOR_LEVEL2) \|\|\
NYX	0:85b3fd62ea1a	855	((LEVEL) == OB_BOR_LEVEL3) \|\| ((LEVEL) == OB_BOR_OFF))
NYX	0:85b3fd62ea1a	856
NYX	0:85b3fd62ea1a	857	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	858	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	859	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	860	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
NYX	0:85b3fd62ea1a	861	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	862	#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	863	((VALUE) == OB_PCROP_STATE_ENABLE))
NYX	0:85b3fd62ea1a	864	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
NYX	0:85b3fd62ea1a	865	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
NYX	0:85b3fd62ea1a	866	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	867
NYX	0:85b3fd62ea1a	868	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	869	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	870	#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) \|\| \
NYX	0:85b3fd62ea1a	871	((VALUE) == OPTIONBYTE_BOOTCONFIG))
NYX	0:85b3fd62ea1a	872	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	873
NYX	0:85b3fd62ea1a	874	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	875	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	876	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
NYX	0:85b3fd62ea1a	877	defined(STM32F423xx)
NYX	0:85b3fd62ea1a	878	#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))
NYX	0:85b3fd62ea1a	879	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\|\
NYX	0:85b3fd62ea1a	880	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	881
NYX	0:85b3fd62ea1a	882	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	883	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	884	#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) \|\| \
NYX	0:85b3fd62ea1a	885	((LATENCY) == FLASH_LATENCY_1) \|\| \
NYX	0:85b3fd62ea1a	886	((LATENCY) == FLASH_LATENCY_2) \|\| \
NYX	0:85b3fd62ea1a	887	((LATENCY) == FLASH_LATENCY_3) \|\| \
NYX	0:85b3fd62ea1a	888	((LATENCY) == FLASH_LATENCY_4) \|\| \
NYX	0:85b3fd62ea1a	889	((LATENCY) == FLASH_LATENCY_5) \|\| \
NYX	0:85b3fd62ea1a	890	((LATENCY) == FLASH_LATENCY_6) \|\| \
NYX	0:85b3fd62ea1a	891	((LATENCY) == FLASH_LATENCY_7) \|\| \
NYX	0:85b3fd62ea1a	892	((LATENCY) == FLASH_LATENCY_8) \|\| \
NYX	0:85b3fd62ea1a	893	((LATENCY) == FLASH_LATENCY_9) \|\| \
NYX	0:85b3fd62ea1a	894	((LATENCY) == FLASH_LATENCY_10) \|\| \
NYX	0:85b3fd62ea1a	895	((LATENCY) == FLASH_LATENCY_11) \|\| \
NYX	0:85b3fd62ea1a	896	((LATENCY) == FLASH_LATENCY_12) \|\| \
NYX	0:85b3fd62ea1a	897	((LATENCY) == FLASH_LATENCY_13) \|\| \
NYX	0:85b3fd62ea1a	898	((LATENCY) == FLASH_LATENCY_14) \|\| \
NYX	0:85b3fd62ea1a	899	((LATENCY) == FLASH_LATENCY_15))
NYX	0:85b3fd62ea1a	900	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	901
NYX	0:85b3fd62ea1a	902	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
NYX	0:85b3fd62ea1a	903	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	904	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\|\
NYX	0:85b3fd62ea1a	905	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	906	#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) \|\| \
NYX	0:85b3fd62ea1a	907	((LATENCY) == FLASH_LATENCY_1) \|\| \
NYX	0:85b3fd62ea1a	908	((LATENCY) == FLASH_LATENCY_2) \|\| \
NYX	0:85b3fd62ea1a	909	((LATENCY) == FLASH_LATENCY_3) \|\| \
NYX	0:85b3fd62ea1a	910	((LATENCY) == FLASH_LATENCY_4) \|\| \
NYX	0:85b3fd62ea1a	911	((LATENCY) == FLASH_LATENCY_5) \|\| \
NYX	0:85b3fd62ea1a	912	((LATENCY) == FLASH_LATENCY_6) \|\| \
NYX	0:85b3fd62ea1a	913	((LATENCY) == FLASH_LATENCY_7))
NYX	0:85b3fd62ea1a	914	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
NYX	0:85b3fd62ea1a	915	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	916
NYX	0:85b3fd62ea1a	917	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	918	#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) \|\| \
NYX	0:85b3fd62ea1a	919	((BANK) == FLASH_BANK_2) \|\| \
NYX	0:85b3fd62ea1a	920	((BANK) == FLASH_BANK_BOTH))
NYX	0:85b3fd62ea1a	921	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	922
NYX	0:85b3fd62ea1a	923	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
NYX	0:85b3fd62ea1a	924	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	925	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	926	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
NYX	0:85b3fd62ea1a	927	defined(STM32F423xx)
NYX	0:85b3fd62ea1a	928	#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
NYX	0:85b3fd62ea1a	929	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
NYX	0:85b3fd62ea1a	930	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	931
NYX	0:85b3fd62ea1a	932	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	933	#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) \|\| ((SECTOR) == FLASH_SECTOR_1) \|\|\
NYX	0:85b3fd62ea1a	934	((SECTOR) == FLASH_SECTOR_2) \|\| ((SECTOR) == FLASH_SECTOR_3) \|\|\
NYX	0:85b3fd62ea1a	935	((SECTOR) == FLASH_SECTOR_4) \|\| ((SECTOR) == FLASH_SECTOR_5) \|\|\
NYX	0:85b3fd62ea1a	936	((SECTOR) == FLASH_SECTOR_6) \|\| ((SECTOR) == FLASH_SECTOR_7) \|\|\
NYX	0:85b3fd62ea1a	937	((SECTOR) == FLASH_SECTOR_8) \|\| ((SECTOR) == FLASH_SECTOR_9) \|\|\
NYX	0:85b3fd62ea1a	938	((SECTOR) == FLASH_SECTOR_10) \|\| ((SECTOR) == FLASH_SECTOR_11) \|\|\
NYX	0:85b3fd62ea1a	939	((SECTOR) == FLASH_SECTOR_12) \|\| ((SECTOR) == FLASH_SECTOR_13) \|\|\
NYX	0:85b3fd62ea1a	940	((SECTOR) == FLASH_SECTOR_14) \|\| ((SECTOR) == FLASH_SECTOR_15) \|\|\
NYX	0:85b3fd62ea1a	941	((SECTOR) == FLASH_SECTOR_16) \|\| ((SECTOR) == FLASH_SECTOR_17) \|\|\
NYX	0:85b3fd62ea1a	942	((SECTOR) == FLASH_SECTOR_18) \|\| ((SECTOR) == FLASH_SECTOR_19) \|\|\
NYX	0:85b3fd62ea1a	943	((SECTOR) == FLASH_SECTOR_20) \|\| ((SECTOR) == FLASH_SECTOR_21) \|\|\
NYX	0:85b3fd62ea1a	944	((SECTOR) == FLASH_SECTOR_22) \|\| ((SECTOR) == FLASH_SECTOR_23))
NYX	0:85b3fd62ea1a	945	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	946
NYX	0:85b3fd62ea1a	947	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	948	#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) \|\| ((SECTOR) == FLASH_SECTOR_1) \|\|\
NYX	0:85b3fd62ea1a	949	((SECTOR) == FLASH_SECTOR_2) \|\| ((SECTOR) == FLASH_SECTOR_3) \|\|\
NYX	0:85b3fd62ea1a	950	((SECTOR) == FLASH_SECTOR_4) \|\| ((SECTOR) == FLASH_SECTOR_5) \|\|\
NYX	0:85b3fd62ea1a	951	((SECTOR) == FLASH_SECTOR_6) \|\| ((SECTOR) == FLASH_SECTOR_7) \|\|\
NYX	0:85b3fd62ea1a	952	((SECTOR) == FLASH_SECTOR_8) \|\| ((SECTOR) == FLASH_SECTOR_9) \|\|\
NYX	0:85b3fd62ea1a	953	((SECTOR) == FLASH_SECTOR_10) \|\| ((SECTOR) == FLASH_SECTOR_11) \|\|\
NYX	0:85b3fd62ea1a	954	((SECTOR) == FLASH_SECTOR_12) \|\| ((SECTOR) == FLASH_SECTOR_13) \|\|\
NYX	0:85b3fd62ea1a	955	((SECTOR) == FLASH_SECTOR_14) \|\| ((SECTOR) == FLASH_SECTOR_15))
NYX	0:85b3fd62ea1a	956	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	957
NYX	0:85b3fd62ea1a	958	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F412Zx) \|\|\
NYX	0:85b3fd62ea1a	959	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	960	#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) \|\| ((SECTOR) == FLASH_SECTOR_1) \|\|\
NYX	0:85b3fd62ea1a	961	((SECTOR) == FLASH_SECTOR_2) \|\| ((SECTOR) == FLASH_SECTOR_3) \|\|\
NYX	0:85b3fd62ea1a	962	((SECTOR) == FLASH_SECTOR_4) \|\| ((SECTOR) == FLASH_SECTOR_5) \|\|\
NYX	0:85b3fd62ea1a	963	((SECTOR) == FLASH_SECTOR_6) \|\| ((SECTOR) == FLASH_SECTOR_7) \|\|\
NYX	0:85b3fd62ea1a	964	((SECTOR) == FLASH_SECTOR_8) \|\| ((SECTOR) == FLASH_SECTOR_9) \|\|\
NYX	0:85b3fd62ea1a	965	((SECTOR) == FLASH_SECTOR_10) \|\| ((SECTOR) == FLASH_SECTOR_11))
NYX	0:85b3fd62ea1a	966	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	967
NYX	0:85b3fd62ea1a	968	#if defined(STM32F401xC)
NYX	0:85b3fd62ea1a	969	#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) \|\| ((SECTOR) == FLASH_SECTOR_1) \|\|\
NYX	0:85b3fd62ea1a	970	((SECTOR) == FLASH_SECTOR_2) \|\| ((SECTOR) == FLASH_SECTOR_3) \|\|\
NYX	0:85b3fd62ea1a	971	((SECTOR) == FLASH_SECTOR_4) \|\| ((SECTOR) == FLASH_SECTOR_5))
NYX	0:85b3fd62ea1a	972	#endif /* STM32F401xC */
NYX	0:85b3fd62ea1a	973
NYX	0:85b3fd62ea1a	974	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	975	#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) \|\| ((SECTOR) == FLASH_SECTOR_1) \|\|\
NYX	0:85b3fd62ea1a	976	((SECTOR) == FLASH_SECTOR_2) \|\| ((SECTOR) == FLASH_SECTOR_3) \|\|\
NYX	0:85b3fd62ea1a	977	((SECTOR) == FLASH_SECTOR_4))
NYX	0:85b3fd62ea1a	978	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	979
NYX	0:85b3fd62ea1a	980	#if defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
NYX	0:85b3fd62ea1a	981	#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) \|\| ((SECTOR) == FLASH_SECTOR_1) \|\|\
NYX	0:85b3fd62ea1a	982	((SECTOR) == FLASH_SECTOR_2) \|\| ((SECTOR) == FLASH_SECTOR_3) \|\|\
NYX	0:85b3fd62ea1a	983	((SECTOR) == FLASH_SECTOR_4) \|\| ((SECTOR) == FLASH_SECTOR_5) \|\|\
NYX	0:85b3fd62ea1a	984	((SECTOR) == FLASH_SECTOR_6) \|\| ((SECTOR) == FLASH_SECTOR_7))
NYX	0:85b3fd62ea1a	985	#endif /* STM32F401xE \|\| STM32F411xE \|\| STM32F446xx */
NYX	0:85b3fd62ea1a	986
NYX	0:85b3fd62ea1a	987	#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) \|\| \
NYX	0:85b3fd62ea1a	988	(((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
NYX	0:85b3fd62ea1a	989
NYX	0:85b3fd62ea1a	990	#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
NYX	0:85b3fd62ea1a	991
NYX	0:85b3fd62ea1a	992	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	993	#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	994	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	995
NYX	0:85b3fd62ea1a	996	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	997	#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	998	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	999
NYX	0:85b3fd62ea1a	1000	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)
NYX	0:85b3fd62ea1a	1001	#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	1002	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
NYX	0:85b3fd62ea1a	1003
NYX	0:85b3fd62ea1a	1004	#if defined(STM32F401xC)
NYX	0:85b3fd62ea1a	1005	#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	1006	#endif /* STM32F401xC */
NYX	0:85b3fd62ea1a	1007
NYX	0:85b3fd62ea1a	1008	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	1009	#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	1010	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	1011
NYX	0:85b3fd62ea1a	1012	#if defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\|\
NYX	0:85b3fd62ea1a	1013	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	1014	#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	1015	#endif /* STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	1016
NYX	0:85b3fd62ea1a	1017	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1018	#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	1019	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1020
NYX	0:85b3fd62ea1a	1021	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1022	#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	1023	#endif /* STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1024
NYX	0:85b3fd62ea1a	1025	#if defined(STM32F401xC)
NYX	0:85b3fd62ea1a	1026	#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	1027	#endif /* STM32F401xC */
NYX	0:85b3fd62ea1a	1028
NYX	0:85b3fd62ea1a	1029	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
NYX	0:85b3fd62ea1a	1030	#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	1031	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
NYX	0:85b3fd62ea1a	1032
NYX	0:85b3fd62ea1a	1033	#if defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\|\
NYX	0:85b3fd62ea1a	1034	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
NYX	0:85b3fd62ea1a	1035	#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
NYX	0:85b3fd62ea1a	1036	#endif /* STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
NYX	0:85b3fd62ea1a	1037
NYX	0:85b3fd62ea1a	1038	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	1039	defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1040	#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) \|\| ((BOOT) == OB_DUAL_BOOT_DISABLE))
NYX	0:85b3fd62ea1a	1041	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1042
NYX	0:85b3fd62ea1a	1043	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	1044	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
NYX	0:85b3fd62ea1a	1045	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
NYX	0:85b3fd62ea1a	1046	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
NYX	0:85b3fd62ea1a	1047	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	1048	#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) \|\| ((PCROP) == OB_PCROP_DESELECTED))
NYX	0:85b3fd62ea1a	1049	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
NYX	0:85b3fd62ea1a	1050	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
NYX	0:85b3fd62ea1a	1051	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1052	/**
NYX	0:85b3fd62ea1a	1053	* @}
NYX	0:85b3fd62ea1a	1054	*/
NYX	0:85b3fd62ea1a	1055
NYX	0:85b3fd62ea1a	1056	/**
NYX	0:85b3fd62ea1a	1057	* @}
NYX	0:85b3fd62ea1a	1058	*/
NYX	0:85b3fd62ea1a	1059
NYX	0:85b3fd62ea1a	1060	/* Private functions ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1061	/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
NYX	0:85b3fd62ea1a	1062	* @{
NYX	0:85b3fd62ea1a	1063	*/
NYX	0:85b3fd62ea1a	1064	void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
NYX	0:85b3fd62ea1a	1065	void FLASH_FlushCaches(void);
NYX	0:85b3fd62ea1a	1066	/**
NYX	0:85b3fd62ea1a	1067	* @}
NYX	0:85b3fd62ea1a	1068	*/
NYX	0:85b3fd62ea1a	1069
NYX	0:85b3fd62ea1a	1070	/**
NYX	0:85b3fd62ea1a	1071	* @}
NYX	0:85b3fd62ea1a	1072	*/
NYX	0:85b3fd62ea1a	1073
NYX	0:85b3fd62ea1a	1074	/**
NYX	0:85b3fd62ea1a	1075	* @}
NYX	0:85b3fd62ea1a	1076	*/
NYX	0:85b3fd62ea1a	1077
NYX	0:85b3fd62ea1a	1078	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	1079	}
NYX	0:85b3fd62ea1a	1080	#endif
NYX	0:85b3fd62ea1a	1081
NYX	0:85b3fd62ea1a	1082	#endif /* __STM32F4xx_HAL_FLASH_EX_H */
NYX	0:85b3fd62ea1a	1083
NYX	0:85b3fd62ea1a	1084	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning