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inport from local

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_hal_eth.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of ETH HAL module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_HAL_ETH_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_HAL_ETH_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
NYX	0:85b3fd62ea1a	47	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	48	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	49	#include "stm32f4xx_hal_def.h"
NYX	0:85b3fd62ea1a	50
NYX	0:85b3fd62ea1a	51	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	52	* @{
NYX	0:85b3fd62ea1a	53	*/
NYX	0:85b3fd62ea1a	54
NYX	0:85b3fd62ea1a	55	/** @addtogroup ETH
NYX	0:85b3fd62ea1a	56	* @{
NYX	0:85b3fd62ea1a	57	*/
NYX	0:85b3fd62ea1a	58
NYX	0:85b3fd62ea1a	59	/** @addtogroup ETH_Private_Macros
NYX	0:85b3fd62ea1a	60	* @{
NYX	0:85b3fd62ea1a	61	*/
NYX	0:85b3fd62ea1a	62	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
NYX	0:85b3fd62ea1a	63	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	64	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
NYX	0:85b3fd62ea1a	65	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
NYX	0:85b3fd62ea1a	66	((SPEED) == ETH_SPEED_100M))
NYX	0:85b3fd62ea1a	67	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
NYX	0:85b3fd62ea1a	68	((MODE) == ETH_MODE_HALFDUPLEX))
NYX	0:85b3fd62ea1a	69	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
NYX	0:85b3fd62ea1a	70	((MODE) == ETH_RXINTERRUPT_MODE))
NYX	0:85b3fd62ea1a	71	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
NYX	0:85b3fd62ea1a	72	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
NYX	0:85b3fd62ea1a	73	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
NYX	0:85b3fd62ea1a	74	((MODE) == ETH_MEDIA_INTERFACE_RMII))
NYX	0:85b3fd62ea1a	75	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	76	((CMD) == ETH_WATCHDOG_DISABLE))
NYX	0:85b3fd62ea1a	77	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	78	((CMD) == ETH_JABBER_DISABLE))
NYX	0:85b3fd62ea1a	79	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
NYX	0:85b3fd62ea1a	80	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
NYX	0:85b3fd62ea1a	81	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
NYX	0:85b3fd62ea1a	82	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
NYX	0:85b3fd62ea1a	83	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
NYX	0:85b3fd62ea1a	84	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
NYX	0:85b3fd62ea1a	85	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
NYX	0:85b3fd62ea1a	86	((GAP) == ETH_INTERFRAMEGAP_40BIT))
NYX	0:85b3fd62ea1a	87	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	88	((CMD) == ETH_CARRIERSENCE_DISABLE))
NYX	0:85b3fd62ea1a	89	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	90	((CMD) == ETH_RECEIVEOWN_DISABLE))
NYX	0:85b3fd62ea1a	91	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	92	((CMD) == ETH_LOOPBACKMODE_DISABLE))
NYX	0:85b3fd62ea1a	93	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	94	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
NYX	0:85b3fd62ea1a	95	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	96	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
NYX	0:85b3fd62ea1a	97	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	98	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
NYX	0:85b3fd62ea1a	99	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
NYX	0:85b3fd62ea1a	100	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
NYX	0:85b3fd62ea1a	101	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
NYX	0:85b3fd62ea1a	102	((LIMIT) == ETH_BACKOFFLIMIT_1))
NYX	0:85b3fd62ea1a	103	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	104	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
NYX	0:85b3fd62ea1a	105	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	106	((CMD) == ETH_RECEIVEAll_DISABLE))
NYX	0:85b3fd62ea1a	107	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	108	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	109	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
NYX	0:85b3fd62ea1a	110	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
NYX	0:85b3fd62ea1a	111	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
NYX	0:85b3fd62ea1a	112	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
NYX	0:85b3fd62ea1a	113	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	114	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
NYX	0:85b3fd62ea1a	115	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
NYX	0:85b3fd62ea1a	116	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
NYX	0:85b3fd62ea1a	117	#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	118	((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
NYX	0:85b3fd62ea1a	119	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
NYX	0:85b3fd62ea1a	120	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
NYX	0:85b3fd62ea1a	121	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
NYX	0:85b3fd62ea1a	122	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
NYX	0:85b3fd62ea1a	123	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
NYX	0:85b3fd62ea1a	124	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
NYX	0:85b3fd62ea1a	125	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
NYX	0:85b3fd62ea1a	126	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
NYX	0:85b3fd62ea1a	127	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	128	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
NYX	0:85b3fd62ea1a	129	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
NYX	0:85b3fd62ea1a	130	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
NYX	0:85b3fd62ea1a	131	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
NYX	0:85b3fd62ea1a	132	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
NYX	0:85b3fd62ea1a	133	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	134	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
NYX	0:85b3fd62ea1a	135	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	136	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
NYX	0:85b3fd62ea1a	137	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	138	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
NYX	0:85b3fd62ea1a	139	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
NYX	0:85b3fd62ea1a	140	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
NYX	0:85b3fd62ea1a	141	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
NYX	0:85b3fd62ea1a	142	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
NYX	0:85b3fd62ea1a	143	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
NYX	0:85b3fd62ea1a	144	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
NYX	0:85b3fd62ea1a	145	((ADDRESS) == ETH_MAC_ADDRESS3))
NYX	0:85b3fd62ea1a	146	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
NYX	0:85b3fd62ea1a	147	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
NYX	0:85b3fd62ea1a	148	((ADDRESS) == ETH_MAC_ADDRESS3))
NYX	0:85b3fd62ea1a	149	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
NYX	0:85b3fd62ea1a	150	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
NYX	0:85b3fd62ea1a	151	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
NYX	0:85b3fd62ea1a	152	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
NYX	0:85b3fd62ea1a	153	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
NYX	0:85b3fd62ea1a	154	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
NYX	0:85b3fd62ea1a	155	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
NYX	0:85b3fd62ea1a	156	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
NYX	0:85b3fd62ea1a	157	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	158	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
NYX	0:85b3fd62ea1a	159	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	160	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
NYX	0:85b3fd62ea1a	161	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	162	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
NYX	0:85b3fd62ea1a	163	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	164	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
NYX	0:85b3fd62ea1a	165	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
NYX	0:85b3fd62ea1a	166	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
NYX	0:85b3fd62ea1a	167	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
NYX	0:85b3fd62ea1a	168	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
NYX	0:85b3fd62ea1a	169	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
NYX	0:85b3fd62ea1a	170	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
NYX	0:85b3fd62ea1a	171	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
NYX	0:85b3fd62ea1a	172	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
NYX	0:85b3fd62ea1a	173	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	174	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
NYX	0:85b3fd62ea1a	175	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	176	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
NYX	0:85b3fd62ea1a	177	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
NYX	0:85b3fd62ea1a	178	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
NYX	0:85b3fd62ea1a	179	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
NYX	0:85b3fd62ea1a	180	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
NYX	0:85b3fd62ea1a	181	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	182	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
NYX	0:85b3fd62ea1a	183	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	184	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
NYX	0:85b3fd62ea1a	185	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	186	((CMD) == ETH_FIXEDBURST_DISABLE))
NYX	0:85b3fd62ea1a	187	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
NYX	0:85b3fd62ea1a	188	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
NYX	0:85b3fd62ea1a	189	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
NYX	0:85b3fd62ea1a	190	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
NYX	0:85b3fd62ea1a	191	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
NYX	0:85b3fd62ea1a	192	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
NYX	0:85b3fd62ea1a	193	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
NYX	0:85b3fd62ea1a	194	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
NYX	0:85b3fd62ea1a	195	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
NYX	0:85b3fd62ea1a	196	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
NYX	0:85b3fd62ea1a	197	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
NYX	0:85b3fd62ea1a	198	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
NYX	0:85b3fd62ea1a	199	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
NYX	0:85b3fd62ea1a	200	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
NYX	0:85b3fd62ea1a	201	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
NYX	0:85b3fd62ea1a	202	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
NYX	0:85b3fd62ea1a	203	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
NYX	0:85b3fd62ea1a	204	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
NYX	0:85b3fd62ea1a	205	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
NYX	0:85b3fd62ea1a	206	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
NYX	0:85b3fd62ea1a	207	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
NYX	0:85b3fd62ea1a	208	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
NYX	0:85b3fd62ea1a	209	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
NYX	0:85b3fd62ea1a	210	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
NYX	0:85b3fd62ea1a	211	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
NYX	0:85b3fd62ea1a	212	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
NYX	0:85b3fd62ea1a	213	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
NYX	0:85b3fd62ea1a	214	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
NYX	0:85b3fd62ea1a	215	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
NYX	0:85b3fd62ea1a	216	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
NYX	0:85b3fd62ea1a	217	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
NYX	0:85b3fd62ea1a	218	((FLAG) == ETH_DMATXDESC_IC) \|\| \
NYX	0:85b3fd62ea1a	219	((FLAG) == ETH_DMATXDESC_LS) \|\| \
NYX	0:85b3fd62ea1a	220	((FLAG) == ETH_DMATXDESC_FS) \|\| \
NYX	0:85b3fd62ea1a	221	((FLAG) == ETH_DMATXDESC_DC) \|\| \
NYX	0:85b3fd62ea1a	222	((FLAG) == ETH_DMATXDESC_DP) \|\| \
NYX	0:85b3fd62ea1a	223	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
NYX	0:85b3fd62ea1a	224	((FLAG) == ETH_DMATXDESC_TER) \|\| \
NYX	0:85b3fd62ea1a	225	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
NYX	0:85b3fd62ea1a	226	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
NYX	0:85b3fd62ea1a	227	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
NYX	0:85b3fd62ea1a	228	((FLAG) == ETH_DMATXDESC_ES) \|\| \
NYX	0:85b3fd62ea1a	229	((FLAG) == ETH_DMATXDESC_JT) \|\| \
NYX	0:85b3fd62ea1a	230	((FLAG) == ETH_DMATXDESC_FF) \|\| \
NYX	0:85b3fd62ea1a	231	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
NYX	0:85b3fd62ea1a	232	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
NYX	0:85b3fd62ea1a	233	((FLAG) == ETH_DMATXDESC_NC) \|\| \
NYX	0:85b3fd62ea1a	234	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
NYX	0:85b3fd62ea1a	235	((FLAG) == ETH_DMATXDESC_EC) \|\| \
NYX	0:85b3fd62ea1a	236	((FLAG) == ETH_DMATXDESC_VF) \|\| \
NYX	0:85b3fd62ea1a	237	((FLAG) == ETH_DMATXDESC_CC) \|\| \
NYX	0:85b3fd62ea1a	238	((FLAG) == ETH_DMATXDESC_ED) \|\| \
NYX	0:85b3fd62ea1a	239	((FLAG) == ETH_DMATXDESC_UF) \|\| \
NYX	0:85b3fd62ea1a	240	((FLAG) == ETH_DMATXDESC_DB))
NYX	0:85b3fd62ea1a	241	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
NYX	0:85b3fd62ea1a	242	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
NYX	0:85b3fd62ea1a	243	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
NYX	0:85b3fd62ea1a	244	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
NYX	0:85b3fd62ea1a	245	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
NYX	0:85b3fd62ea1a	246	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
NYX	0:85b3fd62ea1a	247	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
NYX	0:85b3fd62ea1a	248	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
NYX	0:85b3fd62ea1a	249	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
NYX	0:85b3fd62ea1a	250	((FLAG) == ETH_DMARXDESC_ES) \|\| \
NYX	0:85b3fd62ea1a	251	((FLAG) == ETH_DMARXDESC_DE) \|\| \
NYX	0:85b3fd62ea1a	252	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
NYX	0:85b3fd62ea1a	253	((FLAG) == ETH_DMARXDESC_LE) \|\| \
NYX	0:85b3fd62ea1a	254	((FLAG) == ETH_DMARXDESC_OE) \|\| \
NYX	0:85b3fd62ea1a	255	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
NYX	0:85b3fd62ea1a	256	((FLAG) == ETH_DMARXDESC_FS) \|\| \
NYX	0:85b3fd62ea1a	257	((FLAG) == ETH_DMARXDESC_LS) \|\| \
NYX	0:85b3fd62ea1a	258	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
NYX	0:85b3fd62ea1a	259	((FLAG) == ETH_DMARXDESC_LC) \|\| \
NYX	0:85b3fd62ea1a	260	((FLAG) == ETH_DMARXDESC_FT) \|\| \
NYX	0:85b3fd62ea1a	261	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
NYX	0:85b3fd62ea1a	262	((FLAG) == ETH_DMARXDESC_RE) \|\| \
NYX	0:85b3fd62ea1a	263	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
NYX	0:85b3fd62ea1a	264	((FLAG) == ETH_DMARXDESC_CE) \|\| \
NYX	0:85b3fd62ea1a	265	((FLAG) == ETH_DMARXDESC_MAMPCE))
NYX	0:85b3fd62ea1a	266	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
NYX	0:85b3fd62ea1a	267	((BUFFER) == ETH_DMARXDESC_BUFFER2))
NYX	0:85b3fd62ea1a	268	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
NYX	0:85b3fd62ea1a	269	((FLAG) == ETH_PMT_FLAG_MPR))
NYX	0:85b3fd62ea1a	270	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
NYX	0:85b3fd62ea1a	271	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
NYX	0:85b3fd62ea1a	272	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
NYX	0:85b3fd62ea1a	273	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
NYX	0:85b3fd62ea1a	274	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
NYX	0:85b3fd62ea1a	275	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
NYX	0:85b3fd62ea1a	276	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
NYX	0:85b3fd62ea1a	277	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
NYX	0:85b3fd62ea1a	278	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
NYX	0:85b3fd62ea1a	279	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
NYX	0:85b3fd62ea1a	280	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
NYX	0:85b3fd62ea1a	281	((FLAG) == ETH_DMA_FLAG_T))
NYX	0:85b3fd62ea1a	282	#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
NYX	0:85b3fd62ea1a	283	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
NYX	0:85b3fd62ea1a	284	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
NYX	0:85b3fd62ea1a	285	((IT) == ETH_MAC_IT_PMT))
NYX	0:85b3fd62ea1a	286	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
NYX	0:85b3fd62ea1a	287	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
NYX	0:85b3fd62ea1a	288	((FLAG) == ETH_MAC_FLAG_PMT))
NYX	0:85b3fd62ea1a	289	#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
NYX	0:85b3fd62ea1a	290	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
NYX	0:85b3fd62ea1a	291	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
NYX	0:85b3fd62ea1a	292	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
NYX	0:85b3fd62ea1a	293	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
NYX	0:85b3fd62ea1a	294	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
NYX	0:85b3fd62ea1a	295	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
NYX	0:85b3fd62ea1a	296	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
NYX	0:85b3fd62ea1a	297	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
NYX	0:85b3fd62ea1a	298	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
NYX	0:85b3fd62ea1a	299	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
NYX	0:85b3fd62ea1a	300	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
NYX	0:85b3fd62ea1a	301	#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) \|\| (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
NYX	0:85b3fd62ea1a	302	((IT) != 0x00U))
NYX	0:85b3fd62ea1a	303	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
NYX	0:85b3fd62ea1a	304	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
NYX	0:85b3fd62ea1a	305	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
NYX	0:85b3fd62ea1a	306	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	307	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
NYX	0:85b3fd62ea1a	308
NYX	0:85b3fd62ea1a	309	/**
NYX	0:85b3fd62ea1a	310	* @}
NYX	0:85b3fd62ea1a	311	*/
NYX	0:85b3fd62ea1a	312
NYX	0:85b3fd62ea1a	313	/** @addtogroup ETH_Private_Defines
NYX	0:85b3fd62ea1a	314	* @{
NYX	0:85b3fd62ea1a	315	*/
NYX	0:85b3fd62ea1a	316	/* Delay to wait when writing to some Ethernet registers */
NYX	0:85b3fd62ea1a	317	#define ETH_REG_WRITE_DELAY 0x00000001U
NYX	0:85b3fd62ea1a	318
NYX	0:85b3fd62ea1a	319	/* ETHERNET Errors */
NYX	0:85b3fd62ea1a	320	#define ETH_SUCCESS 0U
NYX	0:85b3fd62ea1a	321	#define ETH_ERROR 1U
NYX	0:85b3fd62ea1a	322
NYX	0:85b3fd62ea1a	323	/* ETHERNET DMA Tx descriptors Collision Count Shift */
NYX	0:85b3fd62ea1a	324	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
NYX	0:85b3fd62ea1a	325
NYX	0:85b3fd62ea1a	326	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
NYX	0:85b3fd62ea1a	327	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
NYX	0:85b3fd62ea1a	328
NYX	0:85b3fd62ea1a	329	/* ETHERNET DMA Rx descriptors Frame Length Shift */
NYX	0:85b3fd62ea1a	330	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
NYX	0:85b3fd62ea1a	331
NYX	0:85b3fd62ea1a	332	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
NYX	0:85b3fd62ea1a	333	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
NYX	0:85b3fd62ea1a	334
NYX	0:85b3fd62ea1a	335	/* ETHERNET DMA Rx descriptors Frame length Shift */
NYX	0:85b3fd62ea1a	336	#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
NYX	0:85b3fd62ea1a	337
NYX	0:85b3fd62ea1a	338	/* ETHERNET MAC address offsets */
NYX	0:85b3fd62ea1a	339	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
NYX	0:85b3fd62ea1a	340	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
NYX	0:85b3fd62ea1a	341
NYX	0:85b3fd62ea1a	342	/* ETHERNET MACMIIAR register Mask */
NYX	0:85b3fd62ea1a	343	#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
NYX	0:85b3fd62ea1a	344
NYX	0:85b3fd62ea1a	345	/* ETHERNET MACCR register Mask */
NYX	0:85b3fd62ea1a	346	#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
NYX	0:85b3fd62ea1a	347
NYX	0:85b3fd62ea1a	348	/* ETHERNET MACFCR register Mask */
NYX	0:85b3fd62ea1a	349	#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
NYX	0:85b3fd62ea1a	350
NYX	0:85b3fd62ea1a	351	/* ETHERNET DMAOMR register Mask */
NYX	0:85b3fd62ea1a	352	#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
NYX	0:85b3fd62ea1a	353
NYX	0:85b3fd62ea1a	354	/* ETHERNET Remote Wake-up frame register length */
NYX	0:85b3fd62ea1a	355	#define ETH_WAKEUP_REGISTER_LENGTH 8U
NYX	0:85b3fd62ea1a	356
NYX	0:85b3fd62ea1a	357	/* ETHERNET Missed frames counter Shift */
NYX	0:85b3fd62ea1a	358	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
NYX	0:85b3fd62ea1a	359	/**
NYX	0:85b3fd62ea1a	360	* @}
NYX	0:85b3fd62ea1a	361	*/
NYX	0:85b3fd62ea1a	362
NYX	0:85b3fd62ea1a	363	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	364	/** @defgroup ETH_Exported_Types ETH Exported Types
NYX	0:85b3fd62ea1a	365	* @{
NYX	0:85b3fd62ea1a	366	*/
NYX	0:85b3fd62ea1a	367
NYX	0:85b3fd62ea1a	368	/**
NYX	0:85b3fd62ea1a	369	* @brief HAL State structures definition
NYX	0:85b3fd62ea1a	370	*/
NYX	0:85b3fd62ea1a	371	typedef enum
NYX	0:85b3fd62ea1a	372	{
NYX	0:85b3fd62ea1a	373	HAL_ETH_STATE_RESET = 0x00U, /!< Peripheral not yet Initialized or disabled /
NYX	0:85b3fd62ea1a	374	HAL_ETH_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
NYX	0:85b3fd62ea1a	375	HAL_ETH_STATE_BUSY = 0x02U, /!< an internal process is ongoing /
NYX	0:85b3fd62ea1a	376	HAL_ETH_STATE_BUSY_TX = 0x12U, /!< Data Transmission process is ongoing /
NYX	0:85b3fd62ea1a	377	HAL_ETH_STATE_BUSY_RX = 0x22U, /!< Data Reception process is ongoing /
NYX	0:85b3fd62ea1a	378	HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /!< Data Transmission and Reception process is ongoing /
NYX	0:85b3fd62ea1a	379	HAL_ETH_STATE_BUSY_WR = 0x42U, /!< Write process is ongoing /
NYX	0:85b3fd62ea1a	380	HAL_ETH_STATE_BUSY_RD = 0x82U, /!< Read process is ongoing /
NYX	0:85b3fd62ea1a	381	HAL_ETH_STATE_TIMEOUT = 0x03U, /!< Timeout state /
NYX	0:85b3fd62ea1a	382	HAL_ETH_STATE_ERROR = 0x04U /!< Reception process is ongoing /
NYX	0:85b3fd62ea1a	383	}HAL_ETH_StateTypeDef;
NYX	0:85b3fd62ea1a	384
NYX	0:85b3fd62ea1a	385	/**
NYX	0:85b3fd62ea1a	386	* @brief ETH Init Structure definition
NYX	0:85b3fd62ea1a	387	*/
NYX	0:85b3fd62ea1a	388
NYX	0:85b3fd62ea1a	389	typedef struct
NYX	0:85b3fd62ea1a	390	{
NYX	0:85b3fd62ea1a	391	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
NYX	0:85b3fd62ea1a	392	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
NYX	0:85b3fd62ea1a	393	and the mode (half/full-duplex).
NYX	0:85b3fd62ea1a	394	This parameter can be a value of @ref ETH_AutoNegotiation */
NYX	0:85b3fd62ea1a	395
NYX	0:85b3fd62ea1a	396	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
NYX	0:85b3fd62ea1a	397	This parameter can be a value of @ref ETH_Speed */
NYX	0:85b3fd62ea1a	398
NYX	0:85b3fd62ea1a	399	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
NYX	0:85b3fd62ea1a	400	This parameter can be a value of @ref ETH_Duplex_Mode */
NYX	0:85b3fd62ea1a	401
NYX	0:85b3fd62ea1a	402	uint16_t PhyAddress; /*!< Ethernet PHY address.
NYX	0:85b3fd62ea1a	403	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
NYX	0:85b3fd62ea1a	404
NYX	0:85b3fd62ea1a	405	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
NYX	0:85b3fd62ea1a	406
NYX	0:85b3fd62ea1a	407	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
NYX	0:85b3fd62ea1a	408	This parameter can be a value of @ref ETH_Rx_Mode */
NYX	0:85b3fd62ea1a	409
NYX	0:85b3fd62ea1a	410	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
NYX	0:85b3fd62ea1a	411	This parameter can be a value of @ref ETH_Checksum_Mode */
NYX	0:85b3fd62ea1a	412
NYX	0:85b3fd62ea1a	413	uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
NYX	0:85b3fd62ea1a	414	This parameter can be a value of @ref ETH_Media_Interface */
NYX	0:85b3fd62ea1a	415
NYX	0:85b3fd62ea1a	416	} ETH_InitTypeDef;
NYX	0:85b3fd62ea1a	417
NYX	0:85b3fd62ea1a	418
NYX	0:85b3fd62ea1a	419	/**
NYX	0:85b3fd62ea1a	420	* @brief ETH MAC Configuration Structure definition
NYX	0:85b3fd62ea1a	421	*/
NYX	0:85b3fd62ea1a	422
NYX	0:85b3fd62ea1a	423	typedef struct
NYX	0:85b3fd62ea1a	424	{
NYX	0:85b3fd62ea1a	425	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
NYX	0:85b3fd62ea1a	426	When enabled, the MAC allows no more then 2048 bytes to be received.
NYX	0:85b3fd62ea1a	427	When disabled, the MAC can receive up to 16384 bytes.
NYX	0:85b3fd62ea1a	428	This parameter can be a value of @ref ETH_Watchdog */
NYX	0:85b3fd62ea1a	429
NYX	0:85b3fd62ea1a	430	uint32_t Jabber; /*!< Selects or not Jabber timer
NYX	0:85b3fd62ea1a	431	When enabled, the MAC allows no more then 2048 bytes to be sent.
NYX	0:85b3fd62ea1a	432	When disabled, the MAC can send up to 16384 bytes.
NYX	0:85b3fd62ea1a	433	This parameter can be a value of @ref ETH_Jabber */
NYX	0:85b3fd62ea1a	434
NYX	0:85b3fd62ea1a	435	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
NYX	0:85b3fd62ea1a	436	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
NYX	0:85b3fd62ea1a	437
NYX	0:85b3fd62ea1a	438	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
NYX	0:85b3fd62ea1a	439	This parameter can be a value of @ref ETH_Carrier_Sense */
NYX	0:85b3fd62ea1a	440
NYX	0:85b3fd62ea1a	441	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
NYX	0:85b3fd62ea1a	442	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
NYX	0:85b3fd62ea1a	443	in Half-Duplex mode.
NYX	0:85b3fd62ea1a	444	This parameter can be a value of @ref ETH_Receive_Own */
NYX	0:85b3fd62ea1a	445
NYX	0:85b3fd62ea1a	446	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
NYX	0:85b3fd62ea1a	447	This parameter can be a value of @ref ETH_Loop_Back_Mode */
NYX	0:85b3fd62ea1a	448
NYX	0:85b3fd62ea1a	449	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
NYX	0:85b3fd62ea1a	450	This parameter can be a value of @ref ETH_Checksum_Offload */
NYX	0:85b3fd62ea1a	451
NYX	0:85b3fd62ea1a	452	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
NYX	0:85b3fd62ea1a	453	when a collision occurs (Half-Duplex mode).
NYX	0:85b3fd62ea1a	454	This parameter can be a value of @ref ETH_Retry_Transmission */
NYX	0:85b3fd62ea1a	455
NYX	0:85b3fd62ea1a	456	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
NYX	0:85b3fd62ea1a	457	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
NYX	0:85b3fd62ea1a	458
NYX	0:85b3fd62ea1a	459	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
NYX	0:85b3fd62ea1a	460	This parameter can be a value of @ref ETH_Back_Off_Limit */
NYX	0:85b3fd62ea1a	461
NYX	0:85b3fd62ea1a	462	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
NYX	0:85b3fd62ea1a	463	This parameter can be a value of @ref ETH_Deferral_Check */
NYX	0:85b3fd62ea1a	464
NYX	0:85b3fd62ea1a	465	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
NYX	0:85b3fd62ea1a	466	This parameter can be a value of @ref ETH_Receive_All */
NYX	0:85b3fd62ea1a	467
NYX	0:85b3fd62ea1a	468	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
NYX	0:85b3fd62ea1a	469	This parameter can be a value of @ref ETH_Source_Addr_Filter */
NYX	0:85b3fd62ea1a	470
NYX	0:85b3fd62ea1a	471	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
NYX	0:85b3fd62ea1a	472	This parameter can be a value of @ref ETH_Pass_Control_Frames */
NYX	0:85b3fd62ea1a	473
NYX	0:85b3fd62ea1a	474	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
NYX	0:85b3fd62ea1a	475	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
NYX	0:85b3fd62ea1a	476
NYX	0:85b3fd62ea1a	477	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
NYX	0:85b3fd62ea1a	478	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
NYX	0:85b3fd62ea1a	479
NYX	0:85b3fd62ea1a	480	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
NYX	0:85b3fd62ea1a	481	This parameter can be a value of @ref ETH_Promiscuous_Mode */
NYX	0:85b3fd62ea1a	482
NYX	0:85b3fd62ea1a	483	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
NYX	0:85b3fd62ea1a	484	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
NYX	0:85b3fd62ea1a	485
NYX	0:85b3fd62ea1a	486	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
NYX	0:85b3fd62ea1a	487	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
NYX	0:85b3fd62ea1a	488
NYX	0:85b3fd62ea1a	489	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
NYX	0:85b3fd62ea1a	490	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
NYX	0:85b3fd62ea1a	491
NYX	0:85b3fd62ea1a	492	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
NYX	0:85b3fd62ea1a	493	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
NYX	0:85b3fd62ea1a	494
NYX	0:85b3fd62ea1a	495	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
NYX	0:85b3fd62ea1a	496	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
NYX	0:85b3fd62ea1a	497
NYX	0:85b3fd62ea1a	498	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
NYX	0:85b3fd62ea1a	499	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
NYX	0:85b3fd62ea1a	500
NYX	0:85b3fd62ea1a	501	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
NYX	0:85b3fd62ea1a	502	automatic retransmission of PAUSE Frame.
NYX	0:85b3fd62ea1a	503	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
NYX	0:85b3fd62ea1a	504
NYX	0:85b3fd62ea1a	505	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
NYX	0:85b3fd62ea1a	506	unicast address and unique multicast address).
NYX	0:85b3fd62ea1a	507	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
NYX	0:85b3fd62ea1a	508
NYX	0:85b3fd62ea1a	509	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
NYX	0:85b3fd62ea1a	510	disable its transmitter for a specified time (Pause Time)
NYX	0:85b3fd62ea1a	511	This parameter can be a value of @ref ETH_Receive_Flow_Control */
NYX	0:85b3fd62ea1a	512
NYX	0:85b3fd62ea1a	513	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
NYX	0:85b3fd62ea1a	514	or the MAC back-pressure operation (Half-Duplex mode)
NYX	0:85b3fd62ea1a	515	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
NYX	0:85b3fd62ea1a	516
NYX	0:85b3fd62ea1a	517	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
NYX	0:85b3fd62ea1a	518	comparison and filtering.
NYX	0:85b3fd62ea1a	519	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
NYX	0:85b3fd62ea1a	520
NYX	0:85b3fd62ea1a	521	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
NYX	0:85b3fd62ea1a	522
NYX	0:85b3fd62ea1a	523	} ETH_MACInitTypeDef;
NYX	0:85b3fd62ea1a	524
NYX	0:85b3fd62ea1a	525	/**
NYX	0:85b3fd62ea1a	526	* @brief ETH DMA Configuration Structure definition
NYX	0:85b3fd62ea1a	527	*/
NYX	0:85b3fd62ea1a	528
NYX	0:85b3fd62ea1a	529	typedef struct
NYX	0:85b3fd62ea1a	530	{
NYX	0:85b3fd62ea1a	531	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
NYX	0:85b3fd62ea1a	532	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
NYX	0:85b3fd62ea1a	533
NYX	0:85b3fd62ea1a	534	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
NYX	0:85b3fd62ea1a	535	This parameter can be a value of @ref ETH_Receive_Store_Forward */
NYX	0:85b3fd62ea1a	536
NYX	0:85b3fd62ea1a	537	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
NYX	0:85b3fd62ea1a	538	This parameter can be a value of @ref ETH_Flush_Received_Frame */
NYX	0:85b3fd62ea1a	539
NYX	0:85b3fd62ea1a	540	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
NYX	0:85b3fd62ea1a	541	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
NYX	0:85b3fd62ea1a	542
NYX	0:85b3fd62ea1a	543	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
NYX	0:85b3fd62ea1a	544	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
NYX	0:85b3fd62ea1a	545
NYX	0:85b3fd62ea1a	546	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
NYX	0:85b3fd62ea1a	547	This parameter can be a value of @ref ETH_Forward_Error_Frames */
NYX	0:85b3fd62ea1a	548
NYX	0:85b3fd62ea1a	549	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
NYX	0:85b3fd62ea1a	550	and length less than 64 bytes) including pad-bytes and CRC)
NYX	0:85b3fd62ea1a	551	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
NYX	0:85b3fd62ea1a	552
NYX	0:85b3fd62ea1a	553	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
NYX	0:85b3fd62ea1a	554	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
NYX	0:85b3fd62ea1a	555
NYX	0:85b3fd62ea1a	556	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
NYX	0:85b3fd62ea1a	557	frame of Transmit data even before obtaining the status for the first frame.
NYX	0:85b3fd62ea1a	558	This parameter can be a value of @ref ETH_Second_Frame_Operate */
NYX	0:85b3fd62ea1a	559
NYX	0:85b3fd62ea1a	560	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
NYX	0:85b3fd62ea1a	561	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
NYX	0:85b3fd62ea1a	562
NYX	0:85b3fd62ea1a	563	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
NYX	0:85b3fd62ea1a	564	This parameter can be a value of @ref ETH_Fixed_Burst */
NYX	0:85b3fd62ea1a	565
NYX	0:85b3fd62ea1a	566	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
NYX	0:85b3fd62ea1a	567	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
NYX	0:85b3fd62ea1a	568
NYX	0:85b3fd62ea1a	569	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
NYX	0:85b3fd62ea1a	570	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
NYX	0:85b3fd62ea1a	571
NYX	0:85b3fd62ea1a	572	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
NYX	0:85b3fd62ea1a	573	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
NYX	0:85b3fd62ea1a	574
NYX	0:85b3fd62ea1a	575	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
NYX	0:85b3fd62ea1a	576	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
NYX	0:85b3fd62ea1a	577
NYX	0:85b3fd62ea1a	578	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
NYX	0:85b3fd62ea1a	579	This parameter can be a value of @ref ETH_DMA_Arbitration */
NYX	0:85b3fd62ea1a	580	} ETH_DMAInitTypeDef;
NYX	0:85b3fd62ea1a	581
NYX	0:85b3fd62ea1a	582
NYX	0:85b3fd62ea1a	583	/**
NYX	0:85b3fd62ea1a	584	* @brief ETH DMA Descriptors data structure definition
NYX	0:85b3fd62ea1a	585	*/
NYX	0:85b3fd62ea1a	586
NYX	0:85b3fd62ea1a	587	typedef struct
NYX	0:85b3fd62ea1a	588	{
NYX	0:85b3fd62ea1a	589	__IO uint32_t Status; /!< Status /
NYX	0:85b3fd62ea1a	590
NYX	0:85b3fd62ea1a	591	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
NYX	0:85b3fd62ea1a	592
NYX	0:85b3fd62ea1a	593	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
NYX	0:85b3fd62ea1a	594
NYX	0:85b3fd62ea1a	595	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
NYX	0:85b3fd62ea1a	596
NYX	0:85b3fd62ea1a	597	/!< Enhanced ETHERNET DMA PTP Descriptors /
NYX	0:85b3fd62ea1a	598	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
NYX	0:85b3fd62ea1a	599
NYX	0:85b3fd62ea1a	600	uint32_t Reserved1; /!< Reserved /
NYX	0:85b3fd62ea1a	601
NYX	0:85b3fd62ea1a	602	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
NYX	0:85b3fd62ea1a	603
NYX	0:85b3fd62ea1a	604	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
NYX	0:85b3fd62ea1a	605
NYX	0:85b3fd62ea1a	606	} ETH_DMADescTypeDef;
NYX	0:85b3fd62ea1a	607
NYX	0:85b3fd62ea1a	608	/**
NYX	0:85b3fd62ea1a	609	* @brief Received Frame Informations structure definition
NYX	0:85b3fd62ea1a	610	*/
NYX	0:85b3fd62ea1a	611	typedef struct
NYX	0:85b3fd62ea1a	612	{
NYX	0:85b3fd62ea1a	613	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
NYX	0:85b3fd62ea1a	614
NYX	0:85b3fd62ea1a	615	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
NYX	0:85b3fd62ea1a	616
NYX	0:85b3fd62ea1a	617	uint32_t SegCount; /!< Segment count /
NYX	0:85b3fd62ea1a	618
NYX	0:85b3fd62ea1a	619	uint32_t length; /!< Frame length /
NYX	0:85b3fd62ea1a	620
NYX	0:85b3fd62ea1a	621	uint32_t buffer; /!< Frame buffer /
NYX	0:85b3fd62ea1a	622
NYX	0:85b3fd62ea1a	623	} ETH_DMARxFrameInfos;
NYX	0:85b3fd62ea1a	624
NYX	0:85b3fd62ea1a	625	/**
NYX	0:85b3fd62ea1a	626	* @brief ETH Handle Structure definition
NYX	0:85b3fd62ea1a	627	*/
NYX	0:85b3fd62ea1a	628
NYX	0:85b3fd62ea1a	629	typedef struct
NYX	0:85b3fd62ea1a	630	{
NYX	0:85b3fd62ea1a	631	ETH_TypeDef Instance; /!< Register base address */
NYX	0:85b3fd62ea1a	632
NYX	0:85b3fd62ea1a	633	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
NYX	0:85b3fd62ea1a	634
NYX	0:85b3fd62ea1a	635	uint32_t LinkStatus; /!< Ethernet link status /
NYX	0:85b3fd62ea1a	636
NYX	0:85b3fd62ea1a	637	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
NYX	0:85b3fd62ea1a	638
NYX	0:85b3fd62ea1a	639	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
NYX	0:85b3fd62ea1a	640
NYX	0:85b3fd62ea1a	641	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
NYX	0:85b3fd62ea1a	642
NYX	0:85b3fd62ea1a	643	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
NYX	0:85b3fd62ea1a	644
NYX	0:85b3fd62ea1a	645	HAL_LockTypeDef Lock; /!< ETH Lock /
NYX	0:85b3fd62ea1a	646
NYX	0:85b3fd62ea1a	647	} ETH_HandleTypeDef;
NYX	0:85b3fd62ea1a	648
NYX	0:85b3fd62ea1a	649	/**
NYX	0:85b3fd62ea1a	650	* @}
NYX	0:85b3fd62ea1a	651	*/
NYX	0:85b3fd62ea1a	652
NYX	0:85b3fd62ea1a	653	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	654	/** @defgroup ETH_Exported_Constants ETH Exported Constants
NYX	0:85b3fd62ea1a	655	* @{
NYX	0:85b3fd62ea1a	656	*/
NYX	0:85b3fd62ea1a	657
NYX	0:85b3fd62ea1a	658	/** @defgroup ETH_Buffers_setting ETH Buffers setting
NYX	0:85b3fd62ea1a	659	* @{
NYX	0:85b3fd62ea1a	660	*/
NYX	0:85b3fd62ea1a	661	#define ETH_MAX_PACKET_SIZE 1524U /!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC /
NYX	0:85b3fd62ea1a	662	#define ETH_HEADER 14U /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
NYX	0:85b3fd62ea1a	663	#define ETH_CRC 4U /!< Ethernet CRC /
NYX	0:85b3fd62ea1a	664	#define ETH_EXTRA 2U /!< Extra bytes in some cases /
NYX	0:85b3fd62ea1a	665	#define ETH_VLAN_TAG 4U /!< optional 802.1q VLAN Tag /
NYX	0:85b3fd62ea1a	666	#define ETH_MIN_ETH_PAYLOAD 46U /!< Minimum Ethernet payload size /
NYX	0:85b3fd62ea1a	667	#define ETH_MAX_ETH_PAYLOAD 1500U /!< Maximum Ethernet payload size /
NYX	0:85b3fd62ea1a	668	#define ETH_JUMBO_FRAME_PAYLOAD 9000U /!< Jumbo frame payload size /
NYX	0:85b3fd62ea1a	669
NYX	0:85b3fd62ea1a	670	/* Ethernet driver receive buffers are organized in a chained linked-list, when
NYX	0:85b3fd62ea1a	671	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
NYX	0:85b3fd62ea1a	672	to the driver receive buffers memory.
NYX	0:85b3fd62ea1a	673
NYX	0:85b3fd62ea1a	674	Depending on the size of the received ethernet packet and the size of
NYX	0:85b3fd62ea1a	675	each ethernet driver receive buffer, the received packet can take one or more
NYX	0:85b3fd62ea1a	676	ethernet driver receive buffer.
NYX	0:85b3fd62ea1a	677
NYX	0:85b3fd62ea1a	678	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
NYX	0:85b3fd62ea1a	679	and the total count of the driver receive buffers ETH_RXBUFNB.
NYX	0:85b3fd62ea1a	680
NYX	0:85b3fd62ea1a	681	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
NYX	0:85b3fd62ea1a	682	example, they can be reconfigured in the application layer to fit the application
NYX	0:85b3fd62ea1a	683	needs */
NYX	0:85b3fd62ea1a	684
NYX	0:85b3fd62ea1a	685	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
NYX	0:85b3fd62ea1a	686	packet */
NYX	0:85b3fd62ea1a	687	#ifndef ETH_RX_BUF_SIZE
NYX	0:85b3fd62ea1a	688	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
NYX	0:85b3fd62ea1a	689	#endif
NYX	0:85b3fd62ea1a	690
NYX	0:85b3fd62ea1a	691	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
NYX	0:85b3fd62ea1a	692	#ifndef ETH_RXBUFNB
NYX	0:85b3fd62ea1a	693	#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
NYX	0:85b3fd62ea1a	694	#endif
NYX	0:85b3fd62ea1a	695
NYX	0:85b3fd62ea1a	696
NYX	0:85b3fd62ea1a	697	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
NYX	0:85b3fd62ea1a	698	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
NYX	0:85b3fd62ea1a	699	driver transmit buffers memory to the TxFIFO.
NYX	0:85b3fd62ea1a	700
NYX	0:85b3fd62ea1a	701	Depending on the size of the Ethernet packet to be transmitted and the size of
NYX	0:85b3fd62ea1a	702	each ethernet driver transmit buffer, the packet to be transmitted can take
NYX	0:85b3fd62ea1a	703	one or more ethernet driver transmit buffer.
NYX	0:85b3fd62ea1a	704
NYX	0:85b3fd62ea1a	705	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
NYX	0:85b3fd62ea1a	706	and the total count of the driver transmit buffers ETH_TXBUFNB.
NYX	0:85b3fd62ea1a	707
NYX	0:85b3fd62ea1a	708	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
NYX	0:85b3fd62ea1a	709	example, they can be reconfigured in the application layer to fit the application
NYX	0:85b3fd62ea1a	710	needs */
NYX	0:85b3fd62ea1a	711
NYX	0:85b3fd62ea1a	712	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
NYX	0:85b3fd62ea1a	713	packet */
NYX	0:85b3fd62ea1a	714	#ifndef ETH_TX_BUF_SIZE
NYX	0:85b3fd62ea1a	715	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
NYX	0:85b3fd62ea1a	716	#endif
NYX	0:85b3fd62ea1a	717
NYX	0:85b3fd62ea1a	718	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
NYX	0:85b3fd62ea1a	719	#ifndef ETH_TXBUFNB
NYX	0:85b3fd62ea1a	720	#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
NYX	0:85b3fd62ea1a	721	#endif
NYX	0:85b3fd62ea1a	722
NYX	0:85b3fd62ea1a	723	/**
NYX	0:85b3fd62ea1a	724	* @}
NYX	0:85b3fd62ea1a	725	*/
NYX	0:85b3fd62ea1a	726
NYX	0:85b3fd62ea1a	727	/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
NYX	0:85b3fd62ea1a	728	* @{
NYX	0:85b3fd62ea1a	729	*/
NYX	0:85b3fd62ea1a	730
NYX	0:85b3fd62ea1a	731	/*
NYX	0:85b3fd62ea1a	732	DMA Tx Descriptor
NYX	0:85b3fd62ea1a	733	-----------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	734	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
NYX	0:85b3fd62ea1a	735	-----------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	736	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
NYX	0:85b3fd62ea1a	737	-----------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	738	TDES2 \| Buffer1 Address [31:0] \|
NYX	0:85b3fd62ea1a	739	-----------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	740	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
NYX	0:85b3fd62ea1a	741	-----------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	742	*/
NYX	0:85b3fd62ea1a	743
NYX	0:85b3fd62ea1a	744	/**
NYX	0:85b3fd62ea1a	745	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
NYX	0:85b3fd62ea1a	746	*/
NYX	0:85b3fd62ea1a	747	#define ETH_DMATXDESC_OWN 0x80000000U /!< OWN bit: descriptor is owned by DMA engine /
NYX	0:85b3fd62ea1a	748	#define ETH_DMATXDESC_IC 0x40000000U /!< Interrupt on Completion /
NYX	0:85b3fd62ea1a	749	#define ETH_DMATXDESC_LS 0x20000000U /!< Last Segment /
NYX	0:85b3fd62ea1a	750	#define ETH_DMATXDESC_FS 0x10000000U /!< First Segment /
NYX	0:85b3fd62ea1a	751	#define ETH_DMATXDESC_DC 0x08000000U /!< Disable CRC /
NYX	0:85b3fd62ea1a	752	#define ETH_DMATXDESC_DP 0x04000000U /!< Disable Padding /
NYX	0:85b3fd62ea1a	753	#define ETH_DMATXDESC_TTSE 0x02000000U /!< Transmit Time Stamp Enable /
NYX	0:85b3fd62ea1a	754	#define ETH_DMATXDESC_CIC 0x00C00000U /!< Checksum Insertion Control: 4 cases /
NYX	0:85b3fd62ea1a	755	#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /!< Do Nothing: Checksum Engine is bypassed /
NYX	0:85b3fd62ea1a	756	#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /!< IPV4 header Checksum Insertion /
NYX	0:85b3fd62ea1a	757	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
NYX	0:85b3fd62ea1a	758	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
NYX	0:85b3fd62ea1a	759	#define ETH_DMATXDESC_TER 0x00200000U /!< Transmit End of Ring /
NYX	0:85b3fd62ea1a	760	#define ETH_DMATXDESC_TCH 0x00100000U /!< Second Address Chained /
NYX	0:85b3fd62ea1a	761	#define ETH_DMATXDESC_TTSS 0x00020000U /!< Tx Time Stamp Status /
NYX	0:85b3fd62ea1a	762	#define ETH_DMATXDESC_IHE 0x00010000U /!< IP Header Error /
NYX	0:85b3fd62ea1a	763	#define ETH_DMATXDESC_ES 0x00008000U /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
NYX	0:85b3fd62ea1a	764	#define ETH_DMATXDESC_JT 0x00004000U /!< Jabber Timeout /
NYX	0:85b3fd62ea1a	765	#define ETH_DMATXDESC_FF 0x00002000U /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
NYX	0:85b3fd62ea1a	766	#define ETH_DMATXDESC_PCE 0x00001000U /!< Payload Checksum Error /
NYX	0:85b3fd62ea1a	767	#define ETH_DMATXDESC_LCA 0x00000800U /!< Loss of Carrier: carrier lost during transmission /
NYX	0:85b3fd62ea1a	768	#define ETH_DMATXDESC_NC 0x00000400U /!< No Carrier: no carrier signal from the transceiver /
NYX	0:85b3fd62ea1a	769	#define ETH_DMATXDESC_LCO 0x00000200U /!< Late Collision: transmission aborted due to collision /
NYX	0:85b3fd62ea1a	770	#define ETH_DMATXDESC_EC 0x00000100U /!< Excessive Collision: transmission aborted after 16 collisions /
NYX	0:85b3fd62ea1a	771	#define ETH_DMATXDESC_VF 0x00000080U /!< VLAN Frame /
NYX	0:85b3fd62ea1a	772	#define ETH_DMATXDESC_CC 0x00000078U /!< Collision Count /
NYX	0:85b3fd62ea1a	773	#define ETH_DMATXDESC_ED 0x00000004U /!< Excessive Deferral /
NYX	0:85b3fd62ea1a	774	#define ETH_DMATXDESC_UF 0x00000002U /!< Underflow Error: late data arrival from the memory /
NYX	0:85b3fd62ea1a	775	#define ETH_DMATXDESC_DB 0x00000001U /!< Deferred Bit /
NYX	0:85b3fd62ea1a	776
NYX	0:85b3fd62ea1a	777	/**
NYX	0:85b3fd62ea1a	778	* @brief Bit definition of TDES1 register
NYX	0:85b3fd62ea1a	779	*/
NYX	0:85b3fd62ea1a	780	#define ETH_DMATXDESC_TBS2 0x1FFF0000U /!< Transmit Buffer2 Size /
NYX	0:85b3fd62ea1a	781	#define ETH_DMATXDESC_TBS1 0x00001FFFU /!< Transmit Buffer1 Size /
NYX	0:85b3fd62ea1a	782
NYX	0:85b3fd62ea1a	783	/**
NYX	0:85b3fd62ea1a	784	* @brief Bit definition of TDES2 register
NYX	0:85b3fd62ea1a	785	*/
NYX	0:85b3fd62ea1a	786	#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /!< Buffer1 Address Pointer /
NYX	0:85b3fd62ea1a	787
NYX	0:85b3fd62ea1a	788	/**
NYX	0:85b3fd62ea1a	789	* @brief Bit definition of TDES3 register
NYX	0:85b3fd62ea1a	790	*/
NYX	0:85b3fd62ea1a	791	#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /!< Buffer2 Address Pointer /
NYX	0:85b3fd62ea1a	792
NYX	0:85b3fd62ea1a	793	/*---------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	794	TDES6 \| Transmit Time Stamp Low [31:0] \|
NYX	0:85b3fd62ea1a	795	-----------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	796	TDES7 \| Transmit Time Stamp High [31:0] \|
NYX	0:85b3fd62ea1a	797	----------------------------------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	798
NYX	0:85b3fd62ea1a	799	/* Bit definition of TDES6 register */
NYX	0:85b3fd62ea1a	800	#define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
NYX	0:85b3fd62ea1a	801
NYX	0:85b3fd62ea1a	802	/* Bit definition of TDES7 register */
NYX	0:85b3fd62ea1a	803	#define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
NYX	0:85b3fd62ea1a	804
NYX	0:85b3fd62ea1a	805	/**
NYX	0:85b3fd62ea1a	806	* @}
NYX	0:85b3fd62ea1a	807	*/
NYX	0:85b3fd62ea1a	808	/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
NYX	0:85b3fd62ea1a	809	* @{
NYX	0:85b3fd62ea1a	810	*/
NYX	0:85b3fd62ea1a	811
NYX	0:85b3fd62ea1a	812	/*
NYX	0:85b3fd62ea1a	813	DMA Rx Descriptor
NYX	0:85b3fd62ea1a	814	--------------------------------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	815	RDES0 \| OWN(31) \| Status [30:0] \|
NYX	0:85b3fd62ea1a	816	---------------------------------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	817	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
NYX	0:85b3fd62ea1a	818	---------------------------------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	819	RDES2 \| Buffer1 Address [31:0] \|
NYX	0:85b3fd62ea1a	820	---------------------------------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	821	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
NYX	0:85b3fd62ea1a	822	---------------------------------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	823	*/
NYX	0:85b3fd62ea1a	824
NYX	0:85b3fd62ea1a	825	/**
NYX	0:85b3fd62ea1a	826	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
NYX	0:85b3fd62ea1a	827	*/
NYX	0:85b3fd62ea1a	828	#define ETH_DMARXDESC_OWN 0x80000000U /!< OWN bit: descriptor is owned by DMA engine /
NYX	0:85b3fd62ea1a	829	#define ETH_DMARXDESC_AFM 0x40000000U /!< DA Filter Fail for the rx frame /
NYX	0:85b3fd62ea1a	830	#define ETH_DMARXDESC_FL 0x3FFF0000U /!< Receive descriptor frame length /
NYX	0:85b3fd62ea1a	831	#define ETH_DMARXDESC_ES 0x00008000U /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
NYX	0:85b3fd62ea1a	832	#define ETH_DMARXDESC_DE 0x00004000U /!< Descriptor error: no more descriptors for receive frame /
NYX	0:85b3fd62ea1a	833	#define ETH_DMARXDESC_SAF 0x00002000U /!< SA Filter Fail for the received frame /
NYX	0:85b3fd62ea1a	834	#define ETH_DMARXDESC_LE 0x00001000U /!< Frame size not matching with length field /
NYX	0:85b3fd62ea1a	835	#define ETH_DMARXDESC_OE 0x00000800U /!< Overflow Error: Frame was damaged due to buffer overflow /
NYX	0:85b3fd62ea1a	836	#define ETH_DMARXDESC_VLAN 0x00000400U /!< VLAN Tag: received frame is a VLAN frame /
NYX	0:85b3fd62ea1a	837	#define ETH_DMARXDESC_FS 0x00000200U /!< First descriptor of the frame /
NYX	0:85b3fd62ea1a	838	#define ETH_DMARXDESC_LS 0x00000100U /!< Last descriptor of the frame /
NYX	0:85b3fd62ea1a	839	#define ETH_DMARXDESC_IPV4HCE 0x00000080U /!< IPC Checksum Error: Rx Ipv4 header checksum error /
NYX	0:85b3fd62ea1a	840	#define ETH_DMARXDESC_LC 0x00000040U /!< Late collision occurred during reception /
NYX	0:85b3fd62ea1a	841	#define ETH_DMARXDESC_FT 0x00000020U /!< Frame type - Ethernet, otherwise 802.3 /
NYX	0:85b3fd62ea1a	842	#define ETH_DMARXDESC_RWT 0x00000010U /!< Receive Watchdog Timeout: watchdog timer expired during reception /
NYX	0:85b3fd62ea1a	843	#define ETH_DMARXDESC_RE 0x00000008U /!< Receive error: error reported by MII interface /
NYX	0:85b3fd62ea1a	844	#define ETH_DMARXDESC_DBE 0x00000004U /!< Dribble bit error: frame contains non int multiple of 8 bits /
NYX	0:85b3fd62ea1a	845	#define ETH_DMARXDESC_CE 0x00000002U /!< CRC error /
NYX	0:85b3fd62ea1a	846	#define ETH_DMARXDESC_MAMPCE 0x00000001U /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
NYX	0:85b3fd62ea1a	847
NYX	0:85b3fd62ea1a	848	/**
NYX	0:85b3fd62ea1a	849	* @brief Bit definition of RDES1 register
NYX	0:85b3fd62ea1a	850	*/
NYX	0:85b3fd62ea1a	851	#define ETH_DMARXDESC_DIC 0x80000000U /!< Disable Interrupt on Completion /
NYX	0:85b3fd62ea1a	852	#define ETH_DMARXDESC_RBS2 0x1FFF0000U /!< Receive Buffer2 Size /
NYX	0:85b3fd62ea1a	853	#define ETH_DMARXDESC_RER 0x00008000U /!< Receive End of Ring /
NYX	0:85b3fd62ea1a	854	#define ETH_DMARXDESC_RCH 0x00004000U /!< Second Address Chained /
NYX	0:85b3fd62ea1a	855	#define ETH_DMARXDESC_RBS1 0x00001FFFU /!< Receive Buffer1 Size /
NYX	0:85b3fd62ea1a	856
NYX	0:85b3fd62ea1a	857	/**
NYX	0:85b3fd62ea1a	858	* @brief Bit definition of RDES2 register
NYX	0:85b3fd62ea1a	859	*/
NYX	0:85b3fd62ea1a	860	#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /!< Buffer1 Address Pointer /
NYX	0:85b3fd62ea1a	861
NYX	0:85b3fd62ea1a	862	/**
NYX	0:85b3fd62ea1a	863	* @brief Bit definition of RDES3 register
NYX	0:85b3fd62ea1a	864	*/
NYX	0:85b3fd62ea1a	865	#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /!< Buffer2 Address Pointer /
NYX	0:85b3fd62ea1a	866
NYX	0:85b3fd62ea1a	867	/*---------------------------------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	868	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
NYX	0:85b3fd62ea1a	869	---------------------------------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	870	RDES5 \| Reserved[31:0] \|
NYX	0:85b3fd62ea1a	871	---------------------------------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	872	RDES6 \| Receive Time Stamp Low [31:0] \|
NYX	0:85b3fd62ea1a	873	---------------------------------------------------------------------------------------------------------------------
NYX	0:85b3fd62ea1a	874	RDES7 \| Receive Time Stamp High [31:0] \|
NYX	0:85b3fd62ea1a	875	--------------------------------------------------------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	876
NYX	0:85b3fd62ea1a	877	/* Bit definition of RDES4 register */
NYX	0:85b3fd62ea1a	878	#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
NYX	0:85b3fd62ea1a	879	#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
NYX	0:85b3fd62ea1a	880	#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
NYX	0:85b3fd62ea1a	881	#define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
NYX	0:85b3fd62ea1a	882	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
NYX	0:85b3fd62ea1a	883	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
NYX	0:85b3fd62ea1a	884	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
NYX	0:85b3fd62ea1a	885	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
NYX	0:85b3fd62ea1a	886	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
NYX	0:85b3fd62ea1a	887	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
NYX	0:85b3fd62ea1a	888	#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
NYX	0:85b3fd62ea1a	889	#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
NYX	0:85b3fd62ea1a	890	#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
NYX	0:85b3fd62ea1a	891	#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
NYX	0:85b3fd62ea1a	892	#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
NYX	0:85b3fd62ea1a	893	#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
NYX	0:85b3fd62ea1a	894	#define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
NYX	0:85b3fd62ea1a	895	#define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
NYX	0:85b3fd62ea1a	896	#define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
NYX	0:85b3fd62ea1a	897
NYX	0:85b3fd62ea1a	898	/* Bit definition of RDES6 register */
NYX	0:85b3fd62ea1a	899	#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
NYX	0:85b3fd62ea1a	900
NYX	0:85b3fd62ea1a	901	/* Bit definition of RDES7 register */
NYX	0:85b3fd62ea1a	902	#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
NYX	0:85b3fd62ea1a	903	/**
NYX	0:85b3fd62ea1a	904	* @}
NYX	0:85b3fd62ea1a	905	*/
NYX	0:85b3fd62ea1a	906	/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
NYX	0:85b3fd62ea1a	907	* @{
NYX	0:85b3fd62ea1a	908	*/
NYX	0:85b3fd62ea1a	909	#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
NYX	0:85b3fd62ea1a	910	#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	911
NYX	0:85b3fd62ea1a	912	/**
NYX	0:85b3fd62ea1a	913	* @}
NYX	0:85b3fd62ea1a	914	*/
NYX	0:85b3fd62ea1a	915	/** @defgroup ETH_Speed ETH Speed
NYX	0:85b3fd62ea1a	916	* @{
NYX	0:85b3fd62ea1a	917	*/
NYX	0:85b3fd62ea1a	918	#define ETH_SPEED_10M 0x00000000U
NYX	0:85b3fd62ea1a	919	#define ETH_SPEED_100M 0x00004000U
NYX	0:85b3fd62ea1a	920
NYX	0:85b3fd62ea1a	921	/**
NYX	0:85b3fd62ea1a	922	* @}
NYX	0:85b3fd62ea1a	923	*/
NYX	0:85b3fd62ea1a	924	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
NYX	0:85b3fd62ea1a	925	* @{
NYX	0:85b3fd62ea1a	926	*/
NYX	0:85b3fd62ea1a	927	#define ETH_MODE_FULLDUPLEX 0x00000800U
NYX	0:85b3fd62ea1a	928	#define ETH_MODE_HALFDUPLEX 0x00000000U
NYX	0:85b3fd62ea1a	929	/**
NYX	0:85b3fd62ea1a	930	* @}
NYX	0:85b3fd62ea1a	931	*/
NYX	0:85b3fd62ea1a	932	/** @defgroup ETH_Rx_Mode ETH Rx Mode
NYX	0:85b3fd62ea1a	933	* @{
NYX	0:85b3fd62ea1a	934	*/
NYX	0:85b3fd62ea1a	935	#define ETH_RXPOLLING_MODE 0x00000000U
NYX	0:85b3fd62ea1a	936	#define ETH_RXINTERRUPT_MODE 0x00000001U
NYX	0:85b3fd62ea1a	937	/**
NYX	0:85b3fd62ea1a	938	* @}
NYX	0:85b3fd62ea1a	939	*/
NYX	0:85b3fd62ea1a	940
NYX	0:85b3fd62ea1a	941	/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
NYX	0:85b3fd62ea1a	942	* @{
NYX	0:85b3fd62ea1a	943	*/
NYX	0:85b3fd62ea1a	944	#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
NYX	0:85b3fd62ea1a	945	#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
NYX	0:85b3fd62ea1a	946	/**
NYX	0:85b3fd62ea1a	947	* @}
NYX	0:85b3fd62ea1a	948	*/
NYX	0:85b3fd62ea1a	949
NYX	0:85b3fd62ea1a	950	/** @defgroup ETH_Media_Interface ETH Media Interface
NYX	0:85b3fd62ea1a	951	* @{
NYX	0:85b3fd62ea1a	952	*/
NYX	0:85b3fd62ea1a	953	#define ETH_MEDIA_INTERFACE_MII 0x00000000U
NYX	0:85b3fd62ea1a	954	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
NYX	0:85b3fd62ea1a	955	/**
NYX	0:85b3fd62ea1a	956	* @}
NYX	0:85b3fd62ea1a	957	*/
NYX	0:85b3fd62ea1a	958
NYX	0:85b3fd62ea1a	959	/** @defgroup ETH_Watchdog ETH Watchdog
NYX	0:85b3fd62ea1a	960	* @{
NYX	0:85b3fd62ea1a	961	*/
NYX	0:85b3fd62ea1a	962	#define ETH_WATCHDOG_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	963	#define ETH_WATCHDOG_DISABLE 0x00800000U
NYX	0:85b3fd62ea1a	964	/**
NYX	0:85b3fd62ea1a	965	* @}
NYX	0:85b3fd62ea1a	966	*/
NYX	0:85b3fd62ea1a	967
NYX	0:85b3fd62ea1a	968	/** @defgroup ETH_Jabber ETH Jabber
NYX	0:85b3fd62ea1a	969	* @{
NYX	0:85b3fd62ea1a	970	*/
NYX	0:85b3fd62ea1a	971	#define ETH_JABBER_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	972	#define ETH_JABBER_DISABLE 0x00400000U
NYX	0:85b3fd62ea1a	973	/**
NYX	0:85b3fd62ea1a	974	* @}
NYX	0:85b3fd62ea1a	975	*/
NYX	0:85b3fd62ea1a	976
NYX	0:85b3fd62ea1a	977	/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
NYX	0:85b3fd62ea1a	978	* @{
NYX	0:85b3fd62ea1a	979	*/
NYX	0:85b3fd62ea1a	980	#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /!< minimum IFG between frames during transmission is 96Bit /
NYX	0:85b3fd62ea1a	981	#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /!< minimum IFG between frames during transmission is 88Bit /
NYX	0:85b3fd62ea1a	982	#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /!< minimum IFG between frames during transmission is 80Bit /
NYX	0:85b3fd62ea1a	983	#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /!< minimum IFG between frames during transmission is 72Bit /
NYX	0:85b3fd62ea1a	984	#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /!< minimum IFG between frames during transmission is 64Bit /
NYX	0:85b3fd62ea1a	985	#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /!< minimum IFG between frames during transmission is 56Bit /
NYX	0:85b3fd62ea1a	986	#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /!< minimum IFG between frames during transmission is 48Bit /
NYX	0:85b3fd62ea1a	987	#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /!< minimum IFG between frames during transmission is 40Bit /
NYX	0:85b3fd62ea1a	988	/**
NYX	0:85b3fd62ea1a	989	* @}
NYX	0:85b3fd62ea1a	990	*/
NYX	0:85b3fd62ea1a	991
NYX	0:85b3fd62ea1a	992	/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
NYX	0:85b3fd62ea1a	993	* @{
NYX	0:85b3fd62ea1a	994	*/
NYX	0:85b3fd62ea1a	995	#define ETH_CARRIERSENCE_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	996	#define ETH_CARRIERSENCE_DISABLE 0x00010000U
NYX	0:85b3fd62ea1a	997	/**
NYX	0:85b3fd62ea1a	998	* @}
NYX	0:85b3fd62ea1a	999	*/
NYX	0:85b3fd62ea1a	1000
NYX	0:85b3fd62ea1a	1001	/** @defgroup ETH_Receive_Own ETH Receive Own
NYX	0:85b3fd62ea1a	1002	* @{
NYX	0:85b3fd62ea1a	1003	*/
NYX	0:85b3fd62ea1a	1004	#define ETH_RECEIVEOWN_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	1005	#define ETH_RECEIVEOWN_DISABLE 0x00002000U
NYX	0:85b3fd62ea1a	1006	/**
NYX	0:85b3fd62ea1a	1007	* @}
NYX	0:85b3fd62ea1a	1008	*/
NYX	0:85b3fd62ea1a	1009
NYX	0:85b3fd62ea1a	1010	/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
NYX	0:85b3fd62ea1a	1011	* @{
NYX	0:85b3fd62ea1a	1012	*/
NYX	0:85b3fd62ea1a	1013	#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
NYX	0:85b3fd62ea1a	1014	#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1015	/**
NYX	0:85b3fd62ea1a	1016	* @}
NYX	0:85b3fd62ea1a	1017	*/
NYX	0:85b3fd62ea1a	1018
NYX	0:85b3fd62ea1a	1019	/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
NYX	0:85b3fd62ea1a	1020	* @{
NYX	0:85b3fd62ea1a	1021	*/
NYX	0:85b3fd62ea1a	1022	#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
NYX	0:85b3fd62ea1a	1023	#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1024	/**
NYX	0:85b3fd62ea1a	1025	* @}
NYX	0:85b3fd62ea1a	1026	*/
NYX	0:85b3fd62ea1a	1027
NYX	0:85b3fd62ea1a	1028	/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
NYX	0:85b3fd62ea1a	1029	* @{
NYX	0:85b3fd62ea1a	1030	*/
NYX	0:85b3fd62ea1a	1031	#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	1032	#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
NYX	0:85b3fd62ea1a	1033	/**
NYX	0:85b3fd62ea1a	1034	* @}
NYX	0:85b3fd62ea1a	1035	*/
NYX	0:85b3fd62ea1a	1036
NYX	0:85b3fd62ea1a	1037	/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
NYX	0:85b3fd62ea1a	1038	* @{
NYX	0:85b3fd62ea1a	1039	*/
NYX	0:85b3fd62ea1a	1040	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
NYX	0:85b3fd62ea1a	1041	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1042	/**
NYX	0:85b3fd62ea1a	1043	* @}
NYX	0:85b3fd62ea1a	1044	*/
NYX	0:85b3fd62ea1a	1045
NYX	0:85b3fd62ea1a	1046	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
NYX	0:85b3fd62ea1a	1047	* @{
NYX	0:85b3fd62ea1a	1048	*/
NYX	0:85b3fd62ea1a	1049	#define ETH_BACKOFFLIMIT_10 0x00000000U
NYX	0:85b3fd62ea1a	1050	#define ETH_BACKOFFLIMIT_8 0x00000020U
NYX	0:85b3fd62ea1a	1051	#define ETH_BACKOFFLIMIT_4 0x00000040U
NYX	0:85b3fd62ea1a	1052	#define ETH_BACKOFFLIMIT_1 0x00000060U
NYX	0:85b3fd62ea1a	1053	/**
NYX	0:85b3fd62ea1a	1054	* @}
NYX	0:85b3fd62ea1a	1055	*/
NYX	0:85b3fd62ea1a	1056
NYX	0:85b3fd62ea1a	1057	/** @defgroup ETH_Deferral_Check ETH Deferral Check
NYX	0:85b3fd62ea1a	1058	* @{
NYX	0:85b3fd62ea1a	1059	*/
NYX	0:85b3fd62ea1a	1060	#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
NYX	0:85b3fd62ea1a	1061	#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1062	/**
NYX	0:85b3fd62ea1a	1063	* @}
NYX	0:85b3fd62ea1a	1064	*/
NYX	0:85b3fd62ea1a	1065
NYX	0:85b3fd62ea1a	1066	/** @defgroup ETH_Receive_All ETH Receive All
NYX	0:85b3fd62ea1a	1067	* @{
NYX	0:85b3fd62ea1a	1068	*/
NYX	0:85b3fd62ea1a	1069	#define ETH_RECEIVEALL_ENABLE 0x80000000U
NYX	0:85b3fd62ea1a	1070	#define ETH_RECEIVEAll_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1071	/**
NYX	0:85b3fd62ea1a	1072	* @}
NYX	0:85b3fd62ea1a	1073	*/
NYX	0:85b3fd62ea1a	1074
NYX	0:85b3fd62ea1a	1075	/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
NYX	0:85b3fd62ea1a	1076	* @{
NYX	0:85b3fd62ea1a	1077	*/
NYX	0:85b3fd62ea1a	1078	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
NYX	0:85b3fd62ea1a	1079	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
NYX	0:85b3fd62ea1a	1080	#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1081	/**
NYX	0:85b3fd62ea1a	1082	* @}
NYX	0:85b3fd62ea1a	1083	*/
NYX	0:85b3fd62ea1a	1084
NYX	0:85b3fd62ea1a	1085	/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
NYX	0:85b3fd62ea1a	1086	* @{
NYX	0:85b3fd62ea1a	1087	*/
NYX	0:85b3fd62ea1a	1088	#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /!< MAC filters all control frames from reaching the application /
NYX	0:85b3fd62ea1a	1089	#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /!< MAC forwards all control frames to application even if they fail the Address Filter /
NYX	0:85b3fd62ea1a	1090	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /!< MAC forwards control frames that pass the Address Filter. /
NYX	0:85b3fd62ea1a	1091	/**
NYX	0:85b3fd62ea1a	1092	* @}
NYX	0:85b3fd62ea1a	1093	*/
NYX	0:85b3fd62ea1a	1094
NYX	0:85b3fd62ea1a	1095	/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
NYX	0:85b3fd62ea1a	1096	* @{
NYX	0:85b3fd62ea1a	1097	*/
NYX	0:85b3fd62ea1a	1098	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	1099	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
NYX	0:85b3fd62ea1a	1100	/**
NYX	0:85b3fd62ea1a	1101	* @}
NYX	0:85b3fd62ea1a	1102	*/
NYX	0:85b3fd62ea1a	1103
NYX	0:85b3fd62ea1a	1104	/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
NYX	0:85b3fd62ea1a	1105	* @{
NYX	0:85b3fd62ea1a	1106	*/
NYX	0:85b3fd62ea1a	1107	#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
NYX	0:85b3fd62ea1a	1108	#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
NYX	0:85b3fd62ea1a	1109	/**
NYX	0:85b3fd62ea1a	1110	* @}
NYX	0:85b3fd62ea1a	1111	*/
NYX	0:85b3fd62ea1a	1112
NYX	0:85b3fd62ea1a	1113	/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
NYX	0:85b3fd62ea1a	1114	* @{
NYX	0:85b3fd62ea1a	1115	*/
NYX	0:85b3fd62ea1a	1116	#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
NYX	0:85b3fd62ea1a	1117	#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1118	/**
NYX	0:85b3fd62ea1a	1119	* @}
NYX	0:85b3fd62ea1a	1120	*/
NYX	0:85b3fd62ea1a	1121
NYX	0:85b3fd62ea1a	1122	/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
NYX	0:85b3fd62ea1a	1123	* @{
NYX	0:85b3fd62ea1a	1124	*/
NYX	0:85b3fd62ea1a	1125	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
NYX	0:85b3fd62ea1a	1126	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
NYX	0:85b3fd62ea1a	1127	#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
NYX	0:85b3fd62ea1a	1128	#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
NYX	0:85b3fd62ea1a	1129	/**
NYX	0:85b3fd62ea1a	1130	* @}
NYX	0:85b3fd62ea1a	1131	*/
NYX	0:85b3fd62ea1a	1132
NYX	0:85b3fd62ea1a	1133	/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
NYX	0:85b3fd62ea1a	1134	* @{
NYX	0:85b3fd62ea1a	1135	*/
NYX	0:85b3fd62ea1a	1136	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
NYX	0:85b3fd62ea1a	1137	#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
NYX	0:85b3fd62ea1a	1138	#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
NYX	0:85b3fd62ea1a	1139	/**
NYX	0:85b3fd62ea1a	1140	* @}
NYX	0:85b3fd62ea1a	1141	*/
NYX	0:85b3fd62ea1a	1142
NYX	0:85b3fd62ea1a	1143	/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
NYX	0:85b3fd62ea1a	1144	* @{
NYX	0:85b3fd62ea1a	1145	*/
NYX	0:85b3fd62ea1a	1146	#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	1147	#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
NYX	0:85b3fd62ea1a	1148	/**
NYX	0:85b3fd62ea1a	1149	* @}
NYX	0:85b3fd62ea1a	1150	*/
NYX	0:85b3fd62ea1a	1151
NYX	0:85b3fd62ea1a	1152	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
NYX	0:85b3fd62ea1a	1153	* @{
NYX	0:85b3fd62ea1a	1154	*/
NYX	0:85b3fd62ea1a	1155	#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /!< Pause time minus 4 slot times /
NYX	0:85b3fd62ea1a	1156	#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /!< Pause time minus 28 slot times /
NYX	0:85b3fd62ea1a	1157	#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /!< Pause time minus 144 slot times /
NYX	0:85b3fd62ea1a	1158	#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /!< Pause time minus 256 slot times /
NYX	0:85b3fd62ea1a	1159	/**
NYX	0:85b3fd62ea1a	1160	* @}
NYX	0:85b3fd62ea1a	1161	*/
NYX	0:85b3fd62ea1a	1162
NYX	0:85b3fd62ea1a	1163	/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
NYX	0:85b3fd62ea1a	1164	* @{
NYX	0:85b3fd62ea1a	1165	*/
NYX	0:85b3fd62ea1a	1166	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
NYX	0:85b3fd62ea1a	1167	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1168	/**
NYX	0:85b3fd62ea1a	1169	* @}
NYX	0:85b3fd62ea1a	1170	*/
NYX	0:85b3fd62ea1a	1171
NYX	0:85b3fd62ea1a	1172	/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
NYX	0:85b3fd62ea1a	1173	* @{
NYX	0:85b3fd62ea1a	1174	*/
NYX	0:85b3fd62ea1a	1175	#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
NYX	0:85b3fd62ea1a	1176	#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1177	/**
NYX	0:85b3fd62ea1a	1178	* @}
NYX	0:85b3fd62ea1a	1179	*/
NYX	0:85b3fd62ea1a	1180
NYX	0:85b3fd62ea1a	1181	/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
NYX	0:85b3fd62ea1a	1182	* @{
NYX	0:85b3fd62ea1a	1183	*/
NYX	0:85b3fd62ea1a	1184	#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
NYX	0:85b3fd62ea1a	1185	#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1186	/**
NYX	0:85b3fd62ea1a	1187	* @}
NYX	0:85b3fd62ea1a	1188	*/
NYX	0:85b3fd62ea1a	1189
NYX	0:85b3fd62ea1a	1190	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
NYX	0:85b3fd62ea1a	1191	* @{
NYX	0:85b3fd62ea1a	1192	*/
NYX	0:85b3fd62ea1a	1193	#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
NYX	0:85b3fd62ea1a	1194	#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
NYX	0:85b3fd62ea1a	1195	/**
NYX	0:85b3fd62ea1a	1196	* @}
NYX	0:85b3fd62ea1a	1197	*/
NYX	0:85b3fd62ea1a	1198
NYX	0:85b3fd62ea1a	1199	/** @defgroup ETH_MAC_addresses ETH MAC addresses
NYX	0:85b3fd62ea1a	1200	* @{
NYX	0:85b3fd62ea1a	1201	*/
NYX	0:85b3fd62ea1a	1202	#define ETH_MAC_ADDRESS0 0x00000000U
NYX	0:85b3fd62ea1a	1203	#define ETH_MAC_ADDRESS1 0x00000008U
NYX	0:85b3fd62ea1a	1204	#define ETH_MAC_ADDRESS2 0x00000010U
NYX	0:85b3fd62ea1a	1205	#define ETH_MAC_ADDRESS3 0x00000018U
NYX	0:85b3fd62ea1a	1206	/**
NYX	0:85b3fd62ea1a	1207	* @}
NYX	0:85b3fd62ea1a	1208	*/
NYX	0:85b3fd62ea1a	1209
NYX	0:85b3fd62ea1a	1210	/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
NYX	0:85b3fd62ea1a	1211	* @{
NYX	0:85b3fd62ea1a	1212	*/
NYX	0:85b3fd62ea1a	1213	#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
NYX	0:85b3fd62ea1a	1214	#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
NYX	0:85b3fd62ea1a	1215	/**
NYX	0:85b3fd62ea1a	1216	* @}
NYX	0:85b3fd62ea1a	1217	*/
NYX	0:85b3fd62ea1a	1218
NYX	0:85b3fd62ea1a	1219	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
NYX	0:85b3fd62ea1a	1220	* @{
NYX	0:85b3fd62ea1a	1221	*/
NYX	0:85b3fd62ea1a	1222	#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /!< Mask MAC Address high reg bits [15:8] /
NYX	0:85b3fd62ea1a	1223	#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /!< Mask MAC Address high reg bits [7:0] /
NYX	0:85b3fd62ea1a	1224	#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /!< Mask MAC Address low reg bits [31:24] /
NYX	0:85b3fd62ea1a	1225	#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /!< Mask MAC Address low reg bits [23:16] /
NYX	0:85b3fd62ea1a	1226	#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /!< Mask MAC Address low reg bits [15:8] /
NYX	0:85b3fd62ea1a	1227	#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /!< Mask MAC Address low reg bits [70] /
NYX	0:85b3fd62ea1a	1228	/**
NYX	0:85b3fd62ea1a	1229	* @}
NYX	0:85b3fd62ea1a	1230	*/
NYX	0:85b3fd62ea1a	1231
NYX	0:85b3fd62ea1a	1232	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
NYX	0:85b3fd62ea1a	1233	* @{
NYX	0:85b3fd62ea1a	1234	*/
NYX	0:85b3fd62ea1a	1235	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	1236	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
NYX	0:85b3fd62ea1a	1237	/**
NYX	0:85b3fd62ea1a	1238	* @}
NYX	0:85b3fd62ea1a	1239	*/
NYX	0:85b3fd62ea1a	1240
NYX	0:85b3fd62ea1a	1241	/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
NYX	0:85b3fd62ea1a	1242	* @{
NYX	0:85b3fd62ea1a	1243	*/
NYX	0:85b3fd62ea1a	1244	#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
NYX	0:85b3fd62ea1a	1245	#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1246	/**
NYX	0:85b3fd62ea1a	1247	* @}
NYX	0:85b3fd62ea1a	1248	*/
NYX	0:85b3fd62ea1a	1249
NYX	0:85b3fd62ea1a	1250	/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
NYX	0:85b3fd62ea1a	1251	* @{
NYX	0:85b3fd62ea1a	1252	*/
NYX	0:85b3fd62ea1a	1253	#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	1254	#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
NYX	0:85b3fd62ea1a	1255	/**
NYX	0:85b3fd62ea1a	1256	* @}
NYX	0:85b3fd62ea1a	1257	*/
NYX	0:85b3fd62ea1a	1258
NYX	0:85b3fd62ea1a	1259	/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
NYX	0:85b3fd62ea1a	1260	* @{
NYX	0:85b3fd62ea1a	1261	*/
NYX	0:85b3fd62ea1a	1262	#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
NYX	0:85b3fd62ea1a	1263	#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1264	/**
NYX	0:85b3fd62ea1a	1265	* @}
NYX	0:85b3fd62ea1a	1266	*/
NYX	0:85b3fd62ea1a	1267
NYX	0:85b3fd62ea1a	1268	/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
NYX	0:85b3fd62ea1a	1269	* @{
NYX	0:85b3fd62ea1a	1270	*/
NYX	0:85b3fd62ea1a	1271	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
NYX	0:85b3fd62ea1a	1272	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
NYX	0:85b3fd62ea1a	1273	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
NYX	0:85b3fd62ea1a	1274	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
NYX	0:85b3fd62ea1a	1275	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
NYX	0:85b3fd62ea1a	1276	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
NYX	0:85b3fd62ea1a	1277	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
NYX	0:85b3fd62ea1a	1278	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
NYX	0:85b3fd62ea1a	1279	/**
NYX	0:85b3fd62ea1a	1280	* @}
NYX	0:85b3fd62ea1a	1281	*/
NYX	0:85b3fd62ea1a	1282
NYX	0:85b3fd62ea1a	1283	/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
NYX	0:85b3fd62ea1a	1284	* @{
NYX	0:85b3fd62ea1a	1285	*/
NYX	0:85b3fd62ea1a	1286	#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
NYX	0:85b3fd62ea1a	1287	#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1288	/**
NYX	0:85b3fd62ea1a	1289	* @}
NYX	0:85b3fd62ea1a	1290	*/
NYX	0:85b3fd62ea1a	1291
NYX	0:85b3fd62ea1a	1292	/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
NYX	0:85b3fd62ea1a	1293	* @{
NYX	0:85b3fd62ea1a	1294	*/
NYX	0:85b3fd62ea1a	1295	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
NYX	0:85b3fd62ea1a	1296	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1297	/**
NYX	0:85b3fd62ea1a	1298	* @}
NYX	0:85b3fd62ea1a	1299	*/
NYX	0:85b3fd62ea1a	1300
NYX	0:85b3fd62ea1a	1301	/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
NYX	0:85b3fd62ea1a	1302	* @{
NYX	0:85b3fd62ea1a	1303	*/
NYX	0:85b3fd62ea1a	1304	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /!< threshold level of the MTL Receive FIFO is 64 Bytes /
NYX	0:85b3fd62ea1a	1305	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /!< threshold level of the MTL Receive FIFO is 32 Bytes /
NYX	0:85b3fd62ea1a	1306	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /!< threshold level of the MTL Receive FIFO is 96 Bytes /
NYX	0:85b3fd62ea1a	1307	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /!< threshold level of the MTL Receive FIFO is 128 Bytes /
NYX	0:85b3fd62ea1a	1308	/**
NYX	0:85b3fd62ea1a	1309	* @}
NYX	0:85b3fd62ea1a	1310	*/
NYX	0:85b3fd62ea1a	1311
NYX	0:85b3fd62ea1a	1312	/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
NYX	0:85b3fd62ea1a	1313	* @{
NYX	0:85b3fd62ea1a	1314	*/
NYX	0:85b3fd62ea1a	1315	#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
NYX	0:85b3fd62ea1a	1316	#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1317	/**
NYX	0:85b3fd62ea1a	1318	* @}
NYX	0:85b3fd62ea1a	1319	*/
NYX	0:85b3fd62ea1a	1320
NYX	0:85b3fd62ea1a	1321	/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
NYX	0:85b3fd62ea1a	1322	* @{
NYX	0:85b3fd62ea1a	1323	*/
NYX	0:85b3fd62ea1a	1324	#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
NYX	0:85b3fd62ea1a	1325	#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1326	/**
NYX	0:85b3fd62ea1a	1327	* @}
NYX	0:85b3fd62ea1a	1328	*/
NYX	0:85b3fd62ea1a	1329
NYX	0:85b3fd62ea1a	1330	/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
NYX	0:85b3fd62ea1a	1331	* @{
NYX	0:85b3fd62ea1a	1332	*/
NYX	0:85b3fd62ea1a	1333	#define ETH_FIXEDBURST_ENABLE 0x00010000U
NYX	0:85b3fd62ea1a	1334	#define ETH_FIXEDBURST_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1335	/**
NYX	0:85b3fd62ea1a	1336	* @}
NYX	0:85b3fd62ea1a	1337	*/
NYX	0:85b3fd62ea1a	1338
NYX	0:85b3fd62ea1a	1339	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
NYX	0:85b3fd62ea1a	1340	* @{
NYX	0:85b3fd62ea1a	1341	*/
NYX	0:85b3fd62ea1a	1342	#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
NYX	0:85b3fd62ea1a	1343	#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
NYX	0:85b3fd62ea1a	1344	#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
NYX	0:85b3fd62ea1a	1345	#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
NYX	0:85b3fd62ea1a	1346	#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
NYX	0:85b3fd62ea1a	1347	#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
NYX	0:85b3fd62ea1a	1348	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
NYX	0:85b3fd62ea1a	1349	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
NYX	0:85b3fd62ea1a	1350	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
NYX	0:85b3fd62ea1a	1351	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
NYX	0:85b3fd62ea1a	1352	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
NYX	0:85b3fd62ea1a	1353	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
NYX	0:85b3fd62ea1a	1354	/**
NYX	0:85b3fd62ea1a	1355	* @}
NYX	0:85b3fd62ea1a	1356	*/
NYX	0:85b3fd62ea1a	1357
NYX	0:85b3fd62ea1a	1358	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
NYX	0:85b3fd62ea1a	1359	* @{
NYX	0:85b3fd62ea1a	1360	*/
NYX	0:85b3fd62ea1a	1361	#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
NYX	0:85b3fd62ea1a	1362	#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
NYX	0:85b3fd62ea1a	1363	#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
NYX	0:85b3fd62ea1a	1364	#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
NYX	0:85b3fd62ea1a	1365	#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
NYX	0:85b3fd62ea1a	1366	#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
NYX	0:85b3fd62ea1a	1367	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
NYX	0:85b3fd62ea1a	1368	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
NYX	0:85b3fd62ea1a	1369	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
NYX	0:85b3fd62ea1a	1370	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
NYX	0:85b3fd62ea1a	1371	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
NYX	0:85b3fd62ea1a	1372	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
NYX	0:85b3fd62ea1a	1373	/**
NYX	0:85b3fd62ea1a	1374	* @}
NYX	0:85b3fd62ea1a	1375	*/
NYX	0:85b3fd62ea1a	1376
NYX	0:85b3fd62ea1a	1377	/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
NYX	0:85b3fd62ea1a	1378	* @{
NYX	0:85b3fd62ea1a	1379	*/
NYX	0:85b3fd62ea1a	1380	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
NYX	0:85b3fd62ea1a	1381	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	1382	/**
NYX	0:85b3fd62ea1a	1383	* @}
NYX	0:85b3fd62ea1a	1384	*/
NYX	0:85b3fd62ea1a	1385
NYX	0:85b3fd62ea1a	1386	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
NYX	0:85b3fd62ea1a	1387	* @{
NYX	0:85b3fd62ea1a	1388	*/
NYX	0:85b3fd62ea1a	1389	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
NYX	0:85b3fd62ea1a	1390	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
NYX	0:85b3fd62ea1a	1391	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
NYX	0:85b3fd62ea1a	1392	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
NYX	0:85b3fd62ea1a	1393	#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
NYX	0:85b3fd62ea1a	1394	/**
NYX	0:85b3fd62ea1a	1395	* @}
NYX	0:85b3fd62ea1a	1396	*/
NYX	0:85b3fd62ea1a	1397
NYX	0:85b3fd62ea1a	1398	/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
NYX	0:85b3fd62ea1a	1399	* @{
NYX	0:85b3fd62ea1a	1400	*/
NYX	0:85b3fd62ea1a	1401	#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /!< Last Segment /
NYX	0:85b3fd62ea1a	1402	#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /!< First Segment /
NYX	0:85b3fd62ea1a	1403	/**
NYX	0:85b3fd62ea1a	1404	* @}
NYX	0:85b3fd62ea1a	1405	*/
NYX	0:85b3fd62ea1a	1406
NYX	0:85b3fd62ea1a	1407	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
NYX	0:85b3fd62ea1a	1408	* @{
NYX	0:85b3fd62ea1a	1409	*/
NYX	0:85b3fd62ea1a	1410	#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /!< Checksum engine bypass /
NYX	0:85b3fd62ea1a	1411	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /!< IPv4 header checksum insertion /
NYX	0:85b3fd62ea1a	1412	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
NYX	0:85b3fd62ea1a	1413	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
NYX	0:85b3fd62ea1a	1414	/**
NYX	0:85b3fd62ea1a	1415	* @}
NYX	0:85b3fd62ea1a	1416	*/
NYX	0:85b3fd62ea1a	1417
NYX	0:85b3fd62ea1a	1418	/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
NYX	0:85b3fd62ea1a	1419	* @{
NYX	0:85b3fd62ea1a	1420	*/
NYX	0:85b3fd62ea1a	1421	#define ETH_DMARXDESC_BUFFER1 0x00000000U /!< DMA Rx Desc Buffer1 /
NYX	0:85b3fd62ea1a	1422	#define ETH_DMARXDESC_BUFFER2 0x00000001U /!< DMA Rx Desc Buffer2 /
NYX	0:85b3fd62ea1a	1423	/**
NYX	0:85b3fd62ea1a	1424	* @}
NYX	0:85b3fd62ea1a	1425	*/
NYX	0:85b3fd62ea1a	1426
NYX	0:85b3fd62ea1a	1427	/** @defgroup ETH_PMT_Flags ETH PMT Flags
NYX	0:85b3fd62ea1a	1428	* @{
NYX	0:85b3fd62ea1a	1429	*/
NYX	0:85b3fd62ea1a	1430	#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /!< Wake-Up Frame Filter Register Pointer Reset /
NYX	0:85b3fd62ea1a	1431	#define ETH_PMT_FLAG_WUFR 0x00000040U /!< Wake-Up Frame Received /
NYX	0:85b3fd62ea1a	1432	#define ETH_PMT_FLAG_MPR 0x00000020U /!< Magic Packet Received /
NYX	0:85b3fd62ea1a	1433	/**
NYX	0:85b3fd62ea1a	1434	* @}
NYX	0:85b3fd62ea1a	1435	*/
NYX	0:85b3fd62ea1a	1436
NYX	0:85b3fd62ea1a	1437	/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
NYX	0:85b3fd62ea1a	1438	* @{
NYX	0:85b3fd62ea1a	1439	*/
NYX	0:85b3fd62ea1a	1440	#define ETH_MMC_IT_TGF 0x00200000U /!< When Tx good frame counter reaches half the maximum value /
NYX	0:85b3fd62ea1a	1441	#define ETH_MMC_IT_TGFMSC 0x00008000U /!< When Tx good multi col counter reaches half the maximum value /
NYX	0:85b3fd62ea1a	1442	#define ETH_MMC_IT_TGFSC 0x00004000U /!< When Tx good single col counter reaches half the maximum value /
NYX	0:85b3fd62ea1a	1443	/**
NYX	0:85b3fd62ea1a	1444	* @}
NYX	0:85b3fd62ea1a	1445	*/
NYX	0:85b3fd62ea1a	1446
NYX	0:85b3fd62ea1a	1447	/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
NYX	0:85b3fd62ea1a	1448	* @{
NYX	0:85b3fd62ea1a	1449	*/
NYX	0:85b3fd62ea1a	1450	#define ETH_MMC_IT_RGUF 0x10020000U /!< When Rx good unicast frames counter reaches half the maximum value /
NYX	0:85b3fd62ea1a	1451	#define ETH_MMC_IT_RFAE 0x10000040U /!< When Rx alignment error counter reaches half the maximum value /
NYX	0:85b3fd62ea1a	1452	#define ETH_MMC_IT_RFCE 0x10000020U /!< When Rx crc error counter reaches half the maximum value /
NYX	0:85b3fd62ea1a	1453	/**
NYX	0:85b3fd62ea1a	1454	* @}
NYX	0:85b3fd62ea1a	1455	*/
NYX	0:85b3fd62ea1a	1456
NYX	0:85b3fd62ea1a	1457	/** @defgroup ETH_MAC_Flags ETH MAC Flags
NYX	0:85b3fd62ea1a	1458	* @{
NYX	0:85b3fd62ea1a	1459	*/
NYX	0:85b3fd62ea1a	1460	#define ETH_MAC_FLAG_TST 0x00000200U /!< Time stamp trigger flag (on MAC) /
NYX	0:85b3fd62ea1a	1461	#define ETH_MAC_FLAG_MMCT 0x00000040U /!< MMC transmit flag /
NYX	0:85b3fd62ea1a	1462	#define ETH_MAC_FLAG_MMCR 0x00000020U /!< MMC receive flag /
NYX	0:85b3fd62ea1a	1463	#define ETH_MAC_FLAG_MMC 0x00000010U /!< MMC flag (on MAC) /
NYX	0:85b3fd62ea1a	1464	#define ETH_MAC_FLAG_PMT 0x00000008U /!< PMT flag (on MAC) /
NYX	0:85b3fd62ea1a	1465	/**
NYX	0:85b3fd62ea1a	1466	* @}
NYX	0:85b3fd62ea1a	1467	*/
NYX	0:85b3fd62ea1a	1468
NYX	0:85b3fd62ea1a	1469	/** @defgroup ETH_DMA_Flags ETH DMA Flags
NYX	0:85b3fd62ea1a	1470	* @{
NYX	0:85b3fd62ea1a	1471	*/
NYX	0:85b3fd62ea1a	1472	#define ETH_DMA_FLAG_TST 0x20000000U /!< Time-stamp trigger interrupt (on DMA) /
NYX	0:85b3fd62ea1a	1473	#define ETH_DMA_FLAG_PMT 0x10000000U /!< PMT interrupt (on DMA) /
NYX	0:85b3fd62ea1a	1474	#define ETH_DMA_FLAG_MMC 0x08000000U /!< MMC interrupt (on DMA) /
NYX	0:85b3fd62ea1a	1475	#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /!< Error bits 0-Rx DMA, 1-Tx DMA /
NYX	0:85b3fd62ea1a	1476	#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /!< Error bits 0-write transfer, 1-read transfer /
NYX	0:85b3fd62ea1a	1477	#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /!< Error bits 0-data buffer, 1-desc. access /
NYX	0:85b3fd62ea1a	1478	#define ETH_DMA_FLAG_NIS 0x00010000U /!< Normal interrupt summary flag /
NYX	0:85b3fd62ea1a	1479	#define ETH_DMA_FLAG_AIS 0x00008000U /!< Abnormal interrupt summary flag /
NYX	0:85b3fd62ea1a	1480	#define ETH_DMA_FLAG_ER 0x00004000U /!< Early receive flag /
NYX	0:85b3fd62ea1a	1481	#define ETH_DMA_FLAG_FBE 0x00002000U /!< Fatal bus error flag /
NYX	0:85b3fd62ea1a	1482	#define ETH_DMA_FLAG_ET 0x00000400U /!< Early transmit flag /
NYX	0:85b3fd62ea1a	1483	#define ETH_DMA_FLAG_RWT 0x00000200U /!< Receive watchdog timeout flag /
NYX	0:85b3fd62ea1a	1484	#define ETH_DMA_FLAG_RPS 0x00000100U /!< Receive process stopped flag /
NYX	0:85b3fd62ea1a	1485	#define ETH_DMA_FLAG_RBU 0x00000080U /!< Receive buffer unavailable flag /
NYX	0:85b3fd62ea1a	1486	#define ETH_DMA_FLAG_R 0x00000040U /!< Receive flag /
NYX	0:85b3fd62ea1a	1487	#define ETH_DMA_FLAG_TU 0x00000020U /!< Underflow flag /
NYX	0:85b3fd62ea1a	1488	#define ETH_DMA_FLAG_RO 0x00000010U /!< Overflow flag /
NYX	0:85b3fd62ea1a	1489	#define ETH_DMA_FLAG_TJT 0x00000008U /!< Transmit jabber timeout flag /
NYX	0:85b3fd62ea1a	1490	#define ETH_DMA_FLAG_TBU 0x00000004U /!< Transmit buffer unavailable flag /
NYX	0:85b3fd62ea1a	1491	#define ETH_DMA_FLAG_TPS 0x00000002U /!< Transmit process stopped flag /
NYX	0:85b3fd62ea1a	1492	#define ETH_DMA_FLAG_T 0x00000001U /!< Transmit flag /
NYX	0:85b3fd62ea1a	1493	/**
NYX	0:85b3fd62ea1a	1494	* @}
NYX	0:85b3fd62ea1a	1495	*/
NYX	0:85b3fd62ea1a	1496
NYX	0:85b3fd62ea1a	1497	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
NYX	0:85b3fd62ea1a	1498	* @{
NYX	0:85b3fd62ea1a	1499	*/
NYX	0:85b3fd62ea1a	1500	#define ETH_MAC_IT_TST 0x00000200U /!< Time stamp trigger interrupt (on MAC) /
NYX	0:85b3fd62ea1a	1501	#define ETH_MAC_IT_MMCT 0x00000040U /!< MMC transmit interrupt /
NYX	0:85b3fd62ea1a	1502	#define ETH_MAC_IT_MMCR 0x00000020U /!< MMC receive interrupt /
NYX	0:85b3fd62ea1a	1503	#define ETH_MAC_IT_MMC 0x00000010U /!< MMC interrupt (on MAC) /
NYX	0:85b3fd62ea1a	1504	#define ETH_MAC_IT_PMT 0x00000008U /!< PMT interrupt (on MAC) /
NYX	0:85b3fd62ea1a	1505	/**
NYX	0:85b3fd62ea1a	1506	* @}
NYX	0:85b3fd62ea1a	1507	*/
NYX	0:85b3fd62ea1a	1508
NYX	0:85b3fd62ea1a	1509	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
NYX	0:85b3fd62ea1a	1510	* @{
NYX	0:85b3fd62ea1a	1511	*/
NYX	0:85b3fd62ea1a	1512	#define ETH_DMA_IT_TST 0x20000000U /!< Time-stamp trigger interrupt (on DMA) /
NYX	0:85b3fd62ea1a	1513	#define ETH_DMA_IT_PMT 0x10000000U /!< PMT interrupt (on DMA) /
NYX	0:85b3fd62ea1a	1514	#define ETH_DMA_IT_MMC 0x08000000U /!< MMC interrupt (on DMA) /
NYX	0:85b3fd62ea1a	1515	#define ETH_DMA_IT_NIS 0x00010000U /!< Normal interrupt summary /
NYX	0:85b3fd62ea1a	1516	#define ETH_DMA_IT_AIS 0x00008000U /!< Abnormal interrupt summary /
NYX	0:85b3fd62ea1a	1517	#define ETH_DMA_IT_ER 0x00004000U /!< Early receive interrupt /
NYX	0:85b3fd62ea1a	1518	#define ETH_DMA_IT_FBE 0x00002000U /!< Fatal bus error interrupt /
NYX	0:85b3fd62ea1a	1519	#define ETH_DMA_IT_ET 0x00000400U /!< Early transmit interrupt /
NYX	0:85b3fd62ea1a	1520	#define ETH_DMA_IT_RWT 0x00000200U /!< Receive watchdog timeout interrupt /
NYX	0:85b3fd62ea1a	1521	#define ETH_DMA_IT_RPS 0x00000100U /!< Receive process stopped interrupt /
NYX	0:85b3fd62ea1a	1522	#define ETH_DMA_IT_RBU 0x00000080U /!< Receive buffer unavailable interrupt /
NYX	0:85b3fd62ea1a	1523	#define ETH_DMA_IT_R 0x00000040U /!< Receive interrupt /
NYX	0:85b3fd62ea1a	1524	#define ETH_DMA_IT_TU 0x00000020U /!< Underflow interrupt /
NYX	0:85b3fd62ea1a	1525	#define ETH_DMA_IT_RO 0x00000010U /!< Overflow interrupt /
NYX	0:85b3fd62ea1a	1526	#define ETH_DMA_IT_TJT 0x00000008U /!< Transmit jabber timeout interrupt /
NYX	0:85b3fd62ea1a	1527	#define ETH_DMA_IT_TBU 0x00000004U /!< Transmit buffer unavailable interrupt /
NYX	0:85b3fd62ea1a	1528	#define ETH_DMA_IT_TPS 0x00000002U /!< Transmit process stopped interrupt /
NYX	0:85b3fd62ea1a	1529	#define ETH_DMA_IT_T 0x00000001U /!< Transmit interrupt /
NYX	0:85b3fd62ea1a	1530	/**
NYX	0:85b3fd62ea1a	1531	* @}
NYX	0:85b3fd62ea1a	1532	*/
NYX	0:85b3fd62ea1a	1533
NYX	0:85b3fd62ea1a	1534	/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
NYX	0:85b3fd62ea1a	1535	* @{
NYX	0:85b3fd62ea1a	1536	*/
NYX	0:85b3fd62ea1a	1537	#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /!< Stopped - Reset or Stop Tx Command issued /
NYX	0:85b3fd62ea1a	1538	#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /!< Running - fetching the Tx descriptor /
NYX	0:85b3fd62ea1a	1539	#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /!< Running - waiting for status /
NYX	0:85b3fd62ea1a	1540	#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /!< Running - reading the data from host memory /
NYX	0:85b3fd62ea1a	1541	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /!< Suspended - Tx Descriptor unavailable /
NYX	0:85b3fd62ea1a	1542	#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /!< Running - closing Rx descriptor /
NYX	0:85b3fd62ea1a	1543
NYX	0:85b3fd62ea1a	1544	/**
NYX	0:85b3fd62ea1a	1545	* @}
NYX	0:85b3fd62ea1a	1546	*/
NYX	0:85b3fd62ea1a	1547
NYX	0:85b3fd62ea1a	1548
NYX	0:85b3fd62ea1a	1549	/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
NYX	0:85b3fd62ea1a	1550	* @{
NYX	0:85b3fd62ea1a	1551	*/
NYX	0:85b3fd62ea1a	1552	#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /!< Stopped - Reset or Stop Rx Command issued /
NYX	0:85b3fd62ea1a	1553	#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /!< Running - fetching the Rx descriptor /
NYX	0:85b3fd62ea1a	1554	#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /!< Running - waiting for packet /
NYX	0:85b3fd62ea1a	1555	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /!< Suspended - Rx Descriptor unavailable /
NYX	0:85b3fd62ea1a	1556	#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /!< Running - closing descriptor /
NYX	0:85b3fd62ea1a	1557	#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /!< Running - queuing the receive frame into host memory /
NYX	0:85b3fd62ea1a	1558
NYX	0:85b3fd62ea1a	1559	/**
NYX	0:85b3fd62ea1a	1560	* @}
NYX	0:85b3fd62ea1a	1561	*/
NYX	0:85b3fd62ea1a	1562
NYX	0:85b3fd62ea1a	1563	/** @defgroup ETH_DMA_overflow ETH DMA overflow
NYX	0:85b3fd62ea1a	1564	* @{
NYX	0:85b3fd62ea1a	1565	*/
NYX	0:85b3fd62ea1a	1566	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /!< Overflow bit for FIFO overflow counter /
NYX	0:85b3fd62ea1a	1567	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /!< Overflow bit for missed frame counter /
NYX	0:85b3fd62ea1a	1568	/**
NYX	0:85b3fd62ea1a	1569	* @}
NYX	0:85b3fd62ea1a	1570	*/
NYX	0:85b3fd62ea1a	1571
NYX	0:85b3fd62ea1a	1572	/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
NYX	0:85b3fd62ea1a	1573	* @{
NYX	0:85b3fd62ea1a	1574	*/
NYX	0:85b3fd62ea1a	1575	#define ETH_EXTI_LINE_WAKEUP 0x00080000U /!< External interrupt line 19 Connected to the ETH EXTI Line /
NYX	0:85b3fd62ea1a	1576
NYX	0:85b3fd62ea1a	1577	/**
NYX	0:85b3fd62ea1a	1578	* @}
NYX	0:85b3fd62ea1a	1579	*/
NYX	0:85b3fd62ea1a	1580
NYX	0:85b3fd62ea1a	1581	/**
NYX	0:85b3fd62ea1a	1582	* @}
NYX	0:85b3fd62ea1a	1583	*/
NYX	0:85b3fd62ea1a	1584
NYX	0:85b3fd62ea1a	1585	/* Exported macro ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1586	/** @defgroup ETH_Exported_Macros ETH Exported Macros
NYX	0:85b3fd62ea1a	1587	* @brief macros to handle interrupts and specific clock configurations
NYX	0:85b3fd62ea1a	1588	* @{
NYX	0:85b3fd62ea1a	1589	*/
NYX	0:85b3fd62ea1a	1590
NYX	0:85b3fd62ea1a	1591	/** @brief Reset ETH handle state
NYX	0:85b3fd62ea1a	1592	* @param __HANDLE__: specifies the ETH handle.
NYX	0:85b3fd62ea1a	1593	* @retval None
NYX	0:85b3fd62ea1a	1594	*/
NYX	0:85b3fd62ea1a	1595	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
NYX	0:85b3fd62ea1a	1596
NYX	0:85b3fd62ea1a	1597	/**
NYX	0:85b3fd62ea1a	1598	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
NYX	0:85b3fd62ea1a	1599	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1600	* @param __FLAG__: specifies the flag of TDES0 to check.
NYX	0:85b3fd62ea1a	1601	* @retval the ETH_DMATxDescFlag (SET or RESET).
NYX	0:85b3fd62ea1a	1602	*/
NYX	0:85b3fd62ea1a	1603	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
NYX	0:85b3fd62ea1a	1604
NYX	0:85b3fd62ea1a	1605	/**
NYX	0:85b3fd62ea1a	1606	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
NYX	0:85b3fd62ea1a	1607	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1608	* @param __FLAG__: specifies the flag of RDES0 to check.
NYX	0:85b3fd62ea1a	1609	* @retval the ETH_DMATxDescFlag (SET or RESET).
NYX	0:85b3fd62ea1a	1610	*/
NYX	0:85b3fd62ea1a	1611	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
NYX	0:85b3fd62ea1a	1612
NYX	0:85b3fd62ea1a	1613	/**
NYX	0:85b3fd62ea1a	1614	* @brief Enables the specified DMA Rx Desc receive interrupt.
NYX	0:85b3fd62ea1a	1615	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1616	* @retval None
NYX	0:85b3fd62ea1a	1617	*/
NYX	0:85b3fd62ea1a	1618	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
NYX	0:85b3fd62ea1a	1619
NYX	0:85b3fd62ea1a	1620	/**
NYX	0:85b3fd62ea1a	1621	* @brief Disables the specified DMA Rx Desc receive interrupt.
NYX	0:85b3fd62ea1a	1622	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1623	* @retval None
NYX	0:85b3fd62ea1a	1624	*/
NYX	0:85b3fd62ea1a	1625	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
NYX	0:85b3fd62ea1a	1626
NYX	0:85b3fd62ea1a	1627	/**
NYX	0:85b3fd62ea1a	1628	* @brief Set the specified DMA Rx Desc Own bit.
NYX	0:85b3fd62ea1a	1629	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1630	* @retval None
NYX	0:85b3fd62ea1a	1631	*/
NYX	0:85b3fd62ea1a	1632	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
NYX	0:85b3fd62ea1a	1633
NYX	0:85b3fd62ea1a	1634	/**
NYX	0:85b3fd62ea1a	1635	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
NYX	0:85b3fd62ea1a	1636	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1637	* @retval The Transmit descriptor collision counter value.
NYX	0:85b3fd62ea1a	1638	*/
NYX	0:85b3fd62ea1a	1639	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
NYX	0:85b3fd62ea1a	1640
NYX	0:85b3fd62ea1a	1641	/**
NYX	0:85b3fd62ea1a	1642	* @brief Set the specified DMA Tx Desc Own bit.
NYX	0:85b3fd62ea1a	1643	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1644	* @retval None
NYX	0:85b3fd62ea1a	1645	*/
NYX	0:85b3fd62ea1a	1646	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
NYX	0:85b3fd62ea1a	1647
NYX	0:85b3fd62ea1a	1648	/**
NYX	0:85b3fd62ea1a	1649	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
NYX	0:85b3fd62ea1a	1650	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1651	* @retval None
NYX	0:85b3fd62ea1a	1652	*/
NYX	0:85b3fd62ea1a	1653	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
NYX	0:85b3fd62ea1a	1654
NYX	0:85b3fd62ea1a	1655	/**
NYX	0:85b3fd62ea1a	1656	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
NYX	0:85b3fd62ea1a	1657	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1658	* @retval None
NYX	0:85b3fd62ea1a	1659	*/
NYX	0:85b3fd62ea1a	1660	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
NYX	0:85b3fd62ea1a	1661
NYX	0:85b3fd62ea1a	1662	/**
NYX	0:85b3fd62ea1a	1663	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
NYX	0:85b3fd62ea1a	1664	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1665	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
NYX	0:85b3fd62ea1a	1666	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1667	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
NYX	0:85b3fd62ea1a	1668	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
NYX	0:85b3fd62ea1a	1669	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
NYX	0:85b3fd62ea1a	1670	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
NYX	0:85b3fd62ea1a	1671	* @retval None
NYX	0:85b3fd62ea1a	1672	*/
NYX	0:85b3fd62ea1a	1673	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
NYX	0:85b3fd62ea1a	1674
NYX	0:85b3fd62ea1a	1675	/**
NYX	0:85b3fd62ea1a	1676	* @brief Enables the DMA Tx Desc CRC.
NYX	0:85b3fd62ea1a	1677	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1678	* @retval None
NYX	0:85b3fd62ea1a	1679	*/
NYX	0:85b3fd62ea1a	1680	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
NYX	0:85b3fd62ea1a	1681
NYX	0:85b3fd62ea1a	1682	/**
NYX	0:85b3fd62ea1a	1683	* @brief Disables the DMA Tx Desc CRC.
NYX	0:85b3fd62ea1a	1684	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1685	* @retval None
NYX	0:85b3fd62ea1a	1686	*/
NYX	0:85b3fd62ea1a	1687	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
NYX	0:85b3fd62ea1a	1688
NYX	0:85b3fd62ea1a	1689	/**
NYX	0:85b3fd62ea1a	1690	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
NYX	0:85b3fd62ea1a	1691	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1692	* @retval None
NYX	0:85b3fd62ea1a	1693	*/
NYX	0:85b3fd62ea1a	1694	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
NYX	0:85b3fd62ea1a	1695
NYX	0:85b3fd62ea1a	1696	/**
NYX	0:85b3fd62ea1a	1697	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
NYX	0:85b3fd62ea1a	1698	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1699	* @retval None
NYX	0:85b3fd62ea1a	1700	*/
NYX	0:85b3fd62ea1a	1701	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
NYX	0:85b3fd62ea1a	1702
NYX	0:85b3fd62ea1a	1703	/**
NYX	0:85b3fd62ea1a	1704	* @brief Enables the specified ETHERNET MAC interrupts.
NYX	0:85b3fd62ea1a	1705	* @param __HANDLE__ : ETH Handle
NYX	0:85b3fd62ea1a	1706	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
NYX	0:85b3fd62ea1a	1707	* enabled or disabled.
NYX	0:85b3fd62ea1a	1708	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1709	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
NYX	0:85b3fd62ea1a	1710	* @arg ETH_MAC_IT_PMT : PMT interrupt
NYX	0:85b3fd62ea1a	1711	* @retval None
NYX	0:85b3fd62ea1a	1712	*/
NYX	0:85b3fd62ea1a	1713	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
NYX	0:85b3fd62ea1a	1714
NYX	0:85b3fd62ea1a	1715	/**
NYX	0:85b3fd62ea1a	1716	* @brief Disables the specified ETHERNET MAC interrupts.
NYX	0:85b3fd62ea1a	1717	* @param __HANDLE__ : ETH Handle
NYX	0:85b3fd62ea1a	1718	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
NYX	0:85b3fd62ea1a	1719	* enabled or disabled.
NYX	0:85b3fd62ea1a	1720	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1721	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
NYX	0:85b3fd62ea1a	1722	* @arg ETH_MAC_IT_PMT : PMT interrupt
NYX	0:85b3fd62ea1a	1723	* @retval None
NYX	0:85b3fd62ea1a	1724	*/
NYX	0:85b3fd62ea1a	1725	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
NYX	0:85b3fd62ea1a	1726
NYX	0:85b3fd62ea1a	1727	/**
NYX	0:85b3fd62ea1a	1728	* @brief Initiate a Pause Control Frame (Full-duplex only).
NYX	0:85b3fd62ea1a	1729	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1730	* @retval None
NYX	0:85b3fd62ea1a	1731	*/
NYX	0:85b3fd62ea1a	1732	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
NYX	0:85b3fd62ea1a	1733
NYX	0:85b3fd62ea1a	1734	/**
NYX	0:85b3fd62ea1a	1735	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
NYX	0:85b3fd62ea1a	1736	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1737	* @retval The new state of flow control busy status bit (SET or RESET).
NYX	0:85b3fd62ea1a	1738	*/
NYX	0:85b3fd62ea1a	1739	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
NYX	0:85b3fd62ea1a	1740
NYX	0:85b3fd62ea1a	1741	/**
NYX	0:85b3fd62ea1a	1742	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
NYX	0:85b3fd62ea1a	1743	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1744	* @retval None
NYX	0:85b3fd62ea1a	1745	*/
NYX	0:85b3fd62ea1a	1746	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
NYX	0:85b3fd62ea1a	1747
NYX	0:85b3fd62ea1a	1748	/**
NYX	0:85b3fd62ea1a	1749	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
NYX	0:85b3fd62ea1a	1750	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1751	* @retval None
NYX	0:85b3fd62ea1a	1752	*/
NYX	0:85b3fd62ea1a	1753	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
NYX	0:85b3fd62ea1a	1754
NYX	0:85b3fd62ea1a	1755	/**
NYX	0:85b3fd62ea1a	1756	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
NYX	0:85b3fd62ea1a	1757	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1758	* @param __FLAG__: specifies the flag to check.
NYX	0:85b3fd62ea1a	1759	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1760	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
NYX	0:85b3fd62ea1a	1761	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
NYX	0:85b3fd62ea1a	1762	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
NYX	0:85b3fd62ea1a	1763	* @arg ETH_MAC_FLAG_MMC : MMC flag
NYX	0:85b3fd62ea1a	1764	* @arg ETH_MAC_FLAG_PMT : PMT flag
NYX	0:85b3fd62ea1a	1765	* @retval The state of ETHERNET MAC flag.
NYX	0:85b3fd62ea1a	1766	*/
NYX	0:85b3fd62ea1a	1767	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
NYX	0:85b3fd62ea1a	1768
NYX	0:85b3fd62ea1a	1769	/**
NYX	0:85b3fd62ea1a	1770	* @brief Enables the specified ETHERNET DMA interrupts.
NYX	0:85b3fd62ea1a	1771	* @param __HANDLE__ : ETH Handle
NYX	0:85b3fd62ea1a	1772	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
NYX	0:85b3fd62ea1a	1773	* enabled @ref ETH_DMA_Interrupts
NYX	0:85b3fd62ea1a	1774	* @retval None
NYX	0:85b3fd62ea1a	1775	*/
NYX	0:85b3fd62ea1a	1776	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
NYX	0:85b3fd62ea1a	1777
NYX	0:85b3fd62ea1a	1778	/**
NYX	0:85b3fd62ea1a	1779	* @brief Disables the specified ETHERNET DMA interrupts.
NYX	0:85b3fd62ea1a	1780	* @param __HANDLE__ : ETH Handle
NYX	0:85b3fd62ea1a	1781	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
NYX	0:85b3fd62ea1a	1782	* disabled. @ref ETH_DMA_Interrupts
NYX	0:85b3fd62ea1a	1783	* @retval None
NYX	0:85b3fd62ea1a	1784	*/
NYX	0:85b3fd62ea1a	1785	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
NYX	0:85b3fd62ea1a	1786
NYX	0:85b3fd62ea1a	1787	/**
NYX	0:85b3fd62ea1a	1788	* @brief Clears the ETHERNET DMA IT pending bit.
NYX	0:85b3fd62ea1a	1789	* @param __HANDLE__ : ETH Handle
NYX	0:85b3fd62ea1a	1790	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
NYX	0:85b3fd62ea1a	1791	* @retval None
NYX	0:85b3fd62ea1a	1792	*/
NYX	0:85b3fd62ea1a	1793	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
NYX	0:85b3fd62ea1a	1794
NYX	0:85b3fd62ea1a	1795	/**
NYX	0:85b3fd62ea1a	1796	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
NYX	0:85b3fd62ea1a	1797	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1798	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
NYX	0:85b3fd62ea1a	1799	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
NYX	0:85b3fd62ea1a	1800	*/
NYX	0:85b3fd62ea1a	1801	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
NYX	0:85b3fd62ea1a	1802
NYX	0:85b3fd62ea1a	1803	/**
NYX	0:85b3fd62ea1a	1804	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
NYX	0:85b3fd62ea1a	1805	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1806	* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
NYX	0:85b3fd62ea1a	1807	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
NYX	0:85b3fd62ea1a	1808	*/
NYX	0:85b3fd62ea1a	1809	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
NYX	0:85b3fd62ea1a	1810
NYX	0:85b3fd62ea1a	1811	/**
NYX	0:85b3fd62ea1a	1812	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
NYX	0:85b3fd62ea1a	1813	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1814	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
NYX	0:85b3fd62ea1a	1815	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1816	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
NYX	0:85b3fd62ea1a	1817	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
NYX	0:85b3fd62ea1a	1818	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
NYX	0:85b3fd62ea1a	1819	*/
NYX	0:85b3fd62ea1a	1820	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
NYX	0:85b3fd62ea1a	1821
NYX	0:85b3fd62ea1a	1822	/**
NYX	0:85b3fd62ea1a	1823	* @brief Set the DMA Receive status watchdog timer register value
NYX	0:85b3fd62ea1a	1824	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1825	* @param __VALUE__: DMA Receive status watchdog timer register value
NYX	0:85b3fd62ea1a	1826	* @retval None
NYX	0:85b3fd62ea1a	1827	*/
NYX	0:85b3fd62ea1a	1828	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
NYX	0:85b3fd62ea1a	1829
NYX	0:85b3fd62ea1a	1830	/**
NYX	0:85b3fd62ea1a	1831	* @brief Enables any unicast packet filtered by the MAC address
NYX	0:85b3fd62ea1a	1832	* recognition to be a wake-up frame.
NYX	0:85b3fd62ea1a	1833	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1834	* @retval None
NYX	0:85b3fd62ea1a	1835	*/
NYX	0:85b3fd62ea1a	1836	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
NYX	0:85b3fd62ea1a	1837
NYX	0:85b3fd62ea1a	1838	/**
NYX	0:85b3fd62ea1a	1839	* @brief Disables any unicast packet filtered by the MAC address
NYX	0:85b3fd62ea1a	1840	* recognition to be a wake-up frame.
NYX	0:85b3fd62ea1a	1841	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1842	* @retval None
NYX	0:85b3fd62ea1a	1843	*/
NYX	0:85b3fd62ea1a	1844	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
NYX	0:85b3fd62ea1a	1845
NYX	0:85b3fd62ea1a	1846	/**
NYX	0:85b3fd62ea1a	1847	* @brief Enables the MAC Wake-Up Frame Detection.
NYX	0:85b3fd62ea1a	1848	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1849	* @retval None
NYX	0:85b3fd62ea1a	1850	*/
NYX	0:85b3fd62ea1a	1851	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
NYX	0:85b3fd62ea1a	1852
NYX	0:85b3fd62ea1a	1853	/**
NYX	0:85b3fd62ea1a	1854	* @brief Disables the MAC Wake-Up Frame Detection.
NYX	0:85b3fd62ea1a	1855	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1856	* @retval None
NYX	0:85b3fd62ea1a	1857	*/
NYX	0:85b3fd62ea1a	1858	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
NYX	0:85b3fd62ea1a	1859
NYX	0:85b3fd62ea1a	1860	/**
NYX	0:85b3fd62ea1a	1861	* @brief Enables the MAC Magic Packet Detection.
NYX	0:85b3fd62ea1a	1862	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1863	* @retval None
NYX	0:85b3fd62ea1a	1864	*/
NYX	0:85b3fd62ea1a	1865	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
NYX	0:85b3fd62ea1a	1866
NYX	0:85b3fd62ea1a	1867	/**
NYX	0:85b3fd62ea1a	1868	* @brief Disables the MAC Magic Packet Detection.
NYX	0:85b3fd62ea1a	1869	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1870	* @retval None
NYX	0:85b3fd62ea1a	1871	*/
NYX	0:85b3fd62ea1a	1872	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
NYX	0:85b3fd62ea1a	1873
NYX	0:85b3fd62ea1a	1874	/**
NYX	0:85b3fd62ea1a	1875	* @brief Enables the MAC Power Down.
NYX	0:85b3fd62ea1a	1876	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1877	* @retval None
NYX	0:85b3fd62ea1a	1878	*/
NYX	0:85b3fd62ea1a	1879	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
NYX	0:85b3fd62ea1a	1880
NYX	0:85b3fd62ea1a	1881	/**
NYX	0:85b3fd62ea1a	1882	* @brief Disables the MAC Power Down.
NYX	0:85b3fd62ea1a	1883	* @param __HANDLE__: ETH Handle
NYX	0:85b3fd62ea1a	1884	* @retval None
NYX	0:85b3fd62ea1a	1885	*/
NYX	0:85b3fd62ea1a	1886	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
NYX	0:85b3fd62ea1a	1887
NYX	0:85b3fd62ea1a	1888	/**
NYX	0:85b3fd62ea1a	1889	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
NYX	0:85b3fd62ea1a	1890	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1891	* @param __FLAG__: specifies the flag to check.
NYX	0:85b3fd62ea1a	1892	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1893	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
NYX	0:85b3fd62ea1a	1894	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
NYX	0:85b3fd62ea1a	1895	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
NYX	0:85b3fd62ea1a	1896	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
NYX	0:85b3fd62ea1a	1897	*/
NYX	0:85b3fd62ea1a	1898	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
NYX	0:85b3fd62ea1a	1899
NYX	0:85b3fd62ea1a	1900	/**
NYX	0:85b3fd62ea1a	1901	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
NYX	0:85b3fd62ea1a	1902	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1903	* @retval None
NYX	0:85b3fd62ea1a	1904	*/
NYX	0:85b3fd62ea1a	1905	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
NYX	0:85b3fd62ea1a	1906
NYX	0:85b3fd62ea1a	1907	/**
NYX	0:85b3fd62ea1a	1908	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
NYX	0:85b3fd62ea1a	1909	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1910	* @retval None
NYX	0:85b3fd62ea1a	1911	*/
NYX	0:85b3fd62ea1a	1912	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
NYX	0:85b3fd62ea1a	1913	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
NYX	0:85b3fd62ea1a	1914
NYX	0:85b3fd62ea1a	1915	/**
NYX	0:85b3fd62ea1a	1916	* @brief Enables the MMC Counter Freeze.
NYX	0:85b3fd62ea1a	1917	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1918	* @retval None
NYX	0:85b3fd62ea1a	1919	*/
NYX	0:85b3fd62ea1a	1920	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
NYX	0:85b3fd62ea1a	1921
NYX	0:85b3fd62ea1a	1922	/**
NYX	0:85b3fd62ea1a	1923	* @brief Disables the MMC Counter Freeze.
NYX	0:85b3fd62ea1a	1924	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1925	* @retval None
NYX	0:85b3fd62ea1a	1926	*/
NYX	0:85b3fd62ea1a	1927	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
NYX	0:85b3fd62ea1a	1928
NYX	0:85b3fd62ea1a	1929	/**
NYX	0:85b3fd62ea1a	1930	* @brief Enables the MMC Reset On Read.
NYX	0:85b3fd62ea1a	1931	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1932	* @retval None
NYX	0:85b3fd62ea1a	1933	*/
NYX	0:85b3fd62ea1a	1934	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
NYX	0:85b3fd62ea1a	1935
NYX	0:85b3fd62ea1a	1936	/**
NYX	0:85b3fd62ea1a	1937	* @brief Disables the MMC Reset On Read.
NYX	0:85b3fd62ea1a	1938	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1939	* @retval None
NYX	0:85b3fd62ea1a	1940	*/
NYX	0:85b3fd62ea1a	1941	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
NYX	0:85b3fd62ea1a	1942
NYX	0:85b3fd62ea1a	1943	/**
NYX	0:85b3fd62ea1a	1944	* @brief Enables the MMC Counter Stop Rollover.
NYX	0:85b3fd62ea1a	1945	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1946	* @retval None
NYX	0:85b3fd62ea1a	1947	*/
NYX	0:85b3fd62ea1a	1948	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
NYX	0:85b3fd62ea1a	1949
NYX	0:85b3fd62ea1a	1950	/**
NYX	0:85b3fd62ea1a	1951	* @brief Disables the MMC Counter Stop Rollover.
NYX	0:85b3fd62ea1a	1952	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1953	* @retval None
NYX	0:85b3fd62ea1a	1954	*/
NYX	0:85b3fd62ea1a	1955	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
NYX	0:85b3fd62ea1a	1956
NYX	0:85b3fd62ea1a	1957	/**
NYX	0:85b3fd62ea1a	1958	* @brief Resets the MMC Counters.
NYX	0:85b3fd62ea1a	1959	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1960	* @retval None
NYX	0:85b3fd62ea1a	1961	*/
NYX	0:85b3fd62ea1a	1962	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
NYX	0:85b3fd62ea1a	1963
NYX	0:85b3fd62ea1a	1964	/**
NYX	0:85b3fd62ea1a	1965	* @brief Enables the specified ETHERNET MMC Rx interrupts.
NYX	0:85b3fd62ea1a	1966	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1967	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
NYX	0:85b3fd62ea1a	1968	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1969	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
NYX	0:85b3fd62ea1a	1970	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
NYX	0:85b3fd62ea1a	1971	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
NYX	0:85b3fd62ea1a	1972	* @retval None
NYX	0:85b3fd62ea1a	1973	*/
NYX	0:85b3fd62ea1a	1974	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
NYX	0:85b3fd62ea1a	1975	/**
NYX	0:85b3fd62ea1a	1976	* @brief Disables the specified ETHERNET MMC Rx interrupts.
NYX	0:85b3fd62ea1a	1977	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1978	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
NYX	0:85b3fd62ea1a	1979	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1980	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
NYX	0:85b3fd62ea1a	1981	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
NYX	0:85b3fd62ea1a	1982	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
NYX	0:85b3fd62ea1a	1983	* @retval None
NYX	0:85b3fd62ea1a	1984	*/
NYX	0:85b3fd62ea1a	1985	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFFU)
NYX	0:85b3fd62ea1a	1986	/**
NYX	0:85b3fd62ea1a	1987	* @brief Enables the specified ETHERNET MMC Tx interrupts.
NYX	0:85b3fd62ea1a	1988	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	1989	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
NYX	0:85b3fd62ea1a	1990	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1991	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
NYX	0:85b3fd62ea1a	1992	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
NYX	0:85b3fd62ea1a	1993	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
NYX	0:85b3fd62ea1a	1994	* @retval None
NYX	0:85b3fd62ea1a	1995	*/
NYX	0:85b3fd62ea1a	1996	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
NYX	0:85b3fd62ea1a	1997
NYX	0:85b3fd62ea1a	1998	/**
NYX	0:85b3fd62ea1a	1999	* @brief Disables the specified ETHERNET MMC Tx interrupts.
NYX	0:85b3fd62ea1a	2000	* @param __HANDLE__: ETH Handle.
NYX	0:85b3fd62ea1a	2001	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
NYX	0:85b3fd62ea1a	2002	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2003	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
NYX	0:85b3fd62ea1a	2004	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
NYX	0:85b3fd62ea1a	2005	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
NYX	0:85b3fd62ea1a	2006	* @retval None
NYX	0:85b3fd62ea1a	2007	*/
NYX	0:85b3fd62ea1a	2008	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
NYX	0:85b3fd62ea1a	2009
NYX	0:85b3fd62ea1a	2010	/**
NYX	0:85b3fd62ea1a	2011	* @brief Enables the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2012	* @retval None
NYX	0:85b3fd62ea1a	2013	*/
NYX	0:85b3fd62ea1a	2014	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
NYX	0:85b3fd62ea1a	2015
NYX	0:85b3fd62ea1a	2016	/**
NYX	0:85b3fd62ea1a	2017	* @brief Disables the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2018	* @retval None
NYX	0:85b3fd62ea1a	2019	*/
NYX	0:85b3fd62ea1a	2020	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
NYX	0:85b3fd62ea1a	2021
NYX	0:85b3fd62ea1a	2022	/**
NYX	0:85b3fd62ea1a	2023	* @brief Enable event on ETH External event line.
NYX	0:85b3fd62ea1a	2024	* @retval None.
NYX	0:85b3fd62ea1a	2025	*/
NYX	0:85b3fd62ea1a	2026	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
NYX	0:85b3fd62ea1a	2027
NYX	0:85b3fd62ea1a	2028	/**
NYX	0:85b3fd62ea1a	2029	* @brief Disable event on ETH External event line
NYX	0:85b3fd62ea1a	2030	* @retval None.
NYX	0:85b3fd62ea1a	2031	*/
NYX	0:85b3fd62ea1a	2032	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
NYX	0:85b3fd62ea1a	2033
NYX	0:85b3fd62ea1a	2034	/**
NYX	0:85b3fd62ea1a	2035	* @brief Get flag of the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2036	* @retval None
NYX	0:85b3fd62ea1a	2037	*/
NYX	0:85b3fd62ea1a	2038	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
NYX	0:85b3fd62ea1a	2039
NYX	0:85b3fd62ea1a	2040	/**
NYX	0:85b3fd62ea1a	2041	* @brief Clear flag of the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2042	* @retval None
NYX	0:85b3fd62ea1a	2043	*/
NYX	0:85b3fd62ea1a	2044	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
NYX	0:85b3fd62ea1a	2045
NYX	0:85b3fd62ea1a	2046	/**
NYX	0:85b3fd62ea1a	2047	* @brief Enables rising edge trigger to the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2048	* @retval None
NYX	0:85b3fd62ea1a	2049	*/
NYX	0:85b3fd62ea1a	2050	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
NYX	0:85b3fd62ea1a	2051
NYX	0:85b3fd62ea1a	2052	/**
NYX	0:85b3fd62ea1a	2053	* @brief Disables the rising edge trigger to the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2054	* @retval None
NYX	0:85b3fd62ea1a	2055	*/
NYX	0:85b3fd62ea1a	2056	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
NYX	0:85b3fd62ea1a	2057
NYX	0:85b3fd62ea1a	2058	/**
NYX	0:85b3fd62ea1a	2059	* @brief Enables falling edge trigger to the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2060	* @retval None
NYX	0:85b3fd62ea1a	2061	*/
NYX	0:85b3fd62ea1a	2062	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
NYX	0:85b3fd62ea1a	2063
NYX	0:85b3fd62ea1a	2064	/**
NYX	0:85b3fd62ea1a	2065	* @brief Disables falling edge trigger to the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2066	* @retval None
NYX	0:85b3fd62ea1a	2067	*/
NYX	0:85b3fd62ea1a	2068	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
NYX	0:85b3fd62ea1a	2069
NYX	0:85b3fd62ea1a	2070	/**
NYX	0:85b3fd62ea1a	2071	* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2072	* @retval None
NYX	0:85b3fd62ea1a	2073	*/
NYX	0:85b3fd62ea1a	2074	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
NYX	0:85b3fd62ea1a	2075	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP;\
NYX	0:85b3fd62ea1a	2076	}while(0U)
NYX	0:85b3fd62ea1a	2077
NYX	0:85b3fd62ea1a	2078	/**
NYX	0:85b3fd62ea1a	2079	* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
NYX	0:85b3fd62ea1a	2080	* @retval None
NYX	0:85b3fd62ea1a	2081	*/
NYX	0:85b3fd62ea1a	2082	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
NYX	0:85b3fd62ea1a	2083	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
NYX	0:85b3fd62ea1a	2084	}while(0U)
NYX	0:85b3fd62ea1a	2085
NYX	0:85b3fd62ea1a	2086	/**
NYX	0:85b3fd62ea1a	2087	* @brief Generate a Software interrupt on selected EXTI line.
NYX	0:85b3fd62ea1a	2088	* @retval None.
NYX	0:85b3fd62ea1a	2089	*/
NYX	0:85b3fd62ea1a	2090	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
NYX	0:85b3fd62ea1a	2091
NYX	0:85b3fd62ea1a	2092	/**
NYX	0:85b3fd62ea1a	2093	* @}
NYX	0:85b3fd62ea1a	2094	*/
NYX	0:85b3fd62ea1a	2095	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	2096
NYX	0:85b3fd62ea1a	2097	/** @addtogroup ETH_Exported_Functions
NYX	0:85b3fd62ea1a	2098	* @{
NYX	0:85b3fd62ea1a	2099	*/
NYX	0:85b3fd62ea1a	2100
NYX	0:85b3fd62ea1a	2101	/* Initialization and de-initialization functions ****************************/
NYX	0:85b3fd62ea1a	2102
NYX	0:85b3fd62ea1a	2103	/** @addtogroup ETH_Exported_Functions_Group1
NYX	0:85b3fd62ea1a	2104	* @{
NYX	0:85b3fd62ea1a	2105	*/
NYX	0:85b3fd62ea1a	2106	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2107	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2108	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2109	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2110	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
NYX	0:85b3fd62ea1a	2111	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
NYX	0:85b3fd62ea1a	2112
NYX	0:85b3fd62ea1a	2113	/**
NYX	0:85b3fd62ea1a	2114	* @}
NYX	0:85b3fd62ea1a	2115	*/
NYX	0:85b3fd62ea1a	2116	/* IO operation functions ****************************************************/
NYX	0:85b3fd62ea1a	2117
NYX	0:85b3fd62ea1a	2118	/** @addtogroup ETH_Exported_Functions_Group2
NYX	0:85b3fd62ea1a	2119	* @{
NYX	0:85b3fd62ea1a	2120	*/
NYX	0:85b3fd62ea1a	2121	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
NYX	0:85b3fd62ea1a	2122	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2123	/* Communication with PHY functions*/
NYX	0:85b3fd62ea1a	2124	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
NYX	0:85b3fd62ea1a	2125	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
NYX	0:85b3fd62ea1a	2126	/* Non-Blocking mode: Interrupt */
NYX	0:85b3fd62ea1a	2127	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2128	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2129	/* Callback in non blocking modes (Interrupt) */
NYX	0:85b3fd62ea1a	2130	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2131	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2132	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2133	/**
NYX	0:85b3fd62ea1a	2134	* @}
NYX	0:85b3fd62ea1a	2135	*/
NYX	0:85b3fd62ea1a	2136
NYX	0:85b3fd62ea1a	2137	/* Peripheral Control functions **********************************************/
NYX	0:85b3fd62ea1a	2138
NYX	0:85b3fd62ea1a	2139	/** @addtogroup ETH_Exported_Functions_Group3
NYX	0:85b3fd62ea1a	2140	* @{
NYX	0:85b3fd62ea1a	2141	*/
NYX	0:85b3fd62ea1a	2142
NYX	0:85b3fd62ea1a	2143	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2144	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2145	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
NYX	0:85b3fd62ea1a	2146	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
NYX	0:85b3fd62ea1a	2147	/**
NYX	0:85b3fd62ea1a	2148	* @}
NYX	0:85b3fd62ea1a	2149	*/
NYX	0:85b3fd62ea1a	2150
NYX	0:85b3fd62ea1a	2151	/* Peripheral State functions ************************************************/
NYX	0:85b3fd62ea1a	2152
NYX	0:85b3fd62ea1a	2153	/** @addtogroup ETH_Exported_Functions_Group4
NYX	0:85b3fd62ea1a	2154	* @{
NYX	0:85b3fd62ea1a	2155	*/
NYX	0:85b3fd62ea1a	2156	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
NYX	0:85b3fd62ea1a	2157	/**
NYX	0:85b3fd62ea1a	2158	* @}
NYX	0:85b3fd62ea1a	2159	*/
NYX	0:85b3fd62ea1a	2160
NYX	0:85b3fd62ea1a	2161	/**
NYX	0:85b3fd62ea1a	2162	* @}
NYX	0:85b3fd62ea1a	2163	*/
NYX	0:85b3fd62ea1a	2164
NYX	0:85b3fd62ea1a	2165	/**
NYX	0:85b3fd62ea1a	2166	* @}
NYX	0:85b3fd62ea1a	2167	*/
NYX	0:85b3fd62ea1a	2168
NYX	0:85b3fd62ea1a	2169	/**
NYX	0:85b3fd62ea1a	2170	* @}
NYX	0:85b3fd62ea1a	2171	*/
NYX	0:85b3fd62ea1a	2172
NYX	0:85b3fd62ea1a	2173	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\|\
NYX	0:85b3fd62ea1a	2174	STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	2175
NYX	0:85b3fd62ea1a	2176	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	2177	}
NYX	0:85b3fd62ea1a	2178	#endif
NYX	0:85b3fd62ea1a	2179
NYX	0:85b3fd62ea1a	2180	#endif /* __STM32F4xx_HAL_ETH_H */
NYX	0:85b3fd62ea1a	2181
NYX	0:85b3fd62ea1a	2182
NYX	0:85b3fd62ea1a	2183	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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