Takaaki Numai / mbed-dev

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Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_eth.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief ETH HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 9 * functionalities of the Ethernet (ETH) peripheral:
NYX 0:85b3fd62ea1a 10 * + Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 11 * + IO operation functions
NYX 0:85b3fd62ea1a 12 * + Peripheral Control functions
NYX 0:85b3fd62ea1a 13 * + Peripheral State and Errors functions
NYX 0:85b3fd62ea1a 14 *
NYX 0:85b3fd62ea1a 15 @verbatim
NYX 0:85b3fd62ea1a 16 ==============================================================================
NYX 0:85b3fd62ea1a 17 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 18 ==============================================================================
NYX 0:85b3fd62ea1a 19 [..]
NYX 0:85b3fd62ea1a 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
NYX 0:85b3fd62ea1a 21 ETH_HandleTypeDef heth;
NYX 0:85b3fd62ea1a 22
NYX 0:85b3fd62ea1a 23 (#)Fill parameters of Init structure in heth handle
NYX 0:85b3fd62ea1a 24
NYX 0:85b3fd62ea1a 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
NYX 0:85b3fd62ea1a 26
NYX 0:85b3fd62ea1a 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
NYX 0:85b3fd62ea1a 28 (##) Enable the Ethernet interface clock using
NYX 0:85b3fd62ea1a 29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
NYX 0:85b3fd62ea1a 30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
NYX 0:85b3fd62ea1a 31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
NYX 0:85b3fd62ea1a 32
NYX 0:85b3fd62ea1a 33 (##) Initialize the related GPIO clocks
NYX 0:85b3fd62ea1a 34 (##) Configure Ethernet pin-out
NYX 0:85b3fd62ea1a 35 (##) Configure Ethernet NVIC interrupt (IT mode)
NYX 0:85b3fd62ea1a 36
NYX 0:85b3fd62ea1a 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
NYX 0:85b3fd62ea1a 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
NYX 0:85b3fd62ea1a 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
NYX 0:85b3fd62ea1a 40
NYX 0:85b3fd62ea1a 41 (#)Enable MAC and DMA transmission and reception:
NYX 0:85b3fd62ea1a 42 (##) HAL_ETH_Start();
NYX 0:85b3fd62ea1a 43
NYX 0:85b3fd62ea1a 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
NYX 0:85b3fd62ea1a 45 the frame to MAC TX FIFO:
NYX 0:85b3fd62ea1a 46 (##) HAL_ETH_TransmitFrame();
NYX 0:85b3fd62ea1a 47
NYX 0:85b3fd62ea1a 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
NYX 0:85b3fd62ea1a 49 frame parameters
NYX 0:85b3fd62ea1a 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
NYX 0:85b3fd62ea1a 51
NYX 0:85b3fd62ea1a 52 (#) Get a received frame when an ETH RX interrupt occurs:
NYX 0:85b3fd62ea1a 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 (#) Communicate with external PHY device:
NYX 0:85b3fd62ea1a 56 (##) Read a specific register from the PHY
NYX 0:85b3fd62ea1a 57 HAL_ETH_ReadPHYRegister();
NYX 0:85b3fd62ea1a 58 (##) Write data to a specific RHY register:
NYX 0:85b3fd62ea1a 59 HAL_ETH_WritePHYRegister();
NYX 0:85b3fd62ea1a 60
NYX 0:85b3fd62ea1a 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
NYX 0:85b3fd62ea1a 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
NYX 0:85b3fd62ea1a 63
NYX 0:85b3fd62ea1a 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
NYX 0:85b3fd62ea1a 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
NYX 0:85b3fd62ea1a 66
NYX 0:85b3fd62ea1a 67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
NYX 0:85b3fd62ea1a 68 in this driver
NYX 0:85b3fd62ea1a 69
NYX 0:85b3fd62ea1a 70 @endverbatim
NYX 0:85b3fd62ea1a 71 ******************************************************************************
NYX 0:85b3fd62ea1a 72 * @attention
NYX 0:85b3fd62ea1a 73 *
NYX 0:85b3fd62ea1a 74 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 75 *
NYX 0:85b3fd62ea1a 76 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 77 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 78 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 79 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 81 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 82 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 84 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 85 * without specific prior written permission.
NYX 0:85b3fd62ea1a 86 *
NYX 0:85b3fd62ea1a 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 97 *
NYX 0:85b3fd62ea1a 98 ******************************************************************************
NYX 0:85b3fd62ea1a 99 */
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 102 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 103
NYX 0:85b3fd62ea1a 104 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 105 * @{
NYX 0:85b3fd62ea1a 106 */
NYX 0:85b3fd62ea1a 107
NYX 0:85b3fd62ea1a 108 /** @defgroup ETH ETH
NYX 0:85b3fd62ea1a 109 * @brief ETH HAL module driver
NYX 0:85b3fd62ea1a 110 * @{
NYX 0:85b3fd62ea1a 111 */
NYX 0:85b3fd62ea1a 112
NYX 0:85b3fd62ea1a 113 #ifdef HAL_ETH_MODULE_ENABLED
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
NYX 0:85b3fd62ea1a 116 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 119 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 120 /** @defgroup ETH_Private_Constants ETH Private Constants
NYX 0:85b3fd62ea1a 121 * @{
NYX 0:85b3fd62ea1a 122 */
NYX 0:85b3fd62ea1a 123 #define ETH_TIMEOUT_SWRESET 500U
NYX 0:85b3fd62ea1a 124 #define ETH_TIMEOUT_LINKED_STATE 5000U
NYX 0:85b3fd62ea1a 125 #define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 /**
NYX 0:85b3fd62ea1a 128 * @}
NYX 0:85b3fd62ea1a 129 */
NYX 0:85b3fd62ea1a 130 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 131 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 132 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 133 /** @defgroup ETH_Private_Functions ETH Private Functions
NYX 0:85b3fd62ea1a 134 * @{
NYX 0:85b3fd62ea1a 135 */
NYX 0:85b3fd62ea1a 136 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
NYX 0:85b3fd62ea1a 137 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
NYX 0:85b3fd62ea1a 138 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
NYX 0:85b3fd62ea1a 139 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
NYX 0:85b3fd62ea1a 140 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
NYX 0:85b3fd62ea1a 141 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
NYX 0:85b3fd62ea1a 142 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
NYX 0:85b3fd62ea1a 143 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
NYX 0:85b3fd62ea1a 144 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
NYX 0:85b3fd62ea1a 145 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
NYX 0:85b3fd62ea1a 146 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
NYX 0:85b3fd62ea1a 147 static void ETH_Delay(uint32_t mdelay);
NYX 0:85b3fd62ea1a 148
NYX 0:85b3fd62ea1a 149 /**
NYX 0:85b3fd62ea1a 150 * @}
NYX 0:85b3fd62ea1a 151 */
NYX 0:85b3fd62ea1a 152 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 153
NYX 0:85b3fd62ea1a 154 /** @defgroup ETH_Exported_Functions ETH Exported Functions
NYX 0:85b3fd62ea1a 155 * @{
NYX 0:85b3fd62ea1a 156 */
NYX 0:85b3fd62ea1a 157
NYX 0:85b3fd62ea1a 158 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 159 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 160 *
NYX 0:85b3fd62ea1a 161 @verbatim
NYX 0:85b3fd62ea1a 162 ===============================================================================
NYX 0:85b3fd62ea1a 163 ##### Initialization and de-initialization functions #####
NYX 0:85b3fd62ea1a 164 ===============================================================================
NYX 0:85b3fd62ea1a 165 [..] This section provides functions allowing to:
NYX 0:85b3fd62ea1a 166 (+) Initialize and configure the Ethernet peripheral
NYX 0:85b3fd62ea1a 167 (+) De-initialize the Ethernet peripheral
NYX 0:85b3fd62ea1a 168
NYX 0:85b3fd62ea1a 169 @endverbatim
NYX 0:85b3fd62ea1a 170 * @{
NYX 0:85b3fd62ea1a 171 */
NYX 0:85b3fd62ea1a 172
NYX 0:85b3fd62ea1a 173 /**
NYX 0:85b3fd62ea1a 174 * @brief Initializes the Ethernet MAC and DMA according to default
NYX 0:85b3fd62ea1a 175 * parameters.
NYX 0:85b3fd62ea1a 176 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 177 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 178 * @retval HAL status
NYX 0:85b3fd62ea1a 179 */
NYX 0:85b3fd62ea1a 180 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 181 {
NYX 0:85b3fd62ea1a 182 uint32_t tmpreg1 = 0U, phyreg = 0U;
NYX 0:85b3fd62ea1a 183 uint32_t hclk = 60000000U;
NYX 0:85b3fd62ea1a 184 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 185 uint32_t err = ETH_SUCCESS;
NYX 0:85b3fd62ea1a 186
NYX 0:85b3fd62ea1a 187 /* Check the ETH peripheral state */
NYX 0:85b3fd62ea1a 188 if(heth == NULL)
NYX 0:85b3fd62ea1a 189 {
NYX 0:85b3fd62ea1a 190 return HAL_ERROR;
NYX 0:85b3fd62ea1a 191 }
NYX 0:85b3fd62ea1a 192
NYX 0:85b3fd62ea1a 193 /* Check parameters */
NYX 0:85b3fd62ea1a 194 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
NYX 0:85b3fd62ea1a 195 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
NYX 0:85b3fd62ea1a 196 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
NYX 0:85b3fd62ea1a 197 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
NYX 0:85b3fd62ea1a 198
NYX 0:85b3fd62ea1a 199 if(heth->State == HAL_ETH_STATE_RESET)
NYX 0:85b3fd62ea1a 200 {
NYX 0:85b3fd62ea1a 201 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 202 heth->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 203 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
NYX 0:85b3fd62ea1a 204 HAL_ETH_MspInit(heth);
NYX 0:85b3fd62ea1a 205 }
NYX 0:85b3fd62ea1a 206
NYX 0:85b3fd62ea1a 207 /* Enable SYSCFG Clock */
NYX 0:85b3fd62ea1a 208 __HAL_RCC_SYSCFG_CLK_ENABLE();
NYX 0:85b3fd62ea1a 209
NYX 0:85b3fd62ea1a 210 /* Select MII or RMII Mode*/
NYX 0:85b3fd62ea1a 211 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
NYX 0:85b3fd62ea1a 212 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
NYX 0:85b3fd62ea1a 213
NYX 0:85b3fd62ea1a 214 /* Ethernet Software reset */
NYX 0:85b3fd62ea1a 215 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
NYX 0:85b3fd62ea1a 216 /* After reset all the registers holds their respective reset values */
NYX 0:85b3fd62ea1a 217 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
NYX 0:85b3fd62ea1a 218
NYX 0:85b3fd62ea1a 219 /* Get tick */
NYX 0:85b3fd62ea1a 220 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 221
NYX 0:85b3fd62ea1a 222 /* Wait for software reset */
NYX 0:85b3fd62ea1a 223 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
NYX 0:85b3fd62ea1a 224 {
NYX 0:85b3fd62ea1a 225 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 226 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
NYX 0:85b3fd62ea1a 227 {
NYX 0:85b3fd62ea1a 228 heth->State= HAL_ETH_STATE_TIMEOUT;
NYX 0:85b3fd62ea1a 229
NYX 0:85b3fd62ea1a 230 /* Process Unlocked */
NYX 0:85b3fd62ea1a 231 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 232
NYX 0:85b3fd62ea1a 233 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
NYX 0:85b3fd62ea1a 234 not available, please check your external PHY or the IO configuration */
NYX 0:85b3fd62ea1a 235 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 236 }
NYX 0:85b3fd62ea1a 237 }
NYX 0:85b3fd62ea1a 238
NYX 0:85b3fd62ea1a 239 /*-------------------------------- MAC Initialization ----------------------*/
NYX 0:85b3fd62ea1a 240 /* Get the ETHERNET MACMIIAR value */
NYX 0:85b3fd62ea1a 241 tmpreg1 = (heth->Instance)->MACMIIAR;
NYX 0:85b3fd62ea1a 242 /* Clear CSR Clock Range CR[2:0] bits */
NYX 0:85b3fd62ea1a 243 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
NYX 0:85b3fd62ea1a 244
NYX 0:85b3fd62ea1a 245 /* Get hclk frequency value */
NYX 0:85b3fd62ea1a 246 hclk = HAL_RCC_GetHCLKFreq();
NYX 0:85b3fd62ea1a 247
NYX 0:85b3fd62ea1a 248 /* Set CR bits depending on hclk value */
NYX 0:85b3fd62ea1a 249 if((hclk >= 20000000U)&&(hclk < 35000000U))
NYX 0:85b3fd62ea1a 250 {
NYX 0:85b3fd62ea1a 251 /* CSR Clock Range between 20-35 MHz */
NYX 0:85b3fd62ea1a 252 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
NYX 0:85b3fd62ea1a 253 }
NYX 0:85b3fd62ea1a 254 else if((hclk >= 35000000U)&&(hclk < 60000000U))
NYX 0:85b3fd62ea1a 255 {
NYX 0:85b3fd62ea1a 256 /* CSR Clock Range between 35-60 MHz */
NYX 0:85b3fd62ea1a 257 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
NYX 0:85b3fd62ea1a 258 }
NYX 0:85b3fd62ea1a 259 else if((hclk >= 60000000U)&&(hclk < 100000000U))
NYX 0:85b3fd62ea1a 260 {
NYX 0:85b3fd62ea1a 261 /* CSR Clock Range between 60-100 MHz */
NYX 0:85b3fd62ea1a 262 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
NYX 0:85b3fd62ea1a 263 }
NYX 0:85b3fd62ea1a 264 else if((hclk >= 100000000U)&&(hclk < 150000000U))
NYX 0:85b3fd62ea1a 265 {
NYX 0:85b3fd62ea1a 266 /* CSR Clock Range between 100-150 MHz */
NYX 0:85b3fd62ea1a 267 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
NYX 0:85b3fd62ea1a 268 }
NYX 0:85b3fd62ea1a 269 else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */
NYX 0:85b3fd62ea1a 270 {
NYX 0:85b3fd62ea1a 271 /* CSR Clock Range between 150-183 MHz */
NYX 0:85b3fd62ea1a 272 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
NYX 0:85b3fd62ea1a 273 }
NYX 0:85b3fd62ea1a 274
NYX 0:85b3fd62ea1a 275 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
NYX 0:85b3fd62ea1a 276 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
NYX 0:85b3fd62ea1a 277
NYX 0:85b3fd62ea1a 278 /*-------------------- PHY initialization and configuration ----------------*/
NYX 0:85b3fd62ea1a 279 /* Put the PHY in reset mode */
NYX 0:85b3fd62ea1a 280 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
NYX 0:85b3fd62ea1a 281 {
NYX 0:85b3fd62ea1a 282 /* In case of write timeout */
NYX 0:85b3fd62ea1a 283 err = ETH_ERROR;
NYX 0:85b3fd62ea1a 284
NYX 0:85b3fd62ea1a 285 /* Config MAC and DMA */
NYX 0:85b3fd62ea1a 286 ETH_MACDMAConfig(heth, err);
NYX 0:85b3fd62ea1a 287
NYX 0:85b3fd62ea1a 288 /* Set the ETH peripheral state to READY */
NYX 0:85b3fd62ea1a 289 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 290
NYX 0:85b3fd62ea1a 291 /* Return HAL_ERROR */
NYX 0:85b3fd62ea1a 292 return HAL_ERROR;
NYX 0:85b3fd62ea1a 293 }
NYX 0:85b3fd62ea1a 294
NYX 0:85b3fd62ea1a 295 /* Delay to assure PHY reset */
NYX 0:85b3fd62ea1a 296 HAL_Delay(PHY_RESET_DELAY);
NYX 0:85b3fd62ea1a 297
NYX 0:85b3fd62ea1a 298 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
NYX 0:85b3fd62ea1a 299 {
NYX 0:85b3fd62ea1a 300 /* Get tick */
NYX 0:85b3fd62ea1a 301 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 302
NYX 0:85b3fd62ea1a 303 /* We wait for linked status */
NYX 0:85b3fd62ea1a 304 do
NYX 0:85b3fd62ea1a 305 {
NYX 0:85b3fd62ea1a 306 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
NYX 0:85b3fd62ea1a 307
NYX 0:85b3fd62ea1a 308 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 309 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
NYX 0:85b3fd62ea1a 310 {
NYX 0:85b3fd62ea1a 311 /* In case of write timeout */
NYX 0:85b3fd62ea1a 312 err = ETH_ERROR;
NYX 0:85b3fd62ea1a 313
NYX 0:85b3fd62ea1a 314 /* Config MAC and DMA */
NYX 0:85b3fd62ea1a 315 ETH_MACDMAConfig(heth, err);
NYX 0:85b3fd62ea1a 316
NYX 0:85b3fd62ea1a 317 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 318
NYX 0:85b3fd62ea1a 319 /* Process Unlocked */
NYX 0:85b3fd62ea1a 320 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 321
NYX 0:85b3fd62ea1a 322 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 323 }
NYX 0:85b3fd62ea1a 324 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
NYX 0:85b3fd62ea1a 325
NYX 0:85b3fd62ea1a 326
NYX 0:85b3fd62ea1a 327 /* Enable Auto-Negotiation */
NYX 0:85b3fd62ea1a 328 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
NYX 0:85b3fd62ea1a 329 {
NYX 0:85b3fd62ea1a 330 /* In case of write timeout */
NYX 0:85b3fd62ea1a 331 err = ETH_ERROR;
NYX 0:85b3fd62ea1a 332
NYX 0:85b3fd62ea1a 333 /* Config MAC and DMA */
NYX 0:85b3fd62ea1a 334 ETH_MACDMAConfig(heth, err);
NYX 0:85b3fd62ea1a 335
NYX 0:85b3fd62ea1a 336 /* Set the ETH peripheral state to READY */
NYX 0:85b3fd62ea1a 337 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 338
NYX 0:85b3fd62ea1a 339 /* Return HAL_ERROR */
NYX 0:85b3fd62ea1a 340 return HAL_ERROR;
NYX 0:85b3fd62ea1a 341 }
NYX 0:85b3fd62ea1a 342
NYX 0:85b3fd62ea1a 343 /* Get tick */
NYX 0:85b3fd62ea1a 344 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 345
NYX 0:85b3fd62ea1a 346 /* Wait until the auto-negotiation will be completed */
NYX 0:85b3fd62ea1a 347 do
NYX 0:85b3fd62ea1a 348 {
NYX 0:85b3fd62ea1a 349 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
NYX 0:85b3fd62ea1a 350
NYX 0:85b3fd62ea1a 351 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 352 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
NYX 0:85b3fd62ea1a 353 {
NYX 0:85b3fd62ea1a 354 /* In case of write timeout */
NYX 0:85b3fd62ea1a 355 err = ETH_ERROR;
NYX 0:85b3fd62ea1a 356
NYX 0:85b3fd62ea1a 357 /* Config MAC and DMA */
NYX 0:85b3fd62ea1a 358 ETH_MACDMAConfig(heth, err);
NYX 0:85b3fd62ea1a 359
NYX 0:85b3fd62ea1a 360 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 361
NYX 0:85b3fd62ea1a 362 /* Process Unlocked */
NYX 0:85b3fd62ea1a 363 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 364
NYX 0:85b3fd62ea1a 365 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 366 }
NYX 0:85b3fd62ea1a 367
NYX 0:85b3fd62ea1a 368 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
NYX 0:85b3fd62ea1a 369
NYX 0:85b3fd62ea1a 370 /* Read the result of the auto-negotiation */
NYX 0:85b3fd62ea1a 371 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
NYX 0:85b3fd62ea1a 372 {
NYX 0:85b3fd62ea1a 373 /* In case of write timeout */
NYX 0:85b3fd62ea1a 374 err = ETH_ERROR;
NYX 0:85b3fd62ea1a 375
NYX 0:85b3fd62ea1a 376 /* Config MAC and DMA */
NYX 0:85b3fd62ea1a 377 ETH_MACDMAConfig(heth, err);
NYX 0:85b3fd62ea1a 378
NYX 0:85b3fd62ea1a 379 /* Set the ETH peripheral state to READY */
NYX 0:85b3fd62ea1a 380 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 381
NYX 0:85b3fd62ea1a 382 /* Return HAL_ERROR */
NYX 0:85b3fd62ea1a 383 return HAL_ERROR;
NYX 0:85b3fd62ea1a 384 }
NYX 0:85b3fd62ea1a 385
NYX 0:85b3fd62ea1a 386 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
NYX 0:85b3fd62ea1a 387 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
NYX 0:85b3fd62ea1a 388 {
NYX 0:85b3fd62ea1a 389 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
NYX 0:85b3fd62ea1a 390 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
NYX 0:85b3fd62ea1a 391 }
NYX 0:85b3fd62ea1a 392 else
NYX 0:85b3fd62ea1a 393 {
NYX 0:85b3fd62ea1a 394 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
NYX 0:85b3fd62ea1a 395 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
NYX 0:85b3fd62ea1a 396 }
NYX 0:85b3fd62ea1a 397 /* Configure the MAC with the speed fixed by the auto-negotiation process */
NYX 0:85b3fd62ea1a 398 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
NYX 0:85b3fd62ea1a 399 {
NYX 0:85b3fd62ea1a 400 /* Set Ethernet speed to 10M following the auto-negotiation */
NYX 0:85b3fd62ea1a 401 (heth->Init).Speed = ETH_SPEED_10M;
NYX 0:85b3fd62ea1a 402 }
NYX 0:85b3fd62ea1a 403 else
NYX 0:85b3fd62ea1a 404 {
NYX 0:85b3fd62ea1a 405 /* Set Ethernet speed to 100M following the auto-negotiation */
NYX 0:85b3fd62ea1a 406 (heth->Init).Speed = ETH_SPEED_100M;
NYX 0:85b3fd62ea1a 407 }
NYX 0:85b3fd62ea1a 408 }
NYX 0:85b3fd62ea1a 409 else /* AutoNegotiation Disable */
NYX 0:85b3fd62ea1a 410 {
NYX 0:85b3fd62ea1a 411 /* Check parameters */
NYX 0:85b3fd62ea1a 412 assert_param(IS_ETH_SPEED(heth->Init.Speed));
NYX 0:85b3fd62ea1a 413 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
NYX 0:85b3fd62ea1a 414
NYX 0:85b3fd62ea1a 415 /* Set MAC Speed and Duplex Mode */
NYX 0:85b3fd62ea1a 416 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
NYX 0:85b3fd62ea1a 417 (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
NYX 0:85b3fd62ea1a 418 {
NYX 0:85b3fd62ea1a 419 /* In case of write timeout */
NYX 0:85b3fd62ea1a 420 err = ETH_ERROR;
NYX 0:85b3fd62ea1a 421
NYX 0:85b3fd62ea1a 422 /* Config MAC and DMA */
NYX 0:85b3fd62ea1a 423 ETH_MACDMAConfig(heth, err);
NYX 0:85b3fd62ea1a 424
NYX 0:85b3fd62ea1a 425 /* Set the ETH peripheral state to READY */
NYX 0:85b3fd62ea1a 426 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428 /* Return HAL_ERROR */
NYX 0:85b3fd62ea1a 429 return HAL_ERROR;
NYX 0:85b3fd62ea1a 430 }
NYX 0:85b3fd62ea1a 431
NYX 0:85b3fd62ea1a 432 /* Delay to assure PHY configuration */
NYX 0:85b3fd62ea1a 433 HAL_Delay(PHY_CONFIG_DELAY);
NYX 0:85b3fd62ea1a 434 }
NYX 0:85b3fd62ea1a 435
NYX 0:85b3fd62ea1a 436 /* Config MAC and DMA */
NYX 0:85b3fd62ea1a 437 ETH_MACDMAConfig(heth, err);
NYX 0:85b3fd62ea1a 438
NYX 0:85b3fd62ea1a 439 /* Set ETH HAL State to Ready */
NYX 0:85b3fd62ea1a 440 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 441
NYX 0:85b3fd62ea1a 442 /* Return function status */
NYX 0:85b3fd62ea1a 443 return HAL_OK;
NYX 0:85b3fd62ea1a 444 }
NYX 0:85b3fd62ea1a 445
NYX 0:85b3fd62ea1a 446 /**
NYX 0:85b3fd62ea1a 447 * @brief De-Initializes the ETH peripheral.
NYX 0:85b3fd62ea1a 448 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 449 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 450 * @retval HAL status
NYX 0:85b3fd62ea1a 451 */
NYX 0:85b3fd62ea1a 452 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 453 {
NYX 0:85b3fd62ea1a 454 /* Set the ETH peripheral state to BUSY */
NYX 0:85b3fd62ea1a 455 heth->State = HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 456
NYX 0:85b3fd62ea1a 457 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
NYX 0:85b3fd62ea1a 458 HAL_ETH_MspDeInit(heth);
NYX 0:85b3fd62ea1a 459
NYX 0:85b3fd62ea1a 460 /* Set ETH HAL state to Disabled */
NYX 0:85b3fd62ea1a 461 heth->State= HAL_ETH_STATE_RESET;
NYX 0:85b3fd62ea1a 462
NYX 0:85b3fd62ea1a 463 /* Release Lock */
NYX 0:85b3fd62ea1a 464 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 465
NYX 0:85b3fd62ea1a 466 /* Return function status */
NYX 0:85b3fd62ea1a 467 return HAL_OK;
NYX 0:85b3fd62ea1a 468 }
NYX 0:85b3fd62ea1a 469
NYX 0:85b3fd62ea1a 470 /**
NYX 0:85b3fd62ea1a 471 * @brief Initializes the DMA Tx descriptors in chain mode.
NYX 0:85b3fd62ea1a 472 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 473 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 474 * @param DMATxDescTab: Pointer to the first Tx desc list
NYX 0:85b3fd62ea1a 475 * @param TxBuff: Pointer to the first TxBuffer list
NYX 0:85b3fd62ea1a 476 * @param TxBuffCount: Number of the used Tx desc in the list
NYX 0:85b3fd62ea1a 477 * @retval HAL status
NYX 0:85b3fd62ea1a 478 */
NYX 0:85b3fd62ea1a 479 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
NYX 0:85b3fd62ea1a 480 {
NYX 0:85b3fd62ea1a 481 uint32_t i = 0U;
NYX 0:85b3fd62ea1a 482 ETH_DMADescTypeDef *dmatxdesc;
NYX 0:85b3fd62ea1a 483
NYX 0:85b3fd62ea1a 484 /* Process Locked */
NYX 0:85b3fd62ea1a 485 __HAL_LOCK(heth);
NYX 0:85b3fd62ea1a 486
NYX 0:85b3fd62ea1a 487 /* Set the ETH peripheral state to BUSY */
NYX 0:85b3fd62ea1a 488 heth->State = HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 489
NYX 0:85b3fd62ea1a 490 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
NYX 0:85b3fd62ea1a 491 heth->TxDesc = DMATxDescTab;
NYX 0:85b3fd62ea1a 492
NYX 0:85b3fd62ea1a 493 /* Fill each DMATxDesc descriptor with the right values */
NYX 0:85b3fd62ea1a 494 for(i=0U; i < TxBuffCount; i++)
NYX 0:85b3fd62ea1a 495 {
NYX 0:85b3fd62ea1a 496 /* Get the pointer on the ith member of the Tx Desc list */
NYX 0:85b3fd62ea1a 497 dmatxdesc = DMATxDescTab + i;
NYX 0:85b3fd62ea1a 498
NYX 0:85b3fd62ea1a 499 /* Set Second Address Chained bit */
NYX 0:85b3fd62ea1a 500 dmatxdesc->Status = ETH_DMATXDESC_TCH;
NYX 0:85b3fd62ea1a 501
NYX 0:85b3fd62ea1a 502 /* Set Buffer1 address pointer */
NYX 0:85b3fd62ea1a 503 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
NYX 0:85b3fd62ea1a 504
NYX 0:85b3fd62ea1a 505 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
NYX 0:85b3fd62ea1a 506 {
NYX 0:85b3fd62ea1a 507 /* Set the DMA Tx descriptors checksum insertion */
NYX 0:85b3fd62ea1a 508 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
NYX 0:85b3fd62ea1a 509 }
NYX 0:85b3fd62ea1a 510
NYX 0:85b3fd62ea1a 511 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
NYX 0:85b3fd62ea1a 512 if(i < (TxBuffCount-1U))
NYX 0:85b3fd62ea1a 513 {
NYX 0:85b3fd62ea1a 514 /* Set next descriptor address register with next descriptor base address */
NYX 0:85b3fd62ea1a 515 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
NYX 0:85b3fd62ea1a 516 }
NYX 0:85b3fd62ea1a 517 else
NYX 0:85b3fd62ea1a 518 {
NYX 0:85b3fd62ea1a 519 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
NYX 0:85b3fd62ea1a 520 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
NYX 0:85b3fd62ea1a 521 }
NYX 0:85b3fd62ea1a 522 }
NYX 0:85b3fd62ea1a 523
NYX 0:85b3fd62ea1a 524 /* Set Transmit Descriptor List Address Register */
NYX 0:85b3fd62ea1a 525 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
NYX 0:85b3fd62ea1a 526
NYX 0:85b3fd62ea1a 527 /* Set ETH HAL State to Ready */
NYX 0:85b3fd62ea1a 528 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 529
NYX 0:85b3fd62ea1a 530 /* Process Unlocked */
NYX 0:85b3fd62ea1a 531 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 532
NYX 0:85b3fd62ea1a 533 /* Return function status */
NYX 0:85b3fd62ea1a 534 return HAL_OK;
NYX 0:85b3fd62ea1a 535 }
NYX 0:85b3fd62ea1a 536
NYX 0:85b3fd62ea1a 537 /**
NYX 0:85b3fd62ea1a 538 * @brief Initializes the DMA Rx descriptors in chain mode.
NYX 0:85b3fd62ea1a 539 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 540 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 541 * @param DMARxDescTab: Pointer to the first Rx desc list
NYX 0:85b3fd62ea1a 542 * @param RxBuff: Pointer to the first RxBuffer list
NYX 0:85b3fd62ea1a 543 * @param RxBuffCount: Number of the used Rx desc in the list
NYX 0:85b3fd62ea1a 544 * @retval HAL status
NYX 0:85b3fd62ea1a 545 */
NYX 0:85b3fd62ea1a 546 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
NYX 0:85b3fd62ea1a 547 {
NYX 0:85b3fd62ea1a 548 uint32_t i = 0U;
NYX 0:85b3fd62ea1a 549 ETH_DMADescTypeDef *DMARxDesc;
NYX 0:85b3fd62ea1a 550
NYX 0:85b3fd62ea1a 551 /* Process Locked */
NYX 0:85b3fd62ea1a 552 __HAL_LOCK(heth);
NYX 0:85b3fd62ea1a 553
NYX 0:85b3fd62ea1a 554 /* Set the ETH peripheral state to BUSY */
NYX 0:85b3fd62ea1a 555 heth->State = HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 556
NYX 0:85b3fd62ea1a 557 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
NYX 0:85b3fd62ea1a 558 heth->RxDesc = DMARxDescTab;
NYX 0:85b3fd62ea1a 559
NYX 0:85b3fd62ea1a 560 /* Fill each DMARxDesc descriptor with the right values */
NYX 0:85b3fd62ea1a 561 for(i=0U; i < RxBuffCount; i++)
NYX 0:85b3fd62ea1a 562 {
NYX 0:85b3fd62ea1a 563 /* Get the pointer on the ith member of the Rx Desc list */
NYX 0:85b3fd62ea1a 564 DMARxDesc = DMARxDescTab+i;
NYX 0:85b3fd62ea1a 565
NYX 0:85b3fd62ea1a 566 /* Set Own bit of the Rx descriptor Status */
NYX 0:85b3fd62ea1a 567 DMARxDesc->Status = ETH_DMARXDESC_OWN;
NYX 0:85b3fd62ea1a 568
NYX 0:85b3fd62ea1a 569 /* Set Buffer1 size and Second Address Chained bit */
NYX 0:85b3fd62ea1a 570 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
NYX 0:85b3fd62ea1a 571
NYX 0:85b3fd62ea1a 572 /* Set Buffer1 address pointer */
NYX 0:85b3fd62ea1a 573 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
NYX 0:85b3fd62ea1a 574
NYX 0:85b3fd62ea1a 575 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
NYX 0:85b3fd62ea1a 576 {
NYX 0:85b3fd62ea1a 577 /* Enable Ethernet DMA Rx Descriptor interrupt */
NYX 0:85b3fd62ea1a 578 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
NYX 0:85b3fd62ea1a 579 }
NYX 0:85b3fd62ea1a 580
NYX 0:85b3fd62ea1a 581 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
NYX 0:85b3fd62ea1a 582 if(i < (RxBuffCount-1U))
NYX 0:85b3fd62ea1a 583 {
NYX 0:85b3fd62ea1a 584 /* Set next descriptor address register with next descriptor base address */
NYX 0:85b3fd62ea1a 585 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
NYX 0:85b3fd62ea1a 586 }
NYX 0:85b3fd62ea1a 587 else
NYX 0:85b3fd62ea1a 588 {
NYX 0:85b3fd62ea1a 589 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
NYX 0:85b3fd62ea1a 590 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
NYX 0:85b3fd62ea1a 591 }
NYX 0:85b3fd62ea1a 592 }
NYX 0:85b3fd62ea1a 593
NYX 0:85b3fd62ea1a 594 /* Set Receive Descriptor List Address Register */
NYX 0:85b3fd62ea1a 595 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
NYX 0:85b3fd62ea1a 596
NYX 0:85b3fd62ea1a 597 /* Set ETH HAL State to Ready */
NYX 0:85b3fd62ea1a 598 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 599
NYX 0:85b3fd62ea1a 600 /* Process Unlocked */
NYX 0:85b3fd62ea1a 601 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 602
NYX 0:85b3fd62ea1a 603 /* Return function status */
NYX 0:85b3fd62ea1a 604 return HAL_OK;
NYX 0:85b3fd62ea1a 605 }
NYX 0:85b3fd62ea1a 606
NYX 0:85b3fd62ea1a 607 /**
NYX 0:85b3fd62ea1a 608 * @brief Initializes the ETH MSP.
NYX 0:85b3fd62ea1a 609 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 610 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 611 * @retval None
NYX 0:85b3fd62ea1a 612 */
NYX 0:85b3fd62ea1a 613 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 614 {
NYX 0:85b3fd62ea1a 615 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 616 UNUSED(heth);
NYX 0:85b3fd62ea1a 617 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 618 the HAL_ETH_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 619 */
NYX 0:85b3fd62ea1a 620 }
NYX 0:85b3fd62ea1a 621
NYX 0:85b3fd62ea1a 622 /**
NYX 0:85b3fd62ea1a 623 * @brief DeInitializes ETH MSP.
NYX 0:85b3fd62ea1a 624 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 625 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 626 * @retval None
NYX 0:85b3fd62ea1a 627 */
NYX 0:85b3fd62ea1a 628 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 629 {
NYX 0:85b3fd62ea1a 630 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 631 UNUSED(heth);
NYX 0:85b3fd62ea1a 632 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 633 the HAL_ETH_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 634 */
NYX 0:85b3fd62ea1a 635 }
NYX 0:85b3fd62ea1a 636
NYX 0:85b3fd62ea1a 637 /**
NYX 0:85b3fd62ea1a 638 * @}
NYX 0:85b3fd62ea1a 639 */
NYX 0:85b3fd62ea1a 640
NYX 0:85b3fd62ea1a 641 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
NYX 0:85b3fd62ea1a 642 * @brief Data transfers functions
NYX 0:85b3fd62ea1a 643 *
NYX 0:85b3fd62ea1a 644 @verbatim
NYX 0:85b3fd62ea1a 645 ==============================================================================
NYX 0:85b3fd62ea1a 646 ##### IO operation functions #####
NYX 0:85b3fd62ea1a 647 ==============================================================================
NYX 0:85b3fd62ea1a 648 [..] This section provides functions allowing to:
NYX 0:85b3fd62ea1a 649 (+) Transmit a frame
NYX 0:85b3fd62ea1a 650 HAL_ETH_TransmitFrame();
NYX 0:85b3fd62ea1a 651 (+) Receive a frame
NYX 0:85b3fd62ea1a 652 HAL_ETH_GetReceivedFrame();
NYX 0:85b3fd62ea1a 653 HAL_ETH_GetReceivedFrame_IT();
NYX 0:85b3fd62ea1a 654 (+) Read from an External PHY register
NYX 0:85b3fd62ea1a 655 HAL_ETH_ReadPHYRegister();
NYX 0:85b3fd62ea1a 656 (+) Write to an External PHY register
NYX 0:85b3fd62ea1a 657 HAL_ETH_WritePHYRegister();
NYX 0:85b3fd62ea1a 658
NYX 0:85b3fd62ea1a 659 @endverbatim
NYX 0:85b3fd62ea1a 660
NYX 0:85b3fd62ea1a 661 * @{
NYX 0:85b3fd62ea1a 662 */
NYX 0:85b3fd62ea1a 663
NYX 0:85b3fd62ea1a 664 /**
NYX 0:85b3fd62ea1a 665 * @brief Sends an Ethernet frame.
NYX 0:85b3fd62ea1a 666 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 667 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 668 * @param FrameLength: Amount of data to be sent
NYX 0:85b3fd62ea1a 669 * @retval HAL status
NYX 0:85b3fd62ea1a 670 */
NYX 0:85b3fd62ea1a 671 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
NYX 0:85b3fd62ea1a 672 {
NYX 0:85b3fd62ea1a 673 uint32_t bufcount = 0U, size = 0U, i = 0U;
NYX 0:85b3fd62ea1a 674
NYX 0:85b3fd62ea1a 675 /* Process Locked */
NYX 0:85b3fd62ea1a 676 __HAL_LOCK(heth);
NYX 0:85b3fd62ea1a 677
NYX 0:85b3fd62ea1a 678 /* Set the ETH peripheral state to BUSY */
NYX 0:85b3fd62ea1a 679 heth->State = HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 680
NYX 0:85b3fd62ea1a 681 if (FrameLength == 0U)
NYX 0:85b3fd62ea1a 682 {
NYX 0:85b3fd62ea1a 683 /* Set ETH HAL state to READY */
NYX 0:85b3fd62ea1a 684 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 685
NYX 0:85b3fd62ea1a 686 /* Process Unlocked */
NYX 0:85b3fd62ea1a 687 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 688
NYX 0:85b3fd62ea1a 689 return HAL_ERROR;
NYX 0:85b3fd62ea1a 690 }
NYX 0:85b3fd62ea1a 691
NYX 0:85b3fd62ea1a 692 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
NYX 0:85b3fd62ea1a 693 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
NYX 0:85b3fd62ea1a 694 {
NYX 0:85b3fd62ea1a 695 /* OWN bit set */
NYX 0:85b3fd62ea1a 696 heth->State = HAL_ETH_STATE_BUSY_TX;
NYX 0:85b3fd62ea1a 697
NYX 0:85b3fd62ea1a 698 /* Process Unlocked */
NYX 0:85b3fd62ea1a 699 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 700
NYX 0:85b3fd62ea1a 701 return HAL_ERROR;
NYX 0:85b3fd62ea1a 702 }
NYX 0:85b3fd62ea1a 703
NYX 0:85b3fd62ea1a 704 /* Get the number of needed Tx buffers for the current frame */
NYX 0:85b3fd62ea1a 705 if (FrameLength > ETH_TX_BUF_SIZE)
NYX 0:85b3fd62ea1a 706 {
NYX 0:85b3fd62ea1a 707 bufcount = FrameLength/ETH_TX_BUF_SIZE;
NYX 0:85b3fd62ea1a 708 if (FrameLength % ETH_TX_BUF_SIZE)
NYX 0:85b3fd62ea1a 709 {
NYX 0:85b3fd62ea1a 710 bufcount++;
NYX 0:85b3fd62ea1a 711 }
NYX 0:85b3fd62ea1a 712 }
NYX 0:85b3fd62ea1a 713 else
NYX 0:85b3fd62ea1a 714 {
NYX 0:85b3fd62ea1a 715 bufcount = 1U;
NYX 0:85b3fd62ea1a 716 }
NYX 0:85b3fd62ea1a 717 if (bufcount == 1U)
NYX 0:85b3fd62ea1a 718 {
NYX 0:85b3fd62ea1a 719 /* Set LAST and FIRST segment */
NYX 0:85b3fd62ea1a 720 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
NYX 0:85b3fd62ea1a 721 /* Set frame size */
NYX 0:85b3fd62ea1a 722 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
NYX 0:85b3fd62ea1a 723 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
NYX 0:85b3fd62ea1a 724 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
NYX 0:85b3fd62ea1a 725 /* Point to next descriptor */
NYX 0:85b3fd62ea1a 726 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
NYX 0:85b3fd62ea1a 727 }
NYX 0:85b3fd62ea1a 728 else
NYX 0:85b3fd62ea1a 729 {
NYX 0:85b3fd62ea1a 730 for (i=0U; i< bufcount; i++)
NYX 0:85b3fd62ea1a 731 {
NYX 0:85b3fd62ea1a 732 /* Clear FIRST and LAST segment bits */
NYX 0:85b3fd62ea1a 733 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
NYX 0:85b3fd62ea1a 734
NYX 0:85b3fd62ea1a 735 if (i == 0U)
NYX 0:85b3fd62ea1a 736 {
NYX 0:85b3fd62ea1a 737 /* Setting the first segment bit */
NYX 0:85b3fd62ea1a 738 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
NYX 0:85b3fd62ea1a 739 }
NYX 0:85b3fd62ea1a 740
NYX 0:85b3fd62ea1a 741 /* Program size */
NYX 0:85b3fd62ea1a 742 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
NYX 0:85b3fd62ea1a 743
NYX 0:85b3fd62ea1a 744 if (i == (bufcount-1U))
NYX 0:85b3fd62ea1a 745 {
NYX 0:85b3fd62ea1a 746 /* Setting the last segment bit */
NYX 0:85b3fd62ea1a 747 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
NYX 0:85b3fd62ea1a 748 size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
NYX 0:85b3fd62ea1a 749 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
NYX 0:85b3fd62ea1a 750 }
NYX 0:85b3fd62ea1a 751
NYX 0:85b3fd62ea1a 752 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
NYX 0:85b3fd62ea1a 753 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
NYX 0:85b3fd62ea1a 754 /* point to next descriptor */
NYX 0:85b3fd62ea1a 755 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
NYX 0:85b3fd62ea1a 756 }
NYX 0:85b3fd62ea1a 757 }
NYX 0:85b3fd62ea1a 758
NYX 0:85b3fd62ea1a 759 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
NYX 0:85b3fd62ea1a 760 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
NYX 0:85b3fd62ea1a 761 {
NYX 0:85b3fd62ea1a 762 /* Clear TBUS ETHERNET DMA flag */
NYX 0:85b3fd62ea1a 763 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
NYX 0:85b3fd62ea1a 764 /* Resume DMA transmission*/
NYX 0:85b3fd62ea1a 765 (heth->Instance)->DMATPDR = 0U;
NYX 0:85b3fd62ea1a 766 }
NYX 0:85b3fd62ea1a 767
NYX 0:85b3fd62ea1a 768 /* Set ETH HAL State to Ready */
NYX 0:85b3fd62ea1a 769 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 770
NYX 0:85b3fd62ea1a 771 /* Process Unlocked */
NYX 0:85b3fd62ea1a 772 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 773
NYX 0:85b3fd62ea1a 774 /* Return function status */
NYX 0:85b3fd62ea1a 775 return HAL_OK;
NYX 0:85b3fd62ea1a 776 }
NYX 0:85b3fd62ea1a 777
NYX 0:85b3fd62ea1a 778 /**
NYX 0:85b3fd62ea1a 779 * @brief Checks for received frames.
NYX 0:85b3fd62ea1a 780 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 781 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 782 * @retval HAL status
NYX 0:85b3fd62ea1a 783 */
NYX 0:85b3fd62ea1a 784 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 785 {
NYX 0:85b3fd62ea1a 786 uint32_t framelength = 0U;
NYX 0:85b3fd62ea1a 787
NYX 0:85b3fd62ea1a 788 /* Process Locked */
NYX 0:85b3fd62ea1a 789 __HAL_LOCK(heth);
NYX 0:85b3fd62ea1a 790
NYX 0:85b3fd62ea1a 791 /* Check the ETH state to BUSY */
NYX 0:85b3fd62ea1a 792 heth->State = HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 793
NYX 0:85b3fd62ea1a 794 /* Check if segment is not owned by DMA */
NYX 0:85b3fd62ea1a 795 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
NYX 0:85b3fd62ea1a 796 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
NYX 0:85b3fd62ea1a 797 {
NYX 0:85b3fd62ea1a 798 /* Check if last segment */
NYX 0:85b3fd62ea1a 799 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
NYX 0:85b3fd62ea1a 800 {
NYX 0:85b3fd62ea1a 801 /* increment segment count */
NYX 0:85b3fd62ea1a 802 (heth->RxFrameInfos).SegCount++;
NYX 0:85b3fd62ea1a 803
NYX 0:85b3fd62ea1a 804 /* Check if last segment is first segment: one segment contains the frame */
NYX 0:85b3fd62ea1a 805 if ((heth->RxFrameInfos).SegCount == 1U)
NYX 0:85b3fd62ea1a 806 {
NYX 0:85b3fd62ea1a 807 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
NYX 0:85b3fd62ea1a 808 }
NYX 0:85b3fd62ea1a 809
NYX 0:85b3fd62ea1a 810 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
NYX 0:85b3fd62ea1a 811
NYX 0:85b3fd62ea1a 812 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
NYX 0:85b3fd62ea1a 813 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
NYX 0:85b3fd62ea1a 814 heth->RxFrameInfos.length = framelength;
NYX 0:85b3fd62ea1a 815
NYX 0:85b3fd62ea1a 816 /* Get the address of the buffer start address */
NYX 0:85b3fd62ea1a 817 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
NYX 0:85b3fd62ea1a 818 /* point to next descriptor */
NYX 0:85b3fd62ea1a 819 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
NYX 0:85b3fd62ea1a 820
NYX 0:85b3fd62ea1a 821 /* Set HAL State to Ready */
NYX 0:85b3fd62ea1a 822 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 823
NYX 0:85b3fd62ea1a 824 /* Process Unlocked */
NYX 0:85b3fd62ea1a 825 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 826
NYX 0:85b3fd62ea1a 827 /* Return function status */
NYX 0:85b3fd62ea1a 828 return HAL_OK;
NYX 0:85b3fd62ea1a 829 }
NYX 0:85b3fd62ea1a 830 /* Check if first segment */
NYX 0:85b3fd62ea1a 831 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
NYX 0:85b3fd62ea1a 832 {
NYX 0:85b3fd62ea1a 833 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
NYX 0:85b3fd62ea1a 834 (heth->RxFrameInfos).LSRxDesc = NULL;
NYX 0:85b3fd62ea1a 835 (heth->RxFrameInfos).SegCount = 1U;
NYX 0:85b3fd62ea1a 836 /* Point to next descriptor */
NYX 0:85b3fd62ea1a 837 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
NYX 0:85b3fd62ea1a 838 }
NYX 0:85b3fd62ea1a 839 /* Check if intermediate segment */
NYX 0:85b3fd62ea1a 840 else
NYX 0:85b3fd62ea1a 841 {
NYX 0:85b3fd62ea1a 842 (heth->RxFrameInfos).SegCount++;
NYX 0:85b3fd62ea1a 843 /* Point to next descriptor */
NYX 0:85b3fd62ea1a 844 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
NYX 0:85b3fd62ea1a 845 }
NYX 0:85b3fd62ea1a 846 }
NYX 0:85b3fd62ea1a 847
NYX 0:85b3fd62ea1a 848 /* Set ETH HAL State to Ready */
NYX 0:85b3fd62ea1a 849 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 850
NYX 0:85b3fd62ea1a 851 /* Process Unlocked */
NYX 0:85b3fd62ea1a 852 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 853
NYX 0:85b3fd62ea1a 854 /* Return function status */
NYX 0:85b3fd62ea1a 855 return HAL_ERROR;
NYX 0:85b3fd62ea1a 856 }
NYX 0:85b3fd62ea1a 857
NYX 0:85b3fd62ea1a 858 /**
NYX 0:85b3fd62ea1a 859 * @brief Gets the Received frame in interrupt mode.
NYX 0:85b3fd62ea1a 860 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 861 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 862 * @retval HAL status
NYX 0:85b3fd62ea1a 863 */
NYX 0:85b3fd62ea1a 864 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 865 {
NYX 0:85b3fd62ea1a 866 uint32_t descriptorscancounter = 0U;
NYX 0:85b3fd62ea1a 867
NYX 0:85b3fd62ea1a 868 /* Process Locked */
NYX 0:85b3fd62ea1a 869 __HAL_LOCK(heth);
NYX 0:85b3fd62ea1a 870
NYX 0:85b3fd62ea1a 871 /* Set ETH HAL State to BUSY */
NYX 0:85b3fd62ea1a 872 heth->State = HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 873
NYX 0:85b3fd62ea1a 874 /* Scan descriptors owned by CPU */
NYX 0:85b3fd62ea1a 875 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
NYX 0:85b3fd62ea1a 876 {
NYX 0:85b3fd62ea1a 877 /* Just for security */
NYX 0:85b3fd62ea1a 878 descriptorscancounter++;
NYX 0:85b3fd62ea1a 879
NYX 0:85b3fd62ea1a 880 /* Check if first segment in frame */
NYX 0:85b3fd62ea1a 881 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
NYX 0:85b3fd62ea1a 882 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
NYX 0:85b3fd62ea1a 883 {
NYX 0:85b3fd62ea1a 884 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
NYX 0:85b3fd62ea1a 885 heth->RxFrameInfos.SegCount = 1U;
NYX 0:85b3fd62ea1a 886 /* Point to next descriptor */
NYX 0:85b3fd62ea1a 887 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
NYX 0:85b3fd62ea1a 888 }
NYX 0:85b3fd62ea1a 889 /* Check if intermediate segment */
NYX 0:85b3fd62ea1a 890 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
NYX 0:85b3fd62ea1a 891 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
NYX 0:85b3fd62ea1a 892 {
NYX 0:85b3fd62ea1a 893 /* Increment segment count */
NYX 0:85b3fd62ea1a 894 (heth->RxFrameInfos.SegCount)++;
NYX 0:85b3fd62ea1a 895 /* Point to next descriptor */
NYX 0:85b3fd62ea1a 896 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
NYX 0:85b3fd62ea1a 897 }
NYX 0:85b3fd62ea1a 898 /* Should be last segment */
NYX 0:85b3fd62ea1a 899 else
NYX 0:85b3fd62ea1a 900 {
NYX 0:85b3fd62ea1a 901 /* Last segment */
NYX 0:85b3fd62ea1a 902 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
NYX 0:85b3fd62ea1a 903
NYX 0:85b3fd62ea1a 904 /* Increment segment count */
NYX 0:85b3fd62ea1a 905 (heth->RxFrameInfos.SegCount)++;
NYX 0:85b3fd62ea1a 906
NYX 0:85b3fd62ea1a 907 /* Check if last segment is first segment: one segment contains the frame */
NYX 0:85b3fd62ea1a 908 if ((heth->RxFrameInfos.SegCount) == 1U)
NYX 0:85b3fd62ea1a 909 {
NYX 0:85b3fd62ea1a 910 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
NYX 0:85b3fd62ea1a 911 }
NYX 0:85b3fd62ea1a 912
NYX 0:85b3fd62ea1a 913 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
NYX 0:85b3fd62ea1a 914 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
NYX 0:85b3fd62ea1a 915
NYX 0:85b3fd62ea1a 916 /* Get the address of the buffer start address */
NYX 0:85b3fd62ea1a 917 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
NYX 0:85b3fd62ea1a 918
NYX 0:85b3fd62ea1a 919 /* Point to next descriptor */
NYX 0:85b3fd62ea1a 920 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
NYX 0:85b3fd62ea1a 921
NYX 0:85b3fd62ea1a 922 /* Set HAL State to Ready */
NYX 0:85b3fd62ea1a 923 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 924
NYX 0:85b3fd62ea1a 925 /* Process Unlocked */
NYX 0:85b3fd62ea1a 926 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 927
NYX 0:85b3fd62ea1a 928 /* Return function status */
NYX 0:85b3fd62ea1a 929 return HAL_OK;
NYX 0:85b3fd62ea1a 930 }
NYX 0:85b3fd62ea1a 931 }
NYX 0:85b3fd62ea1a 932
NYX 0:85b3fd62ea1a 933 /* Set HAL State to Ready */
NYX 0:85b3fd62ea1a 934 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 935
NYX 0:85b3fd62ea1a 936 /* Process Unlocked */
NYX 0:85b3fd62ea1a 937 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 938
NYX 0:85b3fd62ea1a 939 /* Return function status */
NYX 0:85b3fd62ea1a 940 return HAL_ERROR;
NYX 0:85b3fd62ea1a 941 }
NYX 0:85b3fd62ea1a 942
NYX 0:85b3fd62ea1a 943 /**
NYX 0:85b3fd62ea1a 944 * @brief This function handles ETH interrupt request.
NYX 0:85b3fd62ea1a 945 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 946 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 947 * @retval HAL status
NYX 0:85b3fd62ea1a 948 */
NYX 0:85b3fd62ea1a 949 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 950 {
NYX 0:85b3fd62ea1a 951 /* Frame received */
NYX 0:85b3fd62ea1a 952 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
NYX 0:85b3fd62ea1a 953 {
NYX 0:85b3fd62ea1a 954 /* Receive complete callback */
NYX 0:85b3fd62ea1a 955 HAL_ETH_RxCpltCallback(heth);
NYX 0:85b3fd62ea1a 956
NYX 0:85b3fd62ea1a 957 /* Clear the Eth DMA Rx IT pending bits */
NYX 0:85b3fd62ea1a 958 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
NYX 0:85b3fd62ea1a 959
NYX 0:85b3fd62ea1a 960 /* Set HAL State to Ready */
NYX 0:85b3fd62ea1a 961 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 962
NYX 0:85b3fd62ea1a 963 /* Process Unlocked */
NYX 0:85b3fd62ea1a 964 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 965
NYX 0:85b3fd62ea1a 966 }
NYX 0:85b3fd62ea1a 967 /* Frame transmitted */
NYX 0:85b3fd62ea1a 968 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
NYX 0:85b3fd62ea1a 969 {
NYX 0:85b3fd62ea1a 970 /* Transfer complete callback */
NYX 0:85b3fd62ea1a 971 HAL_ETH_TxCpltCallback(heth);
NYX 0:85b3fd62ea1a 972
NYX 0:85b3fd62ea1a 973 /* Clear the Eth DMA Tx IT pending bits */
NYX 0:85b3fd62ea1a 974 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
NYX 0:85b3fd62ea1a 975
NYX 0:85b3fd62ea1a 976 /* Set HAL State to Ready */
NYX 0:85b3fd62ea1a 977 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 978
NYX 0:85b3fd62ea1a 979 /* Process Unlocked */
NYX 0:85b3fd62ea1a 980 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 981 }
NYX 0:85b3fd62ea1a 982
NYX 0:85b3fd62ea1a 983 /* Clear the interrupt flags */
NYX 0:85b3fd62ea1a 984 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
NYX 0:85b3fd62ea1a 985
NYX 0:85b3fd62ea1a 986 /* ETH DMA Error */
NYX 0:85b3fd62ea1a 987 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
NYX 0:85b3fd62ea1a 988 {
NYX 0:85b3fd62ea1a 989 /* Ethernet Error callback */
NYX 0:85b3fd62ea1a 990 HAL_ETH_ErrorCallback(heth);
NYX 0:85b3fd62ea1a 991
NYX 0:85b3fd62ea1a 992 /* Clear the interrupt flags */
NYX 0:85b3fd62ea1a 993 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
NYX 0:85b3fd62ea1a 994
NYX 0:85b3fd62ea1a 995 /* Set HAL State to Ready */
NYX 0:85b3fd62ea1a 996 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 997
NYX 0:85b3fd62ea1a 998 /* Process Unlocked */
NYX 0:85b3fd62ea1a 999 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 1000 }
NYX 0:85b3fd62ea1a 1001 }
NYX 0:85b3fd62ea1a 1002
NYX 0:85b3fd62ea1a 1003 /**
NYX 0:85b3fd62ea1a 1004 * @brief Tx Transfer completed callbacks.
NYX 0:85b3fd62ea1a 1005 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1006 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1007 * @retval None
NYX 0:85b3fd62ea1a 1008 */
NYX 0:85b3fd62ea1a 1009 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1010 {
NYX 0:85b3fd62ea1a 1011 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1012 UNUSED(heth);
NYX 0:85b3fd62ea1a 1013 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1014 the HAL_ETH_TxCpltCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 1015 */
NYX 0:85b3fd62ea1a 1016 }
NYX 0:85b3fd62ea1a 1017
NYX 0:85b3fd62ea1a 1018 /**
NYX 0:85b3fd62ea1a 1019 * @brief Rx Transfer completed callbacks.
NYX 0:85b3fd62ea1a 1020 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1021 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1022 * @retval None
NYX 0:85b3fd62ea1a 1023 */
NYX 0:85b3fd62ea1a 1024 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1025 {
NYX 0:85b3fd62ea1a 1026 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1027 UNUSED(heth);
NYX 0:85b3fd62ea1a 1028 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1029 the HAL_ETH_TxCpltCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 1030 */
NYX 0:85b3fd62ea1a 1031 }
NYX 0:85b3fd62ea1a 1032
NYX 0:85b3fd62ea1a 1033 /**
NYX 0:85b3fd62ea1a 1034 * @brief Ethernet transfer error callbacks
NYX 0:85b3fd62ea1a 1035 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1036 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1037 * @retval None
NYX 0:85b3fd62ea1a 1038 */
NYX 0:85b3fd62ea1a 1039 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1040 {
NYX 0:85b3fd62ea1a 1041 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1042 UNUSED(heth);
NYX 0:85b3fd62ea1a 1043 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1044 the HAL_ETH_TxCpltCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 1045 */
NYX 0:85b3fd62ea1a 1046 }
NYX 0:85b3fd62ea1a 1047
NYX 0:85b3fd62ea1a 1048 /**
NYX 0:85b3fd62ea1a 1049 * @brief Reads a PHY register
NYX 0:85b3fd62ea1a 1050 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1051 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1052 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
NYX 0:85b3fd62ea1a 1053 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1054 * PHY_BCR: Transceiver Basic Control Register,
NYX 0:85b3fd62ea1a 1055 * PHY_BSR: Transceiver Basic Status Register.
NYX 0:85b3fd62ea1a 1056 * More PHY register could be read depending on the used PHY
NYX 0:85b3fd62ea1a 1057 * @param RegValue: PHY register value
NYX 0:85b3fd62ea1a 1058 * @retval HAL status
NYX 0:85b3fd62ea1a 1059 */
NYX 0:85b3fd62ea1a 1060 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
NYX 0:85b3fd62ea1a 1061 {
NYX 0:85b3fd62ea1a 1062 uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 1063 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1064
NYX 0:85b3fd62ea1a 1065 /* Check parameters */
NYX 0:85b3fd62ea1a 1066 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
NYX 0:85b3fd62ea1a 1067
NYX 0:85b3fd62ea1a 1068 /* Check the ETH peripheral state */
NYX 0:85b3fd62ea1a 1069 if(heth->State == HAL_ETH_STATE_BUSY_RD)
NYX 0:85b3fd62ea1a 1070 {
NYX 0:85b3fd62ea1a 1071 return HAL_BUSY;
NYX 0:85b3fd62ea1a 1072 }
NYX 0:85b3fd62ea1a 1073 /* Set ETH HAL State to BUSY_RD */
NYX 0:85b3fd62ea1a 1074 heth->State = HAL_ETH_STATE_BUSY_RD;
NYX 0:85b3fd62ea1a 1075
NYX 0:85b3fd62ea1a 1076 /* Get the ETHERNET MACMIIAR value */
NYX 0:85b3fd62ea1a 1077 tmpreg1 = heth->Instance->MACMIIAR;
NYX 0:85b3fd62ea1a 1078
NYX 0:85b3fd62ea1a 1079 /* Keep only the CSR Clock Range CR[2:0] bits value */
NYX 0:85b3fd62ea1a 1080 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
NYX 0:85b3fd62ea1a 1081
NYX 0:85b3fd62ea1a 1082 /* Prepare the MII address register value */
NYX 0:85b3fd62ea1a 1083 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
NYX 0:85b3fd62ea1a 1084 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
NYX 0:85b3fd62ea1a 1085 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
NYX 0:85b3fd62ea1a 1086 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
NYX 0:85b3fd62ea1a 1087
NYX 0:85b3fd62ea1a 1088 /* Write the result value into the MII Address register */
NYX 0:85b3fd62ea1a 1089 heth->Instance->MACMIIAR = tmpreg1;
NYX 0:85b3fd62ea1a 1090
NYX 0:85b3fd62ea1a 1091 /* Get tick */
NYX 0:85b3fd62ea1a 1092 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1093
NYX 0:85b3fd62ea1a 1094 /* Check for the Busy flag */
NYX 0:85b3fd62ea1a 1095 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
NYX 0:85b3fd62ea1a 1096 {
NYX 0:85b3fd62ea1a 1097 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1098 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
NYX 0:85b3fd62ea1a 1099 {
NYX 0:85b3fd62ea1a 1100 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 1101
NYX 0:85b3fd62ea1a 1102 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1103 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 1104
NYX 0:85b3fd62ea1a 1105 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1106 }
NYX 0:85b3fd62ea1a 1107
NYX 0:85b3fd62ea1a 1108 tmpreg1 = heth->Instance->MACMIIAR;
NYX 0:85b3fd62ea1a 1109 }
NYX 0:85b3fd62ea1a 1110
NYX 0:85b3fd62ea1a 1111 /* Get MACMIIDR value */
NYX 0:85b3fd62ea1a 1112 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
NYX 0:85b3fd62ea1a 1113
NYX 0:85b3fd62ea1a 1114 /* Set ETH HAL State to READY */
NYX 0:85b3fd62ea1a 1115 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 1116
NYX 0:85b3fd62ea1a 1117 /* Return function status */
NYX 0:85b3fd62ea1a 1118 return HAL_OK;
NYX 0:85b3fd62ea1a 1119 }
NYX 0:85b3fd62ea1a 1120
NYX 0:85b3fd62ea1a 1121 /**
NYX 0:85b3fd62ea1a 1122 * @brief Writes to a PHY register.
NYX 0:85b3fd62ea1a 1123 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1124 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1125 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
NYX 0:85b3fd62ea1a 1126 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1127 * PHY_BCR: Transceiver Control Register.
NYX 0:85b3fd62ea1a 1128 * More PHY register could be written depending on the used PHY
NYX 0:85b3fd62ea1a 1129 * @param RegValue: the value to write
NYX 0:85b3fd62ea1a 1130 * @retval HAL status
NYX 0:85b3fd62ea1a 1131 */
NYX 0:85b3fd62ea1a 1132 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
NYX 0:85b3fd62ea1a 1133 {
NYX 0:85b3fd62ea1a 1134 uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 1135 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1136
NYX 0:85b3fd62ea1a 1137 /* Check parameters */
NYX 0:85b3fd62ea1a 1138 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
NYX 0:85b3fd62ea1a 1139
NYX 0:85b3fd62ea1a 1140 /* Check the ETH peripheral state */
NYX 0:85b3fd62ea1a 1141 if(heth->State == HAL_ETH_STATE_BUSY_WR)
NYX 0:85b3fd62ea1a 1142 {
NYX 0:85b3fd62ea1a 1143 return HAL_BUSY;
NYX 0:85b3fd62ea1a 1144 }
NYX 0:85b3fd62ea1a 1145 /* Set ETH HAL State to BUSY_WR */
NYX 0:85b3fd62ea1a 1146 heth->State = HAL_ETH_STATE_BUSY_WR;
NYX 0:85b3fd62ea1a 1147
NYX 0:85b3fd62ea1a 1148 /* Get the ETHERNET MACMIIAR value */
NYX 0:85b3fd62ea1a 1149 tmpreg1 = heth->Instance->MACMIIAR;
NYX 0:85b3fd62ea1a 1150
NYX 0:85b3fd62ea1a 1151 /* Keep only the CSR Clock Range CR[2:0] bits value */
NYX 0:85b3fd62ea1a 1152 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
NYX 0:85b3fd62ea1a 1153
NYX 0:85b3fd62ea1a 1154 /* Prepare the MII register address value */
NYX 0:85b3fd62ea1a 1155 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
NYX 0:85b3fd62ea1a 1156 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
NYX 0:85b3fd62ea1a 1157 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
NYX 0:85b3fd62ea1a 1158 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
NYX 0:85b3fd62ea1a 1159
NYX 0:85b3fd62ea1a 1160 /* Give the value to the MII data register */
NYX 0:85b3fd62ea1a 1161 heth->Instance->MACMIIDR = (uint16_t)RegValue;
NYX 0:85b3fd62ea1a 1162
NYX 0:85b3fd62ea1a 1163 /* Write the result value into the MII Address register */
NYX 0:85b3fd62ea1a 1164 heth->Instance->MACMIIAR = tmpreg1;
NYX 0:85b3fd62ea1a 1165
NYX 0:85b3fd62ea1a 1166 /* Get tick */
NYX 0:85b3fd62ea1a 1167 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1168
NYX 0:85b3fd62ea1a 1169 /* Check for the Busy flag */
NYX 0:85b3fd62ea1a 1170 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
NYX 0:85b3fd62ea1a 1171 {
NYX 0:85b3fd62ea1a 1172 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1173 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
NYX 0:85b3fd62ea1a 1174 {
NYX 0:85b3fd62ea1a 1175 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 1176
NYX 0:85b3fd62ea1a 1177 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1178 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 1179
NYX 0:85b3fd62ea1a 1180 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1181 }
NYX 0:85b3fd62ea1a 1182
NYX 0:85b3fd62ea1a 1183 tmpreg1 = heth->Instance->MACMIIAR;
NYX 0:85b3fd62ea1a 1184 }
NYX 0:85b3fd62ea1a 1185
NYX 0:85b3fd62ea1a 1186 /* Set ETH HAL State to READY */
NYX 0:85b3fd62ea1a 1187 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 1188
NYX 0:85b3fd62ea1a 1189 /* Return function status */
NYX 0:85b3fd62ea1a 1190 return HAL_OK;
NYX 0:85b3fd62ea1a 1191 }
NYX 0:85b3fd62ea1a 1192
NYX 0:85b3fd62ea1a 1193 /**
NYX 0:85b3fd62ea1a 1194 * @}
NYX 0:85b3fd62ea1a 1195 */
NYX 0:85b3fd62ea1a 1196
NYX 0:85b3fd62ea1a 1197 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
NYX 0:85b3fd62ea1a 1198 * @brief Peripheral Control functions
NYX 0:85b3fd62ea1a 1199 *
NYX 0:85b3fd62ea1a 1200 @verbatim
NYX 0:85b3fd62ea1a 1201 ===============================================================================
NYX 0:85b3fd62ea1a 1202 ##### Peripheral Control functions #####
NYX 0:85b3fd62ea1a 1203 ===============================================================================
NYX 0:85b3fd62ea1a 1204 [..] This section provides functions allowing to:
NYX 0:85b3fd62ea1a 1205 (+) Enable MAC and DMA transmission and reception.
NYX 0:85b3fd62ea1a 1206 HAL_ETH_Start();
NYX 0:85b3fd62ea1a 1207 (+) Disable MAC and DMA transmission and reception.
NYX 0:85b3fd62ea1a 1208 HAL_ETH_Stop();
NYX 0:85b3fd62ea1a 1209 (+) Set the MAC configuration in runtime mode
NYX 0:85b3fd62ea1a 1210 HAL_ETH_ConfigMAC();
NYX 0:85b3fd62ea1a 1211 (+) Set the DMA configuration in runtime mode
NYX 0:85b3fd62ea1a 1212 HAL_ETH_ConfigDMA();
NYX 0:85b3fd62ea1a 1213
NYX 0:85b3fd62ea1a 1214 @endverbatim
NYX 0:85b3fd62ea1a 1215 * @{
NYX 0:85b3fd62ea1a 1216 */
NYX 0:85b3fd62ea1a 1217
NYX 0:85b3fd62ea1a 1218 /**
NYX 0:85b3fd62ea1a 1219 * @brief Enables Ethernet MAC and DMA reception/transmission
NYX 0:85b3fd62ea1a 1220 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1221 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1222 * @retval HAL status
NYX 0:85b3fd62ea1a 1223 */
NYX 0:85b3fd62ea1a 1224 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1225 {
NYX 0:85b3fd62ea1a 1226 /* Process Locked */
NYX 0:85b3fd62ea1a 1227 __HAL_LOCK(heth);
NYX 0:85b3fd62ea1a 1228
NYX 0:85b3fd62ea1a 1229 /* Set the ETH peripheral state to BUSY */
NYX 0:85b3fd62ea1a 1230 heth->State = HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 1231
NYX 0:85b3fd62ea1a 1232 /* Enable transmit state machine of the MAC for transmission on the MII */
NYX 0:85b3fd62ea1a 1233 ETH_MACTransmissionEnable(heth);
NYX 0:85b3fd62ea1a 1234
NYX 0:85b3fd62ea1a 1235 /* Enable receive state machine of the MAC for reception from the MII */
NYX 0:85b3fd62ea1a 1236 ETH_MACReceptionEnable(heth);
NYX 0:85b3fd62ea1a 1237
NYX 0:85b3fd62ea1a 1238 /* Flush Transmit FIFO */
NYX 0:85b3fd62ea1a 1239 ETH_FlushTransmitFIFO(heth);
NYX 0:85b3fd62ea1a 1240
NYX 0:85b3fd62ea1a 1241 /* Start DMA transmission */
NYX 0:85b3fd62ea1a 1242 ETH_DMATransmissionEnable(heth);
NYX 0:85b3fd62ea1a 1243
NYX 0:85b3fd62ea1a 1244 /* Start DMA reception */
NYX 0:85b3fd62ea1a 1245 ETH_DMAReceptionEnable(heth);
NYX 0:85b3fd62ea1a 1246
NYX 0:85b3fd62ea1a 1247 /* Set the ETH state to READY*/
NYX 0:85b3fd62ea1a 1248 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 1249
NYX 0:85b3fd62ea1a 1250 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1251 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 1252
NYX 0:85b3fd62ea1a 1253 /* Return function status */
NYX 0:85b3fd62ea1a 1254 return HAL_OK;
NYX 0:85b3fd62ea1a 1255 }
NYX 0:85b3fd62ea1a 1256
NYX 0:85b3fd62ea1a 1257 /**
NYX 0:85b3fd62ea1a 1258 * @brief Stop Ethernet MAC and DMA reception/transmission
NYX 0:85b3fd62ea1a 1259 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1260 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1261 * @retval HAL status
NYX 0:85b3fd62ea1a 1262 */
NYX 0:85b3fd62ea1a 1263 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1264 {
NYX 0:85b3fd62ea1a 1265 /* Process Locked */
NYX 0:85b3fd62ea1a 1266 __HAL_LOCK(heth);
NYX 0:85b3fd62ea1a 1267
NYX 0:85b3fd62ea1a 1268 /* Set the ETH peripheral state to BUSY */
NYX 0:85b3fd62ea1a 1269 heth->State = HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 1270
NYX 0:85b3fd62ea1a 1271 /* Stop DMA transmission */
NYX 0:85b3fd62ea1a 1272 ETH_DMATransmissionDisable(heth);
NYX 0:85b3fd62ea1a 1273
NYX 0:85b3fd62ea1a 1274 /* Stop DMA reception */
NYX 0:85b3fd62ea1a 1275 ETH_DMAReceptionDisable(heth);
NYX 0:85b3fd62ea1a 1276
NYX 0:85b3fd62ea1a 1277 /* Disable receive state machine of the MAC for reception from the MII */
NYX 0:85b3fd62ea1a 1278 ETH_MACReceptionDisable(heth);
NYX 0:85b3fd62ea1a 1279
NYX 0:85b3fd62ea1a 1280 /* Flush Transmit FIFO */
NYX 0:85b3fd62ea1a 1281 ETH_FlushTransmitFIFO(heth);
NYX 0:85b3fd62ea1a 1282
NYX 0:85b3fd62ea1a 1283 /* Disable transmit state machine of the MAC for transmission on the MII */
NYX 0:85b3fd62ea1a 1284 ETH_MACTransmissionDisable(heth);
NYX 0:85b3fd62ea1a 1285
NYX 0:85b3fd62ea1a 1286 /* Set the ETH state*/
NYX 0:85b3fd62ea1a 1287 heth->State = HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 1288
NYX 0:85b3fd62ea1a 1289 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1290 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 1291
NYX 0:85b3fd62ea1a 1292 /* Return function status */
NYX 0:85b3fd62ea1a 1293 return HAL_OK;
NYX 0:85b3fd62ea1a 1294 }
NYX 0:85b3fd62ea1a 1295
NYX 0:85b3fd62ea1a 1296 /**
NYX 0:85b3fd62ea1a 1297 * @brief Set ETH MAC Configuration.
NYX 0:85b3fd62ea1a 1298 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1299 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1300 * @param macconf: MAC Configuration structure
NYX 0:85b3fd62ea1a 1301 * @retval HAL status
NYX 0:85b3fd62ea1a 1302 */
NYX 0:85b3fd62ea1a 1303 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
NYX 0:85b3fd62ea1a 1304 {
NYX 0:85b3fd62ea1a 1305 uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 1306
NYX 0:85b3fd62ea1a 1307 /* Process Locked */
NYX 0:85b3fd62ea1a 1308 __HAL_LOCK(heth);
NYX 0:85b3fd62ea1a 1309
NYX 0:85b3fd62ea1a 1310 /* Set the ETH peripheral state to BUSY */
NYX 0:85b3fd62ea1a 1311 heth->State= HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 1312
NYX 0:85b3fd62ea1a 1313 assert_param(IS_ETH_SPEED(heth->Init.Speed));
NYX 0:85b3fd62ea1a 1314 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
NYX 0:85b3fd62ea1a 1315
NYX 0:85b3fd62ea1a 1316 if (macconf != NULL)
NYX 0:85b3fd62ea1a 1317 {
NYX 0:85b3fd62ea1a 1318 /* Check the parameters */
NYX 0:85b3fd62ea1a 1319 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
NYX 0:85b3fd62ea1a 1320 assert_param(IS_ETH_JABBER(macconf->Jabber));
NYX 0:85b3fd62ea1a 1321 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
NYX 0:85b3fd62ea1a 1322 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
NYX 0:85b3fd62ea1a 1323 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
NYX 0:85b3fd62ea1a 1324 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
NYX 0:85b3fd62ea1a 1325 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
NYX 0:85b3fd62ea1a 1326 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
NYX 0:85b3fd62ea1a 1327 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
NYX 0:85b3fd62ea1a 1328 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
NYX 0:85b3fd62ea1a 1329 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
NYX 0:85b3fd62ea1a 1330 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
NYX 0:85b3fd62ea1a 1331 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
NYX 0:85b3fd62ea1a 1332 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
NYX 0:85b3fd62ea1a 1333 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
NYX 0:85b3fd62ea1a 1334 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
NYX 0:85b3fd62ea1a 1335 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
NYX 0:85b3fd62ea1a 1336 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
NYX 0:85b3fd62ea1a 1337 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
NYX 0:85b3fd62ea1a 1338 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
NYX 0:85b3fd62ea1a 1339 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
NYX 0:85b3fd62ea1a 1340 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
NYX 0:85b3fd62ea1a 1341 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
NYX 0:85b3fd62ea1a 1342 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
NYX 0:85b3fd62ea1a 1343 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
NYX 0:85b3fd62ea1a 1344 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
NYX 0:85b3fd62ea1a 1345 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
NYX 0:85b3fd62ea1a 1346
NYX 0:85b3fd62ea1a 1347 /*------------------------ ETHERNET MACCR Configuration --------------------*/
NYX 0:85b3fd62ea1a 1348 /* Get the ETHERNET MACCR value */
NYX 0:85b3fd62ea1a 1349 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1350 /* Clear WD, PCE, PS, TE and RE bits */
NYX 0:85b3fd62ea1a 1351 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
NYX 0:85b3fd62ea1a 1352
NYX 0:85b3fd62ea1a 1353 tmpreg1 |= (uint32_t)(macconf->Watchdog |
NYX 0:85b3fd62ea1a 1354 macconf->Jabber |
NYX 0:85b3fd62ea1a 1355 macconf->InterFrameGap |
NYX 0:85b3fd62ea1a 1356 macconf->CarrierSense |
NYX 0:85b3fd62ea1a 1357 (heth->Init).Speed |
NYX 0:85b3fd62ea1a 1358 macconf->ReceiveOwn |
NYX 0:85b3fd62ea1a 1359 macconf->LoopbackMode |
NYX 0:85b3fd62ea1a 1360 (heth->Init).DuplexMode |
NYX 0:85b3fd62ea1a 1361 macconf->ChecksumOffload |
NYX 0:85b3fd62ea1a 1362 macconf->RetryTransmission |
NYX 0:85b3fd62ea1a 1363 macconf->AutomaticPadCRCStrip |
NYX 0:85b3fd62ea1a 1364 macconf->BackOffLimit |
NYX 0:85b3fd62ea1a 1365 macconf->DeferralCheck);
NYX 0:85b3fd62ea1a 1366
NYX 0:85b3fd62ea1a 1367 /* Write to ETHERNET MACCR */
NYX 0:85b3fd62ea1a 1368 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
NYX 0:85b3fd62ea1a 1369
NYX 0:85b3fd62ea1a 1370 /* Wait until the write operation will be taken into account :
NYX 0:85b3fd62ea1a 1371 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1372 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1373 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1374 (heth->Instance)->MACCR = tmpreg1;
NYX 0:85b3fd62ea1a 1375
NYX 0:85b3fd62ea1a 1376 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
NYX 0:85b3fd62ea1a 1377 /* Write to ETHERNET MACFFR */
NYX 0:85b3fd62ea1a 1378 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
NYX 0:85b3fd62ea1a 1379 macconf->SourceAddrFilter |
NYX 0:85b3fd62ea1a 1380 macconf->PassControlFrames |
NYX 0:85b3fd62ea1a 1381 macconf->BroadcastFramesReception |
NYX 0:85b3fd62ea1a 1382 macconf->DestinationAddrFilter |
NYX 0:85b3fd62ea1a 1383 macconf->PromiscuousMode |
NYX 0:85b3fd62ea1a 1384 macconf->MulticastFramesFilter |
NYX 0:85b3fd62ea1a 1385 macconf->UnicastFramesFilter);
NYX 0:85b3fd62ea1a 1386
NYX 0:85b3fd62ea1a 1387 /* Wait until the write operation will be taken into account :
NYX 0:85b3fd62ea1a 1388 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1389 tmpreg1 = (heth->Instance)->MACFFR;
NYX 0:85b3fd62ea1a 1390 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1391 (heth->Instance)->MACFFR = tmpreg1;
NYX 0:85b3fd62ea1a 1392
NYX 0:85b3fd62ea1a 1393 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
NYX 0:85b3fd62ea1a 1394 /* Write to ETHERNET MACHTHR */
NYX 0:85b3fd62ea1a 1395 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
NYX 0:85b3fd62ea1a 1396
NYX 0:85b3fd62ea1a 1397 /* Write to ETHERNET MACHTLR */
NYX 0:85b3fd62ea1a 1398 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
NYX 0:85b3fd62ea1a 1399 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
NYX 0:85b3fd62ea1a 1400
NYX 0:85b3fd62ea1a 1401 /* Get the ETHERNET MACFCR value */
NYX 0:85b3fd62ea1a 1402 tmpreg1 = (heth->Instance)->MACFCR;
NYX 0:85b3fd62ea1a 1403 /* Clear xx bits */
NYX 0:85b3fd62ea1a 1404 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
NYX 0:85b3fd62ea1a 1405
NYX 0:85b3fd62ea1a 1406 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
NYX 0:85b3fd62ea1a 1407 macconf->ZeroQuantaPause |
NYX 0:85b3fd62ea1a 1408 macconf->PauseLowThreshold |
NYX 0:85b3fd62ea1a 1409 macconf->UnicastPauseFrameDetect |
NYX 0:85b3fd62ea1a 1410 macconf->ReceiveFlowControl |
NYX 0:85b3fd62ea1a 1411 macconf->TransmitFlowControl);
NYX 0:85b3fd62ea1a 1412
NYX 0:85b3fd62ea1a 1413 /* Write to ETHERNET MACFCR */
NYX 0:85b3fd62ea1a 1414 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
NYX 0:85b3fd62ea1a 1415
NYX 0:85b3fd62ea1a 1416 /* Wait until the write operation will be taken into account :
NYX 0:85b3fd62ea1a 1417 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1418 tmpreg1 = (heth->Instance)->MACFCR;
NYX 0:85b3fd62ea1a 1419 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1420 (heth->Instance)->MACFCR = tmpreg1;
NYX 0:85b3fd62ea1a 1421
NYX 0:85b3fd62ea1a 1422 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
NYX 0:85b3fd62ea1a 1423 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
NYX 0:85b3fd62ea1a 1424 macconf->VLANTagIdentifier);
NYX 0:85b3fd62ea1a 1425
NYX 0:85b3fd62ea1a 1426 /* Wait until the write operation will be taken into account :
NYX 0:85b3fd62ea1a 1427 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1428 tmpreg1 = (heth->Instance)->MACVLANTR;
NYX 0:85b3fd62ea1a 1429 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1430 (heth->Instance)->MACVLANTR = tmpreg1;
NYX 0:85b3fd62ea1a 1431 }
NYX 0:85b3fd62ea1a 1432 else /* macconf == NULL : here we just configure Speed and Duplex mode */
NYX 0:85b3fd62ea1a 1433 {
NYX 0:85b3fd62ea1a 1434 /*------------------------ ETHERNET MACCR Configuration --------------------*/
NYX 0:85b3fd62ea1a 1435 /* Get the ETHERNET MACCR value */
NYX 0:85b3fd62ea1a 1436 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1437
NYX 0:85b3fd62ea1a 1438 /* Clear FES and DM bits */
NYX 0:85b3fd62ea1a 1439 tmpreg1 &= ~(0x00004800U);
NYX 0:85b3fd62ea1a 1440
NYX 0:85b3fd62ea1a 1441 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
NYX 0:85b3fd62ea1a 1442
NYX 0:85b3fd62ea1a 1443 /* Write to ETHERNET MACCR */
NYX 0:85b3fd62ea1a 1444 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
NYX 0:85b3fd62ea1a 1445
NYX 0:85b3fd62ea1a 1446 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1447 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1448 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1449 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1450 (heth->Instance)->MACCR = tmpreg1;
NYX 0:85b3fd62ea1a 1451 }
NYX 0:85b3fd62ea1a 1452
NYX 0:85b3fd62ea1a 1453 /* Set the ETH state to Ready */
NYX 0:85b3fd62ea1a 1454 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 1455
NYX 0:85b3fd62ea1a 1456 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1457 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 1458
NYX 0:85b3fd62ea1a 1459 /* Return function status */
NYX 0:85b3fd62ea1a 1460 return HAL_OK;
NYX 0:85b3fd62ea1a 1461 }
NYX 0:85b3fd62ea1a 1462
NYX 0:85b3fd62ea1a 1463 /**
NYX 0:85b3fd62ea1a 1464 * @brief Sets ETH DMA Configuration.
NYX 0:85b3fd62ea1a 1465 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1466 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1467 * @param dmaconf: DMA Configuration structure
NYX 0:85b3fd62ea1a 1468 * @retval HAL status
NYX 0:85b3fd62ea1a 1469 */
NYX 0:85b3fd62ea1a 1470 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
NYX 0:85b3fd62ea1a 1471 {
NYX 0:85b3fd62ea1a 1472 uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 1473
NYX 0:85b3fd62ea1a 1474 /* Process Locked */
NYX 0:85b3fd62ea1a 1475 __HAL_LOCK(heth);
NYX 0:85b3fd62ea1a 1476
NYX 0:85b3fd62ea1a 1477 /* Set the ETH peripheral state to BUSY */
NYX 0:85b3fd62ea1a 1478 heth->State= HAL_ETH_STATE_BUSY;
NYX 0:85b3fd62ea1a 1479
NYX 0:85b3fd62ea1a 1480 /* Check parameters */
NYX 0:85b3fd62ea1a 1481 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
NYX 0:85b3fd62ea1a 1482 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
NYX 0:85b3fd62ea1a 1483 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
NYX 0:85b3fd62ea1a 1484 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
NYX 0:85b3fd62ea1a 1485 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
NYX 0:85b3fd62ea1a 1486 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
NYX 0:85b3fd62ea1a 1487 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
NYX 0:85b3fd62ea1a 1488 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
NYX 0:85b3fd62ea1a 1489 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
NYX 0:85b3fd62ea1a 1490 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
NYX 0:85b3fd62ea1a 1491 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
NYX 0:85b3fd62ea1a 1492 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
NYX 0:85b3fd62ea1a 1493 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
NYX 0:85b3fd62ea1a 1494 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
NYX 0:85b3fd62ea1a 1495 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
NYX 0:85b3fd62ea1a 1496 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
NYX 0:85b3fd62ea1a 1497
NYX 0:85b3fd62ea1a 1498 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
NYX 0:85b3fd62ea1a 1499 /* Get the ETHERNET DMAOMR value */
NYX 0:85b3fd62ea1a 1500 tmpreg1 = (heth->Instance)->DMAOMR;
NYX 0:85b3fd62ea1a 1501 /* Clear xx bits */
NYX 0:85b3fd62ea1a 1502 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
NYX 0:85b3fd62ea1a 1503
NYX 0:85b3fd62ea1a 1504 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
NYX 0:85b3fd62ea1a 1505 dmaconf->ReceiveStoreForward |
NYX 0:85b3fd62ea1a 1506 dmaconf->FlushReceivedFrame |
NYX 0:85b3fd62ea1a 1507 dmaconf->TransmitStoreForward |
NYX 0:85b3fd62ea1a 1508 dmaconf->TransmitThresholdControl |
NYX 0:85b3fd62ea1a 1509 dmaconf->ForwardErrorFrames |
NYX 0:85b3fd62ea1a 1510 dmaconf->ForwardUndersizedGoodFrames |
NYX 0:85b3fd62ea1a 1511 dmaconf->ReceiveThresholdControl |
NYX 0:85b3fd62ea1a 1512 dmaconf->SecondFrameOperate);
NYX 0:85b3fd62ea1a 1513
NYX 0:85b3fd62ea1a 1514 /* Write to ETHERNET DMAOMR */
NYX 0:85b3fd62ea1a 1515 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
NYX 0:85b3fd62ea1a 1516
NYX 0:85b3fd62ea1a 1517 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1518 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1519 tmpreg1 = (heth->Instance)->DMAOMR;
NYX 0:85b3fd62ea1a 1520 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1521 (heth->Instance)->DMAOMR = tmpreg1;
NYX 0:85b3fd62ea1a 1522
NYX 0:85b3fd62ea1a 1523 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
NYX 0:85b3fd62ea1a 1524 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
NYX 0:85b3fd62ea1a 1525 dmaconf->FixedBurst |
NYX 0:85b3fd62ea1a 1526 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
NYX 0:85b3fd62ea1a 1527 dmaconf->TxDMABurstLength |
NYX 0:85b3fd62ea1a 1528 dmaconf->EnhancedDescriptorFormat |
NYX 0:85b3fd62ea1a 1529 (dmaconf->DescriptorSkipLength << 2U) |
NYX 0:85b3fd62ea1a 1530 dmaconf->DMAArbitration |
NYX 0:85b3fd62ea1a 1531 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
NYX 0:85b3fd62ea1a 1532
NYX 0:85b3fd62ea1a 1533 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1534 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1535 tmpreg1 = (heth->Instance)->DMABMR;
NYX 0:85b3fd62ea1a 1536 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1537 (heth->Instance)->DMABMR = tmpreg1;
NYX 0:85b3fd62ea1a 1538
NYX 0:85b3fd62ea1a 1539 /* Set the ETH state to Ready */
NYX 0:85b3fd62ea1a 1540 heth->State= HAL_ETH_STATE_READY;
NYX 0:85b3fd62ea1a 1541
NYX 0:85b3fd62ea1a 1542 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1543 __HAL_UNLOCK(heth);
NYX 0:85b3fd62ea1a 1544
NYX 0:85b3fd62ea1a 1545 /* Return function status */
NYX 0:85b3fd62ea1a 1546 return HAL_OK;
NYX 0:85b3fd62ea1a 1547 }
NYX 0:85b3fd62ea1a 1548
NYX 0:85b3fd62ea1a 1549 /**
NYX 0:85b3fd62ea1a 1550 * @}
NYX 0:85b3fd62ea1a 1551 */
NYX 0:85b3fd62ea1a 1552
NYX 0:85b3fd62ea1a 1553 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
NYX 0:85b3fd62ea1a 1554 * @brief Peripheral State functions
NYX 0:85b3fd62ea1a 1555 *
NYX 0:85b3fd62ea1a 1556 @verbatim
NYX 0:85b3fd62ea1a 1557 ===============================================================================
NYX 0:85b3fd62ea1a 1558 ##### Peripheral State functions #####
NYX 0:85b3fd62ea1a 1559 ===============================================================================
NYX 0:85b3fd62ea1a 1560 [..]
NYX 0:85b3fd62ea1a 1561 This subsection permits to get in run-time the status of the peripheral
NYX 0:85b3fd62ea1a 1562 and the data flow.
NYX 0:85b3fd62ea1a 1563 (+) Get the ETH handle state:
NYX 0:85b3fd62ea1a 1564 HAL_ETH_GetState();
NYX 0:85b3fd62ea1a 1565
NYX 0:85b3fd62ea1a 1566
NYX 0:85b3fd62ea1a 1567 @endverbatim
NYX 0:85b3fd62ea1a 1568 * @{
NYX 0:85b3fd62ea1a 1569 */
NYX 0:85b3fd62ea1a 1570
NYX 0:85b3fd62ea1a 1571 /**
NYX 0:85b3fd62ea1a 1572 * @brief Return the ETH HAL state
NYX 0:85b3fd62ea1a 1573 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1574 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1575 * @retval HAL state
NYX 0:85b3fd62ea1a 1576 */
NYX 0:85b3fd62ea1a 1577 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1578 {
NYX 0:85b3fd62ea1a 1579 /* Return ETH state */
NYX 0:85b3fd62ea1a 1580 return heth->State;
NYX 0:85b3fd62ea1a 1581 }
NYX 0:85b3fd62ea1a 1582
NYX 0:85b3fd62ea1a 1583 /**
NYX 0:85b3fd62ea1a 1584 * @}
NYX 0:85b3fd62ea1a 1585 */
NYX 0:85b3fd62ea1a 1586
NYX 0:85b3fd62ea1a 1587 /**
NYX 0:85b3fd62ea1a 1588 * @}
NYX 0:85b3fd62ea1a 1589 */
NYX 0:85b3fd62ea1a 1590
NYX 0:85b3fd62ea1a 1591 /** @addtogroup ETH_Private_Functions
NYX 0:85b3fd62ea1a 1592 * @{
NYX 0:85b3fd62ea1a 1593 */
NYX 0:85b3fd62ea1a 1594
NYX 0:85b3fd62ea1a 1595 /**
NYX 0:85b3fd62ea1a 1596 * @brief Configures Ethernet MAC and DMA with default parameters.
NYX 0:85b3fd62ea1a 1597 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1598 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1599 * @param err: Ethernet Init error
NYX 0:85b3fd62ea1a 1600 * @retval HAL status
NYX 0:85b3fd62ea1a 1601 */
NYX 0:85b3fd62ea1a 1602 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
NYX 0:85b3fd62ea1a 1603 {
NYX 0:85b3fd62ea1a 1604 ETH_MACInitTypeDef macinit;
NYX 0:85b3fd62ea1a 1605 ETH_DMAInitTypeDef dmainit;
NYX 0:85b3fd62ea1a 1606 uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 1607
NYX 0:85b3fd62ea1a 1608 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
NYX 0:85b3fd62ea1a 1609 {
NYX 0:85b3fd62ea1a 1610 /* Set Ethernet duplex mode to Full-duplex */
NYX 0:85b3fd62ea1a 1611 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
NYX 0:85b3fd62ea1a 1612
NYX 0:85b3fd62ea1a 1613 /* Set Ethernet speed to 100M */
NYX 0:85b3fd62ea1a 1614 (heth->Init).Speed = ETH_SPEED_100M;
NYX 0:85b3fd62ea1a 1615 }
NYX 0:85b3fd62ea1a 1616
NYX 0:85b3fd62ea1a 1617 /* Ethernet MAC default initialization **************************************/
NYX 0:85b3fd62ea1a 1618 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
NYX 0:85b3fd62ea1a 1619 macinit.Jabber = ETH_JABBER_ENABLE;
NYX 0:85b3fd62ea1a 1620 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
NYX 0:85b3fd62ea1a 1621 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
NYX 0:85b3fd62ea1a 1622 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
NYX 0:85b3fd62ea1a 1623 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
NYX 0:85b3fd62ea1a 1624 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
NYX 0:85b3fd62ea1a 1625 {
NYX 0:85b3fd62ea1a 1626 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
NYX 0:85b3fd62ea1a 1627 }
NYX 0:85b3fd62ea1a 1628 else
NYX 0:85b3fd62ea1a 1629 {
NYX 0:85b3fd62ea1a 1630 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
NYX 0:85b3fd62ea1a 1631 }
NYX 0:85b3fd62ea1a 1632 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
NYX 0:85b3fd62ea1a 1633 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
NYX 0:85b3fd62ea1a 1634 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
NYX 0:85b3fd62ea1a 1635 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
NYX 0:85b3fd62ea1a 1636 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
NYX 0:85b3fd62ea1a 1637 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
NYX 0:85b3fd62ea1a 1638 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
NYX 0:85b3fd62ea1a 1639 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
NYX 0:85b3fd62ea1a 1640 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
NYX 0:85b3fd62ea1a 1641 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
NYX 0:85b3fd62ea1a 1642 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
NYX 0:85b3fd62ea1a 1643 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
NYX 0:85b3fd62ea1a 1644 macinit.HashTableHigh = 0x0U;
NYX 0:85b3fd62ea1a 1645 macinit.HashTableLow = 0x0U;
NYX 0:85b3fd62ea1a 1646 macinit.PauseTime = 0x0U;
NYX 0:85b3fd62ea1a 1647 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
NYX 0:85b3fd62ea1a 1648 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
NYX 0:85b3fd62ea1a 1649 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
NYX 0:85b3fd62ea1a 1650 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
NYX 0:85b3fd62ea1a 1651 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
NYX 0:85b3fd62ea1a 1652 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
NYX 0:85b3fd62ea1a 1653 macinit.VLANTagIdentifier = 0x0U;
NYX 0:85b3fd62ea1a 1654
NYX 0:85b3fd62ea1a 1655 /*------------------------ ETHERNET MACCR Configuration --------------------*/
NYX 0:85b3fd62ea1a 1656 /* Get the ETHERNET MACCR value */
NYX 0:85b3fd62ea1a 1657 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1658 /* Clear WD, PCE, PS, TE and RE bits */
NYX 0:85b3fd62ea1a 1659 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
NYX 0:85b3fd62ea1a 1660 /* Set the WD bit according to ETH Watchdog value */
NYX 0:85b3fd62ea1a 1661 /* Set the JD: bit according to ETH Jabber value */
NYX 0:85b3fd62ea1a 1662 /* Set the IFG bit according to ETH InterFrameGap value */
NYX 0:85b3fd62ea1a 1663 /* Set the DCRS bit according to ETH CarrierSense value */
NYX 0:85b3fd62ea1a 1664 /* Set the FES bit according to ETH Speed value */
NYX 0:85b3fd62ea1a 1665 /* Set the DO bit according to ETH ReceiveOwn value */
NYX 0:85b3fd62ea1a 1666 /* Set the LM bit according to ETH LoopbackMode value */
NYX 0:85b3fd62ea1a 1667 /* Set the DM bit according to ETH Mode value */
NYX 0:85b3fd62ea1a 1668 /* Set the IPCO bit according to ETH ChecksumOffload value */
NYX 0:85b3fd62ea1a 1669 /* Set the DR bit according to ETH RetryTransmission value */
NYX 0:85b3fd62ea1a 1670 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
NYX 0:85b3fd62ea1a 1671 /* Set the BL bit according to ETH BackOffLimit value */
NYX 0:85b3fd62ea1a 1672 /* Set the DC bit according to ETH DeferralCheck value */
NYX 0:85b3fd62ea1a 1673 tmpreg1 |= (uint32_t)(macinit.Watchdog |
NYX 0:85b3fd62ea1a 1674 macinit.Jabber |
NYX 0:85b3fd62ea1a 1675 macinit.InterFrameGap |
NYX 0:85b3fd62ea1a 1676 macinit.CarrierSense |
NYX 0:85b3fd62ea1a 1677 (heth->Init).Speed |
NYX 0:85b3fd62ea1a 1678 macinit.ReceiveOwn |
NYX 0:85b3fd62ea1a 1679 macinit.LoopbackMode |
NYX 0:85b3fd62ea1a 1680 (heth->Init).DuplexMode |
NYX 0:85b3fd62ea1a 1681 macinit.ChecksumOffload |
NYX 0:85b3fd62ea1a 1682 macinit.RetryTransmission |
NYX 0:85b3fd62ea1a 1683 macinit.AutomaticPadCRCStrip |
NYX 0:85b3fd62ea1a 1684 macinit.BackOffLimit |
NYX 0:85b3fd62ea1a 1685 macinit.DeferralCheck);
NYX 0:85b3fd62ea1a 1686
NYX 0:85b3fd62ea1a 1687 /* Write to ETHERNET MACCR */
NYX 0:85b3fd62ea1a 1688 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
NYX 0:85b3fd62ea1a 1689
NYX 0:85b3fd62ea1a 1690 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1691 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1692 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1693 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1694 (heth->Instance)->MACCR = tmpreg1;
NYX 0:85b3fd62ea1a 1695
NYX 0:85b3fd62ea1a 1696 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
NYX 0:85b3fd62ea1a 1697 /* Set the RA bit according to ETH ReceiveAll value */
NYX 0:85b3fd62ea1a 1698 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
NYX 0:85b3fd62ea1a 1699 /* Set the PCF bit according to ETH PassControlFrames value */
NYX 0:85b3fd62ea1a 1700 /* Set the DBF bit according to ETH BroadcastFramesReception value */
NYX 0:85b3fd62ea1a 1701 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
NYX 0:85b3fd62ea1a 1702 /* Set the PR bit according to ETH PromiscuousMode value */
NYX 0:85b3fd62ea1a 1703 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
NYX 0:85b3fd62ea1a 1704 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
NYX 0:85b3fd62ea1a 1705 /* Write to ETHERNET MACFFR */
NYX 0:85b3fd62ea1a 1706 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
NYX 0:85b3fd62ea1a 1707 macinit.SourceAddrFilter |
NYX 0:85b3fd62ea1a 1708 macinit.PassControlFrames |
NYX 0:85b3fd62ea1a 1709 macinit.BroadcastFramesReception |
NYX 0:85b3fd62ea1a 1710 macinit.DestinationAddrFilter |
NYX 0:85b3fd62ea1a 1711 macinit.PromiscuousMode |
NYX 0:85b3fd62ea1a 1712 macinit.MulticastFramesFilter |
NYX 0:85b3fd62ea1a 1713 macinit.UnicastFramesFilter);
NYX 0:85b3fd62ea1a 1714
NYX 0:85b3fd62ea1a 1715 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1716 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1717 tmpreg1 = (heth->Instance)->MACFFR;
NYX 0:85b3fd62ea1a 1718 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1719 (heth->Instance)->MACFFR = tmpreg1;
NYX 0:85b3fd62ea1a 1720
NYX 0:85b3fd62ea1a 1721 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
NYX 0:85b3fd62ea1a 1722 /* Write to ETHERNET MACHTHR */
NYX 0:85b3fd62ea1a 1723 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
NYX 0:85b3fd62ea1a 1724
NYX 0:85b3fd62ea1a 1725 /* Write to ETHERNET MACHTLR */
NYX 0:85b3fd62ea1a 1726 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
NYX 0:85b3fd62ea1a 1727 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
NYX 0:85b3fd62ea1a 1728
NYX 0:85b3fd62ea1a 1729 /* Get the ETHERNET MACFCR value */
NYX 0:85b3fd62ea1a 1730 tmpreg1 = (heth->Instance)->MACFCR;
NYX 0:85b3fd62ea1a 1731 /* Clear xx bits */
NYX 0:85b3fd62ea1a 1732 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
NYX 0:85b3fd62ea1a 1733
NYX 0:85b3fd62ea1a 1734 /* Set the PT bit according to ETH PauseTime value */
NYX 0:85b3fd62ea1a 1735 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
NYX 0:85b3fd62ea1a 1736 /* Set the PLT bit according to ETH PauseLowThreshold value */
NYX 0:85b3fd62ea1a 1737 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
NYX 0:85b3fd62ea1a 1738 /* Set the RFE bit according to ETH ReceiveFlowControl value */
NYX 0:85b3fd62ea1a 1739 /* Set the TFE bit according to ETH TransmitFlowControl value */
NYX 0:85b3fd62ea1a 1740 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
NYX 0:85b3fd62ea1a 1741 macinit.ZeroQuantaPause |
NYX 0:85b3fd62ea1a 1742 macinit.PauseLowThreshold |
NYX 0:85b3fd62ea1a 1743 macinit.UnicastPauseFrameDetect |
NYX 0:85b3fd62ea1a 1744 macinit.ReceiveFlowControl |
NYX 0:85b3fd62ea1a 1745 macinit.TransmitFlowControl);
NYX 0:85b3fd62ea1a 1746
NYX 0:85b3fd62ea1a 1747 /* Write to ETHERNET MACFCR */
NYX 0:85b3fd62ea1a 1748 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
NYX 0:85b3fd62ea1a 1749
NYX 0:85b3fd62ea1a 1750 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1751 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1752 tmpreg1 = (heth->Instance)->MACFCR;
NYX 0:85b3fd62ea1a 1753 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1754 (heth->Instance)->MACFCR = tmpreg1;
NYX 0:85b3fd62ea1a 1755
NYX 0:85b3fd62ea1a 1756 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
NYX 0:85b3fd62ea1a 1757 /* Set the ETV bit according to ETH VLANTagComparison value */
NYX 0:85b3fd62ea1a 1758 /* Set the VL bit according to ETH VLANTagIdentifier value */
NYX 0:85b3fd62ea1a 1759 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
NYX 0:85b3fd62ea1a 1760 macinit.VLANTagIdentifier);
NYX 0:85b3fd62ea1a 1761
NYX 0:85b3fd62ea1a 1762 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1763 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1764 tmpreg1 = (heth->Instance)->MACVLANTR;
NYX 0:85b3fd62ea1a 1765 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1766 (heth->Instance)->MACVLANTR = tmpreg1;
NYX 0:85b3fd62ea1a 1767
NYX 0:85b3fd62ea1a 1768 /* Ethernet DMA default initialization ************************************/
NYX 0:85b3fd62ea1a 1769 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
NYX 0:85b3fd62ea1a 1770 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
NYX 0:85b3fd62ea1a 1771 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
NYX 0:85b3fd62ea1a 1772 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
NYX 0:85b3fd62ea1a 1773 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
NYX 0:85b3fd62ea1a 1774 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
NYX 0:85b3fd62ea1a 1775 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
NYX 0:85b3fd62ea1a 1776 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
NYX 0:85b3fd62ea1a 1777 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
NYX 0:85b3fd62ea1a 1778 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
NYX 0:85b3fd62ea1a 1779 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
NYX 0:85b3fd62ea1a 1780 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
NYX 0:85b3fd62ea1a 1781 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
NYX 0:85b3fd62ea1a 1782 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
NYX 0:85b3fd62ea1a 1783 dmainit.DescriptorSkipLength = 0x0U;
NYX 0:85b3fd62ea1a 1784 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
NYX 0:85b3fd62ea1a 1785
NYX 0:85b3fd62ea1a 1786 /* Get the ETHERNET DMAOMR value */
NYX 0:85b3fd62ea1a 1787 tmpreg1 = (heth->Instance)->DMAOMR;
NYX 0:85b3fd62ea1a 1788 /* Clear xx bits */
NYX 0:85b3fd62ea1a 1789 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
NYX 0:85b3fd62ea1a 1790
NYX 0:85b3fd62ea1a 1791 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
NYX 0:85b3fd62ea1a 1792 /* Set the RSF bit according to ETH ReceiveStoreForward value */
NYX 0:85b3fd62ea1a 1793 /* Set the DFF bit according to ETH FlushReceivedFrame value */
NYX 0:85b3fd62ea1a 1794 /* Set the TSF bit according to ETH TransmitStoreForward value */
NYX 0:85b3fd62ea1a 1795 /* Set the TTC bit according to ETH TransmitThresholdControl value */
NYX 0:85b3fd62ea1a 1796 /* Set the FEF bit according to ETH ForwardErrorFrames value */
NYX 0:85b3fd62ea1a 1797 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
NYX 0:85b3fd62ea1a 1798 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
NYX 0:85b3fd62ea1a 1799 /* Set the OSF bit according to ETH SecondFrameOperate value */
NYX 0:85b3fd62ea1a 1800 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
NYX 0:85b3fd62ea1a 1801 dmainit.ReceiveStoreForward |
NYX 0:85b3fd62ea1a 1802 dmainit.FlushReceivedFrame |
NYX 0:85b3fd62ea1a 1803 dmainit.TransmitStoreForward |
NYX 0:85b3fd62ea1a 1804 dmainit.TransmitThresholdControl |
NYX 0:85b3fd62ea1a 1805 dmainit.ForwardErrorFrames |
NYX 0:85b3fd62ea1a 1806 dmainit.ForwardUndersizedGoodFrames |
NYX 0:85b3fd62ea1a 1807 dmainit.ReceiveThresholdControl |
NYX 0:85b3fd62ea1a 1808 dmainit.SecondFrameOperate);
NYX 0:85b3fd62ea1a 1809
NYX 0:85b3fd62ea1a 1810 /* Write to ETHERNET DMAOMR */
NYX 0:85b3fd62ea1a 1811 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
NYX 0:85b3fd62ea1a 1812
NYX 0:85b3fd62ea1a 1813 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1814 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1815 tmpreg1 = (heth->Instance)->DMAOMR;
NYX 0:85b3fd62ea1a 1816 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1817 (heth->Instance)->DMAOMR = tmpreg1;
NYX 0:85b3fd62ea1a 1818
NYX 0:85b3fd62ea1a 1819 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
NYX 0:85b3fd62ea1a 1820 /* Set the AAL bit according to ETH AddressAlignedBeats value */
NYX 0:85b3fd62ea1a 1821 /* Set the FB bit according to ETH FixedBurst value */
NYX 0:85b3fd62ea1a 1822 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
NYX 0:85b3fd62ea1a 1823 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
NYX 0:85b3fd62ea1a 1824 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
NYX 0:85b3fd62ea1a 1825 /* Set the DSL bit according to ETH DesciptorSkipLength value */
NYX 0:85b3fd62ea1a 1826 /* Set the PR and DA bits according to ETH DMAArbitration value */
NYX 0:85b3fd62ea1a 1827 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
NYX 0:85b3fd62ea1a 1828 dmainit.FixedBurst |
NYX 0:85b3fd62ea1a 1829 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
NYX 0:85b3fd62ea1a 1830 dmainit.TxDMABurstLength |
NYX 0:85b3fd62ea1a 1831 dmainit.EnhancedDescriptorFormat |
NYX 0:85b3fd62ea1a 1832 (dmainit.DescriptorSkipLength << 2U) |
NYX 0:85b3fd62ea1a 1833 dmainit.DMAArbitration |
NYX 0:85b3fd62ea1a 1834 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
NYX 0:85b3fd62ea1a 1835
NYX 0:85b3fd62ea1a 1836 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1837 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1838 tmpreg1 = (heth->Instance)->DMABMR;
NYX 0:85b3fd62ea1a 1839 HAL_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1840 (heth->Instance)->DMABMR = tmpreg1;
NYX 0:85b3fd62ea1a 1841
NYX 0:85b3fd62ea1a 1842 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
NYX 0:85b3fd62ea1a 1843 {
NYX 0:85b3fd62ea1a 1844 /* Enable the Ethernet Rx Interrupt */
NYX 0:85b3fd62ea1a 1845 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
NYX 0:85b3fd62ea1a 1846 }
NYX 0:85b3fd62ea1a 1847
NYX 0:85b3fd62ea1a 1848 /* Initialize MAC address in ethernet MAC */
NYX 0:85b3fd62ea1a 1849 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
NYX 0:85b3fd62ea1a 1850 }
NYX 0:85b3fd62ea1a 1851
NYX 0:85b3fd62ea1a 1852 /**
NYX 0:85b3fd62ea1a 1853 * @brief Configures the selected MAC address.
NYX 0:85b3fd62ea1a 1854 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1855 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1856 * @param MacAddr: The MAC address to configure
NYX 0:85b3fd62ea1a 1857 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1858 * @arg ETH_MAC_Address0: MAC Address0
NYX 0:85b3fd62ea1a 1859 * @arg ETH_MAC_Address1: MAC Address1
NYX 0:85b3fd62ea1a 1860 * @arg ETH_MAC_Address2: MAC Address2
NYX 0:85b3fd62ea1a 1861 * @arg ETH_MAC_Address3: MAC Address3
NYX 0:85b3fd62ea1a 1862 * @param Addr: Pointer to MAC address buffer data (6 bytes)
NYX 0:85b3fd62ea1a 1863 * @retval HAL status
NYX 0:85b3fd62ea1a 1864 */
NYX 0:85b3fd62ea1a 1865 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
NYX 0:85b3fd62ea1a 1866 {
NYX 0:85b3fd62ea1a 1867 uint32_t tmpreg1;
NYX 0:85b3fd62ea1a 1868
NYX 0:85b3fd62ea1a 1869 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1870 UNUSED(heth);
NYX 0:85b3fd62ea1a 1871
NYX 0:85b3fd62ea1a 1872 /* Check the parameters */
NYX 0:85b3fd62ea1a 1873 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
NYX 0:85b3fd62ea1a 1874
NYX 0:85b3fd62ea1a 1875 /* Calculate the selected MAC address high register */
NYX 0:85b3fd62ea1a 1876 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
NYX 0:85b3fd62ea1a 1877 /* Load the selected MAC address high register */
NYX 0:85b3fd62ea1a 1878 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
NYX 0:85b3fd62ea1a 1879 /* Calculate the selected MAC address low register */
NYX 0:85b3fd62ea1a 1880 tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
NYX 0:85b3fd62ea1a 1881
NYX 0:85b3fd62ea1a 1882 /* Load the selected MAC address low register */
NYX 0:85b3fd62ea1a 1883 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
NYX 0:85b3fd62ea1a 1884 }
NYX 0:85b3fd62ea1a 1885
NYX 0:85b3fd62ea1a 1886 /**
NYX 0:85b3fd62ea1a 1887 * @brief Enables the MAC transmission.
NYX 0:85b3fd62ea1a 1888 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1889 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1890 * @retval None
NYX 0:85b3fd62ea1a 1891 */
NYX 0:85b3fd62ea1a 1892 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1893 {
NYX 0:85b3fd62ea1a 1894 __IO uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 1895
NYX 0:85b3fd62ea1a 1896 /* Enable the MAC transmission */
NYX 0:85b3fd62ea1a 1897 (heth->Instance)->MACCR |= ETH_MACCR_TE;
NYX 0:85b3fd62ea1a 1898
NYX 0:85b3fd62ea1a 1899 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1900 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1901 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1902 ETH_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1903 (heth->Instance)->MACCR = tmpreg1;
NYX 0:85b3fd62ea1a 1904 }
NYX 0:85b3fd62ea1a 1905
NYX 0:85b3fd62ea1a 1906 /**
NYX 0:85b3fd62ea1a 1907 * @brief Disables the MAC transmission.
NYX 0:85b3fd62ea1a 1908 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1909 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1910 * @retval None
NYX 0:85b3fd62ea1a 1911 */
NYX 0:85b3fd62ea1a 1912 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1913 {
NYX 0:85b3fd62ea1a 1914 __IO uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 1915
NYX 0:85b3fd62ea1a 1916 /* Disable the MAC transmission */
NYX 0:85b3fd62ea1a 1917 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
NYX 0:85b3fd62ea1a 1918
NYX 0:85b3fd62ea1a 1919 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1920 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1921 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1922 ETH_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1923 (heth->Instance)->MACCR = tmpreg1;
NYX 0:85b3fd62ea1a 1924 }
NYX 0:85b3fd62ea1a 1925
NYX 0:85b3fd62ea1a 1926 /**
NYX 0:85b3fd62ea1a 1927 * @brief Enables the MAC reception.
NYX 0:85b3fd62ea1a 1928 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1929 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1930 * @retval None
NYX 0:85b3fd62ea1a 1931 */
NYX 0:85b3fd62ea1a 1932 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1933 {
NYX 0:85b3fd62ea1a 1934 __IO uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 1935
NYX 0:85b3fd62ea1a 1936 /* Enable the MAC reception */
NYX 0:85b3fd62ea1a 1937 (heth->Instance)->MACCR |= ETH_MACCR_RE;
NYX 0:85b3fd62ea1a 1938
NYX 0:85b3fd62ea1a 1939 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1940 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1941 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1942 ETH_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1943 (heth->Instance)->MACCR = tmpreg1;
NYX 0:85b3fd62ea1a 1944 }
NYX 0:85b3fd62ea1a 1945
NYX 0:85b3fd62ea1a 1946 /**
NYX 0:85b3fd62ea1a 1947 * @brief Disables the MAC reception.
NYX 0:85b3fd62ea1a 1948 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1949 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1950 * @retval None
NYX 0:85b3fd62ea1a 1951 */
NYX 0:85b3fd62ea1a 1952 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1953 {
NYX 0:85b3fd62ea1a 1954 __IO uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 1955
NYX 0:85b3fd62ea1a 1956 /* Disable the MAC reception */
NYX 0:85b3fd62ea1a 1957 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
NYX 0:85b3fd62ea1a 1958
NYX 0:85b3fd62ea1a 1959 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 1960 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 1961 tmpreg1 = (heth->Instance)->MACCR;
NYX 0:85b3fd62ea1a 1962 ETH_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 1963 (heth->Instance)->MACCR = tmpreg1;
NYX 0:85b3fd62ea1a 1964 }
NYX 0:85b3fd62ea1a 1965
NYX 0:85b3fd62ea1a 1966 /**
NYX 0:85b3fd62ea1a 1967 * @brief Enables the DMA transmission.
NYX 0:85b3fd62ea1a 1968 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1969 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1970 * @retval None
NYX 0:85b3fd62ea1a 1971 */
NYX 0:85b3fd62ea1a 1972 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1973 {
NYX 0:85b3fd62ea1a 1974 /* Enable the DMA transmission */
NYX 0:85b3fd62ea1a 1975 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
NYX 0:85b3fd62ea1a 1976 }
NYX 0:85b3fd62ea1a 1977
NYX 0:85b3fd62ea1a 1978 /**
NYX 0:85b3fd62ea1a 1979 * @brief Disables the DMA transmission.
NYX 0:85b3fd62ea1a 1980 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1981 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1982 * @retval None
NYX 0:85b3fd62ea1a 1983 */
NYX 0:85b3fd62ea1a 1984 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1985 {
NYX 0:85b3fd62ea1a 1986 /* Disable the DMA transmission */
NYX 0:85b3fd62ea1a 1987 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
NYX 0:85b3fd62ea1a 1988 }
NYX 0:85b3fd62ea1a 1989
NYX 0:85b3fd62ea1a 1990 /**
NYX 0:85b3fd62ea1a 1991 * @brief Enables the DMA reception.
NYX 0:85b3fd62ea1a 1992 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1993 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 1994 * @retval None
NYX 0:85b3fd62ea1a 1995 */
NYX 0:85b3fd62ea1a 1996 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 1997 {
NYX 0:85b3fd62ea1a 1998 /* Enable the DMA reception */
NYX 0:85b3fd62ea1a 1999 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
NYX 0:85b3fd62ea1a 2000 }
NYX 0:85b3fd62ea1a 2001
NYX 0:85b3fd62ea1a 2002 /**
NYX 0:85b3fd62ea1a 2003 * @brief Disables the DMA reception.
NYX 0:85b3fd62ea1a 2004 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2005 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 2006 * @retval None
NYX 0:85b3fd62ea1a 2007 */
NYX 0:85b3fd62ea1a 2008 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 2009 {
NYX 0:85b3fd62ea1a 2010 /* Disable the DMA reception */
NYX 0:85b3fd62ea1a 2011 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
NYX 0:85b3fd62ea1a 2012 }
NYX 0:85b3fd62ea1a 2013
NYX 0:85b3fd62ea1a 2014 /**
NYX 0:85b3fd62ea1a 2015 * @brief Clears the ETHERNET transmit FIFO.
NYX 0:85b3fd62ea1a 2016 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2017 * the configuration information for ETHERNET module
NYX 0:85b3fd62ea1a 2018 * @retval None
NYX 0:85b3fd62ea1a 2019 */
NYX 0:85b3fd62ea1a 2020 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
NYX 0:85b3fd62ea1a 2021 {
NYX 0:85b3fd62ea1a 2022 __IO uint32_t tmpreg1 = 0U;
NYX 0:85b3fd62ea1a 2023
NYX 0:85b3fd62ea1a 2024 /* Set the Flush Transmit FIFO bit */
NYX 0:85b3fd62ea1a 2025 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
NYX 0:85b3fd62ea1a 2026
NYX 0:85b3fd62ea1a 2027 /* Wait until the write operation will be taken into account:
NYX 0:85b3fd62ea1a 2028 at least four TX_CLK/RX_CLK clock cycles */
NYX 0:85b3fd62ea1a 2029 tmpreg1 = (heth->Instance)->DMAOMR;
NYX 0:85b3fd62ea1a 2030 ETH_Delay(ETH_REG_WRITE_DELAY);
NYX 0:85b3fd62ea1a 2031 (heth->Instance)->DMAOMR = tmpreg1;
NYX 0:85b3fd62ea1a 2032 }
NYX 0:85b3fd62ea1a 2033
NYX 0:85b3fd62ea1a 2034 /**
NYX 0:85b3fd62ea1a 2035 * @brief This function provides delay (in milliseconds) based on CPU cycles method.
NYX 0:85b3fd62ea1a 2036 * @param mdelay: specifies the delay time length, in milliseconds.
NYX 0:85b3fd62ea1a 2037 * @retval None
NYX 0:85b3fd62ea1a 2038 */
NYX 0:85b3fd62ea1a 2039 static void ETH_Delay(uint32_t mdelay)
NYX 0:85b3fd62ea1a 2040 {
NYX 0:85b3fd62ea1a 2041 __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
NYX 0:85b3fd62ea1a 2042 do
NYX 0:85b3fd62ea1a 2043 {
NYX 0:85b3fd62ea1a 2044 __NOP();
NYX 0:85b3fd62ea1a 2045 }
NYX 0:85b3fd62ea1a 2046 while (Delay --);
NYX 0:85b3fd62ea1a 2047 }
NYX 0:85b3fd62ea1a 2048
NYX 0:85b3fd62ea1a 2049 /**
NYX 0:85b3fd62ea1a 2050 * @}
NYX 0:85b3fd62ea1a 2051 */
NYX 0:85b3fd62ea1a 2052
NYX 0:85b3fd62ea1a 2053 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
NYX 0:85b3fd62ea1a 2054 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
NYX 0:85b3fd62ea1a 2055 #endif /* HAL_ETH_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 2056 /**
NYX 0:85b3fd62ea1a 2057 * @}
NYX 0:85b3fd62ea1a 2058 */
NYX 0:85b3fd62ea1a 2059
NYX 0:85b3fd62ea1a 2060 /**
NYX 0:85b3fd62ea1a 2061 * @}
NYX 0:85b3fd62ea1a 2062 */
NYX 0:85b3fd62ea1a 2063
NYX 0:85b3fd62ea1a 2064 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/