Takaaki Numai / mbed-dev

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_dsi.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief DSI HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 9 * functionalities of the DSI peripheral:
NYX 0:85b3fd62ea1a 10 * + Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 11 * + IO operation functions
NYX 0:85b3fd62ea1a 12 * + Peripheral Control functions
NYX 0:85b3fd62ea1a 13 * + Peripheral State and Errors functions
NYX 0:85b3fd62ea1a 14 ******************************************************************************
NYX 0:85b3fd62ea1a 15 * @attention
NYX 0:85b3fd62ea1a 16 *
NYX 0:85b3fd62ea1a 17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 18 *
NYX 0:85b3fd62ea1a 19 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 20 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 21 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 22 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 24 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 25 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 27 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 28 * without specific prior written permission.
NYX 0:85b3fd62ea1a 29 *
NYX 0:85b3fd62ea1a 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 40 *
NYX 0:85b3fd62ea1a 41 ******************************************************************************
NYX 0:85b3fd62ea1a 42 */
NYX 0:85b3fd62ea1a 43
NYX 0:85b3fd62ea1a 44 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 45 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 46
NYX 0:85b3fd62ea1a 47 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 48 * @{
NYX 0:85b3fd62ea1a 49 */
NYX 0:85b3fd62ea1a 50 /** @addtogroup DSI
NYX 0:85b3fd62ea1a 51 * @{
NYX 0:85b3fd62ea1a 52 */
NYX 0:85b3fd62ea1a 53
NYX 0:85b3fd62ea1a 54 #ifdef HAL_DSI_MODULE_ENABLED
NYX 0:85b3fd62ea1a 55
NYX 0:85b3fd62ea1a 56 #if defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 57
NYX 0:85b3fd62ea1a 58 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 59 /* Private defines -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 60 /** @addtogroup DSI_Private_Constants
NYX 0:85b3fd62ea1a 61 * @{
NYX 0:85b3fd62ea1a 62 */
NYX 0:85b3fd62ea1a 63 #define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
NYX 0:85b3fd62ea1a 64
NYX 0:85b3fd62ea1a 65 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
NYX 0:85b3fd62ea1a 66 DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
NYX 0:85b3fd62ea1a 67 DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
NYX 0:85b3fd62ea1a 68 DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
NYX 0:85b3fd62ea1a 69 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
NYX 0:85b3fd62ea1a 70 #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
NYX 0:85b3fd62ea1a 71 #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
NYX 0:85b3fd62ea1a 72 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
NYX 0:85b3fd62ea1a 73 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
NYX 0:85b3fd62ea1a 74 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
NYX 0:85b3fd62ea1a 75 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
NYX 0:85b3fd62ea1a 76 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
NYX 0:85b3fd62ea1a 77 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
NYX 0:85b3fd62ea1a 78 /**
NYX 0:85b3fd62ea1a 79 * @}
NYX 0:85b3fd62ea1a 80 */
NYX 0:85b3fd62ea1a 81
NYX 0:85b3fd62ea1a 82 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 83 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 84 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 85 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 86 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
NYX 0:85b3fd62ea1a 87
NYX 0:85b3fd62ea1a 88 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 89 /**
NYX 0:85b3fd62ea1a 90 * @brief Generic DSI packet header configuration
NYX 0:85b3fd62ea1a 91 * @param DSIx: Pointer to DSI register base
NYX 0:85b3fd62ea1a 92 * @param ChannelID: Virtual channel ID of the header packet
NYX 0:85b3fd62ea1a 93 * @param DataType: Packet data type of the header packet
NYX 0:85b3fd62ea1a 94 * This parameter can be any value of :
NYX 0:85b3fd62ea1a 95 * @ref DSI_SHORT_WRITE_PKT_Data_Type
NYX 0:85b3fd62ea1a 96 * or @ref DSI_LONG_WRITE_PKT_Data_Type
NYX 0:85b3fd62ea1a 97 * or @ref DSI_SHORT_READ_PKT_Data_Type
NYX 0:85b3fd62ea1a 98 * or DSI_MAX_RETURN_PKT_SIZE
NYX 0:85b3fd62ea1a 99 * @param Data0: Word count LSB
NYX 0:85b3fd62ea1a 100 * @param Data1: Word count MSB
NYX 0:85b3fd62ea1a 101 * @retval None
NYX 0:85b3fd62ea1a 102 */
NYX 0:85b3fd62ea1a 103 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
NYX 0:85b3fd62ea1a 104 uint32_t ChannelID,
NYX 0:85b3fd62ea1a 105 uint32_t DataType,
NYX 0:85b3fd62ea1a 106 uint32_t Data0,
NYX 0:85b3fd62ea1a 107 uint32_t Data1)
NYX 0:85b3fd62ea1a 108 {
NYX 0:85b3fd62ea1a 109 /* Update the DSI packet header with new information */
NYX 0:85b3fd62ea1a 110 DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U));
NYX 0:85b3fd62ea1a 111 }
NYX 0:85b3fd62ea1a 112
NYX 0:85b3fd62ea1a 113 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 114 /** @addtogroup DSI_Exported_Functions
NYX 0:85b3fd62ea1a 115 * @{
NYX 0:85b3fd62ea1a 116 */
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 /** @defgroup DSI_Group1 Initialization and Configuration functions
NYX 0:85b3fd62ea1a 119 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 120 *
NYX 0:85b3fd62ea1a 121 @verbatim
NYX 0:85b3fd62ea1a 122 ===============================================================================
NYX 0:85b3fd62ea1a 123 ##### Initialization and Configuration functions #####
NYX 0:85b3fd62ea1a 124 ===============================================================================
NYX 0:85b3fd62ea1a 125 [..] This section provides functions allowing to:
NYX 0:85b3fd62ea1a 126 (+) Initialize and configure the DSI
NYX 0:85b3fd62ea1a 127 (+) De-initialize the DSI
NYX 0:85b3fd62ea1a 128
NYX 0:85b3fd62ea1a 129 @endverbatim
NYX 0:85b3fd62ea1a 130 * @{
NYX 0:85b3fd62ea1a 131 */
NYX 0:85b3fd62ea1a 132
NYX 0:85b3fd62ea1a 133 /**
NYX 0:85b3fd62ea1a 134 * @brief Initializes the DSI according to the specified
NYX 0:85b3fd62ea1a 135 * parameters in the DSI_InitTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 136 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 137 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 138 * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
NYX 0:85b3fd62ea1a 139 * the PLL Clock structure definition for the DSI.
NYX 0:85b3fd62ea1a 140 * @retval HAL status
NYX 0:85b3fd62ea1a 141 */
NYX 0:85b3fd62ea1a 142 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
NYX 0:85b3fd62ea1a 143 {
NYX 0:85b3fd62ea1a 144 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 145 uint32_t unitIntervalx4 = 0U;
NYX 0:85b3fd62ea1a 146 uint32_t tempIDF = 0U;
NYX 0:85b3fd62ea1a 147
NYX 0:85b3fd62ea1a 148 /* Check the DSI handle allocation */
NYX 0:85b3fd62ea1a 149 if(hdsi == NULL)
NYX 0:85b3fd62ea1a 150 {
NYX 0:85b3fd62ea1a 151 return HAL_ERROR;
NYX 0:85b3fd62ea1a 152 }
NYX 0:85b3fd62ea1a 153
NYX 0:85b3fd62ea1a 154 /* Check function parameters */
NYX 0:85b3fd62ea1a 155 assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
NYX 0:85b3fd62ea1a 156 assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
NYX 0:85b3fd62ea1a 157 assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
NYX 0:85b3fd62ea1a 158 assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
NYX 0:85b3fd62ea1a 159 assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
NYX 0:85b3fd62ea1a 160
NYX 0:85b3fd62ea1a 161 if(hdsi->State == HAL_DSI_STATE_RESET)
NYX 0:85b3fd62ea1a 162 {
NYX 0:85b3fd62ea1a 163 /* Initialize the low level hardware */
NYX 0:85b3fd62ea1a 164 HAL_DSI_MspInit(hdsi);
NYX 0:85b3fd62ea1a 165 }
NYX 0:85b3fd62ea1a 166
NYX 0:85b3fd62ea1a 167 /* Change DSI peripheral state */
NYX 0:85b3fd62ea1a 168 hdsi->State = HAL_DSI_STATE_BUSY;
NYX 0:85b3fd62ea1a 169
NYX 0:85b3fd62ea1a 170 /**************** Turn on the regulator and enable the DSI PLL ****************/
NYX 0:85b3fd62ea1a 171
NYX 0:85b3fd62ea1a 172 /* Enable the regulator */
NYX 0:85b3fd62ea1a 173 __HAL_DSI_REG_ENABLE(hdsi);
NYX 0:85b3fd62ea1a 174
NYX 0:85b3fd62ea1a 175 /* Get tick */
NYX 0:85b3fd62ea1a 176 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 177
NYX 0:85b3fd62ea1a 178 /* Wait until the regulator is ready */
NYX 0:85b3fd62ea1a 179 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
NYX 0:85b3fd62ea1a 180 {
NYX 0:85b3fd62ea1a 181 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 182 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 183 {
NYX 0:85b3fd62ea1a 184 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 185 }
NYX 0:85b3fd62ea1a 186 }
NYX 0:85b3fd62ea1a 187
NYX 0:85b3fd62ea1a 188 /* Set the PLL division factors */
NYX 0:85b3fd62ea1a 189 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
NYX 0:85b3fd62ea1a 190 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U));
NYX 0:85b3fd62ea1a 191
NYX 0:85b3fd62ea1a 192 /* Enable the DSI PLL */
NYX 0:85b3fd62ea1a 193 __HAL_DSI_PLL_ENABLE(hdsi);
NYX 0:85b3fd62ea1a 194
NYX 0:85b3fd62ea1a 195 /* Get tick */
NYX 0:85b3fd62ea1a 196 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 197
NYX 0:85b3fd62ea1a 198 /* Wait for the lock of the PLL */
NYX 0:85b3fd62ea1a 199 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
NYX 0:85b3fd62ea1a 200 {
NYX 0:85b3fd62ea1a 201 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 202 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 203 {
NYX 0:85b3fd62ea1a 204 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 205 }
NYX 0:85b3fd62ea1a 206 }
NYX 0:85b3fd62ea1a 207
NYX 0:85b3fd62ea1a 208 /*************************** Set the PHY parameters ***************************/
NYX 0:85b3fd62ea1a 209
NYX 0:85b3fd62ea1a 210 /* D-PHY clock and digital enable*/
NYX 0:85b3fd62ea1a 211 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
NYX 0:85b3fd62ea1a 212
NYX 0:85b3fd62ea1a 213 /* Clock lane configuration */
NYX 0:85b3fd62ea1a 214 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
NYX 0:85b3fd62ea1a 215 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
NYX 0:85b3fd62ea1a 216
NYX 0:85b3fd62ea1a 217 /* Configure the number of active data lanes */
NYX 0:85b3fd62ea1a 218 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
NYX 0:85b3fd62ea1a 219 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
NYX 0:85b3fd62ea1a 220
NYX 0:85b3fd62ea1a 221 /************************ Set the DSI clock parameters ************************/
NYX 0:85b3fd62ea1a 222
NYX 0:85b3fd62ea1a 223 /* Set the TX escape clock division factor */
NYX 0:85b3fd62ea1a 224 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
NYX 0:85b3fd62ea1a 225 hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
NYX 0:85b3fd62ea1a 226
NYX 0:85b3fd62ea1a 227 /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
NYX 0:85b3fd62ea1a 228 /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
NYX 0:85b3fd62ea1a 229 /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
NYX 0:85b3fd62ea1a 230 tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
NYX 0:85b3fd62ea1a 231 unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
NYX 0:85b3fd62ea1a 232
NYX 0:85b3fd62ea1a 233 /* Set the bit period in high-speed mode */
NYX 0:85b3fd62ea1a 234 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
NYX 0:85b3fd62ea1a 235 hdsi->Instance->WPCR[0U] |= unitIntervalx4;
NYX 0:85b3fd62ea1a 236
NYX 0:85b3fd62ea1a 237 /****************************** Error management *****************************/
NYX 0:85b3fd62ea1a 238
NYX 0:85b3fd62ea1a 239 /* Disable all error interrupts and reset the Error Mask */
NYX 0:85b3fd62ea1a 240 hdsi->Instance->IER[0U] = 0U;
NYX 0:85b3fd62ea1a 241 hdsi->Instance->IER[1U] = 0U;
NYX 0:85b3fd62ea1a 242 hdsi->ErrorMsk = 0U;
NYX 0:85b3fd62ea1a 243
NYX 0:85b3fd62ea1a 244 /* Initialise the error code */
NYX 0:85b3fd62ea1a 245 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
NYX 0:85b3fd62ea1a 246
NYX 0:85b3fd62ea1a 247 /* Initialize the DSI state*/
NYX 0:85b3fd62ea1a 248 hdsi->State = HAL_DSI_STATE_READY;
NYX 0:85b3fd62ea1a 249
NYX 0:85b3fd62ea1a 250 return HAL_OK;
NYX 0:85b3fd62ea1a 251 }
NYX 0:85b3fd62ea1a 252
NYX 0:85b3fd62ea1a 253 /**
NYX 0:85b3fd62ea1a 254 * @brief De-initializes the DSI peripheral registers to their default reset
NYX 0:85b3fd62ea1a 255 * values.
NYX 0:85b3fd62ea1a 256 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 257 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 258 * @retval HAL status
NYX 0:85b3fd62ea1a 259 */
NYX 0:85b3fd62ea1a 260 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 261 {
NYX 0:85b3fd62ea1a 262 /* Check the DSI handle allocation */
NYX 0:85b3fd62ea1a 263 if(hdsi == NULL)
NYX 0:85b3fd62ea1a 264 {
NYX 0:85b3fd62ea1a 265 return HAL_ERROR;
NYX 0:85b3fd62ea1a 266 }
NYX 0:85b3fd62ea1a 267
NYX 0:85b3fd62ea1a 268 /* Change DSI peripheral state */
NYX 0:85b3fd62ea1a 269 hdsi->State = HAL_DSI_STATE_BUSY;
NYX 0:85b3fd62ea1a 270
NYX 0:85b3fd62ea1a 271 /* Disable the DSI wrapper */
NYX 0:85b3fd62ea1a 272 __HAL_DSI_WRAPPER_DISABLE(hdsi);
NYX 0:85b3fd62ea1a 273
NYX 0:85b3fd62ea1a 274 /* Disable the DSI host */
NYX 0:85b3fd62ea1a 275 __HAL_DSI_DISABLE(hdsi);
NYX 0:85b3fd62ea1a 276
NYX 0:85b3fd62ea1a 277 /* D-PHY clock and digital disable */
NYX 0:85b3fd62ea1a 278 hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
NYX 0:85b3fd62ea1a 279
NYX 0:85b3fd62ea1a 280 /* Turn off the DSI PLL */
NYX 0:85b3fd62ea1a 281 __HAL_DSI_PLL_DISABLE(hdsi);
NYX 0:85b3fd62ea1a 282
NYX 0:85b3fd62ea1a 283 /* Disable the regulator */
NYX 0:85b3fd62ea1a 284 __HAL_DSI_REG_DISABLE(hdsi);
NYX 0:85b3fd62ea1a 285
NYX 0:85b3fd62ea1a 286 /* DeInit the low level hardware */
NYX 0:85b3fd62ea1a 287 HAL_DSI_MspDeInit(hdsi);
NYX 0:85b3fd62ea1a 288
NYX 0:85b3fd62ea1a 289 /* Initialise the error code */
NYX 0:85b3fd62ea1a 290 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
NYX 0:85b3fd62ea1a 291
NYX 0:85b3fd62ea1a 292 /* Initialize the DSI state*/
NYX 0:85b3fd62ea1a 293 hdsi->State = HAL_DSI_STATE_RESET;
NYX 0:85b3fd62ea1a 294
NYX 0:85b3fd62ea1a 295 /* Release Lock */
NYX 0:85b3fd62ea1a 296 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 297
NYX 0:85b3fd62ea1a 298 return HAL_OK;
NYX 0:85b3fd62ea1a 299 }
NYX 0:85b3fd62ea1a 300
NYX 0:85b3fd62ea1a 301 /**
NYX 0:85b3fd62ea1a 302 * @brief Return the DSI error code
NYX 0:85b3fd62ea1a 303 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 304 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 305 * @retval DSI Error Code
NYX 0:85b3fd62ea1a 306 */
NYX 0:85b3fd62ea1a 307 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 308 {
NYX 0:85b3fd62ea1a 309 /* Get the error code */
NYX 0:85b3fd62ea1a 310 return hdsi->ErrorCode;
NYX 0:85b3fd62ea1a 311 }
NYX 0:85b3fd62ea1a 312
NYX 0:85b3fd62ea1a 313 /**
NYX 0:85b3fd62ea1a 314 * @brief Enable the error monitor flags
NYX 0:85b3fd62ea1a 315 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 316 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 317 * @param ActiveErrors: indicates which error interrupts will be enabled.
NYX 0:85b3fd62ea1a 318 * This parameter can be any combination of @ref DSI_Error_Data_Type.
NYX 0:85b3fd62ea1a 319 * @retval HAL status
NYX 0:85b3fd62ea1a 320 */
NYX 0:85b3fd62ea1a 321 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
NYX 0:85b3fd62ea1a 322 {
NYX 0:85b3fd62ea1a 323 /* Process locked */
NYX 0:85b3fd62ea1a 324 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 325
NYX 0:85b3fd62ea1a 326 hdsi->Instance->IER[0U] = 0U;
NYX 0:85b3fd62ea1a 327 hdsi->Instance->IER[1U] = 0U;
NYX 0:85b3fd62ea1a 328
NYX 0:85b3fd62ea1a 329 /* Store active errors to the handle */
NYX 0:85b3fd62ea1a 330 hdsi->ErrorMsk = ActiveErrors;
NYX 0:85b3fd62ea1a 331
NYX 0:85b3fd62ea1a 332 if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
NYX 0:85b3fd62ea1a 333 {
NYX 0:85b3fd62ea1a 334 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 335 hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
NYX 0:85b3fd62ea1a 336 }
NYX 0:85b3fd62ea1a 337
NYX 0:85b3fd62ea1a 338 if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET)
NYX 0:85b3fd62ea1a 339 {
NYX 0:85b3fd62ea1a 340 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 341 hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
NYX 0:85b3fd62ea1a 342 }
NYX 0:85b3fd62ea1a 343
NYX 0:85b3fd62ea1a 344 if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
NYX 0:85b3fd62ea1a 345 {
NYX 0:85b3fd62ea1a 346 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 347 hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
NYX 0:85b3fd62ea1a 348 }
NYX 0:85b3fd62ea1a 349
NYX 0:85b3fd62ea1a 350 if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
NYX 0:85b3fd62ea1a 351 {
NYX 0:85b3fd62ea1a 352 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 353 hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
NYX 0:85b3fd62ea1a 354 }
NYX 0:85b3fd62ea1a 355
NYX 0:85b3fd62ea1a 356 if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
NYX 0:85b3fd62ea1a 357 {
NYX 0:85b3fd62ea1a 358 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 359 hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
NYX 0:85b3fd62ea1a 360 }
NYX 0:85b3fd62ea1a 361
NYX 0:85b3fd62ea1a 362 if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
NYX 0:85b3fd62ea1a 363 {
NYX 0:85b3fd62ea1a 364 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 365 hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
NYX 0:85b3fd62ea1a 366 }
NYX 0:85b3fd62ea1a 367
NYX 0:85b3fd62ea1a 368 if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
NYX 0:85b3fd62ea1a 369 {
NYX 0:85b3fd62ea1a 370 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 371 hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
NYX 0:85b3fd62ea1a 372 }
NYX 0:85b3fd62ea1a 373
NYX 0:85b3fd62ea1a 374 if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
NYX 0:85b3fd62ea1a 375 {
NYX 0:85b3fd62ea1a 376 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 377 hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
NYX 0:85b3fd62ea1a 378 }
NYX 0:85b3fd62ea1a 379
NYX 0:85b3fd62ea1a 380 if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
NYX 0:85b3fd62ea1a 381 {
NYX 0:85b3fd62ea1a 382 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 383 hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
NYX 0:85b3fd62ea1a 384 }
NYX 0:85b3fd62ea1a 385
NYX 0:85b3fd62ea1a 386 if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
NYX 0:85b3fd62ea1a 387 {
NYX 0:85b3fd62ea1a 388 /* Enable the interrupt generation on selected errors */
NYX 0:85b3fd62ea1a 389 hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
NYX 0:85b3fd62ea1a 390 }
NYX 0:85b3fd62ea1a 391
NYX 0:85b3fd62ea1a 392 /* Process Unlocked */
NYX 0:85b3fd62ea1a 393 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 394
NYX 0:85b3fd62ea1a 395 return HAL_OK;
NYX 0:85b3fd62ea1a 396 }
NYX 0:85b3fd62ea1a 397
NYX 0:85b3fd62ea1a 398 /**
NYX 0:85b3fd62ea1a 399 * @brief Initializes the DSI MSP.
NYX 0:85b3fd62ea1a 400 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 401 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 402 * @retval None
NYX 0:85b3fd62ea1a 403 */
NYX 0:85b3fd62ea1a 404 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
NYX 0:85b3fd62ea1a 405 {
NYX 0:85b3fd62ea1a 406 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 407 UNUSED(hdsi);
NYX 0:85b3fd62ea1a 408 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 409 the HAL_DSI_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 410 */
NYX 0:85b3fd62ea1a 411 }
NYX 0:85b3fd62ea1a 412
NYX 0:85b3fd62ea1a 413 /**
NYX 0:85b3fd62ea1a 414 * @brief De-initializes the DSI MSP.
NYX 0:85b3fd62ea1a 415 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 416 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 417 * @retval None
NYX 0:85b3fd62ea1a 418 */
NYX 0:85b3fd62ea1a 419 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
NYX 0:85b3fd62ea1a 420 {
NYX 0:85b3fd62ea1a 421 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 422 UNUSED(hdsi);
NYX 0:85b3fd62ea1a 423 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 424 the HAL_DSI_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 425 */
NYX 0:85b3fd62ea1a 426 }
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428 /**
NYX 0:85b3fd62ea1a 429 * @}
NYX 0:85b3fd62ea1a 430 */
NYX 0:85b3fd62ea1a 431
NYX 0:85b3fd62ea1a 432 /** @defgroup DSI_Group2 IO operation functions
NYX 0:85b3fd62ea1a 433 * @brief IO operation functions
NYX 0:85b3fd62ea1a 434 *
NYX 0:85b3fd62ea1a 435 @verbatim
NYX 0:85b3fd62ea1a 436 ===============================================================================
NYX 0:85b3fd62ea1a 437 ##### IO operation functions #####
NYX 0:85b3fd62ea1a 438 ===============================================================================
NYX 0:85b3fd62ea1a 439 [..] This section provides function allowing to:
NYX 0:85b3fd62ea1a 440 (+) Handle DSI interrupt request
NYX 0:85b3fd62ea1a 441
NYX 0:85b3fd62ea1a 442 @endverbatim
NYX 0:85b3fd62ea1a 443 * @{
NYX 0:85b3fd62ea1a 444 */
NYX 0:85b3fd62ea1a 445 /**
NYX 0:85b3fd62ea1a 446 * @brief Handles DSI interrupt request.
NYX 0:85b3fd62ea1a 447 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 448 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 449 * @retval HAL status
NYX 0:85b3fd62ea1a 450 */
NYX 0:85b3fd62ea1a 451 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 452 {
NYX 0:85b3fd62ea1a 453 uint32_t ErrorStatus0, ErrorStatus1;
NYX 0:85b3fd62ea1a 454
NYX 0:85b3fd62ea1a 455 /* Tearing Effect Interrupt management ***************************************/
NYX 0:85b3fd62ea1a 456 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
NYX 0:85b3fd62ea1a 457 {
NYX 0:85b3fd62ea1a 458 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
NYX 0:85b3fd62ea1a 459 {
NYX 0:85b3fd62ea1a 460 /* Clear the Tearing Effect Interrupt Flag */
NYX 0:85b3fd62ea1a 461 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
NYX 0:85b3fd62ea1a 462
NYX 0:85b3fd62ea1a 463 /* Tearing Effect Callback */
NYX 0:85b3fd62ea1a 464 HAL_DSI_TearingEffectCallback(hdsi);
NYX 0:85b3fd62ea1a 465 }
NYX 0:85b3fd62ea1a 466 }
NYX 0:85b3fd62ea1a 467
NYX 0:85b3fd62ea1a 468 /* End of Refresh Interrupt management ***************************************/
NYX 0:85b3fd62ea1a 469 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
NYX 0:85b3fd62ea1a 470 {
NYX 0:85b3fd62ea1a 471 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
NYX 0:85b3fd62ea1a 472 {
NYX 0:85b3fd62ea1a 473 /* Clear the End of Refresh Interrupt Flag */
NYX 0:85b3fd62ea1a 474 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
NYX 0:85b3fd62ea1a 475
NYX 0:85b3fd62ea1a 476 /* End of Refresh Callback */
NYX 0:85b3fd62ea1a 477 HAL_DSI_EndOfRefreshCallback(hdsi);
NYX 0:85b3fd62ea1a 478 }
NYX 0:85b3fd62ea1a 479 }
NYX 0:85b3fd62ea1a 480
NYX 0:85b3fd62ea1a 481 /* Error Interrupts management ***********************************************/
NYX 0:85b3fd62ea1a 482 if(hdsi->ErrorMsk != 0U)
NYX 0:85b3fd62ea1a 483 {
NYX 0:85b3fd62ea1a 484 ErrorStatus0 = hdsi->Instance->ISR[0U];
NYX 0:85b3fd62ea1a 485 ErrorStatus0 &= hdsi->Instance->IER[0U];
NYX 0:85b3fd62ea1a 486 ErrorStatus1 = hdsi->Instance->ISR[1U];
NYX 0:85b3fd62ea1a 487 ErrorStatus1 &= hdsi->Instance->IER[1U];
NYX 0:85b3fd62ea1a 488
NYX 0:85b3fd62ea1a 489 if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
NYX 0:85b3fd62ea1a 490 {
NYX 0:85b3fd62ea1a 491 hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
NYX 0:85b3fd62ea1a 492 }
NYX 0:85b3fd62ea1a 493
NYX 0:85b3fd62ea1a 494 if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
NYX 0:85b3fd62ea1a 495 {
NYX 0:85b3fd62ea1a 496 hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
NYX 0:85b3fd62ea1a 497 }
NYX 0:85b3fd62ea1a 498
NYX 0:85b3fd62ea1a 499 if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
NYX 0:85b3fd62ea1a 500 {
NYX 0:85b3fd62ea1a 501 hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
NYX 0:85b3fd62ea1a 502 }
NYX 0:85b3fd62ea1a 503
NYX 0:85b3fd62ea1a 504 if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
NYX 0:85b3fd62ea1a 505 {
NYX 0:85b3fd62ea1a 506 hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
NYX 0:85b3fd62ea1a 507 }
NYX 0:85b3fd62ea1a 508
NYX 0:85b3fd62ea1a 509 if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
NYX 0:85b3fd62ea1a 510 {
NYX 0:85b3fd62ea1a 511 hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
NYX 0:85b3fd62ea1a 512 }
NYX 0:85b3fd62ea1a 513
NYX 0:85b3fd62ea1a 514 if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
NYX 0:85b3fd62ea1a 515 {
NYX 0:85b3fd62ea1a 516 hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
NYX 0:85b3fd62ea1a 517 }
NYX 0:85b3fd62ea1a 518
NYX 0:85b3fd62ea1a 519 if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
NYX 0:85b3fd62ea1a 520 {
NYX 0:85b3fd62ea1a 521 hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
NYX 0:85b3fd62ea1a 522 }
NYX 0:85b3fd62ea1a 523
NYX 0:85b3fd62ea1a 524 if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
NYX 0:85b3fd62ea1a 525 {
NYX 0:85b3fd62ea1a 526 hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
NYX 0:85b3fd62ea1a 527 }
NYX 0:85b3fd62ea1a 528
NYX 0:85b3fd62ea1a 529 if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
NYX 0:85b3fd62ea1a 530 {
NYX 0:85b3fd62ea1a 531 hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
NYX 0:85b3fd62ea1a 532 }
NYX 0:85b3fd62ea1a 533
NYX 0:85b3fd62ea1a 534 if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
NYX 0:85b3fd62ea1a 535 {
NYX 0:85b3fd62ea1a 536 hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
NYX 0:85b3fd62ea1a 537 }
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 /* Check only selected errors */
NYX 0:85b3fd62ea1a 540 if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
NYX 0:85b3fd62ea1a 541 {
NYX 0:85b3fd62ea1a 542 /* DSI error interrupt user callback */
NYX 0:85b3fd62ea1a 543 HAL_DSI_ErrorCallback(hdsi);
NYX 0:85b3fd62ea1a 544 }
NYX 0:85b3fd62ea1a 545 }
NYX 0:85b3fd62ea1a 546 }
NYX 0:85b3fd62ea1a 547
NYX 0:85b3fd62ea1a 548 /**
NYX 0:85b3fd62ea1a 549 * @brief Tearing Effect DSI callback.
NYX 0:85b3fd62ea1a 550 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 551 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 552 * @retval None
NYX 0:85b3fd62ea1a 553 */
NYX 0:85b3fd62ea1a 554 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 555 {
NYX 0:85b3fd62ea1a 556 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 557 UNUSED(hdsi);
NYX 0:85b3fd62ea1a 558 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 559 the HAL_DSI_TearingEffectCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 560 */
NYX 0:85b3fd62ea1a 561 }
NYX 0:85b3fd62ea1a 562
NYX 0:85b3fd62ea1a 563 /**
NYX 0:85b3fd62ea1a 564 * @brief End of Refresh DSI callback.
NYX 0:85b3fd62ea1a 565 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 566 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 567 * @retval None
NYX 0:85b3fd62ea1a 568 */
NYX 0:85b3fd62ea1a 569 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 570 {
NYX 0:85b3fd62ea1a 571 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 572 UNUSED(hdsi);
NYX 0:85b3fd62ea1a 573 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 574 the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 575 */
NYX 0:85b3fd62ea1a 576 }
NYX 0:85b3fd62ea1a 577
NYX 0:85b3fd62ea1a 578 /**
NYX 0:85b3fd62ea1a 579 * @brief Operation Error DSI callback.
NYX 0:85b3fd62ea1a 580 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 581 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 582 * @retval None
NYX 0:85b3fd62ea1a 583 */
NYX 0:85b3fd62ea1a 584 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 585 {
NYX 0:85b3fd62ea1a 586 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 587 UNUSED(hdsi);
NYX 0:85b3fd62ea1a 588 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 589 the HAL_DSI_ErrorCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 590 */
NYX 0:85b3fd62ea1a 591 }
NYX 0:85b3fd62ea1a 592
NYX 0:85b3fd62ea1a 593 /**
NYX 0:85b3fd62ea1a 594 * @}
NYX 0:85b3fd62ea1a 595 */
NYX 0:85b3fd62ea1a 596
NYX 0:85b3fd62ea1a 597 /** @defgroup DSI_Group3 Peripheral Control functions
NYX 0:85b3fd62ea1a 598 * @brief Peripheral Control functions
NYX 0:85b3fd62ea1a 599 *
NYX 0:85b3fd62ea1a 600 @verbatim
NYX 0:85b3fd62ea1a 601 ===============================================================================
NYX 0:85b3fd62ea1a 602 ##### Peripheral Control functions #####
NYX 0:85b3fd62ea1a 603 ===============================================================================
NYX 0:85b3fd62ea1a 604
NYX 0:85b3fd62ea1a 605 @endverbatim
NYX 0:85b3fd62ea1a 606 * @{
NYX 0:85b3fd62ea1a 607 */
NYX 0:85b3fd62ea1a 608
NYX 0:85b3fd62ea1a 609 /**
NYX 0:85b3fd62ea1a 610 * @brief Configure the Generic interface read-back Virtual Channel ID.
NYX 0:85b3fd62ea1a 611 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 612 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 613 * @param VirtualChannelID: Virtual channel ID
NYX 0:85b3fd62ea1a 614 * @retval HAL status
NYX 0:85b3fd62ea1a 615 */
NYX 0:85b3fd62ea1a 616 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
NYX 0:85b3fd62ea1a 617 {
NYX 0:85b3fd62ea1a 618 /* Process locked */
NYX 0:85b3fd62ea1a 619 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 620
NYX 0:85b3fd62ea1a 621 /* Update the GVCID register */
NYX 0:85b3fd62ea1a 622 hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
NYX 0:85b3fd62ea1a 623 hdsi->Instance->GVCIDR |= VirtualChannelID;
NYX 0:85b3fd62ea1a 624
NYX 0:85b3fd62ea1a 625 /* Process unlocked */
NYX 0:85b3fd62ea1a 626 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 627
NYX 0:85b3fd62ea1a 628 return HAL_OK;
NYX 0:85b3fd62ea1a 629 }
NYX 0:85b3fd62ea1a 630
NYX 0:85b3fd62ea1a 631 /**
NYX 0:85b3fd62ea1a 632 * @brief Select video mode and configure the corresponding parameters
NYX 0:85b3fd62ea1a 633 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 634 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 635 * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
NYX 0:85b3fd62ea1a 636 * the DSI video mode configuration parameters
NYX 0:85b3fd62ea1a 637 * @retval HAL status
NYX 0:85b3fd62ea1a 638 */
NYX 0:85b3fd62ea1a 639 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
NYX 0:85b3fd62ea1a 640 {
NYX 0:85b3fd62ea1a 641 /* Process locked */
NYX 0:85b3fd62ea1a 642 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 643
NYX 0:85b3fd62ea1a 644 /* Check the parameters */
NYX 0:85b3fd62ea1a 645 assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
NYX 0:85b3fd62ea1a 646 assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
NYX 0:85b3fd62ea1a 647 assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
NYX 0:85b3fd62ea1a 648 assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
NYX 0:85b3fd62ea1a 649 assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
NYX 0:85b3fd62ea1a 650 assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
NYX 0:85b3fd62ea1a 651 assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
NYX 0:85b3fd62ea1a 652 assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
NYX 0:85b3fd62ea1a 653 assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
NYX 0:85b3fd62ea1a 654 assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
NYX 0:85b3fd62ea1a 655 assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
NYX 0:85b3fd62ea1a 656 assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
NYX 0:85b3fd62ea1a 657 assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
NYX 0:85b3fd62ea1a 658 /* Check the LooselyPacked variant only in 18-bit mode */
NYX 0:85b3fd62ea1a 659 if(VidCfg->ColorCoding == DSI_RGB666)
NYX 0:85b3fd62ea1a 660 {
NYX 0:85b3fd62ea1a 661 assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
NYX 0:85b3fd62ea1a 662 }
NYX 0:85b3fd62ea1a 663
NYX 0:85b3fd62ea1a 664 /* Select video mode by resetting CMDM and DSIM bits */
NYX 0:85b3fd62ea1a 665 hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
NYX 0:85b3fd62ea1a 666 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
NYX 0:85b3fd62ea1a 667
NYX 0:85b3fd62ea1a 668 /* Configure the video mode transmission type */
NYX 0:85b3fd62ea1a 669 hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
NYX 0:85b3fd62ea1a 670 hdsi->Instance->VMCR |= VidCfg->Mode;
NYX 0:85b3fd62ea1a 671
NYX 0:85b3fd62ea1a 672 /* Configure the video packet size */
NYX 0:85b3fd62ea1a 673 hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
NYX 0:85b3fd62ea1a 674 hdsi->Instance->VPCR |= VidCfg->PacketSize;
NYX 0:85b3fd62ea1a 675
NYX 0:85b3fd62ea1a 676 /* Set the chunks number to be transmitted through the DSI link */
NYX 0:85b3fd62ea1a 677 hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
NYX 0:85b3fd62ea1a 678 hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
NYX 0:85b3fd62ea1a 679
NYX 0:85b3fd62ea1a 680 /* Set the size of the null packet */
NYX 0:85b3fd62ea1a 681 hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
NYX 0:85b3fd62ea1a 682 hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
NYX 0:85b3fd62ea1a 683
NYX 0:85b3fd62ea1a 684 /* Select the virtual channel for the LTDC interface traffic */
NYX 0:85b3fd62ea1a 685 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
NYX 0:85b3fd62ea1a 686 hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
NYX 0:85b3fd62ea1a 687
NYX 0:85b3fd62ea1a 688 /* Configure the polarity of control signals */
NYX 0:85b3fd62ea1a 689 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
NYX 0:85b3fd62ea1a 690 hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
NYX 0:85b3fd62ea1a 691
NYX 0:85b3fd62ea1a 692 /* Select the color coding for the host */
NYX 0:85b3fd62ea1a 693 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
NYX 0:85b3fd62ea1a 694 hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
NYX 0:85b3fd62ea1a 695
NYX 0:85b3fd62ea1a 696 /* Select the color coding for the wrapper */
NYX 0:85b3fd62ea1a 697 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
NYX 0:85b3fd62ea1a 698 hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U);
NYX 0:85b3fd62ea1a 699
NYX 0:85b3fd62ea1a 700 /* Enable/disable the loosely packed variant to 18-bit configuration */
NYX 0:85b3fd62ea1a 701 if(VidCfg->ColorCoding == DSI_RGB666)
NYX 0:85b3fd62ea1a 702 {
NYX 0:85b3fd62ea1a 703 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
NYX 0:85b3fd62ea1a 704 hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
NYX 0:85b3fd62ea1a 705 }
NYX 0:85b3fd62ea1a 706
NYX 0:85b3fd62ea1a 707 /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
NYX 0:85b3fd62ea1a 708 hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
NYX 0:85b3fd62ea1a 709 hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
NYX 0:85b3fd62ea1a 710
NYX 0:85b3fd62ea1a 711 /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
NYX 0:85b3fd62ea1a 712 hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
NYX 0:85b3fd62ea1a 713 hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
NYX 0:85b3fd62ea1a 714
NYX 0:85b3fd62ea1a 715 /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
NYX 0:85b3fd62ea1a 716 hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
NYX 0:85b3fd62ea1a 717 hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
NYX 0:85b3fd62ea1a 718
NYX 0:85b3fd62ea1a 719 /* Set the Vertical Synchronization Active (VSA) */
NYX 0:85b3fd62ea1a 720 hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
NYX 0:85b3fd62ea1a 721 hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
NYX 0:85b3fd62ea1a 722
NYX 0:85b3fd62ea1a 723 /* Set the Vertical Back Porch (VBP)*/
NYX 0:85b3fd62ea1a 724 hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
NYX 0:85b3fd62ea1a 725 hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
NYX 0:85b3fd62ea1a 726
NYX 0:85b3fd62ea1a 727 /* Set the Vertical Front Porch (VFP)*/
NYX 0:85b3fd62ea1a 728 hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
NYX 0:85b3fd62ea1a 729 hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
NYX 0:85b3fd62ea1a 730
NYX 0:85b3fd62ea1a 731 /* Set the Vertical Active period*/
NYX 0:85b3fd62ea1a 732 hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
NYX 0:85b3fd62ea1a 733 hdsi->Instance->VVACR |= VidCfg->VerticalActive;
NYX 0:85b3fd62ea1a 734
NYX 0:85b3fd62ea1a 735 /* Configure the command transmission mode */
NYX 0:85b3fd62ea1a 736 hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
NYX 0:85b3fd62ea1a 737 hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
NYX 0:85b3fd62ea1a 738
NYX 0:85b3fd62ea1a 739 /* Low power largest packet size */
NYX 0:85b3fd62ea1a 740 hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
NYX 0:85b3fd62ea1a 741 hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U);
NYX 0:85b3fd62ea1a 742
NYX 0:85b3fd62ea1a 743 /* Low power VACT largest packet size */
NYX 0:85b3fd62ea1a 744 hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
NYX 0:85b3fd62ea1a 745 hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
NYX 0:85b3fd62ea1a 746
NYX 0:85b3fd62ea1a 747 /* Enable LP transition in HFP period */
NYX 0:85b3fd62ea1a 748 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
NYX 0:85b3fd62ea1a 749 hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
NYX 0:85b3fd62ea1a 750
NYX 0:85b3fd62ea1a 751 /* Enable LP transition in HBP period */
NYX 0:85b3fd62ea1a 752 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
NYX 0:85b3fd62ea1a 753 hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
NYX 0:85b3fd62ea1a 754
NYX 0:85b3fd62ea1a 755 /* Enable LP transition in VACT period */
NYX 0:85b3fd62ea1a 756 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
NYX 0:85b3fd62ea1a 757 hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
NYX 0:85b3fd62ea1a 758
NYX 0:85b3fd62ea1a 759 /* Enable LP transition in VFP period */
NYX 0:85b3fd62ea1a 760 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
NYX 0:85b3fd62ea1a 761 hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
NYX 0:85b3fd62ea1a 762
NYX 0:85b3fd62ea1a 763 /* Enable LP transition in VBP period */
NYX 0:85b3fd62ea1a 764 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
NYX 0:85b3fd62ea1a 765 hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
NYX 0:85b3fd62ea1a 766
NYX 0:85b3fd62ea1a 767 /* Enable LP transition in vertical sync period */
NYX 0:85b3fd62ea1a 768 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
NYX 0:85b3fd62ea1a 769 hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
NYX 0:85b3fd62ea1a 770
NYX 0:85b3fd62ea1a 771 /* Enable the request for an acknowledge response at the end of a frame */
NYX 0:85b3fd62ea1a 772 hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
NYX 0:85b3fd62ea1a 773 hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
NYX 0:85b3fd62ea1a 774
NYX 0:85b3fd62ea1a 775 /* Process unlocked */
NYX 0:85b3fd62ea1a 776 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 777
NYX 0:85b3fd62ea1a 778 return HAL_OK;
NYX 0:85b3fd62ea1a 779 }
NYX 0:85b3fd62ea1a 780
NYX 0:85b3fd62ea1a 781 /**
NYX 0:85b3fd62ea1a 782 * @brief Select adapted command mode and configure the corresponding parameters
NYX 0:85b3fd62ea1a 783 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 784 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 785 * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
NYX 0:85b3fd62ea1a 786 * the DSI command mode configuration parameters
NYX 0:85b3fd62ea1a 787 * @retval HAL status
NYX 0:85b3fd62ea1a 788 */
NYX 0:85b3fd62ea1a 789 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
NYX 0:85b3fd62ea1a 790 {
NYX 0:85b3fd62ea1a 791 /* Process locked */
NYX 0:85b3fd62ea1a 792 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 793
NYX 0:85b3fd62ea1a 794 /* Check the parameters */
NYX 0:85b3fd62ea1a 795 assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
NYX 0:85b3fd62ea1a 796 assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
NYX 0:85b3fd62ea1a 797 assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
NYX 0:85b3fd62ea1a 798 assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
NYX 0:85b3fd62ea1a 799 assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
NYX 0:85b3fd62ea1a 800 assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
NYX 0:85b3fd62ea1a 801 assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
NYX 0:85b3fd62ea1a 802 assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
NYX 0:85b3fd62ea1a 803 assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
NYX 0:85b3fd62ea1a 804
NYX 0:85b3fd62ea1a 805 /* Select command mode by setting CMDM and DSIM bits */
NYX 0:85b3fd62ea1a 806 hdsi->Instance->MCR |= DSI_MCR_CMDM;
NYX 0:85b3fd62ea1a 807 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
NYX 0:85b3fd62ea1a 808 hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
NYX 0:85b3fd62ea1a 809
NYX 0:85b3fd62ea1a 810 /* Select the virtual channel for the LTDC interface traffic */
NYX 0:85b3fd62ea1a 811 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
NYX 0:85b3fd62ea1a 812 hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
NYX 0:85b3fd62ea1a 813
NYX 0:85b3fd62ea1a 814 /* Configure the polarity of control signals */
NYX 0:85b3fd62ea1a 815 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
NYX 0:85b3fd62ea1a 816 hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
NYX 0:85b3fd62ea1a 817
NYX 0:85b3fd62ea1a 818 /* Select the color coding for the host */
NYX 0:85b3fd62ea1a 819 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
NYX 0:85b3fd62ea1a 820 hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
NYX 0:85b3fd62ea1a 821
NYX 0:85b3fd62ea1a 822 /* Select the color coding for the wrapper */
NYX 0:85b3fd62ea1a 823 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
NYX 0:85b3fd62ea1a 824 hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U);
NYX 0:85b3fd62ea1a 825
NYX 0:85b3fd62ea1a 826 /* Configure the maximum allowed size for write memory command */
NYX 0:85b3fd62ea1a 827 hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
NYX 0:85b3fd62ea1a 828 hdsi->Instance->LCCR |= CmdCfg->CommandSize;
NYX 0:85b3fd62ea1a 829
NYX 0:85b3fd62ea1a 830 /* Configure the tearing effect source and polarity and select the refresh mode */
NYX 0:85b3fd62ea1a 831 hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
NYX 0:85b3fd62ea1a 832 hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
NYX 0:85b3fd62ea1a 833
NYX 0:85b3fd62ea1a 834 /* Configure the tearing effect acknowledge request */
NYX 0:85b3fd62ea1a 835 hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
NYX 0:85b3fd62ea1a 836 hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
NYX 0:85b3fd62ea1a 837
NYX 0:85b3fd62ea1a 838 /* Enable the Tearing Effect interrupt */
NYX 0:85b3fd62ea1a 839 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
NYX 0:85b3fd62ea1a 840
NYX 0:85b3fd62ea1a 841 /* Enable the End of Refresh interrupt */
NYX 0:85b3fd62ea1a 842 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
NYX 0:85b3fd62ea1a 843
NYX 0:85b3fd62ea1a 844 /* Process unlocked */
NYX 0:85b3fd62ea1a 845 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 846
NYX 0:85b3fd62ea1a 847 return HAL_OK;
NYX 0:85b3fd62ea1a 848 }
NYX 0:85b3fd62ea1a 849
NYX 0:85b3fd62ea1a 850 /**
NYX 0:85b3fd62ea1a 851 * @brief Configure command transmission mode: High-speed or Low-power
NYX 0:85b3fd62ea1a 852 * and enable/disable acknowledge request after packet transmission
NYX 0:85b3fd62ea1a 853 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 854 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 855 * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
NYX 0:85b3fd62ea1a 856 * the DSI command transmission mode configuration parameters
NYX 0:85b3fd62ea1a 857 * @retval HAL status
NYX 0:85b3fd62ea1a 858 */
NYX 0:85b3fd62ea1a 859 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
NYX 0:85b3fd62ea1a 860 {
NYX 0:85b3fd62ea1a 861 /* Process locked */
NYX 0:85b3fd62ea1a 862 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 863
NYX 0:85b3fd62ea1a 864 assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
NYX 0:85b3fd62ea1a 865 assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
NYX 0:85b3fd62ea1a 866 assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
NYX 0:85b3fd62ea1a 867 assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
NYX 0:85b3fd62ea1a 868 assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
NYX 0:85b3fd62ea1a 869 assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
NYX 0:85b3fd62ea1a 870 assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
NYX 0:85b3fd62ea1a 871 assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
NYX 0:85b3fd62ea1a 872 assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
NYX 0:85b3fd62ea1a 873 assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
NYX 0:85b3fd62ea1a 874 assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
NYX 0:85b3fd62ea1a 875 assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
NYX 0:85b3fd62ea1a 876 assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
NYX 0:85b3fd62ea1a 877
NYX 0:85b3fd62ea1a 878 /* Select High-speed or Low-power for command transmission */
NYX 0:85b3fd62ea1a 879 hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
NYX 0:85b3fd62ea1a 880 DSI_CMCR_GSW1TX |\
NYX 0:85b3fd62ea1a 881 DSI_CMCR_GSW2TX |\
NYX 0:85b3fd62ea1a 882 DSI_CMCR_GSR0TX |\
NYX 0:85b3fd62ea1a 883 DSI_CMCR_GSR1TX |\
NYX 0:85b3fd62ea1a 884 DSI_CMCR_GSR2TX |\
NYX 0:85b3fd62ea1a 885 DSI_CMCR_GLWTX |\
NYX 0:85b3fd62ea1a 886 DSI_CMCR_DSW0TX |\
NYX 0:85b3fd62ea1a 887 DSI_CMCR_DSW1TX |\
NYX 0:85b3fd62ea1a 888 DSI_CMCR_DSR0TX |\
NYX 0:85b3fd62ea1a 889 DSI_CMCR_DLWTX |\
NYX 0:85b3fd62ea1a 890 DSI_CMCR_MRDPS);
NYX 0:85b3fd62ea1a 891 hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
NYX 0:85b3fd62ea1a 892 LPCmd->LPGenShortWriteOneP |\
NYX 0:85b3fd62ea1a 893 LPCmd->LPGenShortWriteTwoP |\
NYX 0:85b3fd62ea1a 894 LPCmd->LPGenShortReadNoP |\
NYX 0:85b3fd62ea1a 895 LPCmd->LPGenShortReadOneP |\
NYX 0:85b3fd62ea1a 896 LPCmd->LPGenShortReadTwoP |\
NYX 0:85b3fd62ea1a 897 LPCmd->LPGenLongWrite |\
NYX 0:85b3fd62ea1a 898 LPCmd->LPDcsShortWriteNoP |\
NYX 0:85b3fd62ea1a 899 LPCmd->LPDcsShortWriteOneP |\
NYX 0:85b3fd62ea1a 900 LPCmd->LPDcsShortReadNoP |\
NYX 0:85b3fd62ea1a 901 LPCmd->LPDcsLongWrite |\
NYX 0:85b3fd62ea1a 902 LPCmd->LPMaxReadPacket);
NYX 0:85b3fd62ea1a 903
NYX 0:85b3fd62ea1a 904 /* Configure the acknowledge request after each packet transmission */
NYX 0:85b3fd62ea1a 905 hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
NYX 0:85b3fd62ea1a 906 hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
NYX 0:85b3fd62ea1a 907
NYX 0:85b3fd62ea1a 908 /* Process unlocked */
NYX 0:85b3fd62ea1a 909 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 910
NYX 0:85b3fd62ea1a 911 return HAL_OK;
NYX 0:85b3fd62ea1a 912 }
NYX 0:85b3fd62ea1a 913
NYX 0:85b3fd62ea1a 914 /**
NYX 0:85b3fd62ea1a 915 * @brief Configure the flow control parameters
NYX 0:85b3fd62ea1a 916 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 917 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 918 * @param FlowControl: flow control feature(s) to be enabled.
NYX 0:85b3fd62ea1a 919 * This parameter can be any combination of @ref DSI_FlowControl.
NYX 0:85b3fd62ea1a 920 * @retval HAL status
NYX 0:85b3fd62ea1a 921 */
NYX 0:85b3fd62ea1a 922 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
NYX 0:85b3fd62ea1a 923 {
NYX 0:85b3fd62ea1a 924 /* Process locked */
NYX 0:85b3fd62ea1a 925 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 926
NYX 0:85b3fd62ea1a 927 /* Check the parameters */
NYX 0:85b3fd62ea1a 928 assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
NYX 0:85b3fd62ea1a 929
NYX 0:85b3fd62ea1a 930 /* Set the DSI Host Protocol Configuration Register */
NYX 0:85b3fd62ea1a 931 hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
NYX 0:85b3fd62ea1a 932 hdsi->Instance->PCR |= FlowControl;
NYX 0:85b3fd62ea1a 933
NYX 0:85b3fd62ea1a 934 /* Process unlocked */
NYX 0:85b3fd62ea1a 935 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 936
NYX 0:85b3fd62ea1a 937 return HAL_OK;
NYX 0:85b3fd62ea1a 938 }
NYX 0:85b3fd62ea1a 939
NYX 0:85b3fd62ea1a 940 /**
NYX 0:85b3fd62ea1a 941 * @brief Configure the DSI PHY timer parameters
NYX 0:85b3fd62ea1a 942 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 943 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 944 * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
NYX 0:85b3fd62ea1a 945 * the DSI PHY timing parameters
NYX 0:85b3fd62ea1a 946 * @retval HAL status
NYX 0:85b3fd62ea1a 947 */
NYX 0:85b3fd62ea1a 948 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
NYX 0:85b3fd62ea1a 949 {
NYX 0:85b3fd62ea1a 950 uint32_t maxTime;
NYX 0:85b3fd62ea1a 951 /* Process locked */
NYX 0:85b3fd62ea1a 952 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 953
NYX 0:85b3fd62ea1a 954 maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
NYX 0:85b3fd62ea1a 955
NYX 0:85b3fd62ea1a 956 /* Clock lane timer configuration */
NYX 0:85b3fd62ea1a 957
NYX 0:85b3fd62ea1a 958 /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
NYX 0:85b3fd62ea1a 959 High-Speed transmission.
NYX 0:85b3fd62ea1a 960 To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
NYX 0:85b3fd62ea1a 961 to Low-Power and from Low-Power to High-Speed.
NYX 0:85b3fd62ea1a 962 This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
NYX 0:85b3fd62ea1a 963 But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
NYX 0:85b3fd62ea1a 964
NYX 0:85b3fd62ea1a 965 Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
NYX 0:85b3fd62ea1a 966 */
NYX 0:85b3fd62ea1a 967 hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
NYX 0:85b3fd62ea1a 968 hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U));
NYX 0:85b3fd62ea1a 969
NYX 0:85b3fd62ea1a 970 /* Data lane timer configuration */
NYX 0:85b3fd62ea1a 971 hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
NYX 0:85b3fd62ea1a 972 hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U));
NYX 0:85b3fd62ea1a 973
NYX 0:85b3fd62ea1a 974 /* Configure the wait period to request HS transmission after a stop state */
NYX 0:85b3fd62ea1a 975 hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
NYX 0:85b3fd62ea1a 976 hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U);
NYX 0:85b3fd62ea1a 977
NYX 0:85b3fd62ea1a 978 /* Process unlocked */
NYX 0:85b3fd62ea1a 979 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 980
NYX 0:85b3fd62ea1a 981 return HAL_OK;
NYX 0:85b3fd62ea1a 982 }
NYX 0:85b3fd62ea1a 983
NYX 0:85b3fd62ea1a 984 /**
NYX 0:85b3fd62ea1a 985 * @brief Configure the DSI HOST timeout parameters
NYX 0:85b3fd62ea1a 986 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 987 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 988 * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
NYX 0:85b3fd62ea1a 989 * the DSI host timeout parameters
NYX 0:85b3fd62ea1a 990 * @retval HAL status
NYX 0:85b3fd62ea1a 991 */
NYX 0:85b3fd62ea1a 992 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
NYX 0:85b3fd62ea1a 993 {
NYX 0:85b3fd62ea1a 994 /* Process locked */
NYX 0:85b3fd62ea1a 995 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 996
NYX 0:85b3fd62ea1a 997 /* Set the timeout clock division factor */
NYX 0:85b3fd62ea1a 998 hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
NYX 0:85b3fd62ea1a 999 hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U);
NYX 0:85b3fd62ea1a 1000
NYX 0:85b3fd62ea1a 1001 /* High-speed transmission timeout */
NYX 0:85b3fd62ea1a 1002 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
NYX 0:85b3fd62ea1a 1003 hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U);
NYX 0:85b3fd62ea1a 1004
NYX 0:85b3fd62ea1a 1005 /* Low-power reception timeout */
NYX 0:85b3fd62ea1a 1006 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
NYX 0:85b3fd62ea1a 1007 hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
NYX 0:85b3fd62ea1a 1008
NYX 0:85b3fd62ea1a 1009 /* High-speed read timeout */
NYX 0:85b3fd62ea1a 1010 hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
NYX 0:85b3fd62ea1a 1011 hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
NYX 0:85b3fd62ea1a 1012
NYX 0:85b3fd62ea1a 1013 /* Low-power read timeout */
NYX 0:85b3fd62ea1a 1014 hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
NYX 0:85b3fd62ea1a 1015 hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
NYX 0:85b3fd62ea1a 1016
NYX 0:85b3fd62ea1a 1017 /* High-speed write timeout */
NYX 0:85b3fd62ea1a 1018 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
NYX 0:85b3fd62ea1a 1019 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
NYX 0:85b3fd62ea1a 1020
NYX 0:85b3fd62ea1a 1021 /* High-speed write presp mode */
NYX 0:85b3fd62ea1a 1022 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
NYX 0:85b3fd62ea1a 1023 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
NYX 0:85b3fd62ea1a 1024
NYX 0:85b3fd62ea1a 1025 /* Low-speed write timeout */
NYX 0:85b3fd62ea1a 1026 hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
NYX 0:85b3fd62ea1a 1027 hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
NYX 0:85b3fd62ea1a 1028
NYX 0:85b3fd62ea1a 1029 /* BTA timeout */
NYX 0:85b3fd62ea1a 1030 hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
NYX 0:85b3fd62ea1a 1031 hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
NYX 0:85b3fd62ea1a 1032
NYX 0:85b3fd62ea1a 1033 /* Process unlocked */
NYX 0:85b3fd62ea1a 1034 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1035
NYX 0:85b3fd62ea1a 1036 return HAL_OK;
NYX 0:85b3fd62ea1a 1037 }
NYX 0:85b3fd62ea1a 1038
NYX 0:85b3fd62ea1a 1039 /**
NYX 0:85b3fd62ea1a 1040 * @brief Start the DSI module
NYX 0:85b3fd62ea1a 1041 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1042 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1043 * @retval HAL status
NYX 0:85b3fd62ea1a 1044 */
NYX 0:85b3fd62ea1a 1045 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 1046 {
NYX 0:85b3fd62ea1a 1047 /* Process locked */
NYX 0:85b3fd62ea1a 1048 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1049
NYX 0:85b3fd62ea1a 1050 /* Enable the DSI host */
NYX 0:85b3fd62ea1a 1051 __HAL_DSI_ENABLE(hdsi);
NYX 0:85b3fd62ea1a 1052
NYX 0:85b3fd62ea1a 1053 /* Enable the DSI wrapper */
NYX 0:85b3fd62ea1a 1054 __HAL_DSI_WRAPPER_ENABLE(hdsi);
NYX 0:85b3fd62ea1a 1055
NYX 0:85b3fd62ea1a 1056 /* Process unlocked */
NYX 0:85b3fd62ea1a 1057 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1058
NYX 0:85b3fd62ea1a 1059 return HAL_OK;
NYX 0:85b3fd62ea1a 1060 }
NYX 0:85b3fd62ea1a 1061
NYX 0:85b3fd62ea1a 1062 /**
NYX 0:85b3fd62ea1a 1063 * @brief Stop the DSI module
NYX 0:85b3fd62ea1a 1064 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1065 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1066 * @retval HAL status
NYX 0:85b3fd62ea1a 1067 */
NYX 0:85b3fd62ea1a 1068 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 1069 {
NYX 0:85b3fd62ea1a 1070 /* Process locked */
NYX 0:85b3fd62ea1a 1071 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1072
NYX 0:85b3fd62ea1a 1073 /* Disable the DSI host */
NYX 0:85b3fd62ea1a 1074 __HAL_DSI_DISABLE(hdsi);
NYX 0:85b3fd62ea1a 1075
NYX 0:85b3fd62ea1a 1076 /* Disable the DSI wrapper */
NYX 0:85b3fd62ea1a 1077 __HAL_DSI_WRAPPER_DISABLE(hdsi);
NYX 0:85b3fd62ea1a 1078
NYX 0:85b3fd62ea1a 1079 /* Process unlocked */
NYX 0:85b3fd62ea1a 1080 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1081
NYX 0:85b3fd62ea1a 1082 return HAL_OK;
NYX 0:85b3fd62ea1a 1083 }
NYX 0:85b3fd62ea1a 1084
NYX 0:85b3fd62ea1a 1085 /**
NYX 0:85b3fd62ea1a 1086 * @brief Refresh the display in command mode
NYX 0:85b3fd62ea1a 1087 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1088 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1089 * @retval HAL status
NYX 0:85b3fd62ea1a 1090 */
NYX 0:85b3fd62ea1a 1091 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 1092 {
NYX 0:85b3fd62ea1a 1093 /* Process locked */
NYX 0:85b3fd62ea1a 1094 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1095
NYX 0:85b3fd62ea1a 1096 /* Update the display */
NYX 0:85b3fd62ea1a 1097 hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
NYX 0:85b3fd62ea1a 1098
NYX 0:85b3fd62ea1a 1099 /* Process unlocked */
NYX 0:85b3fd62ea1a 1100 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1101
NYX 0:85b3fd62ea1a 1102 return HAL_OK;
NYX 0:85b3fd62ea1a 1103 }
NYX 0:85b3fd62ea1a 1104
NYX 0:85b3fd62ea1a 1105 /**
NYX 0:85b3fd62ea1a 1106 * @brief Controls the display color mode in Video mode
NYX 0:85b3fd62ea1a 1107 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1108 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1109 * @param ColorMode: Color mode (full or 8-colors).
NYX 0:85b3fd62ea1a 1110 * This parameter can be any value of @ref DSI_Color_Mode
NYX 0:85b3fd62ea1a 1111 * @retval HAL status
NYX 0:85b3fd62ea1a 1112 */
NYX 0:85b3fd62ea1a 1113 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
NYX 0:85b3fd62ea1a 1114 {
NYX 0:85b3fd62ea1a 1115 /* Process locked */
NYX 0:85b3fd62ea1a 1116 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1117
NYX 0:85b3fd62ea1a 1118 /* Check the parameters */
NYX 0:85b3fd62ea1a 1119 assert_param(IS_DSI_COLOR_MODE(ColorMode));
NYX 0:85b3fd62ea1a 1120
NYX 0:85b3fd62ea1a 1121 /* Update the display color mode */
NYX 0:85b3fd62ea1a 1122 hdsi->Instance->WCR &= ~DSI_WCR_COLM;
NYX 0:85b3fd62ea1a 1123 hdsi->Instance->WCR |= ColorMode;
NYX 0:85b3fd62ea1a 1124
NYX 0:85b3fd62ea1a 1125 /* Process unlocked */
NYX 0:85b3fd62ea1a 1126 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1127
NYX 0:85b3fd62ea1a 1128 return HAL_OK;
NYX 0:85b3fd62ea1a 1129 }
NYX 0:85b3fd62ea1a 1130
NYX 0:85b3fd62ea1a 1131 /**
NYX 0:85b3fd62ea1a 1132 * @brief Control the display shutdown in Video mode
NYX 0:85b3fd62ea1a 1133 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1134 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1135 * @param Shutdown: Shut-down (Display-ON or Display-OFF).
NYX 0:85b3fd62ea1a 1136 * This parameter can be any value of @ref DSI_ShutDown
NYX 0:85b3fd62ea1a 1137 * @retval HAL status
NYX 0:85b3fd62ea1a 1138 */
NYX 0:85b3fd62ea1a 1139 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
NYX 0:85b3fd62ea1a 1140 {
NYX 0:85b3fd62ea1a 1141 /* Process locked */
NYX 0:85b3fd62ea1a 1142 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1143
NYX 0:85b3fd62ea1a 1144 /* Check the parameters */
NYX 0:85b3fd62ea1a 1145 assert_param(IS_DSI_SHUT_DOWN(Shutdown));
NYX 0:85b3fd62ea1a 1146
NYX 0:85b3fd62ea1a 1147 /* Update the display Shutdown */
NYX 0:85b3fd62ea1a 1148 hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
NYX 0:85b3fd62ea1a 1149 hdsi->Instance->WCR |= Shutdown;
NYX 0:85b3fd62ea1a 1150
NYX 0:85b3fd62ea1a 1151 /* Process unlocked */
NYX 0:85b3fd62ea1a 1152 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1153
NYX 0:85b3fd62ea1a 1154 return HAL_OK;
NYX 0:85b3fd62ea1a 1155 }
NYX 0:85b3fd62ea1a 1156
NYX 0:85b3fd62ea1a 1157 /**
NYX 0:85b3fd62ea1a 1158 * @brief DCS or Generic short write command
NYX 0:85b3fd62ea1a 1159 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1160 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1161 * @param ChannelID: Virtual channel ID.
NYX 0:85b3fd62ea1a 1162 * @param Mode: DSI short packet data type.
NYX 0:85b3fd62ea1a 1163 * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
NYX 0:85b3fd62ea1a 1164 * @param Param1: DSC command or first generic parameter.
NYX 0:85b3fd62ea1a 1165 * This parameter can be any value of @ref DSI_DCS_Command or a
NYX 0:85b3fd62ea1a 1166 * generic command code.
NYX 0:85b3fd62ea1a 1167 * @param Param2: DSC parameter or second generic parameter.
NYX 0:85b3fd62ea1a 1168 * @retval HAL status
NYX 0:85b3fd62ea1a 1169 */
NYX 0:85b3fd62ea1a 1170 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
NYX 0:85b3fd62ea1a 1171 uint32_t ChannelID,
NYX 0:85b3fd62ea1a 1172 uint32_t Mode,
NYX 0:85b3fd62ea1a 1173 uint32_t Param1,
NYX 0:85b3fd62ea1a 1174 uint32_t Param2)
NYX 0:85b3fd62ea1a 1175 {
NYX 0:85b3fd62ea1a 1176 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1177
NYX 0:85b3fd62ea1a 1178 /* Process locked */
NYX 0:85b3fd62ea1a 1179 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1180
NYX 0:85b3fd62ea1a 1181 /* Check the parameters */
NYX 0:85b3fd62ea1a 1182 assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
NYX 0:85b3fd62ea1a 1183
NYX 0:85b3fd62ea1a 1184 /* Get tick */
NYX 0:85b3fd62ea1a 1185 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1186
NYX 0:85b3fd62ea1a 1187 /* Wait for Command FIFO Empty */
NYX 0:85b3fd62ea1a 1188 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
NYX 0:85b3fd62ea1a 1189 {
NYX 0:85b3fd62ea1a 1190 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1191 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1192 {
NYX 0:85b3fd62ea1a 1193 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1194 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1195
NYX 0:85b3fd62ea1a 1196 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1197 }
NYX 0:85b3fd62ea1a 1198 }
NYX 0:85b3fd62ea1a 1199
NYX 0:85b3fd62ea1a 1200 /* Configure the packet to send a short DCS command with 0 or 1 parameter */
NYX 0:85b3fd62ea1a 1201 DSI_ConfigPacketHeader(hdsi->Instance,
NYX 0:85b3fd62ea1a 1202 ChannelID,
NYX 0:85b3fd62ea1a 1203 Mode,
NYX 0:85b3fd62ea1a 1204 Param1,
NYX 0:85b3fd62ea1a 1205 Param2);
NYX 0:85b3fd62ea1a 1206
NYX 0:85b3fd62ea1a 1207 /* Process unlocked */
NYX 0:85b3fd62ea1a 1208 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1209
NYX 0:85b3fd62ea1a 1210 return HAL_OK;
NYX 0:85b3fd62ea1a 1211 }
NYX 0:85b3fd62ea1a 1212
NYX 0:85b3fd62ea1a 1213 /**
NYX 0:85b3fd62ea1a 1214 * @brief DCS or Generic long write command
NYX 0:85b3fd62ea1a 1215 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1216 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1217 * @param ChannelID: Virtual channel ID.
NYX 0:85b3fd62ea1a 1218 * @param Mode: DSI long packet data type.
NYX 0:85b3fd62ea1a 1219 * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
NYX 0:85b3fd62ea1a 1220 * @param NbParams: Number of parameters.
NYX 0:85b3fd62ea1a 1221 * @param Param1: DSC command or first generic parameter.
NYX 0:85b3fd62ea1a 1222 * This parameter can be any value of @ref DSI_DCS_Command or a
NYX 0:85b3fd62ea1a 1223 * generic command code
NYX 0:85b3fd62ea1a 1224 * @param ParametersTable: Pointer to parameter values table.
NYX 0:85b3fd62ea1a 1225 * @retval HAL status
NYX 0:85b3fd62ea1a 1226 */
NYX 0:85b3fd62ea1a 1227 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
NYX 0:85b3fd62ea1a 1228 uint32_t ChannelID,
NYX 0:85b3fd62ea1a 1229 uint32_t Mode,
NYX 0:85b3fd62ea1a 1230 uint32_t NbParams,
NYX 0:85b3fd62ea1a 1231 uint32_t Param1,
NYX 0:85b3fd62ea1a 1232 uint8_t* ParametersTable)
NYX 0:85b3fd62ea1a 1233 {
NYX 0:85b3fd62ea1a 1234 uint32_t uicounter = 0U, nbBytes = 0U, count = 0U;
NYX 0:85b3fd62ea1a 1235 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1236 uint32_t fifoword = 0U;
NYX 0:85b3fd62ea1a 1237
NYX 0:85b3fd62ea1a 1238 /* Process locked */
NYX 0:85b3fd62ea1a 1239 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1240
NYX 0:85b3fd62ea1a 1241 /* Check the parameters */
NYX 0:85b3fd62ea1a 1242 assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
NYX 0:85b3fd62ea1a 1243
NYX 0:85b3fd62ea1a 1244 /* Get tick */
NYX 0:85b3fd62ea1a 1245 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1246
NYX 0:85b3fd62ea1a 1247 /* Wait for Command FIFO Empty */
NYX 0:85b3fd62ea1a 1248 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
NYX 0:85b3fd62ea1a 1249 {
NYX 0:85b3fd62ea1a 1250 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1251 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1252 {
NYX 0:85b3fd62ea1a 1253 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1254 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1255
NYX 0:85b3fd62ea1a 1256 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1257 }
NYX 0:85b3fd62ea1a 1258 }
NYX 0:85b3fd62ea1a 1259
NYX 0:85b3fd62ea1a 1260 /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
NYX 0:85b3fd62ea1a 1261 fifoword = Param1;
NYX 0:85b3fd62ea1a 1262 nbBytes = (NbParams < 3U) ? NbParams : 3U;
NYX 0:85b3fd62ea1a 1263
NYX 0:85b3fd62ea1a 1264 for(count = 0U; count < nbBytes; count++)
NYX 0:85b3fd62ea1a 1265 {
NYX 0:85b3fd62ea1a 1266 fifoword |= (((uint32_t)(*(ParametersTable + count))) << (8U + (8U*count)));
NYX 0:85b3fd62ea1a 1267 }
NYX 0:85b3fd62ea1a 1268 hdsi->Instance->GPDR = fifoword;
NYX 0:85b3fd62ea1a 1269
NYX 0:85b3fd62ea1a 1270 uicounter = NbParams - nbBytes;
NYX 0:85b3fd62ea1a 1271 ParametersTable += nbBytes;
NYX 0:85b3fd62ea1a 1272 /* Set the Next parameters on the write FIFO command*/
NYX 0:85b3fd62ea1a 1273 while(uicounter != 0U)
NYX 0:85b3fd62ea1a 1274 {
NYX 0:85b3fd62ea1a 1275 nbBytes = (uicounter < 4U) ? uicounter : 4U;
NYX 0:85b3fd62ea1a 1276 fifoword = 0U;
NYX 0:85b3fd62ea1a 1277 for(count = 0U; count < nbBytes; count++)
NYX 0:85b3fd62ea1a 1278 {
NYX 0:85b3fd62ea1a 1279 fifoword |= (((uint32_t)(*(ParametersTable + count))) << (8U*count));
NYX 0:85b3fd62ea1a 1280 }
NYX 0:85b3fd62ea1a 1281 hdsi->Instance->GPDR = fifoword;
NYX 0:85b3fd62ea1a 1282
NYX 0:85b3fd62ea1a 1283 uicounter -= nbBytes;
NYX 0:85b3fd62ea1a 1284 ParametersTable += nbBytes;
NYX 0:85b3fd62ea1a 1285 }
NYX 0:85b3fd62ea1a 1286
NYX 0:85b3fd62ea1a 1287 /* Configure the packet to send a long DCS command */
NYX 0:85b3fd62ea1a 1288 DSI_ConfigPacketHeader(hdsi->Instance,
NYX 0:85b3fd62ea1a 1289 ChannelID,
NYX 0:85b3fd62ea1a 1290 Mode,
NYX 0:85b3fd62ea1a 1291 ((NbParams+1U)&0x00FFU),
NYX 0:85b3fd62ea1a 1292 (((NbParams+1U)&0xFF00U)>>8U));
NYX 0:85b3fd62ea1a 1293
NYX 0:85b3fd62ea1a 1294 /* Process unlocked */
NYX 0:85b3fd62ea1a 1295 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1296
NYX 0:85b3fd62ea1a 1297 return HAL_OK;
NYX 0:85b3fd62ea1a 1298 }
NYX 0:85b3fd62ea1a 1299
NYX 0:85b3fd62ea1a 1300 /**
NYX 0:85b3fd62ea1a 1301 * @brief Read command (DCS or generic)
NYX 0:85b3fd62ea1a 1302 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1303 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1304 * @param ChannelNbr: Virtual channel ID
NYX 0:85b3fd62ea1a 1305 * @param Array: pointer to a buffer to store the payload of a read back operation.
NYX 0:85b3fd62ea1a 1306 * @param Size: Data size to be read (in byte).
NYX 0:85b3fd62ea1a 1307 * @param Mode: DSI read packet data type.
NYX 0:85b3fd62ea1a 1308 * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
NYX 0:85b3fd62ea1a 1309 * @param DCSCmd: DCS get/read command.
NYX 0:85b3fd62ea1a 1310 * @param ParametersTable: Pointer to parameter values table.
NYX 0:85b3fd62ea1a 1311 * @retval HAL status
NYX 0:85b3fd62ea1a 1312 */
NYX 0:85b3fd62ea1a 1313 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
NYX 0:85b3fd62ea1a 1314 uint32_t ChannelNbr,
NYX 0:85b3fd62ea1a 1315 uint8_t* Array,
NYX 0:85b3fd62ea1a 1316 uint32_t Size,
NYX 0:85b3fd62ea1a 1317 uint32_t Mode,
NYX 0:85b3fd62ea1a 1318 uint32_t DCSCmd,
NYX 0:85b3fd62ea1a 1319 uint8_t* ParametersTable)
NYX 0:85b3fd62ea1a 1320 {
NYX 0:85b3fd62ea1a 1321 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1322
NYX 0:85b3fd62ea1a 1323 /* Process locked */
NYX 0:85b3fd62ea1a 1324 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1325
NYX 0:85b3fd62ea1a 1326 /* Check the parameters */
NYX 0:85b3fd62ea1a 1327 assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
NYX 0:85b3fd62ea1a 1328
NYX 0:85b3fd62ea1a 1329 if(Size > 2U)
NYX 0:85b3fd62ea1a 1330 {
NYX 0:85b3fd62ea1a 1331 /* set max return packet size */
NYX 0:85b3fd62ea1a 1332 HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFFU), (((Size)>>8U)&0xFFU));
NYX 0:85b3fd62ea1a 1333 }
NYX 0:85b3fd62ea1a 1334
NYX 0:85b3fd62ea1a 1335 /* Configure the packet to read command */
NYX 0:85b3fd62ea1a 1336 if (Mode == DSI_DCS_SHORT_PKT_READ)
NYX 0:85b3fd62ea1a 1337 {
NYX 0:85b3fd62ea1a 1338 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
NYX 0:85b3fd62ea1a 1339 }
NYX 0:85b3fd62ea1a 1340 else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
NYX 0:85b3fd62ea1a 1341 {
NYX 0:85b3fd62ea1a 1342 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
NYX 0:85b3fd62ea1a 1343 }
NYX 0:85b3fd62ea1a 1344 else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
NYX 0:85b3fd62ea1a 1345 {
NYX 0:85b3fd62ea1a 1346 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
NYX 0:85b3fd62ea1a 1347 }
NYX 0:85b3fd62ea1a 1348 else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
NYX 0:85b3fd62ea1a 1349 {
NYX 0:85b3fd62ea1a 1350 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
NYX 0:85b3fd62ea1a 1351 }
NYX 0:85b3fd62ea1a 1352 else
NYX 0:85b3fd62ea1a 1353 {
NYX 0:85b3fd62ea1a 1354 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1355 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1356
NYX 0:85b3fd62ea1a 1357 return HAL_ERROR;
NYX 0:85b3fd62ea1a 1358 }
NYX 0:85b3fd62ea1a 1359
NYX 0:85b3fd62ea1a 1360 /* Get tick */
NYX 0:85b3fd62ea1a 1361 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1362
NYX 0:85b3fd62ea1a 1363 /* Check that the payload read FIFO is not empty */
NYX 0:85b3fd62ea1a 1364 while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
NYX 0:85b3fd62ea1a 1365 {
NYX 0:85b3fd62ea1a 1366 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1367 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1368 {
NYX 0:85b3fd62ea1a 1369 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1370 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1371
NYX 0:85b3fd62ea1a 1372 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1373 }
NYX 0:85b3fd62ea1a 1374 }
NYX 0:85b3fd62ea1a 1375
NYX 0:85b3fd62ea1a 1376 /* Get the first byte */
NYX 0:85b3fd62ea1a 1377 *((uint32_t *)Array) = (hdsi->Instance->GPDR);
NYX 0:85b3fd62ea1a 1378 if (Size > 4U)
NYX 0:85b3fd62ea1a 1379 {
NYX 0:85b3fd62ea1a 1380 Size -= 4U;
NYX 0:85b3fd62ea1a 1381 Array += 4U;
NYX 0:85b3fd62ea1a 1382 }
NYX 0:85b3fd62ea1a 1383 else
NYX 0:85b3fd62ea1a 1384 {
NYX 0:85b3fd62ea1a 1385 /* Process unlocked */
NYX 0:85b3fd62ea1a 1386 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1387
NYX 0:85b3fd62ea1a 1388 return HAL_OK;
NYX 0:85b3fd62ea1a 1389 }
NYX 0:85b3fd62ea1a 1390
NYX 0:85b3fd62ea1a 1391 /* Get tick */
NYX 0:85b3fd62ea1a 1392 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1393
NYX 0:85b3fd62ea1a 1394 /* Get the remaining bytes if any */
NYX 0:85b3fd62ea1a 1395 while(((int)(Size)) > 0U)
NYX 0:85b3fd62ea1a 1396 {
NYX 0:85b3fd62ea1a 1397 if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
NYX 0:85b3fd62ea1a 1398 {
NYX 0:85b3fd62ea1a 1399 *((uint32_t *)Array) = (hdsi->Instance->GPDR);
NYX 0:85b3fd62ea1a 1400 Size -= 4U;
NYX 0:85b3fd62ea1a 1401 Array += 4U;
NYX 0:85b3fd62ea1a 1402 }
NYX 0:85b3fd62ea1a 1403
NYX 0:85b3fd62ea1a 1404 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1405 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1406 {
NYX 0:85b3fd62ea1a 1407 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1408 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1409
NYX 0:85b3fd62ea1a 1410 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1411 }
NYX 0:85b3fd62ea1a 1412 }
NYX 0:85b3fd62ea1a 1413
NYX 0:85b3fd62ea1a 1414 /* Process unlocked */
NYX 0:85b3fd62ea1a 1415 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1416
NYX 0:85b3fd62ea1a 1417 return HAL_OK;
NYX 0:85b3fd62ea1a 1418 }
NYX 0:85b3fd62ea1a 1419
NYX 0:85b3fd62ea1a 1420 /**
NYX 0:85b3fd62ea1a 1421 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
NYX 0:85b3fd62ea1a 1422 * (only data lanes are in ULPM)
NYX 0:85b3fd62ea1a 1423 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1424 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1425 * @retval HAL status
NYX 0:85b3fd62ea1a 1426 */
NYX 0:85b3fd62ea1a 1427 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 1428 {
NYX 0:85b3fd62ea1a 1429 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1430
NYX 0:85b3fd62ea1a 1431 /* Process locked */
NYX 0:85b3fd62ea1a 1432 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1433
NYX 0:85b3fd62ea1a 1434 /* ULPS Request on Data Lanes */
NYX 0:85b3fd62ea1a 1435 hdsi->Instance->PUCR |= DSI_PUCR_URDL;
NYX 0:85b3fd62ea1a 1436
NYX 0:85b3fd62ea1a 1437 /* Get tick */
NYX 0:85b3fd62ea1a 1438 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1439
NYX 0:85b3fd62ea1a 1440 /* Wait until the D-PHY active lanes enter into ULPM */
NYX 0:85b3fd62ea1a 1441 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
NYX 0:85b3fd62ea1a 1442 {
NYX 0:85b3fd62ea1a 1443 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
NYX 0:85b3fd62ea1a 1444 {
NYX 0:85b3fd62ea1a 1445 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1446 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1447 {
NYX 0:85b3fd62ea1a 1448 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1449 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1450
NYX 0:85b3fd62ea1a 1451 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1452 }
NYX 0:85b3fd62ea1a 1453 }
NYX 0:85b3fd62ea1a 1454 }
NYX 0:85b3fd62ea1a 1455 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
NYX 0:85b3fd62ea1a 1456 {
NYX 0:85b3fd62ea1a 1457 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
NYX 0:85b3fd62ea1a 1458 {
NYX 0:85b3fd62ea1a 1459 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1460 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1461 {
NYX 0:85b3fd62ea1a 1462 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1463 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1464
NYX 0:85b3fd62ea1a 1465 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1466 }
NYX 0:85b3fd62ea1a 1467 }
NYX 0:85b3fd62ea1a 1468 }
NYX 0:85b3fd62ea1a 1469
NYX 0:85b3fd62ea1a 1470 /* Process unlocked */
NYX 0:85b3fd62ea1a 1471 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1472
NYX 0:85b3fd62ea1a 1473 return HAL_OK;
NYX 0:85b3fd62ea1a 1474 }
NYX 0:85b3fd62ea1a 1475
NYX 0:85b3fd62ea1a 1476 /**
NYX 0:85b3fd62ea1a 1477 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
NYX 0:85b3fd62ea1a 1478 * (only data lanes are in ULPM)
NYX 0:85b3fd62ea1a 1479 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1480 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1481 * @retval HAL status
NYX 0:85b3fd62ea1a 1482 */
NYX 0:85b3fd62ea1a 1483 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 1484 {
NYX 0:85b3fd62ea1a 1485 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1486
NYX 0:85b3fd62ea1a 1487 /* Process locked */
NYX 0:85b3fd62ea1a 1488 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1489
NYX 0:85b3fd62ea1a 1490 /* Exit ULPS on Data Lanes */
NYX 0:85b3fd62ea1a 1491 hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
NYX 0:85b3fd62ea1a 1492
NYX 0:85b3fd62ea1a 1493 /* Get tick */
NYX 0:85b3fd62ea1a 1494 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1495
NYX 0:85b3fd62ea1a 1496 /* Wait until all active lanes exit ULPM */
NYX 0:85b3fd62ea1a 1497 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
NYX 0:85b3fd62ea1a 1498 {
NYX 0:85b3fd62ea1a 1499 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
NYX 0:85b3fd62ea1a 1500 {
NYX 0:85b3fd62ea1a 1501 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1502 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1503 {
NYX 0:85b3fd62ea1a 1504 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1505 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1506
NYX 0:85b3fd62ea1a 1507 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1508 }
NYX 0:85b3fd62ea1a 1509 }
NYX 0:85b3fd62ea1a 1510 }
NYX 0:85b3fd62ea1a 1511 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
NYX 0:85b3fd62ea1a 1512 {
NYX 0:85b3fd62ea1a 1513 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
NYX 0:85b3fd62ea1a 1514 {
NYX 0:85b3fd62ea1a 1515 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1516 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1517 {
NYX 0:85b3fd62ea1a 1518 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1519 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1520
NYX 0:85b3fd62ea1a 1521 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1522 }
NYX 0:85b3fd62ea1a 1523 }
NYX 0:85b3fd62ea1a 1524 }
NYX 0:85b3fd62ea1a 1525
NYX 0:85b3fd62ea1a 1526 /* wait for 1 ms*/
NYX 0:85b3fd62ea1a 1527 HAL_Delay(1U);
NYX 0:85b3fd62ea1a 1528
NYX 0:85b3fd62ea1a 1529 /* De-assert the ULPM requests and the ULPM exit bits */
NYX 0:85b3fd62ea1a 1530 hdsi->Instance->PUCR = 0U;
NYX 0:85b3fd62ea1a 1531
NYX 0:85b3fd62ea1a 1532 /* Process unlocked */
NYX 0:85b3fd62ea1a 1533 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1534
NYX 0:85b3fd62ea1a 1535 return HAL_OK;
NYX 0:85b3fd62ea1a 1536 }
NYX 0:85b3fd62ea1a 1537
NYX 0:85b3fd62ea1a 1538 /**
NYX 0:85b3fd62ea1a 1539 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
NYX 0:85b3fd62ea1a 1540 * (both data and clock lanes are in ULPM)
NYX 0:85b3fd62ea1a 1541 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1542 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1543 * @retval HAL status
NYX 0:85b3fd62ea1a 1544 */
NYX 0:85b3fd62ea1a 1545 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 1546 {
NYX 0:85b3fd62ea1a 1547 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1548
NYX 0:85b3fd62ea1a 1549 /* Process locked */
NYX 0:85b3fd62ea1a 1550 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1551
NYX 0:85b3fd62ea1a 1552 /* Clock lane configuration: no more HS request */
NYX 0:85b3fd62ea1a 1553 hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
NYX 0:85b3fd62ea1a 1554
NYX 0:85b3fd62ea1a 1555 /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
NYX 0:85b3fd62ea1a 1556 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
NYX 0:85b3fd62ea1a 1557
NYX 0:85b3fd62ea1a 1558 /* ULPS Request on Clock and Data Lanes */
NYX 0:85b3fd62ea1a 1559 hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
NYX 0:85b3fd62ea1a 1560
NYX 0:85b3fd62ea1a 1561 /* Get tick */
NYX 0:85b3fd62ea1a 1562 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1563
NYX 0:85b3fd62ea1a 1564 /* Wait until all active lanes exit ULPM */
NYX 0:85b3fd62ea1a 1565 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
NYX 0:85b3fd62ea1a 1566 {
NYX 0:85b3fd62ea1a 1567 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
NYX 0:85b3fd62ea1a 1568 {
NYX 0:85b3fd62ea1a 1569 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1570 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1571 {
NYX 0:85b3fd62ea1a 1572 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1573 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1574
NYX 0:85b3fd62ea1a 1575 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1576 }
NYX 0:85b3fd62ea1a 1577 }
NYX 0:85b3fd62ea1a 1578 }
NYX 0:85b3fd62ea1a 1579 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
NYX 0:85b3fd62ea1a 1580 {
NYX 0:85b3fd62ea1a 1581 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
NYX 0:85b3fd62ea1a 1582 {
NYX 0:85b3fd62ea1a 1583 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1584 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1585 {
NYX 0:85b3fd62ea1a 1586 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1587 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1588
NYX 0:85b3fd62ea1a 1589 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1590 }
NYX 0:85b3fd62ea1a 1591 }
NYX 0:85b3fd62ea1a 1592 }
NYX 0:85b3fd62ea1a 1593
NYX 0:85b3fd62ea1a 1594 /* Turn off the DSI PLL */
NYX 0:85b3fd62ea1a 1595 __HAL_DSI_PLL_DISABLE(hdsi);
NYX 0:85b3fd62ea1a 1596
NYX 0:85b3fd62ea1a 1597 /* Process unlocked */
NYX 0:85b3fd62ea1a 1598 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1599
NYX 0:85b3fd62ea1a 1600 return HAL_OK;
NYX 0:85b3fd62ea1a 1601 }
NYX 0:85b3fd62ea1a 1602
NYX 0:85b3fd62ea1a 1603 /**
NYX 0:85b3fd62ea1a 1604 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
NYX 0:85b3fd62ea1a 1605 * (both data and clock lanes are in ULPM)
NYX 0:85b3fd62ea1a 1606 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1607 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1608 * @retval HAL status
NYX 0:85b3fd62ea1a 1609 */
NYX 0:85b3fd62ea1a 1610 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 1611 {
NYX 0:85b3fd62ea1a 1612 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1613
NYX 0:85b3fd62ea1a 1614 /* Process locked */
NYX 0:85b3fd62ea1a 1615 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1616
NYX 0:85b3fd62ea1a 1617 /* Turn on the DSI PLL */
NYX 0:85b3fd62ea1a 1618 __HAL_DSI_PLL_ENABLE(hdsi);
NYX 0:85b3fd62ea1a 1619
NYX 0:85b3fd62ea1a 1620 /* Get tick */
NYX 0:85b3fd62ea1a 1621 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1622
NYX 0:85b3fd62ea1a 1623 /* Wait for the lock of the PLL */
NYX 0:85b3fd62ea1a 1624 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
NYX 0:85b3fd62ea1a 1625 {
NYX 0:85b3fd62ea1a 1626 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1627 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1628 {
NYX 0:85b3fd62ea1a 1629 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1630 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1631
NYX 0:85b3fd62ea1a 1632 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1633 }
NYX 0:85b3fd62ea1a 1634 }
NYX 0:85b3fd62ea1a 1635
NYX 0:85b3fd62ea1a 1636 /* Exit ULPS on Clock and Data Lanes */
NYX 0:85b3fd62ea1a 1637 hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
NYX 0:85b3fd62ea1a 1638
NYX 0:85b3fd62ea1a 1639 /* Get tick */
NYX 0:85b3fd62ea1a 1640 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1641
NYX 0:85b3fd62ea1a 1642 /* Wait until all active lanes exit ULPM */
NYX 0:85b3fd62ea1a 1643 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
NYX 0:85b3fd62ea1a 1644 {
NYX 0:85b3fd62ea1a 1645 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
NYX 0:85b3fd62ea1a 1646 {
NYX 0:85b3fd62ea1a 1647 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1648 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1649 {
NYX 0:85b3fd62ea1a 1650 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1651 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1652
NYX 0:85b3fd62ea1a 1653 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1654 }
NYX 0:85b3fd62ea1a 1655 }
NYX 0:85b3fd62ea1a 1656 }
NYX 0:85b3fd62ea1a 1657 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
NYX 0:85b3fd62ea1a 1658 {
NYX 0:85b3fd62ea1a 1659 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
NYX 0:85b3fd62ea1a 1660 {
NYX 0:85b3fd62ea1a 1661 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1662 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
NYX 0:85b3fd62ea1a 1663 {
NYX 0:85b3fd62ea1a 1664 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1665 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1666
NYX 0:85b3fd62ea1a 1667 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1668 }
NYX 0:85b3fd62ea1a 1669 }
NYX 0:85b3fd62ea1a 1670 }
NYX 0:85b3fd62ea1a 1671
NYX 0:85b3fd62ea1a 1672 /* wait for 1 ms*/
NYX 0:85b3fd62ea1a 1673 HAL_Delay(1U);
NYX 0:85b3fd62ea1a 1674
NYX 0:85b3fd62ea1a 1675 /* De-assert the ULPM requests and the ULPM exit bits */
NYX 0:85b3fd62ea1a 1676 hdsi->Instance->PUCR = 0U;
NYX 0:85b3fd62ea1a 1677
NYX 0:85b3fd62ea1a 1678 /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
NYX 0:85b3fd62ea1a 1679 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
NYX 0:85b3fd62ea1a 1680
NYX 0:85b3fd62ea1a 1681 /* Restore clock lane configuration to HS */
NYX 0:85b3fd62ea1a 1682 hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
NYX 0:85b3fd62ea1a 1683
NYX 0:85b3fd62ea1a 1684 /* Process unlocked */
NYX 0:85b3fd62ea1a 1685 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1686
NYX 0:85b3fd62ea1a 1687 return HAL_OK;
NYX 0:85b3fd62ea1a 1688 }
NYX 0:85b3fd62ea1a 1689
NYX 0:85b3fd62ea1a 1690 /**
NYX 0:85b3fd62ea1a 1691 * @brief Start test pattern generation
NYX 0:85b3fd62ea1a 1692 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1693 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1694 * @param Mode: Pattern generator mode
NYX 0:85b3fd62ea1a 1695 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1696 * 0 : Color bars (horizontal or vertical)
NYX 0:85b3fd62ea1a 1697 * 1 : BER pattern (vertical only)
NYX 0:85b3fd62ea1a 1698 * @param Orientation: Pattern generator orientation
NYX 0:85b3fd62ea1a 1699 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1700 * 0 : Vertical color bars
NYX 0:85b3fd62ea1a 1701 * 1 : Horizontal color bars
NYX 0:85b3fd62ea1a 1702 * @retval HAL status
NYX 0:85b3fd62ea1a 1703 */
NYX 0:85b3fd62ea1a 1704 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
NYX 0:85b3fd62ea1a 1705 {
NYX 0:85b3fd62ea1a 1706 /* Process locked */
NYX 0:85b3fd62ea1a 1707 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1708
NYX 0:85b3fd62ea1a 1709 /* Configure pattern generator mode and orientation */
NYX 0:85b3fd62ea1a 1710 hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
NYX 0:85b3fd62ea1a 1711 hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U));
NYX 0:85b3fd62ea1a 1712
NYX 0:85b3fd62ea1a 1713 /* Enable pattern generator by setting PGE bit */
NYX 0:85b3fd62ea1a 1714 hdsi->Instance->VMCR |= DSI_VMCR_PGE;
NYX 0:85b3fd62ea1a 1715
NYX 0:85b3fd62ea1a 1716 /* Process unlocked */
NYX 0:85b3fd62ea1a 1717 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1718
NYX 0:85b3fd62ea1a 1719 return HAL_OK;
NYX 0:85b3fd62ea1a 1720 }
NYX 0:85b3fd62ea1a 1721
NYX 0:85b3fd62ea1a 1722 /**
NYX 0:85b3fd62ea1a 1723 * @brief Stop test pattern generation
NYX 0:85b3fd62ea1a 1724 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1725 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1726 * @retval HAL status
NYX 0:85b3fd62ea1a 1727 */
NYX 0:85b3fd62ea1a 1728 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 1729 {
NYX 0:85b3fd62ea1a 1730 /* Process locked */
NYX 0:85b3fd62ea1a 1731 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1732
NYX 0:85b3fd62ea1a 1733 /* Disable pattern generator by clearing PGE bit */
NYX 0:85b3fd62ea1a 1734 hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
NYX 0:85b3fd62ea1a 1735
NYX 0:85b3fd62ea1a 1736 /* Process unlocked */
NYX 0:85b3fd62ea1a 1737 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1738
NYX 0:85b3fd62ea1a 1739 return HAL_OK;
NYX 0:85b3fd62ea1a 1740 }
NYX 0:85b3fd62ea1a 1741
NYX 0:85b3fd62ea1a 1742 /**
NYX 0:85b3fd62ea1a 1743 * @brief Set Slew-Rate And Delay Tuning
NYX 0:85b3fd62ea1a 1744 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1745 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1746 * @param CommDelay: Communication delay to be adjusted.
NYX 0:85b3fd62ea1a 1747 * This parameter can be any value of @ref DSI_Communication_Delay
NYX 0:85b3fd62ea1a 1748 * @param Lane: select between clock or data lanes.
NYX 0:85b3fd62ea1a 1749 * This parameter can be any value of @ref DSI_Lane_Group
NYX 0:85b3fd62ea1a 1750 * @param Value: Custom value of the slew-rate or delay
NYX 0:85b3fd62ea1a 1751 * @retval HAL status
NYX 0:85b3fd62ea1a 1752 */
NYX 0:85b3fd62ea1a 1753 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
NYX 0:85b3fd62ea1a 1754 {
NYX 0:85b3fd62ea1a 1755 /* Process locked */
NYX 0:85b3fd62ea1a 1756 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1757
NYX 0:85b3fd62ea1a 1758 /* Check function parameters */
NYX 0:85b3fd62ea1a 1759 assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
NYX 0:85b3fd62ea1a 1760 assert_param(IS_DSI_LANE_GROUP(Lane));
NYX 0:85b3fd62ea1a 1761
NYX 0:85b3fd62ea1a 1762 switch(CommDelay)
NYX 0:85b3fd62ea1a 1763 {
NYX 0:85b3fd62ea1a 1764 case DSI_SLEW_RATE_HSTX:
NYX 0:85b3fd62ea1a 1765 if(Lane == DSI_CLOCK_LANE)
NYX 0:85b3fd62ea1a 1766 {
NYX 0:85b3fd62ea1a 1767 /* High-Speed Transmission Slew Rate Control on Clock Lane */
NYX 0:85b3fd62ea1a 1768 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
NYX 0:85b3fd62ea1a 1769 hdsi->Instance->WPCR[1U] |= Value<<16U;
NYX 0:85b3fd62ea1a 1770 }
NYX 0:85b3fd62ea1a 1771 else if(Lane == DSI_DATA_LANES)
NYX 0:85b3fd62ea1a 1772 {
NYX 0:85b3fd62ea1a 1773 /* High-Speed Transmission Slew Rate Control on Data Lanes */
NYX 0:85b3fd62ea1a 1774 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
NYX 0:85b3fd62ea1a 1775 hdsi->Instance->WPCR[1U] |= Value<<18U;
NYX 0:85b3fd62ea1a 1776 }
NYX 0:85b3fd62ea1a 1777 break;
NYX 0:85b3fd62ea1a 1778 case DSI_SLEW_RATE_LPTX:
NYX 0:85b3fd62ea1a 1779 if(Lane == DSI_CLOCK_LANE)
NYX 0:85b3fd62ea1a 1780 {
NYX 0:85b3fd62ea1a 1781 /* Low-Power transmission Slew Rate Compensation on Clock Lane */
NYX 0:85b3fd62ea1a 1782 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
NYX 0:85b3fd62ea1a 1783 hdsi->Instance->WPCR[1U] |= Value<<6U;
NYX 0:85b3fd62ea1a 1784 }
NYX 0:85b3fd62ea1a 1785 else if(Lane == DSI_DATA_LANES)
NYX 0:85b3fd62ea1a 1786 {
NYX 0:85b3fd62ea1a 1787 /* Low-Power transmission Slew Rate Compensation on Data Lanes */
NYX 0:85b3fd62ea1a 1788 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
NYX 0:85b3fd62ea1a 1789 hdsi->Instance->WPCR[1U] |= Value<<8U;
NYX 0:85b3fd62ea1a 1790 }
NYX 0:85b3fd62ea1a 1791 break;
NYX 0:85b3fd62ea1a 1792 case DSI_HS_DELAY:
NYX 0:85b3fd62ea1a 1793 if(Lane == DSI_CLOCK_LANE)
NYX 0:85b3fd62ea1a 1794 {
NYX 0:85b3fd62ea1a 1795 /* High-Speed Transmission Delay on Clock Lane */
NYX 0:85b3fd62ea1a 1796 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
NYX 0:85b3fd62ea1a 1797 hdsi->Instance->WPCR[1U] |= Value;
NYX 0:85b3fd62ea1a 1798 }
NYX 0:85b3fd62ea1a 1799 else if(Lane == DSI_DATA_LANES)
NYX 0:85b3fd62ea1a 1800 {
NYX 0:85b3fd62ea1a 1801 /* High-Speed Transmission Delay on Data Lanes */
NYX 0:85b3fd62ea1a 1802 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
NYX 0:85b3fd62ea1a 1803 hdsi->Instance->WPCR[1U] |= Value<<2U;
NYX 0:85b3fd62ea1a 1804 }
NYX 0:85b3fd62ea1a 1805 break;
NYX 0:85b3fd62ea1a 1806 default:
NYX 0:85b3fd62ea1a 1807 break;
NYX 0:85b3fd62ea1a 1808 }
NYX 0:85b3fd62ea1a 1809
NYX 0:85b3fd62ea1a 1810 /* Process unlocked */
NYX 0:85b3fd62ea1a 1811 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1812
NYX 0:85b3fd62ea1a 1813 return HAL_OK;
NYX 0:85b3fd62ea1a 1814 }
NYX 0:85b3fd62ea1a 1815
NYX 0:85b3fd62ea1a 1816 /**
NYX 0:85b3fd62ea1a 1817 * @brief Low-Power Reception Filter Tuning
NYX 0:85b3fd62ea1a 1818 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1819 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1820 * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
NYX 0:85b3fd62ea1a 1821 * @retval HAL status
NYX 0:85b3fd62ea1a 1822 */
NYX 0:85b3fd62ea1a 1823 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
NYX 0:85b3fd62ea1a 1824 {
NYX 0:85b3fd62ea1a 1825 /* Process locked */
NYX 0:85b3fd62ea1a 1826 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1827
NYX 0:85b3fd62ea1a 1828 /* Low-Power RX low-pass Filtering Tuning */
NYX 0:85b3fd62ea1a 1829 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
NYX 0:85b3fd62ea1a 1830 hdsi->Instance->WPCR[1U] |= Frequency<<25U;
NYX 0:85b3fd62ea1a 1831
NYX 0:85b3fd62ea1a 1832 /* Process unlocked */
NYX 0:85b3fd62ea1a 1833 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1834
NYX 0:85b3fd62ea1a 1835 return HAL_OK;
NYX 0:85b3fd62ea1a 1836 }
NYX 0:85b3fd62ea1a 1837
NYX 0:85b3fd62ea1a 1838 /**
NYX 0:85b3fd62ea1a 1839 * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
NYX 0:85b3fd62ea1a 1840 * defined in the MIPI D-PHY specification
NYX 0:85b3fd62ea1a 1841 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1842 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1843 * @param State: ENABLE or DISABLE
NYX 0:85b3fd62ea1a 1844 * @retval HAL status
NYX 0:85b3fd62ea1a 1845 */
NYX 0:85b3fd62ea1a 1846 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
NYX 0:85b3fd62ea1a 1847 {
NYX 0:85b3fd62ea1a 1848 /* Process locked */
NYX 0:85b3fd62ea1a 1849 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1850
NYX 0:85b3fd62ea1a 1851 /* Check function parameters */
NYX 0:85b3fd62ea1a 1852 assert_param(IS_FUNCTIONAL_STATE(State));
NYX 0:85b3fd62ea1a 1853
NYX 0:85b3fd62ea1a 1854 /* Activate/Disactivate additional current path on all lanes */
NYX 0:85b3fd62ea1a 1855 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
NYX 0:85b3fd62ea1a 1856 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
NYX 0:85b3fd62ea1a 1857
NYX 0:85b3fd62ea1a 1858 /* Process unlocked */
NYX 0:85b3fd62ea1a 1859 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1860
NYX 0:85b3fd62ea1a 1861 return HAL_OK;
NYX 0:85b3fd62ea1a 1862 }
NYX 0:85b3fd62ea1a 1863
NYX 0:85b3fd62ea1a 1864 /**
NYX 0:85b3fd62ea1a 1865 * @brief Custom lane pins configuration
NYX 0:85b3fd62ea1a 1866 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1867 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1868 * @param CustomLane: Function to be applyed on selected lane.
NYX 0:85b3fd62ea1a 1869 * This parameter can be any value of @ref DSI_CustomLane
NYX 0:85b3fd62ea1a 1870 * @param Lane: select between clock or data lane 0 or data lane 1.
NYX 0:85b3fd62ea1a 1871 * This parameter can be any value of @ref DSI_Lane_Select
NYX 0:85b3fd62ea1a 1872 * @param State: ENABLE or DISABLE
NYX 0:85b3fd62ea1a 1873 * @retval HAL status
NYX 0:85b3fd62ea1a 1874 */
NYX 0:85b3fd62ea1a 1875 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
NYX 0:85b3fd62ea1a 1876 {
NYX 0:85b3fd62ea1a 1877 /* Process locked */
NYX 0:85b3fd62ea1a 1878 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1879
NYX 0:85b3fd62ea1a 1880 /* Check function parameters */
NYX 0:85b3fd62ea1a 1881 assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
NYX 0:85b3fd62ea1a 1882 assert_param(IS_DSI_LANE(Lane));
NYX 0:85b3fd62ea1a 1883 assert_param(IS_FUNCTIONAL_STATE(State));
NYX 0:85b3fd62ea1a 1884
NYX 0:85b3fd62ea1a 1885 switch(CustomLane)
NYX 0:85b3fd62ea1a 1886 {
NYX 0:85b3fd62ea1a 1887 case DSI_SWAP_LANE_PINS:
NYX 0:85b3fd62ea1a 1888 if(Lane == DSI_CLOCK_LANE)
NYX 0:85b3fd62ea1a 1889 {
NYX 0:85b3fd62ea1a 1890 /* Swap pins on clock lane */
NYX 0:85b3fd62ea1a 1891 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
NYX 0:85b3fd62ea1a 1892 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
NYX 0:85b3fd62ea1a 1893 }
NYX 0:85b3fd62ea1a 1894 else if(Lane == DSI_DATA_LANE0)
NYX 0:85b3fd62ea1a 1895 {
NYX 0:85b3fd62ea1a 1896 /* Swap pins on data lane 0 */
NYX 0:85b3fd62ea1a 1897 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
NYX 0:85b3fd62ea1a 1898 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
NYX 0:85b3fd62ea1a 1899 }
NYX 0:85b3fd62ea1a 1900 else if(Lane == DSI_DATA_LANE1)
NYX 0:85b3fd62ea1a 1901 {
NYX 0:85b3fd62ea1a 1902 /* Swap pins on data lane 1 */
NYX 0:85b3fd62ea1a 1903 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
NYX 0:85b3fd62ea1a 1904 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
NYX 0:85b3fd62ea1a 1905 }
NYX 0:85b3fd62ea1a 1906 break;
NYX 0:85b3fd62ea1a 1907 case DSI_INVERT_HS_SIGNAL:
NYX 0:85b3fd62ea1a 1908 if(Lane == DSI_CLOCK_LANE)
NYX 0:85b3fd62ea1a 1909 {
NYX 0:85b3fd62ea1a 1910 /* Invert HS signal on clock lane */
NYX 0:85b3fd62ea1a 1911 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
NYX 0:85b3fd62ea1a 1912 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
NYX 0:85b3fd62ea1a 1913 }
NYX 0:85b3fd62ea1a 1914 else if(Lane == DSI_DATA_LANE0)
NYX 0:85b3fd62ea1a 1915 {
NYX 0:85b3fd62ea1a 1916 /* Invert HS signal on data lane 0 */
NYX 0:85b3fd62ea1a 1917 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
NYX 0:85b3fd62ea1a 1918 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
NYX 0:85b3fd62ea1a 1919 }
NYX 0:85b3fd62ea1a 1920 else if(Lane == DSI_DATA_LANE1)
NYX 0:85b3fd62ea1a 1921 {
NYX 0:85b3fd62ea1a 1922 /* Invert HS signal on data lane 1 */
NYX 0:85b3fd62ea1a 1923 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
NYX 0:85b3fd62ea1a 1924 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
NYX 0:85b3fd62ea1a 1925 }
NYX 0:85b3fd62ea1a 1926 break;
NYX 0:85b3fd62ea1a 1927 default:
NYX 0:85b3fd62ea1a 1928 break;
NYX 0:85b3fd62ea1a 1929 }
NYX 0:85b3fd62ea1a 1930
NYX 0:85b3fd62ea1a 1931 /* Process unlocked */
NYX 0:85b3fd62ea1a 1932 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 1933
NYX 0:85b3fd62ea1a 1934 return HAL_OK;
NYX 0:85b3fd62ea1a 1935 }
NYX 0:85b3fd62ea1a 1936
NYX 0:85b3fd62ea1a 1937 /**
NYX 0:85b3fd62ea1a 1938 * @brief Set custom timing for the PHY
NYX 0:85b3fd62ea1a 1939 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1940 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 1941 * @param Timing: PHY timing to be adjusted.
NYX 0:85b3fd62ea1a 1942 * This parameter can be any value of @ref DSI_PHY_Timing
NYX 0:85b3fd62ea1a 1943 * @param State: ENABLE or DISABLE
NYX 0:85b3fd62ea1a 1944 * @param Value: Custom value of the timing
NYX 0:85b3fd62ea1a 1945 * @retval HAL status
NYX 0:85b3fd62ea1a 1946 */
NYX 0:85b3fd62ea1a 1947 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
NYX 0:85b3fd62ea1a 1948 {
NYX 0:85b3fd62ea1a 1949 /* Process locked */
NYX 0:85b3fd62ea1a 1950 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 1951
NYX 0:85b3fd62ea1a 1952 /* Check function parameters */
NYX 0:85b3fd62ea1a 1953 assert_param(IS_DSI_PHY_TIMING(Timing));
NYX 0:85b3fd62ea1a 1954 assert_param(IS_FUNCTIONAL_STATE(State));
NYX 0:85b3fd62ea1a 1955
NYX 0:85b3fd62ea1a 1956 switch(Timing)
NYX 0:85b3fd62ea1a 1957 {
NYX 0:85b3fd62ea1a 1958 case DSI_TCLK_POST:
NYX 0:85b3fd62ea1a 1959 /* Enable/Disable custom timing setting */
NYX 0:85b3fd62ea1a 1960 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
NYX 0:85b3fd62ea1a 1961 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
NYX 0:85b3fd62ea1a 1962
NYX 0:85b3fd62ea1a 1963 if(State)
NYX 0:85b3fd62ea1a 1964 {
NYX 0:85b3fd62ea1a 1965 /* Set custom value */
NYX 0:85b3fd62ea1a 1966 hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
NYX 0:85b3fd62ea1a 1967 hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
NYX 0:85b3fd62ea1a 1968 }
NYX 0:85b3fd62ea1a 1969
NYX 0:85b3fd62ea1a 1970 break;
NYX 0:85b3fd62ea1a 1971 case DSI_TLPX_CLK:
NYX 0:85b3fd62ea1a 1972 /* Enable/Disable custom timing setting */
NYX 0:85b3fd62ea1a 1973 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
NYX 0:85b3fd62ea1a 1974 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
NYX 0:85b3fd62ea1a 1975
NYX 0:85b3fd62ea1a 1976 if(State)
NYX 0:85b3fd62ea1a 1977 {
NYX 0:85b3fd62ea1a 1978 /* Set custom value */
NYX 0:85b3fd62ea1a 1979 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
NYX 0:85b3fd62ea1a 1980 hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
NYX 0:85b3fd62ea1a 1981 }
NYX 0:85b3fd62ea1a 1982
NYX 0:85b3fd62ea1a 1983 break;
NYX 0:85b3fd62ea1a 1984 case DSI_THS_EXIT:
NYX 0:85b3fd62ea1a 1985 /* Enable/Disable custom timing setting */
NYX 0:85b3fd62ea1a 1986 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
NYX 0:85b3fd62ea1a 1987 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
NYX 0:85b3fd62ea1a 1988
NYX 0:85b3fd62ea1a 1989 if(State)
NYX 0:85b3fd62ea1a 1990 {
NYX 0:85b3fd62ea1a 1991 /* Set custom value */
NYX 0:85b3fd62ea1a 1992 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
NYX 0:85b3fd62ea1a 1993 hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
NYX 0:85b3fd62ea1a 1994 }
NYX 0:85b3fd62ea1a 1995
NYX 0:85b3fd62ea1a 1996 break;
NYX 0:85b3fd62ea1a 1997 case DSI_TLPX_DATA:
NYX 0:85b3fd62ea1a 1998 /* Enable/Disable custom timing setting */
NYX 0:85b3fd62ea1a 1999 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
NYX 0:85b3fd62ea1a 2000 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
NYX 0:85b3fd62ea1a 2001
NYX 0:85b3fd62ea1a 2002 if(State)
NYX 0:85b3fd62ea1a 2003 {
NYX 0:85b3fd62ea1a 2004 /* Set custom value */
NYX 0:85b3fd62ea1a 2005 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
NYX 0:85b3fd62ea1a 2006 hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
NYX 0:85b3fd62ea1a 2007 }
NYX 0:85b3fd62ea1a 2008
NYX 0:85b3fd62ea1a 2009 break;
NYX 0:85b3fd62ea1a 2010 case DSI_THS_ZERO:
NYX 0:85b3fd62ea1a 2011 /* Enable/Disable custom timing setting */
NYX 0:85b3fd62ea1a 2012 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
NYX 0:85b3fd62ea1a 2013 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
NYX 0:85b3fd62ea1a 2014
NYX 0:85b3fd62ea1a 2015 if(State)
NYX 0:85b3fd62ea1a 2016 {
NYX 0:85b3fd62ea1a 2017 /* Set custom value */
NYX 0:85b3fd62ea1a 2018 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
NYX 0:85b3fd62ea1a 2019 hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
NYX 0:85b3fd62ea1a 2020 }
NYX 0:85b3fd62ea1a 2021
NYX 0:85b3fd62ea1a 2022 break;
NYX 0:85b3fd62ea1a 2023 case DSI_THS_TRAIL:
NYX 0:85b3fd62ea1a 2024 /* Enable/Disable custom timing setting */
NYX 0:85b3fd62ea1a 2025 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
NYX 0:85b3fd62ea1a 2026 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
NYX 0:85b3fd62ea1a 2027
NYX 0:85b3fd62ea1a 2028 if(State)
NYX 0:85b3fd62ea1a 2029 {
NYX 0:85b3fd62ea1a 2030 /* Set custom value */
NYX 0:85b3fd62ea1a 2031 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
NYX 0:85b3fd62ea1a 2032 hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
NYX 0:85b3fd62ea1a 2033 }
NYX 0:85b3fd62ea1a 2034
NYX 0:85b3fd62ea1a 2035 break;
NYX 0:85b3fd62ea1a 2036 case DSI_THS_PREPARE:
NYX 0:85b3fd62ea1a 2037 /* Enable/Disable custom timing setting */
NYX 0:85b3fd62ea1a 2038 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
NYX 0:85b3fd62ea1a 2039 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
NYX 0:85b3fd62ea1a 2040
NYX 0:85b3fd62ea1a 2041 if(State)
NYX 0:85b3fd62ea1a 2042 {
NYX 0:85b3fd62ea1a 2043 /* Set custom value */
NYX 0:85b3fd62ea1a 2044 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
NYX 0:85b3fd62ea1a 2045 hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
NYX 0:85b3fd62ea1a 2046 }
NYX 0:85b3fd62ea1a 2047
NYX 0:85b3fd62ea1a 2048 break;
NYX 0:85b3fd62ea1a 2049 case DSI_TCLK_ZERO:
NYX 0:85b3fd62ea1a 2050 /* Enable/Disable custom timing setting */
NYX 0:85b3fd62ea1a 2051 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
NYX 0:85b3fd62ea1a 2052 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
NYX 0:85b3fd62ea1a 2053
NYX 0:85b3fd62ea1a 2054 if(State)
NYX 0:85b3fd62ea1a 2055 {
NYX 0:85b3fd62ea1a 2056 /* Set custom value */
NYX 0:85b3fd62ea1a 2057 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
NYX 0:85b3fd62ea1a 2058 hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
NYX 0:85b3fd62ea1a 2059 }
NYX 0:85b3fd62ea1a 2060
NYX 0:85b3fd62ea1a 2061 break;
NYX 0:85b3fd62ea1a 2062 case DSI_TCLK_PREPARE:
NYX 0:85b3fd62ea1a 2063 /* Enable/Disable custom timing setting */
NYX 0:85b3fd62ea1a 2064 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
NYX 0:85b3fd62ea1a 2065 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
NYX 0:85b3fd62ea1a 2066
NYX 0:85b3fd62ea1a 2067 if(State)
NYX 0:85b3fd62ea1a 2068 {
NYX 0:85b3fd62ea1a 2069 /* Set custom value */
NYX 0:85b3fd62ea1a 2070 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
NYX 0:85b3fd62ea1a 2071 hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
NYX 0:85b3fd62ea1a 2072 }
NYX 0:85b3fd62ea1a 2073
NYX 0:85b3fd62ea1a 2074 break;
NYX 0:85b3fd62ea1a 2075 default:
NYX 0:85b3fd62ea1a 2076 break;
NYX 0:85b3fd62ea1a 2077 }
NYX 0:85b3fd62ea1a 2078
NYX 0:85b3fd62ea1a 2079 /* Process unlocked */
NYX 0:85b3fd62ea1a 2080 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 2081
NYX 0:85b3fd62ea1a 2082 return HAL_OK;
NYX 0:85b3fd62ea1a 2083 }
NYX 0:85b3fd62ea1a 2084
NYX 0:85b3fd62ea1a 2085 /**
NYX 0:85b3fd62ea1a 2086 * @brief Force the Clock/Data Lane in TX Stop Mode
NYX 0:85b3fd62ea1a 2087 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2088 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 2089 * @param Lane: select between clock or data lanes.
NYX 0:85b3fd62ea1a 2090 * This parameter can be any value of @ref DSI_Lane_Group
NYX 0:85b3fd62ea1a 2091 * @param State: ENABLE or DISABLE
NYX 0:85b3fd62ea1a 2092 * @retval HAL status
NYX 0:85b3fd62ea1a 2093 */
NYX 0:85b3fd62ea1a 2094 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
NYX 0:85b3fd62ea1a 2095 {
NYX 0:85b3fd62ea1a 2096 /* Process locked */
NYX 0:85b3fd62ea1a 2097 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 2098
NYX 0:85b3fd62ea1a 2099 /* Check function parameters */
NYX 0:85b3fd62ea1a 2100 assert_param(IS_DSI_LANE_GROUP(Lane));
NYX 0:85b3fd62ea1a 2101 assert_param(IS_FUNCTIONAL_STATE(State));
NYX 0:85b3fd62ea1a 2102
NYX 0:85b3fd62ea1a 2103 if(Lane == DSI_CLOCK_LANE)
NYX 0:85b3fd62ea1a 2104 {
NYX 0:85b3fd62ea1a 2105 /* Force/Unforce the Clock Lane in TX Stop Mode */
NYX 0:85b3fd62ea1a 2106 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
NYX 0:85b3fd62ea1a 2107 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
NYX 0:85b3fd62ea1a 2108 }
NYX 0:85b3fd62ea1a 2109 else if(Lane == DSI_DATA_LANES)
NYX 0:85b3fd62ea1a 2110 {
NYX 0:85b3fd62ea1a 2111 /* Force/Unforce the Data Lanes in TX Stop Mode */
NYX 0:85b3fd62ea1a 2112 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
NYX 0:85b3fd62ea1a 2113 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
NYX 0:85b3fd62ea1a 2114 }
NYX 0:85b3fd62ea1a 2115
NYX 0:85b3fd62ea1a 2116 /* Process unlocked */
NYX 0:85b3fd62ea1a 2117 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 2118
NYX 0:85b3fd62ea1a 2119 return HAL_OK;
NYX 0:85b3fd62ea1a 2120 }
NYX 0:85b3fd62ea1a 2121
NYX 0:85b3fd62ea1a 2122 /**
NYX 0:85b3fd62ea1a 2123 * @brief Forces LP Receiver in Low-Power Mode
NYX 0:85b3fd62ea1a 2124 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2125 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 2126 * @param State: ENABLE or DISABLE
NYX 0:85b3fd62ea1a 2127 * @retval HAL status
NYX 0:85b3fd62ea1a 2128 */
NYX 0:85b3fd62ea1a 2129 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
NYX 0:85b3fd62ea1a 2130 {
NYX 0:85b3fd62ea1a 2131 /* Process locked */
NYX 0:85b3fd62ea1a 2132 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 2133
NYX 0:85b3fd62ea1a 2134 /* Check function parameters */
NYX 0:85b3fd62ea1a 2135 assert_param(IS_FUNCTIONAL_STATE(State));
NYX 0:85b3fd62ea1a 2136
NYX 0:85b3fd62ea1a 2137 /* Force/Unforce LP Receiver in Low-Power Mode */
NYX 0:85b3fd62ea1a 2138 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
NYX 0:85b3fd62ea1a 2139 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
NYX 0:85b3fd62ea1a 2140
NYX 0:85b3fd62ea1a 2141 /* Process unlocked */
NYX 0:85b3fd62ea1a 2142 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 2143
NYX 0:85b3fd62ea1a 2144 return HAL_OK;
NYX 0:85b3fd62ea1a 2145 }
NYX 0:85b3fd62ea1a 2146
NYX 0:85b3fd62ea1a 2147 /**
NYX 0:85b3fd62ea1a 2148 * @brief Force Data Lanes in RX Mode after a BTA
NYX 0:85b3fd62ea1a 2149 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2150 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 2151 * @param State: ENABLE or DISABLE
NYX 0:85b3fd62ea1a 2152 * @retval HAL status
NYX 0:85b3fd62ea1a 2153 */
NYX 0:85b3fd62ea1a 2154 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
NYX 0:85b3fd62ea1a 2155 {
NYX 0:85b3fd62ea1a 2156 /* Process locked */
NYX 0:85b3fd62ea1a 2157 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 2158
NYX 0:85b3fd62ea1a 2159 /* Check function parameters */
NYX 0:85b3fd62ea1a 2160 assert_param(IS_FUNCTIONAL_STATE(State));
NYX 0:85b3fd62ea1a 2161
NYX 0:85b3fd62ea1a 2162 /* Force Data Lanes in RX Mode */
NYX 0:85b3fd62ea1a 2163 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
NYX 0:85b3fd62ea1a 2164 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
NYX 0:85b3fd62ea1a 2165
NYX 0:85b3fd62ea1a 2166 /* Process unlocked */
NYX 0:85b3fd62ea1a 2167 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 2168
NYX 0:85b3fd62ea1a 2169 return HAL_OK;
NYX 0:85b3fd62ea1a 2170 }
NYX 0:85b3fd62ea1a 2171
NYX 0:85b3fd62ea1a 2172 /**
NYX 0:85b3fd62ea1a 2173 * @brief Enable a pull-down on the lanes to prevent from floating states when unused
NYX 0:85b3fd62ea1a 2174 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2175 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 2176 * @param State: ENABLE or DISABLE
NYX 0:85b3fd62ea1a 2177 * @retval HAL status
NYX 0:85b3fd62ea1a 2178 */
NYX 0:85b3fd62ea1a 2179 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
NYX 0:85b3fd62ea1a 2180 {
NYX 0:85b3fd62ea1a 2181 /* Process locked */
NYX 0:85b3fd62ea1a 2182 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 2183
NYX 0:85b3fd62ea1a 2184 /* Check function parameters */
NYX 0:85b3fd62ea1a 2185 assert_param(IS_FUNCTIONAL_STATE(State));
NYX 0:85b3fd62ea1a 2186
NYX 0:85b3fd62ea1a 2187 /* Enable/Disable pull-down on lanes */
NYX 0:85b3fd62ea1a 2188 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
NYX 0:85b3fd62ea1a 2189 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
NYX 0:85b3fd62ea1a 2190
NYX 0:85b3fd62ea1a 2191 /* Process unlocked */
NYX 0:85b3fd62ea1a 2192 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 2193
NYX 0:85b3fd62ea1a 2194 return HAL_OK;
NYX 0:85b3fd62ea1a 2195 }
NYX 0:85b3fd62ea1a 2196
NYX 0:85b3fd62ea1a 2197 /**
NYX 0:85b3fd62ea1a 2198 * @brief Switch off the contention detection on data lanes
NYX 0:85b3fd62ea1a 2199 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2200 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 2201 * @param State: ENABLE or DISABLE
NYX 0:85b3fd62ea1a 2202 * @retval HAL status
NYX 0:85b3fd62ea1a 2203 */
NYX 0:85b3fd62ea1a 2204 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
NYX 0:85b3fd62ea1a 2205 {
NYX 0:85b3fd62ea1a 2206 /* Process locked */
NYX 0:85b3fd62ea1a 2207 __HAL_LOCK(hdsi);
NYX 0:85b3fd62ea1a 2208
NYX 0:85b3fd62ea1a 2209 /* Check function parameters */
NYX 0:85b3fd62ea1a 2210 assert_param(IS_FUNCTIONAL_STATE(State));
NYX 0:85b3fd62ea1a 2211
NYX 0:85b3fd62ea1a 2212 /* Contention Detection on Data Lanes OFF */
NYX 0:85b3fd62ea1a 2213 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
NYX 0:85b3fd62ea1a 2214 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
NYX 0:85b3fd62ea1a 2215
NYX 0:85b3fd62ea1a 2216 /* Process unlocked */
NYX 0:85b3fd62ea1a 2217 __HAL_UNLOCK(hdsi);
NYX 0:85b3fd62ea1a 2218
NYX 0:85b3fd62ea1a 2219 return HAL_OK;
NYX 0:85b3fd62ea1a 2220 }
NYX 0:85b3fd62ea1a 2221
NYX 0:85b3fd62ea1a 2222 /**
NYX 0:85b3fd62ea1a 2223 * @}
NYX 0:85b3fd62ea1a 2224 */
NYX 0:85b3fd62ea1a 2225
NYX 0:85b3fd62ea1a 2226 /** @defgroup DSI_Group4 Peripheral State and Errors functions
NYX 0:85b3fd62ea1a 2227 * @brief Peripheral State and Errors functions
NYX 0:85b3fd62ea1a 2228 *
NYX 0:85b3fd62ea1a 2229 @verbatim
NYX 0:85b3fd62ea1a 2230 ===============================================================================
NYX 0:85b3fd62ea1a 2231 ##### Peripheral State and Errors functions #####
NYX 0:85b3fd62ea1a 2232 ===============================================================================
NYX 0:85b3fd62ea1a 2233 [..]
NYX 0:85b3fd62ea1a 2234 This subsection provides functions allowing to
NYX 0:85b3fd62ea1a 2235 (+) Check the DSI state.
NYX 0:85b3fd62ea1a 2236 (+) Get error code.
NYX 0:85b3fd62ea1a 2237
NYX 0:85b3fd62ea1a 2238 @endverbatim
NYX 0:85b3fd62ea1a 2239 * @{
NYX 0:85b3fd62ea1a 2240 */
NYX 0:85b3fd62ea1a 2241
NYX 0:85b3fd62ea1a 2242 /**
NYX 0:85b3fd62ea1a 2243 * @brief Return the DSI state
NYX 0:85b3fd62ea1a 2244 * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2245 * the configuration information for the DSI.
NYX 0:85b3fd62ea1a 2246 * @retval HAL state
NYX 0:85b3fd62ea1a 2247 */
NYX 0:85b3fd62ea1a 2248 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
NYX 0:85b3fd62ea1a 2249 {
NYX 0:85b3fd62ea1a 2250 return hdsi->State;
NYX 0:85b3fd62ea1a 2251 }
NYX 0:85b3fd62ea1a 2252
NYX 0:85b3fd62ea1a 2253 /**
NYX 0:85b3fd62ea1a 2254 * @}
NYX 0:85b3fd62ea1a 2255 */
NYX 0:85b3fd62ea1a 2256
NYX 0:85b3fd62ea1a 2257 /**
NYX 0:85b3fd62ea1a 2258 * @}
NYX 0:85b3fd62ea1a 2259 */
NYX 0:85b3fd62ea1a 2260 #endif /* STM32F469xx || STM32F479xx */
NYX 0:85b3fd62ea1a 2261 #endif /* HAL_DSI_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 2262 /**
NYX 0:85b3fd62ea1a 2263 * @}
NYX 0:85b3fd62ea1a 2264 */
NYX 0:85b3fd62ea1a 2265
NYX 0:85b3fd62ea1a 2266 /**
NYX 0:85b3fd62ea1a 2267 * @}
NYX 0:85b3fd62ea1a 2268 */
NYX 0:85b3fd62ea1a 2269
NYX 0:85b3fd62ea1a 2270 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/