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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_dma2d.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief DMA2D HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 9 * functionalities of the DMA2D peripheral:
NYX 0:85b3fd62ea1a 10 * + Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 11 * + IO operation functions
NYX 0:85b3fd62ea1a 12 * + Peripheral Control functions
NYX 0:85b3fd62ea1a 13 * + Peripheral State and Errors functions
NYX 0:85b3fd62ea1a 14 *
NYX 0:85b3fd62ea1a 15 @verbatim
NYX 0:85b3fd62ea1a 16 ==============================================================================
NYX 0:85b3fd62ea1a 17 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 18 ==============================================================================
NYX 0:85b3fd62ea1a 19 [..]
NYX 0:85b3fd62ea1a 20 (#) Program the required configuration through the following parameters:
NYX 0:85b3fd62ea1a 21 the transfer mode, the output color mode and the output offset using
NYX 0:85b3fd62ea1a 22 HAL_DMA2D_Init() function.
NYX 0:85b3fd62ea1a 23
NYX 0:85b3fd62ea1a 24 (#) Program the required configuration through the following parameters:
NYX 0:85b3fd62ea1a 25 the input color mode, the input color, the input alpha value, the alpha mode,
NYX 0:85b3fd62ea1a 26 and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
NYX 0:85b3fd62ea1a 27 or/and background layer.
NYX 0:85b3fd62ea1a 28
NYX 0:85b3fd62ea1a 29 *** Polling mode IO operation ***
NYX 0:85b3fd62ea1a 30 =================================
NYX 0:85b3fd62ea1a 31 [..]
NYX 0:85b3fd62ea1a 32 (#) Configure pdata parameter (explained hereafter), destination and data length
NYX 0:85b3fd62ea1a 33 and enable the transfer using HAL_DMA2D_Start().
NYX 0:85b3fd62ea1a 34 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
NYX 0:85b3fd62ea1a 35 user can specify the value of timeout according to his end application.
NYX 0:85b3fd62ea1a 36
NYX 0:85b3fd62ea1a 37 *** Interrupt mode IO operation ***
NYX 0:85b3fd62ea1a 38 ===================================
NYX 0:85b3fd62ea1a 39 [..]
NYX 0:85b3fd62ea1a 40 (#) Configure pdata parameter, destination and data length and enable
NYX 0:85b3fd62ea1a 41 the transfer using HAL_DMA2D_Start_IT().
NYX 0:85b3fd62ea1a 42 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
NYX 0:85b3fd62ea1a 43 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
NYX 0:85b3fd62ea1a 44 add his own function by customization of function pointer XferCpltCallback (member
NYX 0:85b3fd62ea1a 45 of DMA2D handle structure).
NYX 0:85b3fd62ea1a 46 (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
NYX 0:85b3fd62ea1a 47 XferErrorCallback.
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 -@- In Register-to-Memory transfer mode, pdata parameter is the register
NYX 0:85b3fd62ea1a 50 color, in Memory-to-memory or Memory-to-Memory with pixel format
NYX 0:85b3fd62ea1a 51 conversion pdata is the source address.
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 -@- Configure the foreground source address, the background source address,
NYX 0:85b3fd62ea1a 54 the destination and data length then Enable the transfer using
NYX 0:85b3fd62ea1a 55 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
NYX 0:85b3fd62ea1a 56 in interrupt mode
NYX 0:85b3fd62ea1a 57
NYX 0:85b3fd62ea1a 58 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
NYX 0:85b3fd62ea1a 59 are used if the memory to memory with blending transfer mode is selected.
NYX 0:85b3fd62ea1a 60
NYX 0:85b3fd62ea1a 61 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
NYX 0:85b3fd62ea1a 62 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
NYX 0:85b3fd62ea1a 63
NYX 0:85b3fd62ea1a 64 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
NYX 0:85b3fd62ea1a 65
NYX 0:85b3fd62ea1a 66 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
NYX 0:85b3fd62ea1a 67 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
NYX 0:85b3fd62ea1a 68 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
NYX 0:85b3fd62ea1a 69 HAL_DMA2D_DisableDeadTime().
NYX 0:85b3fd62ea1a 70
NYX 0:85b3fd62ea1a 71 (#) The transfer can be suspended, resumed and aborted using the following
NYX 0:85b3fd62ea1a 72 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
NYX 0:85b3fd62ea1a 73
NYX 0:85b3fd62ea1a 74 (#) The CLUT loading can be suspended, resumed and aborted using the following
NYX 0:85b3fd62ea1a 75 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
NYX 0:85b3fd62ea1a 76 HAL_DMA2D_CLUTLoading_Abort().
NYX 0:85b3fd62ea1a 77
NYX 0:85b3fd62ea1a 78 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
NYX 0:85b3fd62ea1a 79
NYX 0:85b3fd62ea1a 80 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
NYX 0:85b3fd62ea1a 81
NYX 0:85b3fd62ea1a 82 *** DMA2D HAL driver macros list ***
NYX 0:85b3fd62ea1a 83 =============================================
NYX 0:85b3fd62ea1a 84 [..]
NYX 0:85b3fd62ea1a 85 Below the list of most used macros in DMA2D HAL driver :
NYX 0:85b3fd62ea1a 86
NYX 0:85b3fd62ea1a 87 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
NYX 0:85b3fd62ea1a 88 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
NYX 0:85b3fd62ea1a 89 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
NYX 0:85b3fd62ea1a 90 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
NYX 0:85b3fd62ea1a 91 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
NYX 0:85b3fd62ea1a 92 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
NYX 0:85b3fd62ea1a 93
NYX 0:85b3fd62ea1a 94 [..]
NYX 0:85b3fd62ea1a 95 (@) You can refer to the DMA2D HAL driver header file for more useful macros
NYX 0:85b3fd62ea1a 96
NYX 0:85b3fd62ea1a 97 @endverbatim
NYX 0:85b3fd62ea1a 98 ******************************************************************************
NYX 0:85b3fd62ea1a 99 * @attention
NYX 0:85b3fd62ea1a 100 *
NYX 0:85b3fd62ea1a 101 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 102 *
NYX 0:85b3fd62ea1a 103 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 104 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 105 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 106 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 108 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 109 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 111 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 112 * without specific prior written permission.
NYX 0:85b3fd62ea1a 113 *
NYX 0:85b3fd62ea1a 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 124 *
NYX 0:85b3fd62ea1a 125 ******************************************************************************
NYX 0:85b3fd62ea1a 126 */
NYX 0:85b3fd62ea1a 127
NYX 0:85b3fd62ea1a 128 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 129 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 130
NYX 0:85b3fd62ea1a 131 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 132 * @{
NYX 0:85b3fd62ea1a 133 */
NYX 0:85b3fd62ea1a 134
NYX 0:85b3fd62ea1a 135 /** @defgroup DMA2D DMA2D
NYX 0:85b3fd62ea1a 136 * @brief DMA2D HAL module driver
NYX 0:85b3fd62ea1a 137 * @{
NYX 0:85b3fd62ea1a 138 */
NYX 0:85b3fd62ea1a 139
NYX 0:85b3fd62ea1a 140 #ifdef HAL_DMA2D_MODULE_ENABLED
NYX 0:85b3fd62ea1a 141
NYX 0:85b3fd62ea1a 142 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 143
NYX 0:85b3fd62ea1a 144 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 145 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 146 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
NYX 0:85b3fd62ea1a 147 * @{
NYX 0:85b3fd62ea1a 148 */
NYX 0:85b3fd62ea1a 149
NYX 0:85b3fd62ea1a 150 /** @defgroup DMA2D_TimeOut DMA2D Time Out
NYX 0:85b3fd62ea1a 151 * @{
NYX 0:85b3fd62ea1a 152 */
NYX 0:85b3fd62ea1a 153 #define DMA2D_TIMEOUT_ABORT 1000U /*!< 1s */
NYX 0:85b3fd62ea1a 154 #define DMA2D_TIMEOUT_SUSPEND 1000U /*!< 1s */
NYX 0:85b3fd62ea1a 155 /**
NYX 0:85b3fd62ea1a 156 * @}
NYX 0:85b3fd62ea1a 157 */
NYX 0:85b3fd62ea1a 158
NYX 0:85b3fd62ea1a 159 /** @defgroup DMA2D_Shifts DMA2D Shifts
NYX 0:85b3fd62ea1a 160 * @{
NYX 0:85b3fd62ea1a 161 */
NYX 0:85b3fd62ea1a 162 #define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */
NYX 0:85b3fd62ea1a 163 #define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */
NYX 0:85b3fd62ea1a 164
NYX 0:85b3fd62ea1a 165 #define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */
NYX 0:85b3fd62ea1a 166 #define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */
NYX 0:85b3fd62ea1a 167
NYX 0:85b3fd62ea1a 168 #define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */
NYX 0:85b3fd62ea1a 169
NYX 0:85b3fd62ea1a 170 #define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */
NYX 0:85b3fd62ea1a 171 #define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */
NYX 0:85b3fd62ea1a 172
NYX 0:85b3fd62ea1a 173 #define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
NYX 0:85b3fd62ea1a 174 #define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
NYX 0:85b3fd62ea1a 175
NYX 0:85b3fd62ea1a 176 #define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */
NYX 0:85b3fd62ea1a 177 /**
NYX 0:85b3fd62ea1a 178 * @}
NYX 0:85b3fd62ea1a 179 */
NYX 0:85b3fd62ea1a 180
NYX 0:85b3fd62ea1a 181 /**
NYX 0:85b3fd62ea1a 182 * @}
NYX 0:85b3fd62ea1a 183 */
NYX 0:85b3fd62ea1a 184
NYX 0:85b3fd62ea1a 185 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 186 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 187 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 188 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 189 /** @addtogroup DMA2D_Private_Functions_Prototypes
NYX 0:85b3fd62ea1a 190 * @{
NYX 0:85b3fd62ea1a 191 */
NYX 0:85b3fd62ea1a 192 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
NYX 0:85b3fd62ea1a 193 /**
NYX 0:85b3fd62ea1a 194 * @}
NYX 0:85b3fd62ea1a 195 */
NYX 0:85b3fd62ea1a 196
NYX 0:85b3fd62ea1a 197 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 198 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 199 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
NYX 0:85b3fd62ea1a 200 * @{
NYX 0:85b3fd62ea1a 201 */
NYX 0:85b3fd62ea1a 202
NYX 0:85b3fd62ea1a 203 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 204 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 205 *
NYX 0:85b3fd62ea1a 206 @verbatim
NYX 0:85b3fd62ea1a 207 ===============================================================================
NYX 0:85b3fd62ea1a 208 ##### Initialization and Configuration functions #####
NYX 0:85b3fd62ea1a 209 ===============================================================================
NYX 0:85b3fd62ea1a 210 [..] This section provides functions allowing to:
NYX 0:85b3fd62ea1a 211 (+) Initialize and configure the DMA2D
NYX 0:85b3fd62ea1a 212 (+) De-initialize the DMA2D
NYX 0:85b3fd62ea1a 213
NYX 0:85b3fd62ea1a 214 @endverbatim
NYX 0:85b3fd62ea1a 215 * @{
NYX 0:85b3fd62ea1a 216 */
NYX 0:85b3fd62ea1a 217
NYX 0:85b3fd62ea1a 218 /**
NYX 0:85b3fd62ea1a 219 * @brief Initialize the DMA2D according to the specified
NYX 0:85b3fd62ea1a 220 * parameters in the DMA2D_InitTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 221 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 222 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 223 * @retval HAL status
NYX 0:85b3fd62ea1a 224 */
NYX 0:85b3fd62ea1a 225 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 226 {
NYX 0:85b3fd62ea1a 227 /* Check the DMA2D peripheral state */
NYX 0:85b3fd62ea1a 228 if(hdma2d == NULL)
NYX 0:85b3fd62ea1a 229 {
NYX 0:85b3fd62ea1a 230 return HAL_ERROR;
NYX 0:85b3fd62ea1a 231 }
NYX 0:85b3fd62ea1a 232
NYX 0:85b3fd62ea1a 233 /* Check the parameters */
NYX 0:85b3fd62ea1a 234 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
NYX 0:85b3fd62ea1a 235 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
NYX 0:85b3fd62ea1a 236 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
NYX 0:85b3fd62ea1a 237 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
NYX 0:85b3fd62ea1a 238
NYX 0:85b3fd62ea1a 239 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
NYX 0:85b3fd62ea1a 240 {
NYX 0:85b3fd62ea1a 241 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 242 hdma2d->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 243 /* Init the low level hardware */
NYX 0:85b3fd62ea1a 244 HAL_DMA2D_MspInit(hdma2d);
NYX 0:85b3fd62ea1a 245 }
NYX 0:85b3fd62ea1a 246
NYX 0:85b3fd62ea1a 247 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 248 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 249
NYX 0:85b3fd62ea1a 250 /* DMA2D CR register configuration -------------------------------------------*/
NYX 0:85b3fd62ea1a 251 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
NYX 0:85b3fd62ea1a 252
NYX 0:85b3fd62ea1a 253 /* DMA2D OPFCCR register configuration ---------------------------------------*/
NYX 0:85b3fd62ea1a 254 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
NYX 0:85b3fd62ea1a 255
NYX 0:85b3fd62ea1a 256 /* DMA2D OOR register configuration ------------------------------------------*/
NYX 0:85b3fd62ea1a 257 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
NYX 0:85b3fd62ea1a 258
NYX 0:85b3fd62ea1a 259 /* Update error code */
NYX 0:85b3fd62ea1a 260 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
NYX 0:85b3fd62ea1a 261
NYX 0:85b3fd62ea1a 262 /* Initialize the DMA2D state*/
NYX 0:85b3fd62ea1a 263 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 264
NYX 0:85b3fd62ea1a 265 return HAL_OK;
NYX 0:85b3fd62ea1a 266 }
NYX 0:85b3fd62ea1a 267
NYX 0:85b3fd62ea1a 268 /**
NYX 0:85b3fd62ea1a 269 * @brief Deinitializes the DMA2D peripheral registers to their default reset
NYX 0:85b3fd62ea1a 270 * values.
NYX 0:85b3fd62ea1a 271 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 272 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 273 * @retval None
NYX 0:85b3fd62ea1a 274 */
NYX 0:85b3fd62ea1a 275
NYX 0:85b3fd62ea1a 276 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 277 {
NYX 0:85b3fd62ea1a 278 /* Check the DMA2D peripheral state */
NYX 0:85b3fd62ea1a 279 if(hdma2d == NULL)
NYX 0:85b3fd62ea1a 280 {
NYX 0:85b3fd62ea1a 281 return HAL_ERROR;
NYX 0:85b3fd62ea1a 282 }
NYX 0:85b3fd62ea1a 283
NYX 0:85b3fd62ea1a 284 /* Before aborting any DMA2D transfer or CLUT loading, check
NYX 0:85b3fd62ea1a 285 first whether or not DMA2D clock is enabled */
NYX 0:85b3fd62ea1a 286 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
NYX 0:85b3fd62ea1a 287 {
NYX 0:85b3fd62ea1a 288 /* Abort DMA2D transfer if any */
NYX 0:85b3fd62ea1a 289 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
NYX 0:85b3fd62ea1a 290 {
NYX 0:85b3fd62ea1a 291 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
NYX 0:85b3fd62ea1a 292 {
NYX 0:85b3fd62ea1a 293 /* Issue when aborting DMA2D transfer */
NYX 0:85b3fd62ea1a 294 return HAL_ERROR;
NYX 0:85b3fd62ea1a 295 }
NYX 0:85b3fd62ea1a 296 }
NYX 0:85b3fd62ea1a 297 else
NYX 0:85b3fd62ea1a 298 {
NYX 0:85b3fd62ea1a 299 /* Abort background CLUT loading if any */
NYX 0:85b3fd62ea1a 300 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
NYX 0:85b3fd62ea1a 301 {
NYX 0:85b3fd62ea1a 302 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
NYX 0:85b3fd62ea1a 303 {
NYX 0:85b3fd62ea1a 304 /* Issue when aborting background CLUT loading */
NYX 0:85b3fd62ea1a 305 return HAL_ERROR;
NYX 0:85b3fd62ea1a 306 }
NYX 0:85b3fd62ea1a 307 }
NYX 0:85b3fd62ea1a 308 else
NYX 0:85b3fd62ea1a 309 {
NYX 0:85b3fd62ea1a 310 /* Abort foreground CLUT loading if any */
NYX 0:85b3fd62ea1a 311 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
NYX 0:85b3fd62ea1a 312 {
NYX 0:85b3fd62ea1a 313 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
NYX 0:85b3fd62ea1a 314 {
NYX 0:85b3fd62ea1a 315 /* Issue when aborting foreground CLUT loading */
NYX 0:85b3fd62ea1a 316 return HAL_ERROR;
NYX 0:85b3fd62ea1a 317 }
NYX 0:85b3fd62ea1a 318 }
NYX 0:85b3fd62ea1a 319 }
NYX 0:85b3fd62ea1a 320 }
NYX 0:85b3fd62ea1a 321 }
NYX 0:85b3fd62ea1a 322
NYX 0:85b3fd62ea1a 323 /* Carry on with de-initialization of low level hardware */
NYX 0:85b3fd62ea1a 324 HAL_DMA2D_MspDeInit(hdma2d);
NYX 0:85b3fd62ea1a 325
NYX 0:85b3fd62ea1a 326 /* Reset DMA2D control registers*/
NYX 0:85b3fd62ea1a 327 hdma2d->Instance->CR = 0U;
NYX 0:85b3fd62ea1a 328 hdma2d->Instance->FGOR = 0U;
NYX 0:85b3fd62ea1a 329 hdma2d->Instance->BGOR = 0U;
NYX 0:85b3fd62ea1a 330 hdma2d->Instance->FGPFCCR = 0U;
NYX 0:85b3fd62ea1a 331 hdma2d->Instance->BGPFCCR = 0U;
NYX 0:85b3fd62ea1a 332 hdma2d->Instance->OPFCCR = 0U;
NYX 0:85b3fd62ea1a 333
NYX 0:85b3fd62ea1a 334 /* Update error code */
NYX 0:85b3fd62ea1a 335 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
NYX 0:85b3fd62ea1a 336
NYX 0:85b3fd62ea1a 337 /* Initialize the DMA2D state*/
NYX 0:85b3fd62ea1a 338 hdma2d->State = HAL_DMA2D_STATE_RESET;
NYX 0:85b3fd62ea1a 339
NYX 0:85b3fd62ea1a 340 /* Release Lock */
NYX 0:85b3fd62ea1a 341 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 342
NYX 0:85b3fd62ea1a 343 return HAL_OK;
NYX 0:85b3fd62ea1a 344 }
NYX 0:85b3fd62ea1a 345
NYX 0:85b3fd62ea1a 346 /**
NYX 0:85b3fd62ea1a 347 * @brief Initializes the DMA2D MSP.
NYX 0:85b3fd62ea1a 348 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 349 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 350 * @retval None
NYX 0:85b3fd62ea1a 351 */
NYX 0:85b3fd62ea1a 352 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
NYX 0:85b3fd62ea1a 353 {
NYX 0:85b3fd62ea1a 354 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 355 UNUSED(hdma2d);
NYX 0:85b3fd62ea1a 356
NYX 0:85b3fd62ea1a 357 /* NOTE : This function should not be modified; when the callback is needed,
NYX 0:85b3fd62ea1a 358 the HAL_DMA2D_MspInit can be implemented in the user file.
NYX 0:85b3fd62ea1a 359 */
NYX 0:85b3fd62ea1a 360 }
NYX 0:85b3fd62ea1a 361
NYX 0:85b3fd62ea1a 362 /**
NYX 0:85b3fd62ea1a 363 * @brief DeInitializes the DMA2D MSP.
NYX 0:85b3fd62ea1a 364 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 365 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 366 * @retval None
NYX 0:85b3fd62ea1a 367 */
NYX 0:85b3fd62ea1a 368 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
NYX 0:85b3fd62ea1a 369 {
NYX 0:85b3fd62ea1a 370 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 371 UNUSED(hdma2d);
NYX 0:85b3fd62ea1a 372
NYX 0:85b3fd62ea1a 373 /* NOTE : This function should not be modified; when the callback is needed,
NYX 0:85b3fd62ea1a 374 the HAL_DMA2D_MspDeInit can be implemented in the user file.
NYX 0:85b3fd62ea1a 375 */
NYX 0:85b3fd62ea1a 376 }
NYX 0:85b3fd62ea1a 377
NYX 0:85b3fd62ea1a 378 /**
NYX 0:85b3fd62ea1a 379 * @}
NYX 0:85b3fd62ea1a 380 */
NYX 0:85b3fd62ea1a 381
NYX 0:85b3fd62ea1a 382 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
NYX 0:85b3fd62ea1a 383 * @brief IO operation functions
NYX 0:85b3fd62ea1a 384 *
NYX 0:85b3fd62ea1a 385 @verbatim
NYX 0:85b3fd62ea1a 386 ===============================================================================
NYX 0:85b3fd62ea1a 387 ##### IO operation functions #####
NYX 0:85b3fd62ea1a 388 ===============================================================================
NYX 0:85b3fd62ea1a 389 [..] This section provides functions allowing to:
NYX 0:85b3fd62ea1a 390 (+) Configure the pdata, destination address and data size then
NYX 0:85b3fd62ea1a 391 start the DMA2D transfer.
NYX 0:85b3fd62ea1a 392 (+) Configure the source for foreground and background, destination address
NYX 0:85b3fd62ea1a 393 and data size then start a MultiBuffer DMA2D transfer.
NYX 0:85b3fd62ea1a 394 (+) Configure the pdata, destination address and data size then
NYX 0:85b3fd62ea1a 395 start the DMA2D transfer with interrupt.
NYX 0:85b3fd62ea1a 396 (+) Configure the source for foreground and background, destination address
NYX 0:85b3fd62ea1a 397 and data size then start a MultiBuffer DMA2D transfer with interrupt.
NYX 0:85b3fd62ea1a 398 (+) Abort DMA2D transfer.
NYX 0:85b3fd62ea1a 399 (+) Suspend DMA2D transfer.
NYX 0:85b3fd62ea1a 400 (+) Resume DMA2D transfer.
NYX 0:85b3fd62ea1a 401 (+) Enable CLUT transfer.
NYX 0:85b3fd62ea1a 402 (+) Configure CLUT loading then start transfer in polling mode.
NYX 0:85b3fd62ea1a 403 (+) Configure CLUT loading then start transfer in interrupt mode.
NYX 0:85b3fd62ea1a 404 (+) Abort DMA2D CLUT loading.
NYX 0:85b3fd62ea1a 405 (+) Suspend DMA2D CLUT loading.
NYX 0:85b3fd62ea1a 406 (+) Resume DMA2D CLUT loading.
NYX 0:85b3fd62ea1a 407 (+) Poll for transfer complete.
NYX 0:85b3fd62ea1a 408 (+) handle DMA2D interrupt request.
NYX 0:85b3fd62ea1a 409 (+) Transfer watermark callback.
NYX 0:85b3fd62ea1a 410 (+) CLUT Transfer Complete callback.
NYX 0:85b3fd62ea1a 411
NYX 0:85b3fd62ea1a 412 @endverbatim
NYX 0:85b3fd62ea1a 413 * @{
NYX 0:85b3fd62ea1a 414 */
NYX 0:85b3fd62ea1a 415
NYX 0:85b3fd62ea1a 416 /**
NYX 0:85b3fd62ea1a 417 * @brief Start the DMA2D Transfer.
NYX 0:85b3fd62ea1a 418 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 419 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 420 * @param pdata: Configure the source memory Buffer address if
NYX 0:85b3fd62ea1a 421 * Memory-to-Memory or Memory-to-Memory with pixel format
NYX 0:85b3fd62ea1a 422 * conversion mode is selected, or configure
NYX 0:85b3fd62ea1a 423 * the color value if Register-to-Memory mode is selected.
NYX 0:85b3fd62ea1a 424 * @param DstAddress: The destination memory Buffer address.
NYX 0:85b3fd62ea1a 425 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
NYX 0:85b3fd62ea1a 426 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
NYX 0:85b3fd62ea1a 427 * @retval HAL status
NYX 0:85b3fd62ea1a 428 */
NYX 0:85b3fd62ea1a 429 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
NYX 0:85b3fd62ea1a 430 {
NYX 0:85b3fd62ea1a 431 /* Check the parameters */
NYX 0:85b3fd62ea1a 432 assert_param(IS_DMA2D_LINE(Height));
NYX 0:85b3fd62ea1a 433 assert_param(IS_DMA2D_PIXEL(Width));
NYX 0:85b3fd62ea1a 434
NYX 0:85b3fd62ea1a 435 /* Process locked */
NYX 0:85b3fd62ea1a 436 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 437
NYX 0:85b3fd62ea1a 438 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 439 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 440
NYX 0:85b3fd62ea1a 441 /* Configure the source, destination address and the data size */
NYX 0:85b3fd62ea1a 442 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
NYX 0:85b3fd62ea1a 443
NYX 0:85b3fd62ea1a 444 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 445 __HAL_DMA2D_ENABLE(hdma2d);
NYX 0:85b3fd62ea1a 446
NYX 0:85b3fd62ea1a 447 return HAL_OK;
NYX 0:85b3fd62ea1a 448 }
NYX 0:85b3fd62ea1a 449
NYX 0:85b3fd62ea1a 450 /**
NYX 0:85b3fd62ea1a 451 * @brief Start the DMA2D Transfer with interrupt enabled.
NYX 0:85b3fd62ea1a 452 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 453 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 454 * @param pdata: Configure the source memory Buffer address if
NYX 0:85b3fd62ea1a 455 * the Memory-to-Memory or Memory-to-Memory with pixel format
NYX 0:85b3fd62ea1a 456 * conversion mode is selected, or configure
NYX 0:85b3fd62ea1a 457 * the color value if Register-to-Memory mode is selected.
NYX 0:85b3fd62ea1a 458 * @param DstAddress: The destination memory Buffer address.
NYX 0:85b3fd62ea1a 459 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
NYX 0:85b3fd62ea1a 460 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
NYX 0:85b3fd62ea1a 461 * @retval HAL status
NYX 0:85b3fd62ea1a 462 */
NYX 0:85b3fd62ea1a 463 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
NYX 0:85b3fd62ea1a 464 {
NYX 0:85b3fd62ea1a 465 /* Check the parameters */
NYX 0:85b3fd62ea1a 466 assert_param(IS_DMA2D_LINE(Height));
NYX 0:85b3fd62ea1a 467 assert_param(IS_DMA2D_PIXEL(Width));
NYX 0:85b3fd62ea1a 468
NYX 0:85b3fd62ea1a 469 /* Process locked */
NYX 0:85b3fd62ea1a 470 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 471
NYX 0:85b3fd62ea1a 472 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 473 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 474
NYX 0:85b3fd62ea1a 475 /* Configure the source, destination address and the data size */
NYX 0:85b3fd62ea1a 476 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
NYX 0:85b3fd62ea1a 477
NYX 0:85b3fd62ea1a 478 /* Enable the transfer complete, transfer error and configuration error interrupts */
NYX 0:85b3fd62ea1a 479 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
NYX 0:85b3fd62ea1a 480
NYX 0:85b3fd62ea1a 481 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 482 __HAL_DMA2D_ENABLE(hdma2d);
NYX 0:85b3fd62ea1a 483
NYX 0:85b3fd62ea1a 484 return HAL_OK;
NYX 0:85b3fd62ea1a 485 }
NYX 0:85b3fd62ea1a 486
NYX 0:85b3fd62ea1a 487 /**
NYX 0:85b3fd62ea1a 488 * @brief Start the multi-source DMA2D Transfer.
NYX 0:85b3fd62ea1a 489 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 490 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 491 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
NYX 0:85b3fd62ea1a 492 * @param SrcAddress2: The source memory Buffer address for the background layer.
NYX 0:85b3fd62ea1a 493 * @param DstAddress: The destination memory Buffer address.
NYX 0:85b3fd62ea1a 494 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
NYX 0:85b3fd62ea1a 495 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
NYX 0:85b3fd62ea1a 496 * @retval HAL status
NYX 0:85b3fd62ea1a 497 */
NYX 0:85b3fd62ea1a 498 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
NYX 0:85b3fd62ea1a 499 {
NYX 0:85b3fd62ea1a 500 /* Check the parameters */
NYX 0:85b3fd62ea1a 501 assert_param(IS_DMA2D_LINE(Height));
NYX 0:85b3fd62ea1a 502 assert_param(IS_DMA2D_PIXEL(Width));
NYX 0:85b3fd62ea1a 503
NYX 0:85b3fd62ea1a 504 /* Process locked */
NYX 0:85b3fd62ea1a 505 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 506
NYX 0:85b3fd62ea1a 507 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 508 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 509
NYX 0:85b3fd62ea1a 510 /* Configure DMA2D Stream source2 address */
NYX 0:85b3fd62ea1a 511 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
NYX 0:85b3fd62ea1a 512
NYX 0:85b3fd62ea1a 513 /* Configure the source, destination address and the data size */
NYX 0:85b3fd62ea1a 514 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
NYX 0:85b3fd62ea1a 515
NYX 0:85b3fd62ea1a 516 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 517 __HAL_DMA2D_ENABLE(hdma2d);
NYX 0:85b3fd62ea1a 518
NYX 0:85b3fd62ea1a 519 return HAL_OK;
NYX 0:85b3fd62ea1a 520 }
NYX 0:85b3fd62ea1a 521
NYX 0:85b3fd62ea1a 522 /**
NYX 0:85b3fd62ea1a 523 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
NYX 0:85b3fd62ea1a 524 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 525 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 526 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
NYX 0:85b3fd62ea1a 527 * @param SrcAddress2: The source memory Buffer address for the background layer.
NYX 0:85b3fd62ea1a 528 * @param DstAddress: The destination memory Buffer address.
NYX 0:85b3fd62ea1a 529 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
NYX 0:85b3fd62ea1a 530 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
NYX 0:85b3fd62ea1a 531 * @retval HAL status
NYX 0:85b3fd62ea1a 532 */
NYX 0:85b3fd62ea1a 533 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
NYX 0:85b3fd62ea1a 534 {
NYX 0:85b3fd62ea1a 535 /* Check the parameters */
NYX 0:85b3fd62ea1a 536 assert_param(IS_DMA2D_LINE(Height));
NYX 0:85b3fd62ea1a 537 assert_param(IS_DMA2D_PIXEL(Width));
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 /* Process locked */
NYX 0:85b3fd62ea1a 540 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 541
NYX 0:85b3fd62ea1a 542 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 543 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 544
NYX 0:85b3fd62ea1a 545 /* Configure DMA2D Stream source2 address */
NYX 0:85b3fd62ea1a 546 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
NYX 0:85b3fd62ea1a 547
NYX 0:85b3fd62ea1a 548 /* Configure the source, destination address and the data size */
NYX 0:85b3fd62ea1a 549 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
NYX 0:85b3fd62ea1a 550
NYX 0:85b3fd62ea1a 551 /* Enable the transfer complete, transfer error and configuration error interrupts */
NYX 0:85b3fd62ea1a 552 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
NYX 0:85b3fd62ea1a 553
NYX 0:85b3fd62ea1a 554 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 555 __HAL_DMA2D_ENABLE(hdma2d);
NYX 0:85b3fd62ea1a 556
NYX 0:85b3fd62ea1a 557 return HAL_OK;
NYX 0:85b3fd62ea1a 558 }
NYX 0:85b3fd62ea1a 559
NYX 0:85b3fd62ea1a 560 /**
NYX 0:85b3fd62ea1a 561 * @brief Abort the DMA2D Transfer.
NYX 0:85b3fd62ea1a 562 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 563 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 564 * @retval HAL status
NYX 0:85b3fd62ea1a 565 */
NYX 0:85b3fd62ea1a 566 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 567 {
NYX 0:85b3fd62ea1a 568 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 569
NYX 0:85b3fd62ea1a 570 /* Abort the DMA2D transfer */
NYX 0:85b3fd62ea1a 571 /* START bit is reset to make sure not to set it again, in the event the HW clears it
NYX 0:85b3fd62ea1a 572 between the register read and the register write by the CPU (writing 0 has no
NYX 0:85b3fd62ea1a 573 effect on START bitvalue) */
NYX 0:85b3fd62ea1a 574 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
NYX 0:85b3fd62ea1a 575
NYX 0:85b3fd62ea1a 576 /* Get tick */
NYX 0:85b3fd62ea1a 577 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 578
NYX 0:85b3fd62ea1a 579 /* Check if the DMA2D is effectively disabled */
NYX 0:85b3fd62ea1a 580 while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
NYX 0:85b3fd62ea1a 581 {
NYX 0:85b3fd62ea1a 582 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
NYX 0:85b3fd62ea1a 583 {
NYX 0:85b3fd62ea1a 584 /* Update error code */
NYX 0:85b3fd62ea1a 585 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
NYX 0:85b3fd62ea1a 586
NYX 0:85b3fd62ea1a 587 /* Change the DMA2D state */
NYX 0:85b3fd62ea1a 588 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
NYX 0:85b3fd62ea1a 589
NYX 0:85b3fd62ea1a 590 /* Process Unlocked */
NYX 0:85b3fd62ea1a 591 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 592
NYX 0:85b3fd62ea1a 593 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 594 }
NYX 0:85b3fd62ea1a 595 }
NYX 0:85b3fd62ea1a 596
NYX 0:85b3fd62ea1a 597 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
NYX 0:85b3fd62ea1a 598 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
NYX 0:85b3fd62ea1a 599
NYX 0:85b3fd62ea1a 600 /* Change the DMA2D state*/
NYX 0:85b3fd62ea1a 601 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 602
NYX 0:85b3fd62ea1a 603 /* Process Unlocked */
NYX 0:85b3fd62ea1a 604 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 605
NYX 0:85b3fd62ea1a 606 return HAL_OK;
NYX 0:85b3fd62ea1a 607 }
NYX 0:85b3fd62ea1a 608
NYX 0:85b3fd62ea1a 609 /**
NYX 0:85b3fd62ea1a 610 * @brief Suspend the DMA2D Transfer.
NYX 0:85b3fd62ea1a 611 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 612 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 613 * @retval HAL status
NYX 0:85b3fd62ea1a 614 */
NYX 0:85b3fd62ea1a 615 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 616 {
NYX 0:85b3fd62ea1a 617 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 618
NYX 0:85b3fd62ea1a 619 /* Suspend the DMA2D transfer */
NYX 0:85b3fd62ea1a 620 /* START bit is reset to make sure not to set it again, in the event the HW clears it
NYX 0:85b3fd62ea1a 621 between the register read and the register write by the CPU (writing 0 has no
NYX 0:85b3fd62ea1a 622 effect on START bitvalue) */
NYX 0:85b3fd62ea1a 623 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
NYX 0:85b3fd62ea1a 624
NYX 0:85b3fd62ea1a 625 /* Get tick */
NYX 0:85b3fd62ea1a 626 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 627
NYX 0:85b3fd62ea1a 628 /* Check if the DMA2D is effectively suspended */
NYX 0:85b3fd62ea1a 629 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
NYX 0:85b3fd62ea1a 630 && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
NYX 0:85b3fd62ea1a 631 {
NYX 0:85b3fd62ea1a 632 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
NYX 0:85b3fd62ea1a 633 {
NYX 0:85b3fd62ea1a 634 /* Update error code */
NYX 0:85b3fd62ea1a 635 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
NYX 0:85b3fd62ea1a 636
NYX 0:85b3fd62ea1a 637 /* Change the DMA2D state */
NYX 0:85b3fd62ea1a 638 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
NYX 0:85b3fd62ea1a 639
NYX 0:85b3fd62ea1a 640 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 641 }
NYX 0:85b3fd62ea1a 642 }
NYX 0:85b3fd62ea1a 643
NYX 0:85b3fd62ea1a 644 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
NYX 0:85b3fd62ea1a 645 if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
NYX 0:85b3fd62ea1a 646 {
NYX 0:85b3fd62ea1a 647 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
NYX 0:85b3fd62ea1a 648 }
NYX 0:85b3fd62ea1a 649 else
NYX 0:85b3fd62ea1a 650 {
NYX 0:85b3fd62ea1a 651 /* Make sure SUSP bit is cleared since it is meaningless
NYX 0:85b3fd62ea1a 652 when no tranfer is on-going */
NYX 0:85b3fd62ea1a 653 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
NYX 0:85b3fd62ea1a 654 }
NYX 0:85b3fd62ea1a 655
NYX 0:85b3fd62ea1a 656 return HAL_OK;
NYX 0:85b3fd62ea1a 657 }
NYX 0:85b3fd62ea1a 658
NYX 0:85b3fd62ea1a 659 /**
NYX 0:85b3fd62ea1a 660 * @brief Resume the DMA2D Transfer.
NYX 0:85b3fd62ea1a 661 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 662 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 663 * @retval HAL status
NYX 0:85b3fd62ea1a 664 */
NYX 0:85b3fd62ea1a 665 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 666 {
NYX 0:85b3fd62ea1a 667 /* Check the SUSP and START bits */
NYX 0:85b3fd62ea1a 668 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
NYX 0:85b3fd62ea1a 669 {
NYX 0:85b3fd62ea1a 670 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
NYX 0:85b3fd62ea1a 671 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 672 }
NYX 0:85b3fd62ea1a 673
NYX 0:85b3fd62ea1a 674 /* Resume the DMA2D transfer */
NYX 0:85b3fd62ea1a 675 /* START bit is reset to make sure not to set it again, in the event the HW clears it
NYX 0:85b3fd62ea1a 676 between the register read and the register write by the CPU (writing 0 has no
NYX 0:85b3fd62ea1a 677 effect on START bitvalue) */
NYX 0:85b3fd62ea1a 678 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
NYX 0:85b3fd62ea1a 679
NYX 0:85b3fd62ea1a 680 return HAL_OK;
NYX 0:85b3fd62ea1a 681 }
NYX 0:85b3fd62ea1a 682
NYX 0:85b3fd62ea1a 683 /**
NYX 0:85b3fd62ea1a 684 * @brief Enable the DMA2D CLUT Transfer.
NYX 0:85b3fd62ea1a 685 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 686 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 687 * @param LayerIdx: DMA2D Layer index.
NYX 0:85b3fd62ea1a 688 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 689 * 0(background) / 1(foreground)
NYX 0:85b3fd62ea1a 690 * @retval HAL status
NYX 0:85b3fd62ea1a 691 */
NYX 0:85b3fd62ea1a 692 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
NYX 0:85b3fd62ea1a 693 {
NYX 0:85b3fd62ea1a 694 /* Check the parameters */
NYX 0:85b3fd62ea1a 695 assert_param(IS_DMA2D_LAYER(LayerIdx));
NYX 0:85b3fd62ea1a 696
NYX 0:85b3fd62ea1a 697 /* Process locked */
NYX 0:85b3fd62ea1a 698 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 699
NYX 0:85b3fd62ea1a 700 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 701 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 702
NYX 0:85b3fd62ea1a 703 if(LayerIdx == 0U)
NYX 0:85b3fd62ea1a 704 {
NYX 0:85b3fd62ea1a 705 /* Enable the background CLUT loading */
NYX 0:85b3fd62ea1a 706 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
NYX 0:85b3fd62ea1a 707 }
NYX 0:85b3fd62ea1a 708 else
NYX 0:85b3fd62ea1a 709 {
NYX 0:85b3fd62ea1a 710 /* Enable the foreground CLUT loading */
NYX 0:85b3fd62ea1a 711 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
NYX 0:85b3fd62ea1a 712 }
NYX 0:85b3fd62ea1a 713
NYX 0:85b3fd62ea1a 714 return HAL_OK;
NYX 0:85b3fd62ea1a 715 }
NYX 0:85b3fd62ea1a 716
NYX 0:85b3fd62ea1a 717 /**
NYX 0:85b3fd62ea1a 718 * @brief Start DMA2D CLUT Loading.
NYX 0:85b3fd62ea1a 719 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 720 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 721 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
NYX 0:85b3fd62ea1a 722 * the configuration information for the color look up table.
NYX 0:85b3fd62ea1a 723 * @param LayerIdx: DMA2D Layer index.
NYX 0:85b3fd62ea1a 724 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 725 * 0(background) / 1(foreground)
NYX 0:85b3fd62ea1a 726 * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
NYX 0:85b3fd62ea1a 727 * @retval HAL status
NYX 0:85b3fd62ea1a 728 */
NYX 0:85b3fd62ea1a 729 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
NYX 0:85b3fd62ea1a 730 {
NYX 0:85b3fd62ea1a 731 /* Check the parameters */
NYX 0:85b3fd62ea1a 732 assert_param(IS_DMA2D_LAYER(LayerIdx));
NYX 0:85b3fd62ea1a 733 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
NYX 0:85b3fd62ea1a 734 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
NYX 0:85b3fd62ea1a 735
NYX 0:85b3fd62ea1a 736 /* Process locked */
NYX 0:85b3fd62ea1a 737 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 738
NYX 0:85b3fd62ea1a 739 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 740 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 741
NYX 0:85b3fd62ea1a 742 /* Configure the CLUT of the background DMA2D layer */
NYX 0:85b3fd62ea1a 743 if(LayerIdx == 0U)
NYX 0:85b3fd62ea1a 744 {
NYX 0:85b3fd62ea1a 745 /* Write background CLUT memory address */
NYX 0:85b3fd62ea1a 746 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
NYX 0:85b3fd62ea1a 747
NYX 0:85b3fd62ea1a 748 /* Write background CLUT size and CLUT color mode */
NYX 0:85b3fd62ea1a 749 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
NYX 0:85b3fd62ea1a 750 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
NYX 0:85b3fd62ea1a 751
NYX 0:85b3fd62ea1a 752 /* Enable the CLUT loading for the background */
NYX 0:85b3fd62ea1a 753 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
NYX 0:85b3fd62ea1a 754 }
NYX 0:85b3fd62ea1a 755 /* Configure the CLUT of the foreground DMA2D layer */
NYX 0:85b3fd62ea1a 756 else
NYX 0:85b3fd62ea1a 757 {
NYX 0:85b3fd62ea1a 758 /* Write foreground CLUT memory address */
NYX 0:85b3fd62ea1a 759 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
NYX 0:85b3fd62ea1a 760
NYX 0:85b3fd62ea1a 761 /* Write foreground CLUT size and CLUT color mode */
NYX 0:85b3fd62ea1a 762 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
NYX 0:85b3fd62ea1a 763 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
NYX 0:85b3fd62ea1a 764
NYX 0:85b3fd62ea1a 765 /* Enable the CLUT loading for the foreground */
NYX 0:85b3fd62ea1a 766 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
NYX 0:85b3fd62ea1a 767 }
NYX 0:85b3fd62ea1a 768
NYX 0:85b3fd62ea1a 769 return HAL_OK;
NYX 0:85b3fd62ea1a 770 }
NYX 0:85b3fd62ea1a 771
NYX 0:85b3fd62ea1a 772 /**
NYX 0:85b3fd62ea1a 773 * @brief Start DMA2D CLUT Loading with interrupt enabled.
NYX 0:85b3fd62ea1a 774 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 775 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 776 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
NYX 0:85b3fd62ea1a 777 * the configuration information for the color look up table.
NYX 0:85b3fd62ea1a 778 * @param LayerIdx: DMA2D Layer index.
NYX 0:85b3fd62ea1a 779 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 780 * 0(background) / 1(foreground)
NYX 0:85b3fd62ea1a 781 * @retval HAL status
NYX 0:85b3fd62ea1a 782 */
NYX 0:85b3fd62ea1a 783 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
NYX 0:85b3fd62ea1a 784 {
NYX 0:85b3fd62ea1a 785 /* Check the parameters */
NYX 0:85b3fd62ea1a 786 assert_param(IS_DMA2D_LAYER(LayerIdx));
NYX 0:85b3fd62ea1a 787 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
NYX 0:85b3fd62ea1a 788 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
NYX 0:85b3fd62ea1a 789
NYX 0:85b3fd62ea1a 790 /* Process locked */
NYX 0:85b3fd62ea1a 791 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 792
NYX 0:85b3fd62ea1a 793 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 794 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 795
NYX 0:85b3fd62ea1a 796 /* Configure the CLUT of the background DMA2D layer */
NYX 0:85b3fd62ea1a 797 if(LayerIdx == 0U)
NYX 0:85b3fd62ea1a 798 {
NYX 0:85b3fd62ea1a 799 /* Write background CLUT memory address */
NYX 0:85b3fd62ea1a 800 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
NYX 0:85b3fd62ea1a 801
NYX 0:85b3fd62ea1a 802 /* Write background CLUT size and CLUT color mode */
NYX 0:85b3fd62ea1a 803 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
NYX 0:85b3fd62ea1a 804 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
NYX 0:85b3fd62ea1a 805
NYX 0:85b3fd62ea1a 806 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
NYX 0:85b3fd62ea1a 807 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
NYX 0:85b3fd62ea1a 808
NYX 0:85b3fd62ea1a 809 /* Enable the CLUT loading for the background */
NYX 0:85b3fd62ea1a 810 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
NYX 0:85b3fd62ea1a 811 }
NYX 0:85b3fd62ea1a 812 /* Configure the CLUT of the foreground DMA2D layer */
NYX 0:85b3fd62ea1a 813 else
NYX 0:85b3fd62ea1a 814 {
NYX 0:85b3fd62ea1a 815 /* Write foreground CLUT memory address */
NYX 0:85b3fd62ea1a 816 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
NYX 0:85b3fd62ea1a 817
NYX 0:85b3fd62ea1a 818 /* Write foreground CLUT size and CLUT color mode */
NYX 0:85b3fd62ea1a 819 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
NYX 0:85b3fd62ea1a 820 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
NYX 0:85b3fd62ea1a 821
NYX 0:85b3fd62ea1a 822 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
NYX 0:85b3fd62ea1a 823 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
NYX 0:85b3fd62ea1a 824
NYX 0:85b3fd62ea1a 825 /* Enable the CLUT loading for the foreground */
NYX 0:85b3fd62ea1a 826 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
NYX 0:85b3fd62ea1a 827 }
NYX 0:85b3fd62ea1a 828
NYX 0:85b3fd62ea1a 829 return HAL_OK;
NYX 0:85b3fd62ea1a 830 }
NYX 0:85b3fd62ea1a 831
NYX 0:85b3fd62ea1a 832 /**
NYX 0:85b3fd62ea1a 833 * @brief Abort the DMA2D CLUT loading.
NYX 0:85b3fd62ea1a 834 * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 835 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 836 * @param LayerIdx: DMA2D Layer index.
NYX 0:85b3fd62ea1a 837 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 838 * 0(background) / 1(foreground)
NYX 0:85b3fd62ea1a 839 * @retval HAL status
NYX 0:85b3fd62ea1a 840 */
NYX 0:85b3fd62ea1a 841 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
NYX 0:85b3fd62ea1a 842 {
NYX 0:85b3fd62ea1a 843 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 844 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
NYX 0:85b3fd62ea1a 845
NYX 0:85b3fd62ea1a 846 /* Abort the CLUT loading */
NYX 0:85b3fd62ea1a 847 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
NYX 0:85b3fd62ea1a 848
NYX 0:85b3fd62ea1a 849 /* If foreground CLUT loading is considered, update local variables */
NYX 0:85b3fd62ea1a 850 if(LayerIdx == 1)
NYX 0:85b3fd62ea1a 851 {
NYX 0:85b3fd62ea1a 852 reg = &(hdma2d->Instance->FGPFCCR);
NYX 0:85b3fd62ea1a 853 }
NYX 0:85b3fd62ea1a 854
NYX 0:85b3fd62ea1a 855 /* Get tick */
NYX 0:85b3fd62ea1a 856 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 857
NYX 0:85b3fd62ea1a 858 /* Check if the CLUT loading is aborted */
NYX 0:85b3fd62ea1a 859 while((*reg & DMA2D_BGPFCCR_START) != RESET)
NYX 0:85b3fd62ea1a 860 {
NYX 0:85b3fd62ea1a 861 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
NYX 0:85b3fd62ea1a 862 {
NYX 0:85b3fd62ea1a 863 /* Update error code */
NYX 0:85b3fd62ea1a 864 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
NYX 0:85b3fd62ea1a 865
NYX 0:85b3fd62ea1a 866 /* Change the DMA2D state */
NYX 0:85b3fd62ea1a 867 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
NYX 0:85b3fd62ea1a 868
NYX 0:85b3fd62ea1a 869 /* Process Unlocked */
NYX 0:85b3fd62ea1a 870 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 871
NYX 0:85b3fd62ea1a 872 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 873 }
NYX 0:85b3fd62ea1a 874 }
NYX 0:85b3fd62ea1a 875
NYX 0:85b3fd62ea1a 876 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
NYX 0:85b3fd62ea1a 877 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
NYX 0:85b3fd62ea1a 878
NYX 0:85b3fd62ea1a 879 /* Change the DMA2D state*/
NYX 0:85b3fd62ea1a 880 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 881
NYX 0:85b3fd62ea1a 882 /* Process Unlocked */
NYX 0:85b3fd62ea1a 883 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 884
NYX 0:85b3fd62ea1a 885 return HAL_OK;
NYX 0:85b3fd62ea1a 886 }
NYX 0:85b3fd62ea1a 887
NYX 0:85b3fd62ea1a 888 /**
NYX 0:85b3fd62ea1a 889 * @brief Suspend the DMA2D CLUT loading.
NYX 0:85b3fd62ea1a 890 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 891 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 892 * @param LayerIdx: DMA2D Layer index.
NYX 0:85b3fd62ea1a 893 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 894 * 0(background) / 1(foreground)
NYX 0:85b3fd62ea1a 895 * @retval HAL status
NYX 0:85b3fd62ea1a 896 */
NYX 0:85b3fd62ea1a 897 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
NYX 0:85b3fd62ea1a 898 {
NYX 0:85b3fd62ea1a 899 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 900 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
NYX 0:85b3fd62ea1a 901
NYX 0:85b3fd62ea1a 902 /* Suspend the CLUT loading */
NYX 0:85b3fd62ea1a 903 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
NYX 0:85b3fd62ea1a 904
NYX 0:85b3fd62ea1a 905 /* If foreground CLUT loading is considered, update local variables */
NYX 0:85b3fd62ea1a 906 if(LayerIdx == 1U)
NYX 0:85b3fd62ea1a 907 {
NYX 0:85b3fd62ea1a 908 reg = &(hdma2d->Instance->FGPFCCR);
NYX 0:85b3fd62ea1a 909 }
NYX 0:85b3fd62ea1a 910
NYX 0:85b3fd62ea1a 911 /* Get tick */
NYX 0:85b3fd62ea1a 912 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 913
NYX 0:85b3fd62ea1a 914 /* Check if the CLUT loading is suspended */
NYX 0:85b3fd62ea1a 915 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
NYX 0:85b3fd62ea1a 916 && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
NYX 0:85b3fd62ea1a 917 {
NYX 0:85b3fd62ea1a 918 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
NYX 0:85b3fd62ea1a 919 {
NYX 0:85b3fd62ea1a 920 /* Update error code */
NYX 0:85b3fd62ea1a 921 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
NYX 0:85b3fd62ea1a 922
NYX 0:85b3fd62ea1a 923 /* Change the DMA2D state */
NYX 0:85b3fd62ea1a 924 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
NYX 0:85b3fd62ea1a 925
NYX 0:85b3fd62ea1a 926 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 927 }
NYX 0:85b3fd62ea1a 928 }
NYX 0:85b3fd62ea1a 929
NYX 0:85b3fd62ea1a 930 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
NYX 0:85b3fd62ea1a 931 if ((*reg & DMA2D_BGPFCCR_START) != RESET)
NYX 0:85b3fd62ea1a 932 {
NYX 0:85b3fd62ea1a 933 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
NYX 0:85b3fd62ea1a 934 }
NYX 0:85b3fd62ea1a 935 else
NYX 0:85b3fd62ea1a 936 {
NYX 0:85b3fd62ea1a 937 /* Make sure SUSP bit is cleared since it is meaningless
NYX 0:85b3fd62ea1a 938 when no tranfer is on-going */
NYX 0:85b3fd62ea1a 939 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
NYX 0:85b3fd62ea1a 940 }
NYX 0:85b3fd62ea1a 941
NYX 0:85b3fd62ea1a 942 return HAL_OK;
NYX 0:85b3fd62ea1a 943 }
NYX 0:85b3fd62ea1a 944
NYX 0:85b3fd62ea1a 945 /**
NYX 0:85b3fd62ea1a 946 * @brief Resume the DMA2D CLUT loading.
NYX 0:85b3fd62ea1a 947 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 948 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 949 * @param LayerIdx: DMA2D Layer index.
NYX 0:85b3fd62ea1a 950 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 951 * 0(background) / 1(foreground)
NYX 0:85b3fd62ea1a 952 * @retval HAL status
NYX 0:85b3fd62ea1a 953 */
NYX 0:85b3fd62ea1a 954 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
NYX 0:85b3fd62ea1a 955 {
NYX 0:85b3fd62ea1a 956 /* Check the SUSP and START bits for background or foreground CLUT loading */
NYX 0:85b3fd62ea1a 957 if(LayerIdx == 0U)
NYX 0:85b3fd62ea1a 958 {
NYX 0:85b3fd62ea1a 959 /* Background CLUT loading suspension check */
NYX 0:85b3fd62ea1a 960 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
NYX 0:85b3fd62ea1a 961 && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
NYX 0:85b3fd62ea1a 962 {
NYX 0:85b3fd62ea1a 963 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
NYX 0:85b3fd62ea1a 964 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 965 }
NYX 0:85b3fd62ea1a 966 }
NYX 0:85b3fd62ea1a 967 else
NYX 0:85b3fd62ea1a 968 {
NYX 0:85b3fd62ea1a 969 /* Foreground CLUT loading suspension check */
NYX 0:85b3fd62ea1a 970 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
NYX 0:85b3fd62ea1a 971 && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
NYX 0:85b3fd62ea1a 972 {
NYX 0:85b3fd62ea1a 973 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
NYX 0:85b3fd62ea1a 974 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 975 }
NYX 0:85b3fd62ea1a 976 }
NYX 0:85b3fd62ea1a 977
NYX 0:85b3fd62ea1a 978 /* Resume the CLUT loading */
NYX 0:85b3fd62ea1a 979 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
NYX 0:85b3fd62ea1a 980
NYX 0:85b3fd62ea1a 981 return HAL_OK;
NYX 0:85b3fd62ea1a 982 }
NYX 0:85b3fd62ea1a 983
NYX 0:85b3fd62ea1a 984 /**
NYX 0:85b3fd62ea1a 985 * @brief Polling for transfer complete or CLUT loading.
NYX 0:85b3fd62ea1a 986 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 987 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 988 * @param Timeout: Timeout duration
NYX 0:85b3fd62ea1a 989 * @retval HAL status
NYX 0:85b3fd62ea1a 990 */
NYX 0:85b3fd62ea1a 991 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
NYX 0:85b3fd62ea1a 992 {
NYX 0:85b3fd62ea1a 993 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 994 __IO uint32_t isrflags = 0x0U;
NYX 0:85b3fd62ea1a 995
NYX 0:85b3fd62ea1a 996 /* Polling for DMA2D transfer */
NYX 0:85b3fd62ea1a 997 if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
NYX 0:85b3fd62ea1a 998 {
NYX 0:85b3fd62ea1a 999 /* Get tick */
NYX 0:85b3fd62ea1a 1000 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1001
NYX 0:85b3fd62ea1a 1002 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
NYX 0:85b3fd62ea1a 1003 {
NYX 0:85b3fd62ea1a 1004 isrflags = READ_REG(hdma2d->Instance->ISR);
NYX 0:85b3fd62ea1a 1005 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
NYX 0:85b3fd62ea1a 1006 {
NYX 0:85b3fd62ea1a 1007 if ((isrflags & DMA2D_FLAG_CE) != RESET)
NYX 0:85b3fd62ea1a 1008 {
NYX 0:85b3fd62ea1a 1009 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
NYX 0:85b3fd62ea1a 1010 }
NYX 0:85b3fd62ea1a 1011 if ((isrflags & DMA2D_FLAG_TE) != RESET)
NYX 0:85b3fd62ea1a 1012 {
NYX 0:85b3fd62ea1a 1013 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
NYX 0:85b3fd62ea1a 1014 }
NYX 0:85b3fd62ea1a 1015 /* Clear the transfer and configuration error flags */
NYX 0:85b3fd62ea1a 1016 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
NYX 0:85b3fd62ea1a 1017
NYX 0:85b3fd62ea1a 1018 /* Change DMA2D state */
NYX 0:85b3fd62ea1a 1019 hdma2d->State = HAL_DMA2D_STATE_ERROR;
NYX 0:85b3fd62ea1a 1020
NYX 0:85b3fd62ea1a 1021 /* Process unlocked */
NYX 0:85b3fd62ea1a 1022 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1023
NYX 0:85b3fd62ea1a 1024 return HAL_ERROR;
NYX 0:85b3fd62ea1a 1025 }
NYX 0:85b3fd62ea1a 1026 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1027 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 1028 {
NYX 0:85b3fd62ea1a 1029 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
NYX 0:85b3fd62ea1a 1030 {
NYX 0:85b3fd62ea1a 1031 /* Update error code */
NYX 0:85b3fd62ea1a 1032 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
NYX 0:85b3fd62ea1a 1033
NYX 0:85b3fd62ea1a 1034 /* Change the DMA2D state */
NYX 0:85b3fd62ea1a 1035 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
NYX 0:85b3fd62ea1a 1036
NYX 0:85b3fd62ea1a 1037 /* Process unlocked */
NYX 0:85b3fd62ea1a 1038 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1039
NYX 0:85b3fd62ea1a 1040 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1041 }
NYX 0:85b3fd62ea1a 1042 }
NYX 0:85b3fd62ea1a 1043 }
NYX 0:85b3fd62ea1a 1044 }
NYX 0:85b3fd62ea1a 1045 /* Polling for CLUT loading (foreground or background) */
NYX 0:85b3fd62ea1a 1046 if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
NYX 0:85b3fd62ea1a 1047 ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
NYX 0:85b3fd62ea1a 1048 {
NYX 0:85b3fd62ea1a 1049 /* Get tick */
NYX 0:85b3fd62ea1a 1050 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1051
NYX 0:85b3fd62ea1a 1052 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
NYX 0:85b3fd62ea1a 1053 {
NYX 0:85b3fd62ea1a 1054 isrflags = READ_REG(hdma2d->Instance->ISR);
NYX 0:85b3fd62ea1a 1055 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
NYX 0:85b3fd62ea1a 1056 {
NYX 0:85b3fd62ea1a 1057 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
NYX 0:85b3fd62ea1a 1058 {
NYX 0:85b3fd62ea1a 1059 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
NYX 0:85b3fd62ea1a 1060 }
NYX 0:85b3fd62ea1a 1061 if ((isrflags & DMA2D_FLAG_CE) != RESET)
NYX 0:85b3fd62ea1a 1062 {
NYX 0:85b3fd62ea1a 1063 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
NYX 0:85b3fd62ea1a 1064 }
NYX 0:85b3fd62ea1a 1065 if ((isrflags & DMA2D_FLAG_TE) != RESET)
NYX 0:85b3fd62ea1a 1066 {
NYX 0:85b3fd62ea1a 1067 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
NYX 0:85b3fd62ea1a 1068 }
NYX 0:85b3fd62ea1a 1069 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
NYX 0:85b3fd62ea1a 1070 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
NYX 0:85b3fd62ea1a 1071
NYX 0:85b3fd62ea1a 1072 /* Change DMA2D state */
NYX 0:85b3fd62ea1a 1073 hdma2d->State= HAL_DMA2D_STATE_ERROR;
NYX 0:85b3fd62ea1a 1074
NYX 0:85b3fd62ea1a 1075 /* Process unlocked */
NYX 0:85b3fd62ea1a 1076 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1077
NYX 0:85b3fd62ea1a 1078 return HAL_ERROR;
NYX 0:85b3fd62ea1a 1079 }
NYX 0:85b3fd62ea1a 1080 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1081 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 1082 {
NYX 0:85b3fd62ea1a 1083 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
NYX 0:85b3fd62ea1a 1084 {
NYX 0:85b3fd62ea1a 1085 /* Update error code */
NYX 0:85b3fd62ea1a 1086 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
NYX 0:85b3fd62ea1a 1087
NYX 0:85b3fd62ea1a 1088 /* Change the DMA2D state */
NYX 0:85b3fd62ea1a 1089 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
NYX 0:85b3fd62ea1a 1090
NYX 0:85b3fd62ea1a 1091 /* Process unlocked */
NYX 0:85b3fd62ea1a 1092 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1093
NYX 0:85b3fd62ea1a 1094 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1095 }
NYX 0:85b3fd62ea1a 1096 }
NYX 0:85b3fd62ea1a 1097 }
NYX 0:85b3fd62ea1a 1098 }
NYX 0:85b3fd62ea1a 1099
NYX 0:85b3fd62ea1a 1100 /* Clear the transfer complete and CLUT loading flags */
NYX 0:85b3fd62ea1a 1101 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
NYX 0:85b3fd62ea1a 1102
NYX 0:85b3fd62ea1a 1103 /* Change DMA2D state */
NYX 0:85b3fd62ea1a 1104 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 1105
NYX 0:85b3fd62ea1a 1106 /* Process unlocked */
NYX 0:85b3fd62ea1a 1107 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1108
NYX 0:85b3fd62ea1a 1109 return HAL_OK;
NYX 0:85b3fd62ea1a 1110 }
NYX 0:85b3fd62ea1a 1111 /**
NYX 0:85b3fd62ea1a 1112 * @brief Handle DMA2D interrupt request.
NYX 0:85b3fd62ea1a 1113 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1114 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 1115 * @retval HAL status
NYX 0:85b3fd62ea1a 1116 */
NYX 0:85b3fd62ea1a 1117 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 1118 {
NYX 0:85b3fd62ea1a 1119 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
NYX 0:85b3fd62ea1a 1120 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
NYX 0:85b3fd62ea1a 1121
NYX 0:85b3fd62ea1a 1122 /* Transfer Error Interrupt management ***************************************/
NYX 0:85b3fd62ea1a 1123 if ((isrflags & DMA2D_FLAG_TE) != RESET)
NYX 0:85b3fd62ea1a 1124 {
NYX 0:85b3fd62ea1a 1125 if ((crflags & DMA2D_IT_TE) != RESET)
NYX 0:85b3fd62ea1a 1126 {
NYX 0:85b3fd62ea1a 1127 /* Disable the transfer Error interrupt */
NYX 0:85b3fd62ea1a 1128 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
NYX 0:85b3fd62ea1a 1129
NYX 0:85b3fd62ea1a 1130 /* Update error code */
NYX 0:85b3fd62ea1a 1131 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
NYX 0:85b3fd62ea1a 1132
NYX 0:85b3fd62ea1a 1133 /* Clear the transfer error flag */
NYX 0:85b3fd62ea1a 1134 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
NYX 0:85b3fd62ea1a 1135
NYX 0:85b3fd62ea1a 1136 /* Change DMA2D state */
NYX 0:85b3fd62ea1a 1137 hdma2d->State = HAL_DMA2D_STATE_ERROR;
NYX 0:85b3fd62ea1a 1138
NYX 0:85b3fd62ea1a 1139 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1140 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1141
NYX 0:85b3fd62ea1a 1142 if(hdma2d->XferErrorCallback != NULL)
NYX 0:85b3fd62ea1a 1143 {
NYX 0:85b3fd62ea1a 1144 /* Transfer error Callback */
NYX 0:85b3fd62ea1a 1145 hdma2d->XferErrorCallback(hdma2d);
NYX 0:85b3fd62ea1a 1146 }
NYX 0:85b3fd62ea1a 1147 }
NYX 0:85b3fd62ea1a 1148 }
NYX 0:85b3fd62ea1a 1149 /* Configuration Error Interrupt management **********************************/
NYX 0:85b3fd62ea1a 1150 if ((isrflags & DMA2D_FLAG_CE) != RESET)
NYX 0:85b3fd62ea1a 1151 {
NYX 0:85b3fd62ea1a 1152 if ((crflags & DMA2D_IT_CE) != RESET)
NYX 0:85b3fd62ea1a 1153 {
NYX 0:85b3fd62ea1a 1154 /* Disable the Configuration Error interrupt */
NYX 0:85b3fd62ea1a 1155 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
NYX 0:85b3fd62ea1a 1156
NYX 0:85b3fd62ea1a 1157 /* Clear the Configuration error flag */
NYX 0:85b3fd62ea1a 1158 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
NYX 0:85b3fd62ea1a 1159
NYX 0:85b3fd62ea1a 1160 /* Update error code */
NYX 0:85b3fd62ea1a 1161 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
NYX 0:85b3fd62ea1a 1162
NYX 0:85b3fd62ea1a 1163 /* Change DMA2D state */
NYX 0:85b3fd62ea1a 1164 hdma2d->State = HAL_DMA2D_STATE_ERROR;
NYX 0:85b3fd62ea1a 1165
NYX 0:85b3fd62ea1a 1166 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1167 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1168
NYX 0:85b3fd62ea1a 1169 if(hdma2d->XferErrorCallback != NULL)
NYX 0:85b3fd62ea1a 1170 {
NYX 0:85b3fd62ea1a 1171 /* Transfer error Callback */
NYX 0:85b3fd62ea1a 1172 hdma2d->XferErrorCallback(hdma2d);
NYX 0:85b3fd62ea1a 1173 }
NYX 0:85b3fd62ea1a 1174 }
NYX 0:85b3fd62ea1a 1175 }
NYX 0:85b3fd62ea1a 1176 /* CLUT access Error Interrupt management ***********************************/
NYX 0:85b3fd62ea1a 1177 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
NYX 0:85b3fd62ea1a 1178 {
NYX 0:85b3fd62ea1a 1179 if ((crflags & DMA2D_IT_CAE) != RESET)
NYX 0:85b3fd62ea1a 1180 {
NYX 0:85b3fd62ea1a 1181 /* Disable the CLUT access error interrupt */
NYX 0:85b3fd62ea1a 1182 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
NYX 0:85b3fd62ea1a 1183
NYX 0:85b3fd62ea1a 1184 /* Clear the CLUT access error flag */
NYX 0:85b3fd62ea1a 1185 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
NYX 0:85b3fd62ea1a 1186
NYX 0:85b3fd62ea1a 1187 /* Update error code */
NYX 0:85b3fd62ea1a 1188 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
NYX 0:85b3fd62ea1a 1189
NYX 0:85b3fd62ea1a 1190 /* Change DMA2D state */
NYX 0:85b3fd62ea1a 1191 hdma2d->State = HAL_DMA2D_STATE_ERROR;
NYX 0:85b3fd62ea1a 1192
NYX 0:85b3fd62ea1a 1193 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1194 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1195
NYX 0:85b3fd62ea1a 1196 if(hdma2d->XferErrorCallback != NULL)
NYX 0:85b3fd62ea1a 1197 {
NYX 0:85b3fd62ea1a 1198 /* Transfer error Callback */
NYX 0:85b3fd62ea1a 1199 hdma2d->XferErrorCallback(hdma2d);
NYX 0:85b3fd62ea1a 1200 }
NYX 0:85b3fd62ea1a 1201 }
NYX 0:85b3fd62ea1a 1202 }
NYX 0:85b3fd62ea1a 1203 /* Transfer watermark Interrupt management **********************************/
NYX 0:85b3fd62ea1a 1204 if ((isrflags & DMA2D_FLAG_TW) != RESET)
NYX 0:85b3fd62ea1a 1205 {
NYX 0:85b3fd62ea1a 1206 if ((crflags & DMA2D_IT_TW) != RESET)
NYX 0:85b3fd62ea1a 1207 {
NYX 0:85b3fd62ea1a 1208 /* Disable the transfer watermark interrupt */
NYX 0:85b3fd62ea1a 1209 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
NYX 0:85b3fd62ea1a 1210
NYX 0:85b3fd62ea1a 1211 /* Clear the transfer watermark flag */
NYX 0:85b3fd62ea1a 1212 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
NYX 0:85b3fd62ea1a 1213
NYX 0:85b3fd62ea1a 1214 /* Transfer watermark Callback */
NYX 0:85b3fd62ea1a 1215 HAL_DMA2D_LineEventCallback(hdma2d);
NYX 0:85b3fd62ea1a 1216 }
NYX 0:85b3fd62ea1a 1217 }
NYX 0:85b3fd62ea1a 1218 /* Transfer Complete Interrupt management ************************************/
NYX 0:85b3fd62ea1a 1219 if ((isrflags & DMA2D_FLAG_TC) != RESET)
NYX 0:85b3fd62ea1a 1220 {
NYX 0:85b3fd62ea1a 1221 if ((crflags & DMA2D_IT_TC) != RESET)
NYX 0:85b3fd62ea1a 1222 {
NYX 0:85b3fd62ea1a 1223 /* Disable the transfer complete interrupt */
NYX 0:85b3fd62ea1a 1224 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
NYX 0:85b3fd62ea1a 1225
NYX 0:85b3fd62ea1a 1226 /* Clear the transfer complete flag */
NYX 0:85b3fd62ea1a 1227 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
NYX 0:85b3fd62ea1a 1228
NYX 0:85b3fd62ea1a 1229 /* Update error code */
NYX 0:85b3fd62ea1a 1230 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
NYX 0:85b3fd62ea1a 1231
NYX 0:85b3fd62ea1a 1232 /* Change DMA2D state */
NYX 0:85b3fd62ea1a 1233 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 1234
NYX 0:85b3fd62ea1a 1235 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1236 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1237
NYX 0:85b3fd62ea1a 1238 if(hdma2d->XferCpltCallback != NULL)
NYX 0:85b3fd62ea1a 1239 {
NYX 0:85b3fd62ea1a 1240 /* Transfer complete Callback */
NYX 0:85b3fd62ea1a 1241 hdma2d->XferCpltCallback(hdma2d);
NYX 0:85b3fd62ea1a 1242 }
NYX 0:85b3fd62ea1a 1243 }
NYX 0:85b3fd62ea1a 1244 }
NYX 0:85b3fd62ea1a 1245 /* CLUT Transfer Complete Interrupt management ******************************/
NYX 0:85b3fd62ea1a 1246 if ((isrflags & DMA2D_FLAG_CTC) != RESET)
NYX 0:85b3fd62ea1a 1247 {
NYX 0:85b3fd62ea1a 1248 if ((crflags & DMA2D_IT_CTC) != RESET)
NYX 0:85b3fd62ea1a 1249 {
NYX 0:85b3fd62ea1a 1250 /* Disable the CLUT transfer complete interrupt */
NYX 0:85b3fd62ea1a 1251 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
NYX 0:85b3fd62ea1a 1252
NYX 0:85b3fd62ea1a 1253 /* Clear the CLUT transfer complete flag */
NYX 0:85b3fd62ea1a 1254 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
NYX 0:85b3fd62ea1a 1255
NYX 0:85b3fd62ea1a 1256 /* Update error code */
NYX 0:85b3fd62ea1a 1257 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
NYX 0:85b3fd62ea1a 1258
NYX 0:85b3fd62ea1a 1259 /* Change DMA2D state */
NYX 0:85b3fd62ea1a 1260 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 1261
NYX 0:85b3fd62ea1a 1262 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1263 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1264
NYX 0:85b3fd62ea1a 1265 /* CLUT Transfer complete Callback */
NYX 0:85b3fd62ea1a 1266 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
NYX 0:85b3fd62ea1a 1267 }
NYX 0:85b3fd62ea1a 1268 }
NYX 0:85b3fd62ea1a 1269 }
NYX 0:85b3fd62ea1a 1270
NYX 0:85b3fd62ea1a 1271 /**
NYX 0:85b3fd62ea1a 1272 * @brief Transfer watermark callback.
NYX 0:85b3fd62ea1a 1273 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1274 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 1275 * @retval None
NYX 0:85b3fd62ea1a 1276 */
NYX 0:85b3fd62ea1a 1277 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 1278 {
NYX 0:85b3fd62ea1a 1279 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1280 UNUSED(hdma2d);
NYX 0:85b3fd62ea1a 1281
NYX 0:85b3fd62ea1a 1282 /* NOTE : This function should not be modified; when the callback is needed,
NYX 0:85b3fd62ea1a 1283 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
NYX 0:85b3fd62ea1a 1284 */
NYX 0:85b3fd62ea1a 1285 }
NYX 0:85b3fd62ea1a 1286
NYX 0:85b3fd62ea1a 1287 /**
NYX 0:85b3fd62ea1a 1288 * @brief CLUT Transfer Complete callback.
NYX 0:85b3fd62ea1a 1289 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1290 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 1291 * @retval None
NYX 0:85b3fd62ea1a 1292 */
NYX 0:85b3fd62ea1a 1293 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 1294 {
NYX 0:85b3fd62ea1a 1295 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1296 UNUSED(hdma2d);
NYX 0:85b3fd62ea1a 1297
NYX 0:85b3fd62ea1a 1298 /* NOTE : This function should not be modified; when the callback is needed,
NYX 0:85b3fd62ea1a 1299 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
NYX 0:85b3fd62ea1a 1300 */
NYX 0:85b3fd62ea1a 1301 }
NYX 0:85b3fd62ea1a 1302
NYX 0:85b3fd62ea1a 1303 /**
NYX 0:85b3fd62ea1a 1304 * @}
NYX 0:85b3fd62ea1a 1305 */
NYX 0:85b3fd62ea1a 1306
NYX 0:85b3fd62ea1a 1307 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
NYX 0:85b3fd62ea1a 1308 * @brief Peripheral Control functions
NYX 0:85b3fd62ea1a 1309 *
NYX 0:85b3fd62ea1a 1310 @verbatim
NYX 0:85b3fd62ea1a 1311 ===============================================================================
NYX 0:85b3fd62ea1a 1312 ##### Peripheral Control functions #####
NYX 0:85b3fd62ea1a 1313 ===============================================================================
NYX 0:85b3fd62ea1a 1314 [..] This section provides functions allowing to:
NYX 0:85b3fd62ea1a 1315 (+) Configure the DMA2D foreground or background layer parameters.
NYX 0:85b3fd62ea1a 1316 (+) Configure the DMA2D CLUT transfer.
NYX 0:85b3fd62ea1a 1317 (+) Configure the line watermark
NYX 0:85b3fd62ea1a 1318 (+) Configure the dead time value.
NYX 0:85b3fd62ea1a 1319 (+) Enable or disable the dead time value functionality.
NYX 0:85b3fd62ea1a 1320
NYX 0:85b3fd62ea1a 1321 @endverbatim
NYX 0:85b3fd62ea1a 1322 * @{
NYX 0:85b3fd62ea1a 1323 */
NYX 0:85b3fd62ea1a 1324
NYX 0:85b3fd62ea1a 1325 /**
NYX 0:85b3fd62ea1a 1326 * @brief Configure the DMA2D Layer according to the specified
NYX 0:85b3fd62ea1a 1327 * parameters in the DMA2D_InitTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 1328 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1329 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 1330 * @param LayerIdx: DMA2D Layer index.
NYX 0:85b3fd62ea1a 1331 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1332 * 0(background) / 1(foreground)
NYX 0:85b3fd62ea1a 1333 * @retval HAL status
NYX 0:85b3fd62ea1a 1334 */
NYX 0:85b3fd62ea1a 1335 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
NYX 0:85b3fd62ea1a 1336 {
NYX 0:85b3fd62ea1a 1337 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
NYX 0:85b3fd62ea1a 1338 uint32_t regValue = 0U;
NYX 0:85b3fd62ea1a 1339
NYX 0:85b3fd62ea1a 1340 /* Check the parameters */
NYX 0:85b3fd62ea1a 1341 assert_param(IS_DMA2D_LAYER(LayerIdx));
NYX 0:85b3fd62ea1a 1342 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
NYX 0:85b3fd62ea1a 1343 if(hdma2d->Init.Mode != DMA2D_R2M)
NYX 0:85b3fd62ea1a 1344 {
NYX 0:85b3fd62ea1a 1345 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
NYX 0:85b3fd62ea1a 1346 if(hdma2d->Init.Mode != DMA2D_M2M)
NYX 0:85b3fd62ea1a 1347 {
NYX 0:85b3fd62ea1a 1348 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
NYX 0:85b3fd62ea1a 1349 }
NYX 0:85b3fd62ea1a 1350 }
NYX 0:85b3fd62ea1a 1351
NYX 0:85b3fd62ea1a 1352 /* Process locked */
NYX 0:85b3fd62ea1a 1353 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 1354
NYX 0:85b3fd62ea1a 1355 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 1356 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 1357
NYX 0:85b3fd62ea1a 1358 /* DMA2D BGPFCR register configuration -----------------------------------*/
NYX 0:85b3fd62ea1a 1359 /* Prepare the value to be written to the BGPFCCR register */
NYX 0:85b3fd62ea1a 1360
NYX 0:85b3fd62ea1a 1361 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
NYX 0:85b3fd62ea1a 1362 {
NYX 0:85b3fd62ea1a 1363 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
NYX 0:85b3fd62ea1a 1364 }
NYX 0:85b3fd62ea1a 1365 else
NYX 0:85b3fd62ea1a 1366 {
NYX 0:85b3fd62ea1a 1367 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
NYX 0:85b3fd62ea1a 1368 }
NYX 0:85b3fd62ea1a 1369
NYX 0:85b3fd62ea1a 1370 /* Configure the background DMA2D layer */
NYX 0:85b3fd62ea1a 1371 if(LayerIdx == 0)
NYX 0:85b3fd62ea1a 1372 {
NYX 0:85b3fd62ea1a 1373 /* Write DMA2D BGPFCCR register */
NYX 0:85b3fd62ea1a 1374 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
NYX 0:85b3fd62ea1a 1375
NYX 0:85b3fd62ea1a 1376 /* DMA2D BGOR register configuration -------------------------------------*/
NYX 0:85b3fd62ea1a 1377 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
NYX 0:85b3fd62ea1a 1378
NYX 0:85b3fd62ea1a 1379 /* DMA2D BGCOLR register configuration -------------------------------------*/
NYX 0:85b3fd62ea1a 1380 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
NYX 0:85b3fd62ea1a 1381 {
NYX 0:85b3fd62ea1a 1382 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
NYX 0:85b3fd62ea1a 1383 }
NYX 0:85b3fd62ea1a 1384 }
NYX 0:85b3fd62ea1a 1385 /* Configure the foreground DMA2D layer */
NYX 0:85b3fd62ea1a 1386 else
NYX 0:85b3fd62ea1a 1387 {
NYX 0:85b3fd62ea1a 1388 /* Write DMA2D FGPFCCR register */
NYX 0:85b3fd62ea1a 1389 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
NYX 0:85b3fd62ea1a 1390
NYX 0:85b3fd62ea1a 1391 /* DMA2D FGOR register configuration -------------------------------------*/
NYX 0:85b3fd62ea1a 1392 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
NYX 0:85b3fd62ea1a 1393
NYX 0:85b3fd62ea1a 1394 /* DMA2D FGCOLR register configuration -------------------------------------*/
NYX 0:85b3fd62ea1a 1395 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
NYX 0:85b3fd62ea1a 1396 {
NYX 0:85b3fd62ea1a 1397 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
NYX 0:85b3fd62ea1a 1398 }
NYX 0:85b3fd62ea1a 1399 }
NYX 0:85b3fd62ea1a 1400 /* Initialize the DMA2D state*/
NYX 0:85b3fd62ea1a 1401 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 1402
NYX 0:85b3fd62ea1a 1403 /* Process unlocked */
NYX 0:85b3fd62ea1a 1404 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1405
NYX 0:85b3fd62ea1a 1406 return HAL_OK;
NYX 0:85b3fd62ea1a 1407 }
NYX 0:85b3fd62ea1a 1408
NYX 0:85b3fd62ea1a 1409 /**
NYX 0:85b3fd62ea1a 1410 * @brief Configure the DMA2D CLUT Transfer.
NYX 0:85b3fd62ea1a 1411 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1412 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 1413 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
NYX 0:85b3fd62ea1a 1414 * the configuration information for the color look up table.
NYX 0:85b3fd62ea1a 1415 * @param LayerIdx: DMA2D Layer index.
NYX 0:85b3fd62ea1a 1416 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1417 * 0(background) / 1(foreground)
NYX 0:85b3fd62ea1a 1418 * @retval HAL status
NYX 0:85b3fd62ea1a 1419 */
NYX 0:85b3fd62ea1a 1420 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
NYX 0:85b3fd62ea1a 1421 {
NYX 0:85b3fd62ea1a 1422 /* Check the parameters */
NYX 0:85b3fd62ea1a 1423 assert_param(IS_DMA2D_LAYER(LayerIdx));
NYX 0:85b3fd62ea1a 1424 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
NYX 0:85b3fd62ea1a 1425 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
NYX 0:85b3fd62ea1a 1426
NYX 0:85b3fd62ea1a 1427 /* Process locked */
NYX 0:85b3fd62ea1a 1428 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 1429
NYX 0:85b3fd62ea1a 1430 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 1431 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 1432
NYX 0:85b3fd62ea1a 1433 /* Configure the CLUT of the background DMA2D layer */
NYX 0:85b3fd62ea1a 1434 if(LayerIdx == 0U)
NYX 0:85b3fd62ea1a 1435 {
NYX 0:85b3fd62ea1a 1436 /* Write background CLUT memory address */
NYX 0:85b3fd62ea1a 1437 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
NYX 0:85b3fd62ea1a 1438
NYX 0:85b3fd62ea1a 1439 /* Write background CLUT size and CLUT color mode */
NYX 0:85b3fd62ea1a 1440 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
NYX 0:85b3fd62ea1a 1441 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
NYX 0:85b3fd62ea1a 1442 }
NYX 0:85b3fd62ea1a 1443 /* Configure the CLUT of the foreground DMA2D layer */
NYX 0:85b3fd62ea1a 1444 else
NYX 0:85b3fd62ea1a 1445 {
NYX 0:85b3fd62ea1a 1446 /* Write foreground CLUT memory address */
NYX 0:85b3fd62ea1a 1447 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
NYX 0:85b3fd62ea1a 1448
NYX 0:85b3fd62ea1a 1449 /* Write foreground CLUT size and CLUT color mode */
NYX 0:85b3fd62ea1a 1450 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
NYX 0:85b3fd62ea1a 1451 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
NYX 0:85b3fd62ea1a 1452 }
NYX 0:85b3fd62ea1a 1453
NYX 0:85b3fd62ea1a 1454 /* Set the DMA2D state to Ready */
NYX 0:85b3fd62ea1a 1455 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 1456
NYX 0:85b3fd62ea1a 1457 /* Process unlocked */
NYX 0:85b3fd62ea1a 1458 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1459
NYX 0:85b3fd62ea1a 1460 return HAL_OK;
NYX 0:85b3fd62ea1a 1461 }
NYX 0:85b3fd62ea1a 1462
NYX 0:85b3fd62ea1a 1463 /**
NYX 0:85b3fd62ea1a 1464 * @brief Configure the line watermark.
NYX 0:85b3fd62ea1a 1465 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1466 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 1467 * @param Line: Line Watermark configuration (maximum 16-bit long value expected).
NYX 0:85b3fd62ea1a 1468 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
NYX 0:85b3fd62ea1a 1469 * @note The transfer watermark interrupt is disabled once it has occurred.
NYX 0:85b3fd62ea1a 1470 * @retval HAL status
NYX 0:85b3fd62ea1a 1471 */
NYX 0:85b3fd62ea1a 1472
NYX 0:85b3fd62ea1a 1473 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
NYX 0:85b3fd62ea1a 1474 {
NYX 0:85b3fd62ea1a 1475 /* Check the parameters */
NYX 0:85b3fd62ea1a 1476 assert_param(IS_DMA2D_LINEWATERMARK(Line));
NYX 0:85b3fd62ea1a 1477
NYX 0:85b3fd62ea1a 1478 if (Line > DMA2D_LWR_LW)
NYX 0:85b3fd62ea1a 1479 {
NYX 0:85b3fd62ea1a 1480 return HAL_ERROR;
NYX 0:85b3fd62ea1a 1481 }
NYX 0:85b3fd62ea1a 1482 else
NYX 0:85b3fd62ea1a 1483 {
NYX 0:85b3fd62ea1a 1484 /* Process locked */
NYX 0:85b3fd62ea1a 1485 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 1486
NYX 0:85b3fd62ea1a 1487 /* Change DMA2D peripheral state */
NYX 0:85b3fd62ea1a 1488 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 1489
NYX 0:85b3fd62ea1a 1490 /* Sets the Line watermark configuration */
NYX 0:85b3fd62ea1a 1491 WRITE_REG(hdma2d->Instance->LWR, Line);
NYX 0:85b3fd62ea1a 1492
NYX 0:85b3fd62ea1a 1493 /* Enable the Line interrupt */
NYX 0:85b3fd62ea1a 1494 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
NYX 0:85b3fd62ea1a 1495
NYX 0:85b3fd62ea1a 1496 /* Initialize the DMA2D state */
NYX 0:85b3fd62ea1a 1497 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 1498
NYX 0:85b3fd62ea1a 1499 /* Process unlocked */
NYX 0:85b3fd62ea1a 1500 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1501
NYX 0:85b3fd62ea1a 1502 return HAL_OK;
NYX 0:85b3fd62ea1a 1503 }
NYX 0:85b3fd62ea1a 1504 }
NYX 0:85b3fd62ea1a 1505
NYX 0:85b3fd62ea1a 1506 /**
NYX 0:85b3fd62ea1a 1507 * @brief Enable DMA2D dead time feature.
NYX 0:85b3fd62ea1a 1508 * @param hdma2d: DMA2D handle.
NYX 0:85b3fd62ea1a 1509 * @retval HAL status
NYX 0:85b3fd62ea1a 1510 */
NYX 0:85b3fd62ea1a 1511 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 1512 {
NYX 0:85b3fd62ea1a 1513 /* Process Locked */
NYX 0:85b3fd62ea1a 1514 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 1515
NYX 0:85b3fd62ea1a 1516 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 1517
NYX 0:85b3fd62ea1a 1518 /* Set DMA2D_AMTCR EN bit */
NYX 0:85b3fd62ea1a 1519 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
NYX 0:85b3fd62ea1a 1520
NYX 0:85b3fd62ea1a 1521 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 1522
NYX 0:85b3fd62ea1a 1523 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1524 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1525
NYX 0:85b3fd62ea1a 1526 return HAL_OK;
NYX 0:85b3fd62ea1a 1527 }
NYX 0:85b3fd62ea1a 1528
NYX 0:85b3fd62ea1a 1529 /**
NYX 0:85b3fd62ea1a 1530 * @brief Disable DMA2D dead time feature.
NYX 0:85b3fd62ea1a 1531 * @param hdma2d: DMA2D handle.
NYX 0:85b3fd62ea1a 1532 * @retval HAL status
NYX 0:85b3fd62ea1a 1533 */
NYX 0:85b3fd62ea1a 1534 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 1535 {
NYX 0:85b3fd62ea1a 1536 /* Process Locked */
NYX 0:85b3fd62ea1a 1537 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 1538
NYX 0:85b3fd62ea1a 1539 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 1540
NYX 0:85b3fd62ea1a 1541 /* Clear DMA2D_AMTCR EN bit */
NYX 0:85b3fd62ea1a 1542 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
NYX 0:85b3fd62ea1a 1543
NYX 0:85b3fd62ea1a 1544 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 1545
NYX 0:85b3fd62ea1a 1546 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1547 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1548
NYX 0:85b3fd62ea1a 1549 return HAL_OK;
NYX 0:85b3fd62ea1a 1550 }
NYX 0:85b3fd62ea1a 1551
NYX 0:85b3fd62ea1a 1552 /**
NYX 0:85b3fd62ea1a 1553 * @brief Configure dead time.
NYX 0:85b3fd62ea1a 1554 * @note The dead time value represents the guaranteed minimum number of cycles between
NYX 0:85b3fd62ea1a 1555 * two consecutive transactions on the AHB bus.
NYX 0:85b3fd62ea1a 1556 * @param hdma2d: DMA2D handle.
NYX 0:85b3fd62ea1a 1557 * @param DeadTime: dead time value.
NYX 0:85b3fd62ea1a 1558 * @retval HAL status
NYX 0:85b3fd62ea1a 1559 */
NYX 0:85b3fd62ea1a 1560 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
NYX 0:85b3fd62ea1a 1561 {
NYX 0:85b3fd62ea1a 1562 /* Process Locked */
NYX 0:85b3fd62ea1a 1563 __HAL_LOCK(hdma2d);
NYX 0:85b3fd62ea1a 1564
NYX 0:85b3fd62ea1a 1565 hdma2d->State = HAL_DMA2D_STATE_BUSY;
NYX 0:85b3fd62ea1a 1566
NYX 0:85b3fd62ea1a 1567 /* Set DMA2D_AMTCR DT field */
NYX 0:85b3fd62ea1a 1568 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
NYX 0:85b3fd62ea1a 1569
NYX 0:85b3fd62ea1a 1570 hdma2d->State = HAL_DMA2D_STATE_READY;
NYX 0:85b3fd62ea1a 1571
NYX 0:85b3fd62ea1a 1572 /* Process Unlocked */
NYX 0:85b3fd62ea1a 1573 __HAL_UNLOCK(hdma2d);
NYX 0:85b3fd62ea1a 1574
NYX 0:85b3fd62ea1a 1575 return HAL_OK;
NYX 0:85b3fd62ea1a 1576 }
NYX 0:85b3fd62ea1a 1577
NYX 0:85b3fd62ea1a 1578 /**
NYX 0:85b3fd62ea1a 1579 * @}
NYX 0:85b3fd62ea1a 1580 */
NYX 0:85b3fd62ea1a 1581
NYX 0:85b3fd62ea1a 1582 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
NYX 0:85b3fd62ea1a 1583 * @brief Peripheral State functions
NYX 0:85b3fd62ea1a 1584 *
NYX 0:85b3fd62ea1a 1585 @verbatim
NYX 0:85b3fd62ea1a 1586 ===============================================================================
NYX 0:85b3fd62ea1a 1587 ##### Peripheral State and Errors functions #####
NYX 0:85b3fd62ea1a 1588 ===============================================================================
NYX 0:85b3fd62ea1a 1589 [..]
NYX 0:85b3fd62ea1a 1590 This subsection provides functions allowing to :
NYX 0:85b3fd62ea1a 1591 (+) Get the DMA2D state
NYX 0:85b3fd62ea1a 1592 (+) Get the DMA2D error code
NYX 0:85b3fd62ea1a 1593
NYX 0:85b3fd62ea1a 1594 @endverbatim
NYX 0:85b3fd62ea1a 1595 * @{
NYX 0:85b3fd62ea1a 1596 */
NYX 0:85b3fd62ea1a 1597
NYX 0:85b3fd62ea1a 1598 /**
NYX 0:85b3fd62ea1a 1599 * @brief Return the DMA2D state
NYX 0:85b3fd62ea1a 1600 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1601 * the configuration information for the DMA2D.
NYX 0:85b3fd62ea1a 1602 * @retval HAL state
NYX 0:85b3fd62ea1a 1603 */
NYX 0:85b3fd62ea1a 1604 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 1605 {
NYX 0:85b3fd62ea1a 1606 return hdma2d->State;
NYX 0:85b3fd62ea1a 1607 }
NYX 0:85b3fd62ea1a 1608
NYX 0:85b3fd62ea1a 1609 /**
NYX 0:85b3fd62ea1a 1610 * @brief Return the DMA2D error code
NYX 0:85b3fd62ea1a 1611 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1612 * the configuration information for DMA2D.
NYX 0:85b3fd62ea1a 1613 * @retval DMA2D Error Code
NYX 0:85b3fd62ea1a 1614 */
NYX 0:85b3fd62ea1a 1615 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
NYX 0:85b3fd62ea1a 1616 {
NYX 0:85b3fd62ea1a 1617 return hdma2d->ErrorCode;
NYX 0:85b3fd62ea1a 1618 }
NYX 0:85b3fd62ea1a 1619
NYX 0:85b3fd62ea1a 1620 /**
NYX 0:85b3fd62ea1a 1621 * @}
NYX 0:85b3fd62ea1a 1622 */
NYX 0:85b3fd62ea1a 1623
NYX 0:85b3fd62ea1a 1624 /**
NYX 0:85b3fd62ea1a 1625 * @}
NYX 0:85b3fd62ea1a 1626 */
NYX 0:85b3fd62ea1a 1627
NYX 0:85b3fd62ea1a 1628 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
NYX 0:85b3fd62ea1a 1629 * @{
NYX 0:85b3fd62ea1a 1630 */
NYX 0:85b3fd62ea1a 1631
NYX 0:85b3fd62ea1a 1632 /**
NYX 0:85b3fd62ea1a 1633 * @brief Set the DMA2D transfer parameters.
NYX 0:85b3fd62ea1a 1634 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1635 * the configuration information for the specified DMA2D.
NYX 0:85b3fd62ea1a 1636 * @param pdata: The source memory Buffer address
NYX 0:85b3fd62ea1a 1637 * @param DstAddress: The destination memory Buffer address
NYX 0:85b3fd62ea1a 1638 * @param Width: The width of data to be transferred from source to destination.
NYX 0:85b3fd62ea1a 1639 * @param Height: The height of data to be transferred from source to destination.
NYX 0:85b3fd62ea1a 1640 * @retval HAL status
NYX 0:85b3fd62ea1a 1641 */
NYX 0:85b3fd62ea1a 1642 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
NYX 0:85b3fd62ea1a 1643 {
NYX 0:85b3fd62ea1a 1644 uint32_t tmp = 0U;
NYX 0:85b3fd62ea1a 1645 uint32_t tmp1 = 0U;
NYX 0:85b3fd62ea1a 1646 uint32_t tmp2 = 0U;
NYX 0:85b3fd62ea1a 1647 uint32_t tmp3 = 0U;
NYX 0:85b3fd62ea1a 1648 uint32_t tmp4 = 0U;
NYX 0:85b3fd62ea1a 1649
NYX 0:85b3fd62ea1a 1650 /* Configure DMA2D data size */
NYX 0:85b3fd62ea1a 1651 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
NYX 0:85b3fd62ea1a 1652
NYX 0:85b3fd62ea1a 1653 /* Configure DMA2D destination address */
NYX 0:85b3fd62ea1a 1654 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
NYX 0:85b3fd62ea1a 1655
NYX 0:85b3fd62ea1a 1656 /* Register to memory DMA2D mode selected */
NYX 0:85b3fd62ea1a 1657 if (hdma2d->Init.Mode == DMA2D_R2M)
NYX 0:85b3fd62ea1a 1658 {
NYX 0:85b3fd62ea1a 1659 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
NYX 0:85b3fd62ea1a 1660 tmp2 = pdata & DMA2D_OCOLR_RED_1;
NYX 0:85b3fd62ea1a 1661 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
NYX 0:85b3fd62ea1a 1662 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
NYX 0:85b3fd62ea1a 1663
NYX 0:85b3fd62ea1a 1664 /* Prepare the value to be written to the OCOLR register according to the color mode */
NYX 0:85b3fd62ea1a 1665 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
NYX 0:85b3fd62ea1a 1666 {
NYX 0:85b3fd62ea1a 1667 tmp = (tmp3 | tmp2 | tmp1| tmp4);
NYX 0:85b3fd62ea1a 1668 }
NYX 0:85b3fd62ea1a 1669 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
NYX 0:85b3fd62ea1a 1670 {
NYX 0:85b3fd62ea1a 1671 tmp = (tmp3 | tmp2 | tmp4);
NYX 0:85b3fd62ea1a 1672 }
NYX 0:85b3fd62ea1a 1673 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
NYX 0:85b3fd62ea1a 1674 {
NYX 0:85b3fd62ea1a 1675 tmp2 = (tmp2 >> 19U);
NYX 0:85b3fd62ea1a 1676 tmp3 = (tmp3 >> 10U);
NYX 0:85b3fd62ea1a 1677 tmp4 = (tmp4 >> 3U);
NYX 0:85b3fd62ea1a 1678 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
NYX 0:85b3fd62ea1a 1679 }
NYX 0:85b3fd62ea1a 1680 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
NYX 0:85b3fd62ea1a 1681 {
NYX 0:85b3fd62ea1a 1682 tmp1 = (tmp1 >> 31U);
NYX 0:85b3fd62ea1a 1683 tmp2 = (tmp2 >> 19U);
NYX 0:85b3fd62ea1a 1684 tmp3 = (tmp3 >> 11U);
NYX 0:85b3fd62ea1a 1685 tmp4 = (tmp4 >> 3U);
NYX 0:85b3fd62ea1a 1686 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
NYX 0:85b3fd62ea1a 1687 }
NYX 0:85b3fd62ea1a 1688 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
NYX 0:85b3fd62ea1a 1689 {
NYX 0:85b3fd62ea1a 1690 tmp1 = (tmp1 >> 28U);
NYX 0:85b3fd62ea1a 1691 tmp2 = (tmp2 >> 20U);
NYX 0:85b3fd62ea1a 1692 tmp3 = (tmp3 >> 12U);
NYX 0:85b3fd62ea1a 1693 tmp4 = (tmp4 >> 4U);
NYX 0:85b3fd62ea1a 1694 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
NYX 0:85b3fd62ea1a 1695 }
NYX 0:85b3fd62ea1a 1696 /* Write to DMA2D OCOLR register */
NYX 0:85b3fd62ea1a 1697 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
NYX 0:85b3fd62ea1a 1698 }
NYX 0:85b3fd62ea1a 1699 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
NYX 0:85b3fd62ea1a 1700 {
NYX 0:85b3fd62ea1a 1701 /* Configure DMA2D source address */
NYX 0:85b3fd62ea1a 1702 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
NYX 0:85b3fd62ea1a 1703 }
NYX 0:85b3fd62ea1a 1704 }
NYX 0:85b3fd62ea1a 1705
NYX 0:85b3fd62ea1a 1706 /**
NYX 0:85b3fd62ea1a 1707 * @}
NYX 0:85b3fd62ea1a 1708 */
NYX 0:85b3fd62ea1a 1709 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
NYX 0:85b3fd62ea1a 1710 #endif /* HAL_DMA2D_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 1711 /**
NYX 0:85b3fd62ea1a 1712 * @}
NYX 0:85b3fd62ea1a 1713 */
NYX 0:85b3fd62ea1a 1714
NYX 0:85b3fd62ea1a 1715 /**
NYX 0:85b3fd62ea1a 1716 * @}
NYX 0:85b3fd62ea1a 1717 */
NYX 0:85b3fd62ea1a 1718
NYX 0:85b3fd62ea1a 1719 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/