Takaaki Numai
inport from local
Dependents: Hobbyking_Cheetah_0511
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h@0:85b3fd62ea1a, 2020-03-16 (annotated)
- Committer:
- NYX
- Date:
- Mon Mar 16 06:35:48 2020 +0000
- Revision:
- 0:85b3fd62ea1a
reinport to mbed;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| NYX | 0:85b3fd62ea1a | 1 | /** |
| NYX | 0:85b3fd62ea1a | 2 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 3 | * @file stm32f4xx_hal_dma.h |
| NYX | 0:85b3fd62ea1a | 4 | * @author MCD Application Team |
| NYX | 0:85b3fd62ea1a | 5 | * @version V1.7.1 |
| NYX | 0:85b3fd62ea1a | 6 | * @date 14-April-2017 |
| NYX | 0:85b3fd62ea1a | 7 | * @brief Header file of DMA HAL module. |
| NYX | 0:85b3fd62ea1a | 8 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 9 | * @attention |
| NYX | 0:85b3fd62ea1a | 10 | * |
| NYX | 0:85b3fd62ea1a | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| NYX | 0:85b3fd62ea1a | 12 | * |
| NYX | 0:85b3fd62ea1a | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| NYX | 0:85b3fd62ea1a | 14 | * are permitted provided that the following conditions are met: |
| NYX | 0:85b3fd62ea1a | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| NYX | 0:85b3fd62ea1a | 16 | * this list of conditions and the following disclaimer. |
| NYX | 0:85b3fd62ea1a | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| NYX | 0:85b3fd62ea1a | 18 | * this list of conditions and the following disclaimer in the documentation |
| NYX | 0:85b3fd62ea1a | 19 | * and/or other materials provided with the distribution. |
| NYX | 0:85b3fd62ea1a | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| NYX | 0:85b3fd62ea1a | 21 | * may be used to endorse or promote products derived from this software |
| NYX | 0:85b3fd62ea1a | 22 | * without specific prior written permission. |
| NYX | 0:85b3fd62ea1a | 23 | * |
| NYX | 0:85b3fd62ea1a | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| NYX | 0:85b3fd62ea1a | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| NYX | 0:85b3fd62ea1a | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| NYX | 0:85b3fd62ea1a | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| NYX | 0:85b3fd62ea1a | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| NYX | 0:85b3fd62ea1a | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| NYX | 0:85b3fd62ea1a | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| NYX | 0:85b3fd62ea1a | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| NYX | 0:85b3fd62ea1a | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| NYX | 0:85b3fd62ea1a | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| NYX | 0:85b3fd62ea1a | 34 | * |
| NYX | 0:85b3fd62ea1a | 35 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 36 | */ |
| NYX | 0:85b3fd62ea1a | 37 | |
| NYX | 0:85b3fd62ea1a | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 39 | #ifndef __STM32F4xx_HAL_DMA_H |
| NYX | 0:85b3fd62ea1a | 40 | #define __STM32F4xx_HAL_DMA_H |
| NYX | 0:85b3fd62ea1a | 41 | |
| NYX | 0:85b3fd62ea1a | 42 | #ifdef __cplusplus |
| NYX | 0:85b3fd62ea1a | 43 | extern "C" { |
| NYX | 0:85b3fd62ea1a | 44 | #endif |
| NYX | 0:85b3fd62ea1a | 45 | |
| NYX | 0:85b3fd62ea1a | 46 | /* Includes ------------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 47 | #include "stm32f4xx_hal_def.h" |
| NYX | 0:85b3fd62ea1a | 48 | |
| NYX | 0:85b3fd62ea1a | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| NYX | 0:85b3fd62ea1a | 50 | * @{ |
| NYX | 0:85b3fd62ea1a | 51 | */ |
| NYX | 0:85b3fd62ea1a | 52 | |
| NYX | 0:85b3fd62ea1a | 53 | /** @addtogroup DMA |
| NYX | 0:85b3fd62ea1a | 54 | * @{ |
| NYX | 0:85b3fd62ea1a | 55 | */ |
| NYX | 0:85b3fd62ea1a | 56 | |
| NYX | 0:85b3fd62ea1a | 57 | /* Exported types ------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 58 | |
| NYX | 0:85b3fd62ea1a | 59 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| NYX | 0:85b3fd62ea1a | 60 | * @brief DMA Exported Types |
| NYX | 0:85b3fd62ea1a | 61 | * @{ |
| NYX | 0:85b3fd62ea1a | 62 | */ |
| NYX | 0:85b3fd62ea1a | 63 | |
| NYX | 0:85b3fd62ea1a | 64 | /** |
| NYX | 0:85b3fd62ea1a | 65 | * @brief DMA Configuration Structure definition |
| NYX | 0:85b3fd62ea1a | 66 | */ |
| NYX | 0:85b3fd62ea1a | 67 | typedef struct |
| NYX | 0:85b3fd62ea1a | 68 | { |
| NYX | 0:85b3fd62ea1a | 69 | uint32_t Channel; /*!< Specifies the channel used for the specified stream. |
| NYX | 0:85b3fd62ea1a | 70 | This parameter can be a value of @ref DMA_Channel_selection */ |
| NYX | 0:85b3fd62ea1a | 71 | |
| NYX | 0:85b3fd62ea1a | 72 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| NYX | 0:85b3fd62ea1a | 73 | from memory to memory or from peripheral to memory. |
| NYX | 0:85b3fd62ea1a | 74 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| NYX | 0:85b3fd62ea1a | 75 | |
| NYX | 0:85b3fd62ea1a | 76 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| NYX | 0:85b3fd62ea1a | 77 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| NYX | 0:85b3fd62ea1a | 78 | |
| NYX | 0:85b3fd62ea1a | 79 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| NYX | 0:85b3fd62ea1a | 80 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| NYX | 0:85b3fd62ea1a | 81 | |
| NYX | 0:85b3fd62ea1a | 82 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| NYX | 0:85b3fd62ea1a | 83 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| NYX | 0:85b3fd62ea1a | 84 | |
| NYX | 0:85b3fd62ea1a | 85 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| NYX | 0:85b3fd62ea1a | 86 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| NYX | 0:85b3fd62ea1a | 87 | |
| NYX | 0:85b3fd62ea1a | 88 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. |
| NYX | 0:85b3fd62ea1a | 89 | This parameter can be a value of @ref DMA_mode |
| NYX | 0:85b3fd62ea1a | 90 | @note The circular buffer mode cannot be used if the memory-to-memory |
| NYX | 0:85b3fd62ea1a | 91 | data transfer is configured on the selected Stream */ |
| NYX | 0:85b3fd62ea1a | 92 | |
| NYX | 0:85b3fd62ea1a | 93 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. |
| NYX | 0:85b3fd62ea1a | 94 | This parameter can be a value of @ref DMA_Priority_level */ |
| NYX | 0:85b3fd62ea1a | 95 | |
| NYX | 0:85b3fd62ea1a | 96 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
| NYX | 0:85b3fd62ea1a | 97 | This parameter can be a value of @ref DMA_FIFO_direct_mode |
| NYX | 0:85b3fd62ea1a | 98 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
| NYX | 0:85b3fd62ea1a | 99 | memory-to-memory data transfer is configured on the selected stream */ |
| NYX | 0:85b3fd62ea1a | 100 | |
| NYX | 0:85b3fd62ea1a | 101 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
| NYX | 0:85b3fd62ea1a | 102 | This parameter can be a value of @ref DMA_FIFO_threshold_level */ |
| NYX | 0:85b3fd62ea1a | 103 | |
| NYX | 0:85b3fd62ea1a | 104 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
| NYX | 0:85b3fd62ea1a | 105 | It specifies the amount of data to be transferred in a single non interruptible |
| NYX | 0:85b3fd62ea1a | 106 | transaction. |
| NYX | 0:85b3fd62ea1a | 107 | This parameter can be a value of @ref DMA_Memory_burst |
| NYX | 0:85b3fd62ea1a | 108 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| NYX | 0:85b3fd62ea1a | 109 | |
| NYX | 0:85b3fd62ea1a | 110 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
| NYX | 0:85b3fd62ea1a | 111 | It specifies the amount of data to be transferred in a single non interruptible |
| NYX | 0:85b3fd62ea1a | 112 | transaction. |
| NYX | 0:85b3fd62ea1a | 113 | This parameter can be a value of @ref DMA_Peripheral_burst |
| NYX | 0:85b3fd62ea1a | 114 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| NYX | 0:85b3fd62ea1a | 115 | }DMA_InitTypeDef; |
| NYX | 0:85b3fd62ea1a | 116 | |
| NYX | 0:85b3fd62ea1a | 117 | |
| NYX | 0:85b3fd62ea1a | 118 | /** |
| NYX | 0:85b3fd62ea1a | 119 | * @brief HAL DMA State structures definition |
| NYX | 0:85b3fd62ea1a | 120 | */ |
| NYX | 0:85b3fd62ea1a | 121 | typedef enum |
| NYX | 0:85b3fd62ea1a | 122 | { |
| NYX | 0:85b3fd62ea1a | 123 | HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
| NYX | 0:85b3fd62ea1a | 124 | HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ |
| NYX | 0:85b3fd62ea1a | 125 | HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
| NYX | 0:85b3fd62ea1a | 126 | HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ |
| NYX | 0:85b3fd62ea1a | 127 | HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ |
| NYX | 0:85b3fd62ea1a | 128 | HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ |
| NYX | 0:85b3fd62ea1a | 129 | }HAL_DMA_StateTypeDef; |
| NYX | 0:85b3fd62ea1a | 130 | |
| NYX | 0:85b3fd62ea1a | 131 | /** |
| NYX | 0:85b3fd62ea1a | 132 | * @brief HAL DMA Error Code structure definition |
| NYX | 0:85b3fd62ea1a | 133 | */ |
| NYX | 0:85b3fd62ea1a | 134 | typedef enum |
| NYX | 0:85b3fd62ea1a | 135 | { |
| NYX | 0:85b3fd62ea1a | 136 | HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
| NYX | 0:85b3fd62ea1a | 137 | HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ |
| NYX | 0:85b3fd62ea1a | 138 | }HAL_DMA_LevelCompleteTypeDef; |
| NYX | 0:85b3fd62ea1a | 139 | |
| NYX | 0:85b3fd62ea1a | 140 | /** |
| NYX | 0:85b3fd62ea1a | 141 | * @brief HAL DMA Error Code structure definition |
| NYX | 0:85b3fd62ea1a | 142 | */ |
| NYX | 0:85b3fd62ea1a | 143 | typedef enum |
| NYX | 0:85b3fd62ea1a | 144 | { |
| NYX | 0:85b3fd62ea1a | 145 | HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ |
| NYX | 0:85b3fd62ea1a | 146 | HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ |
| NYX | 0:85b3fd62ea1a | 147 | HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ |
| NYX | 0:85b3fd62ea1a | 148 | HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ |
| NYX | 0:85b3fd62ea1a | 149 | HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ |
| NYX | 0:85b3fd62ea1a | 150 | HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ |
| NYX | 0:85b3fd62ea1a | 151 | HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ |
| NYX | 0:85b3fd62ea1a | 152 | }HAL_DMA_CallbackIDTypeDef; |
| NYX | 0:85b3fd62ea1a | 153 | |
| NYX | 0:85b3fd62ea1a | 154 | /** |
| NYX | 0:85b3fd62ea1a | 155 | * @brief DMA handle Structure definition |
| NYX | 0:85b3fd62ea1a | 156 | */ |
| NYX | 0:85b3fd62ea1a | 157 | typedef struct __DMA_HandleTypeDef |
| NYX | 0:85b3fd62ea1a | 158 | { |
| NYX | 0:85b3fd62ea1a | 159 | DMA_Stream_TypeDef *Instance; /*!< Register base address */ |
| NYX | 0:85b3fd62ea1a | 160 | |
| NYX | 0:85b3fd62ea1a | 161 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| NYX | 0:85b3fd62ea1a | 162 | |
| NYX | 0:85b3fd62ea1a | 163 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| NYX | 0:85b3fd62ea1a | 164 | |
| NYX | 0:85b3fd62ea1a | 165 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| NYX | 0:85b3fd62ea1a | 166 | |
| NYX | 0:85b3fd62ea1a | 167 | void *Parent; /*!< Parent object state */ |
| NYX | 0:85b3fd62ea1a | 168 | |
| NYX | 0:85b3fd62ea1a | 169 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| NYX | 0:85b3fd62ea1a | 170 | |
| NYX | 0:85b3fd62ea1a | 171 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| NYX | 0:85b3fd62ea1a | 172 | |
| NYX | 0:85b3fd62ea1a | 173 | void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ |
| NYX | 0:85b3fd62ea1a | 174 | |
| NYX | 0:85b3fd62ea1a | 175 | void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ |
| NYX | 0:85b3fd62ea1a | 176 | |
| NYX | 0:85b3fd62ea1a | 177 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| NYX | 0:85b3fd62ea1a | 178 | |
| NYX | 0:85b3fd62ea1a | 179 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ |
| NYX | 0:85b3fd62ea1a | 180 | |
| NYX | 0:85b3fd62ea1a | 181 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| NYX | 0:85b3fd62ea1a | 182 | |
| NYX | 0:85b3fd62ea1a | 183 | uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ |
| NYX | 0:85b3fd62ea1a | 184 | |
| NYX | 0:85b3fd62ea1a | 185 | uint32_t StreamIndex; /*!< DMA Stream Index */ |
| NYX | 0:85b3fd62ea1a | 186 | |
| NYX | 0:85b3fd62ea1a | 187 | }DMA_HandleTypeDef; |
| NYX | 0:85b3fd62ea1a | 188 | |
| NYX | 0:85b3fd62ea1a | 189 | /** |
| NYX | 0:85b3fd62ea1a | 190 | * @} |
| NYX | 0:85b3fd62ea1a | 191 | */ |
| NYX | 0:85b3fd62ea1a | 192 | |
| NYX | 0:85b3fd62ea1a | 193 | /* Exported constants --------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 194 | |
| NYX | 0:85b3fd62ea1a | 195 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| NYX | 0:85b3fd62ea1a | 196 | * @brief DMA Exported constants |
| NYX | 0:85b3fd62ea1a | 197 | * @{ |
| NYX | 0:85b3fd62ea1a | 198 | */ |
| NYX | 0:85b3fd62ea1a | 199 | |
| NYX | 0:85b3fd62ea1a | 200 | /** @defgroup DMA_Error_Code DMA Error Code |
| NYX | 0:85b3fd62ea1a | 201 | * @brief DMA Error Code |
| NYX | 0:85b3fd62ea1a | 202 | * @{ |
| NYX | 0:85b3fd62ea1a | 203 | */ |
| NYX | 0:85b3fd62ea1a | 204 | #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ |
| NYX | 0:85b3fd62ea1a | 205 | #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ |
| NYX | 0:85b3fd62ea1a | 206 | #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ |
| NYX | 0:85b3fd62ea1a | 207 | #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ |
| NYX | 0:85b3fd62ea1a | 208 | #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ |
| NYX | 0:85b3fd62ea1a | 209 | #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ |
| NYX | 0:85b3fd62ea1a | 210 | #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ |
| NYX | 0:85b3fd62ea1a | 211 | #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ |
| NYX | 0:85b3fd62ea1a | 212 | /** |
| NYX | 0:85b3fd62ea1a | 213 | * @} |
| NYX | 0:85b3fd62ea1a | 214 | */ |
| NYX | 0:85b3fd62ea1a | 215 | |
| NYX | 0:85b3fd62ea1a | 216 | /** @defgroup DMA_Channel_selection DMA Channel selection |
| NYX | 0:85b3fd62ea1a | 217 | * @brief DMA channel selection |
| NYX | 0:85b3fd62ea1a | 218 | * @{ |
| NYX | 0:85b3fd62ea1a | 219 | */ |
| NYX | 0:85b3fd62ea1a | 220 | #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ |
| NYX | 0:85b3fd62ea1a | 221 | #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ |
| NYX | 0:85b3fd62ea1a | 222 | #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ |
| NYX | 0:85b3fd62ea1a | 223 | #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ |
| NYX | 0:85b3fd62ea1a | 224 | #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ |
| NYX | 0:85b3fd62ea1a | 225 | #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ |
| NYX | 0:85b3fd62ea1a | 226 | #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ |
| NYX | 0:85b3fd62ea1a | 227 | #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ |
| NYX | 0:85b3fd62ea1a | 228 | #if defined (DMA_SxCR_CHSEL_3) |
| NYX | 0:85b3fd62ea1a | 229 | #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ |
| NYX | 0:85b3fd62ea1a | 230 | #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ |
| NYX | 0:85b3fd62ea1a | 231 | #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ |
| NYX | 0:85b3fd62ea1a | 232 | #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ |
| NYX | 0:85b3fd62ea1a | 233 | #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ |
| NYX | 0:85b3fd62ea1a | 234 | #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ |
| NYX | 0:85b3fd62ea1a | 235 | #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ |
| NYX | 0:85b3fd62ea1a | 236 | #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ |
| NYX | 0:85b3fd62ea1a | 237 | #endif /* DMA_SxCR_CHSEL_3 */ |
| NYX | 0:85b3fd62ea1a | 238 | /** |
| NYX | 0:85b3fd62ea1a | 239 | * @} |
| NYX | 0:85b3fd62ea1a | 240 | */ |
| NYX | 0:85b3fd62ea1a | 241 | |
| NYX | 0:85b3fd62ea1a | 242 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| NYX | 0:85b3fd62ea1a | 243 | * @brief DMA data transfer direction |
| NYX | 0:85b3fd62ea1a | 244 | * @{ |
| NYX | 0:85b3fd62ea1a | 245 | */ |
| NYX | 0:85b3fd62ea1a | 246 | #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
| NYX | 0:85b3fd62ea1a | 247 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ |
| NYX | 0:85b3fd62ea1a | 248 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ |
| NYX | 0:85b3fd62ea1a | 249 | /** |
| NYX | 0:85b3fd62ea1a | 250 | * @} |
| NYX | 0:85b3fd62ea1a | 251 | */ |
| NYX | 0:85b3fd62ea1a | 252 | |
| NYX | 0:85b3fd62ea1a | 253 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| NYX | 0:85b3fd62ea1a | 254 | * @brief DMA peripheral incremented mode |
| NYX | 0:85b3fd62ea1a | 255 | * @{ |
| NYX | 0:85b3fd62ea1a | 256 | */ |
| NYX | 0:85b3fd62ea1a | 257 | #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ |
| NYX | 0:85b3fd62ea1a | 258 | #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ |
| NYX | 0:85b3fd62ea1a | 259 | /** |
| NYX | 0:85b3fd62ea1a | 260 | * @} |
| NYX | 0:85b3fd62ea1a | 261 | */ |
| NYX | 0:85b3fd62ea1a | 262 | |
| NYX | 0:85b3fd62ea1a | 263 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| NYX | 0:85b3fd62ea1a | 264 | * @brief DMA memory incremented mode |
| NYX | 0:85b3fd62ea1a | 265 | * @{ |
| NYX | 0:85b3fd62ea1a | 266 | */ |
| NYX | 0:85b3fd62ea1a | 267 | #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ |
| NYX | 0:85b3fd62ea1a | 268 | #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ |
| NYX | 0:85b3fd62ea1a | 269 | /** |
| NYX | 0:85b3fd62ea1a | 270 | * @} |
| NYX | 0:85b3fd62ea1a | 271 | */ |
| NYX | 0:85b3fd62ea1a | 272 | |
| NYX | 0:85b3fd62ea1a | 273 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| NYX | 0:85b3fd62ea1a | 274 | * @brief DMA peripheral data size |
| NYX | 0:85b3fd62ea1a | 275 | * @{ |
| NYX | 0:85b3fd62ea1a | 276 | */ |
| NYX | 0:85b3fd62ea1a | 277 | #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ |
| NYX | 0:85b3fd62ea1a | 278 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
| NYX | 0:85b3fd62ea1a | 279 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
| NYX | 0:85b3fd62ea1a | 280 | /** |
| NYX | 0:85b3fd62ea1a | 281 | * @} |
| NYX | 0:85b3fd62ea1a | 282 | */ |
| NYX | 0:85b3fd62ea1a | 283 | |
| NYX | 0:85b3fd62ea1a | 284 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| NYX | 0:85b3fd62ea1a | 285 | * @brief DMA memory data size |
| NYX | 0:85b3fd62ea1a | 286 | * @{ |
| NYX | 0:85b3fd62ea1a | 287 | */ |
| NYX | 0:85b3fd62ea1a | 288 | #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ |
| NYX | 0:85b3fd62ea1a | 289 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
| NYX | 0:85b3fd62ea1a | 290 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ |
| NYX | 0:85b3fd62ea1a | 291 | /** |
| NYX | 0:85b3fd62ea1a | 292 | * @} |
| NYX | 0:85b3fd62ea1a | 293 | */ |
| NYX | 0:85b3fd62ea1a | 294 | |
| NYX | 0:85b3fd62ea1a | 295 | /** @defgroup DMA_mode DMA mode |
| NYX | 0:85b3fd62ea1a | 296 | * @brief DMA mode |
| NYX | 0:85b3fd62ea1a | 297 | * @{ |
| NYX | 0:85b3fd62ea1a | 298 | */ |
| NYX | 0:85b3fd62ea1a | 299 | #define DMA_NORMAL 0x00000000U /*!< Normal mode */ |
| NYX | 0:85b3fd62ea1a | 300 | #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ |
| NYX | 0:85b3fd62ea1a | 301 | #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ |
| NYX | 0:85b3fd62ea1a | 302 | /** |
| NYX | 0:85b3fd62ea1a | 303 | * @} |
| NYX | 0:85b3fd62ea1a | 304 | */ |
| NYX | 0:85b3fd62ea1a | 305 | |
| NYX | 0:85b3fd62ea1a | 306 | /** @defgroup DMA_Priority_level DMA Priority level |
| NYX | 0:85b3fd62ea1a | 307 | * @brief DMA priority levels |
| NYX | 0:85b3fd62ea1a | 308 | * @{ |
| NYX | 0:85b3fd62ea1a | 309 | */ |
| NYX | 0:85b3fd62ea1a | 310 | #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ |
| NYX | 0:85b3fd62ea1a | 311 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ |
| NYX | 0:85b3fd62ea1a | 312 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ |
| NYX | 0:85b3fd62ea1a | 313 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ |
| NYX | 0:85b3fd62ea1a | 314 | /** |
| NYX | 0:85b3fd62ea1a | 315 | * @} |
| NYX | 0:85b3fd62ea1a | 316 | */ |
| NYX | 0:85b3fd62ea1a | 317 | |
| NYX | 0:85b3fd62ea1a | 318 | /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode |
| NYX | 0:85b3fd62ea1a | 319 | * @brief DMA FIFO direct mode |
| NYX | 0:85b3fd62ea1a | 320 | * @{ |
| NYX | 0:85b3fd62ea1a | 321 | */ |
| NYX | 0:85b3fd62ea1a | 322 | #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ |
| NYX | 0:85b3fd62ea1a | 323 | #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ |
| NYX | 0:85b3fd62ea1a | 324 | /** |
| NYX | 0:85b3fd62ea1a | 325 | * @} |
| NYX | 0:85b3fd62ea1a | 326 | */ |
| NYX | 0:85b3fd62ea1a | 327 | |
| NYX | 0:85b3fd62ea1a | 328 | /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level |
| NYX | 0:85b3fd62ea1a | 329 | * @brief DMA FIFO level |
| NYX | 0:85b3fd62ea1a | 330 | * @{ |
| NYX | 0:85b3fd62ea1a | 331 | */ |
| NYX | 0:85b3fd62ea1a | 332 | #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ |
| NYX | 0:85b3fd62ea1a | 333 | #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ |
| NYX | 0:85b3fd62ea1a | 334 | #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ |
| NYX | 0:85b3fd62ea1a | 335 | #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ |
| NYX | 0:85b3fd62ea1a | 336 | /** |
| NYX | 0:85b3fd62ea1a | 337 | * @} |
| NYX | 0:85b3fd62ea1a | 338 | */ |
| NYX | 0:85b3fd62ea1a | 339 | |
| NYX | 0:85b3fd62ea1a | 340 | /** @defgroup DMA_Memory_burst DMA Memory burst |
| NYX | 0:85b3fd62ea1a | 341 | * @brief DMA memory burst |
| NYX | 0:85b3fd62ea1a | 342 | * @{ |
| NYX | 0:85b3fd62ea1a | 343 | */ |
| NYX | 0:85b3fd62ea1a | 344 | #define DMA_MBURST_SINGLE 0x00000000U |
| NYX | 0:85b3fd62ea1a | 345 | #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) |
| NYX | 0:85b3fd62ea1a | 346 | #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) |
| NYX | 0:85b3fd62ea1a | 347 | #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) |
| NYX | 0:85b3fd62ea1a | 348 | /** |
| NYX | 0:85b3fd62ea1a | 349 | * @} |
| NYX | 0:85b3fd62ea1a | 350 | */ |
| NYX | 0:85b3fd62ea1a | 351 | |
| NYX | 0:85b3fd62ea1a | 352 | /** @defgroup DMA_Peripheral_burst DMA Peripheral burst |
| NYX | 0:85b3fd62ea1a | 353 | * @brief DMA peripheral burst |
| NYX | 0:85b3fd62ea1a | 354 | * @{ |
| NYX | 0:85b3fd62ea1a | 355 | */ |
| NYX | 0:85b3fd62ea1a | 356 | #define DMA_PBURST_SINGLE 0x00000000U |
| NYX | 0:85b3fd62ea1a | 357 | #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) |
| NYX | 0:85b3fd62ea1a | 358 | #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) |
| NYX | 0:85b3fd62ea1a | 359 | #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) |
| NYX | 0:85b3fd62ea1a | 360 | /** |
| NYX | 0:85b3fd62ea1a | 361 | * @} |
| NYX | 0:85b3fd62ea1a | 362 | */ |
| NYX | 0:85b3fd62ea1a | 363 | |
| NYX | 0:85b3fd62ea1a | 364 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| NYX | 0:85b3fd62ea1a | 365 | * @brief DMA interrupts definition |
| NYX | 0:85b3fd62ea1a | 366 | * @{ |
| NYX | 0:85b3fd62ea1a | 367 | */ |
| NYX | 0:85b3fd62ea1a | 368 | #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) |
| NYX | 0:85b3fd62ea1a | 369 | #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) |
| NYX | 0:85b3fd62ea1a | 370 | #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) |
| NYX | 0:85b3fd62ea1a | 371 | #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) |
| NYX | 0:85b3fd62ea1a | 372 | #define DMA_IT_FE 0x00000080U |
| NYX | 0:85b3fd62ea1a | 373 | /** |
| NYX | 0:85b3fd62ea1a | 374 | * @} |
| NYX | 0:85b3fd62ea1a | 375 | */ |
| NYX | 0:85b3fd62ea1a | 376 | |
| NYX | 0:85b3fd62ea1a | 377 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| NYX | 0:85b3fd62ea1a | 378 | * @brief DMA flag definitions |
| NYX | 0:85b3fd62ea1a | 379 | * @{ |
| NYX | 0:85b3fd62ea1a | 380 | */ |
| NYX | 0:85b3fd62ea1a | 381 | #define DMA_FLAG_FEIF0_4 0x00800001U |
| NYX | 0:85b3fd62ea1a | 382 | #define DMA_FLAG_DMEIF0_4 0x00800004U |
| NYX | 0:85b3fd62ea1a | 383 | #define DMA_FLAG_TEIF0_4 0x00000008U |
| NYX | 0:85b3fd62ea1a | 384 | #define DMA_FLAG_HTIF0_4 0x00000010U |
| NYX | 0:85b3fd62ea1a | 385 | #define DMA_FLAG_TCIF0_4 0x00000020U |
| NYX | 0:85b3fd62ea1a | 386 | #define DMA_FLAG_FEIF1_5 0x00000040U |
| NYX | 0:85b3fd62ea1a | 387 | #define DMA_FLAG_DMEIF1_5 0x00000100U |
| NYX | 0:85b3fd62ea1a | 388 | #define DMA_FLAG_TEIF1_5 0x00000200U |
| NYX | 0:85b3fd62ea1a | 389 | #define DMA_FLAG_HTIF1_5 0x00000400U |
| NYX | 0:85b3fd62ea1a | 390 | #define DMA_FLAG_TCIF1_5 0x00000800U |
| NYX | 0:85b3fd62ea1a | 391 | #define DMA_FLAG_FEIF2_6 0x00010000U |
| NYX | 0:85b3fd62ea1a | 392 | #define DMA_FLAG_DMEIF2_6 0x00040000U |
| NYX | 0:85b3fd62ea1a | 393 | #define DMA_FLAG_TEIF2_6 0x00080000U |
| NYX | 0:85b3fd62ea1a | 394 | #define DMA_FLAG_HTIF2_6 0x00100000U |
| NYX | 0:85b3fd62ea1a | 395 | #define DMA_FLAG_TCIF2_6 0x00200000U |
| NYX | 0:85b3fd62ea1a | 396 | #define DMA_FLAG_FEIF3_7 0x00400000U |
| NYX | 0:85b3fd62ea1a | 397 | #define DMA_FLAG_DMEIF3_7 0x01000000U |
| NYX | 0:85b3fd62ea1a | 398 | #define DMA_FLAG_TEIF3_7 0x02000000U |
| NYX | 0:85b3fd62ea1a | 399 | #define DMA_FLAG_HTIF3_7 0x04000000U |
| NYX | 0:85b3fd62ea1a | 400 | #define DMA_FLAG_TCIF3_7 0x08000000U |
| NYX | 0:85b3fd62ea1a | 401 | /** |
| NYX | 0:85b3fd62ea1a | 402 | * @} |
| NYX | 0:85b3fd62ea1a | 403 | */ |
| NYX | 0:85b3fd62ea1a | 404 | |
| NYX | 0:85b3fd62ea1a | 405 | /** |
| NYX | 0:85b3fd62ea1a | 406 | * @} |
| NYX | 0:85b3fd62ea1a | 407 | */ |
| NYX | 0:85b3fd62ea1a | 408 | |
| NYX | 0:85b3fd62ea1a | 409 | /* Exported macro ------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 410 | |
| NYX | 0:85b3fd62ea1a | 411 | /** @brief Reset DMA handle state |
| NYX | 0:85b3fd62ea1a | 412 | * @param __HANDLE__: specifies the DMA handle. |
| NYX | 0:85b3fd62ea1a | 413 | * @retval None |
| NYX | 0:85b3fd62ea1a | 414 | */ |
| NYX | 0:85b3fd62ea1a | 415 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| NYX | 0:85b3fd62ea1a | 416 | |
| NYX | 0:85b3fd62ea1a | 417 | /** |
| NYX | 0:85b3fd62ea1a | 418 | * @brief Return the current DMA Stream FIFO filled level. |
| NYX | 0:85b3fd62ea1a | 419 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 420 | * @retval The FIFO filling state. |
| NYX | 0:85b3fd62ea1a | 421 | * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full |
| NYX | 0:85b3fd62ea1a | 422 | * and not empty. |
| NYX | 0:85b3fd62ea1a | 423 | * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. |
| NYX | 0:85b3fd62ea1a | 424 | * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. |
| NYX | 0:85b3fd62ea1a | 425 | * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. |
| NYX | 0:85b3fd62ea1a | 426 | * - DMA_FIFOStatus_Empty: when FIFO is empty |
| NYX | 0:85b3fd62ea1a | 427 | * - DMA_FIFOStatus_Full: when FIFO is full |
| NYX | 0:85b3fd62ea1a | 428 | */ |
| NYX | 0:85b3fd62ea1a | 429 | #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) |
| NYX | 0:85b3fd62ea1a | 430 | |
| NYX | 0:85b3fd62ea1a | 431 | /** |
| NYX | 0:85b3fd62ea1a | 432 | * @brief Enable the specified DMA Stream. |
| NYX | 0:85b3fd62ea1a | 433 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 434 | * @retval None |
| NYX | 0:85b3fd62ea1a | 435 | */ |
| NYX | 0:85b3fd62ea1a | 436 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) |
| NYX | 0:85b3fd62ea1a | 437 | |
| NYX | 0:85b3fd62ea1a | 438 | /** |
| NYX | 0:85b3fd62ea1a | 439 | * @brief Disable the specified DMA Stream. |
| NYX | 0:85b3fd62ea1a | 440 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 441 | * @retval None |
| NYX | 0:85b3fd62ea1a | 442 | */ |
| NYX | 0:85b3fd62ea1a | 443 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) |
| NYX | 0:85b3fd62ea1a | 444 | |
| NYX | 0:85b3fd62ea1a | 445 | /* Interrupt & Flag management */ |
| NYX | 0:85b3fd62ea1a | 446 | |
| NYX | 0:85b3fd62ea1a | 447 | /** |
| NYX | 0:85b3fd62ea1a | 448 | * @brief Return the current DMA Stream transfer complete flag. |
| NYX | 0:85b3fd62ea1a | 449 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 450 | * @retval The specified transfer complete flag index. |
| NYX | 0:85b3fd62ea1a | 451 | */ |
| NYX | 0:85b3fd62ea1a | 452 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| NYX | 0:85b3fd62ea1a | 453 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 454 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 455 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 456 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 457 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 458 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 459 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 460 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 461 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 462 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 463 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 464 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 465 | DMA_FLAG_TCIF3_7) |
| NYX | 0:85b3fd62ea1a | 466 | |
| NYX | 0:85b3fd62ea1a | 467 | /** |
| NYX | 0:85b3fd62ea1a | 468 | * @brief Return the current DMA Stream half transfer complete flag. |
| NYX | 0:85b3fd62ea1a | 469 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 470 | * @retval The specified half transfer complete flag index. |
| NYX | 0:85b3fd62ea1a | 471 | */ |
| NYX | 0:85b3fd62ea1a | 472 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| NYX | 0:85b3fd62ea1a | 473 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 474 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 475 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 476 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 477 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 478 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 479 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 480 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 481 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 482 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 483 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 484 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 485 | DMA_FLAG_HTIF3_7) |
| NYX | 0:85b3fd62ea1a | 486 | |
| NYX | 0:85b3fd62ea1a | 487 | /** |
| NYX | 0:85b3fd62ea1a | 488 | * @brief Return the current DMA Stream transfer error flag. |
| NYX | 0:85b3fd62ea1a | 489 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 490 | * @retval The specified transfer error flag index. |
| NYX | 0:85b3fd62ea1a | 491 | */ |
| NYX | 0:85b3fd62ea1a | 492 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| NYX | 0:85b3fd62ea1a | 493 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 494 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 495 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 496 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 497 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 498 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 499 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 500 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 501 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 502 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 503 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 504 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 505 | DMA_FLAG_TEIF3_7) |
| NYX | 0:85b3fd62ea1a | 506 | |
| NYX | 0:85b3fd62ea1a | 507 | /** |
| NYX | 0:85b3fd62ea1a | 508 | * @brief Return the current DMA Stream FIFO error flag. |
| NYX | 0:85b3fd62ea1a | 509 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 510 | * @retval The specified FIFO error flag index. |
| NYX | 0:85b3fd62ea1a | 511 | */ |
| NYX | 0:85b3fd62ea1a | 512 | #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ |
| NYX | 0:85b3fd62ea1a | 513 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 514 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 515 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 516 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 517 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 518 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 519 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 520 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 521 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 522 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 523 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 524 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 525 | DMA_FLAG_FEIF3_7) |
| NYX | 0:85b3fd62ea1a | 526 | |
| NYX | 0:85b3fd62ea1a | 527 | /** |
| NYX | 0:85b3fd62ea1a | 528 | * @brief Return the current DMA Stream direct mode error flag. |
| NYX | 0:85b3fd62ea1a | 529 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 530 | * @retval The specified direct mode error flag index. |
| NYX | 0:85b3fd62ea1a | 531 | */ |
| NYX | 0:85b3fd62ea1a | 532 | #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ |
| NYX | 0:85b3fd62ea1a | 533 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 534 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 535 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 536 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| NYX | 0:85b3fd62ea1a | 537 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 538 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 539 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 540 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| NYX | 0:85b3fd62ea1a | 541 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 542 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 543 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 544 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| NYX | 0:85b3fd62ea1a | 545 | DMA_FLAG_DMEIF3_7) |
| NYX | 0:85b3fd62ea1a | 546 | |
| NYX | 0:85b3fd62ea1a | 547 | /** |
| NYX | 0:85b3fd62ea1a | 548 | * @brief Get the DMA Stream pending flags. |
| NYX | 0:85b3fd62ea1a | 549 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 550 | * @param __FLAG__: Get the specified flag. |
| NYX | 0:85b3fd62ea1a | 551 | * This parameter can be any combination of the following values: |
| NYX | 0:85b3fd62ea1a | 552 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| NYX | 0:85b3fd62ea1a | 553 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| NYX | 0:85b3fd62ea1a | 554 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| NYX | 0:85b3fd62ea1a | 555 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| NYX | 0:85b3fd62ea1a | 556 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| NYX | 0:85b3fd62ea1a | 557 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| NYX | 0:85b3fd62ea1a | 558 | * @retval The state of FLAG (SET or RESET). |
| NYX | 0:85b3fd62ea1a | 559 | */ |
| NYX | 0:85b3fd62ea1a | 560 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
| NYX | 0:85b3fd62ea1a | 561 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ |
| NYX | 0:85b3fd62ea1a | 562 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ |
| NYX | 0:85b3fd62ea1a | 563 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) |
| NYX | 0:85b3fd62ea1a | 564 | |
| NYX | 0:85b3fd62ea1a | 565 | /** |
| NYX | 0:85b3fd62ea1a | 566 | * @brief Clear the DMA Stream pending flags. |
| NYX | 0:85b3fd62ea1a | 567 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 568 | * @param __FLAG__: specifies the flag to clear. |
| NYX | 0:85b3fd62ea1a | 569 | * This parameter can be any combination of the following values: |
| NYX | 0:85b3fd62ea1a | 570 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| NYX | 0:85b3fd62ea1a | 571 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| NYX | 0:85b3fd62ea1a | 572 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| NYX | 0:85b3fd62ea1a | 573 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| NYX | 0:85b3fd62ea1a | 574 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| NYX | 0:85b3fd62ea1a | 575 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| NYX | 0:85b3fd62ea1a | 576 | * @retval None |
| NYX | 0:85b3fd62ea1a | 577 | */ |
| NYX | 0:85b3fd62ea1a | 578 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| NYX | 0:85b3fd62ea1a | 579 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ |
| NYX | 0:85b3fd62ea1a | 580 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ |
| NYX | 0:85b3fd62ea1a | 581 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) |
| NYX | 0:85b3fd62ea1a | 582 | |
| NYX | 0:85b3fd62ea1a | 583 | /** |
| NYX | 0:85b3fd62ea1a | 584 | * @brief Enable the specified DMA Stream interrupts. |
| NYX | 0:85b3fd62ea1a | 585 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 586 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| NYX | 0:85b3fd62ea1a | 587 | * This parameter can be any combination of the following values: |
| NYX | 0:85b3fd62ea1a | 588 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| NYX | 0:85b3fd62ea1a | 589 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| NYX | 0:85b3fd62ea1a | 590 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| NYX | 0:85b3fd62ea1a | 591 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| NYX | 0:85b3fd62ea1a | 592 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| NYX | 0:85b3fd62ea1a | 593 | * @retval None |
| NYX | 0:85b3fd62ea1a | 594 | */ |
| NYX | 0:85b3fd62ea1a | 595 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| NYX | 0:85b3fd62ea1a | 596 | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) |
| NYX | 0:85b3fd62ea1a | 597 | |
| NYX | 0:85b3fd62ea1a | 598 | /** |
| NYX | 0:85b3fd62ea1a | 599 | * @brief Disable the specified DMA Stream interrupts. |
| NYX | 0:85b3fd62ea1a | 600 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 601 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| NYX | 0:85b3fd62ea1a | 602 | * This parameter can be any combination of the following values: |
| NYX | 0:85b3fd62ea1a | 603 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| NYX | 0:85b3fd62ea1a | 604 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| NYX | 0:85b3fd62ea1a | 605 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| NYX | 0:85b3fd62ea1a | 606 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| NYX | 0:85b3fd62ea1a | 607 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| NYX | 0:85b3fd62ea1a | 608 | * @retval None |
| NYX | 0:85b3fd62ea1a | 609 | */ |
| NYX | 0:85b3fd62ea1a | 610 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| NYX | 0:85b3fd62ea1a | 611 | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) |
| NYX | 0:85b3fd62ea1a | 612 | |
| NYX | 0:85b3fd62ea1a | 613 | /** |
| NYX | 0:85b3fd62ea1a | 614 | * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. |
| NYX | 0:85b3fd62ea1a | 615 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 616 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| NYX | 0:85b3fd62ea1a | 617 | * This parameter can be one of the following values: |
| NYX | 0:85b3fd62ea1a | 618 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| NYX | 0:85b3fd62ea1a | 619 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| NYX | 0:85b3fd62ea1a | 620 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| NYX | 0:85b3fd62ea1a | 621 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| NYX | 0:85b3fd62ea1a | 622 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| NYX | 0:85b3fd62ea1a | 623 | * @retval The state of DMA_IT. |
| NYX | 0:85b3fd62ea1a | 624 | */ |
| NYX | 0:85b3fd62ea1a | 625 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| NYX | 0:85b3fd62ea1a | 626 | ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ |
| NYX | 0:85b3fd62ea1a | 627 | ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) |
| NYX | 0:85b3fd62ea1a | 628 | |
| NYX | 0:85b3fd62ea1a | 629 | /** |
| NYX | 0:85b3fd62ea1a | 630 | * @brief Writes the number of data units to be transferred on the DMA Stream. |
| NYX | 0:85b3fd62ea1a | 631 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 632 | * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) |
| NYX | 0:85b3fd62ea1a | 633 | * Number of data items depends only on the Peripheral data format. |
| NYX | 0:85b3fd62ea1a | 634 | * |
| NYX | 0:85b3fd62ea1a | 635 | * @note If Peripheral data format is Bytes: number of data units is equal |
| NYX | 0:85b3fd62ea1a | 636 | * to total number of bytes to be transferred. |
| NYX | 0:85b3fd62ea1a | 637 | * |
| NYX | 0:85b3fd62ea1a | 638 | * @note If Peripheral data format is Half-Word: number of data units is |
| NYX | 0:85b3fd62ea1a | 639 | * equal to total number of bytes to be transferred / 2. |
| NYX | 0:85b3fd62ea1a | 640 | * |
| NYX | 0:85b3fd62ea1a | 641 | * @note If Peripheral data format is Word: number of data units is equal |
| NYX | 0:85b3fd62ea1a | 642 | * to total number of bytes to be transferred / 4. |
| NYX | 0:85b3fd62ea1a | 643 | * |
| NYX | 0:85b3fd62ea1a | 644 | * @retval The number of remaining data units in the current DMAy Streamx transfer. |
| NYX | 0:85b3fd62ea1a | 645 | */ |
| NYX | 0:85b3fd62ea1a | 646 | #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) |
| NYX | 0:85b3fd62ea1a | 647 | |
| NYX | 0:85b3fd62ea1a | 648 | /** |
| NYX | 0:85b3fd62ea1a | 649 | * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. |
| NYX | 0:85b3fd62ea1a | 650 | * @param __HANDLE__: DMA handle |
| NYX | 0:85b3fd62ea1a | 651 | * |
| NYX | 0:85b3fd62ea1a | 652 | * @retval The number of remaining data units in the current DMA Stream transfer. |
| NYX | 0:85b3fd62ea1a | 653 | */ |
| NYX | 0:85b3fd62ea1a | 654 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) |
| NYX | 0:85b3fd62ea1a | 655 | |
| NYX | 0:85b3fd62ea1a | 656 | |
| NYX | 0:85b3fd62ea1a | 657 | /* Include DMA HAL Extension module */ |
| NYX | 0:85b3fd62ea1a | 658 | #include "stm32f4xx_hal_dma_ex.h" |
| NYX | 0:85b3fd62ea1a | 659 | |
| NYX | 0:85b3fd62ea1a | 660 | /* Exported functions --------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 661 | |
| NYX | 0:85b3fd62ea1a | 662 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
| NYX | 0:85b3fd62ea1a | 663 | * @brief DMA Exported functions |
| NYX | 0:85b3fd62ea1a | 664 | * @{ |
| NYX | 0:85b3fd62ea1a | 665 | */ |
| NYX | 0:85b3fd62ea1a | 666 | |
| NYX | 0:85b3fd62ea1a | 667 | /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
| NYX | 0:85b3fd62ea1a | 668 | * @brief Initialization and de-initialization functions |
| NYX | 0:85b3fd62ea1a | 669 | * @{ |
| NYX | 0:85b3fd62ea1a | 670 | */ |
| NYX | 0:85b3fd62ea1a | 671 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| NYX | 0:85b3fd62ea1a | 672 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); |
| NYX | 0:85b3fd62ea1a | 673 | /** |
| NYX | 0:85b3fd62ea1a | 674 | * @} |
| NYX | 0:85b3fd62ea1a | 675 | */ |
| NYX | 0:85b3fd62ea1a | 676 | |
| NYX | 0:85b3fd62ea1a | 677 | /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions |
| NYX | 0:85b3fd62ea1a | 678 | * @brief I/O operation functions |
| NYX | 0:85b3fd62ea1a | 679 | * @{ |
| NYX | 0:85b3fd62ea1a | 680 | */ |
| NYX | 0:85b3fd62ea1a | 681 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| NYX | 0:85b3fd62ea1a | 682 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| NYX | 0:85b3fd62ea1a | 683 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| NYX | 0:85b3fd62ea1a | 684 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
| NYX | 0:85b3fd62ea1a | 685 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); |
| NYX | 0:85b3fd62ea1a | 686 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| NYX | 0:85b3fd62ea1a | 687 | HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); |
| NYX | 0:85b3fd62ea1a | 688 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); |
| NYX | 0:85b3fd62ea1a | 689 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); |
| NYX | 0:85b3fd62ea1a | 690 | |
| NYX | 0:85b3fd62ea1a | 691 | /** |
| NYX | 0:85b3fd62ea1a | 692 | * @} |
| NYX | 0:85b3fd62ea1a | 693 | */ |
| NYX | 0:85b3fd62ea1a | 694 | |
| NYX | 0:85b3fd62ea1a | 695 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions |
| NYX | 0:85b3fd62ea1a | 696 | * @brief Peripheral State functions |
| NYX | 0:85b3fd62ea1a | 697 | * @{ |
| NYX | 0:85b3fd62ea1a | 698 | */ |
| NYX | 0:85b3fd62ea1a | 699 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| NYX | 0:85b3fd62ea1a | 700 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| NYX | 0:85b3fd62ea1a | 701 | /** |
| NYX | 0:85b3fd62ea1a | 702 | * @} |
| NYX | 0:85b3fd62ea1a | 703 | */ |
| NYX | 0:85b3fd62ea1a | 704 | /** |
| NYX | 0:85b3fd62ea1a | 705 | * @} |
| NYX | 0:85b3fd62ea1a | 706 | */ |
| NYX | 0:85b3fd62ea1a | 707 | /* Private Constants -------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 708 | /** @defgroup DMA_Private_Constants DMA Private Constants |
| NYX | 0:85b3fd62ea1a | 709 | * @brief DMA private defines and constants |
| NYX | 0:85b3fd62ea1a | 710 | * @{ |
| NYX | 0:85b3fd62ea1a | 711 | */ |
| NYX | 0:85b3fd62ea1a | 712 | /** |
| NYX | 0:85b3fd62ea1a | 713 | * @} |
| NYX | 0:85b3fd62ea1a | 714 | */ |
| NYX | 0:85b3fd62ea1a | 715 | |
| NYX | 0:85b3fd62ea1a | 716 | /* Private macros ------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 717 | /** @defgroup DMA_Private_Macros DMA Private Macros |
| NYX | 0:85b3fd62ea1a | 718 | * @brief DMA private macros |
| NYX | 0:85b3fd62ea1a | 719 | * @{ |
| NYX | 0:85b3fd62ea1a | 720 | */ |
| NYX | 0:85b3fd62ea1a | 721 | #if defined (DMA_SxCR_CHSEL_3) |
| NYX | 0:85b3fd62ea1a | 722 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ |
| NYX | 0:85b3fd62ea1a | 723 | ((CHANNEL) == DMA_CHANNEL_1) || \ |
| NYX | 0:85b3fd62ea1a | 724 | ((CHANNEL) == DMA_CHANNEL_2) || \ |
| NYX | 0:85b3fd62ea1a | 725 | ((CHANNEL) == DMA_CHANNEL_3) || \ |
| NYX | 0:85b3fd62ea1a | 726 | ((CHANNEL) == DMA_CHANNEL_4) || \ |
| NYX | 0:85b3fd62ea1a | 727 | ((CHANNEL) == DMA_CHANNEL_5) || \ |
| NYX | 0:85b3fd62ea1a | 728 | ((CHANNEL) == DMA_CHANNEL_6) || \ |
| NYX | 0:85b3fd62ea1a | 729 | ((CHANNEL) == DMA_CHANNEL_7) || \ |
| NYX | 0:85b3fd62ea1a | 730 | ((CHANNEL) == DMA_CHANNEL_8) || \ |
| NYX | 0:85b3fd62ea1a | 731 | ((CHANNEL) == DMA_CHANNEL_9) || \ |
| NYX | 0:85b3fd62ea1a | 732 | ((CHANNEL) == DMA_CHANNEL_10)|| \ |
| NYX | 0:85b3fd62ea1a | 733 | ((CHANNEL) == DMA_CHANNEL_11)|| \ |
| NYX | 0:85b3fd62ea1a | 734 | ((CHANNEL) == DMA_CHANNEL_12)|| \ |
| NYX | 0:85b3fd62ea1a | 735 | ((CHANNEL) == DMA_CHANNEL_13)|| \ |
| NYX | 0:85b3fd62ea1a | 736 | ((CHANNEL) == DMA_CHANNEL_14)|| \ |
| NYX | 0:85b3fd62ea1a | 737 | ((CHANNEL) == DMA_CHANNEL_15)) |
| NYX | 0:85b3fd62ea1a | 738 | #else |
| NYX | 0:85b3fd62ea1a | 739 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ |
| NYX | 0:85b3fd62ea1a | 740 | ((CHANNEL) == DMA_CHANNEL_1) || \ |
| NYX | 0:85b3fd62ea1a | 741 | ((CHANNEL) == DMA_CHANNEL_2) || \ |
| NYX | 0:85b3fd62ea1a | 742 | ((CHANNEL) == DMA_CHANNEL_3) || \ |
| NYX | 0:85b3fd62ea1a | 743 | ((CHANNEL) == DMA_CHANNEL_4) || \ |
| NYX | 0:85b3fd62ea1a | 744 | ((CHANNEL) == DMA_CHANNEL_5) || \ |
| NYX | 0:85b3fd62ea1a | 745 | ((CHANNEL) == DMA_CHANNEL_6) || \ |
| NYX | 0:85b3fd62ea1a | 746 | ((CHANNEL) == DMA_CHANNEL_7)) |
| NYX | 0:85b3fd62ea1a | 747 | #endif /* DMA_SxCR_CHSEL_3 */ |
| NYX | 0:85b3fd62ea1a | 748 | |
| NYX | 0:85b3fd62ea1a | 749 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| NYX | 0:85b3fd62ea1a | 750 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| NYX | 0:85b3fd62ea1a | 751 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| NYX | 0:85b3fd62ea1a | 752 | |
| NYX | 0:85b3fd62ea1a | 753 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) |
| NYX | 0:85b3fd62ea1a | 754 | |
| NYX | 0:85b3fd62ea1a | 755 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| NYX | 0:85b3fd62ea1a | 756 | ((STATE) == DMA_PINC_DISABLE)) |
| NYX | 0:85b3fd62ea1a | 757 | |
| NYX | 0:85b3fd62ea1a | 758 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| NYX | 0:85b3fd62ea1a | 759 | ((STATE) == DMA_MINC_DISABLE)) |
| NYX | 0:85b3fd62ea1a | 760 | |
| NYX | 0:85b3fd62ea1a | 761 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| NYX | 0:85b3fd62ea1a | 762 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| NYX | 0:85b3fd62ea1a | 763 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| NYX | 0:85b3fd62ea1a | 764 | |
| NYX | 0:85b3fd62ea1a | 765 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| NYX | 0:85b3fd62ea1a | 766 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| NYX | 0:85b3fd62ea1a | 767 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| NYX | 0:85b3fd62ea1a | 768 | |
| NYX | 0:85b3fd62ea1a | 769 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| NYX | 0:85b3fd62ea1a | 770 | ((MODE) == DMA_CIRCULAR) || \ |
| NYX | 0:85b3fd62ea1a | 771 | ((MODE) == DMA_PFCTRL)) |
| NYX | 0:85b3fd62ea1a | 772 | |
| NYX | 0:85b3fd62ea1a | 773 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| NYX | 0:85b3fd62ea1a | 774 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| NYX | 0:85b3fd62ea1a | 775 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| NYX | 0:85b3fd62ea1a | 776 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| NYX | 0:85b3fd62ea1a | 777 | |
| NYX | 0:85b3fd62ea1a | 778 | #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ |
| NYX | 0:85b3fd62ea1a | 779 | ((STATE) == DMA_FIFOMODE_ENABLE)) |
| NYX | 0:85b3fd62ea1a | 780 | |
| NYX | 0:85b3fd62ea1a | 781 | #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ |
| NYX | 0:85b3fd62ea1a | 782 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ |
| NYX | 0:85b3fd62ea1a | 783 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ |
| NYX | 0:85b3fd62ea1a | 784 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) |
| NYX | 0:85b3fd62ea1a | 785 | |
| NYX | 0:85b3fd62ea1a | 786 | #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ |
| NYX | 0:85b3fd62ea1a | 787 | ((BURST) == DMA_MBURST_INC4) || \ |
| NYX | 0:85b3fd62ea1a | 788 | ((BURST) == DMA_MBURST_INC8) || \ |
| NYX | 0:85b3fd62ea1a | 789 | ((BURST) == DMA_MBURST_INC16)) |
| NYX | 0:85b3fd62ea1a | 790 | |
| NYX | 0:85b3fd62ea1a | 791 | #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ |
| NYX | 0:85b3fd62ea1a | 792 | ((BURST) == DMA_PBURST_INC4) || \ |
| NYX | 0:85b3fd62ea1a | 793 | ((BURST) == DMA_PBURST_INC8) || \ |
| NYX | 0:85b3fd62ea1a | 794 | ((BURST) == DMA_PBURST_INC16)) |
| NYX | 0:85b3fd62ea1a | 795 | /** |
| NYX | 0:85b3fd62ea1a | 796 | * @} |
| NYX | 0:85b3fd62ea1a | 797 | */ |
| NYX | 0:85b3fd62ea1a | 798 | |
| NYX | 0:85b3fd62ea1a | 799 | /* Private functions ---------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 800 | /** @defgroup DMA_Private_Functions DMA Private Functions |
| NYX | 0:85b3fd62ea1a | 801 | * @brief DMA private functions |
| NYX | 0:85b3fd62ea1a | 802 | * @{ |
| NYX | 0:85b3fd62ea1a | 803 | */ |
| NYX | 0:85b3fd62ea1a | 804 | /** |
| NYX | 0:85b3fd62ea1a | 805 | * @} |
| NYX | 0:85b3fd62ea1a | 806 | */ |
| NYX | 0:85b3fd62ea1a | 807 | |
| NYX | 0:85b3fd62ea1a | 808 | /** |
| NYX | 0:85b3fd62ea1a | 809 | * @} |
| NYX | 0:85b3fd62ea1a | 810 | */ |
| NYX | 0:85b3fd62ea1a | 811 | |
| NYX | 0:85b3fd62ea1a | 812 | /** |
| NYX | 0:85b3fd62ea1a | 813 | * @} |
| NYX | 0:85b3fd62ea1a | 814 | */ |
| NYX | 0:85b3fd62ea1a | 815 | |
| NYX | 0:85b3fd62ea1a | 816 | #ifdef __cplusplus |
| NYX | 0:85b3fd62ea1a | 817 | } |
| NYX | 0:85b3fd62ea1a | 818 | #endif |
| NYX | 0:85b3fd62ea1a | 819 | |
| NYX | 0:85b3fd62ea1a | 820 | #endif /* __STM32F4xx_HAL_DMA_H */ |
| NYX | 0:85b3fd62ea1a | 821 | |
| NYX | 0:85b3fd62ea1a | 822 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |