Takaaki Numai / mbed-dev

inport from local

Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_dma.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief DMA HAL module driver.
NYX 0:85b3fd62ea1a 8 *
NYX 0:85b3fd62ea1a 9 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 10 * functionalities of the Direct Memory Access (DMA) peripheral:
NYX 0:85b3fd62ea1a 11 * + Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 12 * + IO operation functions
NYX 0:85b3fd62ea1a 13 * + Peripheral State and errors functions
NYX 0:85b3fd62ea1a 14 @verbatim
NYX 0:85b3fd62ea1a 15 ==============================================================================
NYX 0:85b3fd62ea1a 16 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 17 ==============================================================================
NYX 0:85b3fd62ea1a 18 [..]
NYX 0:85b3fd62ea1a 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
NYX 0:85b3fd62ea1a 20 (except for internal SRAM/FLASH memories: no initialization is
NYX 0:85b3fd62ea1a 21 necessary) please refer to Reference manual for connection between peripherals
NYX 0:85b3fd62ea1a 22 and DMA requests.
NYX 0:85b3fd62ea1a 23
NYX 0:85b3fd62ea1a 24 (#) For a given Stream, program the required configuration through the following parameters:
NYX 0:85b3fd62ea1a 25 Transfer Direction, Source and Destination data formats,
NYX 0:85b3fd62ea1a 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
NYX 0:85b3fd62ea1a 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
NYX 0:85b3fd62ea1a 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
NYX 0:85b3fd62ea1a 29
NYX 0:85b3fd62ea1a 30 -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
NYX 0:85b3fd62ea1a 31 __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
NYX 0:85b3fd62ea1a 32
NYX 0:85b3fd62ea1a 33 *** Polling mode IO operation ***
NYX 0:85b3fd62ea1a 34 =================================
NYX 0:85b3fd62ea1a 35 [..]
NYX 0:85b3fd62ea1a 36 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
NYX 0:85b3fd62ea1a 37 address and destination address and the Length of data to be transferred.
NYX 0:85b3fd62ea1a 38 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
NYX 0:85b3fd62ea1a 39 case a fixed Timeout can be configured by User depending from his application.
NYX 0:85b3fd62ea1a 40 (+) Use HAL_DMA_Abort() function to abort the current transfer.
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 *** Interrupt mode IO operation ***
NYX 0:85b3fd62ea1a 43 ===================================
NYX 0:85b3fd62ea1a 44 [..]
NYX 0:85b3fd62ea1a 45 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
NYX 0:85b3fd62ea1a 46 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
NYX 0:85b3fd62ea1a 47 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
NYX 0:85b3fd62ea1a 48 Source address and destination address and the Length of data to be transferred. In this
NYX 0:85b3fd62ea1a 49 case the DMA interrupt is configured
NYX 0:85b3fd62ea1a 50 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
NYX 0:85b3fd62ea1a 51 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
NYX 0:85b3fd62ea1a 52 add his own function by customization of function pointer XferCpltCallback and
NYX 0:85b3fd62ea1a 53 XferErrorCallback (i.e a member of DMA handle structure).
NYX 0:85b3fd62ea1a 54 [..]
NYX 0:85b3fd62ea1a 55 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
NYX 0:85b3fd62ea1a 56 detection.
NYX 0:85b3fd62ea1a 57
NYX 0:85b3fd62ea1a 58 (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
NYX 0:85b3fd62ea1a 59
NYX 0:85b3fd62ea1a 60 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
NYX 0:85b3fd62ea1a 61
NYX 0:85b3fd62ea1a 62 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
NYX 0:85b3fd62ea1a 63 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
NYX 0:85b3fd62ea1a 64 Half-Word data size for the peripheral to access its data register and set Word data size
NYX 0:85b3fd62ea1a 65 for the Memory to gain in access time. Each two half words will be packed and written in
NYX 0:85b3fd62ea1a 66 a single access to a Word in the Memory).
NYX 0:85b3fd62ea1a 67
NYX 0:85b3fd62ea1a 68 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
NYX 0:85b3fd62ea1a 69 and Destination. In this case the Peripheral Data Size will be applied to both Source
NYX 0:85b3fd62ea1a 70 and Destination.
NYX 0:85b3fd62ea1a 71
NYX 0:85b3fd62ea1a 72 *** DMA HAL driver macros list ***
NYX 0:85b3fd62ea1a 73 =============================================
NYX 0:85b3fd62ea1a 74 [..]
NYX 0:85b3fd62ea1a 75 Below the list of most used macros in DMA HAL driver.
NYX 0:85b3fd62ea1a 76
NYX 0:85b3fd62ea1a 77 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
NYX 0:85b3fd62ea1a 78 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
NYX 0:85b3fd62ea1a 79 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
NYX 0:85b3fd62ea1a 80
NYX 0:85b3fd62ea1a 81 [..]
NYX 0:85b3fd62ea1a 82 (@) You can refer to the DMA HAL driver header file for more useful macros
NYX 0:85b3fd62ea1a 83
NYX 0:85b3fd62ea1a 84 @endverbatim
NYX 0:85b3fd62ea1a 85 ******************************************************************************
NYX 0:85b3fd62ea1a 86 * @attention
NYX 0:85b3fd62ea1a 87 *
NYX 0:85b3fd62ea1a 88 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 89 *
NYX 0:85b3fd62ea1a 90 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 91 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 92 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 93 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 94 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 95 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 96 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 97 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 98 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 99 * without specific prior written permission.
NYX 0:85b3fd62ea1a 100 *
NYX 0:85b3fd62ea1a 101 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 102 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 103 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 104 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 105 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 106 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 107 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 108 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 109 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 110 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 111 *
NYX 0:85b3fd62ea1a 112 ******************************************************************************
NYX 0:85b3fd62ea1a 113 */
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 116 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 119 * @{
NYX 0:85b3fd62ea1a 120 */
NYX 0:85b3fd62ea1a 121
NYX 0:85b3fd62ea1a 122 /** @defgroup DMA DMA
NYX 0:85b3fd62ea1a 123 * @brief DMA HAL module driver
NYX 0:85b3fd62ea1a 124 * @{
NYX 0:85b3fd62ea1a 125 */
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 #ifdef HAL_DMA_MODULE_ENABLED
NYX 0:85b3fd62ea1a 128
NYX 0:85b3fd62ea1a 129 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 130 typedef struct
NYX 0:85b3fd62ea1a 131 {
NYX 0:85b3fd62ea1a 132 __IO uint32_t ISR; /*!< DMA interrupt status register */
NYX 0:85b3fd62ea1a 133 __IO uint32_t Reserved0;
NYX 0:85b3fd62ea1a 134 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
NYX 0:85b3fd62ea1a 135 } DMA_Base_Registers;
NYX 0:85b3fd62ea1a 136
NYX 0:85b3fd62ea1a 137 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 138 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 139 /** @addtogroup DMA_Private_Constants
NYX 0:85b3fd62ea1a 140 * @{
NYX 0:85b3fd62ea1a 141 */
NYX 0:85b3fd62ea1a 142 #define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */
NYX 0:85b3fd62ea1a 143 /**
NYX 0:85b3fd62ea1a 144 * @}
NYX 0:85b3fd62ea1a 145 */
NYX 0:85b3fd62ea1a 146 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 147 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 148 /** @addtogroup DMA_Private_Functions
NYX 0:85b3fd62ea1a 149 * @{
NYX 0:85b3fd62ea1a 150 */
NYX 0:85b3fd62ea1a 151 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
NYX 0:85b3fd62ea1a 152 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 153 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 154
NYX 0:85b3fd62ea1a 155 /**
NYX 0:85b3fd62ea1a 156 * @}
NYX 0:85b3fd62ea1a 157 */
NYX 0:85b3fd62ea1a 158
NYX 0:85b3fd62ea1a 159 /* Exported functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 160 /** @addtogroup DMA_Exported_Functions
NYX 0:85b3fd62ea1a 161 * @{
NYX 0:85b3fd62ea1a 162 */
NYX 0:85b3fd62ea1a 163
NYX 0:85b3fd62ea1a 164 /** @addtogroup DMA_Exported_Functions_Group1
NYX 0:85b3fd62ea1a 165 *
NYX 0:85b3fd62ea1a 166 @verbatim
NYX 0:85b3fd62ea1a 167 ===============================================================================
NYX 0:85b3fd62ea1a 168 ##### Initialization and de-initialization functions #####
NYX 0:85b3fd62ea1a 169 ===============================================================================
NYX 0:85b3fd62ea1a 170 [..]
NYX 0:85b3fd62ea1a 171 This section provides functions allowing to initialize the DMA Stream source
NYX 0:85b3fd62ea1a 172 and destination addresses, incrementation and data sizes, transfer direction,
NYX 0:85b3fd62ea1a 173 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
NYX 0:85b3fd62ea1a 174 [..]
NYX 0:85b3fd62ea1a 175 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
NYX 0:85b3fd62ea1a 176 reference manual.
NYX 0:85b3fd62ea1a 177
NYX 0:85b3fd62ea1a 178 @endverbatim
NYX 0:85b3fd62ea1a 179 * @{
NYX 0:85b3fd62ea1a 180 */
NYX 0:85b3fd62ea1a 181
NYX 0:85b3fd62ea1a 182 /**
NYX 0:85b3fd62ea1a 183 * @brief Initialize the DMA according to the specified
NYX 0:85b3fd62ea1a 184 * parameters in the DMA_InitTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 185 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 186 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 187 * @retval HAL status
NYX 0:85b3fd62ea1a 188 */
NYX 0:85b3fd62ea1a 189 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 190 {
NYX 0:85b3fd62ea1a 191 uint32_t tmp = 0U;
NYX 0:85b3fd62ea1a 192 uint32_t tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 193 DMA_Base_Registers *regs;
NYX 0:85b3fd62ea1a 194
NYX 0:85b3fd62ea1a 195 /* Check the DMA peripheral state */
NYX 0:85b3fd62ea1a 196 if(hdma == NULL)
NYX 0:85b3fd62ea1a 197 {
NYX 0:85b3fd62ea1a 198 return HAL_ERROR;
NYX 0:85b3fd62ea1a 199 }
NYX 0:85b3fd62ea1a 200
NYX 0:85b3fd62ea1a 201 /* Check the parameters */
NYX 0:85b3fd62ea1a 202 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
NYX 0:85b3fd62ea1a 203 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
NYX 0:85b3fd62ea1a 204 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
NYX 0:85b3fd62ea1a 205 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
NYX 0:85b3fd62ea1a 206 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
NYX 0:85b3fd62ea1a 207 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
NYX 0:85b3fd62ea1a 208 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
NYX 0:85b3fd62ea1a 209 assert_param(IS_DMA_MODE(hdma->Init.Mode));
NYX 0:85b3fd62ea1a 210 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
NYX 0:85b3fd62ea1a 211 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
NYX 0:85b3fd62ea1a 212 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
NYX 0:85b3fd62ea1a 213 when FIFO mode is enabled */
NYX 0:85b3fd62ea1a 214 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
NYX 0:85b3fd62ea1a 215 {
NYX 0:85b3fd62ea1a 216 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
NYX 0:85b3fd62ea1a 217 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
NYX 0:85b3fd62ea1a 218 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
NYX 0:85b3fd62ea1a 219 }
NYX 0:85b3fd62ea1a 220
NYX 0:85b3fd62ea1a 221 /* Allocate lock resource */
NYX 0:85b3fd62ea1a 222 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 223
NYX 0:85b3fd62ea1a 224 /* Change DMA peripheral state */
NYX 0:85b3fd62ea1a 225 hdma->State = HAL_DMA_STATE_BUSY;
NYX 0:85b3fd62ea1a 226
NYX 0:85b3fd62ea1a 227 /* Disable the peripheral */
NYX 0:85b3fd62ea1a 228 __HAL_DMA_DISABLE(hdma);
NYX 0:85b3fd62ea1a 229
NYX 0:85b3fd62ea1a 230 /* Check if the DMA Stream is effectively disabled */
NYX 0:85b3fd62ea1a 231 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
NYX 0:85b3fd62ea1a 232 {
NYX 0:85b3fd62ea1a 233 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 234 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
NYX 0:85b3fd62ea1a 235 {
NYX 0:85b3fd62ea1a 236 /* Update error code */
NYX 0:85b3fd62ea1a 237 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
NYX 0:85b3fd62ea1a 238
NYX 0:85b3fd62ea1a 239 /* Change the DMA state */
NYX 0:85b3fd62ea1a 240 hdma->State = HAL_DMA_STATE_TIMEOUT;
NYX 0:85b3fd62ea1a 241
NYX 0:85b3fd62ea1a 242 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 243 }
NYX 0:85b3fd62ea1a 244 }
NYX 0:85b3fd62ea1a 245
NYX 0:85b3fd62ea1a 246 /* Get the CR register value */
NYX 0:85b3fd62ea1a 247 tmp = hdma->Instance->CR;
NYX 0:85b3fd62ea1a 248
NYX 0:85b3fd62ea1a 249 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
NYX 0:85b3fd62ea1a 250 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
NYX 0:85b3fd62ea1a 251 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
NYX 0:85b3fd62ea1a 252 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
NYX 0:85b3fd62ea1a 253 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
NYX 0:85b3fd62ea1a 254
NYX 0:85b3fd62ea1a 255 /* Prepare the DMA Stream configuration */
NYX 0:85b3fd62ea1a 256 tmp |= hdma->Init.Channel | hdma->Init.Direction |
NYX 0:85b3fd62ea1a 257 hdma->Init.PeriphInc | hdma->Init.MemInc |
NYX 0:85b3fd62ea1a 258 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
NYX 0:85b3fd62ea1a 259 hdma->Init.Mode | hdma->Init.Priority;
NYX 0:85b3fd62ea1a 260
NYX 0:85b3fd62ea1a 261 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
NYX 0:85b3fd62ea1a 262 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
NYX 0:85b3fd62ea1a 263 {
NYX 0:85b3fd62ea1a 264 /* Get memory burst and peripheral burst */
NYX 0:85b3fd62ea1a 265 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
NYX 0:85b3fd62ea1a 266 }
NYX 0:85b3fd62ea1a 267
NYX 0:85b3fd62ea1a 268 /* Write to DMA Stream CR register */
NYX 0:85b3fd62ea1a 269 hdma->Instance->CR = tmp;
NYX 0:85b3fd62ea1a 270
NYX 0:85b3fd62ea1a 271 /* Get the FCR register value */
NYX 0:85b3fd62ea1a 272 tmp = hdma->Instance->FCR;
NYX 0:85b3fd62ea1a 273
NYX 0:85b3fd62ea1a 274 /* Clear Direct mode and FIFO threshold bits */
NYX 0:85b3fd62ea1a 275 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
NYX 0:85b3fd62ea1a 276
NYX 0:85b3fd62ea1a 277 /* Prepare the DMA Stream FIFO configuration */
NYX 0:85b3fd62ea1a 278 tmp |= hdma->Init.FIFOMode;
NYX 0:85b3fd62ea1a 279
NYX 0:85b3fd62ea1a 280 /* The FIFO threshold is not used when the FIFO mode is disabled */
NYX 0:85b3fd62ea1a 281 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
NYX 0:85b3fd62ea1a 282 {
NYX 0:85b3fd62ea1a 283 /* Get the FIFO threshold */
NYX 0:85b3fd62ea1a 284 tmp |= hdma->Init.FIFOThreshold;
NYX 0:85b3fd62ea1a 285
NYX 0:85b3fd62ea1a 286 /* Check compatibility between FIFO threshold level and size of the memory burst */
NYX 0:85b3fd62ea1a 287 /* for INCR4, INCR8, INCR16 bursts */
NYX 0:85b3fd62ea1a 288 if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
NYX 0:85b3fd62ea1a 289 {
NYX 0:85b3fd62ea1a 290 if (DMA_CheckFifoParam(hdma) != HAL_OK)
NYX 0:85b3fd62ea1a 291 {
NYX 0:85b3fd62ea1a 292 /* Update error code */
NYX 0:85b3fd62ea1a 293 hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
NYX 0:85b3fd62ea1a 294
NYX 0:85b3fd62ea1a 295 /* Change the DMA state */
NYX 0:85b3fd62ea1a 296 hdma->State = HAL_DMA_STATE_READY;
NYX 0:85b3fd62ea1a 297
NYX 0:85b3fd62ea1a 298 return HAL_ERROR;
NYX 0:85b3fd62ea1a 299 }
NYX 0:85b3fd62ea1a 300 }
NYX 0:85b3fd62ea1a 301 }
NYX 0:85b3fd62ea1a 302
NYX 0:85b3fd62ea1a 303 /* Write to DMA Stream FCR */
NYX 0:85b3fd62ea1a 304 hdma->Instance->FCR = tmp;
NYX 0:85b3fd62ea1a 305
NYX 0:85b3fd62ea1a 306 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
NYX 0:85b3fd62ea1a 307 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
NYX 0:85b3fd62ea1a 308 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
NYX 0:85b3fd62ea1a 309
NYX 0:85b3fd62ea1a 310 /* Clear all interrupt flags */
NYX 0:85b3fd62ea1a 311 regs->IFCR = 0x3FU << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 312
NYX 0:85b3fd62ea1a 313 /* Initialize the error code */
NYX 0:85b3fd62ea1a 314 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
NYX 0:85b3fd62ea1a 315
NYX 0:85b3fd62ea1a 316 /* Initialize the DMA state */
NYX 0:85b3fd62ea1a 317 hdma->State = HAL_DMA_STATE_READY;
NYX 0:85b3fd62ea1a 318
NYX 0:85b3fd62ea1a 319 return HAL_OK;
NYX 0:85b3fd62ea1a 320 }
NYX 0:85b3fd62ea1a 321
NYX 0:85b3fd62ea1a 322 /**
NYX 0:85b3fd62ea1a 323 * @brief DeInitializes the DMA peripheral
NYX 0:85b3fd62ea1a 324 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 325 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 326 * @retval HAL status
NYX 0:85b3fd62ea1a 327 */
NYX 0:85b3fd62ea1a 328 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 329 {
NYX 0:85b3fd62ea1a 330 DMA_Base_Registers *regs;
NYX 0:85b3fd62ea1a 331
NYX 0:85b3fd62ea1a 332 /* Check the DMA peripheral state */
NYX 0:85b3fd62ea1a 333 if(hdma == NULL)
NYX 0:85b3fd62ea1a 334 {
NYX 0:85b3fd62ea1a 335 return HAL_ERROR;
NYX 0:85b3fd62ea1a 336 }
NYX 0:85b3fd62ea1a 337
NYX 0:85b3fd62ea1a 338 /* Check the DMA peripheral state */
NYX 0:85b3fd62ea1a 339 if(hdma->State == HAL_DMA_STATE_BUSY)
NYX 0:85b3fd62ea1a 340 {
NYX 0:85b3fd62ea1a 341 /* Return error status */
NYX 0:85b3fd62ea1a 342 return HAL_BUSY;
NYX 0:85b3fd62ea1a 343 }
NYX 0:85b3fd62ea1a 344
NYX 0:85b3fd62ea1a 345 /* Check the parameters */
NYX 0:85b3fd62ea1a 346 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
NYX 0:85b3fd62ea1a 347
NYX 0:85b3fd62ea1a 348 /* Disable the selected DMA Streamx */
NYX 0:85b3fd62ea1a 349 __HAL_DMA_DISABLE(hdma);
NYX 0:85b3fd62ea1a 350
NYX 0:85b3fd62ea1a 351 /* Reset DMA Streamx control register */
NYX 0:85b3fd62ea1a 352 hdma->Instance->CR = 0U;
NYX 0:85b3fd62ea1a 353
NYX 0:85b3fd62ea1a 354 /* Reset DMA Streamx number of data to transfer register */
NYX 0:85b3fd62ea1a 355 hdma->Instance->NDTR = 0U;
NYX 0:85b3fd62ea1a 356
NYX 0:85b3fd62ea1a 357 /* Reset DMA Streamx peripheral address register */
NYX 0:85b3fd62ea1a 358 hdma->Instance->PAR = 0U;
NYX 0:85b3fd62ea1a 359
NYX 0:85b3fd62ea1a 360 /* Reset DMA Streamx memory 0 address register */
NYX 0:85b3fd62ea1a 361 hdma->Instance->M0AR = 0U;
NYX 0:85b3fd62ea1a 362
NYX 0:85b3fd62ea1a 363 /* Reset DMA Streamx memory 1 address register */
NYX 0:85b3fd62ea1a 364 hdma->Instance->M1AR = 0U;
NYX 0:85b3fd62ea1a 365
NYX 0:85b3fd62ea1a 366 /* Reset DMA Streamx FIFO control register */
NYX 0:85b3fd62ea1a 367 hdma->Instance->FCR = 0x00000021U;
NYX 0:85b3fd62ea1a 368
NYX 0:85b3fd62ea1a 369 /* Get DMA steam Base Address */
NYX 0:85b3fd62ea1a 370 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
NYX 0:85b3fd62ea1a 371
NYX 0:85b3fd62ea1a 372 /* Clear all interrupt flags at correct offset within the register */
NYX 0:85b3fd62ea1a 373 regs->IFCR = 0x3FU << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 374
NYX 0:85b3fd62ea1a 375 /* Initialize the error code */
NYX 0:85b3fd62ea1a 376 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
NYX 0:85b3fd62ea1a 377
NYX 0:85b3fd62ea1a 378 /* Initialize the DMA state */
NYX 0:85b3fd62ea1a 379 hdma->State = HAL_DMA_STATE_RESET;
NYX 0:85b3fd62ea1a 380
NYX 0:85b3fd62ea1a 381 /* Release Lock */
NYX 0:85b3fd62ea1a 382 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 383
NYX 0:85b3fd62ea1a 384 return HAL_OK;
NYX 0:85b3fd62ea1a 385 }
NYX 0:85b3fd62ea1a 386
NYX 0:85b3fd62ea1a 387 /**
NYX 0:85b3fd62ea1a 388 * @}
NYX 0:85b3fd62ea1a 389 */
NYX 0:85b3fd62ea1a 390
NYX 0:85b3fd62ea1a 391 /** @addtogroup DMA_Exported_Functions_Group2
NYX 0:85b3fd62ea1a 392 *
NYX 0:85b3fd62ea1a 393 @verbatim
NYX 0:85b3fd62ea1a 394 ===============================================================================
NYX 0:85b3fd62ea1a 395 ##### IO operation functions #####
NYX 0:85b3fd62ea1a 396 ===============================================================================
NYX 0:85b3fd62ea1a 397 [..] This section provides functions allowing to:
NYX 0:85b3fd62ea1a 398 (+) Configure the source, destination address and data length and Start DMA transfer
NYX 0:85b3fd62ea1a 399 (+) Configure the source, destination address and data length and
NYX 0:85b3fd62ea1a 400 Start DMA transfer with interrupt
NYX 0:85b3fd62ea1a 401 (+) Abort DMA transfer
NYX 0:85b3fd62ea1a 402 (+) Poll for transfer complete
NYX 0:85b3fd62ea1a 403 (+) Handle DMA interrupt request
NYX 0:85b3fd62ea1a 404
NYX 0:85b3fd62ea1a 405 @endverbatim
NYX 0:85b3fd62ea1a 406 * @{
NYX 0:85b3fd62ea1a 407 */
NYX 0:85b3fd62ea1a 408
NYX 0:85b3fd62ea1a 409 /**
NYX 0:85b3fd62ea1a 410 * @brief Starts the DMA Transfer.
NYX 0:85b3fd62ea1a 411 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 412 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 413 * @param SrcAddress: The source memory Buffer address
NYX 0:85b3fd62ea1a 414 * @param DstAddress: The destination memory Buffer address
NYX 0:85b3fd62ea1a 415 * @param DataLength: The length of data to be transferred from source to destination
NYX 0:85b3fd62ea1a 416 * @retval HAL status
NYX 0:85b3fd62ea1a 417 */
NYX 0:85b3fd62ea1a 418 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
NYX 0:85b3fd62ea1a 419 {
NYX 0:85b3fd62ea1a 420 HAL_StatusTypeDef status = HAL_OK;
NYX 0:85b3fd62ea1a 421
NYX 0:85b3fd62ea1a 422 /* Check the parameters */
NYX 0:85b3fd62ea1a 423 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
NYX 0:85b3fd62ea1a 424
NYX 0:85b3fd62ea1a 425 /* Process locked */
NYX 0:85b3fd62ea1a 426 __HAL_LOCK(hdma);
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428 if(HAL_DMA_STATE_READY == hdma->State)
NYX 0:85b3fd62ea1a 429 {
NYX 0:85b3fd62ea1a 430 /* Change DMA peripheral state */
NYX 0:85b3fd62ea1a 431 hdma->State = HAL_DMA_STATE_BUSY;
NYX 0:85b3fd62ea1a 432
NYX 0:85b3fd62ea1a 433 /* Initialize the error code */
NYX 0:85b3fd62ea1a 434 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
NYX 0:85b3fd62ea1a 435
NYX 0:85b3fd62ea1a 436 /* Configure the source, destination address and the data length */
NYX 0:85b3fd62ea1a 437 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
NYX 0:85b3fd62ea1a 438
NYX 0:85b3fd62ea1a 439 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 440 __HAL_DMA_ENABLE(hdma);
NYX 0:85b3fd62ea1a 441 }
NYX 0:85b3fd62ea1a 442 else
NYX 0:85b3fd62ea1a 443 {
NYX 0:85b3fd62ea1a 444 /* Process unlocked */
NYX 0:85b3fd62ea1a 445 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 446
NYX 0:85b3fd62ea1a 447 /* Return error status */
NYX 0:85b3fd62ea1a 448 status = HAL_BUSY;
NYX 0:85b3fd62ea1a 449 }
NYX 0:85b3fd62ea1a 450 return status;
NYX 0:85b3fd62ea1a 451 }
NYX 0:85b3fd62ea1a 452
NYX 0:85b3fd62ea1a 453 /**
NYX 0:85b3fd62ea1a 454 * @brief Start the DMA Transfer with interrupt enabled.
NYX 0:85b3fd62ea1a 455 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 456 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 457 * @param SrcAddress: The source memory Buffer address
NYX 0:85b3fd62ea1a 458 * @param DstAddress: The destination memory Buffer address
NYX 0:85b3fd62ea1a 459 * @param DataLength: The length of data to be transferred from source to destination
NYX 0:85b3fd62ea1a 460 * @retval HAL status
NYX 0:85b3fd62ea1a 461 */
NYX 0:85b3fd62ea1a 462 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
NYX 0:85b3fd62ea1a 463 {
NYX 0:85b3fd62ea1a 464 HAL_StatusTypeDef status = HAL_OK;
NYX 0:85b3fd62ea1a 465
NYX 0:85b3fd62ea1a 466 /* calculate DMA base and stream number */
NYX 0:85b3fd62ea1a 467 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
NYX 0:85b3fd62ea1a 468
NYX 0:85b3fd62ea1a 469 /* Check the parameters */
NYX 0:85b3fd62ea1a 470 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
NYX 0:85b3fd62ea1a 471
NYX 0:85b3fd62ea1a 472 /* Process locked */
NYX 0:85b3fd62ea1a 473 __HAL_LOCK(hdma);
NYX 0:85b3fd62ea1a 474
NYX 0:85b3fd62ea1a 475 if(HAL_DMA_STATE_READY == hdma->State)
NYX 0:85b3fd62ea1a 476 {
NYX 0:85b3fd62ea1a 477 /* Change DMA peripheral state */
NYX 0:85b3fd62ea1a 478 hdma->State = HAL_DMA_STATE_BUSY;
NYX 0:85b3fd62ea1a 479
NYX 0:85b3fd62ea1a 480 /* Initialize the error code */
NYX 0:85b3fd62ea1a 481 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
NYX 0:85b3fd62ea1a 482
NYX 0:85b3fd62ea1a 483 /* Configure the source, destination address and the data length */
NYX 0:85b3fd62ea1a 484 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
NYX 0:85b3fd62ea1a 485
NYX 0:85b3fd62ea1a 486 /* Clear all interrupt flags at correct offset within the register */
NYX 0:85b3fd62ea1a 487 regs->IFCR = 0x3FU << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 488
NYX 0:85b3fd62ea1a 489 /* Enable Common interrupts*/
NYX 0:85b3fd62ea1a 490 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
NYX 0:85b3fd62ea1a 491 hdma->Instance->FCR |= DMA_IT_FE;
NYX 0:85b3fd62ea1a 492
NYX 0:85b3fd62ea1a 493 if(hdma->XferHalfCpltCallback != NULL)
NYX 0:85b3fd62ea1a 494 {
NYX 0:85b3fd62ea1a 495 hdma->Instance->CR |= DMA_IT_HT;
NYX 0:85b3fd62ea1a 496 }
NYX 0:85b3fd62ea1a 497
NYX 0:85b3fd62ea1a 498 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 499 __HAL_DMA_ENABLE(hdma);
NYX 0:85b3fd62ea1a 500 }
NYX 0:85b3fd62ea1a 501 else
NYX 0:85b3fd62ea1a 502 {
NYX 0:85b3fd62ea1a 503 /* Process unlocked */
NYX 0:85b3fd62ea1a 504 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 505
NYX 0:85b3fd62ea1a 506 /* Return error status */
NYX 0:85b3fd62ea1a 507 status = HAL_BUSY;
NYX 0:85b3fd62ea1a 508 }
NYX 0:85b3fd62ea1a 509
NYX 0:85b3fd62ea1a 510 return status;
NYX 0:85b3fd62ea1a 511 }
NYX 0:85b3fd62ea1a 512
NYX 0:85b3fd62ea1a 513 /**
NYX 0:85b3fd62ea1a 514 * @brief Aborts the DMA Transfer.
NYX 0:85b3fd62ea1a 515 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 516 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 517 *
NYX 0:85b3fd62ea1a 518 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
NYX 0:85b3fd62ea1a 519 * effectively disabled is added. If a Stream is disabled
NYX 0:85b3fd62ea1a 520 * while a data transfer is ongoing, the current data will be transferred
NYX 0:85b3fd62ea1a 521 * and the Stream will be effectively disabled only after the transfer of
NYX 0:85b3fd62ea1a 522 * this single data is finished.
NYX 0:85b3fd62ea1a 523 * @retval HAL status
NYX 0:85b3fd62ea1a 524 */
NYX 0:85b3fd62ea1a 525 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 526 {
NYX 0:85b3fd62ea1a 527 /* calculate DMA base and stream number */
NYX 0:85b3fd62ea1a 528 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
NYX 0:85b3fd62ea1a 529
NYX 0:85b3fd62ea1a 530 uint32_t tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 531
NYX 0:85b3fd62ea1a 532 if(hdma->State != HAL_DMA_STATE_BUSY)
NYX 0:85b3fd62ea1a 533 {
NYX 0:85b3fd62ea1a 534 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
NYX 0:85b3fd62ea1a 535
NYX 0:85b3fd62ea1a 536 /* Process Unlocked */
NYX 0:85b3fd62ea1a 537 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 return HAL_ERROR;
NYX 0:85b3fd62ea1a 540 }
NYX 0:85b3fd62ea1a 541 else
NYX 0:85b3fd62ea1a 542 {
NYX 0:85b3fd62ea1a 543 /* Disable all the transfer interrupts */
NYX 0:85b3fd62ea1a 544 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
NYX 0:85b3fd62ea1a 545 hdma->Instance->FCR &= ~(DMA_IT_FE);
NYX 0:85b3fd62ea1a 546
NYX 0:85b3fd62ea1a 547 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
NYX 0:85b3fd62ea1a 548 {
NYX 0:85b3fd62ea1a 549 hdma->Instance->CR &= ~(DMA_IT_HT);
NYX 0:85b3fd62ea1a 550 }
NYX 0:85b3fd62ea1a 551
NYX 0:85b3fd62ea1a 552 /* Disable the stream */
NYX 0:85b3fd62ea1a 553 __HAL_DMA_DISABLE(hdma);
NYX 0:85b3fd62ea1a 554
NYX 0:85b3fd62ea1a 555 /* Check if the DMA Stream is effectively disabled */
NYX 0:85b3fd62ea1a 556 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
NYX 0:85b3fd62ea1a 557 {
NYX 0:85b3fd62ea1a 558 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 559 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
NYX 0:85b3fd62ea1a 560 {
NYX 0:85b3fd62ea1a 561 /* Update error code */
NYX 0:85b3fd62ea1a 562 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
NYX 0:85b3fd62ea1a 563
NYX 0:85b3fd62ea1a 564 /* Process Unlocked */
NYX 0:85b3fd62ea1a 565 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 566
NYX 0:85b3fd62ea1a 567 /* Change the DMA state */
NYX 0:85b3fd62ea1a 568 hdma->State = HAL_DMA_STATE_TIMEOUT;
NYX 0:85b3fd62ea1a 569
NYX 0:85b3fd62ea1a 570 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 571 }
NYX 0:85b3fd62ea1a 572 }
NYX 0:85b3fd62ea1a 573
NYX 0:85b3fd62ea1a 574 /* Clear all interrupt flags at correct offset within the register */
NYX 0:85b3fd62ea1a 575 regs->IFCR = 0x3FU << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 576
NYX 0:85b3fd62ea1a 577 /* Process Unlocked */
NYX 0:85b3fd62ea1a 578 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 579
NYX 0:85b3fd62ea1a 580 /* Change the DMA state*/
NYX 0:85b3fd62ea1a 581 hdma->State = HAL_DMA_STATE_READY;
NYX 0:85b3fd62ea1a 582 }
NYX 0:85b3fd62ea1a 583 return HAL_OK;
NYX 0:85b3fd62ea1a 584 }
NYX 0:85b3fd62ea1a 585
NYX 0:85b3fd62ea1a 586 /**
NYX 0:85b3fd62ea1a 587 * @brief Aborts the DMA Transfer in Interrupt mode.
NYX 0:85b3fd62ea1a 588 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 589 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 590 * @retval HAL status
NYX 0:85b3fd62ea1a 591 */
NYX 0:85b3fd62ea1a 592 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 593 {
NYX 0:85b3fd62ea1a 594 if(hdma->State != HAL_DMA_STATE_BUSY)
NYX 0:85b3fd62ea1a 595 {
NYX 0:85b3fd62ea1a 596 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
NYX 0:85b3fd62ea1a 597 return HAL_ERROR;
NYX 0:85b3fd62ea1a 598 }
NYX 0:85b3fd62ea1a 599 else
NYX 0:85b3fd62ea1a 600 {
NYX 0:85b3fd62ea1a 601 /* Set Abort State */
NYX 0:85b3fd62ea1a 602 hdma->State = HAL_DMA_STATE_ABORT;
NYX 0:85b3fd62ea1a 603
NYX 0:85b3fd62ea1a 604 /* Disable the stream */
NYX 0:85b3fd62ea1a 605 __HAL_DMA_DISABLE(hdma);
NYX 0:85b3fd62ea1a 606 }
NYX 0:85b3fd62ea1a 607
NYX 0:85b3fd62ea1a 608 return HAL_OK;
NYX 0:85b3fd62ea1a 609 }
NYX 0:85b3fd62ea1a 610
NYX 0:85b3fd62ea1a 611 /**
NYX 0:85b3fd62ea1a 612 * @brief Polling for transfer complete.
NYX 0:85b3fd62ea1a 613 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 614 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 615 * @param CompleteLevel: Specifies the DMA level complete.
NYX 0:85b3fd62ea1a 616 * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
NYX 0:85b3fd62ea1a 617 * This model could be used for debug purpose.
NYX 0:85b3fd62ea1a 618 * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
NYX 0:85b3fd62ea1a 619 * @param Timeout: Timeout duration.
NYX 0:85b3fd62ea1a 620 * @retval HAL status
NYX 0:85b3fd62ea1a 621 */
NYX 0:85b3fd62ea1a 622 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
NYX 0:85b3fd62ea1a 623 {
NYX 0:85b3fd62ea1a 624 HAL_StatusTypeDef status = HAL_OK;
NYX 0:85b3fd62ea1a 625 uint32_t mask_cpltlevel;
NYX 0:85b3fd62ea1a 626 uint32_t tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 627 uint32_t tmpisr;
NYX 0:85b3fd62ea1a 628
NYX 0:85b3fd62ea1a 629 /* calculate DMA base and stream number */
NYX 0:85b3fd62ea1a 630 DMA_Base_Registers *regs;
NYX 0:85b3fd62ea1a 631
NYX 0:85b3fd62ea1a 632 if(HAL_DMA_STATE_BUSY != hdma->State)
NYX 0:85b3fd62ea1a 633 {
NYX 0:85b3fd62ea1a 634 /* No transfer ongoing */
NYX 0:85b3fd62ea1a 635 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
NYX 0:85b3fd62ea1a 636 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 637 return HAL_ERROR;
NYX 0:85b3fd62ea1a 638 }
NYX 0:85b3fd62ea1a 639
NYX 0:85b3fd62ea1a 640 /* Polling mode not supported in circular mode and double buffering mode */
NYX 0:85b3fd62ea1a 641 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
NYX 0:85b3fd62ea1a 642 {
NYX 0:85b3fd62ea1a 643 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
NYX 0:85b3fd62ea1a 644 return HAL_ERROR;
NYX 0:85b3fd62ea1a 645 }
NYX 0:85b3fd62ea1a 646
NYX 0:85b3fd62ea1a 647 /* Get the level transfer complete flag */
NYX 0:85b3fd62ea1a 648 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
NYX 0:85b3fd62ea1a 649 {
NYX 0:85b3fd62ea1a 650 /* Transfer Complete flag */
NYX 0:85b3fd62ea1a 651 mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 652 }
NYX 0:85b3fd62ea1a 653 else
NYX 0:85b3fd62ea1a 654 {
NYX 0:85b3fd62ea1a 655 /* Half Transfer Complete flag */
NYX 0:85b3fd62ea1a 656 mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 657 }
NYX 0:85b3fd62ea1a 658
NYX 0:85b3fd62ea1a 659 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
NYX 0:85b3fd62ea1a 660 tmpisr = regs->ISR;
NYX 0:85b3fd62ea1a 661
NYX 0:85b3fd62ea1a 662 while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
NYX 0:85b3fd62ea1a 663 {
NYX 0:85b3fd62ea1a 664 /* Check for the Timeout (Not applicable in circular mode)*/
NYX 0:85b3fd62ea1a 665 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 666 {
NYX 0:85b3fd62ea1a 667 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
NYX 0:85b3fd62ea1a 668 {
NYX 0:85b3fd62ea1a 669 /* Update error code */
NYX 0:85b3fd62ea1a 670 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
NYX 0:85b3fd62ea1a 671
NYX 0:85b3fd62ea1a 672 /* Process Unlocked */
NYX 0:85b3fd62ea1a 673 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 674
NYX 0:85b3fd62ea1a 675 /* Change the DMA state */
NYX 0:85b3fd62ea1a 676 hdma->State = HAL_DMA_STATE_READY;
NYX 0:85b3fd62ea1a 677
NYX 0:85b3fd62ea1a 678 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 679 }
NYX 0:85b3fd62ea1a 680 }
NYX 0:85b3fd62ea1a 681
NYX 0:85b3fd62ea1a 682 /* Get the ISR register value */
NYX 0:85b3fd62ea1a 683 tmpisr = regs->ISR;
NYX 0:85b3fd62ea1a 684
NYX 0:85b3fd62ea1a 685 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
NYX 0:85b3fd62ea1a 686 {
NYX 0:85b3fd62ea1a 687 /* Update error code */
NYX 0:85b3fd62ea1a 688 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
NYX 0:85b3fd62ea1a 689
NYX 0:85b3fd62ea1a 690 /* Clear the transfer error flag */
NYX 0:85b3fd62ea1a 691 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 692 }
NYX 0:85b3fd62ea1a 693
NYX 0:85b3fd62ea1a 694 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
NYX 0:85b3fd62ea1a 695 {
NYX 0:85b3fd62ea1a 696 /* Update error code */
NYX 0:85b3fd62ea1a 697 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
NYX 0:85b3fd62ea1a 698
NYX 0:85b3fd62ea1a 699 /* Clear the FIFO error flag */
NYX 0:85b3fd62ea1a 700 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 701 }
NYX 0:85b3fd62ea1a 702
NYX 0:85b3fd62ea1a 703 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
NYX 0:85b3fd62ea1a 704 {
NYX 0:85b3fd62ea1a 705 /* Update error code */
NYX 0:85b3fd62ea1a 706 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
NYX 0:85b3fd62ea1a 707
NYX 0:85b3fd62ea1a 708 /* Clear the Direct Mode error flag */
NYX 0:85b3fd62ea1a 709 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 710 }
NYX 0:85b3fd62ea1a 711 tmpisr = regs->ISR;
NYX 0:85b3fd62ea1a 712 }
NYX 0:85b3fd62ea1a 713
NYX 0:85b3fd62ea1a 714 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
NYX 0:85b3fd62ea1a 715 {
NYX 0:85b3fd62ea1a 716 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
NYX 0:85b3fd62ea1a 717 {
NYX 0:85b3fd62ea1a 718 HAL_DMA_Abort(hdma);
NYX 0:85b3fd62ea1a 719
NYX 0:85b3fd62ea1a 720 /* Clear the half transfer and transfer complete flags */
NYX 0:85b3fd62ea1a 721 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 722
NYX 0:85b3fd62ea1a 723 /* Process Unlocked */
NYX 0:85b3fd62ea1a 724 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 725
NYX 0:85b3fd62ea1a 726 /* Change the DMA state */
NYX 0:85b3fd62ea1a 727 hdma->State= HAL_DMA_STATE_READY;
NYX 0:85b3fd62ea1a 728
NYX 0:85b3fd62ea1a 729 return HAL_ERROR;
NYX 0:85b3fd62ea1a 730 }
NYX 0:85b3fd62ea1a 731 }
NYX 0:85b3fd62ea1a 732
NYX 0:85b3fd62ea1a 733 /* Get the level transfer complete flag */
NYX 0:85b3fd62ea1a 734 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
NYX 0:85b3fd62ea1a 735 {
NYX 0:85b3fd62ea1a 736 /* Clear the half transfer and transfer complete flags */
NYX 0:85b3fd62ea1a 737 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 738
NYX 0:85b3fd62ea1a 739 /* Process Unlocked */
NYX 0:85b3fd62ea1a 740 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 741
NYX 0:85b3fd62ea1a 742 hdma->State = HAL_DMA_STATE_READY;
NYX 0:85b3fd62ea1a 743 }
NYX 0:85b3fd62ea1a 744 else
NYX 0:85b3fd62ea1a 745 {
NYX 0:85b3fd62ea1a 746 /* Clear the half transfer and transfer complete flags */
NYX 0:85b3fd62ea1a 747 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 748 }
NYX 0:85b3fd62ea1a 749
NYX 0:85b3fd62ea1a 750 return status;
NYX 0:85b3fd62ea1a 751 }
NYX 0:85b3fd62ea1a 752
NYX 0:85b3fd62ea1a 753 /**
NYX 0:85b3fd62ea1a 754 * @brief Handles DMA interrupt request.
NYX 0:85b3fd62ea1a 755 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 756 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 757 * @retval None
NYX 0:85b3fd62ea1a 758 */
NYX 0:85b3fd62ea1a 759 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 760 {
NYX 0:85b3fd62ea1a 761 uint32_t tmpisr;
NYX 0:85b3fd62ea1a 762 __IO uint32_t count = 0U;
NYX 0:85b3fd62ea1a 763 uint32_t timeout = SystemCoreClock / 9600U;
NYX 0:85b3fd62ea1a 764
NYX 0:85b3fd62ea1a 765 /* calculate DMA base and stream number */
NYX 0:85b3fd62ea1a 766 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
NYX 0:85b3fd62ea1a 767
NYX 0:85b3fd62ea1a 768 tmpisr = regs->ISR;
NYX 0:85b3fd62ea1a 769
NYX 0:85b3fd62ea1a 770 /* Transfer Error Interrupt management ***************************************/
NYX 0:85b3fd62ea1a 771 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
NYX 0:85b3fd62ea1a 772 {
NYX 0:85b3fd62ea1a 773 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
NYX 0:85b3fd62ea1a 774 {
NYX 0:85b3fd62ea1a 775 /* Disable the transfer error interrupt */
NYX 0:85b3fd62ea1a 776 hdma->Instance->CR &= ~(DMA_IT_TE);
NYX 0:85b3fd62ea1a 777
NYX 0:85b3fd62ea1a 778 /* Clear the transfer error flag */
NYX 0:85b3fd62ea1a 779 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 780
NYX 0:85b3fd62ea1a 781 /* Update error code */
NYX 0:85b3fd62ea1a 782 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
NYX 0:85b3fd62ea1a 783 }
NYX 0:85b3fd62ea1a 784 }
NYX 0:85b3fd62ea1a 785 /* FIFO Error Interrupt management ******************************************/
NYX 0:85b3fd62ea1a 786 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
NYX 0:85b3fd62ea1a 787 {
NYX 0:85b3fd62ea1a 788 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
NYX 0:85b3fd62ea1a 789 {
NYX 0:85b3fd62ea1a 790 /* Clear the FIFO error flag */
NYX 0:85b3fd62ea1a 791 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 792
NYX 0:85b3fd62ea1a 793 /* Update error code */
NYX 0:85b3fd62ea1a 794 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
NYX 0:85b3fd62ea1a 795 }
NYX 0:85b3fd62ea1a 796 }
NYX 0:85b3fd62ea1a 797 /* Direct Mode Error Interrupt management ***********************************/
NYX 0:85b3fd62ea1a 798 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
NYX 0:85b3fd62ea1a 799 {
NYX 0:85b3fd62ea1a 800 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
NYX 0:85b3fd62ea1a 801 {
NYX 0:85b3fd62ea1a 802 /* Clear the direct mode error flag */
NYX 0:85b3fd62ea1a 803 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 804
NYX 0:85b3fd62ea1a 805 /* Update error code */
NYX 0:85b3fd62ea1a 806 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
NYX 0:85b3fd62ea1a 807 }
NYX 0:85b3fd62ea1a 808 }
NYX 0:85b3fd62ea1a 809 /* Half Transfer Complete Interrupt management ******************************/
NYX 0:85b3fd62ea1a 810 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
NYX 0:85b3fd62ea1a 811 {
NYX 0:85b3fd62ea1a 812 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
NYX 0:85b3fd62ea1a 813 {
NYX 0:85b3fd62ea1a 814 /* Clear the half transfer complete flag */
NYX 0:85b3fd62ea1a 815 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 816
NYX 0:85b3fd62ea1a 817 /* Multi_Buffering mode enabled */
NYX 0:85b3fd62ea1a 818 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
NYX 0:85b3fd62ea1a 819 {
NYX 0:85b3fd62ea1a 820 /* Current memory buffer used is Memory 0 */
NYX 0:85b3fd62ea1a 821 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
NYX 0:85b3fd62ea1a 822 {
NYX 0:85b3fd62ea1a 823 if(hdma->XferHalfCpltCallback != NULL)
NYX 0:85b3fd62ea1a 824 {
NYX 0:85b3fd62ea1a 825 /* Half transfer callback */
NYX 0:85b3fd62ea1a 826 hdma->XferHalfCpltCallback(hdma);
NYX 0:85b3fd62ea1a 827 }
NYX 0:85b3fd62ea1a 828 }
NYX 0:85b3fd62ea1a 829 /* Current memory buffer used is Memory 1 */
NYX 0:85b3fd62ea1a 830 else
NYX 0:85b3fd62ea1a 831 {
NYX 0:85b3fd62ea1a 832 if(hdma->XferM1HalfCpltCallback != NULL)
NYX 0:85b3fd62ea1a 833 {
NYX 0:85b3fd62ea1a 834 /* Half transfer callback */
NYX 0:85b3fd62ea1a 835 hdma->XferM1HalfCpltCallback(hdma);
NYX 0:85b3fd62ea1a 836 }
NYX 0:85b3fd62ea1a 837 }
NYX 0:85b3fd62ea1a 838 }
NYX 0:85b3fd62ea1a 839 else
NYX 0:85b3fd62ea1a 840 {
NYX 0:85b3fd62ea1a 841 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
NYX 0:85b3fd62ea1a 842 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
NYX 0:85b3fd62ea1a 843 {
NYX 0:85b3fd62ea1a 844 /* Disable the half transfer interrupt */
NYX 0:85b3fd62ea1a 845 hdma->Instance->CR &= ~(DMA_IT_HT);
NYX 0:85b3fd62ea1a 846 }
NYX 0:85b3fd62ea1a 847
NYX 0:85b3fd62ea1a 848 if(hdma->XferHalfCpltCallback != NULL)
NYX 0:85b3fd62ea1a 849 {
NYX 0:85b3fd62ea1a 850 /* Half transfer callback */
NYX 0:85b3fd62ea1a 851 hdma->XferHalfCpltCallback(hdma);
NYX 0:85b3fd62ea1a 852 }
NYX 0:85b3fd62ea1a 853 }
NYX 0:85b3fd62ea1a 854 }
NYX 0:85b3fd62ea1a 855 }
NYX 0:85b3fd62ea1a 856 /* Transfer Complete Interrupt management ***********************************/
NYX 0:85b3fd62ea1a 857 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
NYX 0:85b3fd62ea1a 858 {
NYX 0:85b3fd62ea1a 859 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
NYX 0:85b3fd62ea1a 860 {
NYX 0:85b3fd62ea1a 861 /* Clear the transfer complete flag */
NYX 0:85b3fd62ea1a 862 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 863
NYX 0:85b3fd62ea1a 864 if(HAL_DMA_STATE_ABORT == hdma->State)
NYX 0:85b3fd62ea1a 865 {
NYX 0:85b3fd62ea1a 866 /* Disable all the transfer interrupts */
NYX 0:85b3fd62ea1a 867 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
NYX 0:85b3fd62ea1a 868 hdma->Instance->FCR &= ~(DMA_IT_FE);
NYX 0:85b3fd62ea1a 869
NYX 0:85b3fd62ea1a 870 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
NYX 0:85b3fd62ea1a 871 {
NYX 0:85b3fd62ea1a 872 hdma->Instance->CR &= ~(DMA_IT_HT);
NYX 0:85b3fd62ea1a 873 }
NYX 0:85b3fd62ea1a 874
NYX 0:85b3fd62ea1a 875 /* Clear all interrupt flags at correct offset within the register */
NYX 0:85b3fd62ea1a 876 regs->IFCR = 0x3FU << hdma->StreamIndex;
NYX 0:85b3fd62ea1a 877
NYX 0:85b3fd62ea1a 878 /* Process Unlocked */
NYX 0:85b3fd62ea1a 879 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 880
NYX 0:85b3fd62ea1a 881 /* Change the DMA state */
NYX 0:85b3fd62ea1a 882 hdma->State = HAL_DMA_STATE_READY;
NYX 0:85b3fd62ea1a 883
NYX 0:85b3fd62ea1a 884 if(hdma->XferAbortCallback != NULL)
NYX 0:85b3fd62ea1a 885 {
NYX 0:85b3fd62ea1a 886 hdma->XferAbortCallback(hdma);
NYX 0:85b3fd62ea1a 887 }
NYX 0:85b3fd62ea1a 888 return;
NYX 0:85b3fd62ea1a 889 }
NYX 0:85b3fd62ea1a 890
NYX 0:85b3fd62ea1a 891 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
NYX 0:85b3fd62ea1a 892 {
NYX 0:85b3fd62ea1a 893 /* Current memory buffer used is Memory 0 */
NYX 0:85b3fd62ea1a 894 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
NYX 0:85b3fd62ea1a 895 {
NYX 0:85b3fd62ea1a 896 if(hdma->XferM1CpltCallback != NULL)
NYX 0:85b3fd62ea1a 897 {
NYX 0:85b3fd62ea1a 898 /* Transfer complete Callback for memory1 */
NYX 0:85b3fd62ea1a 899 hdma->XferM1CpltCallback(hdma);
NYX 0:85b3fd62ea1a 900 }
NYX 0:85b3fd62ea1a 901 }
NYX 0:85b3fd62ea1a 902 /* Current memory buffer used is Memory 1 */
NYX 0:85b3fd62ea1a 903 else
NYX 0:85b3fd62ea1a 904 {
NYX 0:85b3fd62ea1a 905 if(hdma->XferCpltCallback != NULL)
NYX 0:85b3fd62ea1a 906 {
NYX 0:85b3fd62ea1a 907 /* Transfer complete Callback for memory0 */
NYX 0:85b3fd62ea1a 908 hdma->XferCpltCallback(hdma);
NYX 0:85b3fd62ea1a 909 }
NYX 0:85b3fd62ea1a 910 }
NYX 0:85b3fd62ea1a 911 }
NYX 0:85b3fd62ea1a 912 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
NYX 0:85b3fd62ea1a 913 else
NYX 0:85b3fd62ea1a 914 {
NYX 0:85b3fd62ea1a 915 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
NYX 0:85b3fd62ea1a 916 {
NYX 0:85b3fd62ea1a 917 /* Disable the transfer complete interrupt */
NYX 0:85b3fd62ea1a 918 hdma->Instance->CR &= ~(DMA_IT_TC);
NYX 0:85b3fd62ea1a 919
NYX 0:85b3fd62ea1a 920 /* Process Unlocked */
NYX 0:85b3fd62ea1a 921 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 922
NYX 0:85b3fd62ea1a 923 /* Change the DMA state */
NYX 0:85b3fd62ea1a 924 hdma->State = HAL_DMA_STATE_READY;
NYX 0:85b3fd62ea1a 925 }
NYX 0:85b3fd62ea1a 926
NYX 0:85b3fd62ea1a 927 if(hdma->XferCpltCallback != NULL)
NYX 0:85b3fd62ea1a 928 {
NYX 0:85b3fd62ea1a 929 /* Transfer complete callback */
NYX 0:85b3fd62ea1a 930 hdma->XferCpltCallback(hdma);
NYX 0:85b3fd62ea1a 931 }
NYX 0:85b3fd62ea1a 932 }
NYX 0:85b3fd62ea1a 933 }
NYX 0:85b3fd62ea1a 934 }
NYX 0:85b3fd62ea1a 935
NYX 0:85b3fd62ea1a 936 /* manage error case */
NYX 0:85b3fd62ea1a 937 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
NYX 0:85b3fd62ea1a 938 {
NYX 0:85b3fd62ea1a 939 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
NYX 0:85b3fd62ea1a 940 {
NYX 0:85b3fd62ea1a 941 hdma->State = HAL_DMA_STATE_ABORT;
NYX 0:85b3fd62ea1a 942
NYX 0:85b3fd62ea1a 943 /* Disable the stream */
NYX 0:85b3fd62ea1a 944 __HAL_DMA_DISABLE(hdma);
NYX 0:85b3fd62ea1a 945
NYX 0:85b3fd62ea1a 946 do
NYX 0:85b3fd62ea1a 947 {
NYX 0:85b3fd62ea1a 948 if (++count > timeout)
NYX 0:85b3fd62ea1a 949 {
NYX 0:85b3fd62ea1a 950 break;
NYX 0:85b3fd62ea1a 951 }
NYX 0:85b3fd62ea1a 952 }
NYX 0:85b3fd62ea1a 953 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
NYX 0:85b3fd62ea1a 954
NYX 0:85b3fd62ea1a 955 /* Process Unlocked */
NYX 0:85b3fd62ea1a 956 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 957
NYX 0:85b3fd62ea1a 958 /* Change the DMA state */
NYX 0:85b3fd62ea1a 959 hdma->State = HAL_DMA_STATE_READY;
NYX 0:85b3fd62ea1a 960 }
NYX 0:85b3fd62ea1a 961
NYX 0:85b3fd62ea1a 962 if(hdma->XferErrorCallback != NULL)
NYX 0:85b3fd62ea1a 963 {
NYX 0:85b3fd62ea1a 964 /* Transfer error callback */
NYX 0:85b3fd62ea1a 965 hdma->XferErrorCallback(hdma);
NYX 0:85b3fd62ea1a 966 }
NYX 0:85b3fd62ea1a 967 }
NYX 0:85b3fd62ea1a 968 }
NYX 0:85b3fd62ea1a 969
NYX 0:85b3fd62ea1a 970 /**
NYX 0:85b3fd62ea1a 971 * @brief Register callbacks
NYX 0:85b3fd62ea1a 972 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 973 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 974 * @param CallbackID: User Callback identifer
NYX 0:85b3fd62ea1a 975 * a DMA_HandleTypeDef structure as parameter.
NYX 0:85b3fd62ea1a 976 * @param pCallback: pointer to private callbacsk function which has pointer to
NYX 0:85b3fd62ea1a 977 * a DMA_HandleTypeDef structure as parameter.
NYX 0:85b3fd62ea1a 978 * @retval HAL status
NYX 0:85b3fd62ea1a 979 */
NYX 0:85b3fd62ea1a 980 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
NYX 0:85b3fd62ea1a 981 {
NYX 0:85b3fd62ea1a 982
NYX 0:85b3fd62ea1a 983 HAL_StatusTypeDef status = HAL_OK;
NYX 0:85b3fd62ea1a 984
NYX 0:85b3fd62ea1a 985 /* Process locked */
NYX 0:85b3fd62ea1a 986 __HAL_LOCK(hdma);
NYX 0:85b3fd62ea1a 987
NYX 0:85b3fd62ea1a 988 if(HAL_DMA_STATE_READY == hdma->State)
NYX 0:85b3fd62ea1a 989 {
NYX 0:85b3fd62ea1a 990 switch (CallbackID)
NYX 0:85b3fd62ea1a 991 {
NYX 0:85b3fd62ea1a 992 case HAL_DMA_XFER_CPLT_CB_ID:
NYX 0:85b3fd62ea1a 993 hdma->XferCpltCallback = pCallback;
NYX 0:85b3fd62ea1a 994 break;
NYX 0:85b3fd62ea1a 995
NYX 0:85b3fd62ea1a 996 case HAL_DMA_XFER_HALFCPLT_CB_ID:
NYX 0:85b3fd62ea1a 997 hdma->XferHalfCpltCallback = pCallback;
NYX 0:85b3fd62ea1a 998 break;
NYX 0:85b3fd62ea1a 999
NYX 0:85b3fd62ea1a 1000 case HAL_DMA_XFER_M1CPLT_CB_ID:
NYX 0:85b3fd62ea1a 1001 hdma->XferM1CpltCallback = pCallback;
NYX 0:85b3fd62ea1a 1002 break;
NYX 0:85b3fd62ea1a 1003
NYX 0:85b3fd62ea1a 1004 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
NYX 0:85b3fd62ea1a 1005 hdma->XferM1HalfCpltCallback = pCallback;
NYX 0:85b3fd62ea1a 1006 break;
NYX 0:85b3fd62ea1a 1007
NYX 0:85b3fd62ea1a 1008 case HAL_DMA_XFER_ERROR_CB_ID:
NYX 0:85b3fd62ea1a 1009 hdma->XferErrorCallback = pCallback;
NYX 0:85b3fd62ea1a 1010 break;
NYX 0:85b3fd62ea1a 1011
NYX 0:85b3fd62ea1a 1012 case HAL_DMA_XFER_ABORT_CB_ID:
NYX 0:85b3fd62ea1a 1013 hdma->XferAbortCallback = pCallback;
NYX 0:85b3fd62ea1a 1014 break;
NYX 0:85b3fd62ea1a 1015
NYX 0:85b3fd62ea1a 1016 default:
NYX 0:85b3fd62ea1a 1017 break;
NYX 0:85b3fd62ea1a 1018 }
NYX 0:85b3fd62ea1a 1019 }
NYX 0:85b3fd62ea1a 1020 else
NYX 0:85b3fd62ea1a 1021 {
NYX 0:85b3fd62ea1a 1022 /* Return error status */
NYX 0:85b3fd62ea1a 1023 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1024 }
NYX 0:85b3fd62ea1a 1025
NYX 0:85b3fd62ea1a 1026 /* Release Lock */
NYX 0:85b3fd62ea1a 1027 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 1028
NYX 0:85b3fd62ea1a 1029 return status;
NYX 0:85b3fd62ea1a 1030 }
NYX 0:85b3fd62ea1a 1031
NYX 0:85b3fd62ea1a 1032 /**
NYX 0:85b3fd62ea1a 1033 * @brief UnRegister callbacks
NYX 0:85b3fd62ea1a 1034 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1035 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 1036 * @param CallbackID: User Callback identifer
NYX 0:85b3fd62ea1a 1037 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
NYX 0:85b3fd62ea1a 1038 * @retval HAL status
NYX 0:85b3fd62ea1a 1039 */
NYX 0:85b3fd62ea1a 1040 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
NYX 0:85b3fd62ea1a 1041 {
NYX 0:85b3fd62ea1a 1042 HAL_StatusTypeDef status = HAL_OK;
NYX 0:85b3fd62ea1a 1043
NYX 0:85b3fd62ea1a 1044 /* Process locked */
NYX 0:85b3fd62ea1a 1045 __HAL_LOCK(hdma);
NYX 0:85b3fd62ea1a 1046
NYX 0:85b3fd62ea1a 1047 if(HAL_DMA_STATE_READY == hdma->State)
NYX 0:85b3fd62ea1a 1048 {
NYX 0:85b3fd62ea1a 1049 switch (CallbackID)
NYX 0:85b3fd62ea1a 1050 {
NYX 0:85b3fd62ea1a 1051 case HAL_DMA_XFER_CPLT_CB_ID:
NYX 0:85b3fd62ea1a 1052 hdma->XferCpltCallback = NULL;
NYX 0:85b3fd62ea1a 1053 break;
NYX 0:85b3fd62ea1a 1054
NYX 0:85b3fd62ea1a 1055 case HAL_DMA_XFER_HALFCPLT_CB_ID:
NYX 0:85b3fd62ea1a 1056 hdma->XferHalfCpltCallback = NULL;
NYX 0:85b3fd62ea1a 1057 break;
NYX 0:85b3fd62ea1a 1058
NYX 0:85b3fd62ea1a 1059 case HAL_DMA_XFER_M1CPLT_CB_ID:
NYX 0:85b3fd62ea1a 1060 hdma->XferM1CpltCallback = NULL;
NYX 0:85b3fd62ea1a 1061 break;
NYX 0:85b3fd62ea1a 1062
NYX 0:85b3fd62ea1a 1063 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
NYX 0:85b3fd62ea1a 1064 hdma->XferM1HalfCpltCallback = NULL;
NYX 0:85b3fd62ea1a 1065 break;
NYX 0:85b3fd62ea1a 1066
NYX 0:85b3fd62ea1a 1067 case HAL_DMA_XFER_ERROR_CB_ID:
NYX 0:85b3fd62ea1a 1068 hdma->XferErrorCallback = NULL;
NYX 0:85b3fd62ea1a 1069 break;
NYX 0:85b3fd62ea1a 1070
NYX 0:85b3fd62ea1a 1071 case HAL_DMA_XFER_ABORT_CB_ID:
NYX 0:85b3fd62ea1a 1072 hdma->XferAbortCallback = NULL;
NYX 0:85b3fd62ea1a 1073 break;
NYX 0:85b3fd62ea1a 1074
NYX 0:85b3fd62ea1a 1075 case HAL_DMA_XFER_ALL_CB_ID:
NYX 0:85b3fd62ea1a 1076 hdma->XferCpltCallback = NULL;
NYX 0:85b3fd62ea1a 1077 hdma->XferHalfCpltCallback = NULL;
NYX 0:85b3fd62ea1a 1078 hdma->XferM1CpltCallback = NULL;
NYX 0:85b3fd62ea1a 1079 hdma->XferM1HalfCpltCallback = NULL;
NYX 0:85b3fd62ea1a 1080 hdma->XferErrorCallback = NULL;
NYX 0:85b3fd62ea1a 1081 hdma->XferAbortCallback = NULL;
NYX 0:85b3fd62ea1a 1082 break;
NYX 0:85b3fd62ea1a 1083
NYX 0:85b3fd62ea1a 1084 default:
NYX 0:85b3fd62ea1a 1085 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1086 break;
NYX 0:85b3fd62ea1a 1087 }
NYX 0:85b3fd62ea1a 1088 }
NYX 0:85b3fd62ea1a 1089 else
NYX 0:85b3fd62ea1a 1090 {
NYX 0:85b3fd62ea1a 1091 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1092 }
NYX 0:85b3fd62ea1a 1093
NYX 0:85b3fd62ea1a 1094 /* Release Lock */
NYX 0:85b3fd62ea1a 1095 __HAL_UNLOCK(hdma);
NYX 0:85b3fd62ea1a 1096
NYX 0:85b3fd62ea1a 1097 return status;
NYX 0:85b3fd62ea1a 1098 }
NYX 0:85b3fd62ea1a 1099
NYX 0:85b3fd62ea1a 1100 /**
NYX 0:85b3fd62ea1a 1101 * @}
NYX 0:85b3fd62ea1a 1102 */
NYX 0:85b3fd62ea1a 1103
NYX 0:85b3fd62ea1a 1104 /** @addtogroup DMA_Exported_Functions_Group3
NYX 0:85b3fd62ea1a 1105 *
NYX 0:85b3fd62ea1a 1106 @verbatim
NYX 0:85b3fd62ea1a 1107 ===============================================================================
NYX 0:85b3fd62ea1a 1108 ##### State and Errors functions #####
NYX 0:85b3fd62ea1a 1109 ===============================================================================
NYX 0:85b3fd62ea1a 1110 [..]
NYX 0:85b3fd62ea1a 1111 This subsection provides functions allowing to
NYX 0:85b3fd62ea1a 1112 (+) Check the DMA state
NYX 0:85b3fd62ea1a 1113 (+) Get error code
NYX 0:85b3fd62ea1a 1114
NYX 0:85b3fd62ea1a 1115 @endverbatim
NYX 0:85b3fd62ea1a 1116 * @{
NYX 0:85b3fd62ea1a 1117 */
NYX 0:85b3fd62ea1a 1118
NYX 0:85b3fd62ea1a 1119 /**
NYX 0:85b3fd62ea1a 1120 * @brief Returns the DMA state.
NYX 0:85b3fd62ea1a 1121 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1122 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 1123 * @retval HAL state
NYX 0:85b3fd62ea1a 1124 */
NYX 0:85b3fd62ea1a 1125 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 1126 {
NYX 0:85b3fd62ea1a 1127 return hdma->State;
NYX 0:85b3fd62ea1a 1128 }
NYX 0:85b3fd62ea1a 1129
NYX 0:85b3fd62ea1a 1130 /**
NYX 0:85b3fd62ea1a 1131 * @brief Return the DMA error code
NYX 0:85b3fd62ea1a 1132 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1133 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 1134 * @retval DMA Error Code
NYX 0:85b3fd62ea1a 1135 */
NYX 0:85b3fd62ea1a 1136 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 1137 {
NYX 0:85b3fd62ea1a 1138 return hdma->ErrorCode;
NYX 0:85b3fd62ea1a 1139 }
NYX 0:85b3fd62ea1a 1140
NYX 0:85b3fd62ea1a 1141 /**
NYX 0:85b3fd62ea1a 1142 * @}
NYX 0:85b3fd62ea1a 1143 */
NYX 0:85b3fd62ea1a 1144
NYX 0:85b3fd62ea1a 1145 /**
NYX 0:85b3fd62ea1a 1146 * @}
NYX 0:85b3fd62ea1a 1147 */
NYX 0:85b3fd62ea1a 1148
NYX 0:85b3fd62ea1a 1149 /** @addtogroup DMA_Private_Functions
NYX 0:85b3fd62ea1a 1150 * @{
NYX 0:85b3fd62ea1a 1151 */
NYX 0:85b3fd62ea1a 1152
NYX 0:85b3fd62ea1a 1153 /**
NYX 0:85b3fd62ea1a 1154 * @brief Sets the DMA Transfer parameter.
NYX 0:85b3fd62ea1a 1155 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1156 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 1157 * @param SrcAddress: The source memory Buffer address
NYX 0:85b3fd62ea1a 1158 * @param DstAddress: The destination memory Buffer address
NYX 0:85b3fd62ea1a 1159 * @param DataLength: The length of data to be transferred from source to destination
NYX 0:85b3fd62ea1a 1160 * @retval HAL status
NYX 0:85b3fd62ea1a 1161 */
NYX 0:85b3fd62ea1a 1162 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
NYX 0:85b3fd62ea1a 1163 {
NYX 0:85b3fd62ea1a 1164 /* Clear DBM bit */
NYX 0:85b3fd62ea1a 1165 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
NYX 0:85b3fd62ea1a 1166
NYX 0:85b3fd62ea1a 1167 /* Configure DMA Stream data length */
NYX 0:85b3fd62ea1a 1168 hdma->Instance->NDTR = DataLength;
NYX 0:85b3fd62ea1a 1169
NYX 0:85b3fd62ea1a 1170 /* Peripheral to Memory */
NYX 0:85b3fd62ea1a 1171 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
NYX 0:85b3fd62ea1a 1172 {
NYX 0:85b3fd62ea1a 1173 /* Configure DMA Stream destination address */
NYX 0:85b3fd62ea1a 1174 hdma->Instance->PAR = DstAddress;
NYX 0:85b3fd62ea1a 1175
NYX 0:85b3fd62ea1a 1176 /* Configure DMA Stream source address */
NYX 0:85b3fd62ea1a 1177 hdma->Instance->M0AR = SrcAddress;
NYX 0:85b3fd62ea1a 1178 }
NYX 0:85b3fd62ea1a 1179 /* Memory to Peripheral */
NYX 0:85b3fd62ea1a 1180 else
NYX 0:85b3fd62ea1a 1181 {
NYX 0:85b3fd62ea1a 1182 /* Configure DMA Stream source address */
NYX 0:85b3fd62ea1a 1183 hdma->Instance->PAR = SrcAddress;
NYX 0:85b3fd62ea1a 1184
NYX 0:85b3fd62ea1a 1185 /* Configure DMA Stream destination address */
NYX 0:85b3fd62ea1a 1186 hdma->Instance->M0AR = DstAddress;
NYX 0:85b3fd62ea1a 1187 }
NYX 0:85b3fd62ea1a 1188 }
NYX 0:85b3fd62ea1a 1189
NYX 0:85b3fd62ea1a 1190 /**
NYX 0:85b3fd62ea1a 1191 * @brief Returns the DMA Stream base address depending on stream number
NYX 0:85b3fd62ea1a 1192 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1193 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 1194 * @retval Stream base address
NYX 0:85b3fd62ea1a 1195 */
NYX 0:85b3fd62ea1a 1196 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 1197 {
NYX 0:85b3fd62ea1a 1198 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
NYX 0:85b3fd62ea1a 1199
NYX 0:85b3fd62ea1a 1200 /* lookup table for necessary bitshift of flags within status registers */
NYX 0:85b3fd62ea1a 1201 static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
NYX 0:85b3fd62ea1a 1202 hdma->StreamIndex = flagBitshiftOffset[stream_number];
NYX 0:85b3fd62ea1a 1203
NYX 0:85b3fd62ea1a 1204 if (stream_number > 3U)
NYX 0:85b3fd62ea1a 1205 {
NYX 0:85b3fd62ea1a 1206 /* return pointer to HISR and HIFCR */
NYX 0:85b3fd62ea1a 1207 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
NYX 0:85b3fd62ea1a 1208 }
NYX 0:85b3fd62ea1a 1209 else
NYX 0:85b3fd62ea1a 1210 {
NYX 0:85b3fd62ea1a 1211 /* return pointer to LISR and LIFCR */
NYX 0:85b3fd62ea1a 1212 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
NYX 0:85b3fd62ea1a 1213 }
NYX 0:85b3fd62ea1a 1214
NYX 0:85b3fd62ea1a 1215 return hdma->StreamBaseAddress;
NYX 0:85b3fd62ea1a 1216 }
NYX 0:85b3fd62ea1a 1217
NYX 0:85b3fd62ea1a 1218 /**
NYX 0:85b3fd62ea1a 1219 * @brief Check compatibility between FIFO threshold level and size of the memory burst
NYX 0:85b3fd62ea1a 1220 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1221 * the configuration information for the specified DMA Stream.
NYX 0:85b3fd62ea1a 1222 * @retval HAL status
NYX 0:85b3fd62ea1a 1223 */
NYX 0:85b3fd62ea1a 1224 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 1225 {
NYX 0:85b3fd62ea1a 1226 HAL_StatusTypeDef status = HAL_OK;
NYX 0:85b3fd62ea1a 1227 uint32_t tmp = hdma->Init.FIFOThreshold;
NYX 0:85b3fd62ea1a 1228
NYX 0:85b3fd62ea1a 1229 /* Memory Data size equal to Byte */
NYX 0:85b3fd62ea1a 1230 if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
NYX 0:85b3fd62ea1a 1231 {
NYX 0:85b3fd62ea1a 1232 switch (tmp)
NYX 0:85b3fd62ea1a 1233 {
NYX 0:85b3fd62ea1a 1234 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
NYX 0:85b3fd62ea1a 1235 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
NYX 0:85b3fd62ea1a 1236 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
NYX 0:85b3fd62ea1a 1237 {
NYX 0:85b3fd62ea1a 1238 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1239 }
NYX 0:85b3fd62ea1a 1240 break;
NYX 0:85b3fd62ea1a 1241 case DMA_FIFO_THRESHOLD_HALFFULL:
NYX 0:85b3fd62ea1a 1242 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
NYX 0:85b3fd62ea1a 1243 {
NYX 0:85b3fd62ea1a 1244 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1245 }
NYX 0:85b3fd62ea1a 1246 break;
NYX 0:85b3fd62ea1a 1247 case DMA_FIFO_THRESHOLD_FULL:
NYX 0:85b3fd62ea1a 1248 break;
NYX 0:85b3fd62ea1a 1249 default:
NYX 0:85b3fd62ea1a 1250 break;
NYX 0:85b3fd62ea1a 1251 }
NYX 0:85b3fd62ea1a 1252 }
NYX 0:85b3fd62ea1a 1253
NYX 0:85b3fd62ea1a 1254 /* Memory Data size equal to Half-Word */
NYX 0:85b3fd62ea1a 1255 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
NYX 0:85b3fd62ea1a 1256 {
NYX 0:85b3fd62ea1a 1257 switch (tmp)
NYX 0:85b3fd62ea1a 1258 {
NYX 0:85b3fd62ea1a 1259 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
NYX 0:85b3fd62ea1a 1260 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
NYX 0:85b3fd62ea1a 1261 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1262 break;
NYX 0:85b3fd62ea1a 1263 case DMA_FIFO_THRESHOLD_HALFFULL:
NYX 0:85b3fd62ea1a 1264 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
NYX 0:85b3fd62ea1a 1265 {
NYX 0:85b3fd62ea1a 1266 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1267 }
NYX 0:85b3fd62ea1a 1268 break;
NYX 0:85b3fd62ea1a 1269 case DMA_FIFO_THRESHOLD_FULL:
NYX 0:85b3fd62ea1a 1270 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
NYX 0:85b3fd62ea1a 1271 {
NYX 0:85b3fd62ea1a 1272 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1273 }
NYX 0:85b3fd62ea1a 1274 break;
NYX 0:85b3fd62ea1a 1275 default:
NYX 0:85b3fd62ea1a 1276 break;
NYX 0:85b3fd62ea1a 1277 }
NYX 0:85b3fd62ea1a 1278 }
NYX 0:85b3fd62ea1a 1279
NYX 0:85b3fd62ea1a 1280 /* Memory Data size equal to Word */
NYX 0:85b3fd62ea1a 1281 else
NYX 0:85b3fd62ea1a 1282 {
NYX 0:85b3fd62ea1a 1283 switch (tmp)
NYX 0:85b3fd62ea1a 1284 {
NYX 0:85b3fd62ea1a 1285 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
NYX 0:85b3fd62ea1a 1286 case DMA_FIFO_THRESHOLD_HALFFULL:
NYX 0:85b3fd62ea1a 1287 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
NYX 0:85b3fd62ea1a 1288 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1289 break;
NYX 0:85b3fd62ea1a 1290 case DMA_FIFO_THRESHOLD_FULL:
NYX 0:85b3fd62ea1a 1291 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
NYX 0:85b3fd62ea1a 1292 {
NYX 0:85b3fd62ea1a 1293 status = HAL_ERROR;
NYX 0:85b3fd62ea1a 1294 }
NYX 0:85b3fd62ea1a 1295 break;
NYX 0:85b3fd62ea1a 1296 default:
NYX 0:85b3fd62ea1a 1297 break;
NYX 0:85b3fd62ea1a 1298 }
NYX 0:85b3fd62ea1a 1299 }
NYX 0:85b3fd62ea1a 1300
NYX 0:85b3fd62ea1a 1301 return status;
NYX 0:85b3fd62ea1a 1302 }
NYX 0:85b3fd62ea1a 1303
NYX 0:85b3fd62ea1a 1304 /**
NYX 0:85b3fd62ea1a 1305 * @}
NYX 0:85b3fd62ea1a 1306 */
NYX 0:85b3fd62ea1a 1307
NYX 0:85b3fd62ea1a 1308 #endif /* HAL_DMA_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 1309 /**
NYX 0:85b3fd62ea1a 1310 * @}
NYX 0:85b3fd62ea1a 1311 */
NYX 0:85b3fd62ea1a 1312
NYX 0:85b3fd62ea1a 1313 /**
NYX 0:85b3fd62ea1a 1314 * @}
NYX 0:85b3fd62ea1a 1315 */
NYX 0:85b3fd62ea1a 1316
NYX 0:85b3fd62ea1a 1317 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/