mbed-dev - inport from local

Users » NYX » Code » mbed-dev

inport from local

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_hal_dfsdm.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of DFSDM HAL module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_HAL_DFSDM_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_HAL_DFSDM_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	47	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	48	#include "stm32f4xx_hal_def.h"
NYX	0:85b3fd62ea1a	49
NYX	0:85b3fd62ea1a	50	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	51	* @{
NYX	0:85b3fd62ea1a	52	*/
NYX	0:85b3fd62ea1a	53
NYX	0:85b3fd62ea1a	54	/** @addtogroup DFSDM
NYX	0:85b3fd62ea1a	55	* @{
NYX	0:85b3fd62ea1a	56	*/
NYX	0:85b3fd62ea1a	57
NYX	0:85b3fd62ea1a	58	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	59	/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
NYX	0:85b3fd62ea1a	60	* @{
NYX	0:85b3fd62ea1a	61	*/
NYX	0:85b3fd62ea1a	62
NYX	0:85b3fd62ea1a	63	/**
NYX	0:85b3fd62ea1a	64	* @brief HAL DFSDM Channel states definition
NYX	0:85b3fd62ea1a	65	*/
NYX	0:85b3fd62ea1a	66	typedef enum
NYX	0:85b3fd62ea1a	67	{
NYX	0:85b3fd62ea1a	68	HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /!< DFSDM channel not initialized /
NYX	0:85b3fd62ea1a	69	HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /!< DFSDM channel initialized and ready for use /
NYX	0:85b3fd62ea1a	70	HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /!< DFSDM channel state error /
NYX	0:85b3fd62ea1a	71	}HAL_DFSDM_Channel_StateTypeDef;
NYX	0:85b3fd62ea1a	72
NYX	0:85b3fd62ea1a	73	/**
NYX	0:85b3fd62ea1a	74	* @brief DFSDM channel output clock structure definition
NYX	0:85b3fd62ea1a	75	*/
NYX	0:85b3fd62ea1a	76	typedef struct
NYX	0:85b3fd62ea1a	77	{
NYX	0:85b3fd62ea1a	78	FunctionalState Activation; /!< Output clock enable/disable /
NYX	0:85b3fd62ea1a	79	uint32_t Selection; /*!< Output clock is system clock or audio clock.
NYX	0:85b3fd62ea1a	80	This parameter can be a value of @ref DFSDM_Channel_OuputClock */
NYX	0:85b3fd62ea1a	81	uint32_t Divider; /*!< Output clock divider.
NYX	0:85b3fd62ea1a	82	This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
NYX	0:85b3fd62ea1a	83	}DFSDM_Channel_OutputClockTypeDef;
NYX	0:85b3fd62ea1a	84
NYX	0:85b3fd62ea1a	85	/**
NYX	0:85b3fd62ea1a	86	* @brief DFSDM channel input structure definition
NYX	0:85b3fd62ea1a	87	*/
NYX	0:85b3fd62ea1a	88	typedef struct
NYX	0:85b3fd62ea1a	89	{
NYX	0:85b3fd62ea1a	90	uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
NYX	0:85b3fd62ea1a	91	This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
NYX	0:85b3fd62ea1a	92	uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
NYX	0:85b3fd62ea1a	93	This parameter can be a value of @ref DFSDM_Channel_DataPacking */
NYX	0:85b3fd62ea1a	94	uint32_t Pins; /*!< Input pins are taken from same or following channel.
NYX	0:85b3fd62ea1a	95	This parameter can be a value of @ref DFSDM_Channel_InputPins */
NYX	0:85b3fd62ea1a	96	}DFSDM_Channel_InputTypeDef;
NYX	0:85b3fd62ea1a	97
NYX	0:85b3fd62ea1a	98	/**
NYX	0:85b3fd62ea1a	99	* @brief DFSDM channel serial interface structure definition
NYX	0:85b3fd62ea1a	100	*/
NYX	0:85b3fd62ea1a	101	typedef struct
NYX	0:85b3fd62ea1a	102	{
NYX	0:85b3fd62ea1a	103	uint32_t Type; /*!< SPI or Manchester modes.
NYX	0:85b3fd62ea1a	104	This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
NYX	0:85b3fd62ea1a	105	uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
NYX	0:85b3fd62ea1a	106	This parameter can be a value of @ref DFSDM_Channel_SpiClock */
NYX	0:85b3fd62ea1a	107	}DFSDM_Channel_SerialInterfaceTypeDef;
NYX	0:85b3fd62ea1a	108
NYX	0:85b3fd62ea1a	109	/**
NYX	0:85b3fd62ea1a	110	* @brief DFSDM channel analog watchdog structure definition
NYX	0:85b3fd62ea1a	111	*/
NYX	0:85b3fd62ea1a	112	typedef struct
NYX	0:85b3fd62ea1a	113	{
NYX	0:85b3fd62ea1a	114	uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
NYX	0:85b3fd62ea1a	115	This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
NYX	0:85b3fd62ea1a	116	uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
NYX	0:85b3fd62ea1a	117	This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
NYX	0:85b3fd62ea1a	118	}DFSDM_Channel_AwdTypeDef;
NYX	0:85b3fd62ea1a	119
NYX	0:85b3fd62ea1a	120	/**
NYX	0:85b3fd62ea1a	121	* @brief DFSDM channel init structure definition
NYX	0:85b3fd62ea1a	122	*/
NYX	0:85b3fd62ea1a	123	typedef struct
NYX	0:85b3fd62ea1a	124	{
NYX	0:85b3fd62ea1a	125	DFSDM_Channel_OutputClockTypeDef OutputClock; /!< DFSDM channel output clock parameters /
NYX	0:85b3fd62ea1a	126	DFSDM_Channel_InputTypeDef Input; /!< DFSDM channel input parameters /
NYX	0:85b3fd62ea1a	127	DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /!< DFSDM channel serial interface parameters /
NYX	0:85b3fd62ea1a	128	DFSDM_Channel_AwdTypeDef Awd; /!< DFSDM channel analog watchdog parameters /
NYX	0:85b3fd62ea1a	129	int32_t Offset; /*!< DFSDM channel offset.
NYX	0:85b3fd62ea1a	130	This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
NYX	0:85b3fd62ea1a	131	uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
NYX	0:85b3fd62ea1a	132	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
NYX	0:85b3fd62ea1a	133	}DFSDM_Channel_InitTypeDef;
NYX	0:85b3fd62ea1a	134
NYX	0:85b3fd62ea1a	135	/**
NYX	0:85b3fd62ea1a	136	* @brief DFSDM channel handle structure definition
NYX	0:85b3fd62ea1a	137	*/
NYX	0:85b3fd62ea1a	138	typedef struct
NYX	0:85b3fd62ea1a	139	{
NYX	0:85b3fd62ea1a	140	DFSDM_Channel_TypeDef Instance; /!< DFSDM channel instance */
NYX	0:85b3fd62ea1a	141	DFSDM_Channel_InitTypeDef Init; /!< DFSDM channel init parameters /
NYX	0:85b3fd62ea1a	142	HAL_DFSDM_Channel_StateTypeDef State; /!< DFSDM channel state /
NYX	0:85b3fd62ea1a	143	}DFSDM_Channel_HandleTypeDef;
NYX	0:85b3fd62ea1a	144
NYX	0:85b3fd62ea1a	145	/**
NYX	0:85b3fd62ea1a	146	* @brief HAL DFSDM Filter states definition
NYX	0:85b3fd62ea1a	147	*/
NYX	0:85b3fd62ea1a	148	typedef enum
NYX	0:85b3fd62ea1a	149	{
NYX	0:85b3fd62ea1a	150	HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /!< DFSDM filter not initialized /
NYX	0:85b3fd62ea1a	151	HAL_DFSDM_FILTER_STATE_READY = 0x01U, /!< DFSDM filter initialized and ready for use /
NYX	0:85b3fd62ea1a	152	HAL_DFSDM_FILTER_STATE_REG = 0x02U, /!< DFSDM filter regular conversion in progress /
NYX	0:85b3fd62ea1a	153	HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /!< DFSDM filter injected conversion in progress /
NYX	0:85b3fd62ea1a	154	HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /!< DFSDM filter regular and injected conversions in progress /
NYX	0:85b3fd62ea1a	155	HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /!< DFSDM filter state error /
NYX	0:85b3fd62ea1a	156	}HAL_DFSDM_Filter_StateTypeDef;
NYX	0:85b3fd62ea1a	157
NYX	0:85b3fd62ea1a	158	/**
NYX	0:85b3fd62ea1a	159	* @brief DFSDM filter regular conversion parameters structure definition
NYX	0:85b3fd62ea1a	160	*/
NYX	0:85b3fd62ea1a	161	typedef struct
NYX	0:85b3fd62ea1a	162	{
NYX	0:85b3fd62ea1a	163	uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
NYX	0:85b3fd62ea1a	164	This parameter can be a value of @ref DFSDM_Filter_Trigger */
NYX	0:85b3fd62ea1a	165	FunctionalState FastMode; /!< Enable/disable fast mode for regular conversion /
NYX	0:85b3fd62ea1a	166	FunctionalState DmaMode; /!< Enable/disable DMA for regular conversion /
NYX	0:85b3fd62ea1a	167	}DFSDM_Filter_RegularParamTypeDef;
NYX	0:85b3fd62ea1a	168
NYX	0:85b3fd62ea1a	169	/**
NYX	0:85b3fd62ea1a	170	* @brief DFSDM filter injected conversion parameters structure definition
NYX	0:85b3fd62ea1a	171	*/
NYX	0:85b3fd62ea1a	172	typedef struct
NYX	0:85b3fd62ea1a	173	{
NYX	0:85b3fd62ea1a	174	uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
NYX	0:85b3fd62ea1a	175	This parameter can be a value of @ref DFSDM_Filter_Trigger */
NYX	0:85b3fd62ea1a	176	FunctionalState ScanMode; /!< Enable/disable scanning mode for injected conversion /
NYX	0:85b3fd62ea1a	177	FunctionalState DmaMode; /!< Enable/disable DMA for injected conversion /
NYX	0:85b3fd62ea1a	178	uint32_t ExtTrigger; /*!< External trigger.
NYX	0:85b3fd62ea1a	179	This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
NYX	0:85b3fd62ea1a	180	uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
NYX	0:85b3fd62ea1a	181	This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
NYX	0:85b3fd62ea1a	182	}DFSDM_Filter_InjectedParamTypeDef;
NYX	0:85b3fd62ea1a	183
NYX	0:85b3fd62ea1a	184	/**
NYX	0:85b3fd62ea1a	185	* @brief DFSDM filter parameters structure definition
NYX	0:85b3fd62ea1a	186	*/
NYX	0:85b3fd62ea1a	187	typedef struct
NYX	0:85b3fd62ea1a	188	{
NYX	0:85b3fd62ea1a	189	uint32_t SincOrder; /*!< Sinc filter order.
NYX	0:85b3fd62ea1a	190	This parameter can be a value of @ref DFSDM_Filter_SincOrder */
NYX	0:85b3fd62ea1a	191	uint32_t Oversampling; /*!< Filter oversampling ratio.
NYX	0:85b3fd62ea1a	192	This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
NYX	0:85b3fd62ea1a	193	uint32_t IntOversampling; /*!< Integrator oversampling ratio.
NYX	0:85b3fd62ea1a	194	This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
NYX	0:85b3fd62ea1a	195	}DFSDM_Filter_FilterParamTypeDef;
NYX	0:85b3fd62ea1a	196
NYX	0:85b3fd62ea1a	197	/**
NYX	0:85b3fd62ea1a	198	* @brief DFSDM filter init structure definition
NYX	0:85b3fd62ea1a	199	*/
NYX	0:85b3fd62ea1a	200	typedef struct
NYX	0:85b3fd62ea1a	201	{
NYX	0:85b3fd62ea1a	202	DFSDM_Filter_RegularParamTypeDef RegularParam; /!< DFSDM regular conversion parameters /
NYX	0:85b3fd62ea1a	203	DFSDM_Filter_InjectedParamTypeDef InjectedParam; /!< DFSDM injected conversion parameters /
NYX	0:85b3fd62ea1a	204	DFSDM_Filter_FilterParamTypeDef FilterParam; /!< DFSDM filter parameters /
NYX	0:85b3fd62ea1a	205	}DFSDM_Filter_InitTypeDef;
NYX	0:85b3fd62ea1a	206
NYX	0:85b3fd62ea1a	207	/**
NYX	0:85b3fd62ea1a	208	* @brief DFSDM filter handle structure definition
NYX	0:85b3fd62ea1a	209	*/
NYX	0:85b3fd62ea1a	210	typedef struct
NYX	0:85b3fd62ea1a	211	{
NYX	0:85b3fd62ea1a	212	DFSDM_Filter_TypeDef Instance; /!< DFSDM filter instance */
NYX	0:85b3fd62ea1a	213	DFSDM_Filter_InitTypeDef Init; /!< DFSDM filter init parameters /
NYX	0:85b3fd62ea1a	214	DMA_HandleTypeDef hdmaReg; /!< Pointer on DMA handler for regular conversions */
NYX	0:85b3fd62ea1a	215	DMA_HandleTypeDef hdmaInj; /!< Pointer on DMA handler for injected conversions */
NYX	0:85b3fd62ea1a	216	uint32_t RegularContMode; /!< Regular conversion continuous mode /
NYX	0:85b3fd62ea1a	217	uint32_t RegularTrigger; /!< Trigger used for regular conversion /
NYX	0:85b3fd62ea1a	218	uint32_t InjectedTrigger; /!< Trigger used for injected conversion /
NYX	0:85b3fd62ea1a	219	uint32_t ExtTriggerEdge; /!< Rising, falling or both edges selected /
NYX	0:85b3fd62ea1a	220	FunctionalState InjectedScanMode; /!< Injected scanning mode /
NYX	0:85b3fd62ea1a	221	uint32_t InjectedChannelsNbr; /!< Number of channels in injected sequence /
NYX	0:85b3fd62ea1a	222	uint32_t InjConvRemaining; /!< Injected conversions remaining /
NYX	0:85b3fd62ea1a	223	HAL_DFSDM_Filter_StateTypeDef State; /!< DFSDM filter state /
NYX	0:85b3fd62ea1a	224	uint32_t ErrorCode; /!< DFSDM filter error code /
NYX	0:85b3fd62ea1a	225	}DFSDM_Filter_HandleTypeDef;
NYX	0:85b3fd62ea1a	226
NYX	0:85b3fd62ea1a	227	/**
NYX	0:85b3fd62ea1a	228	* @brief DFSDM filter analog watchdog parameters structure definition
NYX	0:85b3fd62ea1a	229	*/
NYX	0:85b3fd62ea1a	230	typedef struct
NYX	0:85b3fd62ea1a	231	{
NYX	0:85b3fd62ea1a	232	uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
NYX	0:85b3fd62ea1a	233	This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
NYX	0:85b3fd62ea1a	234	uint32_t Channel; /*!< Analog watchdog channel selection.
NYX	0:85b3fd62ea1a	235	This parameter can be a values combination of @ref DFSDM_Channel_Selection */
NYX	0:85b3fd62ea1a	236	int32_t HighThreshold; /*!< High threshold for the analog watchdog.
NYX	0:85b3fd62ea1a	237	This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
NYX	0:85b3fd62ea1a	238	int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
NYX	0:85b3fd62ea1a	239	This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
NYX	0:85b3fd62ea1a	240	uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
NYX	0:85b3fd62ea1a	241	This parameter can be a values combination of @ref DFSDM_BreakSignals */
NYX	0:85b3fd62ea1a	242	uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
NYX	0:85b3fd62ea1a	243	This parameter can be a values combination of @ref DFSDM_BreakSignals */
NYX	0:85b3fd62ea1a	244	}DFSDM_Filter_AwdParamTypeDef;
NYX	0:85b3fd62ea1a	245
NYX	0:85b3fd62ea1a	246	/**
NYX	0:85b3fd62ea1a	247	* @}
NYX	0:85b3fd62ea1a	248	*/
NYX	0:85b3fd62ea1a	249	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
NYX	0:85b3fd62ea1a	250	/**
NYX	0:85b3fd62ea1a	251	* @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices
NYX	0:85b3fd62ea1a	252	*/
NYX	0:85b3fd62ea1a	253	typedef struct
NYX	0:85b3fd62ea1a	254	{
NYX	0:85b3fd62ea1a	255	uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin.
NYX	0:85b3fd62ea1a	256	This parameter can be a value of @ref DFSDM_1_CLOCKIN_SELECTION*/
NYX	0:85b3fd62ea1a	257	uint32_t DFSDM2ClockIn; /*!< Source selection for DFSDM2_Ckin.
NYX	0:85b3fd62ea1a	258	This parameter can be a value of @ref DFSDM_2_CLOCKIN_SELECTION*/
NYX	0:85b3fd62ea1a	259	uint32_t DFSDM1ClockOut; /*!< Source selection for DFSDM1_Ckout.
NYX	0:85b3fd62ea1a	260	This parameter can be a value of @ref DFSDM_1_CLOCKOUT_SELECTION*/
NYX	0:85b3fd62ea1a	261	uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout.
NYX	0:85b3fd62ea1a	262	This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/
NYX	0:85b3fd62ea1a	263	uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2.
NYX	0:85b3fd62ea1a	264	This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION
NYX	0:85b3fd62ea1a	265	@note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2
NYX	0:85b3fd62ea1a	266	@note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */
NYX	0:85b3fd62ea1a	267	uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4.
NYX	0:85b3fd62ea1a	268	This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION
NYX	0:85b3fd62ea1a	269	@note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4
NYX	0:85b3fd62ea1a	270	@note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5
NYX	0:85b3fd62ea1a	271	@note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6
NYX	0:85b3fd62ea1a	272	@note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */
NYX	0:85b3fd62ea1a	273	uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1.
NYX	0:85b3fd62ea1a	274	This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */
NYX	0:85b3fd62ea1a	275	uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2.
NYX	0:85b3fd62ea1a	276	This parameter can be a value of @ref DFSDM_2_DATA_DISTRIBUTION */
NYX	0:85b3fd62ea1a	277	}DFSDM_MultiChannelConfigTypeDef;
NYX	0:85b3fd62ea1a	278	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
NYX	0:85b3fd62ea1a	279	/**
NYX	0:85b3fd62ea1a	280	* @}
NYX	0:85b3fd62ea1a	281	*/
NYX	0:85b3fd62ea1a	282
NYX	0:85b3fd62ea1a	283	/* End of exported types -----------------------------------------------------*/
NYX	0:85b3fd62ea1a	284
NYX	0:85b3fd62ea1a	285	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	286	/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
NYX	0:85b3fd62ea1a	287	* @{
NYX	0:85b3fd62ea1a	288	*/
NYX	0:85b3fd62ea1a	289
NYX	0:85b3fd62ea1a	290	/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
NYX	0:85b3fd62ea1a	291	* @{
NYX	0:85b3fd62ea1a	292	*/
NYX	0:85b3fd62ea1a	293	#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /!< Source for ouput clock is system clock /
NYX	0:85b3fd62ea1a	294	#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /!< Source for ouput clock is audio clock /
NYX	0:85b3fd62ea1a	295	/**
NYX	0:85b3fd62ea1a	296	* @}
NYX	0:85b3fd62ea1a	297	*/
NYX	0:85b3fd62ea1a	298
NYX	0:85b3fd62ea1a	299	/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
NYX	0:85b3fd62ea1a	300	* @{
NYX	0:85b3fd62ea1a	301	*/
NYX	0:85b3fd62ea1a	302	#define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /!< Data are taken from external inputs /
NYX	0:85b3fd62ea1a	303	#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /!< Data are taken from internal register /
NYX	0:85b3fd62ea1a	304	/**
NYX	0:85b3fd62ea1a	305	* @}
NYX	0:85b3fd62ea1a	306	*/
NYX	0:85b3fd62ea1a	307
NYX	0:85b3fd62ea1a	308	/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
NYX	0:85b3fd62ea1a	309	* @{
NYX	0:85b3fd62ea1a	310	*/
NYX	0:85b3fd62ea1a	311	#define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /!< Standard data packing mode /
NYX	0:85b3fd62ea1a	312	#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /!< Interleaved data packing mode /
NYX	0:85b3fd62ea1a	313	#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /!< Dual data packing mode /
NYX	0:85b3fd62ea1a	314	/**
NYX	0:85b3fd62ea1a	315	* @}
NYX	0:85b3fd62ea1a	316	*/
NYX	0:85b3fd62ea1a	317
NYX	0:85b3fd62ea1a	318	/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
NYX	0:85b3fd62ea1a	319	* @{
NYX	0:85b3fd62ea1a	320	*/
NYX	0:85b3fd62ea1a	321	#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /!< Input from pins on same channel /
NYX	0:85b3fd62ea1a	322	#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /!< Input from pins on following channel /
NYX	0:85b3fd62ea1a	323	/**
NYX	0:85b3fd62ea1a	324	* @}
NYX	0:85b3fd62ea1a	325	*/
NYX	0:85b3fd62ea1a	326
NYX	0:85b3fd62ea1a	327	/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
NYX	0:85b3fd62ea1a	328	* @{
NYX	0:85b3fd62ea1a	329	*/
NYX	0:85b3fd62ea1a	330	#define DFSDM_CHANNEL_SPI_RISING 0x00000000U /!< SPI with rising edge /
NYX	0:85b3fd62ea1a	331	#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /!< SPI with falling edge /
NYX	0:85b3fd62ea1a	332	#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /!< Manchester with rising edge /
NYX	0:85b3fd62ea1a	333	#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /!< Manchester with falling edge /
NYX	0:85b3fd62ea1a	334	/**
NYX	0:85b3fd62ea1a	335	* @}
NYX	0:85b3fd62ea1a	336	*/
NYX	0:85b3fd62ea1a	337
NYX	0:85b3fd62ea1a	338	/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
NYX	0:85b3fd62ea1a	339	* @{
NYX	0:85b3fd62ea1a	340	*/
NYX	0:85b3fd62ea1a	341	#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /!< External SPI clock /
NYX	0:85b3fd62ea1a	342	#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /!< Internal SPI clock /
NYX	0:85b3fd62ea1a	343	#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /!< Internal SPI clock divided by 2, falling edge /
NYX	0:85b3fd62ea1a	344	#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /!< Internal SPI clock divided by 2, rising edge /
NYX	0:85b3fd62ea1a	345	/**
NYX	0:85b3fd62ea1a	346	* @}
NYX	0:85b3fd62ea1a	347	*/
NYX	0:85b3fd62ea1a	348
NYX	0:85b3fd62ea1a	349	/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
NYX	0:85b3fd62ea1a	350	* @{
NYX	0:85b3fd62ea1a	351	*/
NYX	0:85b3fd62ea1a	352	#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /!< FastSinc filter type /
NYX	0:85b3fd62ea1a	353	#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /!< Sinc 1 filter type /
NYX	0:85b3fd62ea1a	354	#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /!< Sinc 2 filter type /
NYX	0:85b3fd62ea1a	355	#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /!< Sinc 3 filter type /
NYX	0:85b3fd62ea1a	356	/**
NYX	0:85b3fd62ea1a	357	* @}
NYX	0:85b3fd62ea1a	358	*/
NYX	0:85b3fd62ea1a	359
NYX	0:85b3fd62ea1a	360	/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
NYX	0:85b3fd62ea1a	361	* @{
NYX	0:85b3fd62ea1a	362	*/
NYX	0:85b3fd62ea1a	363	#define DFSDM_FILTER_SW_TRIGGER 0x00000000U /!< Software trigger /
NYX	0:85b3fd62ea1a	364	#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /!< Synchronous with DFSDM_FLT0 /
NYX	0:85b3fd62ea1a	365	#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /!< External trigger (only for injected conversion) /
NYX	0:85b3fd62ea1a	366	/**
NYX	0:85b3fd62ea1a	367	* @}
NYX	0:85b3fd62ea1a	368	*/
NYX	0:85b3fd62ea1a	369
NYX	0:85b3fd62ea1a	370	/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
NYX	0:85b3fd62ea1a	371	* @{
NYX	0:85b3fd62ea1a	372	*/
NYX	0:85b3fd62ea1a	373	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
NYX	0:85b3fd62ea1a	374	/* Trigger for stm32f413xx and STM32f423xx devices */
NYX	0:85b3fd62ea1a	375	#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /!< For All DFSDM1/2 filters /
NYX	0:85b3fd62ea1a	376	#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /!< For All DFSDM1/2 filters /
NYX	0:85b3fd62ea1a	377	#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /!< For All DFSDM1/2 filters /
NYX	0:85b3fd62ea1a	378	#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_1) /!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 /
NYX	0:85b3fd62ea1a	379	#define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_1) /!< For DFSDM2 filter 3 /
NYX	0:85b3fd62ea1a	380	#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 /
NYX	0:85b3fd62ea1a	381	#define DFSDM_FILTER_EXT_TRIG_TIM11_OC1 DFSDM_FLTCR1_JEXTSEL_2 /!< For DFSDM2 filter 3 /
NYX	0:85b3fd62ea1a	382	#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0 and 1 /
NYX	0:85b3fd62ea1a	383	#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For DFSDM2 filter 2 and 3/
NYX	0:85b3fd62ea1a	384	#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For All DFSDM1/2 filters /
NYX	0:85b3fd62ea1a	385	#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /!< For All DFSDM1/2 filters /
NYX	0:85b3fd62ea1a	386	#else
NYX	0:85b3fd62ea1a	387	/* Trigger for stm32f412xx devices */
NYX	0:85b3fd62ea1a	388	#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /!< For DFSDM1 filter 0 and 1/
NYX	0:85b3fd62ea1a	389	#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /!< For DFSDM1 filter 0 and 1/
NYX	0:85b3fd62ea1a	390	#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /!< For DFSDM1 filter 0 and 1/
NYX	0:85b3fd62ea1a	391	#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_1) /!< For DFSDM1 filter 0 and 1/
NYX	0:85b3fd62ea1a	392	#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /!< For DFSDM1 filter 0 and 1/
NYX	0:85b3fd62ea1a	393	#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For DFSDM1 filter 0 and 1/
NYX	0:85b3fd62ea1a	394	#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 \| DFSDM_FLTCR1_JEXTSEL_2) /!< For DFSDM1 filter 0 and 1/
NYX	0:85b3fd62ea1a	395	#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /!< For DFSDM1 filter 0 and 1/
NYX	0:85b3fd62ea1a	396	#endif
NYX	0:85b3fd62ea1a	397	/**
NYX	0:85b3fd62ea1a	398	* @}
NYX	0:85b3fd62ea1a	399	*/
NYX	0:85b3fd62ea1a	400
NYX	0:85b3fd62ea1a	401	/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
NYX	0:85b3fd62ea1a	402	* @{
NYX	0:85b3fd62ea1a	403	*/
NYX	0:85b3fd62ea1a	404	#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /!< External rising edge /
NYX	0:85b3fd62ea1a	405	#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /!< External falling edge /
NYX	0:85b3fd62ea1a	406	#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /!< External rising and falling edges /
NYX	0:85b3fd62ea1a	407	/**
NYX	0:85b3fd62ea1a	408	* @}
NYX	0:85b3fd62ea1a	409	*/
NYX	0:85b3fd62ea1a	410
NYX	0:85b3fd62ea1a	411	/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
NYX	0:85b3fd62ea1a	412	* @{
NYX	0:85b3fd62ea1a	413	*/
NYX	0:85b3fd62ea1a	414	#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /!< FastSinc filter type /
NYX	0:85b3fd62ea1a	415	#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /!< Sinc 1 filter type /
NYX	0:85b3fd62ea1a	416	#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /!< Sinc 2 filter type /
NYX	0:85b3fd62ea1a	417	#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 \| DFSDM_FLTFCR_FORD_1) /!< Sinc 3 filter type /
NYX	0:85b3fd62ea1a	418	#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /!< Sinc 4 filter type /
NYX	0:85b3fd62ea1a	419	#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 \| DFSDM_FLTFCR_FORD_2) /!< Sinc 5 filter type /
NYX	0:85b3fd62ea1a	420	/**
NYX	0:85b3fd62ea1a	421	* @}
NYX	0:85b3fd62ea1a	422	*/
NYX	0:85b3fd62ea1a	423
NYX	0:85b3fd62ea1a	424	/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
NYX	0:85b3fd62ea1a	425	* @{
NYX	0:85b3fd62ea1a	426	*/
NYX	0:85b3fd62ea1a	427	#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /!< From digital filter /
NYX	0:85b3fd62ea1a	428	#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /!< From analog watchdog channel /
NYX	0:85b3fd62ea1a	429	/**
NYX	0:85b3fd62ea1a	430	* @}
NYX	0:85b3fd62ea1a	431	*/
NYX	0:85b3fd62ea1a	432
NYX	0:85b3fd62ea1a	433	/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
NYX	0:85b3fd62ea1a	434	* @{
NYX	0:85b3fd62ea1a	435	*/
NYX	0:85b3fd62ea1a	436	#define DFSDM_FILTER_ERROR_NONE 0x00000000U /!< No error /
NYX	0:85b3fd62ea1a	437	#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /!< Overrun occurs during regular conversion /
NYX	0:85b3fd62ea1a	438	#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /!< Overrun occurs during injected conversion /
NYX	0:85b3fd62ea1a	439	#define DFSDM_FILTER_ERROR_DMA 0x00000003U /!< DMA error occurs /
NYX	0:85b3fd62ea1a	440	/**
NYX	0:85b3fd62ea1a	441	* @}
NYX	0:85b3fd62ea1a	442	*/
NYX	0:85b3fd62ea1a	443
NYX	0:85b3fd62ea1a	444	/** @defgroup DFSDM_BreakSignals DFSDM break signals
NYX	0:85b3fd62ea1a	445	* @{
NYX	0:85b3fd62ea1a	446	*/
NYX	0:85b3fd62ea1a	447	#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /!< No break signal /
NYX	0:85b3fd62ea1a	448	#define DFSDM_BREAK_SIGNAL_0 0x00000001U /!< Break signal 0 /
NYX	0:85b3fd62ea1a	449	#define DFSDM_BREAK_SIGNAL_1 0x00000002U /!< Break signal 1 /
NYX	0:85b3fd62ea1a	450	#define DFSDM_BREAK_SIGNAL_2 0x00000004U /!< Break signal 2 /
NYX	0:85b3fd62ea1a	451	#define DFSDM_BREAK_SIGNAL_3 0x00000008U /!< Break signal 3 /
NYX	0:85b3fd62ea1a	452	/**
NYX	0:85b3fd62ea1a	453	* @}
NYX	0:85b3fd62ea1a	454	*/
NYX	0:85b3fd62ea1a	455
NYX	0:85b3fd62ea1a	456	/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
NYX	0:85b3fd62ea1a	457	* @{
NYX	0:85b3fd62ea1a	458	*/
NYX	0:85b3fd62ea1a	459	/* DFSDM Channels ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	460	/* The DFSDM channels are defined as follows:
NYX	0:85b3fd62ea1a	461	- in 16-bit LSB the channel mask is set
NYX	0:85b3fd62ea1a	462	- in 16-bit MSB the channel number is set
NYX	0:85b3fd62ea1a	463	e.g. for channel 3 definition:
NYX	0:85b3fd62ea1a	464	- the channel mask is 0x00000008 (bit 3 is set)
NYX	0:85b3fd62ea1a	465	- the channel number 3 is 0x00030000
NYX	0:85b3fd62ea1a	466	--> Consequently, channel 3 definition is 0x00000008 \| 0x00030000 = 0x00030008 */
NYX	0:85b3fd62ea1a	467	#define DFSDM_CHANNEL_0 0x00000001U
NYX	0:85b3fd62ea1a	468	#define DFSDM_CHANNEL_1 0x00010002U
NYX	0:85b3fd62ea1a	469	#define DFSDM_CHANNEL_2 0x00020004U
NYX	0:85b3fd62ea1a	470	#define DFSDM_CHANNEL_3 0x00030008U
NYX	0:85b3fd62ea1a	471	#define DFSDM_CHANNEL_4 0x00040010U /* only for stmm32f413xx and stm32f423xx devices */
NYX	0:85b3fd62ea1a	472	#define DFSDM_CHANNEL_5 0x00050020U /* only for stmm32f413xx and stm32f423xx devices */
NYX	0:85b3fd62ea1a	473	#define DFSDM_CHANNEL_6 0x00060040U /* only for stmm32f413xx and stm32f423xx devices */
NYX	0:85b3fd62ea1a	474	#define DFSDM_CHANNEL_7 0x00070080U /* only for stmm32f413xx and stm32f423xx devices */
NYX	0:85b3fd62ea1a	475	/**
NYX	0:85b3fd62ea1a	476	* @}
NYX	0:85b3fd62ea1a	477	*/
NYX	0:85b3fd62ea1a	478
NYX	0:85b3fd62ea1a	479	/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
NYX	0:85b3fd62ea1a	480	* @{
NYX	0:85b3fd62ea1a	481	*/
NYX	0:85b3fd62ea1a	482	#define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /!< Conversion are not continuous /
NYX	0:85b3fd62ea1a	483	#define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /!< Conversion are continuous /
NYX	0:85b3fd62ea1a	484	/**
NYX	0:85b3fd62ea1a	485	* @}
NYX	0:85b3fd62ea1a	486	*/
NYX	0:85b3fd62ea1a	487
NYX	0:85b3fd62ea1a	488	/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
NYX	0:85b3fd62ea1a	489	* @{
NYX	0:85b3fd62ea1a	490	*/
NYX	0:85b3fd62ea1a	491	#define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /!< Analog watchdog high threshold /
NYX	0:85b3fd62ea1a	492	#define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /!< Analog watchdog low threshold /
NYX	0:85b3fd62ea1a	493	/**
NYX	0:85b3fd62ea1a	494	* @}
NYX	0:85b3fd62ea1a	495	*/
NYX	0:85b3fd62ea1a	496
NYX	0:85b3fd62ea1a	497	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
NYX	0:85b3fd62ea1a	498	/** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection
NYX	0:85b3fd62ea1a	499	* @{
NYX	0:85b3fd62ea1a	500	*/
NYX	0:85b3fd62ea1a	501	#define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U
NYX	0:85b3fd62ea1a	502	#define DFSDM1_CKOUT_DFSDM1 0x00000000U
NYX	0:85b3fd62ea1a	503	/**
NYX	0:85b3fd62ea1a	504	* @}
NYX	0:85b3fd62ea1a	505	*/
NYX	0:85b3fd62ea1a	506
NYX	0:85b3fd62ea1a	507	/** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection
NYX	0:85b3fd62ea1a	508	* @{
NYX	0:85b3fd62ea1a	509	*/
NYX	0:85b3fd62ea1a	510	#define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U
NYX	0:85b3fd62ea1a	511	#define DFSDM2_CKOUT_DFSDM2 0x00000000U
NYX	0:85b3fd62ea1a	512	/**
NYX	0:85b3fd62ea1a	513	* @}
NYX	0:85b3fd62ea1a	514	*/
NYX	0:85b3fd62ea1a	515
NYX	0:85b3fd62ea1a	516	/** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection
NYX	0:85b3fd62ea1a	517	* @{
NYX	0:85b3fd62ea1a	518	*/
NYX	0:85b3fd62ea1a	519	#define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U
NYX	0:85b3fd62ea1a	520	#define DFSDM1_CKIN_PAD 0x00000000U
NYX	0:85b3fd62ea1a	521	/**
NYX	0:85b3fd62ea1a	522	* @}
NYX	0:85b3fd62ea1a	523	*/
NYX	0:85b3fd62ea1a	524
NYX	0:85b3fd62ea1a	525	/** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection
NYX	0:85b3fd62ea1a	526	* @{
NYX	0:85b3fd62ea1a	527	*/
NYX	0:85b3fd62ea1a	528	#define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U
NYX	0:85b3fd62ea1a	529	#define DFSDM2_CKIN_PAD 0x00000000U
NYX	0:85b3fd62ea1a	530	/**
NYX	0:85b3fd62ea1a	531	* @}
NYX	0:85b3fd62ea1a	532	*/
NYX	0:85b3fd62ea1a	533
NYX	0:85b3fd62ea1a	534	/** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution
NYX	0:85b3fd62ea1a	535	* @{
NYX	0:85b3fd62ea1a	536	*/
NYX	0:85b3fd62ea1a	537	#define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */
NYX	0:85b3fd62ea1a	538	#define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */
NYX	0:85b3fd62ea1a	539	#define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */
NYX	0:85b3fd62ea1a	540	#define DFSDM1_T4_OC1_BITSTREAM_CKIN1 0x00000000U /* TIM4_OC1 to CLKIN1 */
NYX	0:85b3fd62ea1a	541	/**
NYX	0:85b3fd62ea1a	542	* @}
NYX	0:85b3fd62ea1a	543	*/
NYX	0:85b3fd62ea1a	544
NYX	0:85b3fd62ea1a	545	/** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution
NYX	0:85b3fd62ea1a	546	* @{
NYX	0:85b3fd62ea1a	547	*/
NYX	0:85b3fd62ea1a	548	#define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */
NYX	0:85b3fd62ea1a	549	#define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */
NYX	0:85b3fd62ea1a	550	#define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */
NYX	0:85b3fd62ea1a	551	#define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */
NYX	0:85b3fd62ea1a	552	#define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */
NYX	0:85b3fd62ea1a	553	#define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */
NYX	0:85b3fd62ea1a	554	#define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */
NYX	0:85b3fd62ea1a	555	#define DFSDM2_T3_OC1_BITSTREAM_CKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */
NYX	0:85b3fd62ea1a	556	/**
NYX	0:85b3fd62ea1a	557	* @}
NYX	0:85b3fd62ea1a	558	*/
NYX	0:85b3fd62ea1a	559
NYX	0:85b3fd62ea1a	560	/** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution
NYX	0:85b3fd62ea1a	561	* @{
NYX	0:85b3fd62ea1a	562	*/
NYX	0:85b3fd62ea1a	563	#define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U
NYX	0:85b3fd62ea1a	564	#define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL
NYX	0:85b3fd62ea1a	565	#define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U
NYX	0:85b3fd62ea1a	566	#define DFSDM1_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM1D2SEL
NYX	0:85b3fd62ea1a	567	/**
NYX	0:85b3fd62ea1a	568	* @}
NYX	0:85b3fd62ea1a	569	*/
NYX	0:85b3fd62ea1a	570
NYX	0:85b3fd62ea1a	571	/** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution
NYX	0:85b3fd62ea1a	572	* @{
NYX	0:85b3fd62ea1a	573	*/
NYX	0:85b3fd62ea1a	574	#define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U
NYX	0:85b3fd62ea1a	575	#define DFSDM2_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM2D0SEL
NYX	0:85b3fd62ea1a	576	#define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U
NYX	0:85b3fd62ea1a	577	#define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL
NYX	0:85b3fd62ea1a	578	#define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U
NYX	0:85b3fd62ea1a	579	#define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL
NYX	0:85b3fd62ea1a	580	#define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U
NYX	0:85b3fd62ea1a	581	#define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL
NYX	0:85b3fd62ea1a	582	/**
NYX	0:85b3fd62ea1a	583	* @}
NYX	0:85b3fd62ea1a	584	*/
NYX	0:85b3fd62ea1a	585
NYX	0:85b3fd62ea1a	586	/** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable
NYX	0:85b3fd62ea1a	587	* @{
NYX	0:85b3fd62ea1a	588	*/
NYX	0:85b3fd62ea1a	589	#define HAL_MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN
NYX	0:85b3fd62ea1a	590	#define HAL_MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN
NYX	0:85b3fd62ea1a	591	/**
NYX	0:85b3fd62ea1a	592	* @}
NYX	0:85b3fd62ea1a	593	*/
NYX	0:85b3fd62ea1a	594
NYX	0:85b3fd62ea1a	595	/** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection
NYX	0:85b3fd62ea1a	596	* @{
NYX	0:85b3fd62ea1a	597	*/
NYX	0:85b3fd62ea1a	598	#define HAL_DFSDM2_CKIN_PAD 0x00040000U
NYX	0:85b3fd62ea1a	599	#define HAL_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
NYX	0:85b3fd62ea1a	600	#define HAL_DFSDM1_CKIN_PAD 0x00000000U
NYX	0:85b3fd62ea1a	601	#define HAL_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
NYX	0:85b3fd62ea1a	602	/**
NYX	0:85b3fd62ea1a	603	* @}
NYX	0:85b3fd62ea1a	604	*/
NYX	0:85b3fd62ea1a	605
NYX	0:85b3fd62ea1a	606	/** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection
NYX	0:85b3fd62ea1a	607	* @{
NYX	0:85b3fd62ea1a	608	*/
NYX	0:85b3fd62ea1a	609	#define HAL_DFSDM2_CKOUT_DFSDM2 0x10000000U
NYX	0:85b3fd62ea1a	610	#define HAL_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
NYX	0:85b3fd62ea1a	611	#define HAL_DFSDM1_CKOUT_DFSDM1 0x00000000U
NYX	0:85b3fd62ea1a	612	#define HAL_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
NYX	0:85b3fd62ea1a	613	/**
NYX	0:85b3fd62ea1a	614	* @}
NYX	0:85b3fd62ea1a	615	*/
NYX	0:85b3fd62ea1a	616
NYX	0:85b3fd62ea1a	617	/** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0
NYX	0:85b3fd62ea1a	618	* @{
NYX	0:85b3fd62ea1a	619	*/
NYX	0:85b3fd62ea1a	620	#define HAL_DATAIN0_DFSDM2_PAD 0x10000000U
NYX	0:85b3fd62ea1a	621	#define HAL_DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL
NYX	0:85b3fd62ea1a	622	#define HAL_DATAIN0_DFSDM1_PAD 0x00000000U
NYX	0:85b3fd62ea1a	623	#define HAL_DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL
NYX	0:85b3fd62ea1a	624	/**
NYX	0:85b3fd62ea1a	625	* @}
NYX	0:85b3fd62ea1a	626	*/
NYX	0:85b3fd62ea1a	627
NYX	0:85b3fd62ea1a	628	/** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2
NYX	0:85b3fd62ea1a	629	* @{
NYX	0:85b3fd62ea1a	630	*/
NYX	0:85b3fd62ea1a	631	#define HAL_DATAIN2_DFSDM2_PAD 0x10000000U
NYX	0:85b3fd62ea1a	632	#define HAL_DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL
NYX	0:85b3fd62ea1a	633	#define HAL_DATAIN2_DFSDM1_PAD 0x00000000U
NYX	0:85b3fd62ea1a	634	#define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL
NYX	0:85b3fd62ea1a	635	/**
NYX	0:85b3fd62ea1a	636	* @}
NYX	0:85b3fd62ea1a	637	*/
NYX	0:85b3fd62ea1a	638
NYX	0:85b3fd62ea1a	639	/** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4
NYX	0:85b3fd62ea1a	640	* @{
NYX	0:85b3fd62ea1a	641	*/
NYX	0:85b3fd62ea1a	642	#define HAL_DATAIN4_DFSDM2_PAD 0x00000000U
NYX	0:85b3fd62ea1a	643	#define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL
NYX	0:85b3fd62ea1a	644	/**
NYX	0:85b3fd62ea1a	645	* @}
NYX	0:85b3fd62ea1a	646	*/
NYX	0:85b3fd62ea1a	647
NYX	0:85b3fd62ea1a	648	/** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6
NYX	0:85b3fd62ea1a	649	* @{
NYX	0:85b3fd62ea1a	650	*/
NYX	0:85b3fd62ea1a	651	#define HAL_DATAIN6_DFSDM2_PAD 0x00000000U
NYX	0:85b3fd62ea1a	652	#define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL
NYX	0:85b3fd62ea1a	653	/**
NYX	0:85b3fd62ea1a	654	* @}
NYX	0:85b3fd62ea1a	655	*/
NYX	0:85b3fd62ea1a	656
NYX	0:85b3fd62ea1a	657	/** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN
NYX	0:85b3fd62ea1a	658	* @{
NYX	0:85b3fd62ea1a	659	*/
NYX	0:85b3fd62ea1a	660	#define HAL_DFSDM1_CLKIN0_TIM4OC2 0x01000000U
NYX	0:85b3fd62ea1a	661	#define HAL_DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
NYX	0:85b3fd62ea1a	662	#define HAL_DFSDM1_CLKIN1_TIM4OC1 0x02000000U
NYX	0:85b3fd62ea1a	663	#define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
NYX	0:85b3fd62ea1a	664	/**
NYX	0:85b3fd62ea1a	665	* @}
NYX	0:85b3fd62ea1a	666	*/
NYX	0:85b3fd62ea1a	667
NYX	0:85b3fd62ea1a	668	/** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN
NYX	0:85b3fd62ea1a	669	* @{
NYX	0:85b3fd62ea1a	670	*/
NYX	0:85b3fd62ea1a	671	#define HAL_DFSDM2_CLKIN0_TIM3OC4 0x04000000U
NYX	0:85b3fd62ea1a	672	#define HAL_DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
NYX	0:85b3fd62ea1a	673	#define HAL_DFSDM2_CLKIN1_TIM3OC3 0x08000000U
NYX	0:85b3fd62ea1a	674	#define HAL_DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
NYX	0:85b3fd62ea1a	675	#define HAL_DFSDM2_CLKIN2_TIM3OC2 0x10000000U
NYX	0:85b3fd62ea1a	676	#define HAL_DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
NYX	0:85b3fd62ea1a	677	#define HAL_DFSDM2_CLKIN3_TIM3OC1 0x00000000U
NYX	0:85b3fd62ea1a	678	#define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
NYX	0:85b3fd62ea1a	679	/**
NYX	0:85b3fd62ea1a	680	* @}
NYX	0:85b3fd62ea1a	681	*/
NYX	0:85b3fd62ea1a	682
NYX	0:85b3fd62ea1a	683	#endif /* SYSCFG_MCHDLYCR_BSCKSEL*/
NYX	0:85b3fd62ea1a	684	/**
NYX	0:85b3fd62ea1a	685	* @}
NYX	0:85b3fd62ea1a	686	*/
NYX	0:85b3fd62ea1a	687	/* End of exported constants -------------------------------------------------*/
NYX	0:85b3fd62ea1a	688
NYX	0:85b3fd62ea1a	689	/* Exported macros -----------------------------------------------------------*/
NYX	0:85b3fd62ea1a	690	/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
NYX	0:85b3fd62ea1a	691	* @{
NYX	0:85b3fd62ea1a	692	*/
NYX	0:85b3fd62ea1a	693
NYX	0:85b3fd62ea1a	694	/** @brief Reset DFSDM channel handle state.
NYX	0:85b3fd62ea1a	695	* @param __HANDLE__: DFSDM channel handle.
NYX	0:85b3fd62ea1a	696	* @retval None
NYX	0:85b3fd62ea1a	697	*/
NYX	0:85b3fd62ea1a	698	#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
NYX	0:85b3fd62ea1a	699
NYX	0:85b3fd62ea1a	700	/** @brief Reset DFSDM filter handle state.
NYX	0:85b3fd62ea1a	701	* @param __HANDLE__: DFSDM filter handle.
NYX	0:85b3fd62ea1a	702	* @retval None
NYX	0:85b3fd62ea1a	703	*/
NYX	0:85b3fd62ea1a	704	#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
NYX	0:85b3fd62ea1a	705
NYX	0:85b3fd62ea1a	706	/**
NYX	0:85b3fd62ea1a	707	* @}
NYX	0:85b3fd62ea1a	708	*/
NYX	0:85b3fd62ea1a	709	/* End of exported macros ----------------------------------------------------*/
NYX	0:85b3fd62ea1a	710
NYX	0:85b3fd62ea1a	711	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	712	/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
NYX	0:85b3fd62ea1a	713	* @{
NYX	0:85b3fd62ea1a	714	*/
NYX	0:85b3fd62ea1a	715
NYX	0:85b3fd62ea1a	716	/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
NYX	0:85b3fd62ea1a	717	* @{
NYX	0:85b3fd62ea1a	718	*/
NYX	0:85b3fd62ea1a	719	/* Channel initialization and de-initialization functions *********************/
NYX	0:85b3fd62ea1a	720	HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	721	HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	722	void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	723	void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	724	/**
NYX	0:85b3fd62ea1a	725	* @}
NYX	0:85b3fd62ea1a	726	*/
NYX	0:85b3fd62ea1a	727
NYX	0:85b3fd62ea1a	728	/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
NYX	0:85b3fd62ea1a	729	* @{
NYX	0:85b3fd62ea1a	730	*/
NYX	0:85b3fd62ea1a	731	/* Channel operation functions ************************************************/
NYX	0:85b3fd62ea1a	732	HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	733	HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	734	HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	735	HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	736
NYX	0:85b3fd62ea1a	737	HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
NYX	0:85b3fd62ea1a	738	HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
NYX	0:85b3fd62ea1a	739	HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	740	HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	741
NYX	0:85b3fd62ea1a	742	int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	743	HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
NYX	0:85b3fd62ea1a	744
NYX	0:85b3fd62ea1a	745	HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
NYX	0:85b3fd62ea1a	746	HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
NYX	0:85b3fd62ea1a	747
NYX	0:85b3fd62ea1a	748	void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	749	void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	750	/**
NYX	0:85b3fd62ea1a	751	* @}
NYX	0:85b3fd62ea1a	752	*/
NYX	0:85b3fd62ea1a	753
NYX	0:85b3fd62ea1a	754	/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
NYX	0:85b3fd62ea1a	755	* @{
NYX	0:85b3fd62ea1a	756	*/
NYX	0:85b3fd62ea1a	757	/* Channel state function *****************************************************/
NYX	0:85b3fd62ea1a	758	HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
NYX	0:85b3fd62ea1a	759	/**
NYX	0:85b3fd62ea1a	760	* @}
NYX	0:85b3fd62ea1a	761	*/
NYX	0:85b3fd62ea1a	762
NYX	0:85b3fd62ea1a	763	/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
NYX	0:85b3fd62ea1a	764	* @{
NYX	0:85b3fd62ea1a	765	*/
NYX	0:85b3fd62ea1a	766	/* Filter initialization and de-initialization functions *********************/
NYX	0:85b3fd62ea1a	767	HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	768	HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	769	void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	770	void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	771	/**
NYX	0:85b3fd62ea1a	772	* @}
NYX	0:85b3fd62ea1a	773	*/
NYX	0:85b3fd62ea1a	774
NYX	0:85b3fd62ea1a	775	/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
NYX	0:85b3fd62ea1a	776	* @{
NYX	0:85b3fd62ea1a	777	*/
NYX	0:85b3fd62ea1a	778	/* Filter control functions *********************/
NYX	0:85b3fd62ea1a	779	HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
NYX	0:85b3fd62ea1a	780	uint32_t Channel,
NYX	0:85b3fd62ea1a	781	uint32_t ContinuousMode);
NYX	0:85b3fd62ea1a	782	HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
NYX	0:85b3fd62ea1a	783	uint32_t Channel);
NYX	0:85b3fd62ea1a	784	/**
NYX	0:85b3fd62ea1a	785	* @}
NYX	0:85b3fd62ea1a	786	*/
NYX	0:85b3fd62ea1a	787
NYX	0:85b3fd62ea1a	788	/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
NYX	0:85b3fd62ea1a	789	* @{
NYX	0:85b3fd62ea1a	790	*/
NYX	0:85b3fd62ea1a	791	/* Filter operation functions *********************/
NYX	0:85b3fd62ea1a	792	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	793	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	794	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef hdfsdm_filter, int32_t pData, uint32_t Length);
NYX	0:85b3fd62ea1a	795	HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef hdfsdm_filter, int16_t pData, uint32_t Length);
NYX	0:85b3fd62ea1a	796	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	797	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	798	HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	799	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	800	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	801	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef hdfsdm_filter, int32_t pData, uint32_t Length);
NYX	0:85b3fd62ea1a	802	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef hdfsdm_filter, int16_t pData, uint32_t Length);
NYX	0:85b3fd62ea1a	803	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	804	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	805	HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	806	HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
NYX	0:85b3fd62ea1a	807	DFSDM_Filter_AwdParamTypeDef* awdParam);
NYX	0:85b3fd62ea1a	808	HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	809	HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
NYX	0:85b3fd62ea1a	810	HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	811
NYX	0:85b3fd62ea1a	812	int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef hdfsdm_filter, uint32_t Channel);
NYX	0:85b3fd62ea1a	813	int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef hdfsdm_filter, uint32_t Channel);
NYX	0:85b3fd62ea1a	814	int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef hdfsdm_filter, uint32_t Channel);
NYX	0:85b3fd62ea1a	815	int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef hdfsdm_filter, uint32_t Channel);
NYX	0:85b3fd62ea1a	816	uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	817
NYX	0:85b3fd62ea1a	818	void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	819
NYX	0:85b3fd62ea1a	820	HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
NYX	0:85b3fd62ea1a	821	HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
NYX	0:85b3fd62ea1a	822
NYX	0:85b3fd62ea1a	823	void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	824	void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	825	void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	826	void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	827	void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
NYX	0:85b3fd62ea1a	828	void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	829	/**
NYX	0:85b3fd62ea1a	830	* @}
NYX	0:85b3fd62ea1a	831	*/
NYX	0:85b3fd62ea1a	832
NYX	0:85b3fd62ea1a	833	/** @addtogroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
NYX	0:85b3fd62ea1a	834	* @{
NYX	0:85b3fd62ea1a	835	*/
NYX	0:85b3fd62ea1a	836	/* Filter state functions *****************************************************/
NYX	0:85b3fd62ea1a	837	HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	838	uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
NYX	0:85b3fd62ea1a	839	/**
NYX	0:85b3fd62ea1a	840	* @}
NYX	0:85b3fd62ea1a	841	*/
NYX	0:85b3fd62ea1a	842	/** @addtogroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions
NYX	0:85b3fd62ea1a	843	* @{
NYX	0:85b3fd62ea1a	844	*/
NYX	0:85b3fd62ea1a	845	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
NYX	0:85b3fd62ea1a	846	void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct);
NYX	0:85b3fd62ea1a	847	void HAL_DFSDM_BitstreamClock_Start(void);
NYX	0:85b3fd62ea1a	848	void HAL_DFSDM_BitstreamClock_Stop(void);
NYX	0:85b3fd62ea1a	849	void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY);
NYX	0:85b3fd62ea1a	850	void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY);
NYX	0:85b3fd62ea1a	851	void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source);
NYX	0:85b3fd62ea1a	852	void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source);
NYX	0:85b3fd62ea1a	853	void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source);
NYX	0:85b3fd62ea1a	854	void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source);
NYX	0:85b3fd62ea1a	855	void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source);
NYX	0:85b3fd62ea1a	856	void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source);
NYX	0:85b3fd62ea1a	857	void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
NYX	0:85b3fd62ea1a	858	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
NYX	0:85b3fd62ea1a	859	/**
NYX	0:85b3fd62ea1a	860	* @}
NYX	0:85b3fd62ea1a	861	*/
NYX	0:85b3fd62ea1a	862	/**
NYX	0:85b3fd62ea1a	863	* @}
NYX	0:85b3fd62ea1a	864	*/
NYX	0:85b3fd62ea1a	865	/* End of exported functions -------------------------------------------------*/
NYX	0:85b3fd62ea1a	866
NYX	0:85b3fd62ea1a	867	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	868	/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
NYX	0:85b3fd62ea1a	869	* @{
NYX	0:85b3fd62ea1a	870	*/
NYX	0:85b3fd62ea1a	871	#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) \|\| \
NYX	0:85b3fd62ea1a	872	((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
NYX	0:85b3fd62ea1a	873	#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
NYX	0:85b3fd62ea1a	874	#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) \|\| \
NYX	0:85b3fd62ea1a	875	((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
NYX	0:85b3fd62ea1a	876	#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) \|\| \
NYX	0:85b3fd62ea1a	877	((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) \|\| \
NYX	0:85b3fd62ea1a	878	((MODE) == DFSDM_CHANNEL_DUAL_MODE))
NYX	0:85b3fd62ea1a	879	#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) \|\| \
NYX	0:85b3fd62ea1a	880	((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
NYX	0:85b3fd62ea1a	881	#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) \|\| \
NYX	0:85b3fd62ea1a	882	((MODE) == DFSDM_CHANNEL_SPI_FALLING) \|\| \
NYX	0:85b3fd62ea1a	883	((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) \|\| \
NYX	0:85b3fd62ea1a	884	((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
NYX	0:85b3fd62ea1a	885	#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) \|\| \
NYX	0:85b3fd62ea1a	886	((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) \|\| \
NYX	0:85b3fd62ea1a	887	((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) \|\| \
NYX	0:85b3fd62ea1a	888	((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
NYX	0:85b3fd62ea1a	889	#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) \|\| \
NYX	0:85b3fd62ea1a	890	((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) \|\| \
NYX	0:85b3fd62ea1a	891	((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) \|\| \
NYX	0:85b3fd62ea1a	892	((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
NYX	0:85b3fd62ea1a	893	#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
NYX	0:85b3fd62ea1a	894	#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
NYX	0:85b3fd62ea1a	895	#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
NYX	0:85b3fd62ea1a	896	#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
NYX	0:85b3fd62ea1a	897	#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) \|\| \
NYX	0:85b3fd62ea1a	898	((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
NYX	0:85b3fd62ea1a	899	#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) \|\| \
NYX	0:85b3fd62ea1a	900	((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) \|\| \
NYX	0:85b3fd62ea1a	901	((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
NYX	0:85b3fd62ea1a	902	#if defined (STM32F413xx) \|\| defined (STM32F423xx)
NYX	0:85b3fd62ea1a	903	#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) \|\| \
NYX	0:85b3fd62ea1a	904	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) \|\| \
NYX	0:85b3fd62ea1a	905	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) \|\| \
NYX	0:85b3fd62ea1a	906	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) \|\| \
NYX	0:85b3fd62ea1a	907	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) \|\| \
NYX	0:85b3fd62ea1a	908	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) \|\| \
NYX	0:85b3fd62ea1a	909	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) \|\| \
NYX	0:85b3fd62ea1a	910	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) \|\| \
NYX	0:85b3fd62ea1a	911	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) \|\| \
NYX	0:85b3fd62ea1a	912	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
NYX	0:85b3fd62ea1a	913	#define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) \|\| \
NYX	0:85b3fd62ea1a	914	((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1))
NYX	0:85b3fd62ea1a	915	#else
NYX	0:85b3fd62ea1a	916	#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) \|\| \
NYX	0:85b3fd62ea1a	917	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) \|\| \
NYX	0:85b3fd62ea1a	918	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) \|\| \
NYX	0:85b3fd62ea1a	919	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) \|\| \
NYX	0:85b3fd62ea1a	920	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) \|\| \
NYX	0:85b3fd62ea1a	921	((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) \|\| \
NYX	0:85b3fd62ea1a	922	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) \|\| \
NYX	0:85b3fd62ea1a	923	((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
NYX	0:85b3fd62ea1a	924	#endif
NYX	0:85b3fd62ea1a	925	#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) \|\| \
NYX	0:85b3fd62ea1a	926	((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) \|\| \
NYX	0:85b3fd62ea1a	927	((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
NYX	0:85b3fd62ea1a	928	#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) \|\| \
NYX	0:85b3fd62ea1a	929	((ORDER) == DFSDM_FILTER_SINC1_ORDER) \|\| \
NYX	0:85b3fd62ea1a	930	((ORDER) == DFSDM_FILTER_SINC2_ORDER) \|\| \
NYX	0:85b3fd62ea1a	931	((ORDER) == DFSDM_FILTER_SINC3_ORDER) \|\| \
NYX	0:85b3fd62ea1a	932	((ORDER) == DFSDM_FILTER_SINC4_ORDER) \|\| \
NYX	0:85b3fd62ea1a	933	((ORDER) == DFSDM_FILTER_SINC5_ORDER))
NYX	0:85b3fd62ea1a	934	#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
NYX	0:85b3fd62ea1a	935	#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
NYX	0:85b3fd62ea1a	936	#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) \|\| \
NYX	0:85b3fd62ea1a	937	((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
NYX	0:85b3fd62ea1a	938	#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
NYX	0:85b3fd62ea1a	939	#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU)
NYX	0:85b3fd62ea1a	940	#if defined(DFSDM2_Channel0)
NYX	0:85b3fd62ea1a	941	#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) \|\| \
NYX	0:85b3fd62ea1a	942	((CHANNEL) == DFSDM_CHANNEL_1) \|\| \
NYX	0:85b3fd62ea1a	943	((CHANNEL) == DFSDM_CHANNEL_2) \|\| \
NYX	0:85b3fd62ea1a	944	((CHANNEL) == DFSDM_CHANNEL_3) \|\| \
NYX	0:85b3fd62ea1a	945	((CHANNEL) == DFSDM_CHANNEL_4) \|\| \
NYX	0:85b3fd62ea1a	946	((CHANNEL) == DFSDM_CHANNEL_5) \|\| \
NYX	0:85b3fd62ea1a	947	((CHANNEL) == DFSDM_CHANNEL_6) \|\| \
NYX	0:85b3fd62ea1a	948	((CHANNEL) == DFSDM_CHANNEL_7))
NYX	0:85b3fd62ea1a	949	#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
NYX	0:85b3fd62ea1a	950	#else
NYX	0:85b3fd62ea1a	951	#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) \|\| \
NYX	0:85b3fd62ea1a	952	((CHANNEL) == DFSDM_CHANNEL_1) \|\| \
NYX	0:85b3fd62ea1a	953	((CHANNEL) == DFSDM_CHANNEL_2) \|\| \
NYX	0:85b3fd62ea1a	954	((CHANNEL) == DFSDM_CHANNEL_3))
NYX	0:85b3fd62ea1a	955	#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
NYX	0:85b3fd62ea1a	956	#endif
NYX	0:85b3fd62ea1a	957	#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) \|\| \
NYX	0:85b3fd62ea1a	958	((MODE) == DFSDM_CONTINUOUS_CONV_ON))
NYX	0:85b3fd62ea1a	959	#if defined(DFSDM2_Channel0)
NYX	0:85b3fd62ea1a	960	#define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) \|\| \
NYX	0:85b3fd62ea1a	961	((INSTANCE) == DFSDM1_Channel1) \|\| \
NYX	0:85b3fd62ea1a	962	((INSTANCE) == DFSDM1_Channel2) \|\| \
NYX	0:85b3fd62ea1a	963	((INSTANCE) == DFSDM1_Channel3))
NYX	0:85b3fd62ea1a	964	#define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) \|\| \
NYX	0:85b3fd62ea1a	965	((INSTANCE) == DFSDM1_Filter1))
NYX	0:85b3fd62ea1a	966	#endif /* DFSDM2_Channel0 */
NYX	0:85b3fd62ea1a	967
NYX	0:85b3fd62ea1a	968	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
NYX	0:85b3fd62ea1a	969	#define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) \|\| \
NYX	0:85b3fd62ea1a	970	((SELECTION) == HAL_DFSDM2_CKIN_DM) \|\| \
NYX	0:85b3fd62ea1a	971	((SELECTION) == HAL_DFSDM1_CKIN_PAD) \|\| \
NYX	0:85b3fd62ea1a	972	((SELECTION) == HAL_DFSDM1_CKIN_DM))
NYX	0:85b3fd62ea1a	973	#define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) \|\| \
NYX	0:85b3fd62ea1a	974	((SELECTION) == HAL_DFSDM2_CKOUT_M27) \|\| \
NYX	0:85b3fd62ea1a	975	((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) \|\| \
NYX	0:85b3fd62ea1a	976	((SELECTION) == HAL_DFSDM1_CKOUT_M27))
NYX	0:85b3fd62ea1a	977	#define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) \|\| \
NYX	0:85b3fd62ea1a	978	((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) \|\| \
NYX	0:85b3fd62ea1a	979	((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) \|\| \
NYX	0:85b3fd62ea1a	980	((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1))
NYX	0:85b3fd62ea1a	981	#define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD) \|\| \
NYX	0:85b3fd62ea1a	982	((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) \|\| \
NYX	0:85b3fd62ea1a	983	((SELECTION) == HAL_DATAIN2_DFSDM1_PAD) \|\| \
NYX	0:85b3fd62ea1a	984	((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3))
NYX	0:85b3fd62ea1a	985	#define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD) \|\| \
NYX	0:85b3fd62ea1a	986	((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5))
NYX	0:85b3fd62ea1a	987	#define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD) \|\| \
NYX	0:85b3fd62ea1a	988	((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7))
NYX	0:85b3fd62ea1a	989	#define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) \|\| \
NYX	0:85b3fd62ea1a	990	((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) \|\| \
NYX	0:85b3fd62ea1a	991	((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) \|\| \
NYX	0:85b3fd62ea1a	992	((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) \|\| \
NYX	0:85b3fd62ea1a	993	((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) \|\| \
NYX	0:85b3fd62ea1a	994	((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) \|\| \
NYX	0:85b3fd62ea1a	995	((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)\|\| \
NYX	0:85b3fd62ea1a	996	((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) \|\| \
NYX	0:85b3fd62ea1a	997	((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) \|\| \
NYX	0:85b3fd62ea1a	998	((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) \|\| \
NYX	0:85b3fd62ea1a	999	((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)\|\| \
NYX	0:85b3fd62ea1a	1000	((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1))
NYX	0:85b3fd62ea1a	1001	#define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) \|\| \
NYX	0:85b3fd62ea1a	1002	((CLKOUT) == DFSDM1_CKOUT_DFSDM1))
NYX	0:85b3fd62ea1a	1003	#define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) \|\| \
NYX	0:85b3fd62ea1a	1004	((CLKOUT) == DFSDM2_CKOUT_DFSDM2))
NYX	0:85b3fd62ea1a	1005	#define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) \|\| \
NYX	0:85b3fd62ea1a	1006	((CLKIN) == DFSDM1_CKIN_PAD))
NYX	0:85b3fd62ea1a	1007	#define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) \|\| \
NYX	0:85b3fd62ea1a	1008	((CLKIN) == DFSDM2_CKIN_PAD))
NYX	0:85b3fd62ea1a	1009	#define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) \|\| \
NYX	0:85b3fd62ea1a	1010	((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) \|\| \
NYX	0:85b3fd62ea1a	1011	((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) \|\| \
NYX	0:85b3fd62ea1a	1012	((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) \|\| \
NYX	0:85b3fd62ea1a	1013	((CLK) <= 0x30U))
NYX	0:85b3fd62ea1a	1014
NYX	0:85b3fd62ea1a	1015	#define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) \|\| \
NYX	0:85b3fd62ea1a	1016	((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) \|\| \
NYX	0:85b3fd62ea1a	1017	((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5) \|\| \
NYX	0:85b3fd62ea1a	1018	((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1) \|\| \
NYX	0:85b3fd62ea1a	1019	((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6) \|\| \
NYX	0:85b3fd62ea1a	1020	((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) \|\| \
NYX	0:85b3fd62ea1a	1021	((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) \|\| \
NYX	0:85b3fd62ea1a	1022	((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)\|\| \
NYX	0:85b3fd62ea1a	1023	((CLK) <= 0x1E000U))
NYX	0:85b3fd62ea1a	1024
NYX	0:85b3fd62ea1a	1025	#define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )\|\| \
NYX	0:85b3fd62ea1a	1026	((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) \|\| \
NYX	0:85b3fd62ea1a	1027	((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) \|\| \
NYX	0:85b3fd62ea1a	1028	((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)\|\| \
NYX	0:85b3fd62ea1a	1029	((DISTRIBUTION) <= 0xCU))
NYX	0:85b3fd62ea1a	1030
NYX	0:85b3fd62ea1a	1031	#define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)\|\| \
NYX	0:85b3fd62ea1a	1032	((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)\|\| \
NYX	0:85b3fd62ea1a	1033	((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)\|\| \
NYX	0:85b3fd62ea1a	1034	((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)\|\| \
NYX	0:85b3fd62ea1a	1035	((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)\|\| \
NYX	0:85b3fd62ea1a	1036	((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)\|\| \
NYX	0:85b3fd62ea1a	1037	((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)\|\| \
NYX	0:85b3fd62ea1a	1038	((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)\|\| \
NYX	0:85b3fd62ea1a	1039	((DISTRIBUTION) <= 0x1D00U))
NYX	0:85b3fd62ea1a	1040	#endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */
NYX	0:85b3fd62ea1a	1041	/**
NYX	0:85b3fd62ea1a	1042	* @}
NYX	0:85b3fd62ea1a	1043	*/
NYX	0:85b3fd62ea1a	1044	/* End of private macros -----------------------------------------------------*/
NYX	0:85b3fd62ea1a	1045
NYX	0:85b3fd62ea1a	1046	/**
NYX	0:85b3fd62ea1a	1047	* @}
NYX	0:85b3fd62ea1a	1048	*/
NYX	0:85b3fd62ea1a	1049
NYX	0:85b3fd62ea1a	1050	/**
NYX	0:85b3fd62ea1a	1051	* @}
NYX	0:85b3fd62ea1a	1052	*/
NYX	0:85b3fd62ea1a	1053	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
NYX	0:85b3fd62ea1a	1054	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	1055	}
NYX	0:85b3fd62ea1a	1056	#endif
NYX	0:85b3fd62ea1a	1057
NYX	0:85b3fd62ea1a	1058	#endif /* __STM32F4xx_HAL_DFSDM_H */
NYX	0:85b3fd62ea1a	1059
NYX	0:85b3fd62ea1a	1060	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning