Takaaki Numai / mbed-dev

inport from local

Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_cortex.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of CORTEX HAL module.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 39 #ifndef __STM32F4xx_HAL_CORTEX_H
NYX 0:85b3fd62ea1a 40 #define __STM32F4xx_HAL_CORTEX_H
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 43 extern "C" {
NYX 0:85b3fd62ea1a 44 #endif
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 47 #include "stm32f4xx_hal_def.h"
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 50 * @{
NYX 0:85b3fd62ea1a 51 */
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 /** @addtogroup CORTEX
NYX 0:85b3fd62ea1a 54 * @{
NYX 0:85b3fd62ea1a 55 */
NYX 0:85b3fd62ea1a 56 /* Exported types ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 57 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
NYX 0:85b3fd62ea1a 58 * @{
NYX 0:85b3fd62ea1a 59 */
NYX 0:85b3fd62ea1a 60
NYX 0:85b3fd62ea1a 61 #if (__MPU_PRESENT == 1U)
NYX 0:85b3fd62ea1a 62 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
NYX 0:85b3fd62ea1a 63 * @brief MPU Region initialization structure
NYX 0:85b3fd62ea1a 64 * @{
NYX 0:85b3fd62ea1a 65 */
NYX 0:85b3fd62ea1a 66 typedef struct
NYX 0:85b3fd62ea1a 67 {
NYX 0:85b3fd62ea1a 68 uint8_t Enable; /*!< Specifies the status of the region.
NYX 0:85b3fd62ea1a 69 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
NYX 0:85b3fd62ea1a 70 uint8_t Number; /*!< Specifies the number of the region to protect.
NYX 0:85b3fd62ea1a 71 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
NYX 0:85b3fd62ea1a 72 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
NYX 0:85b3fd62ea1a 73 uint8_t Size; /*!< Specifies the size of the region to protect.
NYX 0:85b3fd62ea1a 74 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
NYX 0:85b3fd62ea1a 75 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
NYX 0:85b3fd62ea1a 76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
NYX 0:85b3fd62ea1a 77 uint8_t TypeExtField; /*!< Specifies the TEX field level.
NYX 0:85b3fd62ea1a 78 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
NYX 0:85b3fd62ea1a 79 uint8_t AccessPermission; /*!< Specifies the region access permission type.
NYX 0:85b3fd62ea1a 80 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
NYX 0:85b3fd62ea1a 81 uint8_t DisableExec; /*!< Specifies the instruction access status.
NYX 0:85b3fd62ea1a 82 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
NYX 0:85b3fd62ea1a 83 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
NYX 0:85b3fd62ea1a 84 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
NYX 0:85b3fd62ea1a 85 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
NYX 0:85b3fd62ea1a 86 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
NYX 0:85b3fd62ea1a 87 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
NYX 0:85b3fd62ea1a 88 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
NYX 0:85b3fd62ea1a 89 }MPU_Region_InitTypeDef;
NYX 0:85b3fd62ea1a 90 /**
NYX 0:85b3fd62ea1a 91 * @}
NYX 0:85b3fd62ea1a 92 */
NYX 0:85b3fd62ea1a 93 #endif /* __MPU_PRESENT */
NYX 0:85b3fd62ea1a 94
NYX 0:85b3fd62ea1a 95 /**
NYX 0:85b3fd62ea1a 96 * @}
NYX 0:85b3fd62ea1a 97 */
NYX 0:85b3fd62ea1a 98
NYX 0:85b3fd62ea1a 99 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
NYX 0:85b3fd62ea1a 102 * @{
NYX 0:85b3fd62ea1a 103 */
NYX 0:85b3fd62ea1a 104
NYX 0:85b3fd62ea1a 105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
NYX 0:85b3fd62ea1a 106 * @{
NYX 0:85b3fd62ea1a 107 */
NYX 0:85b3fd62ea1a 108 #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
NYX 0:85b3fd62ea1a 109 4 bits for subpriority */
NYX 0:85b3fd62ea1a 110 #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
NYX 0:85b3fd62ea1a 111 3 bits for subpriority */
NYX 0:85b3fd62ea1a 112 #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
NYX 0:85b3fd62ea1a 113 2 bits for subpriority */
NYX 0:85b3fd62ea1a 114 #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
NYX 0:85b3fd62ea1a 115 1 bits for subpriority */
NYX 0:85b3fd62ea1a 116 #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
NYX 0:85b3fd62ea1a 117 0 bits for subpriority */
NYX 0:85b3fd62ea1a 118 /**
NYX 0:85b3fd62ea1a 119 * @}
NYX 0:85b3fd62ea1a 120 */
NYX 0:85b3fd62ea1a 121
NYX 0:85b3fd62ea1a 122 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
NYX 0:85b3fd62ea1a 123 * @{
NYX 0:85b3fd62ea1a 124 */
NYX 0:85b3fd62ea1a 125 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
NYX 0:85b3fd62ea1a 126 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U
NYX 0:85b3fd62ea1a 127
NYX 0:85b3fd62ea1a 128 /**
NYX 0:85b3fd62ea1a 129 * @}
NYX 0:85b3fd62ea1a 130 */
NYX 0:85b3fd62ea1a 131
NYX 0:85b3fd62ea1a 132 #if (__MPU_PRESENT == 1)
NYX 0:85b3fd62ea1a 133 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
NYX 0:85b3fd62ea1a 134 * @{
NYX 0:85b3fd62ea1a 135 */
NYX 0:85b3fd62ea1a 136 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
NYX 0:85b3fd62ea1a 137 #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
NYX 0:85b3fd62ea1a 138 #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
NYX 0:85b3fd62ea1a 139 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
NYX 0:85b3fd62ea1a 140
NYX 0:85b3fd62ea1a 141 /**
NYX 0:85b3fd62ea1a 142 * @}
NYX 0:85b3fd62ea1a 143 */
NYX 0:85b3fd62ea1a 144
NYX 0:85b3fd62ea1a 145 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
NYX 0:85b3fd62ea1a 146 * @{
NYX 0:85b3fd62ea1a 147 */
NYX 0:85b3fd62ea1a 148 #define MPU_REGION_ENABLE ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 149 #define MPU_REGION_DISABLE ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 150 /**
NYX 0:85b3fd62ea1a 151 * @}
NYX 0:85b3fd62ea1a 152 */
NYX 0:85b3fd62ea1a 153
NYX 0:85b3fd62ea1a 154 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
NYX 0:85b3fd62ea1a 155 * @{
NYX 0:85b3fd62ea1a 156 */
NYX 0:85b3fd62ea1a 157 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 158 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 159 /**
NYX 0:85b3fd62ea1a 160 * @}
NYX 0:85b3fd62ea1a 161 */
NYX 0:85b3fd62ea1a 162
NYX 0:85b3fd62ea1a 163 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
NYX 0:85b3fd62ea1a 164 * @{
NYX 0:85b3fd62ea1a 165 */
NYX 0:85b3fd62ea1a 166 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 167 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 168 /**
NYX 0:85b3fd62ea1a 169 * @}
NYX 0:85b3fd62ea1a 170 */
NYX 0:85b3fd62ea1a 171
NYX 0:85b3fd62ea1a 172 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
NYX 0:85b3fd62ea1a 173 * @{
NYX 0:85b3fd62ea1a 174 */
NYX 0:85b3fd62ea1a 175 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 176 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 177 /**
NYX 0:85b3fd62ea1a 178 * @}
NYX 0:85b3fd62ea1a 179 */
NYX 0:85b3fd62ea1a 180
NYX 0:85b3fd62ea1a 181 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
NYX 0:85b3fd62ea1a 182 * @{
NYX 0:85b3fd62ea1a 183 */
NYX 0:85b3fd62ea1a 184 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 185 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 186 /**
NYX 0:85b3fd62ea1a 187 * @}
NYX 0:85b3fd62ea1a 188 */
NYX 0:85b3fd62ea1a 189
NYX 0:85b3fd62ea1a 190 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
NYX 0:85b3fd62ea1a 191 * @{
NYX 0:85b3fd62ea1a 192 */
NYX 0:85b3fd62ea1a 193 #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 194 #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 195 #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
NYX 0:85b3fd62ea1a 196 /**
NYX 0:85b3fd62ea1a 197 * @}
NYX 0:85b3fd62ea1a 198 */
NYX 0:85b3fd62ea1a 199
NYX 0:85b3fd62ea1a 200 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
NYX 0:85b3fd62ea1a 201 * @{
NYX 0:85b3fd62ea1a 202 */
NYX 0:85b3fd62ea1a 203 #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
NYX 0:85b3fd62ea1a 204 #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
NYX 0:85b3fd62ea1a 205 #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
NYX 0:85b3fd62ea1a 206 #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
NYX 0:85b3fd62ea1a 207 #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
NYX 0:85b3fd62ea1a 208 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
NYX 0:85b3fd62ea1a 209 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
NYX 0:85b3fd62ea1a 210 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
NYX 0:85b3fd62ea1a 211 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
NYX 0:85b3fd62ea1a 212 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
NYX 0:85b3fd62ea1a 213 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
NYX 0:85b3fd62ea1a 214 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
NYX 0:85b3fd62ea1a 215 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
NYX 0:85b3fd62ea1a 216 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
NYX 0:85b3fd62ea1a 217 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
NYX 0:85b3fd62ea1a 218 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
NYX 0:85b3fd62ea1a 219 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
NYX 0:85b3fd62ea1a 220 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
NYX 0:85b3fd62ea1a 221 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
NYX 0:85b3fd62ea1a 222 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
NYX 0:85b3fd62ea1a 223 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
NYX 0:85b3fd62ea1a 224 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
NYX 0:85b3fd62ea1a 225 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
NYX 0:85b3fd62ea1a 226 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
NYX 0:85b3fd62ea1a 227 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
NYX 0:85b3fd62ea1a 228 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
NYX 0:85b3fd62ea1a 229 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
NYX 0:85b3fd62ea1a 230 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
NYX 0:85b3fd62ea1a 231 /**
NYX 0:85b3fd62ea1a 232 * @}
NYX 0:85b3fd62ea1a 233 */
NYX 0:85b3fd62ea1a 234
NYX 0:85b3fd62ea1a 235 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
NYX 0:85b3fd62ea1a 236 * @{
NYX 0:85b3fd62ea1a 237 */
NYX 0:85b3fd62ea1a 238 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 239 #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 240 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
NYX 0:85b3fd62ea1a 241 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
NYX 0:85b3fd62ea1a 242 #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
NYX 0:85b3fd62ea1a 243 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
NYX 0:85b3fd62ea1a 244 /**
NYX 0:85b3fd62ea1a 245 * @}
NYX 0:85b3fd62ea1a 246 */
NYX 0:85b3fd62ea1a 247
NYX 0:85b3fd62ea1a 248 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
NYX 0:85b3fd62ea1a 249 * @{
NYX 0:85b3fd62ea1a 250 */
NYX 0:85b3fd62ea1a 251 #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
NYX 0:85b3fd62ea1a 252 #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
NYX 0:85b3fd62ea1a 253 #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
NYX 0:85b3fd62ea1a 254 #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
NYX 0:85b3fd62ea1a 255 #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
NYX 0:85b3fd62ea1a 256 #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
NYX 0:85b3fd62ea1a 257 #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
NYX 0:85b3fd62ea1a 258 #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
NYX 0:85b3fd62ea1a 259 /**
NYX 0:85b3fd62ea1a 260 * @}
NYX 0:85b3fd62ea1a 261 */
NYX 0:85b3fd62ea1a 262 #endif /* __MPU_PRESENT */
NYX 0:85b3fd62ea1a 263
NYX 0:85b3fd62ea1a 264 /**
NYX 0:85b3fd62ea1a 265 * @}
NYX 0:85b3fd62ea1a 266 */
NYX 0:85b3fd62ea1a 267
NYX 0:85b3fd62ea1a 268
NYX 0:85b3fd62ea1a 269 /* Exported Macros -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 270
NYX 0:85b3fd62ea1a 271 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 272 /** @addtogroup CORTEX_Exported_Functions
NYX 0:85b3fd62ea1a 273 * @{
NYX 0:85b3fd62ea1a 274 */
NYX 0:85b3fd62ea1a 275
NYX 0:85b3fd62ea1a 276 /** @addtogroup CORTEX_Exported_Functions_Group1
NYX 0:85b3fd62ea1a 277 * @{
NYX 0:85b3fd62ea1a 278 */
NYX 0:85b3fd62ea1a 279 /* Initialization and de-initialization functions *****************************/
NYX 0:85b3fd62ea1a 280 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
NYX 0:85b3fd62ea1a 281 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
NYX 0:85b3fd62ea1a 282 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
NYX 0:85b3fd62ea1a 283 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
NYX 0:85b3fd62ea1a 284 void HAL_NVIC_SystemReset(void);
NYX 0:85b3fd62ea1a 285 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
NYX 0:85b3fd62ea1a 286 /**
NYX 0:85b3fd62ea1a 287 * @}
NYX 0:85b3fd62ea1a 288 */
NYX 0:85b3fd62ea1a 289
NYX 0:85b3fd62ea1a 290 /** @addtogroup CORTEX_Exported_Functions_Group2
NYX 0:85b3fd62ea1a 291 * @{
NYX 0:85b3fd62ea1a 292 */
NYX 0:85b3fd62ea1a 293 /* Peripheral Control functions ***********************************************/
NYX 0:85b3fd62ea1a 294 uint32_t HAL_NVIC_GetPriorityGrouping(void);
NYX 0:85b3fd62ea1a 295 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
NYX 0:85b3fd62ea1a 296 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
NYX 0:85b3fd62ea1a 297 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
NYX 0:85b3fd62ea1a 298 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
NYX 0:85b3fd62ea1a 299 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
NYX 0:85b3fd62ea1a 300 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
NYX 0:85b3fd62ea1a 301 void HAL_SYSTICK_IRQHandler(void);
NYX 0:85b3fd62ea1a 302 void HAL_SYSTICK_Callback(void);
NYX 0:85b3fd62ea1a 303
NYX 0:85b3fd62ea1a 304 #if (__MPU_PRESENT == 1U)
NYX 0:85b3fd62ea1a 305 void HAL_MPU_Enable(uint32_t MPU_Control);
NYX 0:85b3fd62ea1a 306 void HAL_MPU_Disable(void);
NYX 0:85b3fd62ea1a 307 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
NYX 0:85b3fd62ea1a 308 #endif /* __MPU_PRESENT */
NYX 0:85b3fd62ea1a 309 /**
NYX 0:85b3fd62ea1a 310 * @}
NYX 0:85b3fd62ea1a 311 */
NYX 0:85b3fd62ea1a 312
NYX 0:85b3fd62ea1a 313 /**
NYX 0:85b3fd62ea1a 314 * @}
NYX 0:85b3fd62ea1a 315 */
NYX 0:85b3fd62ea1a 316
NYX 0:85b3fd62ea1a 317 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 318 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 319 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 320 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 321 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
NYX 0:85b3fd62ea1a 322 * @{
NYX 0:85b3fd62ea1a 323 */
NYX 0:85b3fd62ea1a 324 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
NYX 0:85b3fd62ea1a 325 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
NYX 0:85b3fd62ea1a 326 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
NYX 0:85b3fd62ea1a 327 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
NYX 0:85b3fd62ea1a 328 ((GROUP) == NVIC_PRIORITYGROUP_4))
NYX 0:85b3fd62ea1a 329
NYX 0:85b3fd62ea1a 330 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
NYX 0:85b3fd62ea1a 331
NYX 0:85b3fd62ea1a 332 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
NYX 0:85b3fd62ea1a 333
NYX 0:85b3fd62ea1a 334 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
NYX 0:85b3fd62ea1a 335
NYX 0:85b3fd62ea1a 336 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
NYX 0:85b3fd62ea1a 337 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
NYX 0:85b3fd62ea1a 338
NYX 0:85b3fd62ea1a 339 #if (__MPU_PRESENT == 1U)
NYX 0:85b3fd62ea1a 340 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
NYX 0:85b3fd62ea1a 341 ((STATE) == MPU_REGION_DISABLE))
NYX 0:85b3fd62ea1a 342
NYX 0:85b3fd62ea1a 343 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
NYX 0:85b3fd62ea1a 344 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
NYX 0:85b3fd62ea1a 345
NYX 0:85b3fd62ea1a 346 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
NYX 0:85b3fd62ea1a 347 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
NYX 0:85b3fd62ea1a 348
NYX 0:85b3fd62ea1a 349 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
NYX 0:85b3fd62ea1a 350 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
NYX 0:85b3fd62ea1a 351
NYX 0:85b3fd62ea1a 352 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
NYX 0:85b3fd62ea1a 353 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
NYX 0:85b3fd62ea1a 354
NYX 0:85b3fd62ea1a 355 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
NYX 0:85b3fd62ea1a 356 ((TYPE) == MPU_TEX_LEVEL1) || \
NYX 0:85b3fd62ea1a 357 ((TYPE) == MPU_TEX_LEVEL2))
NYX 0:85b3fd62ea1a 358
NYX 0:85b3fd62ea1a 359 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
NYX 0:85b3fd62ea1a 360 ((TYPE) == MPU_REGION_PRIV_RW) || \
NYX 0:85b3fd62ea1a 361 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
NYX 0:85b3fd62ea1a 362 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
NYX 0:85b3fd62ea1a 363 ((TYPE) == MPU_REGION_PRIV_RO) || \
NYX 0:85b3fd62ea1a 364 ((TYPE) == MPU_REGION_PRIV_RO_URO))
NYX 0:85b3fd62ea1a 365
NYX 0:85b3fd62ea1a 366 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
NYX 0:85b3fd62ea1a 367 ((NUMBER) == MPU_REGION_NUMBER1) || \
NYX 0:85b3fd62ea1a 368 ((NUMBER) == MPU_REGION_NUMBER2) || \
NYX 0:85b3fd62ea1a 369 ((NUMBER) == MPU_REGION_NUMBER3) || \
NYX 0:85b3fd62ea1a 370 ((NUMBER) == MPU_REGION_NUMBER4) || \
NYX 0:85b3fd62ea1a 371 ((NUMBER) == MPU_REGION_NUMBER5) || \
NYX 0:85b3fd62ea1a 372 ((NUMBER) == MPU_REGION_NUMBER6) || \
NYX 0:85b3fd62ea1a 373 ((NUMBER) == MPU_REGION_NUMBER7))
NYX 0:85b3fd62ea1a 374
NYX 0:85b3fd62ea1a 375 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
NYX 0:85b3fd62ea1a 376 ((SIZE) == MPU_REGION_SIZE_64B) || \
NYX 0:85b3fd62ea1a 377 ((SIZE) == MPU_REGION_SIZE_128B) || \
NYX 0:85b3fd62ea1a 378 ((SIZE) == MPU_REGION_SIZE_256B) || \
NYX 0:85b3fd62ea1a 379 ((SIZE) == MPU_REGION_SIZE_512B) || \
NYX 0:85b3fd62ea1a 380 ((SIZE) == MPU_REGION_SIZE_1KB) || \
NYX 0:85b3fd62ea1a 381 ((SIZE) == MPU_REGION_SIZE_2KB) || \
NYX 0:85b3fd62ea1a 382 ((SIZE) == MPU_REGION_SIZE_4KB) || \
NYX 0:85b3fd62ea1a 383 ((SIZE) == MPU_REGION_SIZE_8KB) || \
NYX 0:85b3fd62ea1a 384 ((SIZE) == MPU_REGION_SIZE_16KB) || \
NYX 0:85b3fd62ea1a 385 ((SIZE) == MPU_REGION_SIZE_32KB) || \
NYX 0:85b3fd62ea1a 386 ((SIZE) == MPU_REGION_SIZE_64KB) || \
NYX 0:85b3fd62ea1a 387 ((SIZE) == MPU_REGION_SIZE_128KB) || \
NYX 0:85b3fd62ea1a 388 ((SIZE) == MPU_REGION_SIZE_256KB) || \
NYX 0:85b3fd62ea1a 389 ((SIZE) == MPU_REGION_SIZE_512KB) || \
NYX 0:85b3fd62ea1a 390 ((SIZE) == MPU_REGION_SIZE_1MB) || \
NYX 0:85b3fd62ea1a 391 ((SIZE) == MPU_REGION_SIZE_2MB) || \
NYX 0:85b3fd62ea1a 392 ((SIZE) == MPU_REGION_SIZE_4MB) || \
NYX 0:85b3fd62ea1a 393 ((SIZE) == MPU_REGION_SIZE_8MB) || \
NYX 0:85b3fd62ea1a 394 ((SIZE) == MPU_REGION_SIZE_16MB) || \
NYX 0:85b3fd62ea1a 395 ((SIZE) == MPU_REGION_SIZE_32MB) || \
NYX 0:85b3fd62ea1a 396 ((SIZE) == MPU_REGION_SIZE_64MB) || \
NYX 0:85b3fd62ea1a 397 ((SIZE) == MPU_REGION_SIZE_128MB) || \
NYX 0:85b3fd62ea1a 398 ((SIZE) == MPU_REGION_SIZE_256MB) || \
NYX 0:85b3fd62ea1a 399 ((SIZE) == MPU_REGION_SIZE_512MB) || \
NYX 0:85b3fd62ea1a 400 ((SIZE) == MPU_REGION_SIZE_1GB) || \
NYX 0:85b3fd62ea1a 401 ((SIZE) == MPU_REGION_SIZE_2GB) || \
NYX 0:85b3fd62ea1a 402 ((SIZE) == MPU_REGION_SIZE_4GB))
NYX 0:85b3fd62ea1a 403
NYX 0:85b3fd62ea1a 404 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
NYX 0:85b3fd62ea1a 405 #endif /* __MPU_PRESENT */
NYX 0:85b3fd62ea1a 406
NYX 0:85b3fd62ea1a 407 /**
NYX 0:85b3fd62ea1a 408 * @}
NYX 0:85b3fd62ea1a 409 */
NYX 0:85b3fd62ea1a 410
NYX 0:85b3fd62ea1a 411 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 412
NYX 0:85b3fd62ea1a 413 /**
NYX 0:85b3fd62ea1a 414 * @}
NYX 0:85b3fd62ea1a 415 */
NYX 0:85b3fd62ea1a 416
NYX 0:85b3fd62ea1a 417 /**
NYX 0:85b3fd62ea1a 418 * @}
NYX 0:85b3fd62ea1a 419 */
NYX 0:85b3fd62ea1a 420
NYX 0:85b3fd62ea1a 421 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 422 }
NYX 0:85b3fd62ea1a 423 #endif
NYX 0:85b3fd62ea1a 424
NYX 0:85b3fd62ea1a 425 #endif /* __STM32F4xx_HAL_CORTEX_H */
NYX 0:85b3fd62ea1a 426
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/