Takaaki Numai / mbed-dev

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_cortex.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief CORTEX HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 9 * functionalities of the CORTEX:
NYX 0:85b3fd62ea1a 10 * + Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 11 * + Peripheral Control functions
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 @verbatim
NYX 0:85b3fd62ea1a 14 ==============================================================================
NYX 0:85b3fd62ea1a 15 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 16 ==============================================================================
NYX 0:85b3fd62ea1a 17
NYX 0:85b3fd62ea1a 18 [..]
NYX 0:85b3fd62ea1a 19 *** How to configure Interrupts using CORTEX HAL driver ***
NYX 0:85b3fd62ea1a 20 ===========================================================
NYX 0:85b3fd62ea1a 21 [..]
NYX 0:85b3fd62ea1a 22 This section provides functions allowing to configure the NVIC interrupts (IRQ).
NYX 0:85b3fd62ea1a 23 The Cortex-M4 exceptions are managed by CMSIS functions.
NYX 0:85b3fd62ea1a 24
NYX 0:85b3fd62ea1a 25 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
NYX 0:85b3fd62ea1a 26 function according to the following table.
NYX 0:85b3fd62ea1a 27 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
NYX 0:85b3fd62ea1a 28 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
NYX 0:85b3fd62ea1a 29 (#) please refer to programming manual for details in how to configure priority.
NYX 0:85b3fd62ea1a 30
NYX 0:85b3fd62ea1a 31 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
NYX 0:85b3fd62ea1a 32 The pending IRQ priority will be managed only by the sub priority.
NYX 0:85b3fd62ea1a 33
NYX 0:85b3fd62ea1a 34 -@- IRQ priority order (sorted by highest to lowest priority):
NYX 0:85b3fd62ea1a 35 (+@) Lowest preemption priority
NYX 0:85b3fd62ea1a 36 (+@) Lowest sub priority
NYX 0:85b3fd62ea1a 37 (+@) Lowest hardware priority (IRQ number)
NYX 0:85b3fd62ea1a 38
NYX 0:85b3fd62ea1a 39 [..]
NYX 0:85b3fd62ea1a 40 *** How to configure Systick using CORTEX HAL driver ***
NYX 0:85b3fd62ea1a 41 ========================================================
NYX 0:85b3fd62ea1a 42 [..]
NYX 0:85b3fd62ea1a 43 Setup SysTick Timer for time base.
NYX 0:85b3fd62ea1a 44
NYX 0:85b3fd62ea1a 45 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
NYX 0:85b3fd62ea1a 46 is a CMSIS function that:
NYX 0:85b3fd62ea1a 47 (++) Configures the SysTick Reload register with value passed as function parameter.
NYX 0:85b3fd62ea1a 48 (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
NYX 0:85b3fd62ea1a 49 (++) Resets the SysTick Counter register.
NYX 0:85b3fd62ea1a 50 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
NYX 0:85b3fd62ea1a 51 (++) Enables the SysTick Interrupt.
NYX 0:85b3fd62ea1a 52 (++) Starts the SysTick Counter.
NYX 0:85b3fd62ea1a 53
NYX 0:85b3fd62ea1a 54 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
NYX 0:85b3fd62ea1a 55 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
NYX 0:85b3fd62ea1a 56 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
NYX 0:85b3fd62ea1a 57 inside the stm32f4xx_hal_cortex.h file.
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 (+) You can change the SysTick IRQ priority by calling the
NYX 0:85b3fd62ea1a 60 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
NYX 0:85b3fd62ea1a 61 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
NYX 0:85b3fd62ea1a 62
NYX 0:85b3fd62ea1a 63 (+) To adjust the SysTick time base, use the following formula:
NYX 0:85b3fd62ea1a 64
NYX 0:85b3fd62ea1a 65 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
NYX 0:85b3fd62ea1a 66 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
NYX 0:85b3fd62ea1a 67 (++) Reload Value should not exceed 0xFFFFFF
NYX 0:85b3fd62ea1a 68
NYX 0:85b3fd62ea1a 69 @endverbatim
NYX 0:85b3fd62ea1a 70 ******************************************************************************
NYX 0:85b3fd62ea1a 71 * @attention
NYX 0:85b3fd62ea1a 72 *
NYX 0:85b3fd62ea1a 73 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 74 *
NYX 0:85b3fd62ea1a 75 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 76 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 77 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 78 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 79 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 80 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 81 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 83 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 84 * without specific prior written permission.
NYX 0:85b3fd62ea1a 85 *
NYX 0:85b3fd62ea1a 86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 96 *
NYX 0:85b3fd62ea1a 97 ******************************************************************************
NYX 0:85b3fd62ea1a 98 */
NYX 0:85b3fd62ea1a 99
NYX 0:85b3fd62ea1a 100 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 101 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 102
NYX 0:85b3fd62ea1a 103 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 104 * @{
NYX 0:85b3fd62ea1a 105 */
NYX 0:85b3fd62ea1a 106
NYX 0:85b3fd62ea1a 107 /** @defgroup CORTEX CORTEX
NYX 0:85b3fd62ea1a 108 * @brief CORTEX HAL module driver
NYX 0:85b3fd62ea1a 109 * @{
NYX 0:85b3fd62ea1a 110 */
NYX 0:85b3fd62ea1a 111
NYX 0:85b3fd62ea1a 112 #ifdef HAL_CORTEX_MODULE_ENABLED
NYX 0:85b3fd62ea1a 113
NYX 0:85b3fd62ea1a 114 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 115 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 116 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 117 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 118 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 119 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 120
NYX 0:85b3fd62ea1a 121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
NYX 0:85b3fd62ea1a 122 * @{
NYX 0:85b3fd62ea1a 123 */
NYX 0:85b3fd62ea1a 124
NYX 0:85b3fd62ea1a 125
NYX 0:85b3fd62ea1a 126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 127 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 128 *
NYX 0:85b3fd62ea1a 129 @verbatim
NYX 0:85b3fd62ea1a 130 ==============================================================================
NYX 0:85b3fd62ea1a 131 ##### Initialization and de-initialization functions #####
NYX 0:85b3fd62ea1a 132 ==============================================================================
NYX 0:85b3fd62ea1a 133 [..]
NYX 0:85b3fd62ea1a 134 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
NYX 0:85b3fd62ea1a 135 Systick functionalities
NYX 0:85b3fd62ea1a 136
NYX 0:85b3fd62ea1a 137 @endverbatim
NYX 0:85b3fd62ea1a 138 * @{
NYX 0:85b3fd62ea1a 139 */
NYX 0:85b3fd62ea1a 140
NYX 0:85b3fd62ea1a 141
NYX 0:85b3fd62ea1a 142 /**
NYX 0:85b3fd62ea1a 143 * @brief Sets the priority grouping field (preemption priority and subpriority)
NYX 0:85b3fd62ea1a 144 * using the required unlock sequence.
NYX 0:85b3fd62ea1a 145 * @param PriorityGroup: The priority grouping bits length.
NYX 0:85b3fd62ea1a 146 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 147 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
NYX 0:85b3fd62ea1a 148 * 4 bits for subpriority
NYX 0:85b3fd62ea1a 149 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
NYX 0:85b3fd62ea1a 150 * 3 bits for subpriority
NYX 0:85b3fd62ea1a 151 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
NYX 0:85b3fd62ea1a 152 * 2 bits for subpriority
NYX 0:85b3fd62ea1a 153 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
NYX 0:85b3fd62ea1a 154 * 1 bits for subpriority
NYX 0:85b3fd62ea1a 155 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
NYX 0:85b3fd62ea1a 156 * 0 bits for subpriority
NYX 0:85b3fd62ea1a 157 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
NYX 0:85b3fd62ea1a 158 * The pending IRQ priority will be managed only by the subpriority.
NYX 0:85b3fd62ea1a 159 * @retval None
NYX 0:85b3fd62ea1a 160 */
NYX 0:85b3fd62ea1a 161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
NYX 0:85b3fd62ea1a 162 {
NYX 0:85b3fd62ea1a 163 /* Check the parameters */
NYX 0:85b3fd62ea1a 164 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
NYX 0:85b3fd62ea1a 165
NYX 0:85b3fd62ea1a 166 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NYX 0:85b3fd62ea1a 167 NVIC_SetPriorityGrouping(PriorityGroup);
NYX 0:85b3fd62ea1a 168 }
NYX 0:85b3fd62ea1a 169
NYX 0:85b3fd62ea1a 170 /**
NYX 0:85b3fd62ea1a 171 * @brief Sets the priority of an interrupt.
NYX 0:85b3fd62ea1a 172 * @param IRQn: External interrupt number.
NYX 0:85b3fd62ea1a 173 * This parameter can be an enumerator of IRQn_Type enumeration
NYX 0:85b3fd62ea1a 174 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
NYX 0:85b3fd62ea1a 175 * @param PreemptPriority: The preemption priority for the IRQn channel.
NYX 0:85b3fd62ea1a 176 * This parameter can be a value between 0 and 15
NYX 0:85b3fd62ea1a 177 * A lower priority value indicates a higher priority
NYX 0:85b3fd62ea1a 178 * @param SubPriority: the subpriority level for the IRQ channel.
NYX 0:85b3fd62ea1a 179 * This parameter can be a value between 0 and 15
NYX 0:85b3fd62ea1a 180 * A lower priority value indicates a higher priority.
NYX 0:85b3fd62ea1a 181 * @retval None
NYX 0:85b3fd62ea1a 182 */
NYX 0:85b3fd62ea1a 183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
NYX 0:85b3fd62ea1a 184 {
NYX 0:85b3fd62ea1a 185 uint32_t prioritygroup = 0x00U;
NYX 0:85b3fd62ea1a 186
NYX 0:85b3fd62ea1a 187 /* Check the parameters */
NYX 0:85b3fd62ea1a 188 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
NYX 0:85b3fd62ea1a 189 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NYX 0:85b3fd62ea1a 190
NYX 0:85b3fd62ea1a 191 prioritygroup = NVIC_GetPriorityGrouping();
NYX 0:85b3fd62ea1a 192
NYX 0:85b3fd62ea1a 193 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
NYX 0:85b3fd62ea1a 194 }
NYX 0:85b3fd62ea1a 195
NYX 0:85b3fd62ea1a 196 /**
NYX 0:85b3fd62ea1a 197 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 198 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
NYX 0:85b3fd62ea1a 199 * function should be called before.
NYX 0:85b3fd62ea1a 200 * @param IRQn External interrupt number.
NYX 0:85b3fd62ea1a 201 * This parameter can be an enumerator of IRQn_Type enumeration
NYX 0:85b3fd62ea1a 202 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
NYX 0:85b3fd62ea1a 203 * @retval None
NYX 0:85b3fd62ea1a 204 */
NYX 0:85b3fd62ea1a 205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 206 {
NYX 0:85b3fd62ea1a 207 /* Check the parameters */
NYX 0:85b3fd62ea1a 208 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
NYX 0:85b3fd62ea1a 209
NYX 0:85b3fd62ea1a 210 /* Enable interrupt */
NYX 0:85b3fd62ea1a 211 NVIC_EnableIRQ(IRQn);
NYX 0:85b3fd62ea1a 212 }
NYX 0:85b3fd62ea1a 213
NYX 0:85b3fd62ea1a 214 /**
NYX 0:85b3fd62ea1a 215 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 216 * @param IRQn External interrupt number.
NYX 0:85b3fd62ea1a 217 * This parameter can be an enumerator of IRQn_Type enumeration
NYX 0:85b3fd62ea1a 218 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
NYX 0:85b3fd62ea1a 219 * @retval None
NYX 0:85b3fd62ea1a 220 */
NYX 0:85b3fd62ea1a 221 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 222 {
NYX 0:85b3fd62ea1a 223 /* Check the parameters */
NYX 0:85b3fd62ea1a 224 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
NYX 0:85b3fd62ea1a 225
NYX 0:85b3fd62ea1a 226 /* Disable interrupt */
NYX 0:85b3fd62ea1a 227 NVIC_DisableIRQ(IRQn);
NYX 0:85b3fd62ea1a 228 }
NYX 0:85b3fd62ea1a 229
NYX 0:85b3fd62ea1a 230 /**
NYX 0:85b3fd62ea1a 231 * @brief Initiates a system reset request to reset the MCU.
NYX 0:85b3fd62ea1a 232 * @retval None
NYX 0:85b3fd62ea1a 233 */
NYX 0:85b3fd62ea1a 234 void HAL_NVIC_SystemReset(void)
NYX 0:85b3fd62ea1a 235 {
NYX 0:85b3fd62ea1a 236 /* System Reset */
NYX 0:85b3fd62ea1a 237 NVIC_SystemReset();
NYX 0:85b3fd62ea1a 238 }
NYX 0:85b3fd62ea1a 239
NYX 0:85b3fd62ea1a 240 /**
NYX 0:85b3fd62ea1a 241 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
NYX 0:85b3fd62ea1a 242 * Counter is in free running mode to generate periodic interrupts.
NYX 0:85b3fd62ea1a 243 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
NYX 0:85b3fd62ea1a 244 * @retval status: - 0 Function succeeded.
NYX 0:85b3fd62ea1a 245 * - 1 Function failed.
NYX 0:85b3fd62ea1a 246 */
NYX 0:85b3fd62ea1a 247 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
NYX 0:85b3fd62ea1a 248 {
NYX 0:85b3fd62ea1a 249 return SysTick_Config(TicksNumb);
NYX 0:85b3fd62ea1a 250 }
NYX 0:85b3fd62ea1a 251 /**
NYX 0:85b3fd62ea1a 252 * @}
NYX 0:85b3fd62ea1a 253 */
NYX 0:85b3fd62ea1a 254
NYX 0:85b3fd62ea1a 255 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
NYX 0:85b3fd62ea1a 256 * @brief Cortex control functions
NYX 0:85b3fd62ea1a 257 *
NYX 0:85b3fd62ea1a 258 @verbatim
NYX 0:85b3fd62ea1a 259 ==============================================================================
NYX 0:85b3fd62ea1a 260 ##### Peripheral Control functions #####
NYX 0:85b3fd62ea1a 261 ==============================================================================
NYX 0:85b3fd62ea1a 262 [..]
NYX 0:85b3fd62ea1a 263 This subsection provides a set of functions allowing to control the CORTEX
NYX 0:85b3fd62ea1a 264 (NVIC, SYSTICK, MPU) functionalities.
NYX 0:85b3fd62ea1a 265
NYX 0:85b3fd62ea1a 266
NYX 0:85b3fd62ea1a 267 @endverbatim
NYX 0:85b3fd62ea1a 268 * @{
NYX 0:85b3fd62ea1a 269 */
NYX 0:85b3fd62ea1a 270
NYX 0:85b3fd62ea1a 271 #if (__MPU_PRESENT == 1U)
NYX 0:85b3fd62ea1a 272 /**
NYX 0:85b3fd62ea1a 273 * @brief Disables the MPU
NYX 0:85b3fd62ea1a 274 * @retval None
NYX 0:85b3fd62ea1a 275 */
NYX 0:85b3fd62ea1a 276 void HAL_MPU_Disable(void)
NYX 0:85b3fd62ea1a 277 {
NYX 0:85b3fd62ea1a 278 /* Make sure outstanding transfers are done */
NYX 0:85b3fd62ea1a 279 __DMB();
NYX 0:85b3fd62ea1a 280
NYX 0:85b3fd62ea1a 281 /* Disable fault exceptions */
NYX 0:85b3fd62ea1a 282 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
NYX 0:85b3fd62ea1a 283
NYX 0:85b3fd62ea1a 284 /* Disable the MPU and clear the control register*/
NYX 0:85b3fd62ea1a 285 MPU->CTRL = 0U;
NYX 0:85b3fd62ea1a 286 }
NYX 0:85b3fd62ea1a 287
NYX 0:85b3fd62ea1a 288 /**
NYX 0:85b3fd62ea1a 289 * @brief Enable the MPU.
NYX 0:85b3fd62ea1a 290 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
NYX 0:85b3fd62ea1a 291 * NMI, FAULTMASK and privileged access to the default memory
NYX 0:85b3fd62ea1a 292 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 293 * @arg MPU_HFNMI_PRIVDEF_NONE
NYX 0:85b3fd62ea1a 294 * @arg MPU_HARDFAULT_NMI
NYX 0:85b3fd62ea1a 295 * @arg MPU_PRIVILEGED_DEFAULT
NYX 0:85b3fd62ea1a 296 * @arg MPU_HFNMI_PRIVDEF
NYX 0:85b3fd62ea1a 297 * @retval None
NYX 0:85b3fd62ea1a 298 */
NYX 0:85b3fd62ea1a 299 void HAL_MPU_Enable(uint32_t MPU_Control)
NYX 0:85b3fd62ea1a 300 {
NYX 0:85b3fd62ea1a 301 /* Enable the MPU */
NYX 0:85b3fd62ea1a 302 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
NYX 0:85b3fd62ea1a 303
NYX 0:85b3fd62ea1a 304 /* Enable fault exceptions */
NYX 0:85b3fd62ea1a 305 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
NYX 0:85b3fd62ea1a 306
NYX 0:85b3fd62ea1a 307 /* Ensure MPU setting take effects */
NYX 0:85b3fd62ea1a 308 __DSB();
NYX 0:85b3fd62ea1a 309 __ISB();
NYX 0:85b3fd62ea1a 310 }
NYX 0:85b3fd62ea1a 311
NYX 0:85b3fd62ea1a 312 /**
NYX 0:85b3fd62ea1a 313 * @brief Initializes and configures the Region and the memory to be protected.
NYX 0:85b3fd62ea1a 314 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
NYX 0:85b3fd62ea1a 315 * the initialization and configuration information.
NYX 0:85b3fd62ea1a 316 * @retval None
NYX 0:85b3fd62ea1a 317 */
NYX 0:85b3fd62ea1a 318 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
NYX 0:85b3fd62ea1a 319 {
NYX 0:85b3fd62ea1a 320 /* Check the parameters */
NYX 0:85b3fd62ea1a 321 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
NYX 0:85b3fd62ea1a 322 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
NYX 0:85b3fd62ea1a 323
NYX 0:85b3fd62ea1a 324 /* Set the Region number */
NYX 0:85b3fd62ea1a 325 MPU->RNR = MPU_Init->Number;
NYX 0:85b3fd62ea1a 326
NYX 0:85b3fd62ea1a 327 if ((MPU_Init->Enable) != RESET)
NYX 0:85b3fd62ea1a 328 {
NYX 0:85b3fd62ea1a 329 /* Check the parameters */
NYX 0:85b3fd62ea1a 330 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
NYX 0:85b3fd62ea1a 331 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
NYX 0:85b3fd62ea1a 332 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
NYX 0:85b3fd62ea1a 333 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
NYX 0:85b3fd62ea1a 334 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
NYX 0:85b3fd62ea1a 335 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
NYX 0:85b3fd62ea1a 336 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
NYX 0:85b3fd62ea1a 337 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
NYX 0:85b3fd62ea1a 338
NYX 0:85b3fd62ea1a 339 MPU->RBAR = MPU_Init->BaseAddress;
NYX 0:85b3fd62ea1a 340 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
NYX 0:85b3fd62ea1a 341 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
NYX 0:85b3fd62ea1a 342 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
NYX 0:85b3fd62ea1a 343 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
NYX 0:85b3fd62ea1a 344 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
NYX 0:85b3fd62ea1a 345 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
NYX 0:85b3fd62ea1a 346 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
NYX 0:85b3fd62ea1a 347 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
NYX 0:85b3fd62ea1a 348 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
NYX 0:85b3fd62ea1a 349 }
NYX 0:85b3fd62ea1a 350 else
NYX 0:85b3fd62ea1a 351 {
NYX 0:85b3fd62ea1a 352 MPU->RBAR = 0x00U;
NYX 0:85b3fd62ea1a 353 MPU->RASR = 0x00U;
NYX 0:85b3fd62ea1a 354 }
NYX 0:85b3fd62ea1a 355 }
NYX 0:85b3fd62ea1a 356 #endif /* __MPU_PRESENT */
NYX 0:85b3fd62ea1a 357
NYX 0:85b3fd62ea1a 358 /**
NYX 0:85b3fd62ea1a 359 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
NYX 0:85b3fd62ea1a 360 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
NYX 0:85b3fd62ea1a 361 */
NYX 0:85b3fd62ea1a 362 uint32_t HAL_NVIC_GetPriorityGrouping(void)
NYX 0:85b3fd62ea1a 363 {
NYX 0:85b3fd62ea1a 364 /* Get the PRIGROUP[10:8] field value */
NYX 0:85b3fd62ea1a 365 return NVIC_GetPriorityGrouping();
NYX 0:85b3fd62ea1a 366 }
NYX 0:85b3fd62ea1a 367
NYX 0:85b3fd62ea1a 368 /**
NYX 0:85b3fd62ea1a 369 * @brief Gets the priority of an interrupt.
NYX 0:85b3fd62ea1a 370 * @param IRQn: External interrupt number.
NYX 0:85b3fd62ea1a 371 * This parameter can be an enumerator of IRQn_Type enumeration
NYX 0:85b3fd62ea1a 372 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
NYX 0:85b3fd62ea1a 373 * @param PriorityGroup: the priority grouping bits length.
NYX 0:85b3fd62ea1a 374 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 375 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
NYX 0:85b3fd62ea1a 376 * 4 bits for subpriority
NYX 0:85b3fd62ea1a 377 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
NYX 0:85b3fd62ea1a 378 * 3 bits for subpriority
NYX 0:85b3fd62ea1a 379 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
NYX 0:85b3fd62ea1a 380 * 2 bits for subpriority
NYX 0:85b3fd62ea1a 381 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
NYX 0:85b3fd62ea1a 382 * 1 bits for subpriority
NYX 0:85b3fd62ea1a 383 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
NYX 0:85b3fd62ea1a 384 * 0 bits for subpriority
NYX 0:85b3fd62ea1a 385 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
NYX 0:85b3fd62ea1a 386 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
NYX 0:85b3fd62ea1a 387 * @retval None
NYX 0:85b3fd62ea1a 388 */
NYX 0:85b3fd62ea1a 389 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
NYX 0:85b3fd62ea1a 390 {
NYX 0:85b3fd62ea1a 391 /* Check the parameters */
NYX 0:85b3fd62ea1a 392 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
NYX 0:85b3fd62ea1a 393 /* Get priority for Cortex-M system or device specific interrupts */
NYX 0:85b3fd62ea1a 394 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
NYX 0:85b3fd62ea1a 395 }
NYX 0:85b3fd62ea1a 396
NYX 0:85b3fd62ea1a 397 /**
NYX 0:85b3fd62ea1a 398 * @brief Sets Pending bit of an external interrupt.
NYX 0:85b3fd62ea1a 399 * @param IRQn External interrupt number
NYX 0:85b3fd62ea1a 400 * This parameter can be an enumerator of IRQn_Type enumeration
NYX 0:85b3fd62ea1a 401 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
NYX 0:85b3fd62ea1a 402 * @retval None
NYX 0:85b3fd62ea1a 403 */
NYX 0:85b3fd62ea1a 404 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 405 {
NYX 0:85b3fd62ea1a 406 /* Check the parameters */
NYX 0:85b3fd62ea1a 407 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
NYX 0:85b3fd62ea1a 408
NYX 0:85b3fd62ea1a 409 /* Set interrupt pending */
NYX 0:85b3fd62ea1a 410 NVIC_SetPendingIRQ(IRQn);
NYX 0:85b3fd62ea1a 411 }
NYX 0:85b3fd62ea1a 412
NYX 0:85b3fd62ea1a 413 /**
NYX 0:85b3fd62ea1a 414 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
NYX 0:85b3fd62ea1a 415 * and returns the pending bit for the specified interrupt).
NYX 0:85b3fd62ea1a 416 * @param IRQn External interrupt number.
NYX 0:85b3fd62ea1a 417 * This parameter can be an enumerator of IRQn_Type enumeration
NYX 0:85b3fd62ea1a 418 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
NYX 0:85b3fd62ea1a 419 * @retval status: - 0 Interrupt status is not pending.
NYX 0:85b3fd62ea1a 420 * - 1 Interrupt status is pending.
NYX 0:85b3fd62ea1a 421 */
NYX 0:85b3fd62ea1a 422 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 423 {
NYX 0:85b3fd62ea1a 424 /* Check the parameters */
NYX 0:85b3fd62ea1a 425 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
NYX 0:85b3fd62ea1a 426
NYX 0:85b3fd62ea1a 427 /* Return 1 if pending else 0 */
NYX 0:85b3fd62ea1a 428 return NVIC_GetPendingIRQ(IRQn);
NYX 0:85b3fd62ea1a 429 }
NYX 0:85b3fd62ea1a 430
NYX 0:85b3fd62ea1a 431 /**
NYX 0:85b3fd62ea1a 432 * @brief Clears the pending bit of an external interrupt.
NYX 0:85b3fd62ea1a 433 * @param IRQn External interrupt number.
NYX 0:85b3fd62ea1a 434 * This parameter can be an enumerator of IRQn_Type enumeration
NYX 0:85b3fd62ea1a 435 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
NYX 0:85b3fd62ea1a 436 * @retval None
NYX 0:85b3fd62ea1a 437 */
NYX 0:85b3fd62ea1a 438 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 439 {
NYX 0:85b3fd62ea1a 440 /* Check the parameters */
NYX 0:85b3fd62ea1a 441 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
NYX 0:85b3fd62ea1a 442
NYX 0:85b3fd62ea1a 443 /* Clear pending interrupt */
NYX 0:85b3fd62ea1a 444 NVIC_ClearPendingIRQ(IRQn);
NYX 0:85b3fd62ea1a 445 }
NYX 0:85b3fd62ea1a 446
NYX 0:85b3fd62ea1a 447 /**
NYX 0:85b3fd62ea1a 448 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
NYX 0:85b3fd62ea1a 449 * @param IRQn External interrupt number
NYX 0:85b3fd62ea1a 450 * This parameter can be an enumerator of IRQn_Type enumeration
NYX 0:85b3fd62ea1a 451 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
NYX 0:85b3fd62ea1a 452 * @retval status: - 0 Interrupt status is not pending.
NYX 0:85b3fd62ea1a 453 * - 1 Interrupt status is pending.
NYX 0:85b3fd62ea1a 454 */
NYX 0:85b3fd62ea1a 455 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 456 {
NYX 0:85b3fd62ea1a 457 /* Check the parameters */
NYX 0:85b3fd62ea1a 458 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
NYX 0:85b3fd62ea1a 459
NYX 0:85b3fd62ea1a 460 /* Return 1 if active else 0 */
NYX 0:85b3fd62ea1a 461 return NVIC_GetActive(IRQn);
NYX 0:85b3fd62ea1a 462 }
NYX 0:85b3fd62ea1a 463
NYX 0:85b3fd62ea1a 464 /**
NYX 0:85b3fd62ea1a 465 * @brief Configures the SysTick clock source.
NYX 0:85b3fd62ea1a 466 * @param CLKSource: specifies the SysTick clock source.
NYX 0:85b3fd62ea1a 467 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 468 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
NYX 0:85b3fd62ea1a 469 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
NYX 0:85b3fd62ea1a 470 * @retval None
NYX 0:85b3fd62ea1a 471 */
NYX 0:85b3fd62ea1a 472 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
NYX 0:85b3fd62ea1a 473 {
NYX 0:85b3fd62ea1a 474 /* Check the parameters */
NYX 0:85b3fd62ea1a 475 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
NYX 0:85b3fd62ea1a 476 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
NYX 0:85b3fd62ea1a 477 {
NYX 0:85b3fd62ea1a 478 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
NYX 0:85b3fd62ea1a 479 }
NYX 0:85b3fd62ea1a 480 else
NYX 0:85b3fd62ea1a 481 {
NYX 0:85b3fd62ea1a 482 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
NYX 0:85b3fd62ea1a 483 }
NYX 0:85b3fd62ea1a 484 }
NYX 0:85b3fd62ea1a 485
NYX 0:85b3fd62ea1a 486 /**
NYX 0:85b3fd62ea1a 487 * @brief This function handles SYSTICK interrupt request.
NYX 0:85b3fd62ea1a 488 * @retval None
NYX 0:85b3fd62ea1a 489 */
NYX 0:85b3fd62ea1a 490 void HAL_SYSTICK_IRQHandler(void)
NYX 0:85b3fd62ea1a 491 {
NYX 0:85b3fd62ea1a 492 HAL_SYSTICK_Callback();
NYX 0:85b3fd62ea1a 493 }
NYX 0:85b3fd62ea1a 494
NYX 0:85b3fd62ea1a 495 /**
NYX 0:85b3fd62ea1a 496 * @brief SYSTICK callback.
NYX 0:85b3fd62ea1a 497 * @retval None
NYX 0:85b3fd62ea1a 498 */
NYX 0:85b3fd62ea1a 499 __weak void HAL_SYSTICK_Callback(void)
NYX 0:85b3fd62ea1a 500 {
NYX 0:85b3fd62ea1a 501 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 502 the HAL_SYSTICK_Callback could be implemented in the user file
NYX 0:85b3fd62ea1a 503 */
NYX 0:85b3fd62ea1a 504 }
NYX 0:85b3fd62ea1a 505
NYX 0:85b3fd62ea1a 506 /**
NYX 0:85b3fd62ea1a 507 * @}
NYX 0:85b3fd62ea1a 508 */
NYX 0:85b3fd62ea1a 509
NYX 0:85b3fd62ea1a 510 /**
NYX 0:85b3fd62ea1a 511 * @}
NYX 0:85b3fd62ea1a 512 */
NYX 0:85b3fd62ea1a 513
NYX 0:85b3fd62ea1a 514 #endif /* HAL_CORTEX_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 515 /**
NYX 0:85b3fd62ea1a 516 * @}
NYX 0:85b3fd62ea1a 517 */
NYX 0:85b3fd62ea1a 518
NYX 0:85b3fd62ea1a 519 /**
NYX 0:85b3fd62ea1a 520 * @}
NYX 0:85b3fd62ea1a 521 */
NYX 0:85b3fd62ea1a 522
NYX 0:85b3fd62ea1a 523 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/