mbed-dev - inport from local

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inport from local

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_hal_adc.c
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief This file provides firmware functions to manage the following
NYX	0:85b3fd62ea1a	8	* functionalities of the Analog to Digital Convertor (ADC) peripheral:
NYX	0:85b3fd62ea1a	9	* + Initialization and de-initialization functions
NYX	0:85b3fd62ea1a	10	* + IO operation functions
NYX	0:85b3fd62ea1a	11	* + State and errors functions
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	@verbatim
NYX	0:85b3fd62ea1a	14	==============================================================================
NYX	0:85b3fd62ea1a	15	##### ADC Peripheral features #####
NYX	0:85b3fd62ea1a	16	==============================================================================
NYX	0:85b3fd62ea1a	17	[..]
NYX	0:85b3fd62ea1a	18	(#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
NYX	0:85b3fd62ea1a	19	(#) Interrupt generation at the end of conversion, end of injected conversion,
NYX	0:85b3fd62ea1a	20	and in case of analog watchdog or overrun events
NYX	0:85b3fd62ea1a	21	(#) Single and continuous conversion modes.
NYX	0:85b3fd62ea1a	22	(#) Scan mode for automatic conversion of channel 0 to channel x.
NYX	0:85b3fd62ea1a	23	(#) Data alignment with in-built data coherency.
NYX	0:85b3fd62ea1a	24	(#) Channel-wise programmable sampling time.
NYX	0:85b3fd62ea1a	25	(#) External trigger option with configurable polarity for both regular and
NYX	0:85b3fd62ea1a	26	injected conversion.
NYX	0:85b3fd62ea1a	27	(#) Dual/Triple mode (on devices with 2 ADCs or more).
NYX	0:85b3fd62ea1a	28	(#) Configurable DMA data storage in Dual/Triple ADC mode.
NYX	0:85b3fd62ea1a	29	(#) Configurable delay between conversions in Dual/Triple interleaved mode.
NYX	0:85b3fd62ea1a	30	(#) ADC conversion type (refer to the datasheets).
NYX	0:85b3fd62ea1a	31	(#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
NYX	0:85b3fd62ea1a	32	slower speed.
NYX	0:85b3fd62ea1a	33	(#) ADC input range: VREF(minus) = VIN = VREF(plus).
NYX	0:85b3fd62ea1a	34	(#) DMA request generation during regular channel conversion.
NYX	0:85b3fd62ea1a	35
NYX	0:85b3fd62ea1a	36
NYX	0:85b3fd62ea1a	37	##### How to use this driver #####
NYX	0:85b3fd62ea1a	38	==============================================================================
NYX	0:85b3fd62ea1a	39	[..]
NYX	0:85b3fd62ea1a	40	(#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
NYX	0:85b3fd62ea1a	41	(##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
NYX	0:85b3fd62ea1a	42	(##) ADC pins configuration
NYX	0:85b3fd62ea1a	43	(+++) Enable the clock for the ADC GPIOs using the following function:
NYX	0:85b3fd62ea1a	44	__HAL_RCC_GPIOx_CLK_ENABLE()
NYX	0:85b3fd62ea1a	45	(+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
NYX	0:85b3fd62ea1a	46	(##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
NYX	0:85b3fd62ea1a	47	(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
NYX	0:85b3fd62ea1a	48	(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
NYX	0:85b3fd62ea1a	49	(+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
NYX	0:85b3fd62ea1a	50	(##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
NYX	0:85b3fd62ea1a	51	(+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
NYX	0:85b3fd62ea1a	52	(+++) Configure and enable two DMA streams stream for managing data
NYX	0:85b3fd62ea1a	53	transfer from peripheral to memory (output stream)
NYX	0:85b3fd62ea1a	54	(+++) Associate the initialized DMA handle to the CRYP DMA handle
NYX	0:85b3fd62ea1a	55	using __HAL_LINKDMA()
NYX	0:85b3fd62ea1a	56	(+++) Configure the priority and enable the NVIC for the transfer complete
NYX	0:85b3fd62ea1a	57	interrupt on the two DMA Streams. The output stream should have higher
NYX	0:85b3fd62ea1a	58	priority than the input stream.
NYX	0:85b3fd62ea1a	59
NYX	0:85b3fd62ea1a	60	* Configuration of ADC, groups regular/injected, channels parameters *
NYX	0:85b3fd62ea1a	61	==============================================================================
NYX	0:85b3fd62ea1a	62	[..]
NYX	0:85b3fd62ea1a	63	(#) Configure the ADC parameters (resolution, data alignment, ...)
NYX	0:85b3fd62ea1a	64	and regular group parameters (conversion trigger, sequencer, ...)
NYX	0:85b3fd62ea1a	65	using function HAL_ADC_Init().
NYX	0:85b3fd62ea1a	66
NYX	0:85b3fd62ea1a	67	(#) Configure the channels for regular group parameters (channel number,
NYX	0:85b3fd62ea1a	68	channel rank into sequencer, ..., into regular group)
NYX	0:85b3fd62ea1a	69	using function HAL_ADC_ConfigChannel().
NYX	0:85b3fd62ea1a	70
NYX	0:85b3fd62ea1a	71	(#) Optionally, configure the injected group parameters (conversion trigger,
NYX	0:85b3fd62ea1a	72	sequencer, ..., of injected group)
NYX	0:85b3fd62ea1a	73	and the channels for injected group parameters (channel number,
NYX	0:85b3fd62ea1a	74	channel rank into sequencer, ..., into injected group)
NYX	0:85b3fd62ea1a	75	using function HAL_ADCEx_InjectedConfigChannel().
NYX	0:85b3fd62ea1a	76
NYX	0:85b3fd62ea1a	77	(#) Optionally, configure the analog watchdog parameters (channels
NYX	0:85b3fd62ea1a	78	monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
NYX	0:85b3fd62ea1a	79
NYX	0:85b3fd62ea1a	80	(#) Optionally, for devices with several ADC instances: configure the
NYX	0:85b3fd62ea1a	81	multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
NYX	0:85b3fd62ea1a	82
NYX	0:85b3fd62ea1a	83	* Execution of ADC conversions *
NYX	0:85b3fd62ea1a	84	==============================================================================
NYX	0:85b3fd62ea1a	85	[..]
NYX	0:85b3fd62ea1a	86	(#) ADC driver can be used among three modes: polling, interruption,
NYX	0:85b3fd62ea1a	87	transfer by DMA.
NYX	0:85b3fd62ea1a	88
NYX	0:85b3fd62ea1a	89	* Polling mode IO operation *
NYX	0:85b3fd62ea1a	90	=================================
NYX	0:85b3fd62ea1a	91	[..]
NYX	0:85b3fd62ea1a	92	(+) Start the ADC peripheral using HAL_ADC_Start()
NYX	0:85b3fd62ea1a	93	(+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
NYX	0:85b3fd62ea1a	94	user can specify the value of timeout according to his end application
NYX	0:85b3fd62ea1a	95	(+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
NYX	0:85b3fd62ea1a	96	(+) Stop the ADC peripheral using HAL_ADC_Stop()
NYX	0:85b3fd62ea1a	97
NYX	0:85b3fd62ea1a	98	* Interrupt mode IO operation *
NYX	0:85b3fd62ea1a	99	===================================
NYX	0:85b3fd62ea1a	100	[..]
NYX	0:85b3fd62ea1a	101	(+) Start the ADC peripheral using HAL_ADC_Start_IT()
NYX	0:85b3fd62ea1a	102	(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
NYX	0:85b3fd62ea1a	103	(+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
NYX	0:85b3fd62ea1a	104	add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
NYX	0:85b3fd62ea1a	105	(+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
NYX	0:85b3fd62ea1a	106	add his own code by customization of function pointer HAL_ADC_ErrorCallback
NYX	0:85b3fd62ea1a	107	(+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
NYX	0:85b3fd62ea1a	108
NYX	0:85b3fd62ea1a	109	* DMA mode IO operation *
NYX	0:85b3fd62ea1a	110	==============================
NYX	0:85b3fd62ea1a	111	[..]
NYX	0:85b3fd62ea1a	112	(+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
NYX	0:85b3fd62ea1a	113	of data to be transferred at each end of conversion
NYX	0:85b3fd62ea1a	114	(+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
NYX	0:85b3fd62ea1a	115	add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
NYX	0:85b3fd62ea1a	116	(+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
NYX	0:85b3fd62ea1a	117	add his own code by customization of function pointer HAL_ADC_ErrorCallback
NYX	0:85b3fd62ea1a	118	(+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
NYX	0:85b3fd62ea1a	119
NYX	0:85b3fd62ea1a	120	* ADC HAL driver macros list *
NYX	0:85b3fd62ea1a	121	=============================================
NYX	0:85b3fd62ea1a	122	[..]
NYX	0:85b3fd62ea1a	123	Below the list of most used macros in ADC HAL driver.
NYX	0:85b3fd62ea1a	124
NYX	0:85b3fd62ea1a	125	(+) __HAL_ADC_ENABLE : Enable the ADC peripheral
NYX	0:85b3fd62ea1a	126	(+) __HAL_ADC_DISABLE : Disable the ADC peripheral
NYX	0:85b3fd62ea1a	127	(+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
NYX	0:85b3fd62ea1a	128	(+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
NYX	0:85b3fd62ea1a	129	(+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
NYX	0:85b3fd62ea1a	130	(+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
NYX	0:85b3fd62ea1a	131	(+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
NYX	0:85b3fd62ea1a	132	(+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
NYX	0:85b3fd62ea1a	133
NYX	0:85b3fd62ea1a	134	[..]
NYX	0:85b3fd62ea1a	135	(@) You can refer to the ADC HAL driver header file for more useful macros
NYX	0:85b3fd62ea1a	136
NYX	0:85b3fd62ea1a	137	* Deinitialization of ADC *
NYX	0:85b3fd62ea1a	138	==============================================================================
NYX	0:85b3fd62ea1a	139	[..]
NYX	0:85b3fd62ea1a	140	(#) Disable the ADC interface
NYX	0:85b3fd62ea1a	141	(++) ADC clock can be hard reset and disabled at RCC top level.
NYX	0:85b3fd62ea1a	142	(++) Hard reset of ADC peripherals
NYX	0:85b3fd62ea1a	143	using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
NYX	0:85b3fd62ea1a	144	(++) ADC clock disable using the equivalent macro/functions as configuration step.
NYX	0:85b3fd62ea1a	145	(+++) Example:
NYX	0:85b3fd62ea1a	146	Into HAL_ADC_MspDeInit() (recommended code location) or with
NYX	0:85b3fd62ea1a	147	other device clock parameters configuration:
NYX	0:85b3fd62ea1a	148	(+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
NYX	0:85b3fd62ea1a	149	(+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
NYX	0:85b3fd62ea1a	150	(+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
NYX	0:85b3fd62ea1a	151	(+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
NYX	0:85b3fd62ea1a	152
NYX	0:85b3fd62ea1a	153	(#) ADC pins configuration
NYX	0:85b3fd62ea1a	154	(++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
NYX	0:85b3fd62ea1a	155
NYX	0:85b3fd62ea1a	156	(#) Optionally, in case of usage of ADC with interruptions:
NYX	0:85b3fd62ea1a	157	(++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
NYX	0:85b3fd62ea1a	158
NYX	0:85b3fd62ea1a	159	(#) Optionally, in case of usage of DMA:
NYX	0:85b3fd62ea1a	160	(++) Deinitialize the DMA using function HAL_DMA_DeInit().
NYX	0:85b3fd62ea1a	161	(++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
NYX	0:85b3fd62ea1a	162
NYX	0:85b3fd62ea1a	163	@endverbatim
NYX	0:85b3fd62ea1a	164	******************************************************************************
NYX	0:85b3fd62ea1a	165	* @attention
NYX	0:85b3fd62ea1a	166	*
NYX	0:85b3fd62ea1a	167	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	168	*
NYX	0:85b3fd62ea1a	169	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	170	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	171	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	172	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	173	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	174	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	175	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	176	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	177	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	178	* without specific prior written permission.
NYX	0:85b3fd62ea1a	179	*
NYX	0:85b3fd62ea1a	180	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	181	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	182	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	183	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	184	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	185	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	186	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	187	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	188	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	189	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	190	*
NYX	0:85b3fd62ea1a	191	******************************************************************************
NYX	0:85b3fd62ea1a	192	*/
NYX	0:85b3fd62ea1a	193
NYX	0:85b3fd62ea1a	194	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	195	#include "stm32f4xx_hal.h"
NYX	0:85b3fd62ea1a	196
NYX	0:85b3fd62ea1a	197	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	198	* @{
NYX	0:85b3fd62ea1a	199	*/
NYX	0:85b3fd62ea1a	200
NYX	0:85b3fd62ea1a	201	/** @defgroup ADC ADC
NYX	0:85b3fd62ea1a	202	* @brief ADC driver modules
NYX	0:85b3fd62ea1a	203	* @{
NYX	0:85b3fd62ea1a	204	*/
NYX	0:85b3fd62ea1a	205
NYX	0:85b3fd62ea1a	206	#ifdef HAL_ADC_MODULE_ENABLED
NYX	0:85b3fd62ea1a	207
NYX	0:85b3fd62ea1a	208	/* Private typedef -----------------------------------------------------------*/
NYX	0:85b3fd62ea1a	209	/* Private define ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	210	/* Private macro -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	211	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	212	/** @addtogroup ADC_Private_Functions
NYX	0:85b3fd62ea1a	213	* @{
NYX	0:85b3fd62ea1a	214	*/
NYX	0:85b3fd62ea1a	215	/* Private function prototypes -----------------------------------------------*/
NYX	0:85b3fd62ea1a	216	static void ADC_Init(ADC_HandleTypeDef* hadc);
NYX	0:85b3fd62ea1a	217	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	218	static void ADC_DMAError(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	219	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	220	/**
NYX	0:85b3fd62ea1a	221	* @}
NYX	0:85b3fd62ea1a	222	*/
NYX	0:85b3fd62ea1a	223	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	224	/** @defgroup ADC_Exported_Functions ADC Exported Functions
NYX	0:85b3fd62ea1a	225	* @{
NYX	0:85b3fd62ea1a	226	*/
NYX	0:85b3fd62ea1a	227
NYX	0:85b3fd62ea1a	228	/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
NYX	0:85b3fd62ea1a	229	* @brief Initialization and Configuration functions
NYX	0:85b3fd62ea1a	230	*
NYX	0:85b3fd62ea1a	231	@verbatim
NYX	0:85b3fd62ea1a	232	===============================================================================
NYX	0:85b3fd62ea1a	233	##### Initialization and de-initialization functions #####
NYX	0:85b3fd62ea1a	234	===============================================================================
NYX	0:85b3fd62ea1a	235	[..] This section provides functions allowing to:
NYX	0:85b3fd62ea1a	236	(+) Initialize and configure the ADC.
NYX	0:85b3fd62ea1a	237	(+) De-initialize the ADC.
NYX	0:85b3fd62ea1a	238
NYX	0:85b3fd62ea1a	239	@endverbatim
NYX	0:85b3fd62ea1a	240	* @{
NYX	0:85b3fd62ea1a	241	*/
NYX	0:85b3fd62ea1a	242
NYX	0:85b3fd62ea1a	243	/**
NYX	0:85b3fd62ea1a	244	* @brief Initializes the ADCx peripheral according to the specified parameters
NYX	0:85b3fd62ea1a	245	* in the ADC_InitStruct and initializes the ADC MSP.
NYX	0:85b3fd62ea1a	246	*
NYX	0:85b3fd62ea1a	247	* @note This function is used to configure the global features of the ADC (
NYX	0:85b3fd62ea1a	248	* ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
NYX	0:85b3fd62ea1a	249	* the rest of the configuration parameters are specific to the regular
NYX	0:85b3fd62ea1a	250	* channels group (scan mode activation, continuous mode activation,
NYX	0:85b3fd62ea1a	251	* External trigger source and edge, DMA continuous request after the
NYX	0:85b3fd62ea1a	252	* last transfer and End of conversion selection).
NYX	0:85b3fd62ea1a	253	*
NYX	0:85b3fd62ea1a	254	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	255	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	256	* @retval HAL status
NYX	0:85b3fd62ea1a	257	*/
NYX	0:85b3fd62ea1a	258	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	259	{
NYX	0:85b3fd62ea1a	260	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
NYX	0:85b3fd62ea1a	261
NYX	0:85b3fd62ea1a	262	/* Check ADC handle */
NYX	0:85b3fd62ea1a	263	if(hadc == NULL)
NYX	0:85b3fd62ea1a	264	{
NYX	0:85b3fd62ea1a	265	return HAL_ERROR;
NYX	0:85b3fd62ea1a	266	}
NYX	0:85b3fd62ea1a	267
NYX	0:85b3fd62ea1a	268	/* Check the parameters */
NYX	0:85b3fd62ea1a	269	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
NYX	0:85b3fd62ea1a	270	assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
NYX	0:85b3fd62ea1a	271	assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
NYX	0:85b3fd62ea1a	272	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
NYX	0:85b3fd62ea1a	273	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
NYX	0:85b3fd62ea1a	274	assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
NYX	0:85b3fd62ea1a	275	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
NYX	0:85b3fd62ea1a	276	assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
NYX	0:85b3fd62ea1a	277	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
NYX	0:85b3fd62ea1a	278	assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
NYX	0:85b3fd62ea1a	279	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
NYX	0:85b3fd62ea1a	280
NYX	0:85b3fd62ea1a	281	if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
NYX	0:85b3fd62ea1a	282	{
NYX	0:85b3fd62ea1a	283	assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
NYX	0:85b3fd62ea1a	284	}
NYX	0:85b3fd62ea1a	285
NYX	0:85b3fd62ea1a	286	if(hadc->State == HAL_ADC_STATE_RESET)
NYX	0:85b3fd62ea1a	287	{
NYX	0:85b3fd62ea1a	288	/* Initialize ADC error code */
NYX	0:85b3fd62ea1a	289	ADC_CLEAR_ERRORCODE(hadc);
NYX	0:85b3fd62ea1a	290
NYX	0:85b3fd62ea1a	291	/* Allocate lock resource and initialize it */
NYX	0:85b3fd62ea1a	292	hadc->Lock = HAL_UNLOCKED;
NYX	0:85b3fd62ea1a	293
NYX	0:85b3fd62ea1a	294	/* Init the low level hardware */
NYX	0:85b3fd62ea1a	295	HAL_ADC_MspInit(hadc);
NYX	0:85b3fd62ea1a	296	}
NYX	0:85b3fd62ea1a	297
NYX	0:85b3fd62ea1a	298	/* Configuration of ADC parameters if previous preliminary actions are */
NYX	0:85b3fd62ea1a	299	/* correctly completed. */
NYX	0:85b3fd62ea1a	300	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
NYX	0:85b3fd62ea1a	301	{
NYX	0:85b3fd62ea1a	302	/* Set ADC state */
NYX	0:85b3fd62ea1a	303	ADC_STATE_CLR_SET(hadc->State,
NYX	0:85b3fd62ea1a	304	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
NYX	0:85b3fd62ea1a	305	HAL_ADC_STATE_BUSY_INTERNAL);
NYX	0:85b3fd62ea1a	306
NYX	0:85b3fd62ea1a	307	/* Set ADC parameters */
NYX	0:85b3fd62ea1a	308	ADC_Init(hadc);
NYX	0:85b3fd62ea1a	309
NYX	0:85b3fd62ea1a	310	/* Set ADC error code to none */
NYX	0:85b3fd62ea1a	311	ADC_CLEAR_ERRORCODE(hadc);
NYX	0:85b3fd62ea1a	312
NYX	0:85b3fd62ea1a	313	/* Set the ADC state */
NYX	0:85b3fd62ea1a	314	ADC_STATE_CLR_SET(hadc->State,
NYX	0:85b3fd62ea1a	315	HAL_ADC_STATE_BUSY_INTERNAL,
NYX	0:85b3fd62ea1a	316	HAL_ADC_STATE_READY);
NYX	0:85b3fd62ea1a	317	}
NYX	0:85b3fd62ea1a	318	else
NYX	0:85b3fd62ea1a	319	{
NYX	0:85b3fd62ea1a	320	tmp_hal_status = HAL_ERROR;
NYX	0:85b3fd62ea1a	321	}
NYX	0:85b3fd62ea1a	322
NYX	0:85b3fd62ea1a	323	/* Release Lock */
NYX	0:85b3fd62ea1a	324	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	325
NYX	0:85b3fd62ea1a	326	/* Return function status */
NYX	0:85b3fd62ea1a	327	return tmp_hal_status;
NYX	0:85b3fd62ea1a	328	}
NYX	0:85b3fd62ea1a	329
NYX	0:85b3fd62ea1a	330	/**
NYX	0:85b3fd62ea1a	331	* @brief Deinitializes the ADCx peripheral registers to their default reset values.
NYX	0:85b3fd62ea1a	332	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	333	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	334	* @retval HAL status
NYX	0:85b3fd62ea1a	335	*/
NYX	0:85b3fd62ea1a	336	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	337	{
NYX	0:85b3fd62ea1a	338	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
NYX	0:85b3fd62ea1a	339
NYX	0:85b3fd62ea1a	340	/* Check ADC handle */
NYX	0:85b3fd62ea1a	341	if(hadc == NULL)
NYX	0:85b3fd62ea1a	342	{
NYX	0:85b3fd62ea1a	343	return HAL_ERROR;
NYX	0:85b3fd62ea1a	344	}
NYX	0:85b3fd62ea1a	345
NYX	0:85b3fd62ea1a	346	/* Check the parameters */
NYX	0:85b3fd62ea1a	347	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
NYX	0:85b3fd62ea1a	348
NYX	0:85b3fd62ea1a	349	/* Set ADC state */
NYX	0:85b3fd62ea1a	350	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
NYX	0:85b3fd62ea1a	351
NYX	0:85b3fd62ea1a	352	/* Stop potential conversion on going, on regular and injected groups */
NYX	0:85b3fd62ea1a	353	/* Disable ADC peripheral */
NYX	0:85b3fd62ea1a	354	__HAL_ADC_DISABLE(hadc);
NYX	0:85b3fd62ea1a	355
NYX	0:85b3fd62ea1a	356	/* Configuration of ADC parameters if previous preliminary actions are */
NYX	0:85b3fd62ea1a	357	/* correctly completed. */
NYX	0:85b3fd62ea1a	358	if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
NYX	0:85b3fd62ea1a	359	{
NYX	0:85b3fd62ea1a	360	/* DeInit the low level hardware */
NYX	0:85b3fd62ea1a	361	HAL_ADC_MspDeInit(hadc);
NYX	0:85b3fd62ea1a	362
NYX	0:85b3fd62ea1a	363	/* Set ADC error code to none */
NYX	0:85b3fd62ea1a	364	ADC_CLEAR_ERRORCODE(hadc);
NYX	0:85b3fd62ea1a	365
NYX	0:85b3fd62ea1a	366	/* Set ADC state */
NYX	0:85b3fd62ea1a	367	hadc->State = HAL_ADC_STATE_RESET;
NYX	0:85b3fd62ea1a	368	}
NYX	0:85b3fd62ea1a	369
NYX	0:85b3fd62ea1a	370	/* Process unlocked */
NYX	0:85b3fd62ea1a	371	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	372
NYX	0:85b3fd62ea1a	373	/* Return function status */
NYX	0:85b3fd62ea1a	374	return tmp_hal_status;
NYX	0:85b3fd62ea1a	375	}
NYX	0:85b3fd62ea1a	376
NYX	0:85b3fd62ea1a	377	/**
NYX	0:85b3fd62ea1a	378	* @brief Initializes the ADC MSP.
NYX	0:85b3fd62ea1a	379	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	380	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	381	* @retval None
NYX	0:85b3fd62ea1a	382	*/
NYX	0:85b3fd62ea1a	383	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	384	{
NYX	0:85b3fd62ea1a	385	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	386	UNUSED(hadc);
NYX	0:85b3fd62ea1a	387	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	388	the HAL_ADC_MspInit could be implemented in the user file
NYX	0:85b3fd62ea1a	389	*/
NYX	0:85b3fd62ea1a	390	}
NYX	0:85b3fd62ea1a	391
NYX	0:85b3fd62ea1a	392	/**
NYX	0:85b3fd62ea1a	393	* @brief DeInitializes the ADC MSP.
NYX	0:85b3fd62ea1a	394	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	395	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	396	* @retval None
NYX	0:85b3fd62ea1a	397	*/
NYX	0:85b3fd62ea1a	398	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	399	{
NYX	0:85b3fd62ea1a	400	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	401	UNUSED(hadc);
NYX	0:85b3fd62ea1a	402	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	403	the HAL_ADC_MspDeInit could be implemented in the user file
NYX	0:85b3fd62ea1a	404	*/
NYX	0:85b3fd62ea1a	405	}
NYX	0:85b3fd62ea1a	406
NYX	0:85b3fd62ea1a	407	/**
NYX	0:85b3fd62ea1a	408	* @}
NYX	0:85b3fd62ea1a	409	*/
NYX	0:85b3fd62ea1a	410
NYX	0:85b3fd62ea1a	411	/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
NYX	0:85b3fd62ea1a	412	* @brief IO operation functions
NYX	0:85b3fd62ea1a	413	*
NYX	0:85b3fd62ea1a	414	@verbatim
NYX	0:85b3fd62ea1a	415	===============================================================================
NYX	0:85b3fd62ea1a	416	##### IO operation functions #####
NYX	0:85b3fd62ea1a	417	===============================================================================
NYX	0:85b3fd62ea1a	418	[..] This section provides functions allowing to:
NYX	0:85b3fd62ea1a	419	(+) Start conversion of regular channel.
NYX	0:85b3fd62ea1a	420	(+) Stop conversion of regular channel.
NYX	0:85b3fd62ea1a	421	(+) Start conversion of regular channel and enable interrupt.
NYX	0:85b3fd62ea1a	422	(+) Stop conversion of regular channel and disable interrupt.
NYX	0:85b3fd62ea1a	423	(+) Start conversion of regular channel and enable DMA transfer.
NYX	0:85b3fd62ea1a	424	(+) Stop conversion of regular channel and disable DMA transfer.
NYX	0:85b3fd62ea1a	425	(+) Handle ADC interrupt request.
NYX	0:85b3fd62ea1a	426
NYX	0:85b3fd62ea1a	427	@endverbatim
NYX	0:85b3fd62ea1a	428	* @{
NYX	0:85b3fd62ea1a	429	*/
NYX	0:85b3fd62ea1a	430
NYX	0:85b3fd62ea1a	431	/**
NYX	0:85b3fd62ea1a	432	* @brief Enables ADC and starts conversion of the regular channels.
NYX	0:85b3fd62ea1a	433	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	434	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	435	* @retval HAL status
NYX	0:85b3fd62ea1a	436	*/
NYX	0:85b3fd62ea1a	437	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	438	{
NYX	0:85b3fd62ea1a	439	__IO uint32_t counter = 0U;
NYX	0:85b3fd62ea1a	440	ADC_Common_TypeDef *tmpADC_Common;
NYX	0:85b3fd62ea1a	441
NYX	0:85b3fd62ea1a	442	/* Check the parameters */
NYX	0:85b3fd62ea1a	443	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
NYX	0:85b3fd62ea1a	444	assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
NYX	0:85b3fd62ea1a	445
NYX	0:85b3fd62ea1a	446	/* Process locked */
NYX	0:85b3fd62ea1a	447	__HAL_LOCK(hadc);
NYX	0:85b3fd62ea1a	448
NYX	0:85b3fd62ea1a	449	/* Enable the ADC peripheral */
NYX	0:85b3fd62ea1a	450	/* Check if ADC peripheral is disabled in order to enable it and wait during
NYX	0:85b3fd62ea1a	451	Tstab time the ADC's stabilization */
NYX	0:85b3fd62ea1a	452	if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
NYX	0:85b3fd62ea1a	453	{
NYX	0:85b3fd62ea1a	454	/* Enable the Peripheral */
NYX	0:85b3fd62ea1a	455	__HAL_ADC_ENABLE(hadc);
NYX	0:85b3fd62ea1a	456
NYX	0:85b3fd62ea1a	457	/* Delay for ADC stabilization time */
NYX	0:85b3fd62ea1a	458	/* Compute number of CPU cycles to wait for */
NYX	0:85b3fd62ea1a	459	counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
NYX	0:85b3fd62ea1a	460	while(counter != 0U)
NYX	0:85b3fd62ea1a	461	{
NYX	0:85b3fd62ea1a	462	counter--;
NYX	0:85b3fd62ea1a	463	}
NYX	0:85b3fd62ea1a	464	}
NYX	0:85b3fd62ea1a	465
NYX	0:85b3fd62ea1a	466	/* Start conversion if ADC is effectively enabled */
NYX	0:85b3fd62ea1a	467	if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
NYX	0:85b3fd62ea1a	468	{
NYX	0:85b3fd62ea1a	469	/* Set ADC state */
NYX	0:85b3fd62ea1a	470	/* - Clear state bitfield related to regular group conversion results */
NYX	0:85b3fd62ea1a	471	/* - Set state bitfield related to regular group operation */
NYX	0:85b3fd62ea1a	472	ADC_STATE_CLR_SET(hadc->State,
NYX	0:85b3fd62ea1a	473	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR,
NYX	0:85b3fd62ea1a	474	HAL_ADC_STATE_REG_BUSY);
NYX	0:85b3fd62ea1a	475
NYX	0:85b3fd62ea1a	476	/* If conversions on group regular are also triggering group injected, */
NYX	0:85b3fd62ea1a	477	/* update ADC state. */
NYX	0:85b3fd62ea1a	478	if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
NYX	0:85b3fd62ea1a	479	{
NYX	0:85b3fd62ea1a	480	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
NYX	0:85b3fd62ea1a	481	}
NYX	0:85b3fd62ea1a	482
NYX	0:85b3fd62ea1a	483	/* State machine update: Check if an injected conversion is ongoing */
NYX	0:85b3fd62ea1a	484	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
NYX	0:85b3fd62ea1a	485	{
NYX	0:85b3fd62ea1a	486	/* Reset ADC error code fields related to conversions on group regular */
NYX	0:85b3fd62ea1a	487	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
NYX	0:85b3fd62ea1a	488	}
NYX	0:85b3fd62ea1a	489	else
NYX	0:85b3fd62ea1a	490	{
NYX	0:85b3fd62ea1a	491	/* Reset ADC all error code fields */
NYX	0:85b3fd62ea1a	492	ADC_CLEAR_ERRORCODE(hadc);
NYX	0:85b3fd62ea1a	493	}
NYX	0:85b3fd62ea1a	494
NYX	0:85b3fd62ea1a	495	/* Process unlocked */
NYX	0:85b3fd62ea1a	496	/* Unlock before starting ADC conversions: in case of potential */
NYX	0:85b3fd62ea1a	497	/* interruption, to let the process to ADC IRQ Handler. */
NYX	0:85b3fd62ea1a	498	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	499
NYX	0:85b3fd62ea1a	500	/* Pointer to the common control register to which is belonging hadc */
NYX	0:85b3fd62ea1a	501	/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
NYX	0:85b3fd62ea1a	502	/* control register) */
NYX	0:85b3fd62ea1a	503	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
NYX	0:85b3fd62ea1a	504
NYX	0:85b3fd62ea1a	505	/* Clear regular group conversion flag and overrun flag */
NYX	0:85b3fd62ea1a	506	/* (To ensure of no unknown state from potential previous ADC operations) */
NYX	0:85b3fd62ea1a	507	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC \| ADC_FLAG_OVR);
NYX	0:85b3fd62ea1a	508
NYX	0:85b3fd62ea1a	509	/* Check if Multimode enabled */
NYX	0:85b3fd62ea1a	510	if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
NYX	0:85b3fd62ea1a	511	{
NYX	0:85b3fd62ea1a	512	/* if no external trigger present enable software conversion of regular channels */
NYX	0:85b3fd62ea1a	513	if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
NYX	0:85b3fd62ea1a	514	{
NYX	0:85b3fd62ea1a	515	/* Enable the selected ADC software conversion for regular group */
NYX	0:85b3fd62ea1a	516	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
NYX	0:85b3fd62ea1a	517	}
NYX	0:85b3fd62ea1a	518	}
NYX	0:85b3fd62ea1a	519	else
NYX	0:85b3fd62ea1a	520	{
NYX	0:85b3fd62ea1a	521	/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
NYX	0:85b3fd62ea1a	522	if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
NYX	0:85b3fd62ea1a	523	{
NYX	0:85b3fd62ea1a	524	/* Enable the selected ADC software conversion for regular group */
NYX	0:85b3fd62ea1a	525	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
NYX	0:85b3fd62ea1a	526	}
NYX	0:85b3fd62ea1a	527	}
NYX	0:85b3fd62ea1a	528	}
NYX	0:85b3fd62ea1a	529
NYX	0:85b3fd62ea1a	530	/* Return function status */
NYX	0:85b3fd62ea1a	531	return HAL_OK;
NYX	0:85b3fd62ea1a	532	}
NYX	0:85b3fd62ea1a	533
NYX	0:85b3fd62ea1a	534	/**
NYX	0:85b3fd62ea1a	535	* @brief Disables ADC and stop conversion of regular channels.
NYX	0:85b3fd62ea1a	536	*
NYX	0:85b3fd62ea1a	537	* @note Caution: This function will stop also injected channels.
NYX	0:85b3fd62ea1a	538	*
NYX	0:85b3fd62ea1a	539	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	540	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	541	*
NYX	0:85b3fd62ea1a	542	* @retval HAL status.
NYX	0:85b3fd62ea1a	543	*/
NYX	0:85b3fd62ea1a	544	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	545	{
NYX	0:85b3fd62ea1a	546	/* Check the parameters */
NYX	0:85b3fd62ea1a	547	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
NYX	0:85b3fd62ea1a	548
NYX	0:85b3fd62ea1a	549	/* Process locked */
NYX	0:85b3fd62ea1a	550	__HAL_LOCK(hadc);
NYX	0:85b3fd62ea1a	551
NYX	0:85b3fd62ea1a	552	/* Stop potential conversion on going, on regular and injected groups */
NYX	0:85b3fd62ea1a	553	/* Disable ADC peripheral */
NYX	0:85b3fd62ea1a	554	__HAL_ADC_DISABLE(hadc);
NYX	0:85b3fd62ea1a	555
NYX	0:85b3fd62ea1a	556	/* Check if ADC is effectively disabled */
NYX	0:85b3fd62ea1a	557	if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
NYX	0:85b3fd62ea1a	558	{
NYX	0:85b3fd62ea1a	559	/* Set ADC state */
NYX	0:85b3fd62ea1a	560	ADC_STATE_CLR_SET(hadc->State,
NYX	0:85b3fd62ea1a	561	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
NYX	0:85b3fd62ea1a	562	HAL_ADC_STATE_READY);
NYX	0:85b3fd62ea1a	563	}
NYX	0:85b3fd62ea1a	564
NYX	0:85b3fd62ea1a	565	/* Process unlocked */
NYX	0:85b3fd62ea1a	566	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	567
NYX	0:85b3fd62ea1a	568	/* Return function status */
NYX	0:85b3fd62ea1a	569	return HAL_OK;
NYX	0:85b3fd62ea1a	570	}
NYX	0:85b3fd62ea1a	571
NYX	0:85b3fd62ea1a	572	/**
NYX	0:85b3fd62ea1a	573	* @brief Poll for regular conversion complete
NYX	0:85b3fd62ea1a	574	* @note ADC conversion flags EOS (end of sequence) and EOC (end of
NYX	0:85b3fd62ea1a	575	* conversion) are cleared by this function.
NYX	0:85b3fd62ea1a	576	* @note This function cannot be used in a particular setup: ADC configured
NYX	0:85b3fd62ea1a	577	* in DMA mode and polling for end of each conversion (ADC init
NYX	0:85b3fd62ea1a	578	* parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
NYX	0:85b3fd62ea1a	579	* In this case, DMA resets the flag EOC and polling cannot be
NYX	0:85b3fd62ea1a	580	* performed on each conversion. Nevertheless, polling can still
NYX	0:85b3fd62ea1a	581	* be performed on the complete sequence.
NYX	0:85b3fd62ea1a	582	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	583	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	584	* @param Timeout: Timeout value in millisecond.
NYX	0:85b3fd62ea1a	585	* @retval HAL status
NYX	0:85b3fd62ea1a	586	*/
NYX	0:85b3fd62ea1a	587	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
NYX	0:85b3fd62ea1a	588	{
NYX	0:85b3fd62ea1a	589	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	590
NYX	0:85b3fd62ea1a	591	/* Verification that ADC configuration is compliant with polling for */
NYX	0:85b3fd62ea1a	592	/* each conversion: */
NYX	0:85b3fd62ea1a	593	/* Particular case is ADC configured in DMA mode and ADC sequencer with */
NYX	0:85b3fd62ea1a	594	/* several ranks and polling for end of each conversion. */
NYX	0:85b3fd62ea1a	595	/* For code simplicity sake, this particular case is generalized to */
NYX	0:85b3fd62ea1a	596	/* ADC configured in DMA mode and polling for end of each conversion. */
NYX	0:85b3fd62ea1a	597	if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
NYX	0:85b3fd62ea1a	598	HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
NYX	0:85b3fd62ea1a	599	{
NYX	0:85b3fd62ea1a	600	/* Update ADC state machine to error */
NYX	0:85b3fd62ea1a	601	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
NYX	0:85b3fd62ea1a	602
NYX	0:85b3fd62ea1a	603	/* Process unlocked */
NYX	0:85b3fd62ea1a	604	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	605
NYX	0:85b3fd62ea1a	606	return HAL_ERROR;
NYX	0:85b3fd62ea1a	607	}
NYX	0:85b3fd62ea1a	608
NYX	0:85b3fd62ea1a	609	/* Get tick */
NYX	0:85b3fd62ea1a	610	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	611
NYX	0:85b3fd62ea1a	612	/* Check End of conversion flag */
NYX	0:85b3fd62ea1a	613	while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
NYX	0:85b3fd62ea1a	614	{
NYX	0:85b3fd62ea1a	615	/* Check if timeout is disabled (set to infinite wait) */
NYX	0:85b3fd62ea1a	616	if(Timeout != HAL_MAX_DELAY)
NYX	0:85b3fd62ea1a	617	{
NYX	0:85b3fd62ea1a	618	if((Timeout == 0U) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
NYX	0:85b3fd62ea1a	619	{
NYX	0:85b3fd62ea1a	620	/* Update ADC state machine to timeout */
NYX	0:85b3fd62ea1a	621	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
NYX	0:85b3fd62ea1a	622
NYX	0:85b3fd62ea1a	623	/* Process unlocked */
NYX	0:85b3fd62ea1a	624	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	625
NYX	0:85b3fd62ea1a	626	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	627	}
NYX	0:85b3fd62ea1a	628	}
NYX	0:85b3fd62ea1a	629	}
NYX	0:85b3fd62ea1a	630
NYX	0:85b3fd62ea1a	631	/* Clear regular group conversion flag */
NYX	0:85b3fd62ea1a	632	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
NYX	0:85b3fd62ea1a	633
NYX	0:85b3fd62ea1a	634	/* Update ADC state machine */
NYX	0:85b3fd62ea1a	635	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
NYX	0:85b3fd62ea1a	636
NYX	0:85b3fd62ea1a	637	/* Determine whether any further conversion upcoming on group regular */
NYX	0:85b3fd62ea1a	638	/* by external trigger, continuous mode or scan sequence on going. */
NYX	0:85b3fd62ea1a	639	/* Note: On STM32F4, there is no independent flag of end of sequence. */
NYX	0:85b3fd62ea1a	640	/* The test of scan sequence on going is done either with scan */
NYX	0:85b3fd62ea1a	641	/* sequence disabled or with end of conversion flag set to */
NYX	0:85b3fd62ea1a	642	/* of end of sequence. */
NYX	0:85b3fd62ea1a	643	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
NYX	0:85b3fd62ea1a	644	(hadc->Init.ContinuousConvMode == DISABLE) &&
NYX	0:85b3fd62ea1a	645	(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) \|\|
NYX	0:85b3fd62ea1a	646	HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
NYX	0:85b3fd62ea1a	647	{
NYX	0:85b3fd62ea1a	648	/* Set ADC state */
NYX	0:85b3fd62ea1a	649	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
NYX	0:85b3fd62ea1a	650
NYX	0:85b3fd62ea1a	651	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
NYX	0:85b3fd62ea1a	652	{
NYX	0:85b3fd62ea1a	653	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
NYX	0:85b3fd62ea1a	654	}
NYX	0:85b3fd62ea1a	655	}
NYX	0:85b3fd62ea1a	656
NYX	0:85b3fd62ea1a	657	/* Return ADC state */
NYX	0:85b3fd62ea1a	658	return HAL_OK;
NYX	0:85b3fd62ea1a	659	}
NYX	0:85b3fd62ea1a	660
NYX	0:85b3fd62ea1a	661	/**
NYX	0:85b3fd62ea1a	662	* @brief Poll for conversion event
NYX	0:85b3fd62ea1a	663	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	664	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	665	* @param EventType: the ADC event type.
NYX	0:85b3fd62ea1a	666	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	667	* @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
NYX	0:85b3fd62ea1a	668	* @arg ADC_OVR_EVENT: ADC Overrun event.
NYX	0:85b3fd62ea1a	669	* @param Timeout: Timeout value in millisecond.
NYX	0:85b3fd62ea1a	670	* @retval HAL status
NYX	0:85b3fd62ea1a	671	*/
NYX	0:85b3fd62ea1a	672	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
NYX	0:85b3fd62ea1a	673	{
NYX	0:85b3fd62ea1a	674	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	675
NYX	0:85b3fd62ea1a	676	/* Check the parameters */
NYX	0:85b3fd62ea1a	677	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
NYX	0:85b3fd62ea1a	678	assert_param(IS_ADC_EVENT_TYPE(EventType));
NYX	0:85b3fd62ea1a	679
NYX	0:85b3fd62ea1a	680	/* Get tick */
NYX	0:85b3fd62ea1a	681	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	682
NYX	0:85b3fd62ea1a	683	/* Check selected event flag */
NYX	0:85b3fd62ea1a	684	while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
NYX	0:85b3fd62ea1a	685	{
NYX	0:85b3fd62ea1a	686	/* Check for the Timeout */
NYX	0:85b3fd62ea1a	687	if(Timeout != HAL_MAX_DELAY)
NYX	0:85b3fd62ea1a	688	{
NYX	0:85b3fd62ea1a	689	if((Timeout == 0U) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
NYX	0:85b3fd62ea1a	690	{
NYX	0:85b3fd62ea1a	691	/* Update ADC state machine to timeout */
NYX	0:85b3fd62ea1a	692	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
NYX	0:85b3fd62ea1a	693
NYX	0:85b3fd62ea1a	694	/* Process unlocked */
NYX	0:85b3fd62ea1a	695	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	696
NYX	0:85b3fd62ea1a	697	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	698	}
NYX	0:85b3fd62ea1a	699	}
NYX	0:85b3fd62ea1a	700	}
NYX	0:85b3fd62ea1a	701
NYX	0:85b3fd62ea1a	702	/* Analog watchdog (level out of window) event */
NYX	0:85b3fd62ea1a	703	if(EventType == ADC_AWD_EVENT)
NYX	0:85b3fd62ea1a	704	{
NYX	0:85b3fd62ea1a	705	/* Set ADC state */
NYX	0:85b3fd62ea1a	706	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
NYX	0:85b3fd62ea1a	707
NYX	0:85b3fd62ea1a	708	/* Clear ADC analog watchdog flag */
NYX	0:85b3fd62ea1a	709	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
NYX	0:85b3fd62ea1a	710	}
NYX	0:85b3fd62ea1a	711	/* Overrun event */
NYX	0:85b3fd62ea1a	712	else
NYX	0:85b3fd62ea1a	713	{
NYX	0:85b3fd62ea1a	714	/* Set ADC state */
NYX	0:85b3fd62ea1a	715	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
NYX	0:85b3fd62ea1a	716	/* Set ADC error code to overrun */
NYX	0:85b3fd62ea1a	717	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
NYX	0:85b3fd62ea1a	718
NYX	0:85b3fd62ea1a	719	/* Clear ADC overrun flag */
NYX	0:85b3fd62ea1a	720	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
NYX	0:85b3fd62ea1a	721	}
NYX	0:85b3fd62ea1a	722
NYX	0:85b3fd62ea1a	723	/* Return ADC state */
NYX	0:85b3fd62ea1a	724	return HAL_OK;
NYX	0:85b3fd62ea1a	725	}
NYX	0:85b3fd62ea1a	726
NYX	0:85b3fd62ea1a	727
NYX	0:85b3fd62ea1a	728	/**
NYX	0:85b3fd62ea1a	729	* @brief Enables the interrupt and starts ADC conversion of regular channels.
NYX	0:85b3fd62ea1a	730	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	731	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	732	* @retval HAL status.
NYX	0:85b3fd62ea1a	733	*/
NYX	0:85b3fd62ea1a	734	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	735	{
NYX	0:85b3fd62ea1a	736	__IO uint32_t counter = 0U;
NYX	0:85b3fd62ea1a	737	ADC_Common_TypeDef *tmpADC_Common;
NYX	0:85b3fd62ea1a	738
NYX	0:85b3fd62ea1a	739	/* Check the parameters */
NYX	0:85b3fd62ea1a	740	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
NYX	0:85b3fd62ea1a	741	assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
NYX	0:85b3fd62ea1a	742
NYX	0:85b3fd62ea1a	743	/* Process locked */
NYX	0:85b3fd62ea1a	744	__HAL_LOCK(hadc);
NYX	0:85b3fd62ea1a	745
NYX	0:85b3fd62ea1a	746	/* Enable the ADC peripheral */
NYX	0:85b3fd62ea1a	747	/* Check if ADC peripheral is disabled in order to enable it and wait during
NYX	0:85b3fd62ea1a	748	Tstab time the ADC's stabilization */
NYX	0:85b3fd62ea1a	749	if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
NYX	0:85b3fd62ea1a	750	{
NYX	0:85b3fd62ea1a	751	/* Enable the Peripheral */
NYX	0:85b3fd62ea1a	752	__HAL_ADC_ENABLE(hadc);
NYX	0:85b3fd62ea1a	753
NYX	0:85b3fd62ea1a	754	/* Delay for ADC stabilization time */
NYX	0:85b3fd62ea1a	755	/* Compute number of CPU cycles to wait for */
NYX	0:85b3fd62ea1a	756	counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
NYX	0:85b3fd62ea1a	757	while(counter != 0U)
NYX	0:85b3fd62ea1a	758	{
NYX	0:85b3fd62ea1a	759	counter--;
NYX	0:85b3fd62ea1a	760	}
NYX	0:85b3fd62ea1a	761	}
NYX	0:85b3fd62ea1a	762
NYX	0:85b3fd62ea1a	763	/* Start conversion if ADC is effectively enabled */
NYX	0:85b3fd62ea1a	764	if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
NYX	0:85b3fd62ea1a	765	{
NYX	0:85b3fd62ea1a	766	/* Set ADC state */
NYX	0:85b3fd62ea1a	767	/* - Clear state bitfield related to regular group conversion results */
NYX	0:85b3fd62ea1a	768	/* - Set state bitfield related to regular group operation */
NYX	0:85b3fd62ea1a	769	ADC_STATE_CLR_SET(hadc->State,
NYX	0:85b3fd62ea1a	770	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR,
NYX	0:85b3fd62ea1a	771	HAL_ADC_STATE_REG_BUSY);
NYX	0:85b3fd62ea1a	772
NYX	0:85b3fd62ea1a	773	/* If conversions on group regular are also triggering group injected, */
NYX	0:85b3fd62ea1a	774	/* update ADC state. */
NYX	0:85b3fd62ea1a	775	if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
NYX	0:85b3fd62ea1a	776	{
NYX	0:85b3fd62ea1a	777	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
NYX	0:85b3fd62ea1a	778	}
NYX	0:85b3fd62ea1a	779
NYX	0:85b3fd62ea1a	780	/* State machine update: Check if an injected conversion is ongoing */
NYX	0:85b3fd62ea1a	781	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
NYX	0:85b3fd62ea1a	782	{
NYX	0:85b3fd62ea1a	783	/* Reset ADC error code fields related to conversions on group regular */
NYX	0:85b3fd62ea1a	784	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
NYX	0:85b3fd62ea1a	785	}
NYX	0:85b3fd62ea1a	786	else
NYX	0:85b3fd62ea1a	787	{
NYX	0:85b3fd62ea1a	788	/* Reset ADC all error code fields */
NYX	0:85b3fd62ea1a	789	ADC_CLEAR_ERRORCODE(hadc);
NYX	0:85b3fd62ea1a	790	}
NYX	0:85b3fd62ea1a	791
NYX	0:85b3fd62ea1a	792	/* Process unlocked */
NYX	0:85b3fd62ea1a	793	/* Unlock before starting ADC conversions: in case of potential */
NYX	0:85b3fd62ea1a	794	/* interruption, to let the process to ADC IRQ Handler. */
NYX	0:85b3fd62ea1a	795	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	796
NYX	0:85b3fd62ea1a	797	/* Pointer to the common control register to which is belonging hadc */
NYX	0:85b3fd62ea1a	798	/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
NYX	0:85b3fd62ea1a	799	/* control register) */
NYX	0:85b3fd62ea1a	800	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
NYX	0:85b3fd62ea1a	801
NYX	0:85b3fd62ea1a	802	/* Clear regular group conversion flag and overrun flag */
NYX	0:85b3fd62ea1a	803	/* (To ensure of no unknown state from potential previous ADC operations) */
NYX	0:85b3fd62ea1a	804	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC \| ADC_FLAG_OVR);
NYX	0:85b3fd62ea1a	805
NYX	0:85b3fd62ea1a	806	/* Enable end of conversion interrupt for regular group */
NYX	0:85b3fd62ea1a	807	__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_OVR));
NYX	0:85b3fd62ea1a	808
NYX	0:85b3fd62ea1a	809	/* Check if Multimode enabled */
NYX	0:85b3fd62ea1a	810	if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
NYX	0:85b3fd62ea1a	811	{
NYX	0:85b3fd62ea1a	812	/* if no external trigger present enable software conversion of regular channels */
NYX	0:85b3fd62ea1a	813	if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
NYX	0:85b3fd62ea1a	814	{
NYX	0:85b3fd62ea1a	815	/* Enable the selected ADC software conversion for regular group */
NYX	0:85b3fd62ea1a	816	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
NYX	0:85b3fd62ea1a	817	}
NYX	0:85b3fd62ea1a	818	}
NYX	0:85b3fd62ea1a	819	else
NYX	0:85b3fd62ea1a	820	{
NYX	0:85b3fd62ea1a	821	/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
NYX	0:85b3fd62ea1a	822	if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
NYX	0:85b3fd62ea1a	823	{
NYX	0:85b3fd62ea1a	824	/* Enable the selected ADC software conversion for regular group */
NYX	0:85b3fd62ea1a	825	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
NYX	0:85b3fd62ea1a	826	}
NYX	0:85b3fd62ea1a	827	}
NYX	0:85b3fd62ea1a	828	}
NYX	0:85b3fd62ea1a	829
NYX	0:85b3fd62ea1a	830	/* Return function status */
NYX	0:85b3fd62ea1a	831	return HAL_OK;
NYX	0:85b3fd62ea1a	832	}
NYX	0:85b3fd62ea1a	833
NYX	0:85b3fd62ea1a	834	/**
NYX	0:85b3fd62ea1a	835	* @brief Disables the interrupt and stop ADC conversion of regular channels.
NYX	0:85b3fd62ea1a	836	*
NYX	0:85b3fd62ea1a	837	* @note Caution: This function will stop also injected channels.
NYX	0:85b3fd62ea1a	838	*
NYX	0:85b3fd62ea1a	839	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	840	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	841	* @retval HAL status.
NYX	0:85b3fd62ea1a	842	*/
NYX	0:85b3fd62ea1a	843	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	844	{
NYX	0:85b3fd62ea1a	845	/* Check the parameters */
NYX	0:85b3fd62ea1a	846	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
NYX	0:85b3fd62ea1a	847
NYX	0:85b3fd62ea1a	848	/* Process locked */
NYX	0:85b3fd62ea1a	849	__HAL_LOCK(hadc);
NYX	0:85b3fd62ea1a	850
NYX	0:85b3fd62ea1a	851	/* Stop potential conversion on going, on regular and injected groups */
NYX	0:85b3fd62ea1a	852	/* Disable ADC peripheral */
NYX	0:85b3fd62ea1a	853	__HAL_ADC_DISABLE(hadc);
NYX	0:85b3fd62ea1a	854
NYX	0:85b3fd62ea1a	855	/* Check if ADC is effectively disabled */
NYX	0:85b3fd62ea1a	856	if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
NYX	0:85b3fd62ea1a	857	{
NYX	0:85b3fd62ea1a	858	/* Disable ADC end of conversion interrupt for regular group */
NYX	0:85b3fd62ea1a	859	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_OVR));
NYX	0:85b3fd62ea1a	860
NYX	0:85b3fd62ea1a	861	/* Set ADC state */
NYX	0:85b3fd62ea1a	862	ADC_STATE_CLR_SET(hadc->State,
NYX	0:85b3fd62ea1a	863	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
NYX	0:85b3fd62ea1a	864	HAL_ADC_STATE_READY);
NYX	0:85b3fd62ea1a	865	}
NYX	0:85b3fd62ea1a	866
NYX	0:85b3fd62ea1a	867	/* Process unlocked */
NYX	0:85b3fd62ea1a	868	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	869
NYX	0:85b3fd62ea1a	870	/* Return function status */
NYX	0:85b3fd62ea1a	871	return HAL_OK;
NYX	0:85b3fd62ea1a	872	}
NYX	0:85b3fd62ea1a	873
NYX	0:85b3fd62ea1a	874	/**
NYX	0:85b3fd62ea1a	875	* @brief Handles ADC interrupt request
NYX	0:85b3fd62ea1a	876	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	877	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	878	* @retval None
NYX	0:85b3fd62ea1a	879	*/
NYX	0:85b3fd62ea1a	880	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	881	{
NYX	0:85b3fd62ea1a	882	uint32_t tmp1 = 0U, tmp2 = 0U;
NYX	0:85b3fd62ea1a	883
NYX	0:85b3fd62ea1a	884	/* Check the parameters */
NYX	0:85b3fd62ea1a	885	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
NYX	0:85b3fd62ea1a	886	assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
NYX	0:85b3fd62ea1a	887	assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
NYX	0:85b3fd62ea1a	888
NYX	0:85b3fd62ea1a	889	tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
NYX	0:85b3fd62ea1a	890	tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
NYX	0:85b3fd62ea1a	891	/* Check End of conversion flag for regular channels */
NYX	0:85b3fd62ea1a	892	if(tmp1 && tmp2)
NYX	0:85b3fd62ea1a	893	{
NYX	0:85b3fd62ea1a	894	/* Update state machine on conversion status if not in error state */
NYX	0:85b3fd62ea1a	895	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
NYX	0:85b3fd62ea1a	896	{
NYX	0:85b3fd62ea1a	897	/* Set ADC state */
NYX	0:85b3fd62ea1a	898	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
NYX	0:85b3fd62ea1a	899	}
NYX	0:85b3fd62ea1a	900
NYX	0:85b3fd62ea1a	901	/* Determine whether any further conversion upcoming on group regular */
NYX	0:85b3fd62ea1a	902	/* by external trigger, continuous mode or scan sequence on going. */
NYX	0:85b3fd62ea1a	903	/* Note: On STM32F4, there is no independent flag of end of sequence. */
NYX	0:85b3fd62ea1a	904	/* The test of scan sequence on going is done either with scan */
NYX	0:85b3fd62ea1a	905	/* sequence disabled or with end of conversion flag set to */
NYX	0:85b3fd62ea1a	906	/* of end of sequence. */
NYX	0:85b3fd62ea1a	907	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
NYX	0:85b3fd62ea1a	908	(hadc->Init.ContinuousConvMode == DISABLE) &&
NYX	0:85b3fd62ea1a	909	(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) \|\|
NYX	0:85b3fd62ea1a	910	HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
NYX	0:85b3fd62ea1a	911	{
NYX	0:85b3fd62ea1a	912	/* Disable ADC end of single conversion interrupt on group regular */
NYX	0:85b3fd62ea1a	913	/* Note: Overrun interrupt was enabled with EOC interrupt in */
NYX	0:85b3fd62ea1a	914	/* HAL_ADC_Start_IT(), but is not disabled here because can be used */
NYX	0:85b3fd62ea1a	915	/* by overrun IRQ process below. */
NYX	0:85b3fd62ea1a	916	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
NYX	0:85b3fd62ea1a	917
NYX	0:85b3fd62ea1a	918	/* Set ADC state */
NYX	0:85b3fd62ea1a	919	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
NYX	0:85b3fd62ea1a	920
NYX	0:85b3fd62ea1a	921	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
NYX	0:85b3fd62ea1a	922	{
NYX	0:85b3fd62ea1a	923	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
NYX	0:85b3fd62ea1a	924	}
NYX	0:85b3fd62ea1a	925	}
NYX	0:85b3fd62ea1a	926
NYX	0:85b3fd62ea1a	927	/* Conversion complete callback */
NYX	0:85b3fd62ea1a	928	HAL_ADC_ConvCpltCallback(hadc);
NYX	0:85b3fd62ea1a	929
NYX	0:85b3fd62ea1a	930	/* Clear regular group conversion flag */
NYX	0:85b3fd62ea1a	931	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
NYX	0:85b3fd62ea1a	932	}
NYX	0:85b3fd62ea1a	933
NYX	0:85b3fd62ea1a	934	tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
NYX	0:85b3fd62ea1a	935	tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
NYX	0:85b3fd62ea1a	936	/* Check End of conversion flag for injected channels */
NYX	0:85b3fd62ea1a	937	if(tmp1 && tmp2)
NYX	0:85b3fd62ea1a	938	{
NYX	0:85b3fd62ea1a	939	/* Update state machine on conversion status if not in error state */
NYX	0:85b3fd62ea1a	940	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
NYX	0:85b3fd62ea1a	941	{
NYX	0:85b3fd62ea1a	942	/* Set ADC state */
NYX	0:85b3fd62ea1a	943	SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
NYX	0:85b3fd62ea1a	944	}
NYX	0:85b3fd62ea1a	945
NYX	0:85b3fd62ea1a	946	/* Determine whether any further conversion upcoming on group injected */
NYX	0:85b3fd62ea1a	947	/* by external trigger, scan sequence on going or by automatic injected */
NYX	0:85b3fd62ea1a	948	/* conversion from group regular (same conditions as group regular */
NYX	0:85b3fd62ea1a	949	/* interruption disabling above). */
NYX	0:85b3fd62ea1a	950	if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
NYX	0:85b3fd62ea1a	951	(HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) \|\|
NYX	0:85b3fd62ea1a	952	HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
NYX	0:85b3fd62ea1a	953	(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
NYX	0:85b3fd62ea1a	954	(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
NYX	0:85b3fd62ea1a	955	(hadc->Init.ContinuousConvMode == DISABLE) ) ) )
NYX	0:85b3fd62ea1a	956	{
NYX	0:85b3fd62ea1a	957	/* Disable ADC end of single conversion interrupt on group injected */
NYX	0:85b3fd62ea1a	958	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
NYX	0:85b3fd62ea1a	959
NYX	0:85b3fd62ea1a	960	/* Set ADC state */
NYX	0:85b3fd62ea1a	961	CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
NYX	0:85b3fd62ea1a	962
NYX	0:85b3fd62ea1a	963	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
NYX	0:85b3fd62ea1a	964	{
NYX	0:85b3fd62ea1a	965	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
NYX	0:85b3fd62ea1a	966	}
NYX	0:85b3fd62ea1a	967	}
NYX	0:85b3fd62ea1a	968
NYX	0:85b3fd62ea1a	969	/* Conversion complete callback */
NYX	0:85b3fd62ea1a	970	HAL_ADCEx_InjectedConvCpltCallback(hadc);
NYX	0:85b3fd62ea1a	971
NYX	0:85b3fd62ea1a	972	/* Clear injected group conversion flag */
NYX	0:85b3fd62ea1a	973	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT \| ADC_FLAG_JEOC));
NYX	0:85b3fd62ea1a	974	}
NYX	0:85b3fd62ea1a	975
NYX	0:85b3fd62ea1a	976	tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
NYX	0:85b3fd62ea1a	977	tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
NYX	0:85b3fd62ea1a	978	/* Check Analog watchdog flag */
NYX	0:85b3fd62ea1a	979	if(tmp1 && tmp2)
NYX	0:85b3fd62ea1a	980	{
NYX	0:85b3fd62ea1a	981	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
NYX	0:85b3fd62ea1a	982	{
NYX	0:85b3fd62ea1a	983	/* Set ADC state */
NYX	0:85b3fd62ea1a	984	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
NYX	0:85b3fd62ea1a	985
NYX	0:85b3fd62ea1a	986	/* Level out of window callback */
NYX	0:85b3fd62ea1a	987	HAL_ADC_LevelOutOfWindowCallback(hadc);
NYX	0:85b3fd62ea1a	988
NYX	0:85b3fd62ea1a	989	/* Clear the ADC analog watchdog flag */
NYX	0:85b3fd62ea1a	990	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
NYX	0:85b3fd62ea1a	991	}
NYX	0:85b3fd62ea1a	992	}
NYX	0:85b3fd62ea1a	993
NYX	0:85b3fd62ea1a	994	tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
NYX	0:85b3fd62ea1a	995	tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
NYX	0:85b3fd62ea1a	996	/* Check Overrun flag */
NYX	0:85b3fd62ea1a	997	if(tmp1 && tmp2)
NYX	0:85b3fd62ea1a	998	{
NYX	0:85b3fd62ea1a	999	/* Note: On STM32F4, ADC overrun can be set through other parameters */
NYX	0:85b3fd62ea1a	1000	/* refer to description of parameter "EOCSelection" for more */
NYX	0:85b3fd62ea1a	1001	/* details. */
NYX	0:85b3fd62ea1a	1002
NYX	0:85b3fd62ea1a	1003	/* Set ADC error code to overrun */
NYX	0:85b3fd62ea1a	1004	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
NYX	0:85b3fd62ea1a	1005
NYX	0:85b3fd62ea1a	1006	/* Clear ADC overrun flag */
NYX	0:85b3fd62ea1a	1007	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
NYX	0:85b3fd62ea1a	1008
NYX	0:85b3fd62ea1a	1009	/* Error callback */
NYX	0:85b3fd62ea1a	1010	HAL_ADC_ErrorCallback(hadc);
NYX	0:85b3fd62ea1a	1011
NYX	0:85b3fd62ea1a	1012	/* Clear the Overrun flag */
NYX	0:85b3fd62ea1a	1013	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
NYX	0:85b3fd62ea1a	1014	}
NYX	0:85b3fd62ea1a	1015	}
NYX	0:85b3fd62ea1a	1016
NYX	0:85b3fd62ea1a	1017	/**
NYX	0:85b3fd62ea1a	1018	* @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
NYX	0:85b3fd62ea1a	1019	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1020	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1021	* @param pData: The destination Buffer address.
NYX	0:85b3fd62ea1a	1022	* @param Length: The length of data to be transferred from ADC peripheral to memory.
NYX	0:85b3fd62ea1a	1023	* @retval HAL status
NYX	0:85b3fd62ea1a	1024	*/
NYX	0:85b3fd62ea1a	1025	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
NYX	0:85b3fd62ea1a	1026	{
NYX	0:85b3fd62ea1a	1027	__IO uint32_t counter = 0U;
NYX	0:85b3fd62ea1a	1028	ADC_Common_TypeDef *tmpADC_Common;
NYX	0:85b3fd62ea1a	1029
NYX	0:85b3fd62ea1a	1030	/* Check the parameters */
NYX	0:85b3fd62ea1a	1031	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
NYX	0:85b3fd62ea1a	1032	assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
NYX	0:85b3fd62ea1a	1033
NYX	0:85b3fd62ea1a	1034	/* Process locked */
NYX	0:85b3fd62ea1a	1035	__HAL_LOCK(hadc);
NYX	0:85b3fd62ea1a	1036
NYX	0:85b3fd62ea1a	1037	/* Enable the ADC peripheral */
NYX	0:85b3fd62ea1a	1038	/* Check if ADC peripheral is disabled in order to enable it and wait during
NYX	0:85b3fd62ea1a	1039	Tstab time the ADC's stabilization */
NYX	0:85b3fd62ea1a	1040	if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
NYX	0:85b3fd62ea1a	1041	{
NYX	0:85b3fd62ea1a	1042	/* Enable the Peripheral */
NYX	0:85b3fd62ea1a	1043	__HAL_ADC_ENABLE(hadc);
NYX	0:85b3fd62ea1a	1044
NYX	0:85b3fd62ea1a	1045	/* Delay for ADC stabilization time */
NYX	0:85b3fd62ea1a	1046	/* Compute number of CPU cycles to wait for */
NYX	0:85b3fd62ea1a	1047	counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
NYX	0:85b3fd62ea1a	1048	while(counter != 0U)
NYX	0:85b3fd62ea1a	1049	{
NYX	0:85b3fd62ea1a	1050	counter--;
NYX	0:85b3fd62ea1a	1051	}
NYX	0:85b3fd62ea1a	1052	}
NYX	0:85b3fd62ea1a	1053
NYX	0:85b3fd62ea1a	1054	/* Start conversion if ADC is effectively enabled */
NYX	0:85b3fd62ea1a	1055	if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
NYX	0:85b3fd62ea1a	1056	{
NYX	0:85b3fd62ea1a	1057	/* Set ADC state */
NYX	0:85b3fd62ea1a	1058	/* - Clear state bitfield related to regular group conversion results */
NYX	0:85b3fd62ea1a	1059	/* - Set state bitfield related to regular group operation */
NYX	0:85b3fd62ea1a	1060	ADC_STATE_CLR_SET(hadc->State,
NYX	0:85b3fd62ea1a	1061	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR,
NYX	0:85b3fd62ea1a	1062	HAL_ADC_STATE_REG_BUSY);
NYX	0:85b3fd62ea1a	1063
NYX	0:85b3fd62ea1a	1064	/* If conversions on group regular are also triggering group injected, */
NYX	0:85b3fd62ea1a	1065	/* update ADC state. */
NYX	0:85b3fd62ea1a	1066	if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
NYX	0:85b3fd62ea1a	1067	{
NYX	0:85b3fd62ea1a	1068	ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
NYX	0:85b3fd62ea1a	1069	}
NYX	0:85b3fd62ea1a	1070
NYX	0:85b3fd62ea1a	1071	/* State machine update: Check if an injected conversion is ongoing */
NYX	0:85b3fd62ea1a	1072	if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
NYX	0:85b3fd62ea1a	1073	{
NYX	0:85b3fd62ea1a	1074	/* Reset ADC error code fields related to conversions on group regular */
NYX	0:85b3fd62ea1a	1075	CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR \| HAL_ADC_ERROR_DMA));
NYX	0:85b3fd62ea1a	1076	}
NYX	0:85b3fd62ea1a	1077	else
NYX	0:85b3fd62ea1a	1078	{
NYX	0:85b3fd62ea1a	1079	/* Reset ADC all error code fields */
NYX	0:85b3fd62ea1a	1080	ADC_CLEAR_ERRORCODE(hadc);
NYX	0:85b3fd62ea1a	1081	}
NYX	0:85b3fd62ea1a	1082
NYX	0:85b3fd62ea1a	1083	/* Process unlocked */
NYX	0:85b3fd62ea1a	1084	/* Unlock before starting ADC conversions: in case of potential */
NYX	0:85b3fd62ea1a	1085	/* interruption, to let the process to ADC IRQ Handler. */
NYX	0:85b3fd62ea1a	1086	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	1087
NYX	0:85b3fd62ea1a	1088	/* Pointer to the common control register to which is belonging hadc */
NYX	0:85b3fd62ea1a	1089	/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
NYX	0:85b3fd62ea1a	1090	/* control register) */
NYX	0:85b3fd62ea1a	1091	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
NYX	0:85b3fd62ea1a	1092
NYX	0:85b3fd62ea1a	1093	/* Set the DMA transfer complete callback */
NYX	0:85b3fd62ea1a	1094	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
NYX	0:85b3fd62ea1a	1095
NYX	0:85b3fd62ea1a	1096	/* Set the DMA half transfer complete callback */
NYX	0:85b3fd62ea1a	1097	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
NYX	0:85b3fd62ea1a	1098
NYX	0:85b3fd62ea1a	1099	/* Set the DMA error callback */
NYX	0:85b3fd62ea1a	1100	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
NYX	0:85b3fd62ea1a	1101
NYX	0:85b3fd62ea1a	1102
NYX	0:85b3fd62ea1a	1103	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
NYX	0:85b3fd62ea1a	1104	/* start (in case of SW start): */
NYX	0:85b3fd62ea1a	1105
NYX	0:85b3fd62ea1a	1106	/* Clear regular group conversion flag and overrun flag */
NYX	0:85b3fd62ea1a	1107	/* (To ensure of no unknown state from potential previous ADC operations) */
NYX	0:85b3fd62ea1a	1108	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC \| ADC_FLAG_OVR);
NYX	0:85b3fd62ea1a	1109
NYX	0:85b3fd62ea1a	1110	/* Enable ADC overrun interrupt */
NYX	0:85b3fd62ea1a	1111	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
NYX	0:85b3fd62ea1a	1112
NYX	0:85b3fd62ea1a	1113	/* Enable ADC DMA mode */
NYX	0:85b3fd62ea1a	1114	hadc->Instance->CR2 \|= ADC_CR2_DMA;
NYX	0:85b3fd62ea1a	1115
NYX	0:85b3fd62ea1a	1116	/* Start the DMA channel */
NYX	0:85b3fd62ea1a	1117	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
NYX	0:85b3fd62ea1a	1118
NYX	0:85b3fd62ea1a	1119	/* Check if Multimode enabled */
NYX	0:85b3fd62ea1a	1120	if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
NYX	0:85b3fd62ea1a	1121	{
NYX	0:85b3fd62ea1a	1122	/* if no external trigger present enable software conversion of regular channels */
NYX	0:85b3fd62ea1a	1123	if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
NYX	0:85b3fd62ea1a	1124	{
NYX	0:85b3fd62ea1a	1125	/* Enable the selected ADC software conversion for regular group */
NYX	0:85b3fd62ea1a	1126	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
NYX	0:85b3fd62ea1a	1127	}
NYX	0:85b3fd62ea1a	1128	}
NYX	0:85b3fd62ea1a	1129	else
NYX	0:85b3fd62ea1a	1130	{
NYX	0:85b3fd62ea1a	1131	/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
NYX	0:85b3fd62ea1a	1132	if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
NYX	0:85b3fd62ea1a	1133	{
NYX	0:85b3fd62ea1a	1134	/* Enable the selected ADC software conversion for regular group */
NYX	0:85b3fd62ea1a	1135	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
NYX	0:85b3fd62ea1a	1136	}
NYX	0:85b3fd62ea1a	1137	}
NYX	0:85b3fd62ea1a	1138	}
NYX	0:85b3fd62ea1a	1139
NYX	0:85b3fd62ea1a	1140	/* Return function status */
NYX	0:85b3fd62ea1a	1141	return HAL_OK;
NYX	0:85b3fd62ea1a	1142	}
NYX	0:85b3fd62ea1a	1143
NYX	0:85b3fd62ea1a	1144	/**
NYX	0:85b3fd62ea1a	1145	* @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
NYX	0:85b3fd62ea1a	1146	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1147	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1148	* @retval HAL status
NYX	0:85b3fd62ea1a	1149	*/
NYX	0:85b3fd62ea1a	1150	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	1151	{
NYX	0:85b3fd62ea1a	1152	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
NYX	0:85b3fd62ea1a	1153
NYX	0:85b3fd62ea1a	1154	/* Check the parameters */
NYX	0:85b3fd62ea1a	1155	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
NYX	0:85b3fd62ea1a	1156
NYX	0:85b3fd62ea1a	1157	/* Process locked */
NYX	0:85b3fd62ea1a	1158	__HAL_LOCK(hadc);
NYX	0:85b3fd62ea1a	1159
NYX	0:85b3fd62ea1a	1160	/* Stop potential conversion on going, on regular and injected groups */
NYX	0:85b3fd62ea1a	1161	/* Disable ADC peripheral */
NYX	0:85b3fd62ea1a	1162	__HAL_ADC_DISABLE(hadc);
NYX	0:85b3fd62ea1a	1163
NYX	0:85b3fd62ea1a	1164	/* Check if ADC is effectively disabled */
NYX	0:85b3fd62ea1a	1165	if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
NYX	0:85b3fd62ea1a	1166	{
NYX	0:85b3fd62ea1a	1167	/* Disable the selected ADC DMA mode */
NYX	0:85b3fd62ea1a	1168	hadc->Instance->CR2 &= ~ADC_CR2_DMA;
NYX	0:85b3fd62ea1a	1169
NYX	0:85b3fd62ea1a	1170	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
NYX	0:85b3fd62ea1a	1171	/* DMA transfer is on going) */
NYX	0:85b3fd62ea1a	1172	tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
NYX	0:85b3fd62ea1a	1173
NYX	0:85b3fd62ea1a	1174	/* Disable ADC overrun interrupt */
NYX	0:85b3fd62ea1a	1175	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
NYX	0:85b3fd62ea1a	1176
NYX	0:85b3fd62ea1a	1177	/* Set ADC state */
NYX	0:85b3fd62ea1a	1178	ADC_STATE_CLR_SET(hadc->State,
NYX	0:85b3fd62ea1a	1179	HAL_ADC_STATE_REG_BUSY \| HAL_ADC_STATE_INJ_BUSY,
NYX	0:85b3fd62ea1a	1180	HAL_ADC_STATE_READY);
NYX	0:85b3fd62ea1a	1181	}
NYX	0:85b3fd62ea1a	1182
NYX	0:85b3fd62ea1a	1183	/* Process unlocked */
NYX	0:85b3fd62ea1a	1184	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	1185
NYX	0:85b3fd62ea1a	1186	/* Return function status */
NYX	0:85b3fd62ea1a	1187	return tmp_hal_status;
NYX	0:85b3fd62ea1a	1188	}
NYX	0:85b3fd62ea1a	1189
NYX	0:85b3fd62ea1a	1190	/**
NYX	0:85b3fd62ea1a	1191	* @brief Gets the converted value from data register of regular channel.
NYX	0:85b3fd62ea1a	1192	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1193	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1194	* @retval Converted value
NYX	0:85b3fd62ea1a	1195	*/
NYX	0:85b3fd62ea1a	1196	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	1197	{
NYX	0:85b3fd62ea1a	1198	/* Return the selected ADC converted value */
NYX	0:85b3fd62ea1a	1199	return hadc->Instance->DR;
NYX	0:85b3fd62ea1a	1200	}
NYX	0:85b3fd62ea1a	1201
NYX	0:85b3fd62ea1a	1202	/**
NYX	0:85b3fd62ea1a	1203	* @brief Regular conversion complete callback in non blocking mode
NYX	0:85b3fd62ea1a	1204	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1205	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1206	* @retval None
NYX	0:85b3fd62ea1a	1207	*/
NYX	0:85b3fd62ea1a	1208	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	1209	{
NYX	0:85b3fd62ea1a	1210	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1211	UNUSED(hadc);
NYX	0:85b3fd62ea1a	1212	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1213	the HAL_ADC_ConvCpltCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1214	*/
NYX	0:85b3fd62ea1a	1215	}
NYX	0:85b3fd62ea1a	1216
NYX	0:85b3fd62ea1a	1217	/**
NYX	0:85b3fd62ea1a	1218	* @brief Regular conversion half DMA transfer callback in non blocking mode
NYX	0:85b3fd62ea1a	1219	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1220	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1221	* @retval None
NYX	0:85b3fd62ea1a	1222	*/
NYX	0:85b3fd62ea1a	1223	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	1224	{
NYX	0:85b3fd62ea1a	1225	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1226	UNUSED(hadc);
NYX	0:85b3fd62ea1a	1227	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1228	the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1229	*/
NYX	0:85b3fd62ea1a	1230	}
NYX	0:85b3fd62ea1a	1231
NYX	0:85b3fd62ea1a	1232	/**
NYX	0:85b3fd62ea1a	1233	* @brief Analog watchdog callback in non blocking mode
NYX	0:85b3fd62ea1a	1234	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1235	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1236	* @retval None
NYX	0:85b3fd62ea1a	1237	*/
NYX	0:85b3fd62ea1a	1238	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	1239	{
NYX	0:85b3fd62ea1a	1240	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1241	UNUSED(hadc);
NYX	0:85b3fd62ea1a	1242	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1243	the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1244	*/
NYX	0:85b3fd62ea1a	1245	}
NYX	0:85b3fd62ea1a	1246
NYX	0:85b3fd62ea1a	1247	/**
NYX	0:85b3fd62ea1a	1248	* @brief Error ADC callback.
NYX	0:85b3fd62ea1a	1249	* @note In case of error due to overrun when using ADC with DMA transfer
NYX	0:85b3fd62ea1a	1250	* (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
NYX	0:85b3fd62ea1a	1251	* - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
NYX	0:85b3fd62ea1a	1252	* - If needed, restart a new ADC conversion using function
NYX	0:85b3fd62ea1a	1253	* "HAL_ADC_Start_DMA()"
NYX	0:85b3fd62ea1a	1254	* (this function is also clearing overrun flag)
NYX	0:85b3fd62ea1a	1255	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1256	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1257	* @retval None
NYX	0:85b3fd62ea1a	1258	*/
NYX	0:85b3fd62ea1a	1259	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
NYX	0:85b3fd62ea1a	1260	{
NYX	0:85b3fd62ea1a	1261	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	1262	UNUSED(hadc);
NYX	0:85b3fd62ea1a	1263	/* NOTE : This function Should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	1264	the HAL_ADC_ErrorCallback could be implemented in the user file
NYX	0:85b3fd62ea1a	1265	*/
NYX	0:85b3fd62ea1a	1266	}
NYX	0:85b3fd62ea1a	1267
NYX	0:85b3fd62ea1a	1268	/**
NYX	0:85b3fd62ea1a	1269	* @}
NYX	0:85b3fd62ea1a	1270	*/
NYX	0:85b3fd62ea1a	1271
NYX	0:85b3fd62ea1a	1272	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
NYX	0:85b3fd62ea1a	1273	* @brief Peripheral Control functions
NYX	0:85b3fd62ea1a	1274	*
NYX	0:85b3fd62ea1a	1275	@verbatim
NYX	0:85b3fd62ea1a	1276	===============================================================================
NYX	0:85b3fd62ea1a	1277	##### Peripheral Control functions #####
NYX	0:85b3fd62ea1a	1278	===============================================================================
NYX	0:85b3fd62ea1a	1279	[..] This section provides functions allowing to:
NYX	0:85b3fd62ea1a	1280	(+) Configure regular channels.
NYX	0:85b3fd62ea1a	1281	(+) Configure injected channels.
NYX	0:85b3fd62ea1a	1282	(+) Configure multimode.
NYX	0:85b3fd62ea1a	1283	(+) Configure the analog watch dog.
NYX	0:85b3fd62ea1a	1284
NYX	0:85b3fd62ea1a	1285	@endverbatim
NYX	0:85b3fd62ea1a	1286	* @{
NYX	0:85b3fd62ea1a	1287	*/
NYX	0:85b3fd62ea1a	1288
NYX	0:85b3fd62ea1a	1289	/**
NYX	0:85b3fd62ea1a	1290	* @brief Configures for the selected ADC regular channel its corresponding
NYX	0:85b3fd62ea1a	1291	* rank in the sequencer and its sample time.
NYX	0:85b3fd62ea1a	1292	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1293	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1294	* @param sConfig: ADC configuration structure.
NYX	0:85b3fd62ea1a	1295	* @retval HAL status
NYX	0:85b3fd62ea1a	1296	*/
NYX	0:85b3fd62ea1a	1297	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
NYX	0:85b3fd62ea1a	1298	{
NYX	0:85b3fd62ea1a	1299	__IO uint32_t counter = 0U;
NYX	0:85b3fd62ea1a	1300	ADC_Common_TypeDef *tmpADC_Common;
NYX	0:85b3fd62ea1a	1301
NYX	0:85b3fd62ea1a	1302	/* Check the parameters */
NYX	0:85b3fd62ea1a	1303	assert_param(IS_ADC_CHANNEL(sConfig->Channel));
NYX	0:85b3fd62ea1a	1304	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
NYX	0:85b3fd62ea1a	1305	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
NYX	0:85b3fd62ea1a	1306
NYX	0:85b3fd62ea1a	1307	/* Process locked */
NYX	0:85b3fd62ea1a	1308	__HAL_LOCK(hadc);
NYX	0:85b3fd62ea1a	1309
NYX	0:85b3fd62ea1a	1310	/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
NYX	0:85b3fd62ea1a	1311	if (sConfig->Channel > ADC_CHANNEL_9)
NYX	0:85b3fd62ea1a	1312	{
NYX	0:85b3fd62ea1a	1313	/* Clear the old sample time */
NYX	0:85b3fd62ea1a	1314	hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
NYX	0:85b3fd62ea1a	1315
NYX	0:85b3fd62ea1a	1316	/* Set the new sample time */
NYX	0:85b3fd62ea1a	1317	hadc->Instance->SMPR1 \|= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
NYX	0:85b3fd62ea1a	1318	}
NYX	0:85b3fd62ea1a	1319	else /* ADC_Channel include in ADC_Channel_[0..9] */
NYX	0:85b3fd62ea1a	1320	{
NYX	0:85b3fd62ea1a	1321	/* Clear the old sample time */
NYX	0:85b3fd62ea1a	1322	hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
NYX	0:85b3fd62ea1a	1323
NYX	0:85b3fd62ea1a	1324	/* Set the new sample time */
NYX	0:85b3fd62ea1a	1325	hadc->Instance->SMPR2 \|= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
NYX	0:85b3fd62ea1a	1326	}
NYX	0:85b3fd62ea1a	1327
NYX	0:85b3fd62ea1a	1328	/* For Rank 1 to 6 */
NYX	0:85b3fd62ea1a	1329	if (sConfig->Rank < 7U)
NYX	0:85b3fd62ea1a	1330	{
NYX	0:85b3fd62ea1a	1331	/* Clear the old SQx bits for the selected rank */
NYX	0:85b3fd62ea1a	1332	hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
NYX	0:85b3fd62ea1a	1333
NYX	0:85b3fd62ea1a	1334	/* Set the SQx bits for the selected rank */
NYX	0:85b3fd62ea1a	1335	hadc->Instance->SQR3 \|= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
NYX	0:85b3fd62ea1a	1336	}
NYX	0:85b3fd62ea1a	1337	/* For Rank 7 to 12 */
NYX	0:85b3fd62ea1a	1338	else if (sConfig->Rank < 13U)
NYX	0:85b3fd62ea1a	1339	{
NYX	0:85b3fd62ea1a	1340	/* Clear the old SQx bits for the selected rank */
NYX	0:85b3fd62ea1a	1341	hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
NYX	0:85b3fd62ea1a	1342
NYX	0:85b3fd62ea1a	1343	/* Set the SQx bits for the selected rank */
NYX	0:85b3fd62ea1a	1344	hadc->Instance->SQR2 \|= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
NYX	0:85b3fd62ea1a	1345	}
NYX	0:85b3fd62ea1a	1346	/* For Rank 13 to 16 */
NYX	0:85b3fd62ea1a	1347	else
NYX	0:85b3fd62ea1a	1348	{
NYX	0:85b3fd62ea1a	1349	/* Clear the old SQx bits for the selected rank */
NYX	0:85b3fd62ea1a	1350	hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
NYX	0:85b3fd62ea1a	1351
NYX	0:85b3fd62ea1a	1352	/* Set the SQx bits for the selected rank */
NYX	0:85b3fd62ea1a	1353	hadc->Instance->SQR1 \|= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
NYX	0:85b3fd62ea1a	1354	}
NYX	0:85b3fd62ea1a	1355
NYX	0:85b3fd62ea1a	1356	/* Pointer to the common control register to which is belonging hadc */
NYX	0:85b3fd62ea1a	1357	/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
NYX	0:85b3fd62ea1a	1358	/* control register) */
NYX	0:85b3fd62ea1a	1359	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
NYX	0:85b3fd62ea1a	1360
NYX	0:85b3fd62ea1a	1361	/* if ADC1 Channel_18 is selected enable VBAT Channel */
NYX	0:85b3fd62ea1a	1362	if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
NYX	0:85b3fd62ea1a	1363	{
NYX	0:85b3fd62ea1a	1364	/* Enable the VBAT channel*/
NYX	0:85b3fd62ea1a	1365	tmpADC_Common->CCR \|= ADC_CCR_VBATE;
NYX	0:85b3fd62ea1a	1366	}
NYX	0:85b3fd62ea1a	1367
NYX	0:85b3fd62ea1a	1368	/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
NYX	0:85b3fd62ea1a	1369	if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) \|\| (sConfig->Channel == ADC_CHANNEL_VREFINT)))
NYX	0:85b3fd62ea1a	1370	{
NYX	0:85b3fd62ea1a	1371	/* Enable the TSVREFE channel*/
NYX	0:85b3fd62ea1a	1372	tmpADC_Common->CCR \|= ADC_CCR_TSVREFE;
NYX	0:85b3fd62ea1a	1373
NYX	0:85b3fd62ea1a	1374	if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
NYX	0:85b3fd62ea1a	1375	{
NYX	0:85b3fd62ea1a	1376	/* Delay for temperature sensor stabilization time */
NYX	0:85b3fd62ea1a	1377	/* Compute number of CPU cycles to wait for */
NYX	0:85b3fd62ea1a	1378	counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
NYX	0:85b3fd62ea1a	1379	while(counter != 0U)
NYX	0:85b3fd62ea1a	1380	{
NYX	0:85b3fd62ea1a	1381	counter--;
NYX	0:85b3fd62ea1a	1382	}
NYX	0:85b3fd62ea1a	1383	}
NYX	0:85b3fd62ea1a	1384	}
NYX	0:85b3fd62ea1a	1385
NYX	0:85b3fd62ea1a	1386	/* Process unlocked */
NYX	0:85b3fd62ea1a	1387	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	1388
NYX	0:85b3fd62ea1a	1389	/* Return function status */
NYX	0:85b3fd62ea1a	1390	return HAL_OK;
NYX	0:85b3fd62ea1a	1391	}
NYX	0:85b3fd62ea1a	1392
NYX	0:85b3fd62ea1a	1393	/**
NYX	0:85b3fd62ea1a	1394	* @brief Configures the analog watchdog.
NYX	0:85b3fd62ea1a	1395	* @note Analog watchdog thresholds can be modified while ADC conversion
NYX	0:85b3fd62ea1a	1396	* is on going.
NYX	0:85b3fd62ea1a	1397	* In this case, some constraints must be taken into account:
NYX	0:85b3fd62ea1a	1398	* The programmed threshold values are effective from the next
NYX	0:85b3fd62ea1a	1399	* ADC EOC (end of unitary conversion).
NYX	0:85b3fd62ea1a	1400	* Considering that registers write delay may happen due to
NYX	0:85b3fd62ea1a	1401	* bus activity, this might cause an uncertainty on the
NYX	0:85b3fd62ea1a	1402	* effective timing of the new programmed threshold values.
NYX	0:85b3fd62ea1a	1403	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1404	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1405	* @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure
NYX	0:85b3fd62ea1a	1406	* that contains the configuration information of ADC analog watchdog.
NYX	0:85b3fd62ea1a	1407	* @retval HAL status
NYX	0:85b3fd62ea1a	1408	*/
NYX	0:85b3fd62ea1a	1409	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
NYX	0:85b3fd62ea1a	1410	{
NYX	0:85b3fd62ea1a	1411	#ifdef USE_FULL_ASSERT
NYX	0:85b3fd62ea1a	1412	uint32_t tmp = 0U;
NYX	0:85b3fd62ea1a	1413	#endif /* USE_FULL_ASSERT */
NYX	0:85b3fd62ea1a	1414
NYX	0:85b3fd62ea1a	1415	/* Check the parameters */
NYX	0:85b3fd62ea1a	1416	assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
NYX	0:85b3fd62ea1a	1417	assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
NYX	0:85b3fd62ea1a	1418	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
NYX	0:85b3fd62ea1a	1419
NYX	0:85b3fd62ea1a	1420	#ifdef USE_FULL_ASSERT
NYX	0:85b3fd62ea1a	1421	tmp = ADC_GET_RESOLUTION(hadc);
NYX	0:85b3fd62ea1a	1422	assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
NYX	0:85b3fd62ea1a	1423	assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
NYX	0:85b3fd62ea1a	1424	#endif /* USE_FULL_ASSERT */
NYX	0:85b3fd62ea1a	1425
NYX	0:85b3fd62ea1a	1426	/* Process locked */
NYX	0:85b3fd62ea1a	1427	__HAL_LOCK(hadc);
NYX	0:85b3fd62ea1a	1428
NYX	0:85b3fd62ea1a	1429	if(AnalogWDGConfig->ITMode == ENABLE)
NYX	0:85b3fd62ea1a	1430	{
NYX	0:85b3fd62ea1a	1431	/* Enable the ADC Analog watchdog interrupt */
NYX	0:85b3fd62ea1a	1432	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
NYX	0:85b3fd62ea1a	1433	}
NYX	0:85b3fd62ea1a	1434	else
NYX	0:85b3fd62ea1a	1435	{
NYX	0:85b3fd62ea1a	1436	/* Disable the ADC Analog watchdog interrupt */
NYX	0:85b3fd62ea1a	1437	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
NYX	0:85b3fd62ea1a	1438	}
NYX	0:85b3fd62ea1a	1439
NYX	0:85b3fd62ea1a	1440	/* Clear AWDEN, JAWDEN and AWDSGL bits */
NYX	0:85b3fd62ea1a	1441	hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN);
NYX	0:85b3fd62ea1a	1442
NYX	0:85b3fd62ea1a	1443	/* Set the analog watchdog enable mode */
NYX	0:85b3fd62ea1a	1444	hadc->Instance->CR1 \|= AnalogWDGConfig->WatchdogMode;
NYX	0:85b3fd62ea1a	1445
NYX	0:85b3fd62ea1a	1446	/* Set the high threshold */
NYX	0:85b3fd62ea1a	1447	hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
NYX	0:85b3fd62ea1a	1448
NYX	0:85b3fd62ea1a	1449	/* Set the low threshold */
NYX	0:85b3fd62ea1a	1450	hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
NYX	0:85b3fd62ea1a	1451
NYX	0:85b3fd62ea1a	1452	/* Clear the Analog watchdog channel select bits */
NYX	0:85b3fd62ea1a	1453	hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
NYX	0:85b3fd62ea1a	1454
NYX	0:85b3fd62ea1a	1455	/* Set the Analog watchdog channel */
NYX	0:85b3fd62ea1a	1456	hadc->Instance->CR1 \|= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
NYX	0:85b3fd62ea1a	1457
NYX	0:85b3fd62ea1a	1458	/* Process unlocked */
NYX	0:85b3fd62ea1a	1459	__HAL_UNLOCK(hadc);
NYX	0:85b3fd62ea1a	1460
NYX	0:85b3fd62ea1a	1461	/* Return function status */
NYX	0:85b3fd62ea1a	1462	return HAL_OK;
NYX	0:85b3fd62ea1a	1463	}
NYX	0:85b3fd62ea1a	1464
NYX	0:85b3fd62ea1a	1465	/**
NYX	0:85b3fd62ea1a	1466	* @}
NYX	0:85b3fd62ea1a	1467	*/
NYX	0:85b3fd62ea1a	1468
NYX	0:85b3fd62ea1a	1469	/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
NYX	0:85b3fd62ea1a	1470	* @brief ADC Peripheral State functions
NYX	0:85b3fd62ea1a	1471	*
NYX	0:85b3fd62ea1a	1472	@verbatim
NYX	0:85b3fd62ea1a	1473	===============================================================================
NYX	0:85b3fd62ea1a	1474	##### Peripheral State and errors functions #####
NYX	0:85b3fd62ea1a	1475	===============================================================================
NYX	0:85b3fd62ea1a	1476	[..]
NYX	0:85b3fd62ea1a	1477	This subsection provides functions allowing to
NYX	0:85b3fd62ea1a	1478	(+) Check the ADC state
NYX	0:85b3fd62ea1a	1479	(+) Check the ADC Error
NYX	0:85b3fd62ea1a	1480
NYX	0:85b3fd62ea1a	1481	@endverbatim
NYX	0:85b3fd62ea1a	1482	* @{
NYX	0:85b3fd62ea1a	1483	*/
NYX	0:85b3fd62ea1a	1484
NYX	0:85b3fd62ea1a	1485	/**
NYX	0:85b3fd62ea1a	1486	* @brief return the ADC state
NYX	0:85b3fd62ea1a	1487	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1488	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1489	* @retval HAL state
NYX	0:85b3fd62ea1a	1490	*/
NYX	0:85b3fd62ea1a	1491	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	1492	{
NYX	0:85b3fd62ea1a	1493	/* Return ADC state */
NYX	0:85b3fd62ea1a	1494	return hadc->State;
NYX	0:85b3fd62ea1a	1495	}
NYX	0:85b3fd62ea1a	1496
NYX	0:85b3fd62ea1a	1497	/**
NYX	0:85b3fd62ea1a	1498	* @brief Return the ADC error code
NYX	0:85b3fd62ea1a	1499	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1500	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1501	* @retval ADC Error Code
NYX	0:85b3fd62ea1a	1502	*/
NYX	0:85b3fd62ea1a	1503	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
NYX	0:85b3fd62ea1a	1504	{
NYX	0:85b3fd62ea1a	1505	return hadc->ErrorCode;
NYX	0:85b3fd62ea1a	1506	}
NYX	0:85b3fd62ea1a	1507
NYX	0:85b3fd62ea1a	1508	/**
NYX	0:85b3fd62ea1a	1509	* @}
NYX	0:85b3fd62ea1a	1510	*/
NYX	0:85b3fd62ea1a	1511
NYX	0:85b3fd62ea1a	1512	/** @addtogroup ADC_Private_Functions
NYX	0:85b3fd62ea1a	1513	* @{
NYX	0:85b3fd62ea1a	1514	*/
NYX	0:85b3fd62ea1a	1515
NYX	0:85b3fd62ea1a	1516	/**
NYX	0:85b3fd62ea1a	1517	* @brief Initializes the ADCx peripheral according to the specified parameters
NYX	0:85b3fd62ea1a	1518	* in the ADC_InitStruct without initializing the ADC MSP.
NYX	0:85b3fd62ea1a	1519	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1520	* the configuration information for the specified ADC.
NYX	0:85b3fd62ea1a	1521	* @retval None
NYX	0:85b3fd62ea1a	1522	*/
NYX	0:85b3fd62ea1a	1523	static void ADC_Init(ADC_HandleTypeDef* hadc)
NYX	0:85b3fd62ea1a	1524	{
NYX	0:85b3fd62ea1a	1525	ADC_Common_TypeDef *tmpADC_Common;
NYX	0:85b3fd62ea1a	1526
NYX	0:85b3fd62ea1a	1527	/* Set ADC parameters */
NYX	0:85b3fd62ea1a	1528	/* Pointer to the common control register to which is belonging hadc */
NYX	0:85b3fd62ea1a	1529	/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
NYX	0:85b3fd62ea1a	1530	/* control register) */
NYX	0:85b3fd62ea1a	1531	tmpADC_Common = ADC_COMMON_REGISTER(hadc);
NYX	0:85b3fd62ea1a	1532
NYX	0:85b3fd62ea1a	1533	/* Set the ADC clock prescaler */
NYX	0:85b3fd62ea1a	1534	tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
NYX	0:85b3fd62ea1a	1535	tmpADC_Common->CCR \|= hadc->Init.ClockPrescaler;
NYX	0:85b3fd62ea1a	1536
NYX	0:85b3fd62ea1a	1537	/* Set ADC scan mode */
NYX	0:85b3fd62ea1a	1538	hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
NYX	0:85b3fd62ea1a	1539	hadc->Instance->CR1 \|= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
NYX	0:85b3fd62ea1a	1540
NYX	0:85b3fd62ea1a	1541	/* Set ADC resolution */
NYX	0:85b3fd62ea1a	1542	hadc->Instance->CR1 &= ~(ADC_CR1_RES);
NYX	0:85b3fd62ea1a	1543	hadc->Instance->CR1 \|= hadc->Init.Resolution;
NYX	0:85b3fd62ea1a	1544
NYX	0:85b3fd62ea1a	1545	/* Set ADC data alignment */
NYX	0:85b3fd62ea1a	1546	hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
NYX	0:85b3fd62ea1a	1547	hadc->Instance->CR2 \|= hadc->Init.DataAlign;
NYX	0:85b3fd62ea1a	1548
NYX	0:85b3fd62ea1a	1549	/* Enable external trigger if trigger selection is different of software */
NYX	0:85b3fd62ea1a	1550	/* start. */
NYX	0:85b3fd62ea1a	1551	/* Note: This configuration keeps the hardware feature of parameter */
NYX	0:85b3fd62ea1a	1552	/* ExternalTrigConvEdge "trigger edge none" equivalent to */
NYX	0:85b3fd62ea1a	1553	/* software start. */
NYX	0:85b3fd62ea1a	1554	if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
NYX	0:85b3fd62ea1a	1555	{
NYX	0:85b3fd62ea1a	1556	/* Select external trigger to start conversion */
NYX	0:85b3fd62ea1a	1557	hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
NYX	0:85b3fd62ea1a	1558	hadc->Instance->CR2 \|= hadc->Init.ExternalTrigConv;
NYX	0:85b3fd62ea1a	1559
NYX	0:85b3fd62ea1a	1560	/* Select external trigger polarity */
NYX	0:85b3fd62ea1a	1561	hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
NYX	0:85b3fd62ea1a	1562	hadc->Instance->CR2 \|= hadc->Init.ExternalTrigConvEdge;
NYX	0:85b3fd62ea1a	1563	}
NYX	0:85b3fd62ea1a	1564	else
NYX	0:85b3fd62ea1a	1565	{
NYX	0:85b3fd62ea1a	1566	/* Reset the external trigger */
NYX	0:85b3fd62ea1a	1567	hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
NYX	0:85b3fd62ea1a	1568	hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
NYX	0:85b3fd62ea1a	1569	}
NYX	0:85b3fd62ea1a	1570
NYX	0:85b3fd62ea1a	1571	/* Enable or disable ADC continuous conversion mode */
NYX	0:85b3fd62ea1a	1572	hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
NYX	0:85b3fd62ea1a	1573	hadc->Instance->CR2 \|= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
NYX	0:85b3fd62ea1a	1574
NYX	0:85b3fd62ea1a	1575	if(hadc->Init.DiscontinuousConvMode != DISABLE)
NYX	0:85b3fd62ea1a	1576	{
NYX	0:85b3fd62ea1a	1577	assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
NYX	0:85b3fd62ea1a	1578
NYX	0:85b3fd62ea1a	1579	/* Enable the selected ADC regular discontinuous mode */
NYX	0:85b3fd62ea1a	1580	hadc->Instance->CR1 \|= (uint32_t)ADC_CR1_DISCEN;
NYX	0:85b3fd62ea1a	1581
NYX	0:85b3fd62ea1a	1582	/* Set the number of channels to be converted in discontinuous mode */
NYX	0:85b3fd62ea1a	1583	hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
NYX	0:85b3fd62ea1a	1584	hadc->Instance->CR1 \|= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
NYX	0:85b3fd62ea1a	1585	}
NYX	0:85b3fd62ea1a	1586	else
NYX	0:85b3fd62ea1a	1587	{
NYX	0:85b3fd62ea1a	1588	/* Disable the selected ADC regular discontinuous mode */
NYX	0:85b3fd62ea1a	1589	hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
NYX	0:85b3fd62ea1a	1590	}
NYX	0:85b3fd62ea1a	1591
NYX	0:85b3fd62ea1a	1592	/* Set ADC number of conversion */
NYX	0:85b3fd62ea1a	1593	hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
NYX	0:85b3fd62ea1a	1594	hadc->Instance->SQR1 \|= ADC_SQR1(hadc->Init.NbrOfConversion);
NYX	0:85b3fd62ea1a	1595
NYX	0:85b3fd62ea1a	1596	/* Enable or disable ADC DMA continuous request */
NYX	0:85b3fd62ea1a	1597	hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
NYX	0:85b3fd62ea1a	1598	hadc->Instance->CR2 \|= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
NYX	0:85b3fd62ea1a	1599
NYX	0:85b3fd62ea1a	1600	/* Enable or disable ADC end of conversion selection */
NYX	0:85b3fd62ea1a	1601	hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
NYX	0:85b3fd62ea1a	1602	hadc->Instance->CR2 \|= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
NYX	0:85b3fd62ea1a	1603	}
NYX	0:85b3fd62ea1a	1604
NYX	0:85b3fd62ea1a	1605	/**
NYX	0:85b3fd62ea1a	1606	* @brief DMA transfer complete callback.
NYX	0:85b3fd62ea1a	1607	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1608	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	1609	* @retval None
NYX	0:85b3fd62ea1a	1610	*/
NYX	0:85b3fd62ea1a	1611	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	1612	{
NYX	0:85b3fd62ea1a	1613	/* Retrieve ADC handle corresponding to current DMA handle */
NYX	0:85b3fd62ea1a	1614	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	1615
NYX	0:85b3fd62ea1a	1616	/* Update state machine on conversion status if not in error state */
NYX	0:85b3fd62ea1a	1617	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL \| HAL_ADC_STATE_ERROR_DMA))
NYX	0:85b3fd62ea1a	1618	{
NYX	0:85b3fd62ea1a	1619	/* Update ADC state machine */
NYX	0:85b3fd62ea1a	1620	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
NYX	0:85b3fd62ea1a	1621
NYX	0:85b3fd62ea1a	1622	/* Determine whether any further conversion upcoming on group regular */
NYX	0:85b3fd62ea1a	1623	/* by external trigger, continuous mode or scan sequence on going. */
NYX	0:85b3fd62ea1a	1624	/* Note: On STM32F4, there is no independent flag of end of sequence. */
NYX	0:85b3fd62ea1a	1625	/* The test of scan sequence on going is done either with scan */
NYX	0:85b3fd62ea1a	1626	/* sequence disabled or with end of conversion flag set to */
NYX	0:85b3fd62ea1a	1627	/* of end of sequence. */
NYX	0:85b3fd62ea1a	1628	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
NYX	0:85b3fd62ea1a	1629	(hadc->Init.ContinuousConvMode == DISABLE) &&
NYX	0:85b3fd62ea1a	1630	(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) \|\|
NYX	0:85b3fd62ea1a	1631	HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
NYX	0:85b3fd62ea1a	1632	{
NYX	0:85b3fd62ea1a	1633	/* Disable ADC end of single conversion interrupt on group regular */
NYX	0:85b3fd62ea1a	1634	/* Note: Overrun interrupt was enabled with EOC interrupt in */
NYX	0:85b3fd62ea1a	1635	/* HAL_ADC_Start_IT(), but is not disabled here because can be used */
NYX	0:85b3fd62ea1a	1636	/* by overrun IRQ process below. */
NYX	0:85b3fd62ea1a	1637	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
NYX	0:85b3fd62ea1a	1638
NYX	0:85b3fd62ea1a	1639	/* Set ADC state */
NYX	0:85b3fd62ea1a	1640	CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
NYX	0:85b3fd62ea1a	1641
NYX	0:85b3fd62ea1a	1642	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
NYX	0:85b3fd62ea1a	1643	{
NYX	0:85b3fd62ea1a	1644	SET_BIT(hadc->State, HAL_ADC_STATE_READY);
NYX	0:85b3fd62ea1a	1645	}
NYX	0:85b3fd62ea1a	1646	}
NYX	0:85b3fd62ea1a	1647
NYX	0:85b3fd62ea1a	1648	/* Conversion complete callback */
NYX	0:85b3fd62ea1a	1649	HAL_ADC_ConvCpltCallback(hadc);
NYX	0:85b3fd62ea1a	1650	}
NYX	0:85b3fd62ea1a	1651	else
NYX	0:85b3fd62ea1a	1652	{
NYX	0:85b3fd62ea1a	1653	/* Call DMA error callback */
NYX	0:85b3fd62ea1a	1654	hadc->DMA_Handle->XferErrorCallback(hdma);
NYX	0:85b3fd62ea1a	1655	}
NYX	0:85b3fd62ea1a	1656	}
NYX	0:85b3fd62ea1a	1657
NYX	0:85b3fd62ea1a	1658	/**
NYX	0:85b3fd62ea1a	1659	* @brief DMA half transfer complete callback.
NYX	0:85b3fd62ea1a	1660	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1661	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	1662	* @retval None
NYX	0:85b3fd62ea1a	1663	*/
NYX	0:85b3fd62ea1a	1664	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	1665	{
NYX	0:85b3fd62ea1a	1666	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	1667	/* Conversion complete callback */
NYX	0:85b3fd62ea1a	1668	HAL_ADC_ConvHalfCpltCallback(hadc);
NYX	0:85b3fd62ea1a	1669	}
NYX	0:85b3fd62ea1a	1670
NYX	0:85b3fd62ea1a	1671	/**
NYX	0:85b3fd62ea1a	1672	* @brief DMA error callback
NYX	0:85b3fd62ea1a	1673	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1674	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	1675	* @retval None
NYX	0:85b3fd62ea1a	1676	*/
NYX	0:85b3fd62ea1a	1677	static void ADC_DMAError(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	1678	{
NYX	0:85b3fd62ea1a	1679	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	1680	hadc->State= HAL_ADC_STATE_ERROR_DMA;
NYX	0:85b3fd62ea1a	1681	/* Set ADC error code to DMA error */
NYX	0:85b3fd62ea1a	1682	hadc->ErrorCode \|= HAL_ADC_ERROR_DMA;
NYX	0:85b3fd62ea1a	1683	HAL_ADC_ErrorCallback(hadc);
NYX	0:85b3fd62ea1a	1684	}
NYX	0:85b3fd62ea1a	1685
NYX	0:85b3fd62ea1a	1686	/**
NYX	0:85b3fd62ea1a	1687	* @}
NYX	0:85b3fd62ea1a	1688	*/
NYX	0:85b3fd62ea1a	1689
NYX	0:85b3fd62ea1a	1690	/**
NYX	0:85b3fd62ea1a	1691	* @}
NYX	0:85b3fd62ea1a	1692	*/
NYX	0:85b3fd62ea1a	1693
NYX	0:85b3fd62ea1a	1694	#endif /* HAL_ADC_MODULE_ENABLED */
NYX	0:85b3fd62ea1a	1695	/**
NYX	0:85b3fd62ea1a	1696	* @}
NYX	0:85b3fd62ea1a	1697	*/
NYX	0:85b3fd62ea1a	1698
NYX	0:85b3fd62ea1a	1699	/**
NYX	0:85b3fd62ea1a	1700	* @}
NYX	0:85b3fd62ea1a	1701	*/
NYX	0:85b3fd62ea1a	1702
NYX	0:85b3fd62ea1a	1703	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
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Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

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