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targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32_hal_legacy.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
NYX	0:85b3fd62ea1a	8	* macros and functions maintained for legacy purpose.
NYX	0:85b3fd62ea1a	9	******************************************************************************
NYX	0:85b3fd62ea1a	10	* @attention
NYX	0:85b3fd62ea1a	11	*
NYX	0:85b3fd62ea1a	12	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	13	*
NYX	0:85b3fd62ea1a	14	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	15	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	16	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	17	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	19	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	20	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	22	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	23	* without specific prior written permission.
NYX	0:85b3fd62ea1a	24	*
NYX	0:85b3fd62ea1a	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	35	*
NYX	0:85b3fd62ea1a	36	******************************************************************************
NYX	0:85b3fd62ea1a	37	*/
NYX	0:85b3fd62ea1a	38
NYX	0:85b3fd62ea1a	39	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	40	#ifndef __STM32_HAL_LEGACY
NYX	0:85b3fd62ea1a	41	#define __STM32_HAL_LEGACY
NYX	0:85b3fd62ea1a	42
NYX	0:85b3fd62ea1a	43	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	44	extern "C" {
NYX	0:85b3fd62ea1a	45	#endif
NYX	0:85b3fd62ea1a	46
NYX	0:85b3fd62ea1a	47	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	48	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	49	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	50
NYX	0:85b3fd62ea1a	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	52	* @{
NYX	0:85b3fd62ea1a	53	*/
NYX	0:85b3fd62ea1a	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
NYX	0:85b3fd62ea1a	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
NYX	0:85b3fd62ea1a	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
NYX	0:85b3fd62ea1a	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
NYX	0:85b3fd62ea1a	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
NYX	0:85b3fd62ea1a	59
NYX	0:85b3fd62ea1a	60	/**
NYX	0:85b3fd62ea1a	61	* @}
NYX	0:85b3fd62ea1a	62	*/
NYX	0:85b3fd62ea1a	63
NYX	0:85b3fd62ea1a	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	65	* @{
NYX	0:85b3fd62ea1a	66	*/
NYX	0:85b3fd62ea1a	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
NYX	0:85b3fd62ea1a	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
NYX	0:85b3fd62ea1a	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
NYX	0:85b3fd62ea1a	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
NYX	0:85b3fd62ea1a	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
NYX	0:85b3fd62ea1a	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
NYX	0:85b3fd62ea1a	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
NYX	0:85b3fd62ea1a	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
NYX	0:85b3fd62ea1a	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
NYX	0:85b3fd62ea1a	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
NYX	0:85b3fd62ea1a	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
NYX	0:85b3fd62ea1a	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
NYX	0:85b3fd62ea1a	79	#define AWD_EVENT ADC_AWD_EVENT
NYX	0:85b3fd62ea1a	80	#define AWD1_EVENT ADC_AWD1_EVENT
NYX	0:85b3fd62ea1a	81	#define AWD2_EVENT ADC_AWD2_EVENT
NYX	0:85b3fd62ea1a	82	#define AWD3_EVENT ADC_AWD3_EVENT
NYX	0:85b3fd62ea1a	83	#define OVR_EVENT ADC_OVR_EVENT
NYX	0:85b3fd62ea1a	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
NYX	0:85b3fd62ea1a	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
NYX	0:85b3fd62ea1a	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
NYX	0:85b3fd62ea1a	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
NYX	0:85b3fd62ea1a	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
NYX	0:85b3fd62ea1a	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
NYX	0:85b3fd62ea1a	90	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
NYX	0:85b3fd62ea1a	91	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
NYX	0:85b3fd62ea1a	92	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
NYX	0:85b3fd62ea1a	93	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
NYX	0:85b3fd62ea1a	94	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
NYX	0:85b3fd62ea1a	95	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
NYX	0:85b3fd62ea1a	96	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
NYX	0:85b3fd62ea1a	97	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
NYX	0:85b3fd62ea1a	98	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
NYX	0:85b3fd62ea1a	99	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
NYX	0:85b3fd62ea1a	100	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
NYX	0:85b3fd62ea1a	101	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
NYX	0:85b3fd62ea1a	102	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
NYX	0:85b3fd62ea1a	103	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
NYX	0:85b3fd62ea1a	104	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
NYX	0:85b3fd62ea1a	105	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
NYX	0:85b3fd62ea1a	106	#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
NYX	0:85b3fd62ea1a	107
NYX	0:85b3fd62ea1a	108	#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
NYX	0:85b3fd62ea1a	109	#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
NYX	0:85b3fd62ea1a	110	#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
NYX	0:85b3fd62ea1a	111	#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
NYX	0:85b3fd62ea1a	112	#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
NYX	0:85b3fd62ea1a	113	#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
NYX	0:85b3fd62ea1a	114	#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
NYX	0:85b3fd62ea1a	115	/**
NYX	0:85b3fd62ea1a	116	* @}
NYX	0:85b3fd62ea1a	117	*/
NYX	0:85b3fd62ea1a	118
NYX	0:85b3fd62ea1a	119	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	120	* @{
NYX	0:85b3fd62ea1a	121	*/
NYX	0:85b3fd62ea1a	122
NYX	0:85b3fd62ea1a	123	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
NYX	0:85b3fd62ea1a	124
NYX	0:85b3fd62ea1a	125	/**
NYX	0:85b3fd62ea1a	126	* @}
NYX	0:85b3fd62ea1a	127	*/
NYX	0:85b3fd62ea1a	128
NYX	0:85b3fd62ea1a	129	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	130	* @{
NYX	0:85b3fd62ea1a	131	*/
NYX	0:85b3fd62ea1a	132	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
NYX	0:85b3fd62ea1a	133	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
NYX	0:85b3fd62ea1a	134	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
NYX	0:85b3fd62ea1a	135	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
NYX	0:85b3fd62ea1a	136	#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
NYX	0:85b3fd62ea1a	137	#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
NYX	0:85b3fd62ea1a	138	#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
NYX	0:85b3fd62ea1a	139	#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
NYX	0:85b3fd62ea1a	140	#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
NYX	0:85b3fd62ea1a	141	#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /!< COMPX output is connected to LPTIM input 1 /
NYX	0:85b3fd62ea1a	142	#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
NYX	0:85b3fd62ea1a	143	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
NYX	0:85b3fd62ea1a	144	#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
NYX	0:85b3fd62ea1a	145	#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
NYX	0:85b3fd62ea1a	146	#endif /* STM32F373xC \|\| STM32F378xx */
NYX	0:85b3fd62ea1a	147
NYX	0:85b3fd62ea1a	148	#if defined(STM32L0) \|\| defined(STM32L4)
NYX	0:85b3fd62ea1a	149	#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
NYX	0:85b3fd62ea1a	150
NYX	0:85b3fd62ea1a	151	#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
NYX	0:85b3fd62ea1a	152	#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
NYX	0:85b3fd62ea1a	153	#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
NYX	0:85b3fd62ea1a	154	#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
NYX	0:85b3fd62ea1a	155	#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
NYX	0:85b3fd62ea1a	156	#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
NYX	0:85b3fd62ea1a	157
NYX	0:85b3fd62ea1a	158	#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
NYX	0:85b3fd62ea1a	159	#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
NYX	0:85b3fd62ea1a	160	#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
NYX	0:85b3fd62ea1a	161	#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
NYX	0:85b3fd62ea1a	162	#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
NYX	0:85b3fd62ea1a	163	#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
NYX	0:85b3fd62ea1a	164	#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
NYX	0:85b3fd62ea1a	165	#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
NYX	0:85b3fd62ea1a	166	#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
NYX	0:85b3fd62ea1a	167	#if defined(STM32L0)
NYX	0:85b3fd62ea1a	168	/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
NYX	0:85b3fd62ea1a	169	/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
NYX	0:85b3fd62ea1a	170	/* to the second dedicated IO (only for COMP2). */
NYX	0:85b3fd62ea1a	171	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
NYX	0:85b3fd62ea1a	172	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
NYX	0:85b3fd62ea1a	173	#else
NYX	0:85b3fd62ea1a	174	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
NYX	0:85b3fd62ea1a	175	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
NYX	0:85b3fd62ea1a	176	#endif
NYX	0:85b3fd62ea1a	177	#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
NYX	0:85b3fd62ea1a	178	#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
NYX	0:85b3fd62ea1a	179
NYX	0:85b3fd62ea1a	180	#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
NYX	0:85b3fd62ea1a	181	#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
NYX	0:85b3fd62ea1a	182
NYX	0:85b3fd62ea1a	183	/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
NYX	0:85b3fd62ea1a	184	/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
NYX	0:85b3fd62ea1a	185	#if defined(COMP_CSR_LOCK)
NYX	0:85b3fd62ea1a	186	#define COMP_FLAG_LOCK COMP_CSR_LOCK
NYX	0:85b3fd62ea1a	187	#elif defined(COMP_CSR_COMP1LOCK)
NYX	0:85b3fd62ea1a	188	#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
NYX	0:85b3fd62ea1a	189	#elif defined(COMP_CSR_COMPxLOCK)
NYX	0:85b3fd62ea1a	190	#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
NYX	0:85b3fd62ea1a	191	#endif
NYX	0:85b3fd62ea1a	192
NYX	0:85b3fd62ea1a	193	#if defined(STM32L4)
NYX	0:85b3fd62ea1a	194	#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
NYX	0:85b3fd62ea1a	195	#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
NYX	0:85b3fd62ea1a	196	#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
NYX	0:85b3fd62ea1a	197	#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
NYX	0:85b3fd62ea1a	198	#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
NYX	0:85b3fd62ea1a	199	#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
NYX	0:85b3fd62ea1a	200	#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
NYX	0:85b3fd62ea1a	201	#endif
NYX	0:85b3fd62ea1a	202
NYX	0:85b3fd62ea1a	203	#if defined(STM32L0)
NYX	0:85b3fd62ea1a	204	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
NYX	0:85b3fd62ea1a	205	#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
NYX	0:85b3fd62ea1a	206	#else
NYX	0:85b3fd62ea1a	207	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
NYX	0:85b3fd62ea1a	208	#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
NYX	0:85b3fd62ea1a	209	#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
NYX	0:85b3fd62ea1a	210	#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
NYX	0:85b3fd62ea1a	211	#endif
NYX	0:85b3fd62ea1a	212
NYX	0:85b3fd62ea1a	213	#endif
NYX	0:85b3fd62ea1a	214	/**
NYX	0:85b3fd62ea1a	215	* @}
NYX	0:85b3fd62ea1a	216	*/
NYX	0:85b3fd62ea1a	217
NYX	0:85b3fd62ea1a	218	/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	219	* @{
NYX	0:85b3fd62ea1a	220	*/
NYX	0:85b3fd62ea1a	221	#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
NYX	0:85b3fd62ea1a	222	/**
NYX	0:85b3fd62ea1a	223	* @}
NYX	0:85b3fd62ea1a	224	*/
NYX	0:85b3fd62ea1a	225
NYX	0:85b3fd62ea1a	226	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	227	* @{
NYX	0:85b3fd62ea1a	228	*/
NYX	0:85b3fd62ea1a	229
NYX	0:85b3fd62ea1a	230	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
NYX	0:85b3fd62ea1a	231	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
NYX	0:85b3fd62ea1a	232
NYX	0:85b3fd62ea1a	233	/**
NYX	0:85b3fd62ea1a	234	* @}
NYX	0:85b3fd62ea1a	235	*/
NYX	0:85b3fd62ea1a	236
NYX	0:85b3fd62ea1a	237	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	238	* @{
NYX	0:85b3fd62ea1a	239	*/
NYX	0:85b3fd62ea1a	240
NYX	0:85b3fd62ea1a	241	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	242	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
NYX	0:85b3fd62ea1a	243	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	244	#define DAC_WAVE_NONE 0x00000000U
NYX	0:85b3fd62ea1a	245	#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
NYX	0:85b3fd62ea1a	246	#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
NYX	0:85b3fd62ea1a	247	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
NYX	0:85b3fd62ea1a	248	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
NYX	0:85b3fd62ea1a	249	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
NYX	0:85b3fd62ea1a	250
NYX	0:85b3fd62ea1a	251	/**
NYX	0:85b3fd62ea1a	252	* @}
NYX	0:85b3fd62ea1a	253	*/
NYX	0:85b3fd62ea1a	254
NYX	0:85b3fd62ea1a	255	/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	256	* @{
NYX	0:85b3fd62ea1a	257	*/
NYX	0:85b3fd62ea1a	258	#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
NYX	0:85b3fd62ea1a	259	#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
NYX	0:85b3fd62ea1a	260	#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
NYX	0:85b3fd62ea1a	261	#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
NYX	0:85b3fd62ea1a	262	#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
NYX	0:85b3fd62ea1a	263	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
NYX	0:85b3fd62ea1a	264	#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
NYX	0:85b3fd62ea1a	265	#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
NYX	0:85b3fd62ea1a	266	#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
NYX	0:85b3fd62ea1a	267	#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
NYX	0:85b3fd62ea1a	268	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
NYX	0:85b3fd62ea1a	269	#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
NYX	0:85b3fd62ea1a	270	#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
NYX	0:85b3fd62ea1a	271	#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
NYX	0:85b3fd62ea1a	272	#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
NYX	0:85b3fd62ea1a	273
NYX	0:85b3fd62ea1a	274	#define IS_HAL_REMAPDMA IS_DMA_REMAP
NYX	0:85b3fd62ea1a	275	#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
NYX	0:85b3fd62ea1a	276	#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
NYX	0:85b3fd62ea1a	277
NYX	0:85b3fd62ea1a	278
NYX	0:85b3fd62ea1a	279
NYX	0:85b3fd62ea1a	280	/**
NYX	0:85b3fd62ea1a	281	* @}
NYX	0:85b3fd62ea1a	282	*/
NYX	0:85b3fd62ea1a	283
NYX	0:85b3fd62ea1a	284	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	285	* @{
NYX	0:85b3fd62ea1a	286	*/
NYX	0:85b3fd62ea1a	287
NYX	0:85b3fd62ea1a	288	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
NYX	0:85b3fd62ea1a	289	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
NYX	0:85b3fd62ea1a	290	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
NYX	0:85b3fd62ea1a	291	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
NYX	0:85b3fd62ea1a	292	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
NYX	0:85b3fd62ea1a	293	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
NYX	0:85b3fd62ea1a	294	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
NYX	0:85b3fd62ea1a	295	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
NYX	0:85b3fd62ea1a	296	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
NYX	0:85b3fd62ea1a	297	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
NYX	0:85b3fd62ea1a	298	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
NYX	0:85b3fd62ea1a	299	#define OBEX_PCROP OPTIONBYTE_PCROP
NYX	0:85b3fd62ea1a	300	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
NYX	0:85b3fd62ea1a	301	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
NYX	0:85b3fd62ea1a	302	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
NYX	0:85b3fd62ea1a	303	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
NYX	0:85b3fd62ea1a	304	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
NYX	0:85b3fd62ea1a	305	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
NYX	0:85b3fd62ea1a	306	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
NYX	0:85b3fd62ea1a	307	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
NYX	0:85b3fd62ea1a	308	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
NYX	0:85b3fd62ea1a	309	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
NYX	0:85b3fd62ea1a	310	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
NYX	0:85b3fd62ea1a	311	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
NYX	0:85b3fd62ea1a	312	#define PAGESIZE FLASH_PAGE_SIZE
NYX	0:85b3fd62ea1a	313	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
NYX	0:85b3fd62ea1a	314	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
NYX	0:85b3fd62ea1a	315	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
NYX	0:85b3fd62ea1a	316	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
NYX	0:85b3fd62ea1a	317	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
NYX	0:85b3fd62ea1a	318	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
NYX	0:85b3fd62ea1a	319	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
NYX	0:85b3fd62ea1a	320	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
NYX	0:85b3fd62ea1a	321	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
NYX	0:85b3fd62ea1a	322	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
NYX	0:85b3fd62ea1a	323	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
NYX	0:85b3fd62ea1a	324	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
NYX	0:85b3fd62ea1a	325	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
NYX	0:85b3fd62ea1a	326	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
NYX	0:85b3fd62ea1a	327	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
NYX	0:85b3fd62ea1a	328	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
NYX	0:85b3fd62ea1a	329	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
NYX	0:85b3fd62ea1a	330	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
NYX	0:85b3fd62ea1a	331	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
NYX	0:85b3fd62ea1a	332	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
NYX	0:85b3fd62ea1a	333	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
NYX	0:85b3fd62ea1a	334	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
NYX	0:85b3fd62ea1a	335	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
NYX	0:85b3fd62ea1a	336	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
NYX	0:85b3fd62ea1a	337	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
NYX	0:85b3fd62ea1a	338	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
NYX	0:85b3fd62ea1a	339	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
NYX	0:85b3fd62ea1a	340	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
NYX	0:85b3fd62ea1a	341	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
NYX	0:85b3fd62ea1a	342	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
NYX	0:85b3fd62ea1a	343	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
NYX	0:85b3fd62ea1a	344	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
NYX	0:85b3fd62ea1a	345	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
NYX	0:85b3fd62ea1a	346	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
NYX	0:85b3fd62ea1a	347	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
NYX	0:85b3fd62ea1a	348	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
NYX	0:85b3fd62ea1a	349	#define OB_WDG_SW OB_IWDG_SW
NYX	0:85b3fd62ea1a	350	#define OB_WDG_HW OB_IWDG_HW
NYX	0:85b3fd62ea1a	351	#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
NYX	0:85b3fd62ea1a	352	#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
NYX	0:85b3fd62ea1a	353	#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
NYX	0:85b3fd62ea1a	354	#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
NYX	0:85b3fd62ea1a	355	#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
NYX	0:85b3fd62ea1a	356	#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
NYX	0:85b3fd62ea1a	357	#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
NYX	0:85b3fd62ea1a	358	#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
NYX	0:85b3fd62ea1a	359
NYX	0:85b3fd62ea1a	360	/**
NYX	0:85b3fd62ea1a	361	* @}
NYX	0:85b3fd62ea1a	362	*/
NYX	0:85b3fd62ea1a	363
NYX	0:85b3fd62ea1a	364	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	365	* @{
NYX	0:85b3fd62ea1a	366	*/
NYX	0:85b3fd62ea1a	367
NYX	0:85b3fd62ea1a	368	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
NYX	0:85b3fd62ea1a	369	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
NYX	0:85b3fd62ea1a	370	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
NYX	0:85b3fd62ea1a	371	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
NYX	0:85b3fd62ea1a	372	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
NYX	0:85b3fd62ea1a	373	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
NYX	0:85b3fd62ea1a	374	#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
NYX	0:85b3fd62ea1a	375	#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
NYX	0:85b3fd62ea1a	376	#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
NYX	0:85b3fd62ea1a	377	/**
NYX	0:85b3fd62ea1a	378	* @}
NYX	0:85b3fd62ea1a	379	*/
NYX	0:85b3fd62ea1a	380
NYX	0:85b3fd62ea1a	381
NYX	0:85b3fd62ea1a	382	/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
NYX	0:85b3fd62ea1a	383	* @{
NYX	0:85b3fd62ea1a	384	*/
NYX	0:85b3fd62ea1a	385	#if defined(STM32L4) \|\| defined(STM32F7) \|\| defined(STM32H7)
NYX	0:85b3fd62ea1a	386	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
NYX	0:85b3fd62ea1a	387	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
NYX	0:85b3fd62ea1a	388	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
NYX	0:85b3fd62ea1a	389	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
NYX	0:85b3fd62ea1a	390	#else
NYX	0:85b3fd62ea1a	391	#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
NYX	0:85b3fd62ea1a	392	#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
NYX	0:85b3fd62ea1a	393	#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
NYX	0:85b3fd62ea1a	394	#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
NYX	0:85b3fd62ea1a	395	#endif
NYX	0:85b3fd62ea1a	396	/**
NYX	0:85b3fd62ea1a	397	* @}
NYX	0:85b3fd62ea1a	398	*/
NYX	0:85b3fd62ea1a	399
NYX	0:85b3fd62ea1a	400	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	401	* @{
NYX	0:85b3fd62ea1a	402	*/
NYX	0:85b3fd62ea1a	403
NYX	0:85b3fd62ea1a	404	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
NYX	0:85b3fd62ea1a	405	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
NYX	0:85b3fd62ea1a	406	/**
NYX	0:85b3fd62ea1a	407	* @}
NYX	0:85b3fd62ea1a	408	*/
NYX	0:85b3fd62ea1a	409
NYX	0:85b3fd62ea1a	410	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	411	* @{
NYX	0:85b3fd62ea1a	412	*/
NYX	0:85b3fd62ea1a	413	#define GET_GPIO_SOURCE GPIO_GET_INDEX
NYX	0:85b3fd62ea1a	414	#define GET_GPIO_INDEX GPIO_GET_INDEX
NYX	0:85b3fd62ea1a	415
NYX	0:85b3fd62ea1a	416	#if defined(STM32F4)
NYX	0:85b3fd62ea1a	417	#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
NYX	0:85b3fd62ea1a	418	#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
NYX	0:85b3fd62ea1a	419	#endif
NYX	0:85b3fd62ea1a	420
NYX	0:85b3fd62ea1a	421	#if defined(STM32F7)
NYX	0:85b3fd62ea1a	422	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
NYX	0:85b3fd62ea1a	423	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
NYX	0:85b3fd62ea1a	424	#endif
NYX	0:85b3fd62ea1a	425
NYX	0:85b3fd62ea1a	426	#if defined(STM32L4)
NYX	0:85b3fd62ea1a	427	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
NYX	0:85b3fd62ea1a	428	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
NYX	0:85b3fd62ea1a	429	#endif
NYX	0:85b3fd62ea1a	430
NYX	0:85b3fd62ea1a	431	#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
NYX	0:85b3fd62ea1a	432	#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
NYX	0:85b3fd62ea1a	433	#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
NYX	0:85b3fd62ea1a	434
NYX	0:85b3fd62ea1a	435	#if defined(STM32L0) \|\| defined(STM32L4) \|\| defined(STM32F4) \|\| defined(STM32F2) \|\| defined(STM32F7)
NYX	0:85b3fd62ea1a	436	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
NYX	0:85b3fd62ea1a	437	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
NYX	0:85b3fd62ea1a	438	#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
NYX	0:85b3fd62ea1a	439	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
NYX	0:85b3fd62ea1a	440	#endif /* STM32L0 \|\| STM32L4 \|\| STM32F4 \|\| STM32F2 \|\| STM32F7 */
NYX	0:85b3fd62ea1a	441
NYX	0:85b3fd62ea1a	442	#if defined(STM32L1)
NYX	0:85b3fd62ea1a	443	#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
NYX	0:85b3fd62ea1a	444	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
NYX	0:85b3fd62ea1a	445	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
NYX	0:85b3fd62ea1a	446	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
NYX	0:85b3fd62ea1a	447	#endif /* STM32L1 */
NYX	0:85b3fd62ea1a	448
NYX	0:85b3fd62ea1a	449	#if defined(STM32F0) \|\| defined(STM32F3) \|\| defined(STM32F1)
NYX	0:85b3fd62ea1a	450	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
NYX	0:85b3fd62ea1a	451	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
NYX	0:85b3fd62ea1a	452	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
NYX	0:85b3fd62ea1a	453	#endif /* STM32F0 \|\| STM32F3 \|\| STM32F1 */
NYX	0:85b3fd62ea1a	454
NYX	0:85b3fd62ea1a	455	#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
NYX	0:85b3fd62ea1a	456	/**
NYX	0:85b3fd62ea1a	457	* @}
NYX	0:85b3fd62ea1a	458	*/
NYX	0:85b3fd62ea1a	459
NYX	0:85b3fd62ea1a	460	/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	461	* @{
NYX	0:85b3fd62ea1a	462	*/
NYX	0:85b3fd62ea1a	463	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
NYX	0:85b3fd62ea1a	464	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
NYX	0:85b3fd62ea1a	465	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
NYX	0:85b3fd62ea1a	466	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
NYX	0:85b3fd62ea1a	467	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
NYX	0:85b3fd62ea1a	468	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
NYX	0:85b3fd62ea1a	469	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
NYX	0:85b3fd62ea1a	470	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
NYX	0:85b3fd62ea1a	471	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
NYX	0:85b3fd62ea1a	472
NYX	0:85b3fd62ea1a	473	#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
NYX	0:85b3fd62ea1a	474	#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
NYX	0:85b3fd62ea1a	475	#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
NYX	0:85b3fd62ea1a	476	#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
NYX	0:85b3fd62ea1a	477	#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
NYX	0:85b3fd62ea1a	478	#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
NYX	0:85b3fd62ea1a	479	#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
NYX	0:85b3fd62ea1a	480	#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
NYX	0:85b3fd62ea1a	481	/**
NYX	0:85b3fd62ea1a	482	* @}
NYX	0:85b3fd62ea1a	483	*/
NYX	0:85b3fd62ea1a	484
NYX	0:85b3fd62ea1a	485	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	486	* @{
NYX	0:85b3fd62ea1a	487	*/
NYX	0:85b3fd62ea1a	488	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
NYX	0:85b3fd62ea1a	489	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
NYX	0:85b3fd62ea1a	490	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
NYX	0:85b3fd62ea1a	491	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
NYX	0:85b3fd62ea1a	492	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
NYX	0:85b3fd62ea1a	493	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
NYX	0:85b3fd62ea1a	494	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
NYX	0:85b3fd62ea1a	495	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
NYX	0:85b3fd62ea1a	496	#if defined(STM32F0) \|\| defined(STM32F1) \|\| defined(STM32F3) \|\| defined(STM32G0) \|\| defined(STM32L4) \|\| defined(STM32L1) \|\| defined(STM32F7)
NYX	0:85b3fd62ea1a	497	#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
NYX	0:85b3fd62ea1a	498	#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
NYX	0:85b3fd62ea1a	499	#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
NYX	0:85b3fd62ea1a	500	#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
NYX	0:85b3fd62ea1a	501	#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
NYX	0:85b3fd62ea1a	502	#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
NYX	0:85b3fd62ea1a	503	#endif
NYX	0:85b3fd62ea1a	504	/**
NYX	0:85b3fd62ea1a	505	* @}
NYX	0:85b3fd62ea1a	506	*/
NYX	0:85b3fd62ea1a	507
NYX	0:85b3fd62ea1a	508	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	509	* @{
NYX	0:85b3fd62ea1a	510	*/
NYX	0:85b3fd62ea1a	511	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
NYX	0:85b3fd62ea1a	512	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
NYX	0:85b3fd62ea1a	513
NYX	0:85b3fd62ea1a	514	/**
NYX	0:85b3fd62ea1a	515	* @}
NYX	0:85b3fd62ea1a	516	*/
NYX	0:85b3fd62ea1a	517
NYX	0:85b3fd62ea1a	518	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	519	* @{
NYX	0:85b3fd62ea1a	520	*/
NYX	0:85b3fd62ea1a	521	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
NYX	0:85b3fd62ea1a	522	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
NYX	0:85b3fd62ea1a	523	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
NYX	0:85b3fd62ea1a	524	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
NYX	0:85b3fd62ea1a	525	/**
NYX	0:85b3fd62ea1a	526	* @}
NYX	0:85b3fd62ea1a	527	*/
NYX	0:85b3fd62ea1a	528
NYX	0:85b3fd62ea1a	529	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	530	* @{
NYX	0:85b3fd62ea1a	531	*/
NYX	0:85b3fd62ea1a	532
NYX	0:85b3fd62ea1a	533	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
NYX	0:85b3fd62ea1a	534	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
NYX	0:85b3fd62ea1a	535	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
NYX	0:85b3fd62ea1a	536	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
NYX	0:85b3fd62ea1a	537
NYX	0:85b3fd62ea1a	538	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
NYX	0:85b3fd62ea1a	539	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
NYX	0:85b3fd62ea1a	540	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
NYX	0:85b3fd62ea1a	541
NYX	0:85b3fd62ea1a	542	#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
NYX	0:85b3fd62ea1a	543	#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
NYX	0:85b3fd62ea1a	544	#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
NYX	0:85b3fd62ea1a	545	#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
NYX	0:85b3fd62ea1a	546
NYX	0:85b3fd62ea1a	547	/* The following 3 definition have also been present in a temporary version of lptim.h */
NYX	0:85b3fd62ea1a	548	/* They need to be renamed also to the right name, just in case */
NYX	0:85b3fd62ea1a	549	#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
NYX	0:85b3fd62ea1a	550	#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
NYX	0:85b3fd62ea1a	551	#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
NYX	0:85b3fd62ea1a	552
NYX	0:85b3fd62ea1a	553	/**
NYX	0:85b3fd62ea1a	554	* @}
NYX	0:85b3fd62ea1a	555	*/
NYX	0:85b3fd62ea1a	556
NYX	0:85b3fd62ea1a	557	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	558	* @{
NYX	0:85b3fd62ea1a	559	*/
NYX	0:85b3fd62ea1a	560	#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
NYX	0:85b3fd62ea1a	561	#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
NYX	0:85b3fd62ea1a	562	#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
NYX	0:85b3fd62ea1a	563	#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
NYX	0:85b3fd62ea1a	564
NYX	0:85b3fd62ea1a	565	#define NAND_AddressTypedef NAND_AddressTypeDef
NYX	0:85b3fd62ea1a	566
NYX	0:85b3fd62ea1a	567	#define __ARRAY_ADDRESS ARRAY_ADDRESS
NYX	0:85b3fd62ea1a	568	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
NYX	0:85b3fd62ea1a	569	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
NYX	0:85b3fd62ea1a	570	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
NYX	0:85b3fd62ea1a	571	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
NYX	0:85b3fd62ea1a	572	/**
NYX	0:85b3fd62ea1a	573	* @}
NYX	0:85b3fd62ea1a	574	*/
NYX	0:85b3fd62ea1a	575
NYX	0:85b3fd62ea1a	576	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	577	* @{
NYX	0:85b3fd62ea1a	578	*/
NYX	0:85b3fd62ea1a	579	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
NYX	0:85b3fd62ea1a	580	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
NYX	0:85b3fd62ea1a	581	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
NYX	0:85b3fd62ea1a	582	#define NOR_ERROR HAL_NOR_STATUS_ERROR
NYX	0:85b3fd62ea1a	583	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
NYX	0:85b3fd62ea1a	584
NYX	0:85b3fd62ea1a	585	#define __NOR_WRITE NOR_WRITE
NYX	0:85b3fd62ea1a	586	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
NYX	0:85b3fd62ea1a	587	/**
NYX	0:85b3fd62ea1a	588	* @}
NYX	0:85b3fd62ea1a	589	*/
NYX	0:85b3fd62ea1a	590
NYX	0:85b3fd62ea1a	591	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	592	* @{
NYX	0:85b3fd62ea1a	593	*/
NYX	0:85b3fd62ea1a	594
NYX	0:85b3fd62ea1a	595	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
NYX	0:85b3fd62ea1a	596	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
NYX	0:85b3fd62ea1a	597	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
NYX	0:85b3fd62ea1a	598	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
NYX	0:85b3fd62ea1a	599
NYX	0:85b3fd62ea1a	600	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
NYX	0:85b3fd62ea1a	601	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
NYX	0:85b3fd62ea1a	602	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
NYX	0:85b3fd62ea1a	603	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
NYX	0:85b3fd62ea1a	604
NYX	0:85b3fd62ea1a	605	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
NYX	0:85b3fd62ea1a	606	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
NYX	0:85b3fd62ea1a	607
NYX	0:85b3fd62ea1a	608	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
NYX	0:85b3fd62ea1a	609	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
NYX	0:85b3fd62ea1a	610
NYX	0:85b3fd62ea1a	611	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
NYX	0:85b3fd62ea1a	612	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
NYX	0:85b3fd62ea1a	613
NYX	0:85b3fd62ea1a	614	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
NYX	0:85b3fd62ea1a	615
NYX	0:85b3fd62ea1a	616	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
NYX	0:85b3fd62ea1a	617	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
NYX	0:85b3fd62ea1a	618	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
NYX	0:85b3fd62ea1a	619
NYX	0:85b3fd62ea1a	620	/**
NYX	0:85b3fd62ea1a	621	* @}
NYX	0:85b3fd62ea1a	622	*/
NYX	0:85b3fd62ea1a	623
NYX	0:85b3fd62ea1a	624	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	625	* @{
NYX	0:85b3fd62ea1a	626	*/
NYX	0:85b3fd62ea1a	627	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
NYX	0:85b3fd62ea1a	628	#if defined(STM32F7)
NYX	0:85b3fd62ea1a	629	#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
NYX	0:85b3fd62ea1a	630	#endif
NYX	0:85b3fd62ea1a	631	/**
NYX	0:85b3fd62ea1a	632	* @}
NYX	0:85b3fd62ea1a	633	*/
NYX	0:85b3fd62ea1a	634
NYX	0:85b3fd62ea1a	635	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	636	* @{
NYX	0:85b3fd62ea1a	637	*/
NYX	0:85b3fd62ea1a	638
NYX	0:85b3fd62ea1a	639	/* Compact Flash-ATA registers description */
NYX	0:85b3fd62ea1a	640	#define CF_DATA ATA_DATA
NYX	0:85b3fd62ea1a	641	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
NYX	0:85b3fd62ea1a	642	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
NYX	0:85b3fd62ea1a	643	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
NYX	0:85b3fd62ea1a	644	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
NYX	0:85b3fd62ea1a	645	#define CF_CARD_HEAD ATA_CARD_HEAD
NYX	0:85b3fd62ea1a	646	#define CF_STATUS_CMD ATA_STATUS_CMD
NYX	0:85b3fd62ea1a	647	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
NYX	0:85b3fd62ea1a	648	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
NYX	0:85b3fd62ea1a	649
NYX	0:85b3fd62ea1a	650	/* Compact Flash-ATA commands */
NYX	0:85b3fd62ea1a	651	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
NYX	0:85b3fd62ea1a	652	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
NYX	0:85b3fd62ea1a	653	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
NYX	0:85b3fd62ea1a	654	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
NYX	0:85b3fd62ea1a	655
NYX	0:85b3fd62ea1a	656	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
NYX	0:85b3fd62ea1a	657	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
NYX	0:85b3fd62ea1a	658	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
NYX	0:85b3fd62ea1a	659	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
NYX	0:85b3fd62ea1a	660	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
NYX	0:85b3fd62ea1a	661	/**
NYX	0:85b3fd62ea1a	662	* @}
NYX	0:85b3fd62ea1a	663	*/
NYX	0:85b3fd62ea1a	664
NYX	0:85b3fd62ea1a	665	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	666	* @{
NYX	0:85b3fd62ea1a	667	*/
NYX	0:85b3fd62ea1a	668
NYX	0:85b3fd62ea1a	669	#define FORMAT_BIN RTC_FORMAT_BIN
NYX	0:85b3fd62ea1a	670	#define FORMAT_BCD RTC_FORMAT_BCD
NYX	0:85b3fd62ea1a	671
NYX	0:85b3fd62ea1a	672	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
NYX	0:85b3fd62ea1a	673	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
NYX	0:85b3fd62ea1a	674	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
NYX	0:85b3fd62ea1a	675	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
NYX	0:85b3fd62ea1a	676	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
NYX	0:85b3fd62ea1a	677
NYX	0:85b3fd62ea1a	678	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
NYX	0:85b3fd62ea1a	679	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
NYX	0:85b3fd62ea1a	680	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
NYX	0:85b3fd62ea1a	681	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
NYX	0:85b3fd62ea1a	682	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
NYX	0:85b3fd62ea1a	683	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
NYX	0:85b3fd62ea1a	684	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
NYX	0:85b3fd62ea1a	685	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
NYX	0:85b3fd62ea1a	686
NYX	0:85b3fd62ea1a	687	#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
NYX	0:85b3fd62ea1a	688	#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
NYX	0:85b3fd62ea1a	689	#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
NYX	0:85b3fd62ea1a	690	#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
NYX	0:85b3fd62ea1a	691
NYX	0:85b3fd62ea1a	692	#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
NYX	0:85b3fd62ea1a	693	#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
NYX	0:85b3fd62ea1a	694	#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
NYX	0:85b3fd62ea1a	695
NYX	0:85b3fd62ea1a	696	#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
NYX	0:85b3fd62ea1a	697	#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
NYX	0:85b3fd62ea1a	698	#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
NYX	0:85b3fd62ea1a	699
NYX	0:85b3fd62ea1a	700	/**
NYX	0:85b3fd62ea1a	701	* @}
NYX	0:85b3fd62ea1a	702	*/
NYX	0:85b3fd62ea1a	703
NYX	0:85b3fd62ea1a	704
NYX	0:85b3fd62ea1a	705	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	706	* @{
NYX	0:85b3fd62ea1a	707	*/
NYX	0:85b3fd62ea1a	708	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
NYX	0:85b3fd62ea1a	709	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
NYX	0:85b3fd62ea1a	710
NYX	0:85b3fd62ea1a	711	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
NYX	0:85b3fd62ea1a	712	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
NYX	0:85b3fd62ea1a	713	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
NYX	0:85b3fd62ea1a	714	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
NYX	0:85b3fd62ea1a	715
NYX	0:85b3fd62ea1a	716	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
NYX	0:85b3fd62ea1a	717	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
NYX	0:85b3fd62ea1a	718
NYX	0:85b3fd62ea1a	719	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
NYX	0:85b3fd62ea1a	720	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
NYX	0:85b3fd62ea1a	721	/**
NYX	0:85b3fd62ea1a	722	* @}
NYX	0:85b3fd62ea1a	723	*/
NYX	0:85b3fd62ea1a	724
NYX	0:85b3fd62ea1a	725
NYX	0:85b3fd62ea1a	726	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	727	* @{
NYX	0:85b3fd62ea1a	728	*/
NYX	0:85b3fd62ea1a	729	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
NYX	0:85b3fd62ea1a	730	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
NYX	0:85b3fd62ea1a	731	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
NYX	0:85b3fd62ea1a	732	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
NYX	0:85b3fd62ea1a	733	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
NYX	0:85b3fd62ea1a	734	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
NYX	0:85b3fd62ea1a	735	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
NYX	0:85b3fd62ea1a	736	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
NYX	0:85b3fd62ea1a	737	#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
NYX	0:85b3fd62ea1a	738	#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
NYX	0:85b3fd62ea1a	739	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
NYX	0:85b3fd62ea1a	740	/**
NYX	0:85b3fd62ea1a	741	* @}
NYX	0:85b3fd62ea1a	742	*/
NYX	0:85b3fd62ea1a	743
NYX	0:85b3fd62ea1a	744	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	745	* @{
NYX	0:85b3fd62ea1a	746	*/
NYX	0:85b3fd62ea1a	747	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
NYX	0:85b3fd62ea1a	748	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
NYX	0:85b3fd62ea1a	749
NYX	0:85b3fd62ea1a	750	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
NYX	0:85b3fd62ea1a	751	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
NYX	0:85b3fd62ea1a	752
NYX	0:85b3fd62ea1a	753	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
NYX	0:85b3fd62ea1a	754	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
NYX	0:85b3fd62ea1a	755
NYX	0:85b3fd62ea1a	756	/**
NYX	0:85b3fd62ea1a	757	* @}
NYX	0:85b3fd62ea1a	758	*/
NYX	0:85b3fd62ea1a	759
NYX	0:85b3fd62ea1a	760	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	761	* @{
NYX	0:85b3fd62ea1a	762	*/
NYX	0:85b3fd62ea1a	763	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
NYX	0:85b3fd62ea1a	764	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
NYX	0:85b3fd62ea1a	765
NYX	0:85b3fd62ea1a	766	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
NYX	0:85b3fd62ea1a	767	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
NYX	0:85b3fd62ea1a	768	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
NYX	0:85b3fd62ea1a	769	#define TIM_DMABase_DIER TIM_DMABASE_DIER
NYX	0:85b3fd62ea1a	770	#define TIM_DMABase_SR TIM_DMABASE_SR
NYX	0:85b3fd62ea1a	771	#define TIM_DMABase_EGR TIM_DMABASE_EGR
NYX	0:85b3fd62ea1a	772	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
NYX	0:85b3fd62ea1a	773	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
NYX	0:85b3fd62ea1a	774	#define TIM_DMABase_CCER TIM_DMABASE_CCER
NYX	0:85b3fd62ea1a	775	#define TIM_DMABase_CNT TIM_DMABASE_CNT
NYX	0:85b3fd62ea1a	776	#define TIM_DMABase_PSC TIM_DMABASE_PSC
NYX	0:85b3fd62ea1a	777	#define TIM_DMABase_ARR TIM_DMABASE_ARR
NYX	0:85b3fd62ea1a	778	#define TIM_DMABase_RCR TIM_DMABASE_RCR
NYX	0:85b3fd62ea1a	779	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
NYX	0:85b3fd62ea1a	780	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
NYX	0:85b3fd62ea1a	781	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
NYX	0:85b3fd62ea1a	782	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
NYX	0:85b3fd62ea1a	783	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
NYX	0:85b3fd62ea1a	784	#define TIM_DMABase_DCR TIM_DMABASE_DCR
NYX	0:85b3fd62ea1a	785	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
NYX	0:85b3fd62ea1a	786	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
NYX	0:85b3fd62ea1a	787	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
NYX	0:85b3fd62ea1a	788	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
NYX	0:85b3fd62ea1a	789	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
NYX	0:85b3fd62ea1a	790	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
NYX	0:85b3fd62ea1a	791	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
NYX	0:85b3fd62ea1a	792	#define TIM_DMABase_OR TIM_DMABASE_OR
NYX	0:85b3fd62ea1a	793
NYX	0:85b3fd62ea1a	794	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
NYX	0:85b3fd62ea1a	795	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
NYX	0:85b3fd62ea1a	796	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
NYX	0:85b3fd62ea1a	797	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
NYX	0:85b3fd62ea1a	798	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
NYX	0:85b3fd62ea1a	799	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
NYX	0:85b3fd62ea1a	800	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
NYX	0:85b3fd62ea1a	801	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
NYX	0:85b3fd62ea1a	802	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
NYX	0:85b3fd62ea1a	803
NYX	0:85b3fd62ea1a	804	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
NYX	0:85b3fd62ea1a	805	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
NYX	0:85b3fd62ea1a	806	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
NYX	0:85b3fd62ea1a	807	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
NYX	0:85b3fd62ea1a	808	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
NYX	0:85b3fd62ea1a	809	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
NYX	0:85b3fd62ea1a	810	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
NYX	0:85b3fd62ea1a	811	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
NYX	0:85b3fd62ea1a	812	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
NYX	0:85b3fd62ea1a	813	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
NYX	0:85b3fd62ea1a	814	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
NYX	0:85b3fd62ea1a	815	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
NYX	0:85b3fd62ea1a	816	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
NYX	0:85b3fd62ea1a	817	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
NYX	0:85b3fd62ea1a	818	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
NYX	0:85b3fd62ea1a	819	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
NYX	0:85b3fd62ea1a	820	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
NYX	0:85b3fd62ea1a	821	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
NYX	0:85b3fd62ea1a	822
NYX	0:85b3fd62ea1a	823	/**
NYX	0:85b3fd62ea1a	824	* @}
NYX	0:85b3fd62ea1a	825	*/
NYX	0:85b3fd62ea1a	826
NYX	0:85b3fd62ea1a	827	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	828	* @{
NYX	0:85b3fd62ea1a	829	*/
NYX	0:85b3fd62ea1a	830	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
NYX	0:85b3fd62ea1a	831	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
NYX	0:85b3fd62ea1a	832	/**
NYX	0:85b3fd62ea1a	833	* @}
NYX	0:85b3fd62ea1a	834	*/
NYX	0:85b3fd62ea1a	835
NYX	0:85b3fd62ea1a	836	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	837	* @{
NYX	0:85b3fd62ea1a	838	*/
NYX	0:85b3fd62ea1a	839	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
NYX	0:85b3fd62ea1a	840	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
NYX	0:85b3fd62ea1a	841	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
NYX	0:85b3fd62ea1a	842	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
NYX	0:85b3fd62ea1a	843
NYX	0:85b3fd62ea1a	844	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
NYX	0:85b3fd62ea1a	845	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
NYX	0:85b3fd62ea1a	846
NYX	0:85b3fd62ea1a	847	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
NYX	0:85b3fd62ea1a	848	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
NYX	0:85b3fd62ea1a	849	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
NYX	0:85b3fd62ea1a	850	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
NYX	0:85b3fd62ea1a	851
NYX	0:85b3fd62ea1a	852	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
NYX	0:85b3fd62ea1a	853	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
NYX	0:85b3fd62ea1a	854	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
NYX	0:85b3fd62ea1a	855	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
NYX	0:85b3fd62ea1a	856
NYX	0:85b3fd62ea1a	857	#define __DIV_LPUART UART_DIV_LPUART
NYX	0:85b3fd62ea1a	858
NYX	0:85b3fd62ea1a	859	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
NYX	0:85b3fd62ea1a	860	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
NYX	0:85b3fd62ea1a	861
NYX	0:85b3fd62ea1a	862	/**
NYX	0:85b3fd62ea1a	863	* @}
NYX	0:85b3fd62ea1a	864	*/
NYX	0:85b3fd62ea1a	865
NYX	0:85b3fd62ea1a	866
NYX	0:85b3fd62ea1a	867	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	868	* @{
NYX	0:85b3fd62ea1a	869	*/
NYX	0:85b3fd62ea1a	870
NYX	0:85b3fd62ea1a	871	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
NYX	0:85b3fd62ea1a	872	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
NYX	0:85b3fd62ea1a	873
NYX	0:85b3fd62ea1a	874	#define USARTNACK_ENABLED USART_NACK_ENABLE
NYX	0:85b3fd62ea1a	875	#define USARTNACK_DISABLED USART_NACK_DISABLE
NYX	0:85b3fd62ea1a	876	/**
NYX	0:85b3fd62ea1a	877	* @}
NYX	0:85b3fd62ea1a	878	*/
NYX	0:85b3fd62ea1a	879
NYX	0:85b3fd62ea1a	880	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	881	* @{
NYX	0:85b3fd62ea1a	882	*/
NYX	0:85b3fd62ea1a	883	#define CFR_BASE WWDG_CFR_BASE
NYX	0:85b3fd62ea1a	884
NYX	0:85b3fd62ea1a	885	/**
NYX	0:85b3fd62ea1a	886	* @}
NYX	0:85b3fd62ea1a	887	*/
NYX	0:85b3fd62ea1a	888
NYX	0:85b3fd62ea1a	889	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	890	* @{
NYX	0:85b3fd62ea1a	891	*/
NYX	0:85b3fd62ea1a	892	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
NYX	0:85b3fd62ea1a	893	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
NYX	0:85b3fd62ea1a	894	#define CAN_IT_RQCP0 CAN_IT_TME
NYX	0:85b3fd62ea1a	895	#define CAN_IT_RQCP1 CAN_IT_TME
NYX	0:85b3fd62ea1a	896	#define CAN_IT_RQCP2 CAN_IT_TME
NYX	0:85b3fd62ea1a	897	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
NYX	0:85b3fd62ea1a	898	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
NYX	0:85b3fd62ea1a	899	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
NYX	0:85b3fd62ea1a	900	#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
NYX	0:85b3fd62ea1a	901	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
NYX	0:85b3fd62ea1a	902
NYX	0:85b3fd62ea1a	903	/**
NYX	0:85b3fd62ea1a	904	* @}
NYX	0:85b3fd62ea1a	905	*/
NYX	0:85b3fd62ea1a	906
NYX	0:85b3fd62ea1a	907	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	908	* @{
NYX	0:85b3fd62ea1a	909	*/
NYX	0:85b3fd62ea1a	910
NYX	0:85b3fd62ea1a	911	#define VLAN_TAG ETH_VLAN_TAG
NYX	0:85b3fd62ea1a	912	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
NYX	0:85b3fd62ea1a	913	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
NYX	0:85b3fd62ea1a	914	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
NYX	0:85b3fd62ea1a	915	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
NYX	0:85b3fd62ea1a	916	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
NYX	0:85b3fd62ea1a	917	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
NYX	0:85b3fd62ea1a	918	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
NYX	0:85b3fd62ea1a	919
NYX	0:85b3fd62ea1a	920	#define ETH_MMCCR 0x00000100U
NYX	0:85b3fd62ea1a	921	#define ETH_MMCRIR 0x00000104U
NYX	0:85b3fd62ea1a	922	#define ETH_MMCTIR 0x00000108U
NYX	0:85b3fd62ea1a	923	#define ETH_MMCRIMR 0x0000010CU
NYX	0:85b3fd62ea1a	924	#define ETH_MMCTIMR 0x00000110U
NYX	0:85b3fd62ea1a	925	#define ETH_MMCTGFSCCR 0x0000014CU
NYX	0:85b3fd62ea1a	926	#define ETH_MMCTGFMSCCR 0x00000150U
NYX	0:85b3fd62ea1a	927	#define ETH_MMCTGFCR 0x00000168U
NYX	0:85b3fd62ea1a	928	#define ETH_MMCRFCECR 0x00000194U
NYX	0:85b3fd62ea1a	929	#define ETH_MMCRFAECR 0x00000198U
NYX	0:85b3fd62ea1a	930	#define ETH_MMCRGUFCR 0x000001C4U
NYX	0:85b3fd62ea1a	931
NYX	0:85b3fd62ea1a	932	#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
NYX	0:85b3fd62ea1a	933	#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
NYX	0:85b3fd62ea1a	934	#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
NYX	0:85b3fd62ea1a	935	#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
NYX	0:85b3fd62ea1a	936	#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
NYX	0:85b3fd62ea1a	937	#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
NYX	0:85b3fd62ea1a	938	#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
NYX	0:85b3fd62ea1a	939	#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
NYX	0:85b3fd62ea1a	940	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
NYX	0:85b3fd62ea1a	941	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
NYX	0:85b3fd62ea1a	942	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
NYX	0:85b3fd62ea1a	943	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
NYX	0:85b3fd62ea1a	944	#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
NYX	0:85b3fd62ea1a	945	#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
NYX	0:85b3fd62ea1a	946	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
NYX	0:85b3fd62ea1a	947	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
NYX	0:85b3fd62ea1a	948	#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
NYX	0:85b3fd62ea1a	949	#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
NYX	0:85b3fd62ea1a	950	#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
NYX	0:85b3fd62ea1a	951	#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
NYX	0:85b3fd62ea1a	952	#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
NYX	0:85b3fd62ea1a	953	#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
NYX	0:85b3fd62ea1a	954	#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
NYX	0:85b3fd62ea1a	955	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
NYX	0:85b3fd62ea1a	956	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
NYX	0:85b3fd62ea1a	957	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
NYX	0:85b3fd62ea1a	958	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
NYX	0:85b3fd62ea1a	959
NYX	0:85b3fd62ea1a	960	/**
NYX	0:85b3fd62ea1a	961	* @}
NYX	0:85b3fd62ea1a	962	*/
NYX	0:85b3fd62ea1a	963
NYX	0:85b3fd62ea1a	964	/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	965	* @{
NYX	0:85b3fd62ea1a	966	*/
NYX	0:85b3fd62ea1a	967	#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
NYX	0:85b3fd62ea1a	968	#define DCMI_IT_OVF DCMI_IT_OVR
NYX	0:85b3fd62ea1a	969	#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
NYX	0:85b3fd62ea1a	970	#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
NYX	0:85b3fd62ea1a	971
NYX	0:85b3fd62ea1a	972	#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
NYX	0:85b3fd62ea1a	973	#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
NYX	0:85b3fd62ea1a	974	#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
NYX	0:85b3fd62ea1a	975
NYX	0:85b3fd62ea1a	976	/**
NYX	0:85b3fd62ea1a	977	* @}
NYX	0:85b3fd62ea1a	978	*/
NYX	0:85b3fd62ea1a	979
NYX	0:85b3fd62ea1a	980	#if defined(STM32L4) \|\| defined(STM32F7) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
NYX	0:85b3fd62ea1a	981	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	982	/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	983	* @{
NYX	0:85b3fd62ea1a	984	*/
NYX	0:85b3fd62ea1a	985	#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
NYX	0:85b3fd62ea1a	986	#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
NYX	0:85b3fd62ea1a	987	#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
NYX	0:85b3fd62ea1a	988	#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
NYX	0:85b3fd62ea1a	989	#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
NYX	0:85b3fd62ea1a	990
NYX	0:85b3fd62ea1a	991	#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
NYX	0:85b3fd62ea1a	992	#define CM_RGB888 DMA2D_INPUT_RGB888
NYX	0:85b3fd62ea1a	993	#define CM_RGB565 DMA2D_INPUT_RGB565
NYX	0:85b3fd62ea1a	994	#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
NYX	0:85b3fd62ea1a	995	#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
NYX	0:85b3fd62ea1a	996	#define CM_L8 DMA2D_INPUT_L8
NYX	0:85b3fd62ea1a	997	#define CM_AL44 DMA2D_INPUT_AL44
NYX	0:85b3fd62ea1a	998	#define CM_AL88 DMA2D_INPUT_AL88
NYX	0:85b3fd62ea1a	999	#define CM_L4 DMA2D_INPUT_L4
NYX	0:85b3fd62ea1a	1000	#define CM_A8 DMA2D_INPUT_A8
NYX	0:85b3fd62ea1a	1001	#define CM_A4 DMA2D_INPUT_A4
NYX	0:85b3fd62ea1a	1002	/**
NYX	0:85b3fd62ea1a	1003	* @}
NYX	0:85b3fd62ea1a	1004	*/
NYX	0:85b3fd62ea1a	1005	#endif /* STM32L4 \|\| STM32F7*/
NYX	0:85b3fd62ea1a	1006
NYX	0:85b3fd62ea1a	1007	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
NYX	0:85b3fd62ea1a	1008	* @{
NYX	0:85b3fd62ea1a	1009	*/
NYX	0:85b3fd62ea1a	1010
NYX	0:85b3fd62ea1a	1011	/**
NYX	0:85b3fd62ea1a	1012	* @}
NYX	0:85b3fd62ea1a	1013	*/
NYX	0:85b3fd62ea1a	1014
NYX	0:85b3fd62ea1a	1015	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1016
NYX	0:85b3fd62ea1a	1017	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1018	* @{
NYX	0:85b3fd62ea1a	1019	*/
NYX	0:85b3fd62ea1a	1020	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
NYX	0:85b3fd62ea1a	1021	/**
NYX	0:85b3fd62ea1a	1022	* @}
NYX	0:85b3fd62ea1a	1023	*/
NYX	0:85b3fd62ea1a	1024
NYX	0:85b3fd62ea1a	1025	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1026	* @{
NYX	0:85b3fd62ea1a	1027	*/
NYX	0:85b3fd62ea1a	1028	#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
NYX	0:85b3fd62ea1a	1029	#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
NYX	0:85b3fd62ea1a	1030	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
NYX	0:85b3fd62ea1a	1031	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
NYX	0:85b3fd62ea1a	1032	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
NYX	0:85b3fd62ea1a	1033	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
NYX	0:85b3fd62ea1a	1034
NYX	0:85b3fd62ea1a	1035	/HASH Algorithm Selection/
NYX	0:85b3fd62ea1a	1036
NYX	0:85b3fd62ea1a	1037	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
NYX	0:85b3fd62ea1a	1038	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
NYX	0:85b3fd62ea1a	1039	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
NYX	0:85b3fd62ea1a	1040	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
NYX	0:85b3fd62ea1a	1041
NYX	0:85b3fd62ea1a	1042	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
NYX	0:85b3fd62ea1a	1043	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
NYX	0:85b3fd62ea1a	1044
NYX	0:85b3fd62ea1a	1045	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
NYX	0:85b3fd62ea1a	1046	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
NYX	0:85b3fd62ea1a	1047	/**
NYX	0:85b3fd62ea1a	1048	* @}
NYX	0:85b3fd62ea1a	1049	*/
NYX	0:85b3fd62ea1a	1050
NYX	0:85b3fd62ea1a	1051	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1052	* @{
NYX	0:85b3fd62ea1a	1053	*/
NYX	0:85b3fd62ea1a	1054	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
NYX	0:85b3fd62ea1a	1055	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
NYX	0:85b3fd62ea1a	1056	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
NYX	0:85b3fd62ea1a	1057	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
NYX	0:85b3fd62ea1a	1058	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
NYX	0:85b3fd62ea1a	1059	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
NYX	0:85b3fd62ea1a	1060	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
NYX	0:85b3fd62ea1a	1061	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
NYX	0:85b3fd62ea1a	1062	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
NYX	0:85b3fd62ea1a	1063	#if defined(STM32L0)
NYX	0:85b3fd62ea1a	1064	#else
NYX	0:85b3fd62ea1a	1065	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
NYX	0:85b3fd62ea1a	1066	#endif
NYX	0:85b3fd62ea1a	1067	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
NYX	0:85b3fd62ea1a	1068	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
NYX	0:85b3fd62ea1a	1069	/**
NYX	0:85b3fd62ea1a	1070	* @}
NYX	0:85b3fd62ea1a	1071	*/
NYX	0:85b3fd62ea1a	1072
NYX	0:85b3fd62ea1a	1073	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1074	* @{
NYX	0:85b3fd62ea1a	1075	*/
NYX	0:85b3fd62ea1a	1076	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
NYX	0:85b3fd62ea1a	1077	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
NYX	0:85b3fd62ea1a	1078	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
NYX	0:85b3fd62ea1a	1079	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
NYX	0:85b3fd62ea1a	1080	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
NYX	0:85b3fd62ea1a	1081	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
NYX	0:85b3fd62ea1a	1082	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
NYX	0:85b3fd62ea1a	1083
NYX	0:85b3fd62ea1a	1084	/**
NYX	0:85b3fd62ea1a	1085	* @}
NYX	0:85b3fd62ea1a	1086	*/
NYX	0:85b3fd62ea1a	1087
NYX	0:85b3fd62ea1a	1088	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1089	* @{
NYX	0:85b3fd62ea1a	1090	*/
NYX	0:85b3fd62ea1a	1091	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
NYX	0:85b3fd62ea1a	1092	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
NYX	0:85b3fd62ea1a	1093	#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
NYX	0:85b3fd62ea1a	1094	#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
NYX	0:85b3fd62ea1a	1095
NYX	0:85b3fd62ea1a	1096	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
NYX	0:85b3fd62ea1a	1097	/**
NYX	0:85b3fd62ea1a	1098	* @}
NYX	0:85b3fd62ea1a	1099	*/
NYX	0:85b3fd62ea1a	1100
NYX	0:85b3fd62ea1a	1101	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
NYX	0:85b3fd62ea1a	1102	* @{
NYX	0:85b3fd62ea1a	1103	*/
NYX	0:85b3fd62ea1a	1104	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
NYX	0:85b3fd62ea1a	1105	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
NYX	0:85b3fd62ea1a	1106	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
NYX	0:85b3fd62ea1a	1107	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
NYX	0:85b3fd62ea1a	1108	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
NYX	0:85b3fd62ea1a	1109	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
NYX	0:85b3fd62ea1a	1110	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
NYX	0:85b3fd62ea1a	1111	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
NYX	0:85b3fd62ea1a	1112	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
NYX	0:85b3fd62ea1a	1113	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
NYX	0:85b3fd62ea1a	1114	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
NYX	0:85b3fd62ea1a	1115	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
NYX	0:85b3fd62ea1a	1116	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
NYX	0:85b3fd62ea1a	1117	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
NYX	0:85b3fd62ea1a	1118	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
NYX	0:85b3fd62ea1a	1119	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
NYX	0:85b3fd62ea1a	1120
NYX	0:85b3fd62ea1a	1121	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
NYX	0:85b3fd62ea1a	1122	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
NYX	0:85b3fd62ea1a	1123	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
NYX	0:85b3fd62ea1a	1124	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
NYX	0:85b3fd62ea1a	1125	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
NYX	0:85b3fd62ea1a	1126	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
NYX	0:85b3fd62ea1a	1127	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
NYX	0:85b3fd62ea1a	1128
NYX	0:85b3fd62ea1a	1129	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
NYX	0:85b3fd62ea1a	1130	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
NYX	0:85b3fd62ea1a	1131
NYX	0:85b3fd62ea1a	1132	#define DBP_BitNumber DBP_BIT_NUMBER
NYX	0:85b3fd62ea1a	1133	#define PVDE_BitNumber PVDE_BIT_NUMBER
NYX	0:85b3fd62ea1a	1134	#define PMODE_BitNumber PMODE_BIT_NUMBER
NYX	0:85b3fd62ea1a	1135	#define EWUP_BitNumber EWUP_BIT_NUMBER
NYX	0:85b3fd62ea1a	1136	#define FPDS_BitNumber FPDS_BIT_NUMBER
NYX	0:85b3fd62ea1a	1137	#define ODEN_BitNumber ODEN_BIT_NUMBER
NYX	0:85b3fd62ea1a	1138	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
NYX	0:85b3fd62ea1a	1139	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
NYX	0:85b3fd62ea1a	1140	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
NYX	0:85b3fd62ea1a	1141	#define BRE_BitNumber BRE_BIT_NUMBER
NYX	0:85b3fd62ea1a	1142
NYX	0:85b3fd62ea1a	1143	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
NYX	0:85b3fd62ea1a	1144
NYX	0:85b3fd62ea1a	1145	/**
NYX	0:85b3fd62ea1a	1146	* @}
NYX	0:85b3fd62ea1a	1147	*/
NYX	0:85b3fd62ea1a	1148
NYX	0:85b3fd62ea1a	1149	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1150	* @{
NYX	0:85b3fd62ea1a	1151	*/
NYX	0:85b3fd62ea1a	1152	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
NYX	0:85b3fd62ea1a	1153	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
NYX	0:85b3fd62ea1a	1154	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
NYX	0:85b3fd62ea1a	1155	/**
NYX	0:85b3fd62ea1a	1156	* @}
NYX	0:85b3fd62ea1a	1157	*/
NYX	0:85b3fd62ea1a	1158
NYX	0:85b3fd62ea1a	1159	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1160	* @{
NYX	0:85b3fd62ea1a	1161	*/
NYX	0:85b3fd62ea1a	1162	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
NYX	0:85b3fd62ea1a	1163	/**
NYX	0:85b3fd62ea1a	1164	* @}
NYX	0:85b3fd62ea1a	1165	*/
NYX	0:85b3fd62ea1a	1166
NYX	0:85b3fd62ea1a	1167	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1168	* @{
NYX	0:85b3fd62ea1a	1169	*/
NYX	0:85b3fd62ea1a	1170	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
NYX	0:85b3fd62ea1a	1171	#define HAL_TIM_DMAError TIM_DMAError
NYX	0:85b3fd62ea1a	1172	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
NYX	0:85b3fd62ea1a	1173	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
NYX	0:85b3fd62ea1a	1174	/**
NYX	0:85b3fd62ea1a	1175	* @}
NYX	0:85b3fd62ea1a	1176	*/
NYX	0:85b3fd62ea1a	1177
NYX	0:85b3fd62ea1a	1178	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1179	* @{
NYX	0:85b3fd62ea1a	1180	*/
NYX	0:85b3fd62ea1a	1181	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
NYX	0:85b3fd62ea1a	1182	/**
NYX	0:85b3fd62ea1a	1183	* @}
NYX	0:85b3fd62ea1a	1184	*/
NYX	0:85b3fd62ea1a	1185
NYX	0:85b3fd62ea1a	1186	/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1187	* @{
NYX	0:85b3fd62ea1a	1188	*/
NYX	0:85b3fd62ea1a	1189	#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
NYX	0:85b3fd62ea1a	1190	#define HAL_LTDC_Relaod HAL_LTDC_Reload
NYX	0:85b3fd62ea1a	1191	#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
NYX	0:85b3fd62ea1a	1192	#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
NYX	0:85b3fd62ea1a	1193	/**
NYX	0:85b3fd62ea1a	1194	* @}
NYX	0:85b3fd62ea1a	1195	*/
NYX	0:85b3fd62ea1a	1196
NYX	0:85b3fd62ea1a	1197
NYX	0:85b3fd62ea1a	1198	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1199	* @{
NYX	0:85b3fd62ea1a	1200	*/
NYX	0:85b3fd62ea1a	1201
NYX	0:85b3fd62ea1a	1202	/**
NYX	0:85b3fd62ea1a	1203	* @}
NYX	0:85b3fd62ea1a	1204	*/
NYX	0:85b3fd62ea1a	1205
NYX	0:85b3fd62ea1a	1206	/* Exported macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1207
NYX	0:85b3fd62ea1a	1208	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1209	* @{
NYX	0:85b3fd62ea1a	1210	*/
NYX	0:85b3fd62ea1a	1211	#define AES_IT_CC CRYP_IT_CC
NYX	0:85b3fd62ea1a	1212	#define AES_IT_ERR CRYP_IT_ERR
NYX	0:85b3fd62ea1a	1213	#define AES_FLAG_CCF CRYP_FLAG_CCF
NYX	0:85b3fd62ea1a	1214	/**
NYX	0:85b3fd62ea1a	1215	* @}
NYX	0:85b3fd62ea1a	1216	*/
NYX	0:85b3fd62ea1a	1217
NYX	0:85b3fd62ea1a	1218	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1219	* @{
NYX	0:85b3fd62ea1a	1220	*/
NYX	0:85b3fd62ea1a	1221	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
NYX	0:85b3fd62ea1a	1222	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
NYX	0:85b3fd62ea1a	1223	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
NYX	0:85b3fd62ea1a	1224	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
NYX	0:85b3fd62ea1a	1225	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
NYX	0:85b3fd62ea1a	1226	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
NYX	0:85b3fd62ea1a	1227	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
NYX	0:85b3fd62ea1a	1228	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
NYX	0:85b3fd62ea1a	1229	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
NYX	0:85b3fd62ea1a	1230	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
NYX	0:85b3fd62ea1a	1231	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
NYX	0:85b3fd62ea1a	1232	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
NYX	0:85b3fd62ea1a	1233	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
NYX	0:85b3fd62ea1a	1234
NYX	0:85b3fd62ea1a	1235	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
NYX	0:85b3fd62ea1a	1236	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
NYX	0:85b3fd62ea1a	1237	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
NYX	0:85b3fd62ea1a	1238	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
NYX	0:85b3fd62ea1a	1239	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
NYX	0:85b3fd62ea1a	1240
NYX	0:85b3fd62ea1a	1241	/**
NYX	0:85b3fd62ea1a	1242	* @}
NYX	0:85b3fd62ea1a	1243	*/
NYX	0:85b3fd62ea1a	1244
NYX	0:85b3fd62ea1a	1245
NYX	0:85b3fd62ea1a	1246	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1247	* @{
NYX	0:85b3fd62ea1a	1248	*/
NYX	0:85b3fd62ea1a	1249	#define __ADC_ENABLE __HAL_ADC_ENABLE
NYX	0:85b3fd62ea1a	1250	#define __ADC_DISABLE __HAL_ADC_DISABLE
NYX	0:85b3fd62ea1a	1251	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
NYX	0:85b3fd62ea1a	1252	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
NYX	0:85b3fd62ea1a	1253	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
NYX	0:85b3fd62ea1a	1254	#define __ADC_IS_ENABLED ADC_IS_ENABLE
NYX	0:85b3fd62ea1a	1255	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
NYX	0:85b3fd62ea1a	1256	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
NYX	0:85b3fd62ea1a	1257	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
NYX	0:85b3fd62ea1a	1258	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
NYX	0:85b3fd62ea1a	1259	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
NYX	0:85b3fd62ea1a	1260	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
NYX	0:85b3fd62ea1a	1261	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
NYX	0:85b3fd62ea1a	1262
NYX	0:85b3fd62ea1a	1263	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
NYX	0:85b3fd62ea1a	1264	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
NYX	0:85b3fd62ea1a	1265	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
NYX	0:85b3fd62ea1a	1266	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
NYX	0:85b3fd62ea1a	1267	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
NYX	0:85b3fd62ea1a	1268	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
NYX	0:85b3fd62ea1a	1269	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
NYX	0:85b3fd62ea1a	1270	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
NYX	0:85b3fd62ea1a	1271	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
NYX	0:85b3fd62ea1a	1272	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
NYX	0:85b3fd62ea1a	1273	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
NYX	0:85b3fd62ea1a	1274	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
NYX	0:85b3fd62ea1a	1275	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
NYX	0:85b3fd62ea1a	1276	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
NYX	0:85b3fd62ea1a	1277	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
NYX	0:85b3fd62ea1a	1278	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
NYX	0:85b3fd62ea1a	1279	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
NYX	0:85b3fd62ea1a	1280	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
NYX	0:85b3fd62ea1a	1281	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
NYX	0:85b3fd62ea1a	1282	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
NYX	0:85b3fd62ea1a	1283
NYX	0:85b3fd62ea1a	1284	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
NYX	0:85b3fd62ea1a	1285	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
NYX	0:85b3fd62ea1a	1286	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
NYX	0:85b3fd62ea1a	1287	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
NYX	0:85b3fd62ea1a	1288	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
NYX	0:85b3fd62ea1a	1289	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
NYX	0:85b3fd62ea1a	1290	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
NYX	0:85b3fd62ea1a	1291	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
NYX	0:85b3fd62ea1a	1292	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
NYX	0:85b3fd62ea1a	1293	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
NYX	0:85b3fd62ea1a	1294
NYX	0:85b3fd62ea1a	1295	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
NYX	0:85b3fd62ea1a	1296	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
NYX	0:85b3fd62ea1a	1297	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
NYX	0:85b3fd62ea1a	1298	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
NYX	0:85b3fd62ea1a	1299	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
NYX	0:85b3fd62ea1a	1300	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
NYX	0:85b3fd62ea1a	1301	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
NYX	0:85b3fd62ea1a	1302	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
NYX	0:85b3fd62ea1a	1303
NYX	0:85b3fd62ea1a	1304	#define __HAL_ADC_SQR1 ADC_SQR1
NYX	0:85b3fd62ea1a	1305	#define __HAL_ADC_SMPR1 ADC_SMPR1
NYX	0:85b3fd62ea1a	1306	#define __HAL_ADC_SMPR2 ADC_SMPR2
NYX	0:85b3fd62ea1a	1307	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
NYX	0:85b3fd62ea1a	1308	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
NYX	0:85b3fd62ea1a	1309	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
NYX	0:85b3fd62ea1a	1310	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
NYX	0:85b3fd62ea1a	1311	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
NYX	0:85b3fd62ea1a	1312	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
NYX	0:85b3fd62ea1a	1313	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
NYX	0:85b3fd62ea1a	1314	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
NYX	0:85b3fd62ea1a	1315	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
NYX	0:85b3fd62ea1a	1316	#define __HAL_ADC_JSQR ADC_JSQR
NYX	0:85b3fd62ea1a	1317
NYX	0:85b3fd62ea1a	1318	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
NYX	0:85b3fd62ea1a	1319	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
NYX	0:85b3fd62ea1a	1320	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
NYX	0:85b3fd62ea1a	1321	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
NYX	0:85b3fd62ea1a	1322	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
NYX	0:85b3fd62ea1a	1323	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
NYX	0:85b3fd62ea1a	1324	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
NYX	0:85b3fd62ea1a	1325	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
NYX	0:85b3fd62ea1a	1326
NYX	0:85b3fd62ea1a	1327	/**
NYX	0:85b3fd62ea1a	1328	* @}
NYX	0:85b3fd62ea1a	1329	*/
NYX	0:85b3fd62ea1a	1330
NYX	0:85b3fd62ea1a	1331	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1332	* @{
NYX	0:85b3fd62ea1a	1333	*/
NYX	0:85b3fd62ea1a	1334	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
NYX	0:85b3fd62ea1a	1335	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
NYX	0:85b3fd62ea1a	1336	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
NYX	0:85b3fd62ea1a	1337	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
NYX	0:85b3fd62ea1a	1338
NYX	0:85b3fd62ea1a	1339	/**
NYX	0:85b3fd62ea1a	1340	* @}
NYX	0:85b3fd62ea1a	1341	*/
NYX	0:85b3fd62ea1a	1342
NYX	0:85b3fd62ea1a	1343	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1344	* @{
NYX	0:85b3fd62ea1a	1345	*/
NYX	0:85b3fd62ea1a	1346	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
NYX	0:85b3fd62ea1a	1347	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
NYX	0:85b3fd62ea1a	1348	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
NYX	0:85b3fd62ea1a	1349	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
NYX	0:85b3fd62ea1a	1350	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
NYX	0:85b3fd62ea1a	1351	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
NYX	0:85b3fd62ea1a	1352	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
NYX	0:85b3fd62ea1a	1353	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
NYX	0:85b3fd62ea1a	1354	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
NYX	0:85b3fd62ea1a	1355	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
NYX	0:85b3fd62ea1a	1356	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
NYX	0:85b3fd62ea1a	1357	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
NYX	0:85b3fd62ea1a	1358	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
NYX	0:85b3fd62ea1a	1359	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
NYX	0:85b3fd62ea1a	1360	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
NYX	0:85b3fd62ea1a	1361	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
NYX	0:85b3fd62ea1a	1362
NYX	0:85b3fd62ea1a	1363	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
NYX	0:85b3fd62ea1a	1364	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
NYX	0:85b3fd62ea1a	1365	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
NYX	0:85b3fd62ea1a	1366	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
NYX	0:85b3fd62ea1a	1367	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
NYX	0:85b3fd62ea1a	1368	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
NYX	0:85b3fd62ea1a	1369	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
NYX	0:85b3fd62ea1a	1370	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
NYX	0:85b3fd62ea1a	1371	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
NYX	0:85b3fd62ea1a	1372	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
NYX	0:85b3fd62ea1a	1373	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
NYX	0:85b3fd62ea1a	1374	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
NYX	0:85b3fd62ea1a	1375	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
NYX	0:85b3fd62ea1a	1376	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
NYX	0:85b3fd62ea1a	1377
NYX	0:85b3fd62ea1a	1378
NYX	0:85b3fd62ea1a	1379	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
NYX	0:85b3fd62ea1a	1380	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
NYX	0:85b3fd62ea1a	1381	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
NYX	0:85b3fd62ea1a	1382	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
NYX	0:85b3fd62ea1a	1383	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
NYX	0:85b3fd62ea1a	1384	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
NYX	0:85b3fd62ea1a	1385	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
NYX	0:85b3fd62ea1a	1386	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
NYX	0:85b3fd62ea1a	1387	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
NYX	0:85b3fd62ea1a	1388	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
NYX	0:85b3fd62ea1a	1389	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
NYX	0:85b3fd62ea1a	1390	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
NYX	0:85b3fd62ea1a	1391	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
NYX	0:85b3fd62ea1a	1392	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
NYX	0:85b3fd62ea1a	1393	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
NYX	0:85b3fd62ea1a	1394	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
NYX	0:85b3fd62ea1a	1395	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
NYX	0:85b3fd62ea1a	1396	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
NYX	0:85b3fd62ea1a	1397	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
NYX	0:85b3fd62ea1a	1398	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
NYX	0:85b3fd62ea1a	1399	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
NYX	0:85b3fd62ea1a	1400	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
NYX	0:85b3fd62ea1a	1401	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
NYX	0:85b3fd62ea1a	1402	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
NYX	0:85b3fd62ea1a	1403
NYX	0:85b3fd62ea1a	1404	/**
NYX	0:85b3fd62ea1a	1405	* @}
NYX	0:85b3fd62ea1a	1406	*/
NYX	0:85b3fd62ea1a	1407
NYX	0:85b3fd62ea1a	1408	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1409	* @{
NYX	0:85b3fd62ea1a	1410	*/
NYX	0:85b3fd62ea1a	1411	#if defined(STM32F3)
NYX	0:85b3fd62ea1a	1412	#define COMP_START __HAL_COMP_ENABLE
NYX	0:85b3fd62ea1a	1413	#define COMP_STOP __HAL_COMP_DISABLE
NYX	0:85b3fd62ea1a	1414	#define COMP_LOCK __HAL_COMP_LOCK
NYX	0:85b3fd62ea1a	1415
NYX	0:85b3fd62ea1a	1416	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
NYX	0:85b3fd62ea1a	1417	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1418	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1419	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1420	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1421	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1422	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1423	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1424	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1425	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1426	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1427	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1428	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1429	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1430	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1431	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
NYX	0:85b3fd62ea1a	1432	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1433	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1434	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
NYX	0:85b3fd62ea1a	1435	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1436	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1437	__HAL_COMP_COMP6_EXTI_GET_FLAG())
NYX	0:85b3fd62ea1a	1438	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1439	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1440	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
NYX	0:85b3fd62ea1a	1441	# endif
NYX	0:85b3fd62ea1a	1442	# if defined(STM32F302xE) \|\| defined(STM32F302xC)
NYX	0:85b3fd62ea1a	1443	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1444	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1445	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1446	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1447	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1448	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1449	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1450	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1451	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1452	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1453	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1454	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1455	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1456	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1457	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1458	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1459	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1460	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1461	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1462	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
NYX	0:85b3fd62ea1a	1463	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1464	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1465	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1466	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
NYX	0:85b3fd62ea1a	1467	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1468	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1469	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1470	__HAL_COMP_COMP6_EXTI_GET_FLAG())
NYX	0:85b3fd62ea1a	1471	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1472	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1473	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1474	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
NYX	0:85b3fd62ea1a	1475	# endif
NYX	0:85b3fd62ea1a	1476	# if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
NYX	0:85b3fd62ea1a	1477	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1478	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1479	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1480	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1481	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1482	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1483	__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1484	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1485	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1486	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1487	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1488	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1489	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1490	__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1491	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1492	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1493	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1494	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1495	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1496	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1497	__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1498	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1499	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1500	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1501	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1502	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1503	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1504	__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1505	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1506	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1507	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1508	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1509	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1510	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1511	__HAL_COMP_COMP7_EXTI_ENABLE_IT())
NYX	0:85b3fd62ea1a	1512	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1513	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1514	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1515	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1516	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1517	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1518	__HAL_COMP_COMP7_EXTI_DISABLE_IT())
NYX	0:85b3fd62ea1a	1519	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1520	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1521	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1522	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1523	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1524	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1525	__HAL_COMP_COMP7_EXTI_GET_FLAG())
NYX	0:85b3fd62ea1a	1526	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1527	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1528	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1529	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1530	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1531	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1532	__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
NYX	0:85b3fd62ea1a	1533	# endif
NYX	0:85b3fd62ea1a	1534	# if defined(STM32F373xC) \|\|defined(STM32F378xx)
NYX	0:85b3fd62ea1a	1535	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1536	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1537	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1538	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1539	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1540	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1541	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1542	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1543	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1544	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
NYX	0:85b3fd62ea1a	1545	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1546	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
NYX	0:85b3fd62ea1a	1547	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1548	__HAL_COMP_COMP2_EXTI_GET_FLAG())
NYX	0:85b3fd62ea1a	1549	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1550	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
NYX	0:85b3fd62ea1a	1551	# endif
NYX	0:85b3fd62ea1a	1552	#else
NYX	0:85b3fd62ea1a	1553	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1554	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1555	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
NYX	0:85b3fd62ea1a	1556	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
NYX	0:85b3fd62ea1a	1557	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1558	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1559	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
NYX	0:85b3fd62ea1a	1560	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
NYX	0:85b3fd62ea1a	1561	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	1562	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
NYX	0:85b3fd62ea1a	1563	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	1564	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
NYX	0:85b3fd62ea1a	1565	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	1566	__HAL_COMP_COMP2_EXTI_GET_FLAG())
NYX	0:85b3fd62ea1a	1567	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	1568	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
NYX	0:85b3fd62ea1a	1569	#endif
NYX	0:85b3fd62ea1a	1570
NYX	0:85b3fd62ea1a	1571	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
NYX	0:85b3fd62ea1a	1572
NYX	0:85b3fd62ea1a	1573	#if defined(STM32L0) \|\| defined(STM32L4)
NYX	0:85b3fd62ea1a	1574	/* Note: On these STM32 families, the only argument of this macro */
NYX	0:85b3fd62ea1a	1575	/* is COMP_FLAG_LOCK. */
NYX	0:85b3fd62ea1a	1576	/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
NYX	0:85b3fd62ea1a	1577	/* argument. */
NYX	0:85b3fd62ea1a	1578	#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
NYX	0:85b3fd62ea1a	1579	#endif
NYX	0:85b3fd62ea1a	1580	/**
NYX	0:85b3fd62ea1a	1581	* @}
NYX	0:85b3fd62ea1a	1582	*/
NYX	0:85b3fd62ea1a	1583
NYX	0:85b3fd62ea1a	1584	#if defined(STM32L0) \|\| defined(STM32L4)
NYX	0:85b3fd62ea1a	1585	/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
NYX	0:85b3fd62ea1a	1586	* @{
NYX	0:85b3fd62ea1a	1587	*/
NYX	0:85b3fd62ea1a	1588	#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
NYX	0:85b3fd62ea1a	1589	#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
NYX	0:85b3fd62ea1a	1590	/**
NYX	0:85b3fd62ea1a	1591	* @}
NYX	0:85b3fd62ea1a	1592	*/
NYX	0:85b3fd62ea1a	1593	#endif
NYX	0:85b3fd62ea1a	1594
NYX	0:85b3fd62ea1a	1595	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1596	* @{
NYX	0:85b3fd62ea1a	1597	*/
NYX	0:85b3fd62ea1a	1598
NYX	0:85b3fd62ea1a	1599	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
NYX	0:85b3fd62ea1a	1600	((WAVE) == DAC_WAVE_NOISE)\|\| \
NYX	0:85b3fd62ea1a	1601	((WAVE) == DAC_WAVE_TRIANGLE))
NYX	0:85b3fd62ea1a	1602
NYX	0:85b3fd62ea1a	1603	/**
NYX	0:85b3fd62ea1a	1604	* @}
NYX	0:85b3fd62ea1a	1605	*/
NYX	0:85b3fd62ea1a	1606
NYX	0:85b3fd62ea1a	1607	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1608	* @{
NYX	0:85b3fd62ea1a	1609	*/
NYX	0:85b3fd62ea1a	1610
NYX	0:85b3fd62ea1a	1611	#define IS_WRPAREA IS_OB_WRPAREA
NYX	0:85b3fd62ea1a	1612	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
NYX	0:85b3fd62ea1a	1613	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
NYX	0:85b3fd62ea1a	1614	#define IS_TYPEERASE IS_FLASH_TYPEERASE
NYX	0:85b3fd62ea1a	1615	#define IS_NBSECTORS IS_FLASH_NBSECTORS
NYX	0:85b3fd62ea1a	1616	#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
NYX	0:85b3fd62ea1a	1617
NYX	0:85b3fd62ea1a	1618	/**
NYX	0:85b3fd62ea1a	1619	* @}
NYX	0:85b3fd62ea1a	1620	*/
NYX	0:85b3fd62ea1a	1621
NYX	0:85b3fd62ea1a	1622	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1623	* @{
NYX	0:85b3fd62ea1a	1624	*/
NYX	0:85b3fd62ea1a	1625
NYX	0:85b3fd62ea1a	1626	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
NYX	0:85b3fd62ea1a	1627	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
NYX	0:85b3fd62ea1a	1628	#if defined(STM32F1)
NYX	0:85b3fd62ea1a	1629	#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
NYX	0:85b3fd62ea1a	1630	#else
NYX	0:85b3fd62ea1a	1631	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
NYX	0:85b3fd62ea1a	1632	#endif /* STM32F1 */
NYX	0:85b3fd62ea1a	1633	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
NYX	0:85b3fd62ea1a	1634	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
NYX	0:85b3fd62ea1a	1635	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
NYX	0:85b3fd62ea1a	1636	#define __HAL_I2C_SPEED I2C_SPEED
NYX	0:85b3fd62ea1a	1637	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
NYX	0:85b3fd62ea1a	1638	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
NYX	0:85b3fd62ea1a	1639	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
NYX	0:85b3fd62ea1a	1640	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
NYX	0:85b3fd62ea1a	1641	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
NYX	0:85b3fd62ea1a	1642	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
NYX	0:85b3fd62ea1a	1643	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
NYX	0:85b3fd62ea1a	1644	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
NYX	0:85b3fd62ea1a	1645	/**
NYX	0:85b3fd62ea1a	1646	* @}
NYX	0:85b3fd62ea1a	1647	*/
NYX	0:85b3fd62ea1a	1648
NYX	0:85b3fd62ea1a	1649	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1650	* @{
NYX	0:85b3fd62ea1a	1651	*/
NYX	0:85b3fd62ea1a	1652
NYX	0:85b3fd62ea1a	1653	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
NYX	0:85b3fd62ea1a	1654	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
NYX	0:85b3fd62ea1a	1655
NYX	0:85b3fd62ea1a	1656	/**
NYX	0:85b3fd62ea1a	1657	* @}
NYX	0:85b3fd62ea1a	1658	*/
NYX	0:85b3fd62ea1a	1659
NYX	0:85b3fd62ea1a	1660	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1661	* @{
NYX	0:85b3fd62ea1a	1662	*/
NYX	0:85b3fd62ea1a	1663
NYX	0:85b3fd62ea1a	1664	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
NYX	0:85b3fd62ea1a	1665	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
NYX	0:85b3fd62ea1a	1666
NYX	0:85b3fd62ea1a	1667	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
NYX	0:85b3fd62ea1a	1668	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
NYX	0:85b3fd62ea1a	1669	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
NYX	0:85b3fd62ea1a	1670	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
NYX	0:85b3fd62ea1a	1671
NYX	0:85b3fd62ea1a	1672	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
NYX	0:85b3fd62ea1a	1673
NYX	0:85b3fd62ea1a	1674
NYX	0:85b3fd62ea1a	1675	/**
NYX	0:85b3fd62ea1a	1676	* @}
NYX	0:85b3fd62ea1a	1677	*/
NYX	0:85b3fd62ea1a	1678
NYX	0:85b3fd62ea1a	1679
NYX	0:85b3fd62ea1a	1680	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1681	* @{
NYX	0:85b3fd62ea1a	1682	*/
NYX	0:85b3fd62ea1a	1683	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
NYX	0:85b3fd62ea1a	1684	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
NYX	0:85b3fd62ea1a	1685	/**
NYX	0:85b3fd62ea1a	1686	* @}
NYX	0:85b3fd62ea1a	1687	*/
NYX	0:85b3fd62ea1a	1688
NYX	0:85b3fd62ea1a	1689
NYX	0:85b3fd62ea1a	1690	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1691	* @{
NYX	0:85b3fd62ea1a	1692	*/
NYX	0:85b3fd62ea1a	1693
NYX	0:85b3fd62ea1a	1694	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
NYX	0:85b3fd62ea1a	1695	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
NYX	0:85b3fd62ea1a	1696	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
NYX	0:85b3fd62ea1a	1697
NYX	0:85b3fd62ea1a	1698	/**
NYX	0:85b3fd62ea1a	1699	* @}
NYX	0:85b3fd62ea1a	1700	*/
NYX	0:85b3fd62ea1a	1701
NYX	0:85b3fd62ea1a	1702
NYX	0:85b3fd62ea1a	1703	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1704	* @{
NYX	0:85b3fd62ea1a	1705	*/
NYX	0:85b3fd62ea1a	1706	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
NYX	0:85b3fd62ea1a	1707	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
NYX	0:85b3fd62ea1a	1708	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
NYX	0:85b3fd62ea1a	1709	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
NYX	0:85b3fd62ea1a	1710	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
NYX	0:85b3fd62ea1a	1711	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
NYX	0:85b3fd62ea1a	1712	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
NYX	0:85b3fd62ea1a	1713	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
NYX	0:85b3fd62ea1a	1714	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
NYX	0:85b3fd62ea1a	1715	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
NYX	0:85b3fd62ea1a	1716	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
NYX	0:85b3fd62ea1a	1717	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
NYX	0:85b3fd62ea1a	1718	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
NYX	0:85b3fd62ea1a	1719
NYX	0:85b3fd62ea1a	1720	/**
NYX	0:85b3fd62ea1a	1721	* @}
NYX	0:85b3fd62ea1a	1722	*/
NYX	0:85b3fd62ea1a	1723
NYX	0:85b3fd62ea1a	1724
NYX	0:85b3fd62ea1a	1725	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	1726	* @{
NYX	0:85b3fd62ea1a	1727	*/
NYX	0:85b3fd62ea1a	1728	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
NYX	0:85b3fd62ea1a	1729	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
NYX	0:85b3fd62ea1a	1730	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	1731	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	1732	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
NYX	0:85b3fd62ea1a	1733	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
NYX	0:85b3fd62ea1a	1734	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
NYX	0:85b3fd62ea1a	1735	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
NYX	0:85b3fd62ea1a	1736	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
NYX	0:85b3fd62ea1a	1737	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
NYX	0:85b3fd62ea1a	1738	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
NYX	0:85b3fd62ea1a	1739	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
NYX	0:85b3fd62ea1a	1740	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
NYX	0:85b3fd62ea1a	1741	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
NYX	0:85b3fd62ea1a	1742	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
NYX	0:85b3fd62ea1a	1743	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
NYX	0:85b3fd62ea1a	1744	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
NYX	0:85b3fd62ea1a	1745	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
NYX	0:85b3fd62ea1a	1746	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
NYX	0:85b3fd62ea1a	1747	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	1748	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	1749	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
NYX	0:85b3fd62ea1a	1750	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
NYX	0:85b3fd62ea1a	1751	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	1752	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
NYX	0:85b3fd62ea1a	1753	#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
NYX	0:85b3fd62ea1a	1754	#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
NYX	0:85b3fd62ea1a	1755	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
NYX	0:85b3fd62ea1a	1756	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
NYX	0:85b3fd62ea1a	1757	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
NYX	0:85b3fd62ea1a	1758	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
NYX	0:85b3fd62ea1a	1759	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	1760	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	1761	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
NYX	0:85b3fd62ea1a	1762	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
NYX	0:85b3fd62ea1a	1763
NYX	0:85b3fd62ea1a	1764	#if defined (STM32F4)
NYX	0:85b3fd62ea1a	1765	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
NYX	0:85b3fd62ea1a	1766	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
NYX	0:85b3fd62ea1a	1767	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
NYX	0:85b3fd62ea1a	1768	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
NYX	0:85b3fd62ea1a	1769	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
NYX	0:85b3fd62ea1a	1770	#else
NYX	0:85b3fd62ea1a	1771	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
NYX	0:85b3fd62ea1a	1772	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
NYX	0:85b3fd62ea1a	1773	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
NYX	0:85b3fd62ea1a	1774	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
NYX	0:85b3fd62ea1a	1775	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
NYX	0:85b3fd62ea1a	1776	#endif /* STM32F4 */
NYX	0:85b3fd62ea1a	1777	/**
NYX	0:85b3fd62ea1a	1778	* @}
NYX	0:85b3fd62ea1a	1779	*/
NYX	0:85b3fd62ea1a	1780
NYX	0:85b3fd62ea1a	1781
NYX	0:85b3fd62ea1a	1782	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
NYX	0:85b3fd62ea1a	1783	* @{
NYX	0:85b3fd62ea1a	1784	*/
NYX	0:85b3fd62ea1a	1785
NYX	0:85b3fd62ea1a	1786	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
NYX	0:85b3fd62ea1a	1787	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
NYX	0:85b3fd62ea1a	1788
NYX	0:85b3fd62ea1a	1789	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
NYX	0:85b3fd62ea1a	1790	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
NYX	0:85b3fd62ea1a	1791
NYX	0:85b3fd62ea1a	1792	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
NYX	0:85b3fd62ea1a	1793	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
NYX	0:85b3fd62ea1a	1794	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1795	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1796	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
NYX	0:85b3fd62ea1a	1797	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
NYX	0:85b3fd62ea1a	1798	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
NYX	0:85b3fd62ea1a	1799	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
NYX	0:85b3fd62ea1a	1800	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
NYX	0:85b3fd62ea1a	1801	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
NYX	0:85b3fd62ea1a	1802	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1803	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1804	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
NYX	0:85b3fd62ea1a	1805	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
NYX	0:85b3fd62ea1a	1806	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
NYX	0:85b3fd62ea1a	1807	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
NYX	0:85b3fd62ea1a	1808	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
NYX	0:85b3fd62ea1a	1809	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
NYX	0:85b3fd62ea1a	1810	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
NYX	0:85b3fd62ea1a	1811	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
NYX	0:85b3fd62ea1a	1812	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
NYX	0:85b3fd62ea1a	1813	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
NYX	0:85b3fd62ea1a	1814	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1815	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1816	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
NYX	0:85b3fd62ea1a	1817	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
NYX	0:85b3fd62ea1a	1818	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1819	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1820	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
NYX	0:85b3fd62ea1a	1821	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
NYX	0:85b3fd62ea1a	1822	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
NYX	0:85b3fd62ea1a	1823	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
NYX	0:85b3fd62ea1a	1824	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
NYX	0:85b3fd62ea1a	1825	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
NYX	0:85b3fd62ea1a	1826	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
NYX	0:85b3fd62ea1a	1827	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
NYX	0:85b3fd62ea1a	1828	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
NYX	0:85b3fd62ea1a	1829	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
NYX	0:85b3fd62ea1a	1830	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
NYX	0:85b3fd62ea1a	1831	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
NYX	0:85b3fd62ea1a	1832	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
NYX	0:85b3fd62ea1a	1833	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
NYX	0:85b3fd62ea1a	1834	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
NYX	0:85b3fd62ea1a	1835	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
NYX	0:85b3fd62ea1a	1836	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
NYX	0:85b3fd62ea1a	1837	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
NYX	0:85b3fd62ea1a	1838	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
NYX	0:85b3fd62ea1a	1839	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
NYX	0:85b3fd62ea1a	1840	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
NYX	0:85b3fd62ea1a	1841	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
NYX	0:85b3fd62ea1a	1842	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
NYX	0:85b3fd62ea1a	1843	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
NYX	0:85b3fd62ea1a	1844	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
NYX	0:85b3fd62ea1a	1845	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
NYX	0:85b3fd62ea1a	1846	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1847	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1848	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
NYX	0:85b3fd62ea1a	1849	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
NYX	0:85b3fd62ea1a	1850	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
NYX	0:85b3fd62ea1a	1851	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
NYX	0:85b3fd62ea1a	1852	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
NYX	0:85b3fd62ea1a	1853	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
NYX	0:85b3fd62ea1a	1854	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
NYX	0:85b3fd62ea1a	1855	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
NYX	0:85b3fd62ea1a	1856	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
NYX	0:85b3fd62ea1a	1857	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
NYX	0:85b3fd62ea1a	1858	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
NYX	0:85b3fd62ea1a	1859	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
NYX	0:85b3fd62ea1a	1860	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
NYX	0:85b3fd62ea1a	1861	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
NYX	0:85b3fd62ea1a	1862	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
NYX	0:85b3fd62ea1a	1863	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
NYX	0:85b3fd62ea1a	1864	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1865	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1866	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
NYX	0:85b3fd62ea1a	1867	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
NYX	0:85b3fd62ea1a	1868	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
NYX	0:85b3fd62ea1a	1869	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
NYX	0:85b3fd62ea1a	1870	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1871	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1872	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
NYX	0:85b3fd62ea1a	1873	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
NYX	0:85b3fd62ea1a	1874	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
NYX	0:85b3fd62ea1a	1875	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
NYX	0:85b3fd62ea1a	1876	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
NYX	0:85b3fd62ea1a	1877	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
NYX	0:85b3fd62ea1a	1878	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
NYX	0:85b3fd62ea1a	1879	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
NYX	0:85b3fd62ea1a	1880	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1881	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1882	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
NYX	0:85b3fd62ea1a	1883	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
NYX	0:85b3fd62ea1a	1884	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
NYX	0:85b3fd62ea1a	1885	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
NYX	0:85b3fd62ea1a	1886	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
NYX	0:85b3fd62ea1a	1887	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
NYX	0:85b3fd62ea1a	1888	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
NYX	0:85b3fd62ea1a	1889	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
NYX	0:85b3fd62ea1a	1890	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1891	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1892	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
NYX	0:85b3fd62ea1a	1893	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
NYX	0:85b3fd62ea1a	1894	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
NYX	0:85b3fd62ea1a	1895	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
NYX	0:85b3fd62ea1a	1896	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1897	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1898	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
NYX	0:85b3fd62ea1a	1899	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
NYX	0:85b3fd62ea1a	1900	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
NYX	0:85b3fd62ea1a	1901	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
NYX	0:85b3fd62ea1a	1902	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1903	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1904	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
NYX	0:85b3fd62ea1a	1905	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
NYX	0:85b3fd62ea1a	1906	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
NYX	0:85b3fd62ea1a	1907	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
NYX	0:85b3fd62ea1a	1908	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
NYX	0:85b3fd62ea1a	1909	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
NYX	0:85b3fd62ea1a	1910	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
NYX	0:85b3fd62ea1a	1911	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
NYX	0:85b3fd62ea1a	1912	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
NYX	0:85b3fd62ea1a	1913	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
NYX	0:85b3fd62ea1a	1914	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
NYX	0:85b3fd62ea1a	1915	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
NYX	0:85b3fd62ea1a	1916	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
NYX	0:85b3fd62ea1a	1917	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
NYX	0:85b3fd62ea1a	1918	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1919	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1920	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
NYX	0:85b3fd62ea1a	1921	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
NYX	0:85b3fd62ea1a	1922	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
NYX	0:85b3fd62ea1a	1923	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
NYX	0:85b3fd62ea1a	1924	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
NYX	0:85b3fd62ea1a	1925	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
NYX	0:85b3fd62ea1a	1926	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1927	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1928	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
NYX	0:85b3fd62ea1a	1929	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
NYX	0:85b3fd62ea1a	1930	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1931	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1932	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
NYX	0:85b3fd62ea1a	1933	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
NYX	0:85b3fd62ea1a	1934	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
NYX	0:85b3fd62ea1a	1935	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
NYX	0:85b3fd62ea1a	1936	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
NYX	0:85b3fd62ea1a	1937	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
NYX	0:85b3fd62ea1a	1938	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1939	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1940	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
NYX	0:85b3fd62ea1a	1941	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
NYX	0:85b3fd62ea1a	1942	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
NYX	0:85b3fd62ea1a	1943	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
NYX	0:85b3fd62ea1a	1944	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1945	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1946	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
NYX	0:85b3fd62ea1a	1947	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
NYX	0:85b3fd62ea1a	1948	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
NYX	0:85b3fd62ea1a	1949	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
NYX	0:85b3fd62ea1a	1950	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1951	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1952	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
NYX	0:85b3fd62ea1a	1953	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
NYX	0:85b3fd62ea1a	1954	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
NYX	0:85b3fd62ea1a	1955	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
NYX	0:85b3fd62ea1a	1956	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1957	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1958	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
NYX	0:85b3fd62ea1a	1959	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
NYX	0:85b3fd62ea1a	1960	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
NYX	0:85b3fd62ea1a	1961	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
NYX	0:85b3fd62ea1a	1962	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1963	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1964	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
NYX	0:85b3fd62ea1a	1965	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
NYX	0:85b3fd62ea1a	1966	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
NYX	0:85b3fd62ea1a	1967	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
NYX	0:85b3fd62ea1a	1968	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1969	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1970	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
NYX	0:85b3fd62ea1a	1971	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
NYX	0:85b3fd62ea1a	1972	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
NYX	0:85b3fd62ea1a	1973	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
NYX	0:85b3fd62ea1a	1974	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1975	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1976	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
NYX	0:85b3fd62ea1a	1977	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
NYX	0:85b3fd62ea1a	1978	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
NYX	0:85b3fd62ea1a	1979	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
NYX	0:85b3fd62ea1a	1980	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1981	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1982	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
NYX	0:85b3fd62ea1a	1983	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
NYX	0:85b3fd62ea1a	1984	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
NYX	0:85b3fd62ea1a	1985	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
NYX	0:85b3fd62ea1a	1986	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1987	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1988	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
NYX	0:85b3fd62ea1a	1989	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
NYX	0:85b3fd62ea1a	1990	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
NYX	0:85b3fd62ea1a	1991	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
NYX	0:85b3fd62ea1a	1992	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1993	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	1994	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
NYX	0:85b3fd62ea1a	1995	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
NYX	0:85b3fd62ea1a	1996	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
NYX	0:85b3fd62ea1a	1997	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
NYX	0:85b3fd62ea1a	1998	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	1999	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2000	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
NYX	0:85b3fd62ea1a	2001	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
NYX	0:85b3fd62ea1a	2002	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
NYX	0:85b3fd62ea1a	2003	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
NYX	0:85b3fd62ea1a	2004	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2005	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2006	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
NYX	0:85b3fd62ea1a	2007	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
NYX	0:85b3fd62ea1a	2008	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2009	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2010	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2011	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2012	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
NYX	0:85b3fd62ea1a	2013	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2014	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
NYX	0:85b3fd62ea1a	2015	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
NYX	0:85b3fd62ea1a	2016	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2017	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2018	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
NYX	0:85b3fd62ea1a	2019	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
NYX	0:85b3fd62ea1a	2020	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2021	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2022	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2023	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2024	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
NYX	0:85b3fd62ea1a	2025	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2026	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
NYX	0:85b3fd62ea1a	2027	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
NYX	0:85b3fd62ea1a	2028	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2029	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2030	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
NYX	0:85b3fd62ea1a	2031	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
NYX	0:85b3fd62ea1a	2032	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
NYX	0:85b3fd62ea1a	2033	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
NYX	0:85b3fd62ea1a	2034	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2035	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2036	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
NYX	0:85b3fd62ea1a	2037	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
NYX	0:85b3fd62ea1a	2038	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
NYX	0:85b3fd62ea1a	2039	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
NYX	0:85b3fd62ea1a	2040	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2041	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2042	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
NYX	0:85b3fd62ea1a	2043	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
NYX	0:85b3fd62ea1a	2044	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
NYX	0:85b3fd62ea1a	2045	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
NYX	0:85b3fd62ea1a	2046	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2047	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2048	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
NYX	0:85b3fd62ea1a	2049	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
NYX	0:85b3fd62ea1a	2050	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
NYX	0:85b3fd62ea1a	2051	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
NYX	0:85b3fd62ea1a	2052	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2053	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2054	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
NYX	0:85b3fd62ea1a	2055	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
NYX	0:85b3fd62ea1a	2056	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2057	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2058	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2059	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2060	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
NYX	0:85b3fd62ea1a	2061	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2062	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
NYX	0:85b3fd62ea1a	2063	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
NYX	0:85b3fd62ea1a	2064	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2065	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2066	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
NYX	0:85b3fd62ea1a	2067	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
NYX	0:85b3fd62ea1a	2068	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
NYX	0:85b3fd62ea1a	2069	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
NYX	0:85b3fd62ea1a	2070	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
NYX	0:85b3fd62ea1a	2071	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
NYX	0:85b3fd62ea1a	2072	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2073	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2074	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
NYX	0:85b3fd62ea1a	2075	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
NYX	0:85b3fd62ea1a	2076	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2077	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2078	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2079	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2080	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
NYX	0:85b3fd62ea1a	2081	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2082	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
NYX	0:85b3fd62ea1a	2083	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
NYX	0:85b3fd62ea1a	2084	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2085	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2086	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
NYX	0:85b3fd62ea1a	2087	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
NYX	0:85b3fd62ea1a	2088	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
NYX	0:85b3fd62ea1a	2089	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
NYX	0:85b3fd62ea1a	2090	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2091	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2092	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
NYX	0:85b3fd62ea1a	2093	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
NYX	0:85b3fd62ea1a	2094	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
NYX	0:85b3fd62ea1a	2095	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
NYX	0:85b3fd62ea1a	2096	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2097	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2098	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2099	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2100	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2101	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2102	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2103	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2104	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
NYX	0:85b3fd62ea1a	2105	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2106	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
NYX	0:85b3fd62ea1a	2107	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
NYX	0:85b3fd62ea1a	2108	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2109	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2110	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
NYX	0:85b3fd62ea1a	2111	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
NYX	0:85b3fd62ea1a	2112	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2113	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2114	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2115	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2116	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
NYX	0:85b3fd62ea1a	2117	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2118	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
NYX	0:85b3fd62ea1a	2119	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
NYX	0:85b3fd62ea1a	2120	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
NYX	0:85b3fd62ea1a	2121	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
NYX	0:85b3fd62ea1a	2122	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
NYX	0:85b3fd62ea1a	2123	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
NYX	0:85b3fd62ea1a	2124	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
NYX	0:85b3fd62ea1a	2125	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
NYX	0:85b3fd62ea1a	2126	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
NYX	0:85b3fd62ea1a	2127	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
NYX	0:85b3fd62ea1a	2128	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
NYX	0:85b3fd62ea1a	2129	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
NYX	0:85b3fd62ea1a	2130	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
NYX	0:85b3fd62ea1a	2131	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
NYX	0:85b3fd62ea1a	2132	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
NYX	0:85b3fd62ea1a	2133	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
NYX	0:85b3fd62ea1a	2134	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
NYX	0:85b3fd62ea1a	2135	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
NYX	0:85b3fd62ea1a	2136	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
NYX	0:85b3fd62ea1a	2137	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
NYX	0:85b3fd62ea1a	2138	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
NYX	0:85b3fd62ea1a	2139	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
NYX	0:85b3fd62ea1a	2140	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2141	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2142	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
NYX	0:85b3fd62ea1a	2143	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
NYX	0:85b3fd62ea1a	2144	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
NYX	0:85b3fd62ea1a	2145	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
NYX	0:85b3fd62ea1a	2146	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2147	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2148	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
NYX	0:85b3fd62ea1a	2149	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
NYX	0:85b3fd62ea1a	2150	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
NYX	0:85b3fd62ea1a	2151	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
NYX	0:85b3fd62ea1a	2152	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2153	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2154	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
NYX	0:85b3fd62ea1a	2155	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
NYX	0:85b3fd62ea1a	2156	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
NYX	0:85b3fd62ea1a	2157	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
NYX	0:85b3fd62ea1a	2158	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2159	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2160	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
NYX	0:85b3fd62ea1a	2161	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
NYX	0:85b3fd62ea1a	2162	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
NYX	0:85b3fd62ea1a	2163	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
NYX	0:85b3fd62ea1a	2164	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2165	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2166	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
NYX	0:85b3fd62ea1a	2167	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
NYX	0:85b3fd62ea1a	2168	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
NYX	0:85b3fd62ea1a	2169	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
NYX	0:85b3fd62ea1a	2170	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2171	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2172	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
NYX	0:85b3fd62ea1a	2173	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
NYX	0:85b3fd62ea1a	2174	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
NYX	0:85b3fd62ea1a	2175	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
NYX	0:85b3fd62ea1a	2176	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2177	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2178	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
NYX	0:85b3fd62ea1a	2179	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
NYX	0:85b3fd62ea1a	2180	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
NYX	0:85b3fd62ea1a	2181	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
NYX	0:85b3fd62ea1a	2182	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2183	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2184	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
NYX	0:85b3fd62ea1a	2185	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
NYX	0:85b3fd62ea1a	2186	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
NYX	0:85b3fd62ea1a	2187	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
NYX	0:85b3fd62ea1a	2188	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2189	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2190	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
NYX	0:85b3fd62ea1a	2191	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
NYX	0:85b3fd62ea1a	2192	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
NYX	0:85b3fd62ea1a	2193	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
NYX	0:85b3fd62ea1a	2194	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2195	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2196	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
NYX	0:85b3fd62ea1a	2197	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
NYX	0:85b3fd62ea1a	2198	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
NYX	0:85b3fd62ea1a	2199	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
NYX	0:85b3fd62ea1a	2200	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
NYX	0:85b3fd62ea1a	2201	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
NYX	0:85b3fd62ea1a	2202	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
NYX	0:85b3fd62ea1a	2203	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
NYX	0:85b3fd62ea1a	2204	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2205	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2206	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
NYX	0:85b3fd62ea1a	2207	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
NYX	0:85b3fd62ea1a	2208	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
NYX	0:85b3fd62ea1a	2209	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
NYX	0:85b3fd62ea1a	2210	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2211	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2212	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
NYX	0:85b3fd62ea1a	2213	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
NYX	0:85b3fd62ea1a	2214	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
NYX	0:85b3fd62ea1a	2215	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
NYX	0:85b3fd62ea1a	2216	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2217	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2218	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
NYX	0:85b3fd62ea1a	2219	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
NYX	0:85b3fd62ea1a	2220	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2221	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2222	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2223	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2224	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
NYX	0:85b3fd62ea1a	2225	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2226	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
NYX	0:85b3fd62ea1a	2227	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
NYX	0:85b3fd62ea1a	2228	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2229	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2230	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
NYX	0:85b3fd62ea1a	2231	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
NYX	0:85b3fd62ea1a	2232	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
NYX	0:85b3fd62ea1a	2233	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
NYX	0:85b3fd62ea1a	2234	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2235	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2236	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
NYX	0:85b3fd62ea1a	2237	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
NYX	0:85b3fd62ea1a	2238	#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
NYX	0:85b3fd62ea1a	2239	#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
NYX	0:85b3fd62ea1a	2240	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2241	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2242	#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
NYX	0:85b3fd62ea1a	2243	#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
NYX	0:85b3fd62ea1a	2244	#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
NYX	0:85b3fd62ea1a	2245	#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
NYX	0:85b3fd62ea1a	2246	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2247	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2248	#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
NYX	0:85b3fd62ea1a	2249	#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
NYX	0:85b3fd62ea1a	2250	#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
NYX	0:85b3fd62ea1a	2251	#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
NYX	0:85b3fd62ea1a	2252	#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
NYX	0:85b3fd62ea1a	2253	#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
NYX	0:85b3fd62ea1a	2254	#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
NYX	0:85b3fd62ea1a	2255	#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
NYX	0:85b3fd62ea1a	2256	#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
NYX	0:85b3fd62ea1a	2257	#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
NYX	0:85b3fd62ea1a	2258	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
NYX	0:85b3fd62ea1a	2259	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
NYX	0:85b3fd62ea1a	2260	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
NYX	0:85b3fd62ea1a	2261	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2262	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2263	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
NYX	0:85b3fd62ea1a	2264	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
NYX	0:85b3fd62ea1a	2265	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
NYX	0:85b3fd62ea1a	2266	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
NYX	0:85b3fd62ea1a	2267	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
NYX	0:85b3fd62ea1a	2268	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2269	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2270	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
NYX	0:85b3fd62ea1a	2271	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
NYX	0:85b3fd62ea1a	2272	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
NYX	0:85b3fd62ea1a	2273	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
NYX	0:85b3fd62ea1a	2274	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
NYX	0:85b3fd62ea1a	2275	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
NYX	0:85b3fd62ea1a	2276	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2277	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2278	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
NYX	0:85b3fd62ea1a	2279	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
NYX	0:85b3fd62ea1a	2280	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
NYX	0:85b3fd62ea1a	2281	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
NYX	0:85b3fd62ea1a	2282	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2283	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2284	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
NYX	0:85b3fd62ea1a	2285	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
NYX	0:85b3fd62ea1a	2286	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2287	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2288	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
NYX	0:85b3fd62ea1a	2289	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
NYX	0:85b3fd62ea1a	2290	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
NYX	0:85b3fd62ea1a	2291	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
NYX	0:85b3fd62ea1a	2292
NYX	0:85b3fd62ea1a	2293	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
NYX	0:85b3fd62ea1a	2294	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
NYX	0:85b3fd62ea1a	2295	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2296	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2297	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
NYX	0:85b3fd62ea1a	2298	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
NYX	0:85b3fd62ea1a	2299	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
NYX	0:85b3fd62ea1a	2300	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
NYX	0:85b3fd62ea1a	2301	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2302	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2303	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2304	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2305	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2306	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2307	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2308	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2309	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
NYX	0:85b3fd62ea1a	2310	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
NYX	0:85b3fd62ea1a	2311	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
NYX	0:85b3fd62ea1a	2312	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
NYX	0:85b3fd62ea1a	2313	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
NYX	0:85b3fd62ea1a	2314	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2315	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2316	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
NYX	0:85b3fd62ea1a	2317	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
NYX	0:85b3fd62ea1a	2318	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
NYX	0:85b3fd62ea1a	2319	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
NYX	0:85b3fd62ea1a	2320	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
NYX	0:85b3fd62ea1a	2321	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2322	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2323	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
NYX	0:85b3fd62ea1a	2324	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
NYX	0:85b3fd62ea1a	2325	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
NYX	0:85b3fd62ea1a	2326	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
NYX	0:85b3fd62ea1a	2327	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2328	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2329	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
NYX	0:85b3fd62ea1a	2330	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
NYX	0:85b3fd62ea1a	2331	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
NYX	0:85b3fd62ea1a	2332	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
NYX	0:85b3fd62ea1a	2333	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2334	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2335	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2336	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2337	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2338	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2339	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2340	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2341	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2342	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2343	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2344	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2345	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2346	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
NYX	0:85b3fd62ea1a	2347	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
NYX	0:85b3fd62ea1a	2348	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2349	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2350	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
NYX	0:85b3fd62ea1a	2351	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
NYX	0:85b3fd62ea1a	2352	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
NYX	0:85b3fd62ea1a	2353	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
NYX	0:85b3fd62ea1a	2354	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
NYX	0:85b3fd62ea1a	2355	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
NYX	0:85b3fd62ea1a	2356	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2357	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2358	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
NYX	0:85b3fd62ea1a	2359	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
NYX	0:85b3fd62ea1a	2360	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
NYX	0:85b3fd62ea1a	2361	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
NYX	0:85b3fd62ea1a	2362	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2363	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2364	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
NYX	0:85b3fd62ea1a	2365	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
NYX	0:85b3fd62ea1a	2366	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
NYX	0:85b3fd62ea1a	2367	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
NYX	0:85b3fd62ea1a	2368	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2369	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2370	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
NYX	0:85b3fd62ea1a	2371	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
NYX	0:85b3fd62ea1a	2372	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
NYX	0:85b3fd62ea1a	2373	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
NYX	0:85b3fd62ea1a	2374	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2375	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2376	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
NYX	0:85b3fd62ea1a	2377	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
NYX	0:85b3fd62ea1a	2378	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
NYX	0:85b3fd62ea1a	2379	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2380	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2381	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
NYX	0:85b3fd62ea1a	2382	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
NYX	0:85b3fd62ea1a	2383	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
NYX	0:85b3fd62ea1a	2384	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
NYX	0:85b3fd62ea1a	2385	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
NYX	0:85b3fd62ea1a	2386	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
NYX	0:85b3fd62ea1a	2387	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2388	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2389	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
NYX	0:85b3fd62ea1a	2390	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
NYX	0:85b3fd62ea1a	2391	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
NYX	0:85b3fd62ea1a	2392	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
NYX	0:85b3fd62ea1a	2393	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2394	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2395	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
NYX	0:85b3fd62ea1a	2396	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
NYX	0:85b3fd62ea1a	2397	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
NYX	0:85b3fd62ea1a	2398	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
NYX	0:85b3fd62ea1a	2399	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2400	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2401	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2402	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2403	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
NYX	0:85b3fd62ea1a	2404	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
NYX	0:85b3fd62ea1a	2405	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2406	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2407	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2408	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2409	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
NYX	0:85b3fd62ea1a	2410	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
NYX	0:85b3fd62ea1a	2411	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
NYX	0:85b3fd62ea1a	2412	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
NYX	0:85b3fd62ea1a	2413	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2414	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2415	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
NYX	0:85b3fd62ea1a	2416	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
NYX	0:85b3fd62ea1a	2417	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
NYX	0:85b3fd62ea1a	2418	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2419	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2420	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2421	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2422	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2423	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2424	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2425	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2426	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2427	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
NYX	0:85b3fd62ea1a	2428	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
NYX	0:85b3fd62ea1a	2429	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2430	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2431	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
NYX	0:85b3fd62ea1a	2432	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
NYX	0:85b3fd62ea1a	2433	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2434	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2435	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
NYX	0:85b3fd62ea1a	2436	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
NYX	0:85b3fd62ea1a	2437	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
NYX	0:85b3fd62ea1a	2438	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
NYX	0:85b3fd62ea1a	2439	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2440	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2441
NYX	0:85b3fd62ea1a	2442	/* alias define maintained for legacy */
NYX	0:85b3fd62ea1a	2443	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
NYX	0:85b3fd62ea1a	2444	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
NYX	0:85b3fd62ea1a	2445
NYX	0:85b3fd62ea1a	2446	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
NYX	0:85b3fd62ea1a	2447	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
NYX	0:85b3fd62ea1a	2448	#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
NYX	0:85b3fd62ea1a	2449	#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
NYX	0:85b3fd62ea1a	2450	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
NYX	0:85b3fd62ea1a	2451	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
NYX	0:85b3fd62ea1a	2452	#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
NYX	0:85b3fd62ea1a	2453	#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
NYX	0:85b3fd62ea1a	2454	#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
NYX	0:85b3fd62ea1a	2455	#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
NYX	0:85b3fd62ea1a	2456	#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
NYX	0:85b3fd62ea1a	2457	#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
NYX	0:85b3fd62ea1a	2458	#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
NYX	0:85b3fd62ea1a	2459	#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
NYX	0:85b3fd62ea1a	2460	#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2461	#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2462	#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2463	#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
NYX	0:85b3fd62ea1a	2464	#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
NYX	0:85b3fd62ea1a	2465	#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2466	#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
NYX	0:85b3fd62ea1a	2467	#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
NYX	0:85b3fd62ea1a	2468
NYX	0:85b3fd62ea1a	2469	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
NYX	0:85b3fd62ea1a	2470	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
NYX	0:85b3fd62ea1a	2471	#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
NYX	0:85b3fd62ea1a	2472	#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
NYX	0:85b3fd62ea1a	2473	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
NYX	0:85b3fd62ea1a	2474	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
NYX	0:85b3fd62ea1a	2475	#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
NYX	0:85b3fd62ea1a	2476	#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
NYX	0:85b3fd62ea1a	2477	#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
NYX	0:85b3fd62ea1a	2478	#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
NYX	0:85b3fd62ea1a	2479	#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
NYX	0:85b3fd62ea1a	2480	#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
NYX	0:85b3fd62ea1a	2481	#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
NYX	0:85b3fd62ea1a	2482	#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
NYX	0:85b3fd62ea1a	2483	#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
NYX	0:85b3fd62ea1a	2484	#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2485	#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
NYX	0:85b3fd62ea1a	2486	#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
NYX	0:85b3fd62ea1a	2487	#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
NYX	0:85b3fd62ea1a	2488	#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2489	#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
NYX	0:85b3fd62ea1a	2490	#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
NYX	0:85b3fd62ea1a	2491
NYX	0:85b3fd62ea1a	2492	#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2493	#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2494	#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2495	#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2496	#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2497	#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2498	#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2499	#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2500	#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2501	#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2502	#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2503	#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2504	#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2505	#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2506	#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2507	#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2508	#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2509	#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2510	#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2511	#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2512	#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2513	#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2514	#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2515	#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2516	#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2517	#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2518	#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2519	#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2520	#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2521	#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2522	#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2523	#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2524	#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2525	#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2526	#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2527	#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2528	#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2529	#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2530	#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2531	#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2532	#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2533	#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2534	#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2535	#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2536	#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2537	#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2538	#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2539	#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2540	#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2541	#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2542	#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2543	#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2544	#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2545	#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2546	#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2547	#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2548	#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2549	#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2550	#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2551	#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2552	#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2553	#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2554	#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2555	#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2556	#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2557	#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2558	#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2559	#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2560	#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2561	#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2562	#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2563	#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2564	#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2565	#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2566	#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2567	#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2568	#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2569	#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2570	#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2571	#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2572	#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2573	#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2574	#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2575	#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2576	#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2577	#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2578	#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2579	#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2580	#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2581	#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2582	#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2583	#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2584	#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2585	#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2586	#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2587	#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2588	#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2589	#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2590	#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2591	#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2592	#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2593	#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2594	#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2595	#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2596	#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2597	#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2598	#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2599	#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2600	#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2601	#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2602	#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2603	#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2604	#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2605	#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2606	#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2607	#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2608
NYX	0:85b3fd62ea1a	2609	#if defined(STM32F4)
NYX	0:85b3fd62ea1a	2610	#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
NYX	0:85b3fd62ea1a	2611	#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
NYX	0:85b3fd62ea1a	2612	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2613	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2614	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
NYX	0:85b3fd62ea1a	2615	#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
NYX	0:85b3fd62ea1a	2616	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2617	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2618	#define Sdmmc1ClockSelection SdioClockSelection
NYX	0:85b3fd62ea1a	2619	#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
NYX	0:85b3fd62ea1a	2620	#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
NYX	0:85b3fd62ea1a	2621	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
NYX	0:85b3fd62ea1a	2622	#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
NYX	0:85b3fd62ea1a	2623	#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
NYX	0:85b3fd62ea1a	2624	#endif
NYX	0:85b3fd62ea1a	2625
NYX	0:85b3fd62ea1a	2626	#if defined(STM32F7) \|\| defined(STM32L4)
NYX	0:85b3fd62ea1a	2627	#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
NYX	0:85b3fd62ea1a	2628	#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2629	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2630	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2631	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2632	#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2633	#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2634	#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2635	#define SdioClockSelection Sdmmc1ClockSelection
NYX	0:85b3fd62ea1a	2636	#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
NYX	0:85b3fd62ea1a	2637	#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
NYX	0:85b3fd62ea1a	2638	#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
NYX	0:85b3fd62ea1a	2639	#endif
NYX	0:85b3fd62ea1a	2640
NYX	0:85b3fd62ea1a	2641	#if defined(STM32F7)
NYX	0:85b3fd62ea1a	2642	#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
NYX	0:85b3fd62ea1a	2643	#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
NYX	0:85b3fd62ea1a	2644	#endif
NYX	0:85b3fd62ea1a	2645
NYX	0:85b3fd62ea1a	2646	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
NYX	0:85b3fd62ea1a	2647	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
NYX	0:85b3fd62ea1a	2648
NYX	0:85b3fd62ea1a	2649	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
NYX	0:85b3fd62ea1a	2650
NYX	0:85b3fd62ea1a	2651	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
NYX	0:85b3fd62ea1a	2652	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
NYX	0:85b3fd62ea1a	2653	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
NYX	0:85b3fd62ea1a	2654	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
NYX	0:85b3fd62ea1a	2655	#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
NYX	0:85b3fd62ea1a	2656
NYX	0:85b3fd62ea1a	2657	#define RCC_IT_HSI14 RCC_IT_HSI14RDY
NYX	0:85b3fd62ea1a	2658
NYX	0:85b3fd62ea1a	2659	#define RCC_IT_CSSLSE RCC_IT_LSECSS
NYX	0:85b3fd62ea1a	2660	#define RCC_IT_CSSHSE RCC_IT_CSS
NYX	0:85b3fd62ea1a	2661
NYX	0:85b3fd62ea1a	2662	#define RCC_PLLMUL_3 RCC_PLL_MUL3
NYX	0:85b3fd62ea1a	2663	#define RCC_PLLMUL_4 RCC_PLL_MUL4
NYX	0:85b3fd62ea1a	2664	#define RCC_PLLMUL_6 RCC_PLL_MUL6
NYX	0:85b3fd62ea1a	2665	#define RCC_PLLMUL_8 RCC_PLL_MUL8
NYX	0:85b3fd62ea1a	2666	#define RCC_PLLMUL_12 RCC_PLL_MUL12
NYX	0:85b3fd62ea1a	2667	#define RCC_PLLMUL_16 RCC_PLL_MUL16
NYX	0:85b3fd62ea1a	2668	#define RCC_PLLMUL_24 RCC_PLL_MUL24
NYX	0:85b3fd62ea1a	2669	#define RCC_PLLMUL_32 RCC_PLL_MUL32
NYX	0:85b3fd62ea1a	2670	#define RCC_PLLMUL_48 RCC_PLL_MUL48
NYX	0:85b3fd62ea1a	2671
NYX	0:85b3fd62ea1a	2672	#define RCC_PLLDIV_2 RCC_PLL_DIV2
NYX	0:85b3fd62ea1a	2673	#define RCC_PLLDIV_3 RCC_PLL_DIV3
NYX	0:85b3fd62ea1a	2674	#define RCC_PLLDIV_4 RCC_PLL_DIV4
NYX	0:85b3fd62ea1a	2675
NYX	0:85b3fd62ea1a	2676	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
NYX	0:85b3fd62ea1a	2677	#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
NYX	0:85b3fd62ea1a	2678	#define RCC_MCO_NODIV RCC_MCODIV_1
NYX	0:85b3fd62ea1a	2679	#define RCC_MCO_DIV1 RCC_MCODIV_1
NYX	0:85b3fd62ea1a	2680	#define RCC_MCO_DIV2 RCC_MCODIV_2
NYX	0:85b3fd62ea1a	2681	#define RCC_MCO_DIV4 RCC_MCODIV_4
NYX	0:85b3fd62ea1a	2682	#define RCC_MCO_DIV8 RCC_MCODIV_8
NYX	0:85b3fd62ea1a	2683	#define RCC_MCO_DIV16 RCC_MCODIV_16
NYX	0:85b3fd62ea1a	2684	#define RCC_MCO_DIV32 RCC_MCODIV_32
NYX	0:85b3fd62ea1a	2685	#define RCC_MCO_DIV64 RCC_MCODIV_64
NYX	0:85b3fd62ea1a	2686	#define RCC_MCO_DIV128 RCC_MCODIV_128
NYX	0:85b3fd62ea1a	2687	#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
NYX	0:85b3fd62ea1a	2688	#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
NYX	0:85b3fd62ea1a	2689	#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
NYX	0:85b3fd62ea1a	2690	#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
NYX	0:85b3fd62ea1a	2691	#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
NYX	0:85b3fd62ea1a	2692	#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
NYX	0:85b3fd62ea1a	2693	#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
NYX	0:85b3fd62ea1a	2694	#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
NYX	0:85b3fd62ea1a	2695	#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
NYX	0:85b3fd62ea1a	2696	#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
NYX	0:85b3fd62ea1a	2697	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
NYX	0:85b3fd62ea1a	2698
NYX	0:85b3fd62ea1a	2699	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
NYX	0:85b3fd62ea1a	2700
NYX	0:85b3fd62ea1a	2701	#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
NYX	0:85b3fd62ea1a	2702	#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
NYX	0:85b3fd62ea1a	2703	#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
NYX	0:85b3fd62ea1a	2704	#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
NYX	0:85b3fd62ea1a	2705	#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
NYX	0:85b3fd62ea1a	2706	#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
NYX	0:85b3fd62ea1a	2707	#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
NYX	0:85b3fd62ea1a	2708	#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
NYX	0:85b3fd62ea1a	2709
NYX	0:85b3fd62ea1a	2710	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
NYX	0:85b3fd62ea1a	2711	#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
NYX	0:85b3fd62ea1a	2712	#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
NYX	0:85b3fd62ea1a	2713	#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
NYX	0:85b3fd62ea1a	2714	#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
NYX	0:85b3fd62ea1a	2715	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
NYX	0:85b3fd62ea1a	2716	#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
NYX	0:85b3fd62ea1a	2717	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
NYX	0:85b3fd62ea1a	2718	#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
NYX	0:85b3fd62ea1a	2719	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
NYX	0:85b3fd62ea1a	2720	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
NYX	0:85b3fd62ea1a	2721	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
NYX	0:85b3fd62ea1a	2722	#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
NYX	0:85b3fd62ea1a	2723	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
NYX	0:85b3fd62ea1a	2724	#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
NYX	0:85b3fd62ea1a	2725	#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
NYX	0:85b3fd62ea1a	2726	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
NYX	0:85b3fd62ea1a	2727	#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
NYX	0:85b3fd62ea1a	2728	#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
NYX	0:85b3fd62ea1a	2729	#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
NYX	0:85b3fd62ea1a	2730	#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
NYX	0:85b3fd62ea1a	2731	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
NYX	0:85b3fd62ea1a	2732	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
NYX	0:85b3fd62ea1a	2733	#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
NYX	0:85b3fd62ea1a	2734	#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
NYX	0:85b3fd62ea1a	2735	#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
NYX	0:85b3fd62ea1a	2736	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
NYX	0:85b3fd62ea1a	2737	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
NYX	0:85b3fd62ea1a	2738	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
NYX	0:85b3fd62ea1a	2739	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
NYX	0:85b3fd62ea1a	2740	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
NYX	0:85b3fd62ea1a	2741	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
NYX	0:85b3fd62ea1a	2742
NYX	0:85b3fd62ea1a	2743	#define CR_HSION_BB RCC_CR_HSION_BB
NYX	0:85b3fd62ea1a	2744	#define CR_CSSON_BB RCC_CR_CSSON_BB
NYX	0:85b3fd62ea1a	2745	#define CR_PLLON_BB RCC_CR_PLLON_BB
NYX	0:85b3fd62ea1a	2746	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
NYX	0:85b3fd62ea1a	2747	#define CR_MSION_BB RCC_CR_MSION_BB
NYX	0:85b3fd62ea1a	2748	#define CSR_LSION_BB RCC_CSR_LSION_BB
NYX	0:85b3fd62ea1a	2749	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
NYX	0:85b3fd62ea1a	2750	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
NYX	0:85b3fd62ea1a	2751	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
NYX	0:85b3fd62ea1a	2752	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
NYX	0:85b3fd62ea1a	2753	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
NYX	0:85b3fd62ea1a	2754	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
NYX	0:85b3fd62ea1a	2755	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
NYX	0:85b3fd62ea1a	2756	#define CR_HSEON_BB RCC_CR_HSEON_BB
NYX	0:85b3fd62ea1a	2757	#define CSR_RMVF_BB RCC_CSR_RMVF_BB
NYX	0:85b3fd62ea1a	2758	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
NYX	0:85b3fd62ea1a	2759	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
NYX	0:85b3fd62ea1a	2760
NYX	0:85b3fd62ea1a	2761	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
NYX	0:85b3fd62ea1a	2762	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
NYX	0:85b3fd62ea1a	2763	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
NYX	0:85b3fd62ea1a	2764	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
NYX	0:85b3fd62ea1a	2765	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
NYX	0:85b3fd62ea1a	2766
NYX	0:85b3fd62ea1a	2767	#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
NYX	0:85b3fd62ea1a	2768
NYX	0:85b3fd62ea1a	2769	#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
NYX	0:85b3fd62ea1a	2770	#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
NYX	0:85b3fd62ea1a	2771
NYX	0:85b3fd62ea1a	2772	#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
NYX	0:85b3fd62ea1a	2773	#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
NYX	0:85b3fd62ea1a	2774	#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
NYX	0:85b3fd62ea1a	2775	#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
NYX	0:85b3fd62ea1a	2776	#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
NYX	0:85b3fd62ea1a	2777	#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
NYX	0:85b3fd62ea1a	2778
NYX	0:85b3fd62ea1a	2779	#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
NYX	0:85b3fd62ea1a	2780	#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
NYX	0:85b3fd62ea1a	2781	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
NYX	0:85b3fd62ea1a	2782	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
NYX	0:85b3fd62ea1a	2783	#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
NYX	0:85b3fd62ea1a	2784	#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
NYX	0:85b3fd62ea1a	2785	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
NYX	0:85b3fd62ea1a	2786	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
NYX	0:85b3fd62ea1a	2787	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
NYX	0:85b3fd62ea1a	2788	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
NYX	0:85b3fd62ea1a	2789	#define DfsdmClockSelection Dfsdm1ClockSelection
NYX	0:85b3fd62ea1a	2790	#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
NYX	0:85b3fd62ea1a	2791	#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
NYX	0:85b3fd62ea1a	2792	#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
NYX	0:85b3fd62ea1a	2793	#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
NYX	0:85b3fd62ea1a	2794	#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
NYX	0:85b3fd62ea1a	2795	#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
NYX	0:85b3fd62ea1a	2796	#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
NYX	0:85b3fd62ea1a	2797	#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
NYX	0:85b3fd62ea1a	2798	#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
NYX	0:85b3fd62ea1a	2799
NYX	0:85b3fd62ea1a	2800	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
NYX	0:85b3fd62ea1a	2801	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
NYX	0:85b3fd62ea1a	2802	#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
NYX	0:85b3fd62ea1a	2803	#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
NYX	0:85b3fd62ea1a	2804	#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
NYX	0:85b3fd62ea1a	2805	#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
NYX	0:85b3fd62ea1a	2806	#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
NYX	0:85b3fd62ea1a	2807
NYX	0:85b3fd62ea1a	2808	/**
NYX	0:85b3fd62ea1a	2809	* @}
NYX	0:85b3fd62ea1a	2810	*/
NYX	0:85b3fd62ea1a	2811
NYX	0:85b3fd62ea1a	2812	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	2813	* @{
NYX	0:85b3fd62ea1a	2814	*/
NYX	0:85b3fd62ea1a	2815	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
NYX	0:85b3fd62ea1a	2816
NYX	0:85b3fd62ea1a	2817	/**
NYX	0:85b3fd62ea1a	2818	* @}
NYX	0:85b3fd62ea1a	2819	*/
NYX	0:85b3fd62ea1a	2820
NYX	0:85b3fd62ea1a	2821	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	2822	* @{
NYX	0:85b3fd62ea1a	2823	*/
NYX	0:85b3fd62ea1a	2824
NYX	0:85b3fd62ea1a	2825	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
NYX	0:85b3fd62ea1a	2826	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
NYX	0:85b3fd62ea1a	2827	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
NYX	0:85b3fd62ea1a	2828
NYX	0:85b3fd62ea1a	2829	#if defined (STM32F1)
NYX	0:85b3fd62ea1a	2830	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
NYX	0:85b3fd62ea1a	2831
NYX	0:85b3fd62ea1a	2832	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
NYX	0:85b3fd62ea1a	2833
NYX	0:85b3fd62ea1a	2834	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
NYX	0:85b3fd62ea1a	2835
NYX	0:85b3fd62ea1a	2836	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
NYX	0:85b3fd62ea1a	2837
NYX	0:85b3fd62ea1a	2838	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
NYX	0:85b3fd62ea1a	2839	#else
NYX	0:85b3fd62ea1a	2840	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	2841	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
NYX	0:85b3fd62ea1a	2842	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
NYX	0:85b3fd62ea1a	2843	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	2844	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
NYX	0:85b3fd62ea1a	2845	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
NYX	0:85b3fd62ea1a	2846	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	2847	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
NYX	0:85b3fd62ea1a	2848	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
NYX	0:85b3fd62ea1a	2849	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	2850	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
NYX	0:85b3fd62ea1a	2851	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
NYX	0:85b3fd62ea1a	2852	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
NYX	0:85b3fd62ea1a	2853	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
NYX	0:85b3fd62ea1a	2854	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
NYX	0:85b3fd62ea1a	2855	#endif /* STM32F1 */
NYX	0:85b3fd62ea1a	2856
NYX	0:85b3fd62ea1a	2857	#define IS_ALARM IS_RTC_ALARM
NYX	0:85b3fd62ea1a	2858	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
NYX	0:85b3fd62ea1a	2859	#define IS_TAMPER IS_RTC_TAMPER
NYX	0:85b3fd62ea1a	2860	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
NYX	0:85b3fd62ea1a	2861	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
NYX	0:85b3fd62ea1a	2862	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
NYX	0:85b3fd62ea1a	2863	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
NYX	0:85b3fd62ea1a	2864	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
NYX	0:85b3fd62ea1a	2865	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
NYX	0:85b3fd62ea1a	2866	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
NYX	0:85b3fd62ea1a	2867	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
NYX	0:85b3fd62ea1a	2868	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
NYX	0:85b3fd62ea1a	2869	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
NYX	0:85b3fd62ea1a	2870	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
NYX	0:85b3fd62ea1a	2871
NYX	0:85b3fd62ea1a	2872	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
NYX	0:85b3fd62ea1a	2873	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
NYX	0:85b3fd62ea1a	2874
NYX	0:85b3fd62ea1a	2875	/**
NYX	0:85b3fd62ea1a	2876	* @}
NYX	0:85b3fd62ea1a	2877	*/
NYX	0:85b3fd62ea1a	2878
NYX	0:85b3fd62ea1a	2879	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	2880	* @{
NYX	0:85b3fd62ea1a	2881	*/
NYX	0:85b3fd62ea1a	2882
NYX	0:85b3fd62ea1a	2883	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
NYX	0:85b3fd62ea1a	2884	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
NYX	0:85b3fd62ea1a	2885
NYX	0:85b3fd62ea1a	2886	#if defined(STM32F4)
NYX	0:85b3fd62ea1a	2887	#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
NYX	0:85b3fd62ea1a	2888	#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
NYX	0:85b3fd62ea1a	2889	#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
NYX	0:85b3fd62ea1a	2890	#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
NYX	0:85b3fd62ea1a	2891	#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
NYX	0:85b3fd62ea1a	2892	#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
NYX	0:85b3fd62ea1a	2893	#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
NYX	0:85b3fd62ea1a	2894	#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
NYX	0:85b3fd62ea1a	2895	#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
NYX	0:85b3fd62ea1a	2896	#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
NYX	0:85b3fd62ea1a	2897	#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
NYX	0:85b3fd62ea1a	2898	#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
NYX	0:85b3fd62ea1a	2899	#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
NYX	0:85b3fd62ea1a	2900	#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
NYX	0:85b3fd62ea1a	2901	#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
NYX	0:85b3fd62ea1a	2902	#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
NYX	0:85b3fd62ea1a	2903	#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
NYX	0:85b3fd62ea1a	2904	#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
NYX	0:85b3fd62ea1a	2905	#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
NYX	0:85b3fd62ea1a	2906	#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
NYX	0:85b3fd62ea1a	2907	/* alias CMSIS */
NYX	0:85b3fd62ea1a	2908	#define SDMMC1_IRQn SDIO_IRQn
NYX	0:85b3fd62ea1a	2909	#define SDMMC1_IRQHandler SDIO_IRQHandler
NYX	0:85b3fd62ea1a	2910	#endif
NYX	0:85b3fd62ea1a	2911
NYX	0:85b3fd62ea1a	2912	#if defined(STM32F7) \|\| defined(STM32L4)
NYX	0:85b3fd62ea1a	2913	#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
NYX	0:85b3fd62ea1a	2914	#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
NYX	0:85b3fd62ea1a	2915	#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
NYX	0:85b3fd62ea1a	2916	#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
NYX	0:85b3fd62ea1a	2917	#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
NYX	0:85b3fd62ea1a	2918	#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
NYX	0:85b3fd62ea1a	2919	#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
NYX	0:85b3fd62ea1a	2920	#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
NYX	0:85b3fd62ea1a	2921	#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
NYX	0:85b3fd62ea1a	2922	#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
NYX	0:85b3fd62ea1a	2923	#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
NYX	0:85b3fd62ea1a	2924	#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
NYX	0:85b3fd62ea1a	2925	#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
NYX	0:85b3fd62ea1a	2926	#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
NYX	0:85b3fd62ea1a	2927	#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
NYX	0:85b3fd62ea1a	2928	#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
NYX	0:85b3fd62ea1a	2929	#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
NYX	0:85b3fd62ea1a	2930	#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
NYX	0:85b3fd62ea1a	2931	#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
NYX	0:85b3fd62ea1a	2932	#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
NYX	0:85b3fd62ea1a	2933	/* alias CMSIS for compatibilities */
NYX	0:85b3fd62ea1a	2934	#define SDIO_IRQn SDMMC1_IRQn
NYX	0:85b3fd62ea1a	2935	#define SDIO_IRQHandler SDMMC1_IRQHandler
NYX	0:85b3fd62ea1a	2936	#endif
NYX	0:85b3fd62ea1a	2937
NYX	0:85b3fd62ea1a	2938	#if defined(STM32F7) \|\| defined(STM32F4) \|\| defined(STM32F2)
NYX	0:85b3fd62ea1a	2939	#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
NYX	0:85b3fd62ea1a	2940	#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
NYX	0:85b3fd62ea1a	2941	#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
NYX	0:85b3fd62ea1a	2942	#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
NYX	0:85b3fd62ea1a	2943	#endif
NYX	0:85b3fd62ea1a	2944
NYX	0:85b3fd62ea1a	2945	/**
NYX	0:85b3fd62ea1a	2946	* @}
NYX	0:85b3fd62ea1a	2947	*/
NYX	0:85b3fd62ea1a	2948
NYX	0:85b3fd62ea1a	2949	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	2950	* @{
NYX	0:85b3fd62ea1a	2951	*/
NYX	0:85b3fd62ea1a	2952
NYX	0:85b3fd62ea1a	2953	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
NYX	0:85b3fd62ea1a	2954	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
NYX	0:85b3fd62ea1a	2955	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
NYX	0:85b3fd62ea1a	2956	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
NYX	0:85b3fd62ea1a	2957	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
NYX	0:85b3fd62ea1a	2958	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
NYX	0:85b3fd62ea1a	2959
NYX	0:85b3fd62ea1a	2960	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
NYX	0:85b3fd62ea1a	2961	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
NYX	0:85b3fd62ea1a	2962
NYX	0:85b3fd62ea1a	2963	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
NYX	0:85b3fd62ea1a	2964
NYX	0:85b3fd62ea1a	2965	/**
NYX	0:85b3fd62ea1a	2966	* @}
NYX	0:85b3fd62ea1a	2967	*/
NYX	0:85b3fd62ea1a	2968
NYX	0:85b3fd62ea1a	2969	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	2970	* @{
NYX	0:85b3fd62ea1a	2971	*/
NYX	0:85b3fd62ea1a	2972	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
NYX	0:85b3fd62ea1a	2973	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
NYX	0:85b3fd62ea1a	2974	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
NYX	0:85b3fd62ea1a	2975	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
NYX	0:85b3fd62ea1a	2976	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
NYX	0:85b3fd62ea1a	2977	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
NYX	0:85b3fd62ea1a	2978	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
NYX	0:85b3fd62ea1a	2979	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
NYX	0:85b3fd62ea1a	2980	/**
NYX	0:85b3fd62ea1a	2981	* @}
NYX	0:85b3fd62ea1a	2982	*/
NYX	0:85b3fd62ea1a	2983
NYX	0:85b3fd62ea1a	2984	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	2985	* @{
NYX	0:85b3fd62ea1a	2986	*/
NYX	0:85b3fd62ea1a	2987
NYX	0:85b3fd62ea1a	2988	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
NYX	0:85b3fd62ea1a	2989	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
NYX	0:85b3fd62ea1a	2990	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
NYX	0:85b3fd62ea1a	2991
NYX	0:85b3fd62ea1a	2992	/**
NYX	0:85b3fd62ea1a	2993	* @}
NYX	0:85b3fd62ea1a	2994	*/
NYX	0:85b3fd62ea1a	2995
NYX	0:85b3fd62ea1a	2996	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	2997	* @{
NYX	0:85b3fd62ea1a	2998	*/
NYX	0:85b3fd62ea1a	2999
NYX	0:85b3fd62ea1a	3000	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
NYX	0:85b3fd62ea1a	3001	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
NYX	0:85b3fd62ea1a	3002	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
NYX	0:85b3fd62ea1a	3003	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
NYX	0:85b3fd62ea1a	3004
NYX	0:85b3fd62ea1a	3005	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
NYX	0:85b3fd62ea1a	3006
NYX	0:85b3fd62ea1a	3007	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
NYX	0:85b3fd62ea1a	3008	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
NYX	0:85b3fd62ea1a	3009
NYX	0:85b3fd62ea1a	3010	/**
NYX	0:85b3fd62ea1a	3011	* @}
NYX	0:85b3fd62ea1a	3012	*/
NYX	0:85b3fd62ea1a	3013
NYX	0:85b3fd62ea1a	3014
NYX	0:85b3fd62ea1a	3015	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	3016	* @{
NYX	0:85b3fd62ea1a	3017	*/
NYX	0:85b3fd62ea1a	3018
NYX	0:85b3fd62ea1a	3019	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
NYX	0:85b3fd62ea1a	3020	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
NYX	0:85b3fd62ea1a	3021	#define __USART_ENABLE __HAL_USART_ENABLE
NYX	0:85b3fd62ea1a	3022	#define __USART_DISABLE __HAL_USART_DISABLE
NYX	0:85b3fd62ea1a	3023
NYX	0:85b3fd62ea1a	3024	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
NYX	0:85b3fd62ea1a	3025	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
NYX	0:85b3fd62ea1a	3026
NYX	0:85b3fd62ea1a	3027	/**
NYX	0:85b3fd62ea1a	3028	* @}
NYX	0:85b3fd62ea1a	3029	*/
NYX	0:85b3fd62ea1a	3030
NYX	0:85b3fd62ea1a	3031	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	3032	* @{
NYX	0:85b3fd62ea1a	3033	*/
NYX	0:85b3fd62ea1a	3034	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
NYX	0:85b3fd62ea1a	3035
NYX	0:85b3fd62ea1a	3036	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
NYX	0:85b3fd62ea1a	3037	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
NYX	0:85b3fd62ea1a	3038	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
NYX	0:85b3fd62ea1a	3039	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
NYX	0:85b3fd62ea1a	3040
NYX	0:85b3fd62ea1a	3041	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
NYX	0:85b3fd62ea1a	3042	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
NYX	0:85b3fd62ea1a	3043	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
NYX	0:85b3fd62ea1a	3044	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
NYX	0:85b3fd62ea1a	3045
NYX	0:85b3fd62ea1a	3046	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
NYX	0:85b3fd62ea1a	3047	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
NYX	0:85b3fd62ea1a	3048	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
NYX	0:85b3fd62ea1a	3049	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
NYX	0:85b3fd62ea1a	3050	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
NYX	0:85b3fd62ea1a	3051	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	3052	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
NYX	0:85b3fd62ea1a	3053
NYX	0:85b3fd62ea1a	3054	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
NYX	0:85b3fd62ea1a	3055	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
NYX	0:85b3fd62ea1a	3056	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
NYX	0:85b3fd62ea1a	3057	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
NYX	0:85b3fd62ea1a	3058	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
NYX	0:85b3fd62ea1a	3059	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	3060	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
NYX	0:85b3fd62ea1a	3061	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
NYX	0:85b3fd62ea1a	3062
NYX	0:85b3fd62ea1a	3063	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
NYX	0:85b3fd62ea1a	3064	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
NYX	0:85b3fd62ea1a	3065	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
NYX	0:85b3fd62ea1a	3066	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
NYX	0:85b3fd62ea1a	3067	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
NYX	0:85b3fd62ea1a	3068	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
NYX	0:85b3fd62ea1a	3069	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
NYX	0:85b3fd62ea1a	3070	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
NYX	0:85b3fd62ea1a	3071
NYX	0:85b3fd62ea1a	3072	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
NYX	0:85b3fd62ea1a	3073	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
NYX	0:85b3fd62ea1a	3074
NYX	0:85b3fd62ea1a	3075	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
NYX	0:85b3fd62ea1a	3076	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
NYX	0:85b3fd62ea1a	3077	/**
NYX	0:85b3fd62ea1a	3078	* @}
NYX	0:85b3fd62ea1a	3079	*/
NYX	0:85b3fd62ea1a	3080
NYX	0:85b3fd62ea1a	3081	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	3082	* @{
NYX	0:85b3fd62ea1a	3083	*/
NYX	0:85b3fd62ea1a	3084	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
NYX	0:85b3fd62ea1a	3085	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
NYX	0:85b3fd62ea1a	3086
NYX	0:85b3fd62ea1a	3087	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
NYX	0:85b3fd62ea1a	3088	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
NYX	0:85b3fd62ea1a	3089
NYX	0:85b3fd62ea1a	3090	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
NYX	0:85b3fd62ea1a	3091
NYX	0:85b3fd62ea1a	3092	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
NYX	0:85b3fd62ea1a	3093	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
NYX	0:85b3fd62ea1a	3094	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
NYX	0:85b3fd62ea1a	3095	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
NYX	0:85b3fd62ea1a	3096	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
NYX	0:85b3fd62ea1a	3097	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
NYX	0:85b3fd62ea1a	3098	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
NYX	0:85b3fd62ea1a	3099	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
NYX	0:85b3fd62ea1a	3100	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
NYX	0:85b3fd62ea1a	3101	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
NYX	0:85b3fd62ea1a	3102	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
NYX	0:85b3fd62ea1a	3103	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
NYX	0:85b3fd62ea1a	3104
NYX	0:85b3fd62ea1a	3105	#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
NYX	0:85b3fd62ea1a	3106	/**
NYX	0:85b3fd62ea1a	3107	* @}
NYX	0:85b3fd62ea1a	3108	*/
NYX	0:85b3fd62ea1a	3109
NYX	0:85b3fd62ea1a	3110	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	3111	* @{
NYX	0:85b3fd62ea1a	3112	*/
NYX	0:85b3fd62ea1a	3113
NYX	0:85b3fd62ea1a	3114	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
NYX	0:85b3fd62ea1a	3115	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
NYX	0:85b3fd62ea1a	3116	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
NYX	0:85b3fd62ea1a	3117	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
NYX	0:85b3fd62ea1a	3118	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
NYX	0:85b3fd62ea1a	3119	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
NYX	0:85b3fd62ea1a	3120	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
NYX	0:85b3fd62ea1a	3121
NYX	0:85b3fd62ea1a	3122	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
NYX	0:85b3fd62ea1a	3123	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
NYX	0:85b3fd62ea1a	3124	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
NYX	0:85b3fd62ea1a	3125	/**
NYX	0:85b3fd62ea1a	3126	* @}
NYX	0:85b3fd62ea1a	3127	*/
NYX	0:85b3fd62ea1a	3128
NYX	0:85b3fd62ea1a	3129	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	3130	* @{
NYX	0:85b3fd62ea1a	3131	*/
NYX	0:85b3fd62ea1a	3132	#define __HAL_LTDC_LAYER LTDC_LAYER
NYX	0:85b3fd62ea1a	3133	#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
NYX	0:85b3fd62ea1a	3134	/**
NYX	0:85b3fd62ea1a	3135	* @}
NYX	0:85b3fd62ea1a	3136	*/
NYX	0:85b3fd62ea1a	3137
NYX	0:85b3fd62ea1a	3138	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	3139	* @{
NYX	0:85b3fd62ea1a	3140	*/
NYX	0:85b3fd62ea1a	3141	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
NYX	0:85b3fd62ea1a	3142	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
NYX	0:85b3fd62ea1a	3143	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
NYX	0:85b3fd62ea1a	3144	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
NYX	0:85b3fd62ea1a	3145	#define SAI_STREOMODE SAI_STEREOMODE
NYX	0:85b3fd62ea1a	3146	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
NYX	0:85b3fd62ea1a	3147	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
NYX	0:85b3fd62ea1a	3148	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
NYX	0:85b3fd62ea1a	3149	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
NYX	0:85b3fd62ea1a	3150	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
NYX	0:85b3fd62ea1a	3151	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
NYX	0:85b3fd62ea1a	3152	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
NYX	0:85b3fd62ea1a	3153	#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
NYX	0:85b3fd62ea1a	3154	#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
NYX	0:85b3fd62ea1a	3155	/**
NYX	0:85b3fd62ea1a	3156	* @}
NYX	0:85b3fd62ea1a	3157	*/
NYX	0:85b3fd62ea1a	3158
NYX	0:85b3fd62ea1a	3159
NYX	0:85b3fd62ea1a	3160	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
NYX	0:85b3fd62ea1a	3161	* @{
NYX	0:85b3fd62ea1a	3162	*/
NYX	0:85b3fd62ea1a	3163
NYX	0:85b3fd62ea1a	3164	/**
NYX	0:85b3fd62ea1a	3165	* @}
NYX	0:85b3fd62ea1a	3166	*/
NYX	0:85b3fd62ea1a	3167
NYX	0:85b3fd62ea1a	3168	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	3169	}
NYX	0:85b3fd62ea1a	3170	#endif
NYX	0:85b3fd62ea1a	3171
NYX	0:85b3fd62ea1a	3172	#endif /* ___STM32_HAL_LEGACY */
NYX	0:85b3fd62ea1a	3173
NYX	0:85b3fd62ea1a	3174	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
NYX	0:85b3fd62ea1a	3175

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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