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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f446xx.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

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NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f446xx.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V2.6.1
NYX 0:85b3fd62ea1a 6 * @date 14-February-2017
NYX 0:85b3fd62ea1a 7 * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File.
NYX 0:85b3fd62ea1a 8 *
NYX 0:85b3fd62ea1a 9 * This file contains:
NYX 0:85b3fd62ea1a 10 * - Data structures and the address mapping for all peripherals
NYX 0:85b3fd62ea1a 11 * - peripherals registers declarations and bits definition
NYX 0:85b3fd62ea1a 12 * - Macros to access peripheral's registers hardware
NYX 0:85b3fd62ea1a 13 *
NYX 0:85b3fd62ea1a 14 ******************************************************************************
NYX 0:85b3fd62ea1a 15 * @attention
NYX 0:85b3fd62ea1a 16 *
NYX 0:85b3fd62ea1a 17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 18 *
NYX 0:85b3fd62ea1a 19 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 20 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 21 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 22 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 24 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 25 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 27 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 28 * without specific prior written permission.
NYX 0:85b3fd62ea1a 29 *
NYX 0:85b3fd62ea1a 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 40 *
NYX 0:85b3fd62ea1a 41 ******************************************************************************
NYX 0:85b3fd62ea1a 42 */
NYX 0:85b3fd62ea1a 43
NYX 0:85b3fd62ea1a 44 /** @addtogroup CMSIS_Device
NYX 0:85b3fd62ea1a 45 * @{
NYX 0:85b3fd62ea1a 46 */
NYX 0:85b3fd62ea1a 47
NYX 0:85b3fd62ea1a 48 /** @addtogroup stm32f446xx
NYX 0:85b3fd62ea1a 49 * @{
NYX 0:85b3fd62ea1a 50 */
NYX 0:85b3fd62ea1a 51
NYX 0:85b3fd62ea1a 52 #ifndef __STM32F446xx_H
NYX 0:85b3fd62ea1a 53 #define __STM32F446xx_H
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 56 extern "C" {
NYX 0:85b3fd62ea1a 57 #endif /* __cplusplus */
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 /** @addtogroup Configuration_section_for_CMSIS
NYX 0:85b3fd62ea1a 60 * @{
NYX 0:85b3fd62ea1a 61 */
NYX 0:85b3fd62ea1a 62
NYX 0:85b3fd62ea1a 63 /**
NYX 0:85b3fd62ea1a 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
NYX 0:85b3fd62ea1a 65 */
NYX 0:85b3fd62ea1a 66 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
NYX 0:85b3fd62ea1a 67 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
NYX 0:85b3fd62ea1a 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
NYX 0:85b3fd62ea1a 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
NYX 0:85b3fd62ea1a 70 #ifndef __FPU_PRESENT
NYX 0:85b3fd62ea1a 71 #define __FPU_PRESENT 1U /*!< FPU present */
NYX 0:85b3fd62ea1a 72 #endif /* __FPU_PRESENT */
NYX 0:85b3fd62ea1a 73
NYX 0:85b3fd62ea1a 74 /**
NYX 0:85b3fd62ea1a 75 * @}
NYX 0:85b3fd62ea1a 76 */
NYX 0:85b3fd62ea1a 77
NYX 0:85b3fd62ea1a 78 /** @addtogroup Peripheral_interrupt_number_definition
NYX 0:85b3fd62ea1a 79 * @{
NYX 0:85b3fd62ea1a 80 */
NYX 0:85b3fd62ea1a 81
NYX 0:85b3fd62ea1a 82 /**
NYX 0:85b3fd62ea1a 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
NYX 0:85b3fd62ea1a 84 * in @ref Library_configuration_section
NYX 0:85b3fd62ea1a 85 */
NYX 0:85b3fd62ea1a 86 typedef enum
NYX 0:85b3fd62ea1a 87 {
NYX 0:85b3fd62ea1a 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NYX 0:85b3fd62ea1a 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
NYX 0:85b3fd62ea1a 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
NYX 0:85b3fd62ea1a 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
NYX 0:85b3fd62ea1a 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
NYX 0:85b3fd62ea1a 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
NYX 0:85b3fd62ea1a 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
NYX 0:85b3fd62ea1a 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
NYX 0:85b3fd62ea1a 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
NYX 0:85b3fd62ea1a 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
NYX 0:85b3fd62ea1a 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
NYX 0:85b3fd62ea1a 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
NYX 0:85b3fd62ea1a 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
NYX 0:85b3fd62ea1a 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
NYX 0:85b3fd62ea1a 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
NYX 0:85b3fd62ea1a 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
NYX 0:85b3fd62ea1a 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
NYX 0:85b3fd62ea1a 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
NYX 0:85b3fd62ea1a 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
NYX 0:85b3fd62ea1a 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
NYX 0:85b3fd62ea1a 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
NYX 0:85b3fd62ea1a 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
NYX 0:85b3fd62ea1a 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
NYX 0:85b3fd62ea1a 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
NYX 0:85b3fd62ea1a 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
NYX 0:85b3fd62ea1a 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
NYX 0:85b3fd62ea1a 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
NYX 0:85b3fd62ea1a 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
NYX 0:85b3fd62ea1a 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
NYX 0:85b3fd62ea1a 117 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
NYX 0:85b3fd62ea1a 118 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
NYX 0:85b3fd62ea1a 119 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
NYX 0:85b3fd62ea1a 120 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
NYX 0:85b3fd62ea1a 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
NYX 0:85b3fd62ea1a 122 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
NYX 0:85b3fd62ea1a 123 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
NYX 0:85b3fd62ea1a 124 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
NYX 0:85b3fd62ea1a 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
NYX 0:85b3fd62ea1a 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
NYX 0:85b3fd62ea1a 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
NYX 0:85b3fd62ea1a 128 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
NYX 0:85b3fd62ea1a 129 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
NYX 0:85b3fd62ea1a 130 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
NYX 0:85b3fd62ea1a 131 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
NYX 0:85b3fd62ea1a 132 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
NYX 0:85b3fd62ea1a 133 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
NYX 0:85b3fd62ea1a 134 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
NYX 0:85b3fd62ea1a 135 USART1_IRQn = 37, /*!< USART1 global Interrupt */
NYX 0:85b3fd62ea1a 136 USART2_IRQn = 38, /*!< USART2 global Interrupt */
NYX 0:85b3fd62ea1a 137 USART3_IRQn = 39, /*!< USART3 global Interrupt */
NYX 0:85b3fd62ea1a 138 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
NYX 0:85b3fd62ea1a 139 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
NYX 0:85b3fd62ea1a 140 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
NYX 0:85b3fd62ea1a 141 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
NYX 0:85b3fd62ea1a 142 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
NYX 0:85b3fd62ea1a 143 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
NYX 0:85b3fd62ea1a 144 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
NYX 0:85b3fd62ea1a 145 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
NYX 0:85b3fd62ea1a 146 FMC_IRQn = 48, /*!< FMC global Interrupt */
NYX 0:85b3fd62ea1a 147 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
NYX 0:85b3fd62ea1a 148 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
NYX 0:85b3fd62ea1a 149 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
NYX 0:85b3fd62ea1a 150 UART4_IRQn = 52, /*!< UART4 global Interrupt */
NYX 0:85b3fd62ea1a 151 UART5_IRQn = 53, /*!< UART5 global Interrupt */
NYX 0:85b3fd62ea1a 152 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
NYX 0:85b3fd62ea1a 153 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
NYX 0:85b3fd62ea1a 154 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
NYX 0:85b3fd62ea1a 155 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
NYX 0:85b3fd62ea1a 156 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
NYX 0:85b3fd62ea1a 157 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
NYX 0:85b3fd62ea1a 158 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
NYX 0:85b3fd62ea1a 159 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
NYX 0:85b3fd62ea1a 160 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
NYX 0:85b3fd62ea1a 161 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
NYX 0:85b3fd62ea1a 162 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
NYX 0:85b3fd62ea1a 163 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
NYX 0:85b3fd62ea1a 164 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
NYX 0:85b3fd62ea1a 165 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
NYX 0:85b3fd62ea1a 166 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
NYX 0:85b3fd62ea1a 167 USART6_IRQn = 71, /*!< USART6 global interrupt */
NYX 0:85b3fd62ea1a 168 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
NYX 0:85b3fd62ea1a 169 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
NYX 0:85b3fd62ea1a 170 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
NYX 0:85b3fd62ea1a 171 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
NYX 0:85b3fd62ea1a 172 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
NYX 0:85b3fd62ea1a 173 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
NYX 0:85b3fd62ea1a 174 DCMI_IRQn = 78, /*!< DCMI global interrupt */
NYX 0:85b3fd62ea1a 175 FPU_IRQn = 81, /*!< FPU global interrupt */
NYX 0:85b3fd62ea1a 176 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
NYX 0:85b3fd62ea1a 177 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
NYX 0:85b3fd62ea1a 178 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
NYX 0:85b3fd62ea1a 179 QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
NYX 0:85b3fd62ea1a 180 CEC_IRQn = 93, /*!< CEC global Interrupt */
NYX 0:85b3fd62ea1a 181 SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */
NYX 0:85b3fd62ea1a 182 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
NYX 0:85b3fd62ea1a 183 FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
NYX 0:85b3fd62ea1a 184 } IRQn_Type;
NYX 0:85b3fd62ea1a 185
NYX 0:85b3fd62ea1a 186 /**
NYX 0:85b3fd62ea1a 187 * @}
NYX 0:85b3fd62ea1a 188 */
NYX 0:85b3fd62ea1a 189
NYX 0:85b3fd62ea1a 190 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
NYX 0:85b3fd62ea1a 191 #include "system_stm32f4xx.h"
NYX 0:85b3fd62ea1a 192 #include <stdint.h>
NYX 0:85b3fd62ea1a 193
NYX 0:85b3fd62ea1a 194 /** @addtogroup Peripheral_registers_structures
NYX 0:85b3fd62ea1a 195 * @{
NYX 0:85b3fd62ea1a 196 */
NYX 0:85b3fd62ea1a 197
NYX 0:85b3fd62ea1a 198 /**
NYX 0:85b3fd62ea1a 199 * @brief Analog to Digital Converter
NYX 0:85b3fd62ea1a 200 */
NYX 0:85b3fd62ea1a 201
NYX 0:85b3fd62ea1a 202 typedef struct
NYX 0:85b3fd62ea1a 203 {
NYX 0:85b3fd62ea1a 204 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 205 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 206 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 207 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 208 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 209 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 210 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 211 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 212 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 213 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 214 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
NYX 0:85b3fd62ea1a 215 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
NYX 0:85b3fd62ea1a 216 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
NYX 0:85b3fd62ea1a 217 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
NYX 0:85b3fd62ea1a 218 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
NYX 0:85b3fd62ea1a 219 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
NYX 0:85b3fd62ea1a 220 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
NYX 0:85b3fd62ea1a 221 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
NYX 0:85b3fd62ea1a 222 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
NYX 0:85b3fd62ea1a 223 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
NYX 0:85b3fd62ea1a 224 } ADC_TypeDef;
NYX 0:85b3fd62ea1a 225
NYX 0:85b3fd62ea1a 226 typedef struct
NYX 0:85b3fd62ea1a 227 {
NYX 0:85b3fd62ea1a 228 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
NYX 0:85b3fd62ea1a 229 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
NYX 0:85b3fd62ea1a 230 __IO uint32_t CDR; /*!< ADC common regular data register for dual
NYX 0:85b3fd62ea1a 231 AND triple modes, Address offset: ADC1 base address + 0x308 */
NYX 0:85b3fd62ea1a 232 } ADC_Common_TypeDef;
NYX 0:85b3fd62ea1a 233
NYX 0:85b3fd62ea1a 234
NYX 0:85b3fd62ea1a 235 /**
NYX 0:85b3fd62ea1a 236 * @brief Controller Area Network TxMailBox
NYX 0:85b3fd62ea1a 237 */
NYX 0:85b3fd62ea1a 238
NYX 0:85b3fd62ea1a 239 typedef struct
NYX 0:85b3fd62ea1a 240 {
NYX 0:85b3fd62ea1a 241 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
NYX 0:85b3fd62ea1a 242 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
NYX 0:85b3fd62ea1a 243 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
NYX 0:85b3fd62ea1a 244 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
NYX 0:85b3fd62ea1a 245 } CAN_TxMailBox_TypeDef;
NYX 0:85b3fd62ea1a 246
NYX 0:85b3fd62ea1a 247 /**
NYX 0:85b3fd62ea1a 248 * @brief Controller Area Network FIFOMailBox
NYX 0:85b3fd62ea1a 249 */
NYX 0:85b3fd62ea1a 250
NYX 0:85b3fd62ea1a 251 typedef struct
NYX 0:85b3fd62ea1a 252 {
NYX 0:85b3fd62ea1a 253 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
NYX 0:85b3fd62ea1a 254 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
NYX 0:85b3fd62ea1a 255 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
NYX 0:85b3fd62ea1a 256 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
NYX 0:85b3fd62ea1a 257 } CAN_FIFOMailBox_TypeDef;
NYX 0:85b3fd62ea1a 258
NYX 0:85b3fd62ea1a 259 /**
NYX 0:85b3fd62ea1a 260 * @brief Controller Area Network FilterRegister
NYX 0:85b3fd62ea1a 261 */
NYX 0:85b3fd62ea1a 262
NYX 0:85b3fd62ea1a 263 typedef struct
NYX 0:85b3fd62ea1a 264 {
NYX 0:85b3fd62ea1a 265 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
NYX 0:85b3fd62ea1a 266 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
NYX 0:85b3fd62ea1a 267 } CAN_FilterRegister_TypeDef;
NYX 0:85b3fd62ea1a 268
NYX 0:85b3fd62ea1a 269 /**
NYX 0:85b3fd62ea1a 270 * @brief Controller Area Network
NYX 0:85b3fd62ea1a 271 */
NYX 0:85b3fd62ea1a 272
NYX 0:85b3fd62ea1a 273 typedef struct
NYX 0:85b3fd62ea1a 274 {
NYX 0:85b3fd62ea1a 275 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 276 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 277 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 278 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 279 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 280 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 281 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 282 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 283 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
NYX 0:85b3fd62ea1a 284 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
NYX 0:85b3fd62ea1a 285 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
NYX 0:85b3fd62ea1a 286 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
NYX 0:85b3fd62ea1a 287 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
NYX 0:85b3fd62ea1a 288 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
NYX 0:85b3fd62ea1a 289 uint32_t RESERVED2; /*!< Reserved, 0x208 */
NYX 0:85b3fd62ea1a 290 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
NYX 0:85b3fd62ea1a 291 uint32_t RESERVED3; /*!< Reserved, 0x210 */
NYX 0:85b3fd62ea1a 292 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
NYX 0:85b3fd62ea1a 293 uint32_t RESERVED4; /*!< Reserved, 0x218 */
NYX 0:85b3fd62ea1a 294 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
NYX 0:85b3fd62ea1a 295 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
NYX 0:85b3fd62ea1a 296 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
NYX 0:85b3fd62ea1a 297 } CAN_TypeDef;
NYX 0:85b3fd62ea1a 298
NYX 0:85b3fd62ea1a 299
NYX 0:85b3fd62ea1a 300 /**
NYX 0:85b3fd62ea1a 301 * @brief Consumer Electronics Control
NYX 0:85b3fd62ea1a 302 */
NYX 0:85b3fd62ea1a 303
NYX 0:85b3fd62ea1a 304 typedef struct
NYX 0:85b3fd62ea1a 305 {
NYX 0:85b3fd62ea1a 306 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
NYX 0:85b3fd62ea1a 307 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
NYX 0:85b3fd62ea1a 308 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
NYX 0:85b3fd62ea1a 309 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
NYX 0:85b3fd62ea1a 310 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
NYX 0:85b3fd62ea1a 311 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
NYX 0:85b3fd62ea1a 312 }CEC_TypeDef;
NYX 0:85b3fd62ea1a 313 /**
NYX 0:85b3fd62ea1a 314 * @brief CRC calculation unit
NYX 0:85b3fd62ea1a 315 */
NYX 0:85b3fd62ea1a 316
NYX 0:85b3fd62ea1a 317 typedef struct
NYX 0:85b3fd62ea1a 318 {
NYX 0:85b3fd62ea1a 319 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 320 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 321 uint8_t RESERVED0; /*!< Reserved, 0x05 */
NYX 0:85b3fd62ea1a 322 uint16_t RESERVED1; /*!< Reserved, 0x06 */
NYX 0:85b3fd62ea1a 323 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 324 } CRC_TypeDef;
NYX 0:85b3fd62ea1a 325
NYX 0:85b3fd62ea1a 326 /**
NYX 0:85b3fd62ea1a 327 * @brief Digital to Analog Converter
NYX 0:85b3fd62ea1a 328 */
NYX 0:85b3fd62ea1a 329
NYX 0:85b3fd62ea1a 330 typedef struct
NYX 0:85b3fd62ea1a 331 {
NYX 0:85b3fd62ea1a 332 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 333 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 334 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 335 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 336 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 337 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 338 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 339 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 340 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 341 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 342 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
NYX 0:85b3fd62ea1a 343 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
NYX 0:85b3fd62ea1a 344 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
NYX 0:85b3fd62ea1a 345 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
NYX 0:85b3fd62ea1a 346 } DAC_TypeDef;
NYX 0:85b3fd62ea1a 347
NYX 0:85b3fd62ea1a 348 /**
NYX 0:85b3fd62ea1a 349 * @brief Debug MCU
NYX 0:85b3fd62ea1a 350 */
NYX 0:85b3fd62ea1a 351
NYX 0:85b3fd62ea1a 352 typedef struct
NYX 0:85b3fd62ea1a 353 {
NYX 0:85b3fd62ea1a 354 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 355 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 356 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 357 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 358 }DBGMCU_TypeDef;
NYX 0:85b3fd62ea1a 359
NYX 0:85b3fd62ea1a 360 /**
NYX 0:85b3fd62ea1a 361 * @brief DCMI
NYX 0:85b3fd62ea1a 362 */
NYX 0:85b3fd62ea1a 363
NYX 0:85b3fd62ea1a 364 typedef struct
NYX 0:85b3fd62ea1a 365 {
NYX 0:85b3fd62ea1a 366 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 367 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 368 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 369 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 370 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 371 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 372 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 373 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 374 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 375 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 376 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
NYX 0:85b3fd62ea1a 377 } DCMI_TypeDef;
NYX 0:85b3fd62ea1a 378
NYX 0:85b3fd62ea1a 379 /**
NYX 0:85b3fd62ea1a 380 * @brief DMA Controller
NYX 0:85b3fd62ea1a 381 */
NYX 0:85b3fd62ea1a 382
NYX 0:85b3fd62ea1a 383 typedef struct
NYX 0:85b3fd62ea1a 384 {
NYX 0:85b3fd62ea1a 385 __IO uint32_t CR; /*!< DMA stream x configuration register */
NYX 0:85b3fd62ea1a 386 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
NYX 0:85b3fd62ea1a 387 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
NYX 0:85b3fd62ea1a 388 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
NYX 0:85b3fd62ea1a 389 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
NYX 0:85b3fd62ea1a 390 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
NYX 0:85b3fd62ea1a 391 } DMA_Stream_TypeDef;
NYX 0:85b3fd62ea1a 392
NYX 0:85b3fd62ea1a 393 typedef struct
NYX 0:85b3fd62ea1a 394 {
NYX 0:85b3fd62ea1a 395 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 396 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 397 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 398 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 399 } DMA_TypeDef;
NYX 0:85b3fd62ea1a 400
NYX 0:85b3fd62ea1a 401 /**
NYX 0:85b3fd62ea1a 402 * @brief External Interrupt/Event Controller
NYX 0:85b3fd62ea1a 403 */
NYX 0:85b3fd62ea1a 404
NYX 0:85b3fd62ea1a 405 typedef struct
NYX 0:85b3fd62ea1a 406 {
NYX 0:85b3fd62ea1a 407 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 408 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 409 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 410 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 411 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 412 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 413 } EXTI_TypeDef;
NYX 0:85b3fd62ea1a 414
NYX 0:85b3fd62ea1a 415 /**
NYX 0:85b3fd62ea1a 416 * @brief FLASH Registers
NYX 0:85b3fd62ea1a 417 */
NYX 0:85b3fd62ea1a 418
NYX 0:85b3fd62ea1a 419 typedef struct
NYX 0:85b3fd62ea1a 420 {
NYX 0:85b3fd62ea1a 421 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 422 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 423 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 424 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 425 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 426 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
NYX 0:85b3fd62ea1a 427 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 428 } FLASH_TypeDef;
NYX 0:85b3fd62ea1a 429
NYX 0:85b3fd62ea1a 430 /**
NYX 0:85b3fd62ea1a 431 * @brief Flexible Memory Controller
NYX 0:85b3fd62ea1a 432 */
NYX 0:85b3fd62ea1a 433
NYX 0:85b3fd62ea1a 434 typedef struct
NYX 0:85b3fd62ea1a 435 {
NYX 0:85b3fd62ea1a 436 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
NYX 0:85b3fd62ea1a 437 } FMC_Bank1_TypeDef;
NYX 0:85b3fd62ea1a 438
NYX 0:85b3fd62ea1a 439 /**
NYX 0:85b3fd62ea1a 440 * @brief Flexible Memory Controller Bank1E
NYX 0:85b3fd62ea1a 441 */
NYX 0:85b3fd62ea1a 442
NYX 0:85b3fd62ea1a 443 typedef struct
NYX 0:85b3fd62ea1a 444 {
NYX 0:85b3fd62ea1a 445 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
NYX 0:85b3fd62ea1a 446 } FMC_Bank1E_TypeDef;
NYX 0:85b3fd62ea1a 447
NYX 0:85b3fd62ea1a 448 /**
NYX 0:85b3fd62ea1a 449 * @brief Flexible Memory Controller Bank3
NYX 0:85b3fd62ea1a 450 */
NYX 0:85b3fd62ea1a 451
NYX 0:85b3fd62ea1a 452 typedef struct
NYX 0:85b3fd62ea1a 453 {
NYX 0:85b3fd62ea1a 454 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
NYX 0:85b3fd62ea1a 455 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
NYX 0:85b3fd62ea1a 456 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
NYX 0:85b3fd62ea1a 457 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
NYX 0:85b3fd62ea1a 458 uint32_t RESERVED; /*!< Reserved, 0x90 */
NYX 0:85b3fd62ea1a 459 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
NYX 0:85b3fd62ea1a 460 } FMC_Bank3_TypeDef;
NYX 0:85b3fd62ea1a 461
NYX 0:85b3fd62ea1a 462 /**
NYX 0:85b3fd62ea1a 463 * @brief Flexible Memory Controller Bank5_6
NYX 0:85b3fd62ea1a 464 */
NYX 0:85b3fd62ea1a 465
NYX 0:85b3fd62ea1a 466 typedef struct
NYX 0:85b3fd62ea1a 467 {
NYX 0:85b3fd62ea1a 468 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
NYX 0:85b3fd62ea1a 469 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
NYX 0:85b3fd62ea1a 470 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
NYX 0:85b3fd62ea1a 471 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
NYX 0:85b3fd62ea1a 472 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
NYX 0:85b3fd62ea1a 473 } FMC_Bank5_6_TypeDef;
NYX 0:85b3fd62ea1a 474
NYX 0:85b3fd62ea1a 475 /**
NYX 0:85b3fd62ea1a 476 * @brief General Purpose I/O
NYX 0:85b3fd62ea1a 477 */
NYX 0:85b3fd62ea1a 478
NYX 0:85b3fd62ea1a 479 typedef struct
NYX 0:85b3fd62ea1a 480 {
NYX 0:85b3fd62ea1a 481 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 482 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 483 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 484 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 485 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 486 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 487 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 488 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 489 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
NYX 0:85b3fd62ea1a 490 } GPIO_TypeDef;
NYX 0:85b3fd62ea1a 491
NYX 0:85b3fd62ea1a 492 /**
NYX 0:85b3fd62ea1a 493 * @brief System configuration controller
NYX 0:85b3fd62ea1a 494 */
NYX 0:85b3fd62ea1a 495
NYX 0:85b3fd62ea1a 496 typedef struct
NYX 0:85b3fd62ea1a 497 {
NYX 0:85b3fd62ea1a 498 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 499 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 500 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
NYX 0:85b3fd62ea1a 501 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
NYX 0:85b3fd62ea1a 502 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 503 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
NYX 0:85b3fd62ea1a 504 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
NYX 0:85b3fd62ea1a 505 } SYSCFG_TypeDef;
NYX 0:85b3fd62ea1a 506
NYX 0:85b3fd62ea1a 507 /**
NYX 0:85b3fd62ea1a 508 * @brief Inter-integrated Circuit Interface
NYX 0:85b3fd62ea1a 509 */
NYX 0:85b3fd62ea1a 510
NYX 0:85b3fd62ea1a 511 typedef struct
NYX 0:85b3fd62ea1a 512 {
NYX 0:85b3fd62ea1a 513 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 514 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 515 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 516 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 517 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 518 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 519 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 520 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 521 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 522 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 523 } I2C_TypeDef;
NYX 0:85b3fd62ea1a 524
NYX 0:85b3fd62ea1a 525 /**
NYX 0:85b3fd62ea1a 526 * @brief Inter-integrated Circuit Interface
NYX 0:85b3fd62ea1a 527 */
NYX 0:85b3fd62ea1a 528
NYX 0:85b3fd62ea1a 529 typedef struct
NYX 0:85b3fd62ea1a 530 {
NYX 0:85b3fd62ea1a 531 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 532 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 533 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 534 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 535 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 536 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 537 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 538 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 539 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 540 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 541 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
NYX 0:85b3fd62ea1a 542 } FMPI2C_TypeDef;
NYX 0:85b3fd62ea1a 543
NYX 0:85b3fd62ea1a 544 /**
NYX 0:85b3fd62ea1a 545 * @brief Independent WATCHDOG
NYX 0:85b3fd62ea1a 546 */
NYX 0:85b3fd62ea1a 547
NYX 0:85b3fd62ea1a 548 typedef struct
NYX 0:85b3fd62ea1a 549 {
NYX 0:85b3fd62ea1a 550 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 551 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 552 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 553 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 554 } IWDG_TypeDef;
NYX 0:85b3fd62ea1a 555
NYX 0:85b3fd62ea1a 556
NYX 0:85b3fd62ea1a 557 /**
NYX 0:85b3fd62ea1a 558 * @brief Power Control
NYX 0:85b3fd62ea1a 559 */
NYX 0:85b3fd62ea1a 560
NYX 0:85b3fd62ea1a 561 typedef struct
NYX 0:85b3fd62ea1a 562 {
NYX 0:85b3fd62ea1a 563 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 564 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 565 } PWR_TypeDef;
NYX 0:85b3fd62ea1a 566
NYX 0:85b3fd62ea1a 567 /**
NYX 0:85b3fd62ea1a 568 * @brief Reset and Clock Control
NYX 0:85b3fd62ea1a 569 */
NYX 0:85b3fd62ea1a 570
NYX 0:85b3fd62ea1a 571 typedef struct
NYX 0:85b3fd62ea1a 572 {
NYX 0:85b3fd62ea1a 573 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 574 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 575 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 576 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 577 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 578 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 579 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 580 uint32_t RESERVED0; /*!< Reserved, 0x1C */
NYX 0:85b3fd62ea1a 581 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 582 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 583 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
NYX 0:85b3fd62ea1a 584 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
NYX 0:85b3fd62ea1a 585 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
NYX 0:85b3fd62ea1a 586 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
NYX 0:85b3fd62ea1a 587 uint32_t RESERVED2; /*!< Reserved, 0x3C */
NYX 0:85b3fd62ea1a 588 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
NYX 0:85b3fd62ea1a 589 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
NYX 0:85b3fd62ea1a 590 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
NYX 0:85b3fd62ea1a 591 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
NYX 0:85b3fd62ea1a 592 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
NYX 0:85b3fd62ea1a 593 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
NYX 0:85b3fd62ea1a 594 uint32_t RESERVED4; /*!< Reserved, 0x5C */
NYX 0:85b3fd62ea1a 595 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
NYX 0:85b3fd62ea1a 596 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
NYX 0:85b3fd62ea1a 597 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
NYX 0:85b3fd62ea1a 598 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
NYX 0:85b3fd62ea1a 599 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
NYX 0:85b3fd62ea1a 600 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
NYX 0:85b3fd62ea1a 601 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
NYX 0:85b3fd62ea1a 602 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
NYX 0:85b3fd62ea1a 603 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
NYX 0:85b3fd62ea1a 604 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
NYX 0:85b3fd62ea1a 605 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
NYX 0:85b3fd62ea1a 606 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
NYX 0:85b3fd62ea1a 607 } RCC_TypeDef;
NYX 0:85b3fd62ea1a 608
NYX 0:85b3fd62ea1a 609 /**
NYX 0:85b3fd62ea1a 610 * @brief Real-Time Clock
NYX 0:85b3fd62ea1a 611 */
NYX 0:85b3fd62ea1a 612
NYX 0:85b3fd62ea1a 613 typedef struct
NYX 0:85b3fd62ea1a 614 {
NYX 0:85b3fd62ea1a 615 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 616 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 617 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 618 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 619 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 620 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 621 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 622 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 623 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 624 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 625 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
NYX 0:85b3fd62ea1a 626 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
NYX 0:85b3fd62ea1a 627 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
NYX 0:85b3fd62ea1a 628 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
NYX 0:85b3fd62ea1a 629 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
NYX 0:85b3fd62ea1a 630 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
NYX 0:85b3fd62ea1a 631 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
NYX 0:85b3fd62ea1a 632 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
NYX 0:85b3fd62ea1a 633 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
NYX 0:85b3fd62ea1a 634 uint32_t RESERVED7; /*!< Reserved, 0x4C */
NYX 0:85b3fd62ea1a 635 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
NYX 0:85b3fd62ea1a 636 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
NYX 0:85b3fd62ea1a 637 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
NYX 0:85b3fd62ea1a 638 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
NYX 0:85b3fd62ea1a 639 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
NYX 0:85b3fd62ea1a 640 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
NYX 0:85b3fd62ea1a 641 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
NYX 0:85b3fd62ea1a 642 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
NYX 0:85b3fd62ea1a 643 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
NYX 0:85b3fd62ea1a 644 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
NYX 0:85b3fd62ea1a 645 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
NYX 0:85b3fd62ea1a 646 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
NYX 0:85b3fd62ea1a 647 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
NYX 0:85b3fd62ea1a 648 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
NYX 0:85b3fd62ea1a 649 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
NYX 0:85b3fd62ea1a 650 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
NYX 0:85b3fd62ea1a 651 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
NYX 0:85b3fd62ea1a 652 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
NYX 0:85b3fd62ea1a 653 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
NYX 0:85b3fd62ea1a 654 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
NYX 0:85b3fd62ea1a 655 } RTC_TypeDef;
NYX 0:85b3fd62ea1a 656
NYX 0:85b3fd62ea1a 657 /**
NYX 0:85b3fd62ea1a 658 * @brief Serial Audio Interface
NYX 0:85b3fd62ea1a 659 */
NYX 0:85b3fd62ea1a 660
NYX 0:85b3fd62ea1a 661 typedef struct
NYX 0:85b3fd62ea1a 662 {
NYX 0:85b3fd62ea1a 663 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 664 } SAI_TypeDef;
NYX 0:85b3fd62ea1a 665
NYX 0:85b3fd62ea1a 666 typedef struct
NYX 0:85b3fd62ea1a 667 {
NYX 0:85b3fd62ea1a 668 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 669 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 670 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 671 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 672 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 673 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 674 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 675 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 676 } SAI_Block_TypeDef;
NYX 0:85b3fd62ea1a 677
NYX 0:85b3fd62ea1a 678 /**
NYX 0:85b3fd62ea1a 679 * @brief SD host Interface
NYX 0:85b3fd62ea1a 680 */
NYX 0:85b3fd62ea1a 681
NYX 0:85b3fd62ea1a 682 typedef struct
NYX 0:85b3fd62ea1a 683 {
NYX 0:85b3fd62ea1a 684 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 685 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 686 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 687 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 688 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 689 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 690 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 691 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 692 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 693 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 694 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
NYX 0:85b3fd62ea1a 695 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
NYX 0:85b3fd62ea1a 696 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
NYX 0:85b3fd62ea1a 697 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
NYX 0:85b3fd62ea1a 698 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
NYX 0:85b3fd62ea1a 699 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
NYX 0:85b3fd62ea1a 700 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
NYX 0:85b3fd62ea1a 701 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
NYX 0:85b3fd62ea1a 702 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
NYX 0:85b3fd62ea1a 703 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
NYX 0:85b3fd62ea1a 704 } SDIO_TypeDef;
NYX 0:85b3fd62ea1a 705
NYX 0:85b3fd62ea1a 706 /**
NYX 0:85b3fd62ea1a 707 * @brief Serial Peripheral Interface
NYX 0:85b3fd62ea1a 708 */
NYX 0:85b3fd62ea1a 709
NYX 0:85b3fd62ea1a 710 typedef struct
NYX 0:85b3fd62ea1a 711 {
NYX 0:85b3fd62ea1a 712 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
NYX 0:85b3fd62ea1a 713 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 714 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 715 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 716 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
NYX 0:85b3fd62ea1a 717 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
NYX 0:85b3fd62ea1a 718 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
NYX 0:85b3fd62ea1a 719 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 720 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 721 } SPI_TypeDef;
NYX 0:85b3fd62ea1a 722
NYX 0:85b3fd62ea1a 723 /**
NYX 0:85b3fd62ea1a 724 * @brief QUAD Serial Peripheral Interface
NYX 0:85b3fd62ea1a 725 */
NYX 0:85b3fd62ea1a 726
NYX 0:85b3fd62ea1a 727 typedef struct
NYX 0:85b3fd62ea1a 728 {
NYX 0:85b3fd62ea1a 729 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 730 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 731 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 732 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 733 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 734 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 735 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 736 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 737 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 738 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 739 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
NYX 0:85b3fd62ea1a 740 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
NYX 0:85b3fd62ea1a 741 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
NYX 0:85b3fd62ea1a 742 } QUADSPI_TypeDef;
NYX 0:85b3fd62ea1a 743
NYX 0:85b3fd62ea1a 744 /**
NYX 0:85b3fd62ea1a 745 * @brief SPDIFRX Interface
NYX 0:85b3fd62ea1a 746 */
NYX 0:85b3fd62ea1a 747
NYX 0:85b3fd62ea1a 748 typedef struct
NYX 0:85b3fd62ea1a 749 {
NYX 0:85b3fd62ea1a 750 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 751 __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 752 uint16_t RESERVED0; /*!< Reserved, 0x06 */
NYX 0:85b3fd62ea1a 753 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 754 __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 755 uint16_t RESERVED1; /*!< Reserved, 0x0E */
NYX 0:85b3fd62ea1a 756 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 757 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 758 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 759 uint16_t RESERVED2; /*!< Reserved, 0x1A */
NYX 0:85b3fd62ea1a 760 } SPDIFRX_TypeDef;
NYX 0:85b3fd62ea1a 761
NYX 0:85b3fd62ea1a 762 /**
NYX 0:85b3fd62ea1a 763 * @brief TIM
NYX 0:85b3fd62ea1a 764 */
NYX 0:85b3fd62ea1a 765
NYX 0:85b3fd62ea1a 766 typedef struct
NYX 0:85b3fd62ea1a 767 {
NYX 0:85b3fd62ea1a 768 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 769 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 770 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 771 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 772 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 773 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 774 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 775 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
NYX 0:85b3fd62ea1a 776 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
NYX 0:85b3fd62ea1a 777 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
NYX 0:85b3fd62ea1a 778 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
NYX 0:85b3fd62ea1a 779 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
NYX 0:85b3fd62ea1a 780 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
NYX 0:85b3fd62ea1a 781 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
NYX 0:85b3fd62ea1a 782 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
NYX 0:85b3fd62ea1a 783 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
NYX 0:85b3fd62ea1a 784 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
NYX 0:85b3fd62ea1a 785 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
NYX 0:85b3fd62ea1a 786 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
NYX 0:85b3fd62ea1a 787 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
NYX 0:85b3fd62ea1a 788 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
NYX 0:85b3fd62ea1a 789 } TIM_TypeDef;
NYX 0:85b3fd62ea1a 790
NYX 0:85b3fd62ea1a 791 /**
NYX 0:85b3fd62ea1a 792 * @brief Universal Synchronous Asynchronous Receiver Transmitter
NYX 0:85b3fd62ea1a 793 */
NYX 0:85b3fd62ea1a 794
NYX 0:85b3fd62ea1a 795 typedef struct
NYX 0:85b3fd62ea1a 796 {
NYX 0:85b3fd62ea1a 797 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 798 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 799 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 800 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
NYX 0:85b3fd62ea1a 801 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
NYX 0:85b3fd62ea1a 802 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
NYX 0:85b3fd62ea1a 803 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
NYX 0:85b3fd62ea1a 804 } USART_TypeDef;
NYX 0:85b3fd62ea1a 805
NYX 0:85b3fd62ea1a 806 /**
NYX 0:85b3fd62ea1a 807 * @brief Window WATCHDOG
NYX 0:85b3fd62ea1a 808 */
NYX 0:85b3fd62ea1a 809
NYX 0:85b3fd62ea1a 810 typedef struct
NYX 0:85b3fd62ea1a 811 {
NYX 0:85b3fd62ea1a 812 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
NYX 0:85b3fd62ea1a 813 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
NYX 0:85b3fd62ea1a 814 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
NYX 0:85b3fd62ea1a 815 } WWDG_TypeDef;
NYX 0:85b3fd62ea1a 816 /**
NYX 0:85b3fd62ea1a 817 * @brief USB_OTG_Core_Registers
NYX 0:85b3fd62ea1a 818 */
NYX 0:85b3fd62ea1a 819 typedef struct
NYX 0:85b3fd62ea1a 820 {
NYX 0:85b3fd62ea1a 821 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
NYX 0:85b3fd62ea1a 822 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
NYX 0:85b3fd62ea1a 823 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
NYX 0:85b3fd62ea1a 824 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
NYX 0:85b3fd62ea1a 825 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
NYX 0:85b3fd62ea1a 826 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
NYX 0:85b3fd62ea1a 827 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
NYX 0:85b3fd62ea1a 828 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
NYX 0:85b3fd62ea1a 829 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
NYX 0:85b3fd62ea1a 830 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
NYX 0:85b3fd62ea1a 831 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
NYX 0:85b3fd62ea1a 832 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
NYX 0:85b3fd62ea1a 833 uint32_t Reserved30[2]; /*!< Reserved 030h */
NYX 0:85b3fd62ea1a 834 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
NYX 0:85b3fd62ea1a 835 __IO uint32_t CID; /*!< User ID Register 03Ch */
NYX 0:85b3fd62ea1a 836 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
NYX 0:85b3fd62ea1a 837 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
NYX 0:85b3fd62ea1a 838 uint32_t Reserved6; /*!< Reserved 050h */
NYX 0:85b3fd62ea1a 839 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
NYX 0:85b3fd62ea1a 840 uint32_t Reserved; /*!< Reserved 058h */
NYX 0:85b3fd62ea1a 841 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
NYX 0:85b3fd62ea1a 842 uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
NYX 0:85b3fd62ea1a 843 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
NYX 0:85b3fd62ea1a 844 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
NYX 0:85b3fd62ea1a 845 } USB_OTG_GlobalTypeDef;
NYX 0:85b3fd62ea1a 846
NYX 0:85b3fd62ea1a 847 /**
NYX 0:85b3fd62ea1a 848 * @brief USB_OTG_device_Registers
NYX 0:85b3fd62ea1a 849 */
NYX 0:85b3fd62ea1a 850 typedef struct
NYX 0:85b3fd62ea1a 851 {
NYX 0:85b3fd62ea1a 852 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
NYX 0:85b3fd62ea1a 853 __IO uint32_t DCTL; /*!< dev Control Register 804h */
NYX 0:85b3fd62ea1a 854 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
NYX 0:85b3fd62ea1a 855 uint32_t Reserved0C; /*!< Reserved 80Ch */
NYX 0:85b3fd62ea1a 856 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
NYX 0:85b3fd62ea1a 857 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
NYX 0:85b3fd62ea1a 858 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
NYX 0:85b3fd62ea1a 859 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
NYX 0:85b3fd62ea1a 860 uint32_t Reserved20; /*!< Reserved 820h */
NYX 0:85b3fd62ea1a 861 uint32_t Reserved9; /*!< Reserved 824h */
NYX 0:85b3fd62ea1a 862 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
NYX 0:85b3fd62ea1a 863 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
NYX 0:85b3fd62ea1a 864 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
NYX 0:85b3fd62ea1a 865 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
NYX 0:85b3fd62ea1a 866 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
NYX 0:85b3fd62ea1a 867 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
NYX 0:85b3fd62ea1a 868 uint32_t Reserved40; /*!< dedicated EP mask 840h */
NYX 0:85b3fd62ea1a 869 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
NYX 0:85b3fd62ea1a 870 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
NYX 0:85b3fd62ea1a 871 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
NYX 0:85b3fd62ea1a 872 } USB_OTG_DeviceTypeDef;
NYX 0:85b3fd62ea1a 873
NYX 0:85b3fd62ea1a 874 /**
NYX 0:85b3fd62ea1a 875 * @brief USB_OTG_IN_Endpoint-Specific_Register
NYX 0:85b3fd62ea1a 876 */
NYX 0:85b3fd62ea1a 877 typedef struct
NYX 0:85b3fd62ea1a 878 {
NYX 0:85b3fd62ea1a 879 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
NYX 0:85b3fd62ea1a 880 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
NYX 0:85b3fd62ea1a 881 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
NYX 0:85b3fd62ea1a 882 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
NYX 0:85b3fd62ea1a 883 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
NYX 0:85b3fd62ea1a 884 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
NYX 0:85b3fd62ea1a 885 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
NYX 0:85b3fd62ea1a 886 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
NYX 0:85b3fd62ea1a 887 } USB_OTG_INEndpointTypeDef;
NYX 0:85b3fd62ea1a 888
NYX 0:85b3fd62ea1a 889 /**
NYX 0:85b3fd62ea1a 890 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
NYX 0:85b3fd62ea1a 891 */
NYX 0:85b3fd62ea1a 892 typedef struct
NYX 0:85b3fd62ea1a 893 {
NYX 0:85b3fd62ea1a 894 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
NYX 0:85b3fd62ea1a 895 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
NYX 0:85b3fd62ea1a 896 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
NYX 0:85b3fd62ea1a 897 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
NYX 0:85b3fd62ea1a 898 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
NYX 0:85b3fd62ea1a 899 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
NYX 0:85b3fd62ea1a 900 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
NYX 0:85b3fd62ea1a 901 } USB_OTG_OUTEndpointTypeDef;
NYX 0:85b3fd62ea1a 902
NYX 0:85b3fd62ea1a 903 /**
NYX 0:85b3fd62ea1a 904 * @brief USB_OTG_Host_Mode_Register_Structures
NYX 0:85b3fd62ea1a 905 */
NYX 0:85b3fd62ea1a 906 typedef struct
NYX 0:85b3fd62ea1a 907 {
NYX 0:85b3fd62ea1a 908 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
NYX 0:85b3fd62ea1a 909 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
NYX 0:85b3fd62ea1a 910 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
NYX 0:85b3fd62ea1a 911 uint32_t Reserved40C; /*!< Reserved 40Ch */
NYX 0:85b3fd62ea1a 912 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
NYX 0:85b3fd62ea1a 913 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
NYX 0:85b3fd62ea1a 914 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
NYX 0:85b3fd62ea1a 915 } USB_OTG_HostTypeDef;
NYX 0:85b3fd62ea1a 916
NYX 0:85b3fd62ea1a 917 /**
NYX 0:85b3fd62ea1a 918 * @brief USB_OTG_Host_Channel_Specific_Registers
NYX 0:85b3fd62ea1a 919 */
NYX 0:85b3fd62ea1a 920 typedef struct
NYX 0:85b3fd62ea1a 921 {
NYX 0:85b3fd62ea1a 922 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
NYX 0:85b3fd62ea1a 923 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
NYX 0:85b3fd62ea1a 924 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
NYX 0:85b3fd62ea1a 925 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
NYX 0:85b3fd62ea1a 926 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
NYX 0:85b3fd62ea1a 927 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
NYX 0:85b3fd62ea1a 928 uint32_t Reserved[2]; /*!< Reserved */
NYX 0:85b3fd62ea1a 929 } USB_OTG_HostChannelTypeDef;
NYX 0:85b3fd62ea1a 930
NYX 0:85b3fd62ea1a 931 /**
NYX 0:85b3fd62ea1a 932 * @}
NYX 0:85b3fd62ea1a 933 */
NYX 0:85b3fd62ea1a 934
NYX 0:85b3fd62ea1a 935 /** @addtogroup Peripheral_memory_map
NYX 0:85b3fd62ea1a 936 * @{
NYX 0:85b3fd62ea1a 937 */
NYX 0:85b3fd62ea1a 938 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
NYX 0:85b3fd62ea1a 939 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
NYX 0:85b3fd62ea1a 940 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
NYX 0:85b3fd62ea1a 941 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
NYX 0:85b3fd62ea1a 942 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
NYX 0:85b3fd62ea1a 943 #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
NYX 0:85b3fd62ea1a 944 #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
NYX 0:85b3fd62ea1a 945 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
NYX 0:85b3fd62ea1a 946 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
NYX 0:85b3fd62ea1a 947 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
NYX 0:85b3fd62ea1a 948 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
NYX 0:85b3fd62ea1a 949 #define FLASH_END 0x0807FFFFU /*!< FLASH end address */
NYX 0:85b3fd62ea1a 950 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
NYX 0:85b3fd62ea1a 951 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
NYX 0:85b3fd62ea1a 952
NYX 0:85b3fd62ea1a 953 /* Legacy defines */
NYX 0:85b3fd62ea1a 954 #define SRAM_BASE SRAM1_BASE
NYX 0:85b3fd62ea1a 955 #define SRAM_BB_BASE SRAM1_BB_BASE
NYX 0:85b3fd62ea1a 956
NYX 0:85b3fd62ea1a 957 /*!< Peripheral memory map */
NYX 0:85b3fd62ea1a 958 #define APB1PERIPH_BASE PERIPH_BASE
NYX 0:85b3fd62ea1a 959 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
NYX 0:85b3fd62ea1a 960 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
NYX 0:85b3fd62ea1a 961 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
NYX 0:85b3fd62ea1a 962
NYX 0:85b3fd62ea1a 963 /*!< APB1 peripherals */
NYX 0:85b3fd62ea1a 964 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
NYX 0:85b3fd62ea1a 965 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
NYX 0:85b3fd62ea1a 966 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
NYX 0:85b3fd62ea1a 967 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
NYX 0:85b3fd62ea1a 968 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
NYX 0:85b3fd62ea1a 969 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
NYX 0:85b3fd62ea1a 970 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
NYX 0:85b3fd62ea1a 971 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
NYX 0:85b3fd62ea1a 972 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
NYX 0:85b3fd62ea1a 973 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
NYX 0:85b3fd62ea1a 974 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
NYX 0:85b3fd62ea1a 975 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
NYX 0:85b3fd62ea1a 976 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
NYX 0:85b3fd62ea1a 977 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
NYX 0:85b3fd62ea1a 978 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
NYX 0:85b3fd62ea1a 979 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
NYX 0:85b3fd62ea1a 980 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
NYX 0:85b3fd62ea1a 981 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
NYX 0:85b3fd62ea1a 982 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
NYX 0:85b3fd62ea1a 983 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
NYX 0:85b3fd62ea1a 984 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
NYX 0:85b3fd62ea1a 985 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
NYX 0:85b3fd62ea1a 986 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
NYX 0:85b3fd62ea1a 987 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
NYX 0:85b3fd62ea1a 988 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
NYX 0:85b3fd62ea1a 989 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
NYX 0:85b3fd62ea1a 990 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
NYX 0:85b3fd62ea1a 991 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
NYX 0:85b3fd62ea1a 992
NYX 0:85b3fd62ea1a 993 /*!< APB2 peripherals */
NYX 0:85b3fd62ea1a 994 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
NYX 0:85b3fd62ea1a 995 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
NYX 0:85b3fd62ea1a 996 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
NYX 0:85b3fd62ea1a 997 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
NYX 0:85b3fd62ea1a 998 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
NYX 0:85b3fd62ea1a 999 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
NYX 0:85b3fd62ea1a 1000 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
NYX 0:85b3fd62ea1a 1001 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
NYX 0:85b3fd62ea1a 1002 /* Legacy define */
NYX 0:85b3fd62ea1a 1003 #define ADC_BASE ADC123_COMMON_BASE
NYX 0:85b3fd62ea1a 1004 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
NYX 0:85b3fd62ea1a 1005 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
NYX 0:85b3fd62ea1a 1006 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
NYX 0:85b3fd62ea1a 1007 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
NYX 0:85b3fd62ea1a 1008 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
NYX 0:85b3fd62ea1a 1009 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
NYX 0:85b3fd62ea1a 1010 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
NYX 0:85b3fd62ea1a 1011 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
NYX 0:85b3fd62ea1a 1012 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
NYX 0:85b3fd62ea1a 1013 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
NYX 0:85b3fd62ea1a 1014 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
NYX 0:85b3fd62ea1a 1015 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
NYX 0:85b3fd62ea1a 1016 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
NYX 0:85b3fd62ea1a 1017 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
NYX 0:85b3fd62ea1a 1018
NYX 0:85b3fd62ea1a 1019 /*!< AHB1 peripherals */
NYX 0:85b3fd62ea1a 1020 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
NYX 0:85b3fd62ea1a 1021 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
NYX 0:85b3fd62ea1a 1022 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
NYX 0:85b3fd62ea1a 1023 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
NYX 0:85b3fd62ea1a 1024 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
NYX 0:85b3fd62ea1a 1025 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
NYX 0:85b3fd62ea1a 1026 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
NYX 0:85b3fd62ea1a 1027 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
NYX 0:85b3fd62ea1a 1028 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
NYX 0:85b3fd62ea1a 1029 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
NYX 0:85b3fd62ea1a 1030 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
NYX 0:85b3fd62ea1a 1031 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
NYX 0:85b3fd62ea1a 1032 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
NYX 0:85b3fd62ea1a 1033 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
NYX 0:85b3fd62ea1a 1034 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
NYX 0:85b3fd62ea1a 1035 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
NYX 0:85b3fd62ea1a 1036 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
NYX 0:85b3fd62ea1a 1037 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
NYX 0:85b3fd62ea1a 1038 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
NYX 0:85b3fd62ea1a 1039 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
NYX 0:85b3fd62ea1a 1040 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
NYX 0:85b3fd62ea1a 1041 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
NYX 0:85b3fd62ea1a 1042 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
NYX 0:85b3fd62ea1a 1043 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
NYX 0:85b3fd62ea1a 1044 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
NYX 0:85b3fd62ea1a 1045 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
NYX 0:85b3fd62ea1a 1046 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
NYX 0:85b3fd62ea1a 1047 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
NYX 0:85b3fd62ea1a 1048 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
NYX 0:85b3fd62ea1a 1049
NYX 0:85b3fd62ea1a 1050 /*!< AHB2 peripherals */
NYX 0:85b3fd62ea1a 1051 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
NYX 0:85b3fd62ea1a 1052
NYX 0:85b3fd62ea1a 1053 /*!< FMC Bankx registers base address */
NYX 0:85b3fd62ea1a 1054 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
NYX 0:85b3fd62ea1a 1055 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
NYX 0:85b3fd62ea1a 1056 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
NYX 0:85b3fd62ea1a 1057 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
NYX 0:85b3fd62ea1a 1058
NYX 0:85b3fd62ea1a 1059
NYX 0:85b3fd62ea1a 1060 /*!< Debug MCU registers base address */
NYX 0:85b3fd62ea1a 1061 #define DBGMCU_BASE 0xE0042000U
NYX 0:85b3fd62ea1a 1062 /*!< USB registers base address */
NYX 0:85b3fd62ea1a 1063 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
NYX 0:85b3fd62ea1a 1064 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
NYX 0:85b3fd62ea1a 1065
NYX 0:85b3fd62ea1a 1066 #define USB_OTG_GLOBAL_BASE 0x000U
NYX 0:85b3fd62ea1a 1067 #define USB_OTG_DEVICE_BASE 0x800U
NYX 0:85b3fd62ea1a 1068 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
NYX 0:85b3fd62ea1a 1069 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
NYX 0:85b3fd62ea1a 1070 #define USB_OTG_EP_REG_SIZE 0x20U
NYX 0:85b3fd62ea1a 1071 #define USB_OTG_HOST_BASE 0x400U
NYX 0:85b3fd62ea1a 1072 #define USB_OTG_HOST_PORT_BASE 0x440U
NYX 0:85b3fd62ea1a 1073 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
NYX 0:85b3fd62ea1a 1074 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
NYX 0:85b3fd62ea1a 1075 #define USB_OTG_PCGCCTL_BASE 0xE00U
NYX 0:85b3fd62ea1a 1076 #define USB_OTG_FIFO_BASE 0x1000U
NYX 0:85b3fd62ea1a 1077 #define USB_OTG_FIFO_SIZE 0x1000U
NYX 0:85b3fd62ea1a 1078
NYX 0:85b3fd62ea1a 1079 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
NYX 0:85b3fd62ea1a 1080 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
NYX 0:85b3fd62ea1a 1081 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
NYX 0:85b3fd62ea1a 1082 /**
NYX 0:85b3fd62ea1a 1083 * @}
NYX 0:85b3fd62ea1a 1084 */
NYX 0:85b3fd62ea1a 1085
NYX 0:85b3fd62ea1a 1086 /** @addtogroup Peripheral_declaration
NYX 0:85b3fd62ea1a 1087 * @{
NYX 0:85b3fd62ea1a 1088 */
NYX 0:85b3fd62ea1a 1089 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
NYX 0:85b3fd62ea1a 1090 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
NYX 0:85b3fd62ea1a 1091 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
NYX 0:85b3fd62ea1a 1092 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
NYX 0:85b3fd62ea1a 1093 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
NYX 0:85b3fd62ea1a 1094 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
NYX 0:85b3fd62ea1a 1095 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
NYX 0:85b3fd62ea1a 1096 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
NYX 0:85b3fd62ea1a 1097 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
NYX 0:85b3fd62ea1a 1098 #define RTC ((RTC_TypeDef *) RTC_BASE)
NYX 0:85b3fd62ea1a 1099 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
NYX 0:85b3fd62ea1a 1100 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
NYX 0:85b3fd62ea1a 1101 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
NYX 0:85b3fd62ea1a 1102 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
NYX 0:85b3fd62ea1a 1103 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
NYX 0:85b3fd62ea1a 1104 #define USART2 ((USART_TypeDef *) USART2_BASE)
NYX 0:85b3fd62ea1a 1105 #define USART3 ((USART_TypeDef *) USART3_BASE)
NYX 0:85b3fd62ea1a 1106 #define UART4 ((USART_TypeDef *) UART4_BASE)
NYX 0:85b3fd62ea1a 1107 #define UART5 ((USART_TypeDef *) UART5_BASE)
NYX 0:85b3fd62ea1a 1108 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
NYX 0:85b3fd62ea1a 1109 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
NYX 0:85b3fd62ea1a 1110 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
NYX 0:85b3fd62ea1a 1111 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
NYX 0:85b3fd62ea1a 1112 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
NYX 0:85b3fd62ea1a 1113 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
NYX 0:85b3fd62ea1a 1114 #define CEC ((CEC_TypeDef *) CEC_BASE)
NYX 0:85b3fd62ea1a 1115 #define PWR ((PWR_TypeDef *) PWR_BASE)
NYX 0:85b3fd62ea1a 1116 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
NYX 0:85b3fd62ea1a 1117 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
NYX 0:85b3fd62ea1a 1118 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
NYX 0:85b3fd62ea1a 1119 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
NYX 0:85b3fd62ea1a 1120 #define USART1 ((USART_TypeDef *) USART1_BASE)
NYX 0:85b3fd62ea1a 1121 #define USART6 ((USART_TypeDef *) USART6_BASE)
NYX 0:85b3fd62ea1a 1122 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
NYX 0:85b3fd62ea1a 1123 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
NYX 0:85b3fd62ea1a 1124 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
NYX 0:85b3fd62ea1a 1125 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
NYX 0:85b3fd62ea1a 1126 /* Legacy define */
NYX 0:85b3fd62ea1a 1127 #define ADC ADC123_COMMON
NYX 0:85b3fd62ea1a 1128 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
NYX 0:85b3fd62ea1a 1129 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
NYX 0:85b3fd62ea1a 1130 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
NYX 0:85b3fd62ea1a 1131 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
NYX 0:85b3fd62ea1a 1132 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
NYX 0:85b3fd62ea1a 1133 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
NYX 0:85b3fd62ea1a 1134 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
NYX 0:85b3fd62ea1a 1135 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
NYX 0:85b3fd62ea1a 1136 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
NYX 0:85b3fd62ea1a 1137 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
NYX 0:85b3fd62ea1a 1138 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
NYX 0:85b3fd62ea1a 1139 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
NYX 0:85b3fd62ea1a 1140 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
NYX 0:85b3fd62ea1a 1141 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
NYX 0:85b3fd62ea1a 1142 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
NYX 0:85b3fd62ea1a 1143 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
NYX 0:85b3fd62ea1a 1144 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
NYX 0:85b3fd62ea1a 1145 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
NYX 0:85b3fd62ea1a 1146 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
NYX 0:85b3fd62ea1a 1147 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
NYX 0:85b3fd62ea1a 1148 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
NYX 0:85b3fd62ea1a 1149 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
NYX 0:85b3fd62ea1a 1150 #define CRC ((CRC_TypeDef *) CRC_BASE)
NYX 0:85b3fd62ea1a 1151 #define RCC ((RCC_TypeDef *) RCC_BASE)
NYX 0:85b3fd62ea1a 1152 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
NYX 0:85b3fd62ea1a 1153 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
NYX 0:85b3fd62ea1a 1154 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
NYX 0:85b3fd62ea1a 1155 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
NYX 0:85b3fd62ea1a 1156 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
NYX 0:85b3fd62ea1a 1157 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
NYX 0:85b3fd62ea1a 1158 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
NYX 0:85b3fd62ea1a 1159 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
NYX 0:85b3fd62ea1a 1160 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
NYX 0:85b3fd62ea1a 1161 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
NYX 0:85b3fd62ea1a 1162 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
NYX 0:85b3fd62ea1a 1163 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
NYX 0:85b3fd62ea1a 1164 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
NYX 0:85b3fd62ea1a 1165 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
NYX 0:85b3fd62ea1a 1166 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
NYX 0:85b3fd62ea1a 1167 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
NYX 0:85b3fd62ea1a 1168 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
NYX 0:85b3fd62ea1a 1169 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
NYX 0:85b3fd62ea1a 1170 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
NYX 0:85b3fd62ea1a 1171 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
NYX 0:85b3fd62ea1a 1172 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
NYX 0:85b3fd62ea1a 1173 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
NYX 0:85b3fd62ea1a 1174 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
NYX 0:85b3fd62ea1a 1175 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
NYX 0:85b3fd62ea1a 1176 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
NYX 0:85b3fd62ea1a 1177 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
NYX 0:85b3fd62ea1a 1178 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
NYX 0:85b3fd62ea1a 1179 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
NYX 0:85b3fd62ea1a 1180
NYX 0:85b3fd62ea1a 1181 /**
NYX 0:85b3fd62ea1a 1182 * @}
NYX 0:85b3fd62ea1a 1183 */
NYX 0:85b3fd62ea1a 1184
NYX 0:85b3fd62ea1a 1185 /** @addtogroup Exported_constants
NYX 0:85b3fd62ea1a 1186 * @{
NYX 0:85b3fd62ea1a 1187 */
NYX 0:85b3fd62ea1a 1188
NYX 0:85b3fd62ea1a 1189 /** @addtogroup Peripheral_Registers_Bits_Definition
NYX 0:85b3fd62ea1a 1190 * @{
NYX 0:85b3fd62ea1a 1191 */
NYX 0:85b3fd62ea1a 1192
NYX 0:85b3fd62ea1a 1193 /******************************************************************************/
NYX 0:85b3fd62ea1a 1194 /* Peripheral Registers_Bits_Definition */
NYX 0:85b3fd62ea1a 1195 /******************************************************************************/
NYX 0:85b3fd62ea1a 1196
NYX 0:85b3fd62ea1a 1197 /******************************************************************************/
NYX 0:85b3fd62ea1a 1198 /* */
NYX 0:85b3fd62ea1a 1199 /* Analog to Digital Converter */
NYX 0:85b3fd62ea1a 1200 /* */
NYX 0:85b3fd62ea1a 1201 /******************************************************************************/
NYX 0:85b3fd62ea1a 1202 /*
NYX 0:85b3fd62ea1a 1203 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
NYX 0:85b3fd62ea1a 1204 */
NYX 0:85b3fd62ea1a 1205 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
NYX 0:85b3fd62ea1a 1206
NYX 0:85b3fd62ea1a 1207 /******************** Bit definition for ADC_SR register ********************/
NYX 0:85b3fd62ea1a 1208 #define ADC_SR_AWD_Pos (0U)
NYX 0:85b3fd62ea1a 1209 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1210 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
NYX 0:85b3fd62ea1a 1211 #define ADC_SR_EOC_Pos (1U)
NYX 0:85b3fd62ea1a 1212 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1213 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
NYX 0:85b3fd62ea1a 1214 #define ADC_SR_JEOC_Pos (2U)
NYX 0:85b3fd62ea1a 1215 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1216 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
NYX 0:85b3fd62ea1a 1217 #define ADC_SR_JSTRT_Pos (3U)
NYX 0:85b3fd62ea1a 1218 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1219 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
NYX 0:85b3fd62ea1a 1220 #define ADC_SR_STRT_Pos (4U)
NYX 0:85b3fd62ea1a 1221 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1222 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
NYX 0:85b3fd62ea1a 1223 #define ADC_SR_OVR_Pos (5U)
NYX 0:85b3fd62ea1a 1224 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1225 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
NYX 0:85b3fd62ea1a 1226
NYX 0:85b3fd62ea1a 1227 /******************* Bit definition for ADC_CR1 register ********************/
NYX 0:85b3fd62ea1a 1228 #define ADC_CR1_AWDCH_Pos (0U)
NYX 0:85b3fd62ea1a 1229 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 1230 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
NYX 0:85b3fd62ea1a 1231 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1232 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1233 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1234 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1235 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1236 #define ADC_CR1_EOCIE_Pos (5U)
NYX 0:85b3fd62ea1a 1237 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1238 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
NYX 0:85b3fd62ea1a 1239 #define ADC_CR1_AWDIE_Pos (6U)
NYX 0:85b3fd62ea1a 1240 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 1241 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
NYX 0:85b3fd62ea1a 1242 #define ADC_CR1_JEOCIE_Pos (7U)
NYX 0:85b3fd62ea1a 1243 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 1244 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
NYX 0:85b3fd62ea1a 1245 #define ADC_CR1_SCAN_Pos (8U)
NYX 0:85b3fd62ea1a 1246 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1247 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
NYX 0:85b3fd62ea1a 1248 #define ADC_CR1_AWDSGL_Pos (9U)
NYX 0:85b3fd62ea1a 1249 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1250 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
NYX 0:85b3fd62ea1a 1251 #define ADC_CR1_JAUTO_Pos (10U)
NYX 0:85b3fd62ea1a 1252 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1253 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
NYX 0:85b3fd62ea1a 1254 #define ADC_CR1_DISCEN_Pos (11U)
NYX 0:85b3fd62ea1a 1255 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1256 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
NYX 0:85b3fd62ea1a 1257 #define ADC_CR1_JDISCEN_Pos (12U)
NYX 0:85b3fd62ea1a 1258 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 1259 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
NYX 0:85b3fd62ea1a 1260 #define ADC_CR1_DISCNUM_Pos (13U)
NYX 0:85b3fd62ea1a 1261 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
NYX 0:85b3fd62ea1a 1262 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
NYX 0:85b3fd62ea1a 1263 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 1264 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 1265 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1266 #define ADC_CR1_JAWDEN_Pos (22U)
NYX 0:85b3fd62ea1a 1267 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 1268 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
NYX 0:85b3fd62ea1a 1269 #define ADC_CR1_AWDEN_Pos (23U)
NYX 0:85b3fd62ea1a 1270 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 1271 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
NYX 0:85b3fd62ea1a 1272 #define ADC_CR1_RES_Pos (24U)
NYX 0:85b3fd62ea1a 1273 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
NYX 0:85b3fd62ea1a 1274 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
NYX 0:85b3fd62ea1a 1275 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 1276 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 1277 #define ADC_CR1_OVRIE_Pos (26U)
NYX 0:85b3fd62ea1a 1278 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 1279 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
NYX 0:85b3fd62ea1a 1280
NYX 0:85b3fd62ea1a 1281 /******************* Bit definition for ADC_CR2 register ********************/
NYX 0:85b3fd62ea1a 1282 #define ADC_CR2_ADON_Pos (0U)
NYX 0:85b3fd62ea1a 1283 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1284 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
NYX 0:85b3fd62ea1a 1285 #define ADC_CR2_CONT_Pos (1U)
NYX 0:85b3fd62ea1a 1286 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1287 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
NYX 0:85b3fd62ea1a 1288 #define ADC_CR2_DMA_Pos (8U)
NYX 0:85b3fd62ea1a 1289 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1290 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
NYX 0:85b3fd62ea1a 1291 #define ADC_CR2_DDS_Pos (9U)
NYX 0:85b3fd62ea1a 1292 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1293 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
NYX 0:85b3fd62ea1a 1294 #define ADC_CR2_EOCS_Pos (10U)
NYX 0:85b3fd62ea1a 1295 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1296 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
NYX 0:85b3fd62ea1a 1297 #define ADC_CR2_ALIGN_Pos (11U)
NYX 0:85b3fd62ea1a 1298 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1299 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
NYX 0:85b3fd62ea1a 1300 #define ADC_CR2_JEXTSEL_Pos (16U)
NYX 0:85b3fd62ea1a 1301 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 1302 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
NYX 0:85b3fd62ea1a 1303 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1304 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1305 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 1306 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 1307 #define ADC_CR2_JEXTEN_Pos (20U)
NYX 0:85b3fd62ea1a 1308 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 1309 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
NYX 0:85b3fd62ea1a 1310 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 1311 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 1312 #define ADC_CR2_JSWSTART_Pos (22U)
NYX 0:85b3fd62ea1a 1313 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 1314 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
NYX 0:85b3fd62ea1a 1315 #define ADC_CR2_EXTSEL_Pos (24U)
NYX 0:85b3fd62ea1a 1316 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 1317 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
NYX 0:85b3fd62ea1a 1318 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 1319 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 1320 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 1321 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 1322 #define ADC_CR2_EXTEN_Pos (28U)
NYX 0:85b3fd62ea1a 1323 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 1324 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
NYX 0:85b3fd62ea1a 1325 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 1326 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 1327 #define ADC_CR2_SWSTART_Pos (30U)
NYX 0:85b3fd62ea1a 1328 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 1329 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
NYX 0:85b3fd62ea1a 1330
NYX 0:85b3fd62ea1a 1331 /****************** Bit definition for ADC_SMPR1 register *******************/
NYX 0:85b3fd62ea1a 1332 #define ADC_SMPR1_SMP10_Pos (0U)
NYX 0:85b3fd62ea1a 1333 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 1334 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
NYX 0:85b3fd62ea1a 1335 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1336 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1337 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1338 #define ADC_SMPR1_SMP11_Pos (3U)
NYX 0:85b3fd62ea1a 1339 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
NYX 0:85b3fd62ea1a 1340 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
NYX 0:85b3fd62ea1a 1341 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1342 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1343 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1344 #define ADC_SMPR1_SMP12_Pos (6U)
NYX 0:85b3fd62ea1a 1345 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
NYX 0:85b3fd62ea1a 1346 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
NYX 0:85b3fd62ea1a 1347 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 1348 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 1349 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1350 #define ADC_SMPR1_SMP13_Pos (9U)
NYX 0:85b3fd62ea1a 1351 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
NYX 0:85b3fd62ea1a 1352 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
NYX 0:85b3fd62ea1a 1353 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1354 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1355 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1356 #define ADC_SMPR1_SMP14_Pos (12U)
NYX 0:85b3fd62ea1a 1357 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
NYX 0:85b3fd62ea1a 1358 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
NYX 0:85b3fd62ea1a 1359 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 1360 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 1361 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 1362 #define ADC_SMPR1_SMP15_Pos (15U)
NYX 0:85b3fd62ea1a 1363 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
NYX 0:85b3fd62ea1a 1364 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
NYX 0:85b3fd62ea1a 1365 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1366 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1367 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1368 #define ADC_SMPR1_SMP16_Pos (18U)
NYX 0:85b3fd62ea1a 1369 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
NYX 0:85b3fd62ea1a 1370 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
NYX 0:85b3fd62ea1a 1371 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 1372 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 1373 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 1374 #define ADC_SMPR1_SMP17_Pos (21U)
NYX 0:85b3fd62ea1a 1375 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
NYX 0:85b3fd62ea1a 1376 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
NYX 0:85b3fd62ea1a 1377 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 1378 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 1379 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 1380 #define ADC_SMPR1_SMP18_Pos (24U)
NYX 0:85b3fd62ea1a 1381 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
NYX 0:85b3fd62ea1a 1382 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
NYX 0:85b3fd62ea1a 1383 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 1384 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 1385 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 1386
NYX 0:85b3fd62ea1a 1387 /****************** Bit definition for ADC_SMPR2 register *******************/
NYX 0:85b3fd62ea1a 1388 #define ADC_SMPR2_SMP0_Pos (0U)
NYX 0:85b3fd62ea1a 1389 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 1390 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
NYX 0:85b3fd62ea1a 1391 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1392 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1393 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1394 #define ADC_SMPR2_SMP1_Pos (3U)
NYX 0:85b3fd62ea1a 1395 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
NYX 0:85b3fd62ea1a 1396 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
NYX 0:85b3fd62ea1a 1397 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1398 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1399 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1400 #define ADC_SMPR2_SMP2_Pos (6U)
NYX 0:85b3fd62ea1a 1401 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
NYX 0:85b3fd62ea1a 1402 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
NYX 0:85b3fd62ea1a 1403 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 1404 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 1405 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1406 #define ADC_SMPR2_SMP3_Pos (9U)
NYX 0:85b3fd62ea1a 1407 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
NYX 0:85b3fd62ea1a 1408 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
NYX 0:85b3fd62ea1a 1409 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1410 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1411 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1412 #define ADC_SMPR2_SMP4_Pos (12U)
NYX 0:85b3fd62ea1a 1413 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
NYX 0:85b3fd62ea1a 1414 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
NYX 0:85b3fd62ea1a 1415 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 1416 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 1417 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 1418 #define ADC_SMPR2_SMP5_Pos (15U)
NYX 0:85b3fd62ea1a 1419 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
NYX 0:85b3fd62ea1a 1420 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
NYX 0:85b3fd62ea1a 1421 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1422 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1423 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1424 #define ADC_SMPR2_SMP6_Pos (18U)
NYX 0:85b3fd62ea1a 1425 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
NYX 0:85b3fd62ea1a 1426 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
NYX 0:85b3fd62ea1a 1427 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 1428 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 1429 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 1430 #define ADC_SMPR2_SMP7_Pos (21U)
NYX 0:85b3fd62ea1a 1431 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
NYX 0:85b3fd62ea1a 1432 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
NYX 0:85b3fd62ea1a 1433 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 1434 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 1435 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 1436 #define ADC_SMPR2_SMP8_Pos (24U)
NYX 0:85b3fd62ea1a 1437 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
NYX 0:85b3fd62ea1a 1438 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
NYX 0:85b3fd62ea1a 1439 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 1440 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 1441 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 1442 #define ADC_SMPR2_SMP9_Pos (27U)
NYX 0:85b3fd62ea1a 1443 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
NYX 0:85b3fd62ea1a 1444 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
NYX 0:85b3fd62ea1a 1445 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 1446 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 1447 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 1448
NYX 0:85b3fd62ea1a 1449 /****************** Bit definition for ADC_JOFR1 register *******************/
NYX 0:85b3fd62ea1a 1450 #define ADC_JOFR1_JOFFSET1_Pos (0U)
NYX 0:85b3fd62ea1a 1451 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 1452 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
NYX 0:85b3fd62ea1a 1453
NYX 0:85b3fd62ea1a 1454 /****************** Bit definition for ADC_JOFR2 register *******************/
NYX 0:85b3fd62ea1a 1455 #define ADC_JOFR2_JOFFSET2_Pos (0U)
NYX 0:85b3fd62ea1a 1456 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 1457 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
NYX 0:85b3fd62ea1a 1458
NYX 0:85b3fd62ea1a 1459 /****************** Bit definition for ADC_JOFR3 register *******************/
NYX 0:85b3fd62ea1a 1460 #define ADC_JOFR3_JOFFSET3_Pos (0U)
NYX 0:85b3fd62ea1a 1461 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 1462 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
NYX 0:85b3fd62ea1a 1463
NYX 0:85b3fd62ea1a 1464 /****************** Bit definition for ADC_JOFR4 register *******************/
NYX 0:85b3fd62ea1a 1465 #define ADC_JOFR4_JOFFSET4_Pos (0U)
NYX 0:85b3fd62ea1a 1466 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 1467 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
NYX 0:85b3fd62ea1a 1468
NYX 0:85b3fd62ea1a 1469 /******************* Bit definition for ADC_HTR register ********************/
NYX 0:85b3fd62ea1a 1470 #define ADC_HTR_HT_Pos (0U)
NYX 0:85b3fd62ea1a 1471 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 1472 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
NYX 0:85b3fd62ea1a 1473
NYX 0:85b3fd62ea1a 1474 /******************* Bit definition for ADC_LTR register ********************/
NYX 0:85b3fd62ea1a 1475 #define ADC_LTR_LT_Pos (0U)
NYX 0:85b3fd62ea1a 1476 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 1477 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
NYX 0:85b3fd62ea1a 1478
NYX 0:85b3fd62ea1a 1479 /******************* Bit definition for ADC_SQR1 register *******************/
NYX 0:85b3fd62ea1a 1480 #define ADC_SQR1_SQ13_Pos (0U)
NYX 0:85b3fd62ea1a 1481 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 1482 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1483 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1484 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1485 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1486 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1487 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1488 #define ADC_SQR1_SQ14_Pos (5U)
NYX 0:85b3fd62ea1a 1489 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
NYX 0:85b3fd62ea1a 1490 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1491 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1492 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 1493 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 1494 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1495 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1496 #define ADC_SQR1_SQ15_Pos (10U)
NYX 0:85b3fd62ea1a 1497 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
NYX 0:85b3fd62ea1a 1498 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1499 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1500 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1501 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 1502 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 1503 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 1504 #define ADC_SQR1_SQ16_Pos (15U)
NYX 0:85b3fd62ea1a 1505 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
NYX 0:85b3fd62ea1a 1506 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1507 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1508 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1509 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1510 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 1511 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 1512 #define ADC_SQR1_L_Pos (20U)
NYX 0:85b3fd62ea1a 1513 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 1514 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
NYX 0:85b3fd62ea1a 1515 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 1516 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 1517 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 1518 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 1519
NYX 0:85b3fd62ea1a 1520 /******************* Bit definition for ADC_SQR2 register *******************/
NYX 0:85b3fd62ea1a 1521 #define ADC_SQR2_SQ7_Pos (0U)
NYX 0:85b3fd62ea1a 1522 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 1523 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1524 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1525 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1526 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1527 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1528 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1529 #define ADC_SQR2_SQ8_Pos (5U)
NYX 0:85b3fd62ea1a 1530 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
NYX 0:85b3fd62ea1a 1531 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1532 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1533 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 1534 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 1535 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1536 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1537 #define ADC_SQR2_SQ9_Pos (10U)
NYX 0:85b3fd62ea1a 1538 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
NYX 0:85b3fd62ea1a 1539 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1540 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1541 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1542 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 1543 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 1544 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 1545 #define ADC_SQR2_SQ10_Pos (15U)
NYX 0:85b3fd62ea1a 1546 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
NYX 0:85b3fd62ea1a 1547 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1548 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1549 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1550 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1551 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 1552 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 1553 #define ADC_SQR2_SQ11_Pos (20U)
NYX 0:85b3fd62ea1a 1554 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
NYX 0:85b3fd62ea1a 1555 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1556 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 1557 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 1558 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 1559 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 1560 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 1561 #define ADC_SQR2_SQ12_Pos (25U)
NYX 0:85b3fd62ea1a 1562 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
NYX 0:85b3fd62ea1a 1563 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1564 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 1565 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 1566 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 1567 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 1568 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 1569
NYX 0:85b3fd62ea1a 1570 /******************* Bit definition for ADC_SQR3 register *******************/
NYX 0:85b3fd62ea1a 1571 #define ADC_SQR3_SQ1_Pos (0U)
NYX 0:85b3fd62ea1a 1572 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 1573 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1574 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1575 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1576 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1577 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1578 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1579 #define ADC_SQR3_SQ2_Pos (5U)
NYX 0:85b3fd62ea1a 1580 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
NYX 0:85b3fd62ea1a 1581 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1582 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1583 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 1584 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 1585 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1586 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1587 #define ADC_SQR3_SQ3_Pos (10U)
NYX 0:85b3fd62ea1a 1588 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
NYX 0:85b3fd62ea1a 1589 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1590 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1591 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1592 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 1593 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 1594 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 1595 #define ADC_SQR3_SQ4_Pos (15U)
NYX 0:85b3fd62ea1a 1596 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
NYX 0:85b3fd62ea1a 1597 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1598 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1599 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1600 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1601 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 1602 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 1603 #define ADC_SQR3_SQ5_Pos (20U)
NYX 0:85b3fd62ea1a 1604 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
NYX 0:85b3fd62ea1a 1605 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1606 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 1607 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 1608 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 1609 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 1610 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 1611 #define ADC_SQR3_SQ6_Pos (25U)
NYX 0:85b3fd62ea1a 1612 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
NYX 0:85b3fd62ea1a 1613 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
NYX 0:85b3fd62ea1a 1614 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 1615 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 1616 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 1617 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 1618 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 1619
NYX 0:85b3fd62ea1a 1620 /******************* Bit definition for ADC_JSQR register *******************/
NYX 0:85b3fd62ea1a 1621 #define ADC_JSQR_JSQ1_Pos (0U)
NYX 0:85b3fd62ea1a 1622 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 1623 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
NYX 0:85b3fd62ea1a 1624 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1625 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1626 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1627 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1628 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1629 #define ADC_JSQR_JSQ2_Pos (5U)
NYX 0:85b3fd62ea1a 1630 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
NYX 0:85b3fd62ea1a 1631 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
NYX 0:85b3fd62ea1a 1632 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1633 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 1634 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 1635 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1636 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1637 #define ADC_JSQR_JSQ3_Pos (10U)
NYX 0:85b3fd62ea1a 1638 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
NYX 0:85b3fd62ea1a 1639 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
NYX 0:85b3fd62ea1a 1640 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1641 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1642 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 1643 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 1644 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 1645 #define ADC_JSQR_JSQ4_Pos (15U)
NYX 0:85b3fd62ea1a 1646 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
NYX 0:85b3fd62ea1a 1647 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
NYX 0:85b3fd62ea1a 1648 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1649 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1650 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1651 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 1652 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 1653 #define ADC_JSQR_JL_Pos (20U)
NYX 0:85b3fd62ea1a 1654 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 1655 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
NYX 0:85b3fd62ea1a 1656 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 1657 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 1658
NYX 0:85b3fd62ea1a 1659 /******************* Bit definition for ADC_JDR1 register *******************/
NYX 0:85b3fd62ea1a 1660 #define ADC_JDR1_JDATA_Pos (0U)
NYX 0:85b3fd62ea1a 1661 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 1662 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
NYX 0:85b3fd62ea1a 1663
NYX 0:85b3fd62ea1a 1664 /******************* Bit definition for ADC_JDR2 register *******************/
NYX 0:85b3fd62ea1a 1665 #define ADC_JDR2_JDATA_Pos (0U)
NYX 0:85b3fd62ea1a 1666 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 1667 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
NYX 0:85b3fd62ea1a 1668
NYX 0:85b3fd62ea1a 1669 /******************* Bit definition for ADC_JDR3 register *******************/
NYX 0:85b3fd62ea1a 1670 #define ADC_JDR3_JDATA_Pos (0U)
NYX 0:85b3fd62ea1a 1671 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 1672 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
NYX 0:85b3fd62ea1a 1673
NYX 0:85b3fd62ea1a 1674 /******************* Bit definition for ADC_JDR4 register *******************/
NYX 0:85b3fd62ea1a 1675 #define ADC_JDR4_JDATA_Pos (0U)
NYX 0:85b3fd62ea1a 1676 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 1677 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
NYX 0:85b3fd62ea1a 1678
NYX 0:85b3fd62ea1a 1679 /******************** Bit definition for ADC_DR register ********************/
NYX 0:85b3fd62ea1a 1680 #define ADC_DR_DATA_Pos (0U)
NYX 0:85b3fd62ea1a 1681 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 1682 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
NYX 0:85b3fd62ea1a 1683 #define ADC_DR_ADC2DATA_Pos (16U)
NYX 0:85b3fd62ea1a 1684 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 1685 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
NYX 0:85b3fd62ea1a 1686
NYX 0:85b3fd62ea1a 1687 /******************* Bit definition for ADC_CSR register ********************/
NYX 0:85b3fd62ea1a 1688 #define ADC_CSR_AWD1_Pos (0U)
NYX 0:85b3fd62ea1a 1689 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1690 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
NYX 0:85b3fd62ea1a 1691 #define ADC_CSR_EOC1_Pos (1U)
NYX 0:85b3fd62ea1a 1692 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1693 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
NYX 0:85b3fd62ea1a 1694 #define ADC_CSR_JEOC1_Pos (2U)
NYX 0:85b3fd62ea1a 1695 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1696 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
NYX 0:85b3fd62ea1a 1697 #define ADC_CSR_JSTRT1_Pos (3U)
NYX 0:85b3fd62ea1a 1698 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1699 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
NYX 0:85b3fd62ea1a 1700 #define ADC_CSR_STRT1_Pos (4U)
NYX 0:85b3fd62ea1a 1701 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1702 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
NYX 0:85b3fd62ea1a 1703 #define ADC_CSR_OVR1_Pos (5U)
NYX 0:85b3fd62ea1a 1704 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1705 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
NYX 0:85b3fd62ea1a 1706 #define ADC_CSR_AWD2_Pos (8U)
NYX 0:85b3fd62ea1a 1707 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1708 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
NYX 0:85b3fd62ea1a 1709 #define ADC_CSR_EOC2_Pos (9U)
NYX 0:85b3fd62ea1a 1710 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1711 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
NYX 0:85b3fd62ea1a 1712 #define ADC_CSR_JEOC2_Pos (10U)
NYX 0:85b3fd62ea1a 1713 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1714 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
NYX 0:85b3fd62ea1a 1715 #define ADC_CSR_JSTRT2_Pos (11U)
NYX 0:85b3fd62ea1a 1716 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1717 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
NYX 0:85b3fd62ea1a 1718 #define ADC_CSR_STRT2_Pos (12U)
NYX 0:85b3fd62ea1a 1719 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 1720 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
NYX 0:85b3fd62ea1a 1721 #define ADC_CSR_OVR2_Pos (13U)
NYX 0:85b3fd62ea1a 1722 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 1723 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
NYX 0:85b3fd62ea1a 1724 #define ADC_CSR_AWD3_Pos (16U)
NYX 0:85b3fd62ea1a 1725 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1726 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
NYX 0:85b3fd62ea1a 1727 #define ADC_CSR_EOC3_Pos (17U)
NYX 0:85b3fd62ea1a 1728 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1729 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
NYX 0:85b3fd62ea1a 1730 #define ADC_CSR_JEOC3_Pos (18U)
NYX 0:85b3fd62ea1a 1731 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 1732 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
NYX 0:85b3fd62ea1a 1733 #define ADC_CSR_JSTRT3_Pos (19U)
NYX 0:85b3fd62ea1a 1734 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 1735 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
NYX 0:85b3fd62ea1a 1736 #define ADC_CSR_STRT3_Pos (20U)
NYX 0:85b3fd62ea1a 1737 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 1738 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
NYX 0:85b3fd62ea1a 1739 #define ADC_CSR_OVR3_Pos (21U)
NYX 0:85b3fd62ea1a 1740 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 1741 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
NYX 0:85b3fd62ea1a 1742
NYX 0:85b3fd62ea1a 1743 /* Legacy defines */
NYX 0:85b3fd62ea1a 1744 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
NYX 0:85b3fd62ea1a 1745 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
NYX 0:85b3fd62ea1a 1746 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
NYX 0:85b3fd62ea1a 1747
NYX 0:85b3fd62ea1a 1748 /******************* Bit definition for ADC_CCR register ********************/
NYX 0:85b3fd62ea1a 1749 #define ADC_CCR_MULTI_Pos (0U)
NYX 0:85b3fd62ea1a 1750 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 1751 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
NYX 0:85b3fd62ea1a 1752 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1753 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1754 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1755 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1756 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1757 #define ADC_CCR_DELAY_Pos (8U)
NYX 0:85b3fd62ea1a 1758 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 1759 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
NYX 0:85b3fd62ea1a 1760 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1761 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1762 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1763 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1764 #define ADC_CCR_DDS_Pos (13U)
NYX 0:85b3fd62ea1a 1765 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 1766 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
NYX 0:85b3fd62ea1a 1767 #define ADC_CCR_DMA_Pos (14U)
NYX 0:85b3fd62ea1a 1768 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
NYX 0:85b3fd62ea1a 1769 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
NYX 0:85b3fd62ea1a 1770 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 1771 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1772 #define ADC_CCR_ADCPRE_Pos (16U)
NYX 0:85b3fd62ea1a 1773 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 1774 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
NYX 0:85b3fd62ea1a 1775 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1776 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1777 #define ADC_CCR_VBATE_Pos (22U)
NYX 0:85b3fd62ea1a 1778 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 1779 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
NYX 0:85b3fd62ea1a 1780 #define ADC_CCR_TSVREFE_Pos (23U)
NYX 0:85b3fd62ea1a 1781 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 1782 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
NYX 0:85b3fd62ea1a 1783
NYX 0:85b3fd62ea1a 1784 /******************* Bit definition for ADC_CDR register ********************/
NYX 0:85b3fd62ea1a 1785 #define ADC_CDR_DATA1_Pos (0U)
NYX 0:85b3fd62ea1a 1786 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 1787 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
NYX 0:85b3fd62ea1a 1788 #define ADC_CDR_DATA2_Pos (16U)
NYX 0:85b3fd62ea1a 1789 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 1790 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
NYX 0:85b3fd62ea1a 1791
NYX 0:85b3fd62ea1a 1792 /* Legacy defines */
NYX 0:85b3fd62ea1a 1793 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
NYX 0:85b3fd62ea1a 1794 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
NYX 0:85b3fd62ea1a 1795
NYX 0:85b3fd62ea1a 1796 /******************************************************************************/
NYX 0:85b3fd62ea1a 1797 /* */
NYX 0:85b3fd62ea1a 1798 /* Controller Area Network */
NYX 0:85b3fd62ea1a 1799 /* */
NYX 0:85b3fd62ea1a 1800 /******************************************************************************/
NYX 0:85b3fd62ea1a 1801 /*!<CAN control and status registers */
NYX 0:85b3fd62ea1a 1802 /******************* Bit definition for CAN_MCR register ********************/
NYX 0:85b3fd62ea1a 1803 #define CAN_MCR_INRQ_Pos (0U)
NYX 0:85b3fd62ea1a 1804 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1805 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
NYX 0:85b3fd62ea1a 1806 #define CAN_MCR_SLEEP_Pos (1U)
NYX 0:85b3fd62ea1a 1807 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1808 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
NYX 0:85b3fd62ea1a 1809 #define CAN_MCR_TXFP_Pos (2U)
NYX 0:85b3fd62ea1a 1810 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1811 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
NYX 0:85b3fd62ea1a 1812 #define CAN_MCR_RFLM_Pos (3U)
NYX 0:85b3fd62ea1a 1813 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1814 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
NYX 0:85b3fd62ea1a 1815 #define CAN_MCR_NART_Pos (4U)
NYX 0:85b3fd62ea1a 1816 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1817 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
NYX 0:85b3fd62ea1a 1818 #define CAN_MCR_AWUM_Pos (5U)
NYX 0:85b3fd62ea1a 1819 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1820 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
NYX 0:85b3fd62ea1a 1821 #define CAN_MCR_ABOM_Pos (6U)
NYX 0:85b3fd62ea1a 1822 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 1823 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
NYX 0:85b3fd62ea1a 1824 #define CAN_MCR_TTCM_Pos (7U)
NYX 0:85b3fd62ea1a 1825 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 1826 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
NYX 0:85b3fd62ea1a 1827 #define CAN_MCR_RESET_Pos (15U)
NYX 0:85b3fd62ea1a 1828 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1829 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
NYX 0:85b3fd62ea1a 1830 #define CAN_MCR_DBF_Pos (16U)
NYX 0:85b3fd62ea1a 1831 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1832 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
NYX 0:85b3fd62ea1a 1833 /******************* Bit definition for CAN_MSR register ********************/
NYX 0:85b3fd62ea1a 1834 #define CAN_MSR_INAK_Pos (0U)
NYX 0:85b3fd62ea1a 1835 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1836 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
NYX 0:85b3fd62ea1a 1837 #define CAN_MSR_SLAK_Pos (1U)
NYX 0:85b3fd62ea1a 1838 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1839 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
NYX 0:85b3fd62ea1a 1840 #define CAN_MSR_ERRI_Pos (2U)
NYX 0:85b3fd62ea1a 1841 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1842 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
NYX 0:85b3fd62ea1a 1843 #define CAN_MSR_WKUI_Pos (3U)
NYX 0:85b3fd62ea1a 1844 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1845 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
NYX 0:85b3fd62ea1a 1846 #define CAN_MSR_SLAKI_Pos (4U)
NYX 0:85b3fd62ea1a 1847 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1848 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
NYX 0:85b3fd62ea1a 1849 #define CAN_MSR_TXM_Pos (8U)
NYX 0:85b3fd62ea1a 1850 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1851 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
NYX 0:85b3fd62ea1a 1852 #define CAN_MSR_RXM_Pos (9U)
NYX 0:85b3fd62ea1a 1853 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1854 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
NYX 0:85b3fd62ea1a 1855 #define CAN_MSR_SAMP_Pos (10U)
NYX 0:85b3fd62ea1a 1856 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1857 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
NYX 0:85b3fd62ea1a 1858 #define CAN_MSR_RX_Pos (11U)
NYX 0:85b3fd62ea1a 1859 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1860 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
NYX 0:85b3fd62ea1a 1861
NYX 0:85b3fd62ea1a 1862 /******************* Bit definition for CAN_TSR register ********************/
NYX 0:85b3fd62ea1a 1863 #define CAN_TSR_RQCP0_Pos (0U)
NYX 0:85b3fd62ea1a 1864 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1865 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
NYX 0:85b3fd62ea1a 1866 #define CAN_TSR_TXOK0_Pos (1U)
NYX 0:85b3fd62ea1a 1867 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1868 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
NYX 0:85b3fd62ea1a 1869 #define CAN_TSR_ALST0_Pos (2U)
NYX 0:85b3fd62ea1a 1870 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1871 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
NYX 0:85b3fd62ea1a 1872 #define CAN_TSR_TERR0_Pos (3U)
NYX 0:85b3fd62ea1a 1873 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1874 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
NYX 0:85b3fd62ea1a 1875 #define CAN_TSR_ABRQ0_Pos (7U)
NYX 0:85b3fd62ea1a 1876 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 1877 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
NYX 0:85b3fd62ea1a 1878 #define CAN_TSR_RQCP1_Pos (8U)
NYX 0:85b3fd62ea1a 1879 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1880 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
NYX 0:85b3fd62ea1a 1881 #define CAN_TSR_TXOK1_Pos (9U)
NYX 0:85b3fd62ea1a 1882 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1883 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
NYX 0:85b3fd62ea1a 1884 #define CAN_TSR_ALST1_Pos (10U)
NYX 0:85b3fd62ea1a 1885 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1886 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
NYX 0:85b3fd62ea1a 1887 #define CAN_TSR_TERR1_Pos (11U)
NYX 0:85b3fd62ea1a 1888 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1889 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
NYX 0:85b3fd62ea1a 1890 #define CAN_TSR_ABRQ1_Pos (15U)
NYX 0:85b3fd62ea1a 1891 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 1892 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
NYX 0:85b3fd62ea1a 1893 #define CAN_TSR_RQCP2_Pos (16U)
NYX 0:85b3fd62ea1a 1894 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 1895 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
NYX 0:85b3fd62ea1a 1896 #define CAN_TSR_TXOK2_Pos (17U)
NYX 0:85b3fd62ea1a 1897 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 1898 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
NYX 0:85b3fd62ea1a 1899 #define CAN_TSR_ALST2_Pos (18U)
NYX 0:85b3fd62ea1a 1900 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 1901 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
NYX 0:85b3fd62ea1a 1902 #define CAN_TSR_TERR2_Pos (19U)
NYX 0:85b3fd62ea1a 1903 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 1904 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
NYX 0:85b3fd62ea1a 1905 #define CAN_TSR_ABRQ2_Pos (23U)
NYX 0:85b3fd62ea1a 1906 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 1907 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
NYX 0:85b3fd62ea1a 1908 #define CAN_TSR_CODE_Pos (24U)
NYX 0:85b3fd62ea1a 1909 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
NYX 0:85b3fd62ea1a 1910 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
NYX 0:85b3fd62ea1a 1911
NYX 0:85b3fd62ea1a 1912 #define CAN_TSR_TME_Pos (26U)
NYX 0:85b3fd62ea1a 1913 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
NYX 0:85b3fd62ea1a 1914 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
NYX 0:85b3fd62ea1a 1915 #define CAN_TSR_TME0_Pos (26U)
NYX 0:85b3fd62ea1a 1916 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 1917 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
NYX 0:85b3fd62ea1a 1918 #define CAN_TSR_TME1_Pos (27U)
NYX 0:85b3fd62ea1a 1919 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 1920 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
NYX 0:85b3fd62ea1a 1921 #define CAN_TSR_TME2_Pos (28U)
NYX 0:85b3fd62ea1a 1922 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 1923 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
NYX 0:85b3fd62ea1a 1924
NYX 0:85b3fd62ea1a 1925 #define CAN_TSR_LOW_Pos (29U)
NYX 0:85b3fd62ea1a 1926 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
NYX 0:85b3fd62ea1a 1927 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
NYX 0:85b3fd62ea1a 1928 #define CAN_TSR_LOW0_Pos (29U)
NYX 0:85b3fd62ea1a 1929 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 1930 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
NYX 0:85b3fd62ea1a 1931 #define CAN_TSR_LOW1_Pos (30U)
NYX 0:85b3fd62ea1a 1932 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 1933 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
NYX 0:85b3fd62ea1a 1934 #define CAN_TSR_LOW2_Pos (31U)
NYX 0:85b3fd62ea1a 1935 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 1936 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
NYX 0:85b3fd62ea1a 1937
NYX 0:85b3fd62ea1a 1938 /******************* Bit definition for CAN_RF0R register *******************/
NYX 0:85b3fd62ea1a 1939 #define CAN_RF0R_FMP0_Pos (0U)
NYX 0:85b3fd62ea1a 1940 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 1941 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
NYX 0:85b3fd62ea1a 1942 #define CAN_RF0R_FULL0_Pos (3U)
NYX 0:85b3fd62ea1a 1943 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1944 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
NYX 0:85b3fd62ea1a 1945 #define CAN_RF0R_FOVR0_Pos (4U)
NYX 0:85b3fd62ea1a 1946 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1947 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
NYX 0:85b3fd62ea1a 1948 #define CAN_RF0R_RFOM0_Pos (5U)
NYX 0:85b3fd62ea1a 1949 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1950 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
NYX 0:85b3fd62ea1a 1951
NYX 0:85b3fd62ea1a 1952 /******************* Bit definition for CAN_RF1R register *******************/
NYX 0:85b3fd62ea1a 1953 #define CAN_RF1R_FMP1_Pos (0U)
NYX 0:85b3fd62ea1a 1954 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 1955 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
NYX 0:85b3fd62ea1a 1956 #define CAN_RF1R_FULL1_Pos (3U)
NYX 0:85b3fd62ea1a 1957 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1958 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
NYX 0:85b3fd62ea1a 1959 #define CAN_RF1R_FOVR1_Pos (4U)
NYX 0:85b3fd62ea1a 1960 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1961 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
NYX 0:85b3fd62ea1a 1962 #define CAN_RF1R_RFOM1_Pos (5U)
NYX 0:85b3fd62ea1a 1963 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1964 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
NYX 0:85b3fd62ea1a 1965
NYX 0:85b3fd62ea1a 1966 /******************** Bit definition for CAN_IER register *******************/
NYX 0:85b3fd62ea1a 1967 #define CAN_IER_TMEIE_Pos (0U)
NYX 0:85b3fd62ea1a 1968 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 1969 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
NYX 0:85b3fd62ea1a 1970 #define CAN_IER_FMPIE0_Pos (1U)
NYX 0:85b3fd62ea1a 1971 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 1972 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
NYX 0:85b3fd62ea1a 1973 #define CAN_IER_FFIE0_Pos (2U)
NYX 0:85b3fd62ea1a 1974 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 1975 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
NYX 0:85b3fd62ea1a 1976 #define CAN_IER_FOVIE0_Pos (3U)
NYX 0:85b3fd62ea1a 1977 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 1978 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
NYX 0:85b3fd62ea1a 1979 #define CAN_IER_FMPIE1_Pos (4U)
NYX 0:85b3fd62ea1a 1980 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 1981 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
NYX 0:85b3fd62ea1a 1982 #define CAN_IER_FFIE1_Pos (5U)
NYX 0:85b3fd62ea1a 1983 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 1984 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
NYX 0:85b3fd62ea1a 1985 #define CAN_IER_FOVIE1_Pos (6U)
NYX 0:85b3fd62ea1a 1986 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 1987 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
NYX 0:85b3fd62ea1a 1988 #define CAN_IER_EWGIE_Pos (8U)
NYX 0:85b3fd62ea1a 1989 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 1990 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
NYX 0:85b3fd62ea1a 1991 #define CAN_IER_EPVIE_Pos (9U)
NYX 0:85b3fd62ea1a 1992 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 1993 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
NYX 0:85b3fd62ea1a 1994 #define CAN_IER_BOFIE_Pos (10U)
NYX 0:85b3fd62ea1a 1995 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 1996 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
NYX 0:85b3fd62ea1a 1997 #define CAN_IER_LECIE_Pos (11U)
NYX 0:85b3fd62ea1a 1998 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 1999 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
NYX 0:85b3fd62ea1a 2000 #define CAN_IER_ERRIE_Pos (15U)
NYX 0:85b3fd62ea1a 2001 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 2002 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
NYX 0:85b3fd62ea1a 2003 #define CAN_IER_WKUIE_Pos (16U)
NYX 0:85b3fd62ea1a 2004 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 2005 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
NYX 0:85b3fd62ea1a 2006 #define CAN_IER_SLKIE_Pos (17U)
NYX 0:85b3fd62ea1a 2007 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 2008 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
NYX 0:85b3fd62ea1a 2009 #define CAN_IER_EWGIE_Pos (8U)
NYX 0:85b3fd62ea1a 2010
NYX 0:85b3fd62ea1a 2011 /******************** Bit definition for CAN_ESR register *******************/
NYX 0:85b3fd62ea1a 2012 #define CAN_ESR_EWGF_Pos (0U)
NYX 0:85b3fd62ea1a 2013 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2014 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
NYX 0:85b3fd62ea1a 2015 #define CAN_ESR_EPVF_Pos (1U)
NYX 0:85b3fd62ea1a 2016 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2017 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
NYX 0:85b3fd62ea1a 2018 #define CAN_ESR_BOFF_Pos (2U)
NYX 0:85b3fd62ea1a 2019 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2020 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
NYX 0:85b3fd62ea1a 2021
NYX 0:85b3fd62ea1a 2022 #define CAN_ESR_LEC_Pos (4U)
NYX 0:85b3fd62ea1a 2023 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 2024 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
NYX 0:85b3fd62ea1a 2025 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 2026 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 2027 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 2028
NYX 0:85b3fd62ea1a 2029 #define CAN_ESR_TEC_Pos (16U)
NYX 0:85b3fd62ea1a 2030 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2031 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
NYX 0:85b3fd62ea1a 2032 #define CAN_ESR_REC_Pos (24U)
NYX 0:85b3fd62ea1a 2033 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2034 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
NYX 0:85b3fd62ea1a 2035
NYX 0:85b3fd62ea1a 2036 /******************* Bit definition for CAN_BTR register ********************/
NYX 0:85b3fd62ea1a 2037 #define CAN_BTR_BRP_Pos (0U)
NYX 0:85b3fd62ea1a 2038 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
NYX 0:85b3fd62ea1a 2039 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
NYX 0:85b3fd62ea1a 2040 #define CAN_BTR_TS1_Pos (16U)
NYX 0:85b3fd62ea1a 2041 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 2042 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
NYX 0:85b3fd62ea1a 2043 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 2044 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 2045 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 2046 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 2047 #define CAN_BTR_TS2_Pos (20U)
NYX 0:85b3fd62ea1a 2048 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
NYX 0:85b3fd62ea1a 2049 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
NYX 0:85b3fd62ea1a 2050 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 2051 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 2052 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 2053 #define CAN_BTR_SJW_Pos (24U)
NYX 0:85b3fd62ea1a 2054 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
NYX 0:85b3fd62ea1a 2055 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
NYX 0:85b3fd62ea1a 2056 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 2057 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 2058 #define CAN_BTR_LBKM_Pos (30U)
NYX 0:85b3fd62ea1a 2059 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 2060 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
NYX 0:85b3fd62ea1a 2061 #define CAN_BTR_SILM_Pos (31U)
NYX 0:85b3fd62ea1a 2062 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 2063 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
NYX 0:85b3fd62ea1a 2064
NYX 0:85b3fd62ea1a 2065
NYX 0:85b3fd62ea1a 2066 /*!<Mailbox registers */
NYX 0:85b3fd62ea1a 2067 /****************** Bit definition for CAN_TI0R register ********************/
NYX 0:85b3fd62ea1a 2068 #define CAN_TI0R_TXRQ_Pos (0U)
NYX 0:85b3fd62ea1a 2069 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2070 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
NYX 0:85b3fd62ea1a 2071 #define CAN_TI0R_RTR_Pos (1U)
NYX 0:85b3fd62ea1a 2072 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2073 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
NYX 0:85b3fd62ea1a 2074 #define CAN_TI0R_IDE_Pos (2U)
NYX 0:85b3fd62ea1a 2075 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2076 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
NYX 0:85b3fd62ea1a 2077 #define CAN_TI0R_EXID_Pos (3U)
NYX 0:85b3fd62ea1a 2078 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
NYX 0:85b3fd62ea1a 2079 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
NYX 0:85b3fd62ea1a 2080 #define CAN_TI0R_STID_Pos (21U)
NYX 0:85b3fd62ea1a 2081 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
NYX 0:85b3fd62ea1a 2082 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
NYX 0:85b3fd62ea1a 2083
NYX 0:85b3fd62ea1a 2084 /****************** Bit definition for CAN_TDT0R register *******************/
NYX 0:85b3fd62ea1a 2085 #define CAN_TDT0R_DLC_Pos (0U)
NYX 0:85b3fd62ea1a 2086 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 2087 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
NYX 0:85b3fd62ea1a 2088 #define CAN_TDT0R_TGT_Pos (8U)
NYX 0:85b3fd62ea1a 2089 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2090 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
NYX 0:85b3fd62ea1a 2091 #define CAN_TDT0R_TIME_Pos (16U)
NYX 0:85b3fd62ea1a 2092 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 2093 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
NYX 0:85b3fd62ea1a 2094
NYX 0:85b3fd62ea1a 2095 /****************** Bit definition for CAN_TDL0R register *******************/
NYX 0:85b3fd62ea1a 2096 #define CAN_TDL0R_DATA0_Pos (0U)
NYX 0:85b3fd62ea1a 2097 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2098 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
NYX 0:85b3fd62ea1a 2099 #define CAN_TDL0R_DATA1_Pos (8U)
NYX 0:85b3fd62ea1a 2100 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2101 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
NYX 0:85b3fd62ea1a 2102 #define CAN_TDL0R_DATA2_Pos (16U)
NYX 0:85b3fd62ea1a 2103 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2104 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
NYX 0:85b3fd62ea1a 2105 #define CAN_TDL0R_DATA3_Pos (24U)
NYX 0:85b3fd62ea1a 2106 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2107 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
NYX 0:85b3fd62ea1a 2108
NYX 0:85b3fd62ea1a 2109 /****************** Bit definition for CAN_TDH0R register *******************/
NYX 0:85b3fd62ea1a 2110 #define CAN_TDH0R_DATA4_Pos (0U)
NYX 0:85b3fd62ea1a 2111 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2112 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
NYX 0:85b3fd62ea1a 2113 #define CAN_TDH0R_DATA5_Pos (8U)
NYX 0:85b3fd62ea1a 2114 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2115 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
NYX 0:85b3fd62ea1a 2116 #define CAN_TDH0R_DATA6_Pos (16U)
NYX 0:85b3fd62ea1a 2117 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2118 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
NYX 0:85b3fd62ea1a 2119 #define CAN_TDH0R_DATA7_Pos (24U)
NYX 0:85b3fd62ea1a 2120 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2121 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
NYX 0:85b3fd62ea1a 2122
NYX 0:85b3fd62ea1a 2123 /******************* Bit definition for CAN_TI1R register *******************/
NYX 0:85b3fd62ea1a 2124 #define CAN_TI1R_TXRQ_Pos (0U)
NYX 0:85b3fd62ea1a 2125 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2126 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
NYX 0:85b3fd62ea1a 2127 #define CAN_TI1R_RTR_Pos (1U)
NYX 0:85b3fd62ea1a 2128 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2129 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
NYX 0:85b3fd62ea1a 2130 #define CAN_TI1R_IDE_Pos (2U)
NYX 0:85b3fd62ea1a 2131 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2132 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
NYX 0:85b3fd62ea1a 2133 #define CAN_TI1R_EXID_Pos (3U)
NYX 0:85b3fd62ea1a 2134 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
NYX 0:85b3fd62ea1a 2135 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
NYX 0:85b3fd62ea1a 2136 #define CAN_TI1R_STID_Pos (21U)
NYX 0:85b3fd62ea1a 2137 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
NYX 0:85b3fd62ea1a 2138 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
NYX 0:85b3fd62ea1a 2139
NYX 0:85b3fd62ea1a 2140 /******************* Bit definition for CAN_TDT1R register ******************/
NYX 0:85b3fd62ea1a 2141 #define CAN_TDT1R_DLC_Pos (0U)
NYX 0:85b3fd62ea1a 2142 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 2143 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
NYX 0:85b3fd62ea1a 2144 #define CAN_TDT1R_TGT_Pos (8U)
NYX 0:85b3fd62ea1a 2145 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2146 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
NYX 0:85b3fd62ea1a 2147 #define CAN_TDT1R_TIME_Pos (16U)
NYX 0:85b3fd62ea1a 2148 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 2149 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
NYX 0:85b3fd62ea1a 2150
NYX 0:85b3fd62ea1a 2151 /******************* Bit definition for CAN_TDL1R register ******************/
NYX 0:85b3fd62ea1a 2152 #define CAN_TDL1R_DATA0_Pos (0U)
NYX 0:85b3fd62ea1a 2153 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2154 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
NYX 0:85b3fd62ea1a 2155 #define CAN_TDL1R_DATA1_Pos (8U)
NYX 0:85b3fd62ea1a 2156 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2157 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
NYX 0:85b3fd62ea1a 2158 #define CAN_TDL1R_DATA2_Pos (16U)
NYX 0:85b3fd62ea1a 2159 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2160 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
NYX 0:85b3fd62ea1a 2161 #define CAN_TDL1R_DATA3_Pos (24U)
NYX 0:85b3fd62ea1a 2162 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2163 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
NYX 0:85b3fd62ea1a 2164
NYX 0:85b3fd62ea1a 2165 /******************* Bit definition for CAN_TDH1R register ******************/
NYX 0:85b3fd62ea1a 2166 #define CAN_TDH1R_DATA4_Pos (0U)
NYX 0:85b3fd62ea1a 2167 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2168 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
NYX 0:85b3fd62ea1a 2169 #define CAN_TDH1R_DATA5_Pos (8U)
NYX 0:85b3fd62ea1a 2170 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2171 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
NYX 0:85b3fd62ea1a 2172 #define CAN_TDH1R_DATA6_Pos (16U)
NYX 0:85b3fd62ea1a 2173 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2174 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
NYX 0:85b3fd62ea1a 2175 #define CAN_TDH1R_DATA7_Pos (24U)
NYX 0:85b3fd62ea1a 2176 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2177 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
NYX 0:85b3fd62ea1a 2178
NYX 0:85b3fd62ea1a 2179 /******************* Bit definition for CAN_TI2R register *******************/
NYX 0:85b3fd62ea1a 2180 #define CAN_TI2R_TXRQ_Pos (0U)
NYX 0:85b3fd62ea1a 2181 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2182 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
NYX 0:85b3fd62ea1a 2183 #define CAN_TI2R_RTR_Pos (1U)
NYX 0:85b3fd62ea1a 2184 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2185 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
NYX 0:85b3fd62ea1a 2186 #define CAN_TI2R_IDE_Pos (2U)
NYX 0:85b3fd62ea1a 2187 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2188 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
NYX 0:85b3fd62ea1a 2189 #define CAN_TI2R_EXID_Pos (3U)
NYX 0:85b3fd62ea1a 2190 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
NYX 0:85b3fd62ea1a 2191 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
NYX 0:85b3fd62ea1a 2192 #define CAN_TI2R_STID_Pos (21U)
NYX 0:85b3fd62ea1a 2193 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
NYX 0:85b3fd62ea1a 2194 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
NYX 0:85b3fd62ea1a 2195
NYX 0:85b3fd62ea1a 2196 /******************* Bit definition for CAN_TDT2R register ******************/
NYX 0:85b3fd62ea1a 2197 #define CAN_TDT2R_DLC_Pos (0U)
NYX 0:85b3fd62ea1a 2198 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 2199 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
NYX 0:85b3fd62ea1a 2200 #define CAN_TDT2R_TGT_Pos (8U)
NYX 0:85b3fd62ea1a 2201 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2202 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
NYX 0:85b3fd62ea1a 2203 #define CAN_TDT2R_TIME_Pos (16U)
NYX 0:85b3fd62ea1a 2204 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 2205 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
NYX 0:85b3fd62ea1a 2206
NYX 0:85b3fd62ea1a 2207 /******************* Bit definition for CAN_TDL2R register ******************/
NYX 0:85b3fd62ea1a 2208 #define CAN_TDL2R_DATA0_Pos (0U)
NYX 0:85b3fd62ea1a 2209 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2210 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
NYX 0:85b3fd62ea1a 2211 #define CAN_TDL2R_DATA1_Pos (8U)
NYX 0:85b3fd62ea1a 2212 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2213 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
NYX 0:85b3fd62ea1a 2214 #define CAN_TDL2R_DATA2_Pos (16U)
NYX 0:85b3fd62ea1a 2215 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2216 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
NYX 0:85b3fd62ea1a 2217 #define CAN_TDL2R_DATA3_Pos (24U)
NYX 0:85b3fd62ea1a 2218 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2219 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
NYX 0:85b3fd62ea1a 2220
NYX 0:85b3fd62ea1a 2221 /******************* Bit definition for CAN_TDH2R register ******************/
NYX 0:85b3fd62ea1a 2222 #define CAN_TDH2R_DATA4_Pos (0U)
NYX 0:85b3fd62ea1a 2223 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2224 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
NYX 0:85b3fd62ea1a 2225 #define CAN_TDH2R_DATA5_Pos (8U)
NYX 0:85b3fd62ea1a 2226 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2227 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
NYX 0:85b3fd62ea1a 2228 #define CAN_TDH2R_DATA6_Pos (16U)
NYX 0:85b3fd62ea1a 2229 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2230 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
NYX 0:85b3fd62ea1a 2231 #define CAN_TDH2R_DATA7_Pos (24U)
NYX 0:85b3fd62ea1a 2232 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2233 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
NYX 0:85b3fd62ea1a 2234
NYX 0:85b3fd62ea1a 2235 /******************* Bit definition for CAN_RI0R register *******************/
NYX 0:85b3fd62ea1a 2236 #define CAN_RI0R_RTR_Pos (1U)
NYX 0:85b3fd62ea1a 2237 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2238 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
NYX 0:85b3fd62ea1a 2239 #define CAN_RI0R_IDE_Pos (2U)
NYX 0:85b3fd62ea1a 2240 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2241 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
NYX 0:85b3fd62ea1a 2242 #define CAN_RI0R_EXID_Pos (3U)
NYX 0:85b3fd62ea1a 2243 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
NYX 0:85b3fd62ea1a 2244 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
NYX 0:85b3fd62ea1a 2245 #define CAN_RI0R_STID_Pos (21U)
NYX 0:85b3fd62ea1a 2246 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
NYX 0:85b3fd62ea1a 2247 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
NYX 0:85b3fd62ea1a 2248
NYX 0:85b3fd62ea1a 2249 /******************* Bit definition for CAN_RDT0R register ******************/
NYX 0:85b3fd62ea1a 2250 #define CAN_RDT0R_DLC_Pos (0U)
NYX 0:85b3fd62ea1a 2251 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 2252 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
NYX 0:85b3fd62ea1a 2253 #define CAN_RDT0R_FMI_Pos (8U)
NYX 0:85b3fd62ea1a 2254 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2255 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
NYX 0:85b3fd62ea1a 2256 #define CAN_RDT0R_TIME_Pos (16U)
NYX 0:85b3fd62ea1a 2257 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 2258 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
NYX 0:85b3fd62ea1a 2259
NYX 0:85b3fd62ea1a 2260 /******************* Bit definition for CAN_RDL0R register ******************/
NYX 0:85b3fd62ea1a 2261 #define CAN_RDL0R_DATA0_Pos (0U)
NYX 0:85b3fd62ea1a 2262 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2263 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
NYX 0:85b3fd62ea1a 2264 #define CAN_RDL0R_DATA1_Pos (8U)
NYX 0:85b3fd62ea1a 2265 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2266 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
NYX 0:85b3fd62ea1a 2267 #define CAN_RDL0R_DATA2_Pos (16U)
NYX 0:85b3fd62ea1a 2268 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2269 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
NYX 0:85b3fd62ea1a 2270 #define CAN_RDL0R_DATA3_Pos (24U)
NYX 0:85b3fd62ea1a 2271 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2272 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
NYX 0:85b3fd62ea1a 2273
NYX 0:85b3fd62ea1a 2274 /******************* Bit definition for CAN_RDH0R register ******************/
NYX 0:85b3fd62ea1a 2275 #define CAN_RDH0R_DATA4_Pos (0U)
NYX 0:85b3fd62ea1a 2276 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2277 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
NYX 0:85b3fd62ea1a 2278 #define CAN_RDH0R_DATA5_Pos (8U)
NYX 0:85b3fd62ea1a 2279 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2280 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
NYX 0:85b3fd62ea1a 2281 #define CAN_RDH0R_DATA6_Pos (16U)
NYX 0:85b3fd62ea1a 2282 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2283 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
NYX 0:85b3fd62ea1a 2284 #define CAN_RDH0R_DATA7_Pos (24U)
NYX 0:85b3fd62ea1a 2285 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2286 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
NYX 0:85b3fd62ea1a 2287
NYX 0:85b3fd62ea1a 2288 /******************* Bit definition for CAN_RI1R register *******************/
NYX 0:85b3fd62ea1a 2289 #define CAN_RI1R_RTR_Pos (1U)
NYX 0:85b3fd62ea1a 2290 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2291 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
NYX 0:85b3fd62ea1a 2292 #define CAN_RI1R_IDE_Pos (2U)
NYX 0:85b3fd62ea1a 2293 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2294 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
NYX 0:85b3fd62ea1a 2295 #define CAN_RI1R_EXID_Pos (3U)
NYX 0:85b3fd62ea1a 2296 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
NYX 0:85b3fd62ea1a 2297 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
NYX 0:85b3fd62ea1a 2298 #define CAN_RI1R_STID_Pos (21U)
NYX 0:85b3fd62ea1a 2299 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
NYX 0:85b3fd62ea1a 2300 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
NYX 0:85b3fd62ea1a 2301
NYX 0:85b3fd62ea1a 2302 /******************* Bit definition for CAN_RDT1R register ******************/
NYX 0:85b3fd62ea1a 2303 #define CAN_RDT1R_DLC_Pos (0U)
NYX 0:85b3fd62ea1a 2304 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 2305 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
NYX 0:85b3fd62ea1a 2306 #define CAN_RDT1R_FMI_Pos (8U)
NYX 0:85b3fd62ea1a 2307 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2308 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
NYX 0:85b3fd62ea1a 2309 #define CAN_RDT1R_TIME_Pos (16U)
NYX 0:85b3fd62ea1a 2310 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 2311 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
NYX 0:85b3fd62ea1a 2312
NYX 0:85b3fd62ea1a 2313 /******************* Bit definition for CAN_RDL1R register ******************/
NYX 0:85b3fd62ea1a 2314 #define CAN_RDL1R_DATA0_Pos (0U)
NYX 0:85b3fd62ea1a 2315 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2316 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
NYX 0:85b3fd62ea1a 2317 #define CAN_RDL1R_DATA1_Pos (8U)
NYX 0:85b3fd62ea1a 2318 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2319 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
NYX 0:85b3fd62ea1a 2320 #define CAN_RDL1R_DATA2_Pos (16U)
NYX 0:85b3fd62ea1a 2321 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2322 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
NYX 0:85b3fd62ea1a 2323 #define CAN_RDL1R_DATA3_Pos (24U)
NYX 0:85b3fd62ea1a 2324 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2325 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
NYX 0:85b3fd62ea1a 2326
NYX 0:85b3fd62ea1a 2327 /******************* Bit definition for CAN_RDH1R register ******************/
NYX 0:85b3fd62ea1a 2328 #define CAN_RDH1R_DATA4_Pos (0U)
NYX 0:85b3fd62ea1a 2329 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 2330 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
NYX 0:85b3fd62ea1a 2331 #define CAN_RDH1R_DATA5_Pos (8U)
NYX 0:85b3fd62ea1a 2332 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 2333 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
NYX 0:85b3fd62ea1a 2334 #define CAN_RDH1R_DATA6_Pos (16U)
NYX 0:85b3fd62ea1a 2335 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 2336 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
NYX 0:85b3fd62ea1a 2337 #define CAN_RDH1R_DATA7_Pos (24U)
NYX 0:85b3fd62ea1a 2338 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 2339 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
NYX 0:85b3fd62ea1a 2340
NYX 0:85b3fd62ea1a 2341 /*!<CAN filter registers */
NYX 0:85b3fd62ea1a 2342 /******************* Bit definition for CAN_FMR register ********************/
NYX 0:85b3fd62ea1a 2343 #define CAN_FMR_FINIT_Pos (0U)
NYX 0:85b3fd62ea1a 2344 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2345 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
NYX 0:85b3fd62ea1a 2346 #define CAN_FMR_CAN2SB_Pos (8U)
NYX 0:85b3fd62ea1a 2347 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
NYX 0:85b3fd62ea1a 2348 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
NYX 0:85b3fd62ea1a 2349
NYX 0:85b3fd62ea1a 2350 /******************* Bit definition for CAN_FM1R register *******************/
NYX 0:85b3fd62ea1a 2351 #define CAN_FM1R_FBM_Pos (0U)
NYX 0:85b3fd62ea1a 2352 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
NYX 0:85b3fd62ea1a 2353 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
NYX 0:85b3fd62ea1a 2354 #define CAN_FM1R_FBM0_Pos (0U)
NYX 0:85b3fd62ea1a 2355 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2356 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
NYX 0:85b3fd62ea1a 2357 #define CAN_FM1R_FBM1_Pos (1U)
NYX 0:85b3fd62ea1a 2358 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2359 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
NYX 0:85b3fd62ea1a 2360 #define CAN_FM1R_FBM2_Pos (2U)
NYX 0:85b3fd62ea1a 2361 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2362 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
NYX 0:85b3fd62ea1a 2363 #define CAN_FM1R_FBM3_Pos (3U)
NYX 0:85b3fd62ea1a 2364 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 2365 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
NYX 0:85b3fd62ea1a 2366 #define CAN_FM1R_FBM4_Pos (4U)
NYX 0:85b3fd62ea1a 2367 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 2368 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
NYX 0:85b3fd62ea1a 2369 #define CAN_FM1R_FBM5_Pos (5U)
NYX 0:85b3fd62ea1a 2370 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 2371 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
NYX 0:85b3fd62ea1a 2372 #define CAN_FM1R_FBM6_Pos (6U)
NYX 0:85b3fd62ea1a 2373 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 2374 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
NYX 0:85b3fd62ea1a 2375 #define CAN_FM1R_FBM7_Pos (7U)
NYX 0:85b3fd62ea1a 2376 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 2377 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
NYX 0:85b3fd62ea1a 2378 #define CAN_FM1R_FBM8_Pos (8U)
NYX 0:85b3fd62ea1a 2379 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2380 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
NYX 0:85b3fd62ea1a 2381 #define CAN_FM1R_FBM9_Pos (9U)
NYX 0:85b3fd62ea1a 2382 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 2383 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
NYX 0:85b3fd62ea1a 2384 #define CAN_FM1R_FBM10_Pos (10U)
NYX 0:85b3fd62ea1a 2385 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 2386 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
NYX 0:85b3fd62ea1a 2387 #define CAN_FM1R_FBM11_Pos (11U)
NYX 0:85b3fd62ea1a 2388 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 2389 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
NYX 0:85b3fd62ea1a 2390 #define CAN_FM1R_FBM12_Pos (12U)
NYX 0:85b3fd62ea1a 2391 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 2392 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
NYX 0:85b3fd62ea1a 2393 #define CAN_FM1R_FBM13_Pos (13U)
NYX 0:85b3fd62ea1a 2394 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 2395 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
NYX 0:85b3fd62ea1a 2396 #define CAN_FM1R_FBM14_Pos (14U)
NYX 0:85b3fd62ea1a 2397 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 2398 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
NYX 0:85b3fd62ea1a 2399 #define CAN_FM1R_FBM15_Pos (15U)
NYX 0:85b3fd62ea1a 2400 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 2401 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
NYX 0:85b3fd62ea1a 2402 #define CAN_FM1R_FBM16_Pos (16U)
NYX 0:85b3fd62ea1a 2403 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 2404 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
NYX 0:85b3fd62ea1a 2405 #define CAN_FM1R_FBM17_Pos (17U)
NYX 0:85b3fd62ea1a 2406 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 2407 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
NYX 0:85b3fd62ea1a 2408 #define CAN_FM1R_FBM18_Pos (18U)
NYX 0:85b3fd62ea1a 2409 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 2410 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
NYX 0:85b3fd62ea1a 2411 #define CAN_FM1R_FBM19_Pos (19U)
NYX 0:85b3fd62ea1a 2412 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 2413 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
NYX 0:85b3fd62ea1a 2414 #define CAN_FM1R_FBM20_Pos (20U)
NYX 0:85b3fd62ea1a 2415 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 2416 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
NYX 0:85b3fd62ea1a 2417 #define CAN_FM1R_FBM21_Pos (21U)
NYX 0:85b3fd62ea1a 2418 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 2419 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
NYX 0:85b3fd62ea1a 2420 #define CAN_FM1R_FBM22_Pos (22U)
NYX 0:85b3fd62ea1a 2421 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 2422 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
NYX 0:85b3fd62ea1a 2423 #define CAN_FM1R_FBM23_Pos (23U)
NYX 0:85b3fd62ea1a 2424 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 2425 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
NYX 0:85b3fd62ea1a 2426 #define CAN_FM1R_FBM24_Pos (24U)
NYX 0:85b3fd62ea1a 2427 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 2428 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
NYX 0:85b3fd62ea1a 2429 #define CAN_FM1R_FBM25_Pos (25U)
NYX 0:85b3fd62ea1a 2430 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 2431 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
NYX 0:85b3fd62ea1a 2432 #define CAN_FM1R_FBM26_Pos (26U)
NYX 0:85b3fd62ea1a 2433 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 2434 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
NYX 0:85b3fd62ea1a 2435 #define CAN_FM1R_FBM27_Pos (27U)
NYX 0:85b3fd62ea1a 2436 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 2437 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
NYX 0:85b3fd62ea1a 2438
NYX 0:85b3fd62ea1a 2439 /******************* Bit definition for CAN_FS1R register *******************/
NYX 0:85b3fd62ea1a 2440 #define CAN_FS1R_FSC_Pos (0U)
NYX 0:85b3fd62ea1a 2441 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
NYX 0:85b3fd62ea1a 2442 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
NYX 0:85b3fd62ea1a 2443 #define CAN_FS1R_FSC0_Pos (0U)
NYX 0:85b3fd62ea1a 2444 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2445 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
NYX 0:85b3fd62ea1a 2446 #define CAN_FS1R_FSC1_Pos (1U)
NYX 0:85b3fd62ea1a 2447 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2448 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
NYX 0:85b3fd62ea1a 2449 #define CAN_FS1R_FSC2_Pos (2U)
NYX 0:85b3fd62ea1a 2450 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2451 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
NYX 0:85b3fd62ea1a 2452 #define CAN_FS1R_FSC3_Pos (3U)
NYX 0:85b3fd62ea1a 2453 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 2454 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
NYX 0:85b3fd62ea1a 2455 #define CAN_FS1R_FSC4_Pos (4U)
NYX 0:85b3fd62ea1a 2456 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 2457 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
NYX 0:85b3fd62ea1a 2458 #define CAN_FS1R_FSC5_Pos (5U)
NYX 0:85b3fd62ea1a 2459 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 2460 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
NYX 0:85b3fd62ea1a 2461 #define CAN_FS1R_FSC6_Pos (6U)
NYX 0:85b3fd62ea1a 2462 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 2463 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
NYX 0:85b3fd62ea1a 2464 #define CAN_FS1R_FSC7_Pos (7U)
NYX 0:85b3fd62ea1a 2465 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 2466 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
NYX 0:85b3fd62ea1a 2467 #define CAN_FS1R_FSC8_Pos (8U)
NYX 0:85b3fd62ea1a 2468 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2469 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
NYX 0:85b3fd62ea1a 2470 #define CAN_FS1R_FSC9_Pos (9U)
NYX 0:85b3fd62ea1a 2471 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 2472 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
NYX 0:85b3fd62ea1a 2473 #define CAN_FS1R_FSC10_Pos (10U)
NYX 0:85b3fd62ea1a 2474 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 2475 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
NYX 0:85b3fd62ea1a 2476 #define CAN_FS1R_FSC11_Pos (11U)
NYX 0:85b3fd62ea1a 2477 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 2478 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
NYX 0:85b3fd62ea1a 2479 #define CAN_FS1R_FSC12_Pos (12U)
NYX 0:85b3fd62ea1a 2480 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 2481 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
NYX 0:85b3fd62ea1a 2482 #define CAN_FS1R_FSC13_Pos (13U)
NYX 0:85b3fd62ea1a 2483 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 2484 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
NYX 0:85b3fd62ea1a 2485 #define CAN_FS1R_FSC14_Pos (14U)
NYX 0:85b3fd62ea1a 2486 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 2487 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
NYX 0:85b3fd62ea1a 2488 #define CAN_FS1R_FSC15_Pos (15U)
NYX 0:85b3fd62ea1a 2489 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 2490 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
NYX 0:85b3fd62ea1a 2491 #define CAN_FS1R_FSC16_Pos (16U)
NYX 0:85b3fd62ea1a 2492 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 2493 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
NYX 0:85b3fd62ea1a 2494 #define CAN_FS1R_FSC17_Pos (17U)
NYX 0:85b3fd62ea1a 2495 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 2496 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
NYX 0:85b3fd62ea1a 2497 #define CAN_FS1R_FSC18_Pos (18U)
NYX 0:85b3fd62ea1a 2498 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 2499 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
NYX 0:85b3fd62ea1a 2500 #define CAN_FS1R_FSC19_Pos (19U)
NYX 0:85b3fd62ea1a 2501 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 2502 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
NYX 0:85b3fd62ea1a 2503 #define CAN_FS1R_FSC20_Pos (20U)
NYX 0:85b3fd62ea1a 2504 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 2505 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
NYX 0:85b3fd62ea1a 2506 #define CAN_FS1R_FSC21_Pos (21U)
NYX 0:85b3fd62ea1a 2507 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 2508 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
NYX 0:85b3fd62ea1a 2509 #define CAN_FS1R_FSC22_Pos (22U)
NYX 0:85b3fd62ea1a 2510 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 2511 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
NYX 0:85b3fd62ea1a 2512 #define CAN_FS1R_FSC23_Pos (23U)
NYX 0:85b3fd62ea1a 2513 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 2514 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
NYX 0:85b3fd62ea1a 2515 #define CAN_FS1R_FSC24_Pos (24U)
NYX 0:85b3fd62ea1a 2516 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 2517 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
NYX 0:85b3fd62ea1a 2518 #define CAN_FS1R_FSC25_Pos (25U)
NYX 0:85b3fd62ea1a 2519 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 2520 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
NYX 0:85b3fd62ea1a 2521 #define CAN_FS1R_FSC26_Pos (26U)
NYX 0:85b3fd62ea1a 2522 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 2523 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
NYX 0:85b3fd62ea1a 2524 #define CAN_FS1R_FSC27_Pos (27U)
NYX 0:85b3fd62ea1a 2525 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 2526 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
NYX 0:85b3fd62ea1a 2527
NYX 0:85b3fd62ea1a 2528 /****************** Bit definition for CAN_FFA1R register *******************/
NYX 0:85b3fd62ea1a 2529 #define CAN_FFA1R_FFA_Pos (0U)
NYX 0:85b3fd62ea1a 2530 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
NYX 0:85b3fd62ea1a 2531 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
NYX 0:85b3fd62ea1a 2532 #define CAN_FFA1R_FFA0_Pos (0U)
NYX 0:85b3fd62ea1a 2533 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2534 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
NYX 0:85b3fd62ea1a 2535 #define CAN_FFA1R_FFA1_Pos (1U)
NYX 0:85b3fd62ea1a 2536 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2537 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
NYX 0:85b3fd62ea1a 2538 #define CAN_FFA1R_FFA2_Pos (2U)
NYX 0:85b3fd62ea1a 2539 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2540 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
NYX 0:85b3fd62ea1a 2541 #define CAN_FFA1R_FFA3_Pos (3U)
NYX 0:85b3fd62ea1a 2542 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 2543 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
NYX 0:85b3fd62ea1a 2544 #define CAN_FFA1R_FFA4_Pos (4U)
NYX 0:85b3fd62ea1a 2545 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 2546 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
NYX 0:85b3fd62ea1a 2547 #define CAN_FFA1R_FFA5_Pos (5U)
NYX 0:85b3fd62ea1a 2548 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 2549 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
NYX 0:85b3fd62ea1a 2550 #define CAN_FFA1R_FFA6_Pos (6U)
NYX 0:85b3fd62ea1a 2551 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 2552 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
NYX 0:85b3fd62ea1a 2553 #define CAN_FFA1R_FFA7_Pos (7U)
NYX 0:85b3fd62ea1a 2554 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 2555 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
NYX 0:85b3fd62ea1a 2556 #define CAN_FFA1R_FFA8_Pos (8U)
NYX 0:85b3fd62ea1a 2557 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2558 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
NYX 0:85b3fd62ea1a 2559 #define CAN_FFA1R_FFA9_Pos (9U)
NYX 0:85b3fd62ea1a 2560 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 2561 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
NYX 0:85b3fd62ea1a 2562 #define CAN_FFA1R_FFA10_Pos (10U)
NYX 0:85b3fd62ea1a 2563 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 2564 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
NYX 0:85b3fd62ea1a 2565 #define CAN_FFA1R_FFA11_Pos (11U)
NYX 0:85b3fd62ea1a 2566 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 2567 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
NYX 0:85b3fd62ea1a 2568 #define CAN_FFA1R_FFA12_Pos (12U)
NYX 0:85b3fd62ea1a 2569 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 2570 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
NYX 0:85b3fd62ea1a 2571 #define CAN_FFA1R_FFA13_Pos (13U)
NYX 0:85b3fd62ea1a 2572 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 2573 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
NYX 0:85b3fd62ea1a 2574 #define CAN_FFA1R_FFA14_Pos (14U)
NYX 0:85b3fd62ea1a 2575 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 2576 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
NYX 0:85b3fd62ea1a 2577 #define CAN_FFA1R_FFA15_Pos (15U)
NYX 0:85b3fd62ea1a 2578 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 2579 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
NYX 0:85b3fd62ea1a 2580 #define CAN_FFA1R_FFA16_Pos (16U)
NYX 0:85b3fd62ea1a 2581 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 2582 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
NYX 0:85b3fd62ea1a 2583 #define CAN_FFA1R_FFA17_Pos (17U)
NYX 0:85b3fd62ea1a 2584 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 2585 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
NYX 0:85b3fd62ea1a 2586 #define CAN_FFA1R_FFA18_Pos (18U)
NYX 0:85b3fd62ea1a 2587 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 2588 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
NYX 0:85b3fd62ea1a 2589 #define CAN_FFA1R_FFA19_Pos (19U)
NYX 0:85b3fd62ea1a 2590 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 2591 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
NYX 0:85b3fd62ea1a 2592 #define CAN_FFA1R_FFA20_Pos (20U)
NYX 0:85b3fd62ea1a 2593 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 2594 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
NYX 0:85b3fd62ea1a 2595 #define CAN_FFA1R_FFA21_Pos (21U)
NYX 0:85b3fd62ea1a 2596 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 2597 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
NYX 0:85b3fd62ea1a 2598 #define CAN_FFA1R_FFA22_Pos (22U)
NYX 0:85b3fd62ea1a 2599 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 2600 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
NYX 0:85b3fd62ea1a 2601 #define CAN_FFA1R_FFA23_Pos (23U)
NYX 0:85b3fd62ea1a 2602 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 2603 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
NYX 0:85b3fd62ea1a 2604 #define CAN_FFA1R_FFA24_Pos (24U)
NYX 0:85b3fd62ea1a 2605 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 2606 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
NYX 0:85b3fd62ea1a 2607 #define CAN_FFA1R_FFA25_Pos (25U)
NYX 0:85b3fd62ea1a 2608 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 2609 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
NYX 0:85b3fd62ea1a 2610 #define CAN_FFA1R_FFA26_Pos (26U)
NYX 0:85b3fd62ea1a 2611 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 2612 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
NYX 0:85b3fd62ea1a 2613 #define CAN_FFA1R_FFA27_Pos (27U)
NYX 0:85b3fd62ea1a 2614 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 2615 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
NYX 0:85b3fd62ea1a 2616
NYX 0:85b3fd62ea1a 2617 /******************* Bit definition for CAN_FA1R register *******************/
NYX 0:85b3fd62ea1a 2618 #define CAN_FA1R_FACT_Pos (0U)
NYX 0:85b3fd62ea1a 2619 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
NYX 0:85b3fd62ea1a 2620 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
NYX 0:85b3fd62ea1a 2621 #define CAN_FA1R_FACT0_Pos (0U)
NYX 0:85b3fd62ea1a 2622 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2623 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
NYX 0:85b3fd62ea1a 2624 #define CAN_FA1R_FACT1_Pos (1U)
NYX 0:85b3fd62ea1a 2625 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2626 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
NYX 0:85b3fd62ea1a 2627 #define CAN_FA1R_FACT2_Pos (2U)
NYX 0:85b3fd62ea1a 2628 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2629 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
NYX 0:85b3fd62ea1a 2630 #define CAN_FA1R_FACT3_Pos (3U)
NYX 0:85b3fd62ea1a 2631 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 2632 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
NYX 0:85b3fd62ea1a 2633 #define CAN_FA1R_FACT4_Pos (4U)
NYX 0:85b3fd62ea1a 2634 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 2635 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
NYX 0:85b3fd62ea1a 2636 #define CAN_FA1R_FACT5_Pos (5U)
NYX 0:85b3fd62ea1a 2637 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 2638 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
NYX 0:85b3fd62ea1a 2639 #define CAN_FA1R_FACT6_Pos (6U)
NYX 0:85b3fd62ea1a 2640 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 2641 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
NYX 0:85b3fd62ea1a 2642 #define CAN_FA1R_FACT7_Pos (7U)
NYX 0:85b3fd62ea1a 2643 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 2644 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
NYX 0:85b3fd62ea1a 2645 #define CAN_FA1R_FACT8_Pos (8U)
NYX 0:85b3fd62ea1a 2646 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2647 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
NYX 0:85b3fd62ea1a 2648 #define CAN_FA1R_FACT9_Pos (9U)
NYX 0:85b3fd62ea1a 2649 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 2650 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
NYX 0:85b3fd62ea1a 2651 #define CAN_FA1R_FACT10_Pos (10U)
NYX 0:85b3fd62ea1a 2652 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 2653 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
NYX 0:85b3fd62ea1a 2654 #define CAN_FA1R_FACT11_Pos (11U)
NYX 0:85b3fd62ea1a 2655 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 2656 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
NYX 0:85b3fd62ea1a 2657 #define CAN_FA1R_FACT12_Pos (12U)
NYX 0:85b3fd62ea1a 2658 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 2659 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
NYX 0:85b3fd62ea1a 2660 #define CAN_FA1R_FACT13_Pos (13U)
NYX 0:85b3fd62ea1a 2661 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 2662 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
NYX 0:85b3fd62ea1a 2663 #define CAN_FA1R_FACT14_Pos (14U)
NYX 0:85b3fd62ea1a 2664 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 2665 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
NYX 0:85b3fd62ea1a 2666 #define CAN_FA1R_FACT15_Pos (15U)
NYX 0:85b3fd62ea1a 2667 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 2668 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
NYX 0:85b3fd62ea1a 2669 #define CAN_FA1R_FACT16_Pos (16U)
NYX 0:85b3fd62ea1a 2670 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 2671 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
NYX 0:85b3fd62ea1a 2672 #define CAN_FA1R_FACT17_Pos (17U)
NYX 0:85b3fd62ea1a 2673 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 2674 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
NYX 0:85b3fd62ea1a 2675 #define CAN_FA1R_FACT18_Pos (18U)
NYX 0:85b3fd62ea1a 2676 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 2677 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
NYX 0:85b3fd62ea1a 2678 #define CAN_FA1R_FACT19_Pos (19U)
NYX 0:85b3fd62ea1a 2679 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 2680 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
NYX 0:85b3fd62ea1a 2681 #define CAN_FA1R_FACT20_Pos (20U)
NYX 0:85b3fd62ea1a 2682 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 2683 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
NYX 0:85b3fd62ea1a 2684 #define CAN_FA1R_FACT21_Pos (21U)
NYX 0:85b3fd62ea1a 2685 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 2686 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
NYX 0:85b3fd62ea1a 2687 #define CAN_FA1R_FACT22_Pos (22U)
NYX 0:85b3fd62ea1a 2688 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 2689 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
NYX 0:85b3fd62ea1a 2690 #define CAN_FA1R_FACT23_Pos (23U)
NYX 0:85b3fd62ea1a 2691 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 2692 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
NYX 0:85b3fd62ea1a 2693 #define CAN_FA1R_FACT24_Pos (24U)
NYX 0:85b3fd62ea1a 2694 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 2695 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
NYX 0:85b3fd62ea1a 2696 #define CAN_FA1R_FACT25_Pos (25U)
NYX 0:85b3fd62ea1a 2697 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 2698 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
NYX 0:85b3fd62ea1a 2699 #define CAN_FA1R_FACT26_Pos (26U)
NYX 0:85b3fd62ea1a 2700 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 2701 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
NYX 0:85b3fd62ea1a 2702 #define CAN_FA1R_FACT27_Pos (27U)
NYX 0:85b3fd62ea1a 2703 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 2704 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
NYX 0:85b3fd62ea1a 2705
NYX 0:85b3fd62ea1a 2706
NYX 0:85b3fd62ea1a 2707 /******************* Bit definition for CAN_F0R1 register *******************/
NYX 0:85b3fd62ea1a 2708 #define CAN_F0R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 2709 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2710 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 2711 #define CAN_F0R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 2712 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2713 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 2714 #define CAN_F0R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 2715 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2716 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 2717 #define CAN_F0R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 2718 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 2719 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 2720 #define CAN_F0R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 2721 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 2722 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 2723 #define CAN_F0R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 2724 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 2725 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 2726 #define CAN_F0R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 2727 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 2728 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 2729 #define CAN_F0R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 2730 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 2731 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 2732 #define CAN_F0R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 2733 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2734 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 2735 #define CAN_F0R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 2736 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 2737 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 2738 #define CAN_F0R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 2739 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 2740 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 2741 #define CAN_F0R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 2742 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 2743 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 2744 #define CAN_F0R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 2745 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 2746 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 2747 #define CAN_F0R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 2748 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 2749 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 2750 #define CAN_F0R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 2751 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 2752 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 2753 #define CAN_F0R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 2754 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 2755 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 2756 #define CAN_F0R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 2757 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 2758 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 2759 #define CAN_F0R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 2760 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 2761 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 2762 #define CAN_F0R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 2763 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 2764 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 2765 #define CAN_F0R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 2766 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 2767 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 2768 #define CAN_F0R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 2769 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 2770 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 2771 #define CAN_F0R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 2772 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 2773 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 2774 #define CAN_F0R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 2775 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 2776 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 2777 #define CAN_F0R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 2778 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 2779 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 2780 #define CAN_F0R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 2781 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 2782 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 2783 #define CAN_F0R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 2784 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 2785 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 2786 #define CAN_F0R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 2787 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 2788 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 2789 #define CAN_F0R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 2790 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 2791 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 2792 #define CAN_F0R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 2793 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 2794 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 2795 #define CAN_F0R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 2796 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 2797 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 2798 #define CAN_F0R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 2799 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 2800 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 2801 #define CAN_F0R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 2802 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 2803 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 2804
NYX 0:85b3fd62ea1a 2805 /******************* Bit definition for CAN_F1R1 register *******************/
NYX 0:85b3fd62ea1a 2806 #define CAN_F1R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 2807 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2808 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 2809 #define CAN_F1R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 2810 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2811 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 2812 #define CAN_F1R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 2813 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2814 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 2815 #define CAN_F1R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 2816 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 2817 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 2818 #define CAN_F1R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 2819 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 2820 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 2821 #define CAN_F1R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 2822 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 2823 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 2824 #define CAN_F1R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 2825 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 2826 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 2827 #define CAN_F1R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 2828 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 2829 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 2830 #define CAN_F1R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 2831 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2832 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 2833 #define CAN_F1R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 2834 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 2835 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 2836 #define CAN_F1R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 2837 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 2838 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 2839 #define CAN_F1R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 2840 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 2841 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 2842 #define CAN_F1R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 2843 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 2844 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 2845 #define CAN_F1R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 2846 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 2847 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 2848 #define CAN_F1R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 2849 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 2850 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 2851 #define CAN_F1R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 2852 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 2853 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 2854 #define CAN_F1R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 2855 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 2856 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 2857 #define CAN_F1R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 2858 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 2859 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 2860 #define CAN_F1R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 2861 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 2862 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 2863 #define CAN_F1R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 2864 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 2865 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 2866 #define CAN_F1R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 2867 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 2868 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 2869 #define CAN_F1R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 2870 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 2871 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 2872 #define CAN_F1R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 2873 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 2874 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 2875 #define CAN_F1R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 2876 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 2877 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 2878 #define CAN_F1R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 2879 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 2880 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 2881 #define CAN_F1R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 2882 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 2883 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 2884 #define CAN_F1R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 2885 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 2886 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 2887 #define CAN_F1R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 2888 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 2889 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 2890 #define CAN_F1R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 2891 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 2892 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 2893 #define CAN_F1R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 2894 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 2895 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 2896 #define CAN_F1R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 2897 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 2898 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 2899 #define CAN_F1R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 2900 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 2901 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 2902
NYX 0:85b3fd62ea1a 2903 /******************* Bit definition for CAN_F2R1 register *******************/
NYX 0:85b3fd62ea1a 2904 #define CAN_F2R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 2905 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 2906 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 2907 #define CAN_F2R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 2908 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 2909 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 2910 #define CAN_F2R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 2911 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 2912 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 2913 #define CAN_F2R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 2914 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 2915 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 2916 #define CAN_F2R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 2917 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 2918 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 2919 #define CAN_F2R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 2920 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 2921 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 2922 #define CAN_F2R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 2923 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 2924 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 2925 #define CAN_F2R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 2926 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 2927 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 2928 #define CAN_F2R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 2929 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 2930 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 2931 #define CAN_F2R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 2932 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 2933 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 2934 #define CAN_F2R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 2935 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 2936 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 2937 #define CAN_F2R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 2938 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 2939 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 2940 #define CAN_F2R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 2941 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 2942 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 2943 #define CAN_F2R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 2944 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 2945 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 2946 #define CAN_F2R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 2947 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 2948 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 2949 #define CAN_F2R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 2950 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 2951 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 2952 #define CAN_F2R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 2953 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 2954 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 2955 #define CAN_F2R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 2956 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 2957 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 2958 #define CAN_F2R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 2959 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 2960 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 2961 #define CAN_F2R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 2962 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 2963 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 2964 #define CAN_F2R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 2965 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 2966 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 2967 #define CAN_F2R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 2968 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 2969 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 2970 #define CAN_F2R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 2971 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 2972 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 2973 #define CAN_F2R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 2974 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 2975 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 2976 #define CAN_F2R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 2977 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 2978 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 2979 #define CAN_F2R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 2980 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 2981 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 2982 #define CAN_F2R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 2983 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 2984 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 2985 #define CAN_F2R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 2986 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 2987 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 2988 #define CAN_F2R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 2989 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 2990 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 2991 #define CAN_F2R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 2992 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 2993 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 2994 #define CAN_F2R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 2995 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 2996 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 2997 #define CAN_F2R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 2998 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 2999 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3000
NYX 0:85b3fd62ea1a 3001 /******************* Bit definition for CAN_F3R1 register *******************/
NYX 0:85b3fd62ea1a 3002 #define CAN_F3R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3003 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3004 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3005 #define CAN_F3R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3006 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3007 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3008 #define CAN_F3R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3009 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3010 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3011 #define CAN_F3R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3012 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3013 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3014 #define CAN_F3R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3015 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3016 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3017 #define CAN_F3R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3018 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3019 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3020 #define CAN_F3R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3021 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3022 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3023 #define CAN_F3R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3024 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3025 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3026 #define CAN_F3R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3027 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3028 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3029 #define CAN_F3R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3030 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3031 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3032 #define CAN_F3R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3033 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3034 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3035 #define CAN_F3R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3036 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3037 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3038 #define CAN_F3R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3039 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3040 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3041 #define CAN_F3R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3042 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3043 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3044 #define CAN_F3R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3045 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3046 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3047 #define CAN_F3R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3048 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3049 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3050 #define CAN_F3R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3051 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3052 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3053 #define CAN_F3R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3054 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3055 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3056 #define CAN_F3R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3057 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3058 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3059 #define CAN_F3R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3060 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3061 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3062 #define CAN_F3R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3063 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3064 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3065 #define CAN_F3R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3066 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3067 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3068 #define CAN_F3R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3069 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3070 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3071 #define CAN_F3R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3072 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3073 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3074 #define CAN_F3R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3075 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3076 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3077 #define CAN_F3R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3078 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3079 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3080 #define CAN_F3R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3081 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3082 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3083 #define CAN_F3R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3084 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3085 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3086 #define CAN_F3R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3087 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3088 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3089 #define CAN_F3R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3090 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3091 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3092 #define CAN_F3R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3093 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3094 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3095 #define CAN_F3R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3096 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3097 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3098
NYX 0:85b3fd62ea1a 3099 /******************* Bit definition for CAN_F4R1 register *******************/
NYX 0:85b3fd62ea1a 3100 #define CAN_F4R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3101 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3102 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3103 #define CAN_F4R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3104 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3105 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3106 #define CAN_F4R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3107 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3108 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3109 #define CAN_F4R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3110 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3111 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3112 #define CAN_F4R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3113 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3114 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3115 #define CAN_F4R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3116 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3117 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3118 #define CAN_F4R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3119 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3120 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3121 #define CAN_F4R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3122 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3123 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3124 #define CAN_F4R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3125 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3126 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3127 #define CAN_F4R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3128 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3129 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3130 #define CAN_F4R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3131 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3132 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3133 #define CAN_F4R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3134 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3135 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3136 #define CAN_F4R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3137 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3138 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3139 #define CAN_F4R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3140 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3141 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3142 #define CAN_F4R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3143 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3144 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3145 #define CAN_F4R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3146 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3147 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3148 #define CAN_F4R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3149 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3150 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3151 #define CAN_F4R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3152 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3153 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3154 #define CAN_F4R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3155 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3156 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3157 #define CAN_F4R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3158 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3159 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3160 #define CAN_F4R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3161 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3162 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3163 #define CAN_F4R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3164 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3165 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3166 #define CAN_F4R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3167 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3168 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3169 #define CAN_F4R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3170 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3171 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3172 #define CAN_F4R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3173 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3174 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3175 #define CAN_F4R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3176 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3177 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3178 #define CAN_F4R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3179 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3180 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3181 #define CAN_F4R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3182 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3183 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3184 #define CAN_F4R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3185 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3186 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3187 #define CAN_F4R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3188 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3189 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3190 #define CAN_F4R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3191 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3192 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3193 #define CAN_F4R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3194 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3195 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3196
NYX 0:85b3fd62ea1a 3197 /******************* Bit definition for CAN_F5R1 register *******************/
NYX 0:85b3fd62ea1a 3198 #define CAN_F5R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3199 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3200 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3201 #define CAN_F5R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3202 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3203 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3204 #define CAN_F5R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3205 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3206 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3207 #define CAN_F5R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3208 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3209 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3210 #define CAN_F5R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3211 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3212 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3213 #define CAN_F5R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3214 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3215 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3216 #define CAN_F5R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3217 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3218 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3219 #define CAN_F5R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3220 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3221 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3222 #define CAN_F5R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3223 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3224 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3225 #define CAN_F5R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3226 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3227 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3228 #define CAN_F5R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3229 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3230 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3231 #define CAN_F5R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3232 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3233 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3234 #define CAN_F5R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3235 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3236 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3237 #define CAN_F5R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3238 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3239 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3240 #define CAN_F5R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3241 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3242 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3243 #define CAN_F5R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3244 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3245 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3246 #define CAN_F5R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3247 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3248 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3249 #define CAN_F5R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3250 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3251 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3252 #define CAN_F5R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3253 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3254 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3255 #define CAN_F5R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3256 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3257 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3258 #define CAN_F5R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3259 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3260 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3261 #define CAN_F5R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3262 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3263 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3264 #define CAN_F5R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3265 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3266 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3267 #define CAN_F5R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3268 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3269 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3270 #define CAN_F5R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3271 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3272 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3273 #define CAN_F5R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3274 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3275 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3276 #define CAN_F5R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3277 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3278 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3279 #define CAN_F5R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3280 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3281 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3282 #define CAN_F5R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3283 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3284 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3285 #define CAN_F5R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3286 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3287 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3288 #define CAN_F5R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3289 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3290 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3291 #define CAN_F5R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3292 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3293 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3294
NYX 0:85b3fd62ea1a 3295 /******************* Bit definition for CAN_F6R1 register *******************/
NYX 0:85b3fd62ea1a 3296 #define CAN_F6R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3297 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3298 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3299 #define CAN_F6R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3300 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3301 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3302 #define CAN_F6R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3303 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3304 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3305 #define CAN_F6R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3306 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3307 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3308 #define CAN_F6R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3309 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3310 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3311 #define CAN_F6R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3312 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3313 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3314 #define CAN_F6R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3315 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3316 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3317 #define CAN_F6R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3318 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3319 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3320 #define CAN_F6R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3321 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3322 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3323 #define CAN_F6R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3324 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3325 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3326 #define CAN_F6R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3327 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3328 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3329 #define CAN_F6R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3330 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3331 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3332 #define CAN_F6R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3333 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3334 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3335 #define CAN_F6R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3336 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3337 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3338 #define CAN_F6R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3339 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3340 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3341 #define CAN_F6R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3342 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3343 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3344 #define CAN_F6R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3345 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3346 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3347 #define CAN_F6R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3348 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3349 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3350 #define CAN_F6R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3351 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3352 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3353 #define CAN_F6R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3354 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3355 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3356 #define CAN_F6R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3357 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3358 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3359 #define CAN_F6R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3360 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3361 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3362 #define CAN_F6R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3363 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3364 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3365 #define CAN_F6R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3366 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3367 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3368 #define CAN_F6R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3369 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3370 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3371 #define CAN_F6R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3372 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3373 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3374 #define CAN_F6R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3375 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3376 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3377 #define CAN_F6R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3378 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3379 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3380 #define CAN_F6R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3381 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3382 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3383 #define CAN_F6R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3384 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3385 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3386 #define CAN_F6R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3387 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3388 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3389 #define CAN_F6R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3390 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3391 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3392
NYX 0:85b3fd62ea1a 3393 /******************* Bit definition for CAN_F7R1 register *******************/
NYX 0:85b3fd62ea1a 3394 #define CAN_F7R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3395 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3396 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3397 #define CAN_F7R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3398 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3399 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3400 #define CAN_F7R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3401 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3402 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3403 #define CAN_F7R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3404 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3405 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3406 #define CAN_F7R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3407 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3408 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3409 #define CAN_F7R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3410 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3411 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3412 #define CAN_F7R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3413 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3414 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3415 #define CAN_F7R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3416 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3417 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3418 #define CAN_F7R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3419 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3420 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3421 #define CAN_F7R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3422 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3423 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3424 #define CAN_F7R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3425 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3426 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3427 #define CAN_F7R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3428 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3429 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3430 #define CAN_F7R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3431 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3432 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3433 #define CAN_F7R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3434 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3435 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3436 #define CAN_F7R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3437 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3438 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3439 #define CAN_F7R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3440 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3441 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3442 #define CAN_F7R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3443 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3444 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3445 #define CAN_F7R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3446 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3447 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3448 #define CAN_F7R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3449 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3450 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3451 #define CAN_F7R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3452 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3453 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3454 #define CAN_F7R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3455 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3456 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3457 #define CAN_F7R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3458 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3459 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3460 #define CAN_F7R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3461 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3462 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3463 #define CAN_F7R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3464 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3465 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3466 #define CAN_F7R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3467 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3468 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3469 #define CAN_F7R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3470 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3471 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3472 #define CAN_F7R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3473 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3474 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3475 #define CAN_F7R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3476 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3477 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3478 #define CAN_F7R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3479 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3480 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3481 #define CAN_F7R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3482 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3483 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3484 #define CAN_F7R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3485 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3486 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3487 #define CAN_F7R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3488 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3489 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3490
NYX 0:85b3fd62ea1a 3491 /******************* Bit definition for CAN_F8R1 register *******************/
NYX 0:85b3fd62ea1a 3492 #define CAN_F8R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3493 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3494 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3495 #define CAN_F8R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3496 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3497 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3498 #define CAN_F8R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3499 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3500 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3501 #define CAN_F8R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3502 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3503 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3504 #define CAN_F8R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3505 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3506 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3507 #define CAN_F8R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3508 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3509 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3510 #define CAN_F8R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3511 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3512 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3513 #define CAN_F8R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3514 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3515 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3516 #define CAN_F8R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3517 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3518 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3519 #define CAN_F8R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3520 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3521 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3522 #define CAN_F8R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3523 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3524 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3525 #define CAN_F8R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3526 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3527 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3528 #define CAN_F8R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3529 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3530 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3531 #define CAN_F8R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3532 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3533 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3534 #define CAN_F8R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3535 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3536 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3537 #define CAN_F8R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3538 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3539 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3540 #define CAN_F8R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3541 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3542 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3543 #define CAN_F8R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3544 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3545 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3546 #define CAN_F8R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3547 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3548 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3549 #define CAN_F8R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3550 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3551 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3552 #define CAN_F8R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3553 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3554 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3555 #define CAN_F8R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3556 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3557 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3558 #define CAN_F8R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3559 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3560 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3561 #define CAN_F8R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3562 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3563 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3564 #define CAN_F8R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3565 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3566 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3567 #define CAN_F8R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3568 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3569 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3570 #define CAN_F8R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3571 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3572 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3573 #define CAN_F8R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3574 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3575 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3576 #define CAN_F8R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3577 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3578 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3579 #define CAN_F8R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3580 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3581 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3582 #define CAN_F8R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3583 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3584 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3585 #define CAN_F8R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3586 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3587 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3588
NYX 0:85b3fd62ea1a 3589 /******************* Bit definition for CAN_F9R1 register *******************/
NYX 0:85b3fd62ea1a 3590 #define CAN_F9R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3591 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3592 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3593 #define CAN_F9R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3594 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3595 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3596 #define CAN_F9R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3597 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3598 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3599 #define CAN_F9R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3600 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3601 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3602 #define CAN_F9R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3603 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3604 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3605 #define CAN_F9R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3606 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3607 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3608 #define CAN_F9R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3609 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3610 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3611 #define CAN_F9R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3612 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3613 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3614 #define CAN_F9R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3615 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3616 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3617 #define CAN_F9R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3618 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3619 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3620 #define CAN_F9R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3621 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3622 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3623 #define CAN_F9R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3624 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3625 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3626 #define CAN_F9R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3627 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3628 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3629 #define CAN_F9R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3630 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3631 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3632 #define CAN_F9R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3633 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3634 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3635 #define CAN_F9R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3636 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3637 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3638 #define CAN_F9R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3639 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3640 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3641 #define CAN_F9R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3642 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3643 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3644 #define CAN_F9R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3645 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3646 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3647 #define CAN_F9R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3648 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3649 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3650 #define CAN_F9R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3651 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3652 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3653 #define CAN_F9R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3654 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3655 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3656 #define CAN_F9R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3657 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3658 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3659 #define CAN_F9R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3660 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3661 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3662 #define CAN_F9R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3663 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3664 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3665 #define CAN_F9R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3666 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3667 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3668 #define CAN_F9R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3669 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3670 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3671 #define CAN_F9R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3672 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3673 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3674 #define CAN_F9R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3675 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3676 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3677 #define CAN_F9R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3678 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3679 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3680 #define CAN_F9R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3681 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3682 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3683 #define CAN_F9R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3684 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3685 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3686
NYX 0:85b3fd62ea1a 3687 /******************* Bit definition for CAN_F10R1 register ******************/
NYX 0:85b3fd62ea1a 3688 #define CAN_F10R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3689 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3690 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3691 #define CAN_F10R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3692 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3693 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3694 #define CAN_F10R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3695 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3696 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3697 #define CAN_F10R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3698 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3699 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3700 #define CAN_F10R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3701 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3702 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3703 #define CAN_F10R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3704 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3705 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3706 #define CAN_F10R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3707 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3708 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3709 #define CAN_F10R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3710 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3711 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3712 #define CAN_F10R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3713 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3714 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3715 #define CAN_F10R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3716 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3717 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3718 #define CAN_F10R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3719 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3720 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3721 #define CAN_F10R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3722 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3723 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3724 #define CAN_F10R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3725 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3726 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3727 #define CAN_F10R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3728 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3729 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3730 #define CAN_F10R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3731 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3732 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3733 #define CAN_F10R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3734 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3735 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3736 #define CAN_F10R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3737 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3738 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3739 #define CAN_F10R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3740 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3741 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3742 #define CAN_F10R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3743 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3744 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3745 #define CAN_F10R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3746 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3747 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3748 #define CAN_F10R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3749 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3750 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3751 #define CAN_F10R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3752 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3753 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3754 #define CAN_F10R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3755 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3756 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3757 #define CAN_F10R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3758 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3759 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3760 #define CAN_F10R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3761 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3762 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3763 #define CAN_F10R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3764 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3765 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3766 #define CAN_F10R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3767 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3768 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3769 #define CAN_F10R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3770 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3771 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3772 #define CAN_F10R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3773 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3774 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3775 #define CAN_F10R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3776 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3777 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3778 #define CAN_F10R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3779 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3780 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3781 #define CAN_F10R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3782 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3783 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3784
NYX 0:85b3fd62ea1a 3785 /******************* Bit definition for CAN_F11R1 register ******************/
NYX 0:85b3fd62ea1a 3786 #define CAN_F11R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3787 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3788 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3789 #define CAN_F11R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3790 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3791 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3792 #define CAN_F11R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3793 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3794 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3795 #define CAN_F11R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3796 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3797 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3798 #define CAN_F11R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3799 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3800 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3801 #define CAN_F11R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3802 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3803 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3804 #define CAN_F11R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3805 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3806 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3807 #define CAN_F11R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3808 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3809 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3810 #define CAN_F11R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3811 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3812 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3813 #define CAN_F11R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3814 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3815 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3816 #define CAN_F11R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3817 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3818 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3819 #define CAN_F11R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3820 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3821 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3822 #define CAN_F11R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3823 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3824 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3825 #define CAN_F11R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3826 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3827 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3828 #define CAN_F11R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3829 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3830 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3831 #define CAN_F11R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3832 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3833 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3834 #define CAN_F11R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3835 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3836 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3837 #define CAN_F11R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3838 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3839 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3840 #define CAN_F11R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3841 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3842 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3843 #define CAN_F11R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3844 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3845 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3846 #define CAN_F11R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3847 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3848 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3849 #define CAN_F11R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3850 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3851 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3852 #define CAN_F11R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3853 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3854 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3855 #define CAN_F11R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3856 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3857 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3858 #define CAN_F11R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3859 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3860 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3861 #define CAN_F11R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3862 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3863 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3864 #define CAN_F11R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3865 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3866 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3867 #define CAN_F11R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3868 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3869 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3870 #define CAN_F11R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3871 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3872 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3873 #define CAN_F11R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3874 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3875 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3876 #define CAN_F11R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3877 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3878 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3879 #define CAN_F11R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3880 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3881 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3882
NYX 0:85b3fd62ea1a 3883 /******************* Bit definition for CAN_F12R1 register ******************/
NYX 0:85b3fd62ea1a 3884 #define CAN_F12R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3885 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3886 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3887 #define CAN_F12R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3888 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3889 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3890 #define CAN_F12R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3891 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3892 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3893 #define CAN_F12R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3894 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3895 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3896 #define CAN_F12R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3897 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3898 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3899 #define CAN_F12R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3900 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3901 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 3902 #define CAN_F12R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 3903 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 3904 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 3905 #define CAN_F12R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 3906 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 3907 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 3908 #define CAN_F12R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 3909 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 3910 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 3911 #define CAN_F12R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 3912 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 3913 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 3914 #define CAN_F12R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 3915 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 3916 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 3917 #define CAN_F12R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 3918 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 3919 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 3920 #define CAN_F12R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 3921 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 3922 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 3923 #define CAN_F12R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 3924 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 3925 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 3926 #define CAN_F12R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 3927 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 3928 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 3929 #define CAN_F12R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 3930 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 3931 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 3932 #define CAN_F12R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 3933 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 3934 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 3935 #define CAN_F12R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 3936 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 3937 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 3938 #define CAN_F12R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 3939 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 3940 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 3941 #define CAN_F12R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 3942 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 3943 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 3944 #define CAN_F12R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 3945 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 3946 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 3947 #define CAN_F12R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 3948 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 3949 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 3950 #define CAN_F12R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 3951 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 3952 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 3953 #define CAN_F12R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 3954 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 3955 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 3956 #define CAN_F12R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 3957 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 3958 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 3959 #define CAN_F12R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 3960 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 3961 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 3962 #define CAN_F12R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 3963 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 3964 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 3965 #define CAN_F12R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 3966 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 3967 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 3968 #define CAN_F12R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 3969 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 3970 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 3971 #define CAN_F12R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 3972 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 3973 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 3974 #define CAN_F12R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 3975 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 3976 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 3977 #define CAN_F12R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 3978 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 3979 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 3980
NYX 0:85b3fd62ea1a 3981 /******************* Bit definition for CAN_F13R1 register ******************/
NYX 0:85b3fd62ea1a 3982 #define CAN_F13R1_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 3983 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 3984 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 3985 #define CAN_F13R1_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 3986 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 3987 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 3988 #define CAN_F13R1_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 3989 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 3990 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 3991 #define CAN_F13R1_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 3992 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 3993 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 3994 #define CAN_F13R1_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 3995 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 3996 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 3997 #define CAN_F13R1_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 3998 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 3999 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4000 #define CAN_F13R1_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4001 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4002 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4003 #define CAN_F13R1_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4004 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4005 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4006 #define CAN_F13R1_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4007 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4008 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4009 #define CAN_F13R1_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4010 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4011 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4012 #define CAN_F13R1_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4013 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4014 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4015 #define CAN_F13R1_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4016 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4017 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4018 #define CAN_F13R1_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4019 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4020 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4021 #define CAN_F13R1_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4022 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4023 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4024 #define CAN_F13R1_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4025 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4026 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4027 #define CAN_F13R1_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4028 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4029 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4030 #define CAN_F13R1_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4031 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4032 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4033 #define CAN_F13R1_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4034 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4035 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4036 #define CAN_F13R1_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4037 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4038 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4039 #define CAN_F13R1_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4040 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4041 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4042 #define CAN_F13R1_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4043 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4044 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4045 #define CAN_F13R1_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4046 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4047 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4048 #define CAN_F13R1_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4049 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4050 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4051 #define CAN_F13R1_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4052 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4053 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4054 #define CAN_F13R1_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4055 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4056 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4057 #define CAN_F13R1_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4058 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4059 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4060 #define CAN_F13R1_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4061 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4062 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4063 #define CAN_F13R1_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4064 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4065 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4066 #define CAN_F13R1_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4067 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4068 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4069 #define CAN_F13R1_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4070 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4071 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4072 #define CAN_F13R1_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4073 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4074 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4075 #define CAN_F13R1_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4076 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4077 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4078
NYX 0:85b3fd62ea1a 4079 /******************* Bit definition for CAN_F0R2 register *******************/
NYX 0:85b3fd62ea1a 4080 #define CAN_F0R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4081 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4082 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4083 #define CAN_F0R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4084 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4085 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4086 #define CAN_F0R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4087 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4088 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4089 #define CAN_F0R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4090 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4091 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4092 #define CAN_F0R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4093 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4094 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4095 #define CAN_F0R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4096 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4097 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4098 #define CAN_F0R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4099 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4100 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4101 #define CAN_F0R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4102 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4103 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4104 #define CAN_F0R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4105 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4106 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4107 #define CAN_F0R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4108 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4109 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4110 #define CAN_F0R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4111 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4112 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4113 #define CAN_F0R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4114 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4115 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4116 #define CAN_F0R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4117 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4118 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4119 #define CAN_F0R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4120 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4121 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4122 #define CAN_F0R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4123 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4124 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4125 #define CAN_F0R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4126 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4127 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4128 #define CAN_F0R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4129 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4130 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4131 #define CAN_F0R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4132 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4133 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4134 #define CAN_F0R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4135 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4136 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4137 #define CAN_F0R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4138 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4139 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4140 #define CAN_F0R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4141 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4142 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4143 #define CAN_F0R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4144 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4145 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4146 #define CAN_F0R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4147 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4148 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4149 #define CAN_F0R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4150 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4151 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4152 #define CAN_F0R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4153 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4154 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4155 #define CAN_F0R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4156 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4157 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4158 #define CAN_F0R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4159 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4160 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4161 #define CAN_F0R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4162 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4163 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4164 #define CAN_F0R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4165 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4166 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4167 #define CAN_F0R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4168 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4169 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4170 #define CAN_F0R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4171 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4172 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4173 #define CAN_F0R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4174 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4175 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4176
NYX 0:85b3fd62ea1a 4177 /******************* Bit definition for CAN_F1R2 register *******************/
NYX 0:85b3fd62ea1a 4178 #define CAN_F1R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4179 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4180 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4181 #define CAN_F1R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4182 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4183 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4184 #define CAN_F1R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4185 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4186 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4187 #define CAN_F1R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4188 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4189 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4190 #define CAN_F1R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4191 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4192 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4193 #define CAN_F1R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4194 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4195 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4196 #define CAN_F1R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4197 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4198 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4199 #define CAN_F1R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4200 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4201 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4202 #define CAN_F1R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4203 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4204 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4205 #define CAN_F1R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4206 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4207 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4208 #define CAN_F1R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4209 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4210 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4211 #define CAN_F1R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4212 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4213 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4214 #define CAN_F1R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4215 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4216 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4217 #define CAN_F1R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4218 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4219 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4220 #define CAN_F1R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4221 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4222 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4223 #define CAN_F1R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4224 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4225 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4226 #define CAN_F1R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4227 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4228 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4229 #define CAN_F1R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4230 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4231 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4232 #define CAN_F1R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4233 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4234 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4235 #define CAN_F1R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4236 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4237 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4238 #define CAN_F1R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4239 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4240 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4241 #define CAN_F1R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4242 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4243 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4244 #define CAN_F1R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4245 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4246 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4247 #define CAN_F1R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4248 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4249 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4250 #define CAN_F1R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4251 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4252 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4253 #define CAN_F1R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4254 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4255 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4256 #define CAN_F1R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4257 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4258 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4259 #define CAN_F1R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4260 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4261 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4262 #define CAN_F1R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4263 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4264 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4265 #define CAN_F1R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4266 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4267 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4268 #define CAN_F1R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4269 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4270 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4271 #define CAN_F1R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4272 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4273 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4274
NYX 0:85b3fd62ea1a 4275 /******************* Bit definition for CAN_F2R2 register *******************/
NYX 0:85b3fd62ea1a 4276 #define CAN_F2R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4277 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4278 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4279 #define CAN_F2R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4280 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4281 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4282 #define CAN_F2R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4283 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4284 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4285 #define CAN_F2R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4286 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4287 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4288 #define CAN_F2R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4289 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4290 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4291 #define CAN_F2R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4292 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4293 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4294 #define CAN_F2R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4295 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4296 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4297 #define CAN_F2R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4298 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4299 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4300 #define CAN_F2R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4301 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4302 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4303 #define CAN_F2R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4304 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4305 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4306 #define CAN_F2R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4307 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4308 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4309 #define CAN_F2R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4310 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4311 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4312 #define CAN_F2R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4313 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4314 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4315 #define CAN_F2R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4316 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4317 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4318 #define CAN_F2R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4319 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4320 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4321 #define CAN_F2R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4322 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4323 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4324 #define CAN_F2R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4325 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4326 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4327 #define CAN_F2R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4328 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4329 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4330 #define CAN_F2R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4331 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4332 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4333 #define CAN_F2R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4334 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4335 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4336 #define CAN_F2R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4337 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4338 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4339 #define CAN_F2R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4340 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4341 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4342 #define CAN_F2R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4343 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4344 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4345 #define CAN_F2R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4346 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4347 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4348 #define CAN_F2R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4349 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4350 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4351 #define CAN_F2R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4352 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4353 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4354 #define CAN_F2R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4355 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4356 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4357 #define CAN_F2R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4358 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4359 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4360 #define CAN_F2R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4361 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4362 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4363 #define CAN_F2R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4364 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4365 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4366 #define CAN_F2R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4367 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4368 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4369 #define CAN_F2R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4370 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4371 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4372
NYX 0:85b3fd62ea1a 4373 /******************* Bit definition for CAN_F3R2 register *******************/
NYX 0:85b3fd62ea1a 4374 #define CAN_F3R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4375 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4376 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4377 #define CAN_F3R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4378 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4379 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4380 #define CAN_F3R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4381 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4382 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4383 #define CAN_F3R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4384 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4385 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4386 #define CAN_F3R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4387 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4388 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4389 #define CAN_F3R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4390 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4391 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4392 #define CAN_F3R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4393 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4394 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4395 #define CAN_F3R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4396 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4397 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4398 #define CAN_F3R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4399 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4400 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4401 #define CAN_F3R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4402 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4403 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4404 #define CAN_F3R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4405 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4406 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4407 #define CAN_F3R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4408 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4409 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4410 #define CAN_F3R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4411 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4412 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4413 #define CAN_F3R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4414 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4415 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4416 #define CAN_F3R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4417 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4418 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4419 #define CAN_F3R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4420 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4421 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4422 #define CAN_F3R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4423 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4424 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4425 #define CAN_F3R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4426 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4427 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4428 #define CAN_F3R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4429 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4430 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4431 #define CAN_F3R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4432 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4433 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4434 #define CAN_F3R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4435 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4436 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4437 #define CAN_F3R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4438 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4439 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4440 #define CAN_F3R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4441 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4442 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4443 #define CAN_F3R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4444 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4445 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4446 #define CAN_F3R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4447 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4448 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4449 #define CAN_F3R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4450 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4451 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4452 #define CAN_F3R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4453 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4454 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4455 #define CAN_F3R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4456 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4457 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4458 #define CAN_F3R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4459 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4460 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4461 #define CAN_F3R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4462 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4463 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4464 #define CAN_F3R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4465 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4466 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4467 #define CAN_F3R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4468 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4469 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4470
NYX 0:85b3fd62ea1a 4471 /******************* Bit definition for CAN_F4R2 register *******************/
NYX 0:85b3fd62ea1a 4472 #define CAN_F4R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4473 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4474 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4475 #define CAN_F4R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4476 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4477 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4478 #define CAN_F4R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4479 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4480 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4481 #define CAN_F4R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4482 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4483 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4484 #define CAN_F4R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4485 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4486 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4487 #define CAN_F4R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4488 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4489 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4490 #define CAN_F4R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4491 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4492 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4493 #define CAN_F4R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4494 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4495 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4496 #define CAN_F4R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4497 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4498 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4499 #define CAN_F4R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4500 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4501 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4502 #define CAN_F4R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4503 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4504 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4505 #define CAN_F4R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4506 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4507 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4508 #define CAN_F4R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4509 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4510 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4511 #define CAN_F4R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4512 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4513 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4514 #define CAN_F4R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4515 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4516 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4517 #define CAN_F4R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4518 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4519 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4520 #define CAN_F4R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4521 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4522 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4523 #define CAN_F4R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4524 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4525 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4526 #define CAN_F4R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4527 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4528 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4529 #define CAN_F4R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4530 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4531 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4532 #define CAN_F4R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4533 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4534 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4535 #define CAN_F4R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4536 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4537 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4538 #define CAN_F4R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4539 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4540 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4541 #define CAN_F4R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4542 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4543 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4544 #define CAN_F4R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4545 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4546 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4547 #define CAN_F4R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4548 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4549 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4550 #define CAN_F4R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4551 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4552 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4553 #define CAN_F4R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4554 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4555 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4556 #define CAN_F4R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4557 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4558 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4559 #define CAN_F4R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4560 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4561 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4562 #define CAN_F4R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4563 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4564 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4565 #define CAN_F4R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4566 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4567 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4568
NYX 0:85b3fd62ea1a 4569 /******************* Bit definition for CAN_F5R2 register *******************/
NYX 0:85b3fd62ea1a 4570 #define CAN_F5R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4571 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4572 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4573 #define CAN_F5R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4574 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4575 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4576 #define CAN_F5R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4577 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4578 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4579 #define CAN_F5R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4580 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4581 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4582 #define CAN_F5R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4583 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4584 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4585 #define CAN_F5R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4586 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4587 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4588 #define CAN_F5R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4589 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4590 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4591 #define CAN_F5R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4592 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4593 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4594 #define CAN_F5R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4595 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4596 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4597 #define CAN_F5R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4598 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4599 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4600 #define CAN_F5R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4601 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4602 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4603 #define CAN_F5R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4604 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4605 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4606 #define CAN_F5R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4607 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4608 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4609 #define CAN_F5R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4610 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4611 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4612 #define CAN_F5R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4613 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4614 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4615 #define CAN_F5R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4616 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4617 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4618 #define CAN_F5R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4619 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4620 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4621 #define CAN_F5R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4622 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4623 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4624 #define CAN_F5R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4625 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4626 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4627 #define CAN_F5R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4628 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4629 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4630 #define CAN_F5R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4631 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4632 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4633 #define CAN_F5R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4634 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4635 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4636 #define CAN_F5R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4637 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4638 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4639 #define CAN_F5R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4640 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4641 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4642 #define CAN_F5R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4643 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4644 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4645 #define CAN_F5R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4646 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4647 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4648 #define CAN_F5R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4649 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4650 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4651 #define CAN_F5R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4652 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4653 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4654 #define CAN_F5R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4655 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4656 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4657 #define CAN_F5R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4658 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4659 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4660 #define CAN_F5R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4661 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4662 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4663 #define CAN_F5R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4664 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4665 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4666
NYX 0:85b3fd62ea1a 4667 /******************* Bit definition for CAN_F6R2 register *******************/
NYX 0:85b3fd62ea1a 4668 #define CAN_F6R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4669 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4670 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4671 #define CAN_F6R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4672 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4673 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4674 #define CAN_F6R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4675 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4676 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4677 #define CAN_F6R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4678 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4679 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4680 #define CAN_F6R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4681 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4682 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4683 #define CAN_F6R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4684 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4685 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4686 #define CAN_F6R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4687 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4688 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4689 #define CAN_F6R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4690 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4691 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4692 #define CAN_F6R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4693 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4694 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4695 #define CAN_F6R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4696 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4697 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4698 #define CAN_F6R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4699 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4700 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4701 #define CAN_F6R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4702 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4703 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4704 #define CAN_F6R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4705 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4706 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4707 #define CAN_F6R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4708 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4709 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4710 #define CAN_F6R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4711 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4712 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4713 #define CAN_F6R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4714 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4715 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4716 #define CAN_F6R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4717 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4718 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4719 #define CAN_F6R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4720 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4721 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4722 #define CAN_F6R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4723 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4724 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4725 #define CAN_F6R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4726 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4727 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4728 #define CAN_F6R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4729 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4730 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4731 #define CAN_F6R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4732 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4733 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4734 #define CAN_F6R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4735 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4736 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4737 #define CAN_F6R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4738 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4739 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4740 #define CAN_F6R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4741 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4742 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4743 #define CAN_F6R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4744 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4745 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4746 #define CAN_F6R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4747 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4748 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4749 #define CAN_F6R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4750 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4751 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4752 #define CAN_F6R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4753 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4754 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4755 #define CAN_F6R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4756 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4757 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4758 #define CAN_F6R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4759 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4760 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4761 #define CAN_F6R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4762 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4763 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4764
NYX 0:85b3fd62ea1a 4765 /******************* Bit definition for CAN_F7R2 register *******************/
NYX 0:85b3fd62ea1a 4766 #define CAN_F7R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4767 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4768 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4769 #define CAN_F7R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4770 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4771 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4772 #define CAN_F7R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4773 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4774 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4775 #define CAN_F7R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4776 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4777 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4778 #define CAN_F7R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4779 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4780 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4781 #define CAN_F7R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4782 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4783 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4784 #define CAN_F7R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4785 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4786 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4787 #define CAN_F7R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4788 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4789 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4790 #define CAN_F7R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4791 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4792 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4793 #define CAN_F7R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4794 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4795 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4796 #define CAN_F7R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4797 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4798 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4799 #define CAN_F7R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4800 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4801 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4802 #define CAN_F7R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4803 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4804 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4805 #define CAN_F7R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4806 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4807 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4808 #define CAN_F7R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4809 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4810 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4811 #define CAN_F7R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4812 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4813 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4814 #define CAN_F7R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4815 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4816 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4817 #define CAN_F7R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4818 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4819 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4820 #define CAN_F7R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4821 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4822 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4823 #define CAN_F7R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4824 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4825 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4826 #define CAN_F7R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4827 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4828 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4829 #define CAN_F7R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4830 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4831 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4832 #define CAN_F7R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4833 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4834 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4835 #define CAN_F7R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4836 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4837 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4838 #define CAN_F7R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4839 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4840 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4841 #define CAN_F7R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4842 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4843 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4844 #define CAN_F7R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4845 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4846 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4847 #define CAN_F7R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4848 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4849 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4850 #define CAN_F7R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4851 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4852 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4853 #define CAN_F7R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4854 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4855 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4856 #define CAN_F7R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4857 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4858 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4859 #define CAN_F7R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4860 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4861 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4862
NYX 0:85b3fd62ea1a 4863 /******************* Bit definition for CAN_F8R2 register *******************/
NYX 0:85b3fd62ea1a 4864 #define CAN_F8R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4865 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4866 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4867 #define CAN_F8R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4868 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4869 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4870 #define CAN_F8R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4871 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4872 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4873 #define CAN_F8R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4874 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4875 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4876 #define CAN_F8R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4877 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4878 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4879 #define CAN_F8R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4880 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4881 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4882 #define CAN_F8R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4883 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4884 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4885 #define CAN_F8R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4886 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4887 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4888 #define CAN_F8R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4889 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4890 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4891 #define CAN_F8R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4892 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4893 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4894 #define CAN_F8R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4895 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4896 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4897 #define CAN_F8R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4898 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4899 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4900 #define CAN_F8R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4901 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 4902 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 4903 #define CAN_F8R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 4904 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 4905 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 4906 #define CAN_F8R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 4907 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 4908 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 4909 #define CAN_F8R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 4910 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 4911 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 4912 #define CAN_F8R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 4913 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 4914 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 4915 #define CAN_F8R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 4916 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 4917 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 4918 #define CAN_F8R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 4919 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 4920 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 4921 #define CAN_F8R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 4922 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 4923 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 4924 #define CAN_F8R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 4925 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 4926 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 4927 #define CAN_F8R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 4928 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 4929 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 4930 #define CAN_F8R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 4931 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 4932 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 4933 #define CAN_F8R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 4934 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 4935 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 4936 #define CAN_F8R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 4937 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 4938 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 4939 #define CAN_F8R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 4940 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 4941 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 4942 #define CAN_F8R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 4943 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 4944 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 4945 #define CAN_F8R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 4946 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 4947 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 4948 #define CAN_F8R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 4949 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 4950 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 4951 #define CAN_F8R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 4952 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 4953 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 4954 #define CAN_F8R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 4955 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 4956 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 4957 #define CAN_F8R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 4958 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 4959 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 4960
NYX 0:85b3fd62ea1a 4961 /******************* Bit definition for CAN_F9R2 register *******************/
NYX 0:85b3fd62ea1a 4962 #define CAN_F9R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 4963 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 4964 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 4965 #define CAN_F9R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 4966 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 4967 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 4968 #define CAN_F9R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 4969 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 4970 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 4971 #define CAN_F9R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 4972 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 4973 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 4974 #define CAN_F9R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 4975 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 4976 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 4977 #define CAN_F9R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 4978 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 4979 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 4980 #define CAN_F9R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 4981 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 4982 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 4983 #define CAN_F9R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 4984 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 4985 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 4986 #define CAN_F9R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 4987 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 4988 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 4989 #define CAN_F9R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 4990 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 4991 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 4992 #define CAN_F9R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 4993 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 4994 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 4995 #define CAN_F9R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 4996 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 4997 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 4998 #define CAN_F9R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 4999 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 5000 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 5001 #define CAN_F9R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 5002 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 5003 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 5004 #define CAN_F9R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 5005 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 5006 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 5007 #define CAN_F9R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 5008 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 5009 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 5010 #define CAN_F9R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 5011 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 5012 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 5013 #define CAN_F9R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 5014 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 5015 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 5016 #define CAN_F9R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 5017 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 5018 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 5019 #define CAN_F9R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 5020 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 5021 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 5022 #define CAN_F9R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 5023 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 5024 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 5025 #define CAN_F9R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 5026 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 5027 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 5028 #define CAN_F9R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 5029 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 5030 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 5031 #define CAN_F9R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 5032 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 5033 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 5034 #define CAN_F9R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 5035 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 5036 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 5037 #define CAN_F9R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 5038 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 5039 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 5040 #define CAN_F9R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 5041 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 5042 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 5043 #define CAN_F9R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 5044 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 5045 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 5046 #define CAN_F9R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 5047 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 5048 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 5049 #define CAN_F9R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 5050 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 5051 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 5052 #define CAN_F9R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 5053 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 5054 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 5055 #define CAN_F9R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 5056 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 5057 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 5058
NYX 0:85b3fd62ea1a 5059 /******************* Bit definition for CAN_F10R2 register ******************/
NYX 0:85b3fd62ea1a 5060 #define CAN_F10R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 5061 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5062 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 5063 #define CAN_F10R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 5064 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5065 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 5066 #define CAN_F10R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 5067 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5068 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 5069 #define CAN_F10R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 5070 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5071 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 5072 #define CAN_F10R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 5073 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5074 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 5075 #define CAN_F10R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 5076 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 5077 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 5078 #define CAN_F10R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 5079 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 5080 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 5081 #define CAN_F10R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 5082 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 5083 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 5084 #define CAN_F10R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 5085 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 5086 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 5087 #define CAN_F10R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 5088 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 5089 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 5090 #define CAN_F10R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 5091 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 5092 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 5093 #define CAN_F10R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 5094 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 5095 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 5096 #define CAN_F10R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 5097 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 5098 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 5099 #define CAN_F10R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 5100 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 5101 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 5102 #define CAN_F10R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 5103 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 5104 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 5105 #define CAN_F10R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 5106 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 5107 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 5108 #define CAN_F10R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 5109 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 5110 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 5111 #define CAN_F10R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 5112 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 5113 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 5114 #define CAN_F10R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 5115 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 5116 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 5117 #define CAN_F10R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 5118 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 5119 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 5120 #define CAN_F10R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 5121 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 5122 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 5123 #define CAN_F10R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 5124 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 5125 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 5126 #define CAN_F10R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 5127 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 5128 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 5129 #define CAN_F10R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 5130 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 5131 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 5132 #define CAN_F10R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 5133 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 5134 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 5135 #define CAN_F10R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 5136 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 5137 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 5138 #define CAN_F10R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 5139 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 5140 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 5141 #define CAN_F10R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 5142 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 5143 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 5144 #define CAN_F10R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 5145 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 5146 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 5147 #define CAN_F10R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 5148 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 5149 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 5150 #define CAN_F10R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 5151 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 5152 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 5153 #define CAN_F10R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 5154 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 5155 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 5156
NYX 0:85b3fd62ea1a 5157 /******************* Bit definition for CAN_F11R2 register ******************/
NYX 0:85b3fd62ea1a 5158 #define CAN_F11R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 5159 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5160 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 5161 #define CAN_F11R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 5162 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5163 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 5164 #define CAN_F11R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 5165 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5166 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 5167 #define CAN_F11R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 5168 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5169 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 5170 #define CAN_F11R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 5171 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5172 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 5173 #define CAN_F11R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 5174 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 5175 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 5176 #define CAN_F11R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 5177 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 5178 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 5179 #define CAN_F11R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 5180 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 5181 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 5182 #define CAN_F11R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 5183 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 5184 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 5185 #define CAN_F11R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 5186 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 5187 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 5188 #define CAN_F11R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 5189 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 5190 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 5191 #define CAN_F11R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 5192 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 5193 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 5194 #define CAN_F11R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 5195 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 5196 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 5197 #define CAN_F11R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 5198 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 5199 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 5200 #define CAN_F11R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 5201 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 5202 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 5203 #define CAN_F11R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 5204 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 5205 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 5206 #define CAN_F11R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 5207 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 5208 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 5209 #define CAN_F11R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 5210 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 5211 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 5212 #define CAN_F11R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 5213 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 5214 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 5215 #define CAN_F11R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 5216 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 5217 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 5218 #define CAN_F11R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 5219 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 5220 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 5221 #define CAN_F11R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 5222 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 5223 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 5224 #define CAN_F11R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 5225 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 5226 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 5227 #define CAN_F11R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 5228 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 5229 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 5230 #define CAN_F11R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 5231 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 5232 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 5233 #define CAN_F11R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 5234 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 5235 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 5236 #define CAN_F11R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 5237 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 5238 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 5239 #define CAN_F11R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 5240 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 5241 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 5242 #define CAN_F11R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 5243 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 5244 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 5245 #define CAN_F11R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 5246 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 5247 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 5248 #define CAN_F11R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 5249 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 5250 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 5251 #define CAN_F11R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 5252 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 5253 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 5254
NYX 0:85b3fd62ea1a 5255 /******************* Bit definition for CAN_F12R2 register ******************/
NYX 0:85b3fd62ea1a 5256 #define CAN_F12R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 5257 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5258 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 5259 #define CAN_F12R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 5260 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5261 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 5262 #define CAN_F12R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 5263 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5264 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 5265 #define CAN_F12R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 5266 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5267 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 5268 #define CAN_F12R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 5269 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5270 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 5271 #define CAN_F12R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 5272 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 5273 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 5274 #define CAN_F12R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 5275 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 5276 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 5277 #define CAN_F12R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 5278 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 5279 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 5280 #define CAN_F12R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 5281 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 5282 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 5283 #define CAN_F12R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 5284 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 5285 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 5286 #define CAN_F12R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 5287 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 5288 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 5289 #define CAN_F12R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 5290 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 5291 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 5292 #define CAN_F12R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 5293 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 5294 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 5295 #define CAN_F12R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 5296 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 5297 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 5298 #define CAN_F12R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 5299 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 5300 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 5301 #define CAN_F12R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 5302 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 5303 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 5304 #define CAN_F12R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 5305 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 5306 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 5307 #define CAN_F12R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 5308 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 5309 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 5310 #define CAN_F12R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 5311 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 5312 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 5313 #define CAN_F12R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 5314 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 5315 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 5316 #define CAN_F12R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 5317 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 5318 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 5319 #define CAN_F12R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 5320 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 5321 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 5322 #define CAN_F12R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 5323 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 5324 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 5325 #define CAN_F12R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 5326 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 5327 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 5328 #define CAN_F12R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 5329 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 5330 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 5331 #define CAN_F12R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 5332 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 5333 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 5334 #define CAN_F12R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 5335 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 5336 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 5337 #define CAN_F12R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 5338 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 5339 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 5340 #define CAN_F12R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 5341 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 5342 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 5343 #define CAN_F12R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 5344 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 5345 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 5346 #define CAN_F12R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 5347 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 5348 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 5349 #define CAN_F12R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 5350 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 5351 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 5352
NYX 0:85b3fd62ea1a 5353 /******************* Bit definition for CAN_F13R2 register ******************/
NYX 0:85b3fd62ea1a 5354 #define CAN_F13R2_FB0_Pos (0U)
NYX 0:85b3fd62ea1a 5355 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5356 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
NYX 0:85b3fd62ea1a 5357 #define CAN_F13R2_FB1_Pos (1U)
NYX 0:85b3fd62ea1a 5358 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5359 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
NYX 0:85b3fd62ea1a 5360 #define CAN_F13R2_FB2_Pos (2U)
NYX 0:85b3fd62ea1a 5361 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5362 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
NYX 0:85b3fd62ea1a 5363 #define CAN_F13R2_FB3_Pos (3U)
NYX 0:85b3fd62ea1a 5364 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5365 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
NYX 0:85b3fd62ea1a 5366 #define CAN_F13R2_FB4_Pos (4U)
NYX 0:85b3fd62ea1a 5367 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5368 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
NYX 0:85b3fd62ea1a 5369 #define CAN_F13R2_FB5_Pos (5U)
NYX 0:85b3fd62ea1a 5370 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 5371 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
NYX 0:85b3fd62ea1a 5372 #define CAN_F13R2_FB6_Pos (6U)
NYX 0:85b3fd62ea1a 5373 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 5374 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
NYX 0:85b3fd62ea1a 5375 #define CAN_F13R2_FB7_Pos (7U)
NYX 0:85b3fd62ea1a 5376 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 5377 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
NYX 0:85b3fd62ea1a 5378 #define CAN_F13R2_FB8_Pos (8U)
NYX 0:85b3fd62ea1a 5379 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 5380 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
NYX 0:85b3fd62ea1a 5381 #define CAN_F13R2_FB9_Pos (9U)
NYX 0:85b3fd62ea1a 5382 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 5383 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
NYX 0:85b3fd62ea1a 5384 #define CAN_F13R2_FB10_Pos (10U)
NYX 0:85b3fd62ea1a 5385 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 5386 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
NYX 0:85b3fd62ea1a 5387 #define CAN_F13R2_FB11_Pos (11U)
NYX 0:85b3fd62ea1a 5388 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 5389 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
NYX 0:85b3fd62ea1a 5390 #define CAN_F13R2_FB12_Pos (12U)
NYX 0:85b3fd62ea1a 5391 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 5392 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
NYX 0:85b3fd62ea1a 5393 #define CAN_F13R2_FB13_Pos (13U)
NYX 0:85b3fd62ea1a 5394 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 5395 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
NYX 0:85b3fd62ea1a 5396 #define CAN_F13R2_FB14_Pos (14U)
NYX 0:85b3fd62ea1a 5397 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 5398 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
NYX 0:85b3fd62ea1a 5399 #define CAN_F13R2_FB15_Pos (15U)
NYX 0:85b3fd62ea1a 5400 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 5401 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
NYX 0:85b3fd62ea1a 5402 #define CAN_F13R2_FB16_Pos (16U)
NYX 0:85b3fd62ea1a 5403 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 5404 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
NYX 0:85b3fd62ea1a 5405 #define CAN_F13R2_FB17_Pos (17U)
NYX 0:85b3fd62ea1a 5406 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 5407 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
NYX 0:85b3fd62ea1a 5408 #define CAN_F13R2_FB18_Pos (18U)
NYX 0:85b3fd62ea1a 5409 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 5410 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
NYX 0:85b3fd62ea1a 5411 #define CAN_F13R2_FB19_Pos (19U)
NYX 0:85b3fd62ea1a 5412 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 5413 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
NYX 0:85b3fd62ea1a 5414 #define CAN_F13R2_FB20_Pos (20U)
NYX 0:85b3fd62ea1a 5415 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 5416 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
NYX 0:85b3fd62ea1a 5417 #define CAN_F13R2_FB21_Pos (21U)
NYX 0:85b3fd62ea1a 5418 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 5419 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
NYX 0:85b3fd62ea1a 5420 #define CAN_F13R2_FB22_Pos (22U)
NYX 0:85b3fd62ea1a 5421 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 5422 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
NYX 0:85b3fd62ea1a 5423 #define CAN_F13R2_FB23_Pos (23U)
NYX 0:85b3fd62ea1a 5424 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 5425 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
NYX 0:85b3fd62ea1a 5426 #define CAN_F13R2_FB24_Pos (24U)
NYX 0:85b3fd62ea1a 5427 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 5428 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
NYX 0:85b3fd62ea1a 5429 #define CAN_F13R2_FB25_Pos (25U)
NYX 0:85b3fd62ea1a 5430 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 5431 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
NYX 0:85b3fd62ea1a 5432 #define CAN_F13R2_FB26_Pos (26U)
NYX 0:85b3fd62ea1a 5433 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 5434 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
NYX 0:85b3fd62ea1a 5435 #define CAN_F13R2_FB27_Pos (27U)
NYX 0:85b3fd62ea1a 5436 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 5437 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
NYX 0:85b3fd62ea1a 5438 #define CAN_F13R2_FB28_Pos (28U)
NYX 0:85b3fd62ea1a 5439 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 5440 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
NYX 0:85b3fd62ea1a 5441 #define CAN_F13R2_FB29_Pos (29U)
NYX 0:85b3fd62ea1a 5442 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 5443 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
NYX 0:85b3fd62ea1a 5444 #define CAN_F13R2_FB30_Pos (30U)
NYX 0:85b3fd62ea1a 5445 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 5446 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
NYX 0:85b3fd62ea1a 5447 #define CAN_F13R2_FB31_Pos (31U)
NYX 0:85b3fd62ea1a 5448 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 5449 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
NYX 0:85b3fd62ea1a 5450
NYX 0:85b3fd62ea1a 5451 /******************************************************************************/
NYX 0:85b3fd62ea1a 5452 /* */
NYX 0:85b3fd62ea1a 5453 /* HDMI-CEC (CEC) */
NYX 0:85b3fd62ea1a 5454 /* */
NYX 0:85b3fd62ea1a 5455 /******************************************************************************/
NYX 0:85b3fd62ea1a 5456
NYX 0:85b3fd62ea1a 5457 /******************* Bit definition for CEC_CR register *********************/
NYX 0:85b3fd62ea1a 5458 #define CEC_CR_CECEN_Pos (0U)
NYX 0:85b3fd62ea1a 5459 #define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5460 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
NYX 0:85b3fd62ea1a 5461 #define CEC_CR_TXSOM_Pos (1U)
NYX 0:85b3fd62ea1a 5462 #define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5463 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
NYX 0:85b3fd62ea1a 5464 #define CEC_CR_TXEOM_Pos (2U)
NYX 0:85b3fd62ea1a 5465 #define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5466 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
NYX 0:85b3fd62ea1a 5467
NYX 0:85b3fd62ea1a 5468 /******************* Bit definition for CEC_CFGR register *******************/
NYX 0:85b3fd62ea1a 5469 #define CEC_CFGR_SFT_Pos (0U)
NYX 0:85b3fd62ea1a 5470 #define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 5471 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
NYX 0:85b3fd62ea1a 5472 #define CEC_CFGR_RXTOL_Pos (3U)
NYX 0:85b3fd62ea1a 5473 #define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5474 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
NYX 0:85b3fd62ea1a 5475 #define CEC_CFGR_BRESTP_Pos (4U)
NYX 0:85b3fd62ea1a 5476 #define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5477 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
NYX 0:85b3fd62ea1a 5478 #define CEC_CFGR_BREGEN_Pos (5U)
NYX 0:85b3fd62ea1a 5479 #define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 5480 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
NYX 0:85b3fd62ea1a 5481 #define CEC_CFGR_LBPEGEN_Pos (6U)
NYX 0:85b3fd62ea1a 5482 #define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 5483 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
NYX 0:85b3fd62ea1a 5484 #define CEC_CFGR_SFTOPT_Pos (8U)
NYX 0:85b3fd62ea1a 5485 #define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 5486 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
NYX 0:85b3fd62ea1a 5487 #define CEC_CFGR_BRDNOGEN_Pos (7U)
NYX 0:85b3fd62ea1a 5488 #define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 5489 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
NYX 0:85b3fd62ea1a 5490 #define CEC_CFGR_OAR_Pos (16U)
NYX 0:85b3fd62ea1a 5491 #define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
NYX 0:85b3fd62ea1a 5492 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
NYX 0:85b3fd62ea1a 5493 #define CEC_CFGR_LSTN_Pos (31U)
NYX 0:85b3fd62ea1a 5494 #define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 5495 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
NYX 0:85b3fd62ea1a 5496
NYX 0:85b3fd62ea1a 5497 /******************* Bit definition for CEC_TXDR register *******************/
NYX 0:85b3fd62ea1a 5498 #define CEC_TXDR_TXD_Pos (0U)
NYX 0:85b3fd62ea1a 5499 #define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 5500 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
NYX 0:85b3fd62ea1a 5501
NYX 0:85b3fd62ea1a 5502 /******************* Bit definition for CEC_RXDR register *******************/
NYX 0:85b3fd62ea1a 5503 #define CEC_RXDR_RXD_Pos (0U)
NYX 0:85b3fd62ea1a 5504 #define CEC_RXDR_RXD_Msk (0xFFU << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 5505 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
NYX 0:85b3fd62ea1a 5506 /*legacy define*/
NYX 0:85b3fd62ea1a 5507 #define CEC_TXDR_RXD CEC_RXDR_RXD /*!< CEC Rx Data */
NYX 0:85b3fd62ea1a 5508
NYX 0:85b3fd62ea1a 5509 /******************* Bit definition for CEC_ISR register ********************/
NYX 0:85b3fd62ea1a 5510 #define CEC_ISR_RXBR_Pos (0U)
NYX 0:85b3fd62ea1a 5511 #define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5512 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
NYX 0:85b3fd62ea1a 5513 #define CEC_ISR_RXEND_Pos (1U)
NYX 0:85b3fd62ea1a 5514 #define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5515 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
NYX 0:85b3fd62ea1a 5516 #define CEC_ISR_RXOVR_Pos (2U)
NYX 0:85b3fd62ea1a 5517 #define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5518 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
NYX 0:85b3fd62ea1a 5519 #define CEC_ISR_BRE_Pos (3U)
NYX 0:85b3fd62ea1a 5520 #define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5521 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
NYX 0:85b3fd62ea1a 5522 #define CEC_ISR_SBPE_Pos (4U)
NYX 0:85b3fd62ea1a 5523 #define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5524 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
NYX 0:85b3fd62ea1a 5525 #define CEC_ISR_LBPE_Pos (5U)
NYX 0:85b3fd62ea1a 5526 #define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 5527 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
NYX 0:85b3fd62ea1a 5528 #define CEC_ISR_RXACKE_Pos (6U)
NYX 0:85b3fd62ea1a 5529 #define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 5530 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
NYX 0:85b3fd62ea1a 5531 #define CEC_ISR_ARBLST_Pos (7U)
NYX 0:85b3fd62ea1a 5532 #define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 5533 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
NYX 0:85b3fd62ea1a 5534 #define CEC_ISR_TXBR_Pos (8U)
NYX 0:85b3fd62ea1a 5535 #define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 5536 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
NYX 0:85b3fd62ea1a 5537 #define CEC_ISR_TXEND_Pos (9U)
NYX 0:85b3fd62ea1a 5538 #define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 5539 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
NYX 0:85b3fd62ea1a 5540 #define CEC_ISR_TXUDR_Pos (10U)
NYX 0:85b3fd62ea1a 5541 #define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 5542 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
NYX 0:85b3fd62ea1a 5543 #define CEC_ISR_TXERR_Pos (11U)
NYX 0:85b3fd62ea1a 5544 #define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 5545 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
NYX 0:85b3fd62ea1a 5546 #define CEC_ISR_TXACKE_Pos (12U)
NYX 0:85b3fd62ea1a 5547 #define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 5548 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
NYX 0:85b3fd62ea1a 5549
NYX 0:85b3fd62ea1a 5550 /******************* Bit definition for CEC_IER register ********************/
NYX 0:85b3fd62ea1a 5551 #define CEC_IER_RXBRIE_Pos (0U)
NYX 0:85b3fd62ea1a 5552 #define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5553 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
NYX 0:85b3fd62ea1a 5554 #define CEC_IER_RXENDIE_Pos (1U)
NYX 0:85b3fd62ea1a 5555 #define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5556 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
NYX 0:85b3fd62ea1a 5557 #define CEC_IER_RXOVRIE_Pos (2U)
NYX 0:85b3fd62ea1a 5558 #define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5559 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
NYX 0:85b3fd62ea1a 5560 #define CEC_IER_BREIE_Pos (3U)
NYX 0:85b3fd62ea1a 5561 #define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5562 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
NYX 0:85b3fd62ea1a 5563 #define CEC_IER_SBPEIE_Pos (4U)
NYX 0:85b3fd62ea1a 5564 #define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5565 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
NYX 0:85b3fd62ea1a 5566 #define CEC_IER_LBPEIE_Pos (5U)
NYX 0:85b3fd62ea1a 5567 #define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 5568 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
NYX 0:85b3fd62ea1a 5569 #define CEC_IER_RXACKEIE_Pos (6U)
NYX 0:85b3fd62ea1a 5570 #define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 5571 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
NYX 0:85b3fd62ea1a 5572 #define CEC_IER_ARBLSTIE_Pos (7U)
NYX 0:85b3fd62ea1a 5573 #define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 5574 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
NYX 0:85b3fd62ea1a 5575 #define CEC_IER_TXBRIE_Pos (8U)
NYX 0:85b3fd62ea1a 5576 #define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 5577 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
NYX 0:85b3fd62ea1a 5578 #define CEC_IER_TXENDIE_Pos (9U)
NYX 0:85b3fd62ea1a 5579 #define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 5580 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
NYX 0:85b3fd62ea1a 5581 #define CEC_IER_TXUDRIE_Pos (10U)
NYX 0:85b3fd62ea1a 5582 #define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 5583 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
NYX 0:85b3fd62ea1a 5584 #define CEC_IER_TXERRIE_Pos (11U)
NYX 0:85b3fd62ea1a 5585 #define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 5586 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
NYX 0:85b3fd62ea1a 5587 #define CEC_IER_TXACKEIE_Pos (12U)
NYX 0:85b3fd62ea1a 5588 #define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 5589 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
NYX 0:85b3fd62ea1a 5590
NYX 0:85b3fd62ea1a 5591 /******************************************************************************/
NYX 0:85b3fd62ea1a 5592 /* */
NYX 0:85b3fd62ea1a 5593 /* CRC calculation unit */
NYX 0:85b3fd62ea1a 5594 /* */
NYX 0:85b3fd62ea1a 5595 /******************************************************************************/
NYX 0:85b3fd62ea1a 5596 /******************* Bit definition for CRC_DR register *********************/
NYX 0:85b3fd62ea1a 5597 #define CRC_DR_DR_Pos (0U)
NYX 0:85b3fd62ea1a 5598 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 5599 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
NYX 0:85b3fd62ea1a 5600
NYX 0:85b3fd62ea1a 5601
NYX 0:85b3fd62ea1a 5602 /******************* Bit definition for CRC_IDR register ********************/
NYX 0:85b3fd62ea1a 5603 #define CRC_IDR_IDR_Pos (0U)
NYX 0:85b3fd62ea1a 5604 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 5605 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
NYX 0:85b3fd62ea1a 5606
NYX 0:85b3fd62ea1a 5607
NYX 0:85b3fd62ea1a 5608 /******************** Bit definition for CRC_CR register ********************/
NYX 0:85b3fd62ea1a 5609 #define CRC_CR_RESET_Pos (0U)
NYX 0:85b3fd62ea1a 5610 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5611 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
NYX 0:85b3fd62ea1a 5612
NYX 0:85b3fd62ea1a 5613 /******************************************************************************/
NYX 0:85b3fd62ea1a 5614 /* */
NYX 0:85b3fd62ea1a 5615 /* Digital to Analog Converter */
NYX 0:85b3fd62ea1a 5616 /* */
NYX 0:85b3fd62ea1a 5617 /******************************************************************************/
NYX 0:85b3fd62ea1a 5618 /*
NYX 0:85b3fd62ea1a 5619 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
NYX 0:85b3fd62ea1a 5620 */
NYX 0:85b3fd62ea1a 5621 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
NYX 0:85b3fd62ea1a 5622 /******************** Bit definition for DAC_CR register ********************/
NYX 0:85b3fd62ea1a 5623 #define DAC_CR_EN1_Pos (0U)
NYX 0:85b3fd62ea1a 5624 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5625 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
NYX 0:85b3fd62ea1a 5626 #define DAC_CR_BOFF1_Pos (1U)
NYX 0:85b3fd62ea1a 5627 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5628 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
NYX 0:85b3fd62ea1a 5629 #define DAC_CR_TEN1_Pos (2U)
NYX 0:85b3fd62ea1a 5630 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5631 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
NYX 0:85b3fd62ea1a 5632
NYX 0:85b3fd62ea1a 5633 #define DAC_CR_TSEL1_Pos (3U)
NYX 0:85b3fd62ea1a 5634 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
NYX 0:85b3fd62ea1a 5635 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
NYX 0:85b3fd62ea1a 5636 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5637 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5638 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 5639
NYX 0:85b3fd62ea1a 5640 #define DAC_CR_WAVE1_Pos (6U)
NYX 0:85b3fd62ea1a 5641 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 5642 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
NYX 0:85b3fd62ea1a 5643 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 5644 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 5645
NYX 0:85b3fd62ea1a 5646 #define DAC_CR_MAMP1_Pos (8U)
NYX 0:85b3fd62ea1a 5647 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 5648 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
NYX 0:85b3fd62ea1a 5649 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 5650 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 5651 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 5652 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 5653
NYX 0:85b3fd62ea1a 5654 #define DAC_CR_DMAEN1_Pos (12U)
NYX 0:85b3fd62ea1a 5655 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 5656 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
NYX 0:85b3fd62ea1a 5657 #define DAC_CR_DMAUDRIE1_Pos (13U)
NYX 0:85b3fd62ea1a 5658 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 5659 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
NYX 0:85b3fd62ea1a 5660 #define DAC_CR_EN2_Pos (16U)
NYX 0:85b3fd62ea1a 5661 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 5662 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
NYX 0:85b3fd62ea1a 5663 #define DAC_CR_BOFF2_Pos (17U)
NYX 0:85b3fd62ea1a 5664 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 5665 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
NYX 0:85b3fd62ea1a 5666 #define DAC_CR_TEN2_Pos (18U)
NYX 0:85b3fd62ea1a 5667 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 5668 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
NYX 0:85b3fd62ea1a 5669
NYX 0:85b3fd62ea1a 5670 #define DAC_CR_TSEL2_Pos (19U)
NYX 0:85b3fd62ea1a 5671 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
NYX 0:85b3fd62ea1a 5672 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
NYX 0:85b3fd62ea1a 5673 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 5674 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 5675 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 5676
NYX 0:85b3fd62ea1a 5677 #define DAC_CR_WAVE2_Pos (22U)
NYX 0:85b3fd62ea1a 5678 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
NYX 0:85b3fd62ea1a 5679 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
NYX 0:85b3fd62ea1a 5680 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 5681 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 5682
NYX 0:85b3fd62ea1a 5683 #define DAC_CR_MAMP2_Pos (24U)
NYX 0:85b3fd62ea1a 5684 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 5685 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
NYX 0:85b3fd62ea1a 5686 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 5687 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 5688 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 5689 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 5690
NYX 0:85b3fd62ea1a 5691 #define DAC_CR_DMAEN2_Pos (28U)
NYX 0:85b3fd62ea1a 5692 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 5693 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
NYX 0:85b3fd62ea1a 5694 #define DAC_CR_DMAUDRIE2_Pos (29U)
NYX 0:85b3fd62ea1a 5695 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 5696 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
NYX 0:85b3fd62ea1a 5697
NYX 0:85b3fd62ea1a 5698 /***************** Bit definition for DAC_SWTRIGR register ******************/
NYX 0:85b3fd62ea1a 5699 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
NYX 0:85b3fd62ea1a 5700 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5701 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
NYX 0:85b3fd62ea1a 5702 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
NYX 0:85b3fd62ea1a 5703 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5704 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
NYX 0:85b3fd62ea1a 5705
NYX 0:85b3fd62ea1a 5706 /***************** Bit definition for DAC_DHR12R1 register ******************/
NYX 0:85b3fd62ea1a 5707 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
NYX 0:85b3fd62ea1a 5708 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 5709 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
NYX 0:85b3fd62ea1a 5710
NYX 0:85b3fd62ea1a 5711 /***************** Bit definition for DAC_DHR12L1 register ******************/
NYX 0:85b3fd62ea1a 5712 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
NYX 0:85b3fd62ea1a 5713 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
NYX 0:85b3fd62ea1a 5714 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
NYX 0:85b3fd62ea1a 5715
NYX 0:85b3fd62ea1a 5716 /****************** Bit definition for DAC_DHR8R1 register ******************/
NYX 0:85b3fd62ea1a 5717 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
NYX 0:85b3fd62ea1a 5718 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 5719 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
NYX 0:85b3fd62ea1a 5720
NYX 0:85b3fd62ea1a 5721 /***************** Bit definition for DAC_DHR12R2 register ******************/
NYX 0:85b3fd62ea1a 5722 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
NYX 0:85b3fd62ea1a 5723 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 5724 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
NYX 0:85b3fd62ea1a 5725
NYX 0:85b3fd62ea1a 5726 /***************** Bit definition for DAC_DHR12L2 register ******************/
NYX 0:85b3fd62ea1a 5727 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
NYX 0:85b3fd62ea1a 5728 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
NYX 0:85b3fd62ea1a 5729 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
NYX 0:85b3fd62ea1a 5730
NYX 0:85b3fd62ea1a 5731 /****************** Bit definition for DAC_DHR8R2 register ******************/
NYX 0:85b3fd62ea1a 5732 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
NYX 0:85b3fd62ea1a 5733 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 5734 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
NYX 0:85b3fd62ea1a 5735
NYX 0:85b3fd62ea1a 5736 /***************** Bit definition for DAC_DHR12RD register ******************/
NYX 0:85b3fd62ea1a 5737 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
NYX 0:85b3fd62ea1a 5738 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 5739 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
NYX 0:85b3fd62ea1a 5740 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
NYX 0:85b3fd62ea1a 5741 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
NYX 0:85b3fd62ea1a 5742 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
NYX 0:85b3fd62ea1a 5743
NYX 0:85b3fd62ea1a 5744 /***************** Bit definition for DAC_DHR12LD register ******************/
NYX 0:85b3fd62ea1a 5745 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
NYX 0:85b3fd62ea1a 5746 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
NYX 0:85b3fd62ea1a 5747 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
NYX 0:85b3fd62ea1a 5748 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
NYX 0:85b3fd62ea1a 5749 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
NYX 0:85b3fd62ea1a 5750 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
NYX 0:85b3fd62ea1a 5751
NYX 0:85b3fd62ea1a 5752 /****************** Bit definition for DAC_DHR8RD register ******************/
NYX 0:85b3fd62ea1a 5753 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
NYX 0:85b3fd62ea1a 5754 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 5755 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
NYX 0:85b3fd62ea1a 5756 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
NYX 0:85b3fd62ea1a 5757 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 5758 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
NYX 0:85b3fd62ea1a 5759
NYX 0:85b3fd62ea1a 5760 /******************* Bit definition for DAC_DOR1 register *******************/
NYX 0:85b3fd62ea1a 5761 #define DAC_DOR1_DACC1DOR_Pos (0U)
NYX 0:85b3fd62ea1a 5762 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 5763 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
NYX 0:85b3fd62ea1a 5764
NYX 0:85b3fd62ea1a 5765 /******************* Bit definition for DAC_DOR2 register *******************/
NYX 0:85b3fd62ea1a 5766 #define DAC_DOR2_DACC2DOR_Pos (0U)
NYX 0:85b3fd62ea1a 5767 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 5768 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
NYX 0:85b3fd62ea1a 5769
NYX 0:85b3fd62ea1a 5770 /******************** Bit definition for DAC_SR register ********************/
NYX 0:85b3fd62ea1a 5771 #define DAC_SR_DMAUDR1_Pos (13U)
NYX 0:85b3fd62ea1a 5772 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 5773 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
NYX 0:85b3fd62ea1a 5774 #define DAC_SR_DMAUDR2_Pos (29U)
NYX 0:85b3fd62ea1a 5775 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 5776 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
NYX 0:85b3fd62ea1a 5777
NYX 0:85b3fd62ea1a 5778 /******************************************************************************/
NYX 0:85b3fd62ea1a 5779 /* */
NYX 0:85b3fd62ea1a 5780 /* DCMI */
NYX 0:85b3fd62ea1a 5781 /* */
NYX 0:85b3fd62ea1a 5782 /******************************************************************************/
NYX 0:85b3fd62ea1a 5783 /******************** Bits definition for DCMI_CR register ******************/
NYX 0:85b3fd62ea1a 5784 #define DCMI_CR_CAPTURE_Pos (0U)
NYX 0:85b3fd62ea1a 5785 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5786 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
NYX 0:85b3fd62ea1a 5787 #define DCMI_CR_CM_Pos (1U)
NYX 0:85b3fd62ea1a 5788 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5789 #define DCMI_CR_CM DCMI_CR_CM_Msk
NYX 0:85b3fd62ea1a 5790 #define DCMI_CR_CROP_Pos (2U)
NYX 0:85b3fd62ea1a 5791 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5792 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
NYX 0:85b3fd62ea1a 5793 #define DCMI_CR_JPEG_Pos (3U)
NYX 0:85b3fd62ea1a 5794 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5795 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
NYX 0:85b3fd62ea1a 5796 #define DCMI_CR_ESS_Pos (4U)
NYX 0:85b3fd62ea1a 5797 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5798 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
NYX 0:85b3fd62ea1a 5799 #define DCMI_CR_PCKPOL_Pos (5U)
NYX 0:85b3fd62ea1a 5800 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 5801 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
NYX 0:85b3fd62ea1a 5802 #define DCMI_CR_HSPOL_Pos (6U)
NYX 0:85b3fd62ea1a 5803 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 5804 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
NYX 0:85b3fd62ea1a 5805 #define DCMI_CR_VSPOL_Pos (7U)
NYX 0:85b3fd62ea1a 5806 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 5807 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
NYX 0:85b3fd62ea1a 5808 #define DCMI_CR_FCRC_0 0x00000100U
NYX 0:85b3fd62ea1a 5809 #define DCMI_CR_FCRC_1 0x00000200U
NYX 0:85b3fd62ea1a 5810 #define DCMI_CR_EDM_0 0x00000400U
NYX 0:85b3fd62ea1a 5811 #define DCMI_CR_EDM_1 0x00000800U
NYX 0:85b3fd62ea1a 5812 #define DCMI_CR_OUTEN_Pos (13U)
NYX 0:85b3fd62ea1a 5813 #define DCMI_CR_OUTEN_Msk (0x1U << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 5814 #define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
NYX 0:85b3fd62ea1a 5815 #define DCMI_CR_ENABLE_Pos (14U)
NYX 0:85b3fd62ea1a 5816 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 5817 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
NYX 0:85b3fd62ea1a 5818 #define DCMI_CR_BSM_0 0x00010000U
NYX 0:85b3fd62ea1a 5819 #define DCMI_CR_BSM_1 0x00020000U
NYX 0:85b3fd62ea1a 5820 #define DCMI_CR_OEBS_Pos (18U)
NYX 0:85b3fd62ea1a 5821 #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 5822 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
NYX 0:85b3fd62ea1a 5823 #define DCMI_CR_LSM_Pos (19U)
NYX 0:85b3fd62ea1a 5824 #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 5825 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
NYX 0:85b3fd62ea1a 5826 #define DCMI_CR_OELS_Pos (20U)
NYX 0:85b3fd62ea1a 5827 #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 5828 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
NYX 0:85b3fd62ea1a 5829
NYX 0:85b3fd62ea1a 5830 /******************** Bits definition for DCMI_SR register ******************/
NYX 0:85b3fd62ea1a 5831 #define DCMI_SR_HSYNC_Pos (0U)
NYX 0:85b3fd62ea1a 5832 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5833 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
NYX 0:85b3fd62ea1a 5834 #define DCMI_SR_VSYNC_Pos (1U)
NYX 0:85b3fd62ea1a 5835 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5836 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
NYX 0:85b3fd62ea1a 5837 #define DCMI_SR_FNE_Pos (2U)
NYX 0:85b3fd62ea1a 5838 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5839 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
NYX 0:85b3fd62ea1a 5840
NYX 0:85b3fd62ea1a 5841 /******************** Bits definition for DCMI_RIS register *****************/
NYX 0:85b3fd62ea1a 5842 #define DCMI_RIS_FRAME_RIS_Pos (0U)
NYX 0:85b3fd62ea1a 5843 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5844 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
NYX 0:85b3fd62ea1a 5845 #define DCMI_RIS_OVR_RIS_Pos (1U)
NYX 0:85b3fd62ea1a 5846 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5847 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
NYX 0:85b3fd62ea1a 5848 #define DCMI_RIS_ERR_RIS_Pos (2U)
NYX 0:85b3fd62ea1a 5849 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5850 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
NYX 0:85b3fd62ea1a 5851 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
NYX 0:85b3fd62ea1a 5852 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5853 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
NYX 0:85b3fd62ea1a 5854 #define DCMI_RIS_LINE_RIS_Pos (4U)
NYX 0:85b3fd62ea1a 5855 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5856 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
NYX 0:85b3fd62ea1a 5857 /* Legacy defines */
NYX 0:85b3fd62ea1a 5858 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
NYX 0:85b3fd62ea1a 5859 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
NYX 0:85b3fd62ea1a 5860 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
NYX 0:85b3fd62ea1a 5861 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
NYX 0:85b3fd62ea1a 5862 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
NYX 0:85b3fd62ea1a 5863 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
NYX 0:85b3fd62ea1a 5864
NYX 0:85b3fd62ea1a 5865 /******************** Bits definition for DCMI_IER register *****************/
NYX 0:85b3fd62ea1a 5866 #define DCMI_IER_FRAME_IE_Pos (0U)
NYX 0:85b3fd62ea1a 5867 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5868 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
NYX 0:85b3fd62ea1a 5869 #define DCMI_IER_OVR_IE_Pos (1U)
NYX 0:85b3fd62ea1a 5870 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5871 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
NYX 0:85b3fd62ea1a 5872 #define DCMI_IER_ERR_IE_Pos (2U)
NYX 0:85b3fd62ea1a 5873 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5874 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
NYX 0:85b3fd62ea1a 5875 #define DCMI_IER_VSYNC_IE_Pos (3U)
NYX 0:85b3fd62ea1a 5876 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5877 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
NYX 0:85b3fd62ea1a 5878 #define DCMI_IER_LINE_IE_Pos (4U)
NYX 0:85b3fd62ea1a 5879 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5880 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
NYX 0:85b3fd62ea1a 5881 /* Legacy defines */
NYX 0:85b3fd62ea1a 5882 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
NYX 0:85b3fd62ea1a 5883
NYX 0:85b3fd62ea1a 5884 /******************** Bits definition for DCMI_MIS register *****************/
NYX 0:85b3fd62ea1a 5885 #define DCMI_MIS_FRAME_MIS_Pos (0U)
NYX 0:85b3fd62ea1a 5886 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5887 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
NYX 0:85b3fd62ea1a 5888 #define DCMI_MIS_OVR_MIS_Pos (1U)
NYX 0:85b3fd62ea1a 5889 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5890 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
NYX 0:85b3fd62ea1a 5891 #define DCMI_MIS_ERR_MIS_Pos (2U)
NYX 0:85b3fd62ea1a 5892 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5893 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
NYX 0:85b3fd62ea1a 5894 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
NYX 0:85b3fd62ea1a 5895 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5896 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
NYX 0:85b3fd62ea1a 5897 #define DCMI_MIS_LINE_MIS_Pos (4U)
NYX 0:85b3fd62ea1a 5898 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5899 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
NYX 0:85b3fd62ea1a 5900
NYX 0:85b3fd62ea1a 5901 /* Legacy defines */
NYX 0:85b3fd62ea1a 5902 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
NYX 0:85b3fd62ea1a 5903 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
NYX 0:85b3fd62ea1a 5904 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
NYX 0:85b3fd62ea1a 5905 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
NYX 0:85b3fd62ea1a 5906 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
NYX 0:85b3fd62ea1a 5907
NYX 0:85b3fd62ea1a 5908 /******************** Bits definition for DCMI_ICR register *****************/
NYX 0:85b3fd62ea1a 5909 #define DCMI_ICR_FRAME_ISC_Pos (0U)
NYX 0:85b3fd62ea1a 5910 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 5911 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
NYX 0:85b3fd62ea1a 5912 #define DCMI_ICR_OVR_ISC_Pos (1U)
NYX 0:85b3fd62ea1a 5913 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 5914 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
NYX 0:85b3fd62ea1a 5915 #define DCMI_ICR_ERR_ISC_Pos (2U)
NYX 0:85b3fd62ea1a 5916 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 5917 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
NYX 0:85b3fd62ea1a 5918 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
NYX 0:85b3fd62ea1a 5919 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 5920 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
NYX 0:85b3fd62ea1a 5921 #define DCMI_ICR_LINE_ISC_Pos (4U)
NYX 0:85b3fd62ea1a 5922 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 5923 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
NYX 0:85b3fd62ea1a 5924
NYX 0:85b3fd62ea1a 5925 /* Legacy defines */
NYX 0:85b3fd62ea1a 5926 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
NYX 0:85b3fd62ea1a 5927
NYX 0:85b3fd62ea1a 5928 /******************** Bits definition for DCMI_ESCR register ******************/
NYX 0:85b3fd62ea1a 5929 #define DCMI_ESCR_FSC_Pos (0U)
NYX 0:85b3fd62ea1a 5930 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 5931 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
NYX 0:85b3fd62ea1a 5932 #define DCMI_ESCR_LSC_Pos (8U)
NYX 0:85b3fd62ea1a 5933 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 5934 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
NYX 0:85b3fd62ea1a 5935 #define DCMI_ESCR_LEC_Pos (16U)
NYX 0:85b3fd62ea1a 5936 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 5937 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
NYX 0:85b3fd62ea1a 5938 #define DCMI_ESCR_FEC_Pos (24U)
NYX 0:85b3fd62ea1a 5939 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 5940 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
NYX 0:85b3fd62ea1a 5941
NYX 0:85b3fd62ea1a 5942 /******************** Bits definition for DCMI_ESUR register ******************/
NYX 0:85b3fd62ea1a 5943 #define DCMI_ESUR_FSU_Pos (0U)
NYX 0:85b3fd62ea1a 5944 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 5945 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
NYX 0:85b3fd62ea1a 5946 #define DCMI_ESUR_LSU_Pos (8U)
NYX 0:85b3fd62ea1a 5947 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 5948 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
NYX 0:85b3fd62ea1a 5949 #define DCMI_ESUR_LEU_Pos (16U)
NYX 0:85b3fd62ea1a 5950 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 5951 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
NYX 0:85b3fd62ea1a 5952 #define DCMI_ESUR_FEU_Pos (24U)
NYX 0:85b3fd62ea1a 5953 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 5954 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
NYX 0:85b3fd62ea1a 5955
NYX 0:85b3fd62ea1a 5956 /******************** Bits definition for DCMI_CWSTRT register ******************/
NYX 0:85b3fd62ea1a 5957 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
NYX 0:85b3fd62ea1a 5958 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
NYX 0:85b3fd62ea1a 5959 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
NYX 0:85b3fd62ea1a 5960 #define DCMI_CWSTRT_VST_Pos (16U)
NYX 0:85b3fd62ea1a 5961 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
NYX 0:85b3fd62ea1a 5962 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
NYX 0:85b3fd62ea1a 5963
NYX 0:85b3fd62ea1a 5964 /******************** Bits definition for DCMI_CWSIZE register ******************/
NYX 0:85b3fd62ea1a 5965 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
NYX 0:85b3fd62ea1a 5966 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
NYX 0:85b3fd62ea1a 5967 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
NYX 0:85b3fd62ea1a 5968 #define DCMI_CWSIZE_VLINE_Pos (16U)
NYX 0:85b3fd62ea1a 5969 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
NYX 0:85b3fd62ea1a 5970 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
NYX 0:85b3fd62ea1a 5971
NYX 0:85b3fd62ea1a 5972 /******************** Bits definition for DCMI_DR register *********************/
NYX 0:85b3fd62ea1a 5973 #define DCMI_DR_BYTE0_Pos (0U)
NYX 0:85b3fd62ea1a 5974 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 5975 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
NYX 0:85b3fd62ea1a 5976 #define DCMI_DR_BYTE1_Pos (8U)
NYX 0:85b3fd62ea1a 5977 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 5978 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
NYX 0:85b3fd62ea1a 5979 #define DCMI_DR_BYTE2_Pos (16U)
NYX 0:85b3fd62ea1a 5980 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 5981 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
NYX 0:85b3fd62ea1a 5982 #define DCMI_DR_BYTE3_Pos (24U)
NYX 0:85b3fd62ea1a 5983 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 5984 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
NYX 0:85b3fd62ea1a 5985
NYX 0:85b3fd62ea1a 5986 /******************************************************************************/
NYX 0:85b3fd62ea1a 5987 /* */
NYX 0:85b3fd62ea1a 5988 /* DMA Controller */
NYX 0:85b3fd62ea1a 5989 /* */
NYX 0:85b3fd62ea1a 5990 /******************************************************************************/
NYX 0:85b3fd62ea1a 5991 /******************** Bits definition for DMA_SxCR register *****************/
NYX 0:85b3fd62ea1a 5992 #define DMA_SxCR_CHSEL_Pos (25U)
NYX 0:85b3fd62ea1a 5993 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
NYX 0:85b3fd62ea1a 5994 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
NYX 0:85b3fd62ea1a 5995 #define DMA_SxCR_CHSEL_0 0x02000000U
NYX 0:85b3fd62ea1a 5996 #define DMA_SxCR_CHSEL_1 0x04000000U
NYX 0:85b3fd62ea1a 5997 #define DMA_SxCR_CHSEL_2 0x08000000U
NYX 0:85b3fd62ea1a 5998 #define DMA_SxCR_MBURST_Pos (23U)
NYX 0:85b3fd62ea1a 5999 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
NYX 0:85b3fd62ea1a 6000 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
NYX 0:85b3fd62ea1a 6001 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 6002 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 6003 #define DMA_SxCR_PBURST_Pos (21U)
NYX 0:85b3fd62ea1a 6004 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
NYX 0:85b3fd62ea1a 6005 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
NYX 0:85b3fd62ea1a 6006 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6007 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6008 #define DMA_SxCR_CT_Pos (19U)
NYX 0:85b3fd62ea1a 6009 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6010 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
NYX 0:85b3fd62ea1a 6011 #define DMA_SxCR_DBM_Pos (18U)
NYX 0:85b3fd62ea1a 6012 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6013 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
NYX 0:85b3fd62ea1a 6014 #define DMA_SxCR_PL_Pos (16U)
NYX 0:85b3fd62ea1a 6015 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 6016 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
NYX 0:85b3fd62ea1a 6017 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6018 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 6019 #define DMA_SxCR_PINCOS_Pos (15U)
NYX 0:85b3fd62ea1a 6020 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 6021 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
NYX 0:85b3fd62ea1a 6022 #define DMA_SxCR_MSIZE_Pos (13U)
NYX 0:85b3fd62ea1a 6023 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
NYX 0:85b3fd62ea1a 6024 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
NYX 0:85b3fd62ea1a 6025 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 6026 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 6027 #define DMA_SxCR_PSIZE_Pos (11U)
NYX 0:85b3fd62ea1a 6028 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
NYX 0:85b3fd62ea1a 6029 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
NYX 0:85b3fd62ea1a 6030 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6031 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 6032 #define DMA_SxCR_MINC_Pos (10U)
NYX 0:85b3fd62ea1a 6033 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6034 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
NYX 0:85b3fd62ea1a 6035 #define DMA_SxCR_PINC_Pos (9U)
NYX 0:85b3fd62ea1a 6036 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6037 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
NYX 0:85b3fd62ea1a 6038 #define DMA_SxCR_CIRC_Pos (8U)
NYX 0:85b3fd62ea1a 6039 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6040 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
NYX 0:85b3fd62ea1a 6041 #define DMA_SxCR_DIR_Pos (6U)
NYX 0:85b3fd62ea1a 6042 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 6043 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
NYX 0:85b3fd62ea1a 6044 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6045 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6046 #define DMA_SxCR_PFCTRL_Pos (5U)
NYX 0:85b3fd62ea1a 6047 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6048 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
NYX 0:85b3fd62ea1a 6049 #define DMA_SxCR_TCIE_Pos (4U)
NYX 0:85b3fd62ea1a 6050 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6051 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
NYX 0:85b3fd62ea1a 6052 #define DMA_SxCR_HTIE_Pos (3U)
NYX 0:85b3fd62ea1a 6053 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6054 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
NYX 0:85b3fd62ea1a 6055 #define DMA_SxCR_TEIE_Pos (2U)
NYX 0:85b3fd62ea1a 6056 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6057 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
NYX 0:85b3fd62ea1a 6058 #define DMA_SxCR_DMEIE_Pos (1U)
NYX 0:85b3fd62ea1a 6059 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6060 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
NYX 0:85b3fd62ea1a 6061 #define DMA_SxCR_EN_Pos (0U)
NYX 0:85b3fd62ea1a 6062 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6063 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
NYX 0:85b3fd62ea1a 6064
NYX 0:85b3fd62ea1a 6065 /* Legacy defines */
NYX 0:85b3fd62ea1a 6066 #define DMA_SxCR_ACK_Pos (20U)
NYX 0:85b3fd62ea1a 6067 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6068 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
NYX 0:85b3fd62ea1a 6069
NYX 0:85b3fd62ea1a 6070 /******************** Bits definition for DMA_SxCNDTR register **************/
NYX 0:85b3fd62ea1a 6071 #define DMA_SxNDT_Pos (0U)
NYX 0:85b3fd62ea1a 6072 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 6073 #define DMA_SxNDT DMA_SxNDT_Msk
NYX 0:85b3fd62ea1a 6074 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6075 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6076 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6077 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6078 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6079 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6080 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6081 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6082 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6083 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6084 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6085 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6086 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 6087 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 6088 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 6089 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 6090
NYX 0:85b3fd62ea1a 6091 /******************** Bits definition for DMA_SxFCR register ****************/
NYX 0:85b3fd62ea1a 6092 #define DMA_SxFCR_FEIE_Pos (7U)
NYX 0:85b3fd62ea1a 6093 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6094 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
NYX 0:85b3fd62ea1a 6095 #define DMA_SxFCR_FS_Pos (3U)
NYX 0:85b3fd62ea1a 6096 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
NYX 0:85b3fd62ea1a 6097 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
NYX 0:85b3fd62ea1a 6098 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6099 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6100 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6101 #define DMA_SxFCR_DMDIS_Pos (2U)
NYX 0:85b3fd62ea1a 6102 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6103 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
NYX 0:85b3fd62ea1a 6104 #define DMA_SxFCR_FTH_Pos (0U)
NYX 0:85b3fd62ea1a 6105 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 6106 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
NYX 0:85b3fd62ea1a 6107 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6108 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6109
NYX 0:85b3fd62ea1a 6110 /******************** Bits definition for DMA_LISR register *****************/
NYX 0:85b3fd62ea1a 6111 #define DMA_LISR_TCIF3_Pos (27U)
NYX 0:85b3fd62ea1a 6112 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 6113 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
NYX 0:85b3fd62ea1a 6114 #define DMA_LISR_HTIF3_Pos (26U)
NYX 0:85b3fd62ea1a 6115 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 6116 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
NYX 0:85b3fd62ea1a 6117 #define DMA_LISR_TEIF3_Pos (25U)
NYX 0:85b3fd62ea1a 6118 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 6119 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
NYX 0:85b3fd62ea1a 6120 #define DMA_LISR_DMEIF3_Pos (24U)
NYX 0:85b3fd62ea1a 6121 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 6122 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
NYX 0:85b3fd62ea1a 6123 #define DMA_LISR_FEIF3_Pos (22U)
NYX 0:85b3fd62ea1a 6124 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6125 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
NYX 0:85b3fd62ea1a 6126 #define DMA_LISR_TCIF2_Pos (21U)
NYX 0:85b3fd62ea1a 6127 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6128 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
NYX 0:85b3fd62ea1a 6129 #define DMA_LISR_HTIF2_Pos (20U)
NYX 0:85b3fd62ea1a 6130 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6131 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
NYX 0:85b3fd62ea1a 6132 #define DMA_LISR_TEIF2_Pos (19U)
NYX 0:85b3fd62ea1a 6133 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6134 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
NYX 0:85b3fd62ea1a 6135 #define DMA_LISR_DMEIF2_Pos (18U)
NYX 0:85b3fd62ea1a 6136 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6137 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
NYX 0:85b3fd62ea1a 6138 #define DMA_LISR_FEIF2_Pos (16U)
NYX 0:85b3fd62ea1a 6139 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6140 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
NYX 0:85b3fd62ea1a 6141 #define DMA_LISR_TCIF1_Pos (11U)
NYX 0:85b3fd62ea1a 6142 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6143 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
NYX 0:85b3fd62ea1a 6144 #define DMA_LISR_HTIF1_Pos (10U)
NYX 0:85b3fd62ea1a 6145 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6146 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
NYX 0:85b3fd62ea1a 6147 #define DMA_LISR_TEIF1_Pos (9U)
NYX 0:85b3fd62ea1a 6148 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6149 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
NYX 0:85b3fd62ea1a 6150 #define DMA_LISR_DMEIF1_Pos (8U)
NYX 0:85b3fd62ea1a 6151 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6152 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
NYX 0:85b3fd62ea1a 6153 #define DMA_LISR_FEIF1_Pos (6U)
NYX 0:85b3fd62ea1a 6154 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6155 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
NYX 0:85b3fd62ea1a 6156 #define DMA_LISR_TCIF0_Pos (5U)
NYX 0:85b3fd62ea1a 6157 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6158 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
NYX 0:85b3fd62ea1a 6159 #define DMA_LISR_HTIF0_Pos (4U)
NYX 0:85b3fd62ea1a 6160 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6161 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
NYX 0:85b3fd62ea1a 6162 #define DMA_LISR_TEIF0_Pos (3U)
NYX 0:85b3fd62ea1a 6163 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6164 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
NYX 0:85b3fd62ea1a 6165 #define DMA_LISR_DMEIF0_Pos (2U)
NYX 0:85b3fd62ea1a 6166 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6167 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
NYX 0:85b3fd62ea1a 6168 #define DMA_LISR_FEIF0_Pos (0U)
NYX 0:85b3fd62ea1a 6169 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6170 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
NYX 0:85b3fd62ea1a 6171
NYX 0:85b3fd62ea1a 6172 /******************** Bits definition for DMA_HISR register *****************/
NYX 0:85b3fd62ea1a 6173 #define DMA_HISR_TCIF7_Pos (27U)
NYX 0:85b3fd62ea1a 6174 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 6175 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
NYX 0:85b3fd62ea1a 6176 #define DMA_HISR_HTIF7_Pos (26U)
NYX 0:85b3fd62ea1a 6177 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 6178 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
NYX 0:85b3fd62ea1a 6179 #define DMA_HISR_TEIF7_Pos (25U)
NYX 0:85b3fd62ea1a 6180 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 6181 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
NYX 0:85b3fd62ea1a 6182 #define DMA_HISR_DMEIF7_Pos (24U)
NYX 0:85b3fd62ea1a 6183 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 6184 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
NYX 0:85b3fd62ea1a 6185 #define DMA_HISR_FEIF7_Pos (22U)
NYX 0:85b3fd62ea1a 6186 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6187 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
NYX 0:85b3fd62ea1a 6188 #define DMA_HISR_TCIF6_Pos (21U)
NYX 0:85b3fd62ea1a 6189 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6190 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
NYX 0:85b3fd62ea1a 6191 #define DMA_HISR_HTIF6_Pos (20U)
NYX 0:85b3fd62ea1a 6192 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6193 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
NYX 0:85b3fd62ea1a 6194 #define DMA_HISR_TEIF6_Pos (19U)
NYX 0:85b3fd62ea1a 6195 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6196 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
NYX 0:85b3fd62ea1a 6197 #define DMA_HISR_DMEIF6_Pos (18U)
NYX 0:85b3fd62ea1a 6198 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6199 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
NYX 0:85b3fd62ea1a 6200 #define DMA_HISR_FEIF6_Pos (16U)
NYX 0:85b3fd62ea1a 6201 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6202 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
NYX 0:85b3fd62ea1a 6203 #define DMA_HISR_TCIF5_Pos (11U)
NYX 0:85b3fd62ea1a 6204 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6205 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
NYX 0:85b3fd62ea1a 6206 #define DMA_HISR_HTIF5_Pos (10U)
NYX 0:85b3fd62ea1a 6207 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6208 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
NYX 0:85b3fd62ea1a 6209 #define DMA_HISR_TEIF5_Pos (9U)
NYX 0:85b3fd62ea1a 6210 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6211 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
NYX 0:85b3fd62ea1a 6212 #define DMA_HISR_DMEIF5_Pos (8U)
NYX 0:85b3fd62ea1a 6213 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6214 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
NYX 0:85b3fd62ea1a 6215 #define DMA_HISR_FEIF5_Pos (6U)
NYX 0:85b3fd62ea1a 6216 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6217 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
NYX 0:85b3fd62ea1a 6218 #define DMA_HISR_TCIF4_Pos (5U)
NYX 0:85b3fd62ea1a 6219 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6220 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
NYX 0:85b3fd62ea1a 6221 #define DMA_HISR_HTIF4_Pos (4U)
NYX 0:85b3fd62ea1a 6222 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6223 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
NYX 0:85b3fd62ea1a 6224 #define DMA_HISR_TEIF4_Pos (3U)
NYX 0:85b3fd62ea1a 6225 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6226 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
NYX 0:85b3fd62ea1a 6227 #define DMA_HISR_DMEIF4_Pos (2U)
NYX 0:85b3fd62ea1a 6228 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6229 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
NYX 0:85b3fd62ea1a 6230 #define DMA_HISR_FEIF4_Pos (0U)
NYX 0:85b3fd62ea1a 6231 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6232 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
NYX 0:85b3fd62ea1a 6233
NYX 0:85b3fd62ea1a 6234 /******************** Bits definition for DMA_LIFCR register ****************/
NYX 0:85b3fd62ea1a 6235 #define DMA_LIFCR_CTCIF3_Pos (27U)
NYX 0:85b3fd62ea1a 6236 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 6237 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
NYX 0:85b3fd62ea1a 6238 #define DMA_LIFCR_CHTIF3_Pos (26U)
NYX 0:85b3fd62ea1a 6239 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 6240 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
NYX 0:85b3fd62ea1a 6241 #define DMA_LIFCR_CTEIF3_Pos (25U)
NYX 0:85b3fd62ea1a 6242 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 6243 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
NYX 0:85b3fd62ea1a 6244 #define DMA_LIFCR_CDMEIF3_Pos (24U)
NYX 0:85b3fd62ea1a 6245 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 6246 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
NYX 0:85b3fd62ea1a 6247 #define DMA_LIFCR_CFEIF3_Pos (22U)
NYX 0:85b3fd62ea1a 6248 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6249 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
NYX 0:85b3fd62ea1a 6250 #define DMA_LIFCR_CTCIF2_Pos (21U)
NYX 0:85b3fd62ea1a 6251 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6252 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
NYX 0:85b3fd62ea1a 6253 #define DMA_LIFCR_CHTIF2_Pos (20U)
NYX 0:85b3fd62ea1a 6254 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6255 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
NYX 0:85b3fd62ea1a 6256 #define DMA_LIFCR_CTEIF2_Pos (19U)
NYX 0:85b3fd62ea1a 6257 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6258 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
NYX 0:85b3fd62ea1a 6259 #define DMA_LIFCR_CDMEIF2_Pos (18U)
NYX 0:85b3fd62ea1a 6260 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6261 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
NYX 0:85b3fd62ea1a 6262 #define DMA_LIFCR_CFEIF2_Pos (16U)
NYX 0:85b3fd62ea1a 6263 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6264 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
NYX 0:85b3fd62ea1a 6265 #define DMA_LIFCR_CTCIF1_Pos (11U)
NYX 0:85b3fd62ea1a 6266 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6267 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
NYX 0:85b3fd62ea1a 6268 #define DMA_LIFCR_CHTIF1_Pos (10U)
NYX 0:85b3fd62ea1a 6269 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6270 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
NYX 0:85b3fd62ea1a 6271 #define DMA_LIFCR_CTEIF1_Pos (9U)
NYX 0:85b3fd62ea1a 6272 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6273 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
NYX 0:85b3fd62ea1a 6274 #define DMA_LIFCR_CDMEIF1_Pos (8U)
NYX 0:85b3fd62ea1a 6275 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6276 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
NYX 0:85b3fd62ea1a 6277 #define DMA_LIFCR_CFEIF1_Pos (6U)
NYX 0:85b3fd62ea1a 6278 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6279 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
NYX 0:85b3fd62ea1a 6280 #define DMA_LIFCR_CTCIF0_Pos (5U)
NYX 0:85b3fd62ea1a 6281 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6282 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
NYX 0:85b3fd62ea1a 6283 #define DMA_LIFCR_CHTIF0_Pos (4U)
NYX 0:85b3fd62ea1a 6284 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6285 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
NYX 0:85b3fd62ea1a 6286 #define DMA_LIFCR_CTEIF0_Pos (3U)
NYX 0:85b3fd62ea1a 6287 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6288 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
NYX 0:85b3fd62ea1a 6289 #define DMA_LIFCR_CDMEIF0_Pos (2U)
NYX 0:85b3fd62ea1a 6290 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6291 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
NYX 0:85b3fd62ea1a 6292 #define DMA_LIFCR_CFEIF0_Pos (0U)
NYX 0:85b3fd62ea1a 6293 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6294 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
NYX 0:85b3fd62ea1a 6295
NYX 0:85b3fd62ea1a 6296 /******************** Bits definition for DMA_HIFCR register ****************/
NYX 0:85b3fd62ea1a 6297 #define DMA_HIFCR_CTCIF7_Pos (27U)
NYX 0:85b3fd62ea1a 6298 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 6299 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
NYX 0:85b3fd62ea1a 6300 #define DMA_HIFCR_CHTIF7_Pos (26U)
NYX 0:85b3fd62ea1a 6301 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 6302 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
NYX 0:85b3fd62ea1a 6303 #define DMA_HIFCR_CTEIF7_Pos (25U)
NYX 0:85b3fd62ea1a 6304 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 6305 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
NYX 0:85b3fd62ea1a 6306 #define DMA_HIFCR_CDMEIF7_Pos (24U)
NYX 0:85b3fd62ea1a 6307 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 6308 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
NYX 0:85b3fd62ea1a 6309 #define DMA_HIFCR_CFEIF7_Pos (22U)
NYX 0:85b3fd62ea1a 6310 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6311 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
NYX 0:85b3fd62ea1a 6312 #define DMA_HIFCR_CTCIF6_Pos (21U)
NYX 0:85b3fd62ea1a 6313 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6314 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
NYX 0:85b3fd62ea1a 6315 #define DMA_HIFCR_CHTIF6_Pos (20U)
NYX 0:85b3fd62ea1a 6316 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6317 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
NYX 0:85b3fd62ea1a 6318 #define DMA_HIFCR_CTEIF6_Pos (19U)
NYX 0:85b3fd62ea1a 6319 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6320 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
NYX 0:85b3fd62ea1a 6321 #define DMA_HIFCR_CDMEIF6_Pos (18U)
NYX 0:85b3fd62ea1a 6322 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6323 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
NYX 0:85b3fd62ea1a 6324 #define DMA_HIFCR_CFEIF6_Pos (16U)
NYX 0:85b3fd62ea1a 6325 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6326 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
NYX 0:85b3fd62ea1a 6327 #define DMA_HIFCR_CTCIF5_Pos (11U)
NYX 0:85b3fd62ea1a 6328 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6329 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
NYX 0:85b3fd62ea1a 6330 #define DMA_HIFCR_CHTIF5_Pos (10U)
NYX 0:85b3fd62ea1a 6331 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6332 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
NYX 0:85b3fd62ea1a 6333 #define DMA_HIFCR_CTEIF5_Pos (9U)
NYX 0:85b3fd62ea1a 6334 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6335 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
NYX 0:85b3fd62ea1a 6336 #define DMA_HIFCR_CDMEIF5_Pos (8U)
NYX 0:85b3fd62ea1a 6337 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6338 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
NYX 0:85b3fd62ea1a 6339 #define DMA_HIFCR_CFEIF5_Pos (6U)
NYX 0:85b3fd62ea1a 6340 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6341 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
NYX 0:85b3fd62ea1a 6342 #define DMA_HIFCR_CTCIF4_Pos (5U)
NYX 0:85b3fd62ea1a 6343 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6344 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
NYX 0:85b3fd62ea1a 6345 #define DMA_HIFCR_CHTIF4_Pos (4U)
NYX 0:85b3fd62ea1a 6346 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6347 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
NYX 0:85b3fd62ea1a 6348 #define DMA_HIFCR_CTEIF4_Pos (3U)
NYX 0:85b3fd62ea1a 6349 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6350 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
NYX 0:85b3fd62ea1a 6351 #define DMA_HIFCR_CDMEIF4_Pos (2U)
NYX 0:85b3fd62ea1a 6352 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6353 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
NYX 0:85b3fd62ea1a 6354 #define DMA_HIFCR_CFEIF4_Pos (0U)
NYX 0:85b3fd62ea1a 6355 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6356 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
NYX 0:85b3fd62ea1a 6357
NYX 0:85b3fd62ea1a 6358 /****************** Bit definition for DMA_SxPAR register ********************/
NYX 0:85b3fd62ea1a 6359 #define DMA_SxPAR_PA_Pos (0U)
NYX 0:85b3fd62ea1a 6360 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 6361 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
NYX 0:85b3fd62ea1a 6362
NYX 0:85b3fd62ea1a 6363 /****************** Bit definition for DMA_SxM0AR register ********************/
NYX 0:85b3fd62ea1a 6364 #define DMA_SxM0AR_M0A_Pos (0U)
NYX 0:85b3fd62ea1a 6365 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 6366 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
NYX 0:85b3fd62ea1a 6367
NYX 0:85b3fd62ea1a 6368 /****************** Bit definition for DMA_SxM1AR register ********************/
NYX 0:85b3fd62ea1a 6369 #define DMA_SxM1AR_M1A_Pos (0U)
NYX 0:85b3fd62ea1a 6370 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 6371 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
NYX 0:85b3fd62ea1a 6372
NYX 0:85b3fd62ea1a 6373
NYX 0:85b3fd62ea1a 6374 /******************************************************************************/
NYX 0:85b3fd62ea1a 6375 /* */
NYX 0:85b3fd62ea1a 6376 /* External Interrupt/Event Controller */
NYX 0:85b3fd62ea1a 6377 /* */
NYX 0:85b3fd62ea1a 6378 /******************************************************************************/
NYX 0:85b3fd62ea1a 6379 /******************* Bit definition for EXTI_IMR register *******************/
NYX 0:85b3fd62ea1a 6380 #define EXTI_IMR_MR0_Pos (0U)
NYX 0:85b3fd62ea1a 6381 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6382 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
NYX 0:85b3fd62ea1a 6383 #define EXTI_IMR_MR1_Pos (1U)
NYX 0:85b3fd62ea1a 6384 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6385 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
NYX 0:85b3fd62ea1a 6386 #define EXTI_IMR_MR2_Pos (2U)
NYX 0:85b3fd62ea1a 6387 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6388 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
NYX 0:85b3fd62ea1a 6389 #define EXTI_IMR_MR3_Pos (3U)
NYX 0:85b3fd62ea1a 6390 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6391 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
NYX 0:85b3fd62ea1a 6392 #define EXTI_IMR_MR4_Pos (4U)
NYX 0:85b3fd62ea1a 6393 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6394 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
NYX 0:85b3fd62ea1a 6395 #define EXTI_IMR_MR5_Pos (5U)
NYX 0:85b3fd62ea1a 6396 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6397 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
NYX 0:85b3fd62ea1a 6398 #define EXTI_IMR_MR6_Pos (6U)
NYX 0:85b3fd62ea1a 6399 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6400 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
NYX 0:85b3fd62ea1a 6401 #define EXTI_IMR_MR7_Pos (7U)
NYX 0:85b3fd62ea1a 6402 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6403 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
NYX 0:85b3fd62ea1a 6404 #define EXTI_IMR_MR8_Pos (8U)
NYX 0:85b3fd62ea1a 6405 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6406 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
NYX 0:85b3fd62ea1a 6407 #define EXTI_IMR_MR9_Pos (9U)
NYX 0:85b3fd62ea1a 6408 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6409 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
NYX 0:85b3fd62ea1a 6410 #define EXTI_IMR_MR10_Pos (10U)
NYX 0:85b3fd62ea1a 6411 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6412 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
NYX 0:85b3fd62ea1a 6413 #define EXTI_IMR_MR11_Pos (11U)
NYX 0:85b3fd62ea1a 6414 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6415 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
NYX 0:85b3fd62ea1a 6416 #define EXTI_IMR_MR12_Pos (12U)
NYX 0:85b3fd62ea1a 6417 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 6418 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
NYX 0:85b3fd62ea1a 6419 #define EXTI_IMR_MR13_Pos (13U)
NYX 0:85b3fd62ea1a 6420 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 6421 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
NYX 0:85b3fd62ea1a 6422 #define EXTI_IMR_MR14_Pos (14U)
NYX 0:85b3fd62ea1a 6423 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 6424 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
NYX 0:85b3fd62ea1a 6425 #define EXTI_IMR_MR15_Pos (15U)
NYX 0:85b3fd62ea1a 6426 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 6427 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
NYX 0:85b3fd62ea1a 6428 #define EXTI_IMR_MR16_Pos (16U)
NYX 0:85b3fd62ea1a 6429 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6430 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
NYX 0:85b3fd62ea1a 6431 #define EXTI_IMR_MR17_Pos (17U)
NYX 0:85b3fd62ea1a 6432 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 6433 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
NYX 0:85b3fd62ea1a 6434 #define EXTI_IMR_MR18_Pos (18U)
NYX 0:85b3fd62ea1a 6435 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6436 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
NYX 0:85b3fd62ea1a 6437 #define EXTI_IMR_MR19_Pos (19U)
NYX 0:85b3fd62ea1a 6438 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6439 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
NYX 0:85b3fd62ea1a 6440 #define EXTI_IMR_MR20_Pos (20U)
NYX 0:85b3fd62ea1a 6441 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6442 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
NYX 0:85b3fd62ea1a 6443 #define EXTI_IMR_MR21_Pos (21U)
NYX 0:85b3fd62ea1a 6444 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6445 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
NYX 0:85b3fd62ea1a 6446 #define EXTI_IMR_MR22_Pos (22U)
NYX 0:85b3fd62ea1a 6447 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6448 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
NYX 0:85b3fd62ea1a 6449
NYX 0:85b3fd62ea1a 6450 /* Reference Defines */
NYX 0:85b3fd62ea1a 6451 #define EXTI_IMR_IM0 EXTI_IMR_MR0
NYX 0:85b3fd62ea1a 6452 #define EXTI_IMR_IM1 EXTI_IMR_MR1
NYX 0:85b3fd62ea1a 6453 #define EXTI_IMR_IM2 EXTI_IMR_MR2
NYX 0:85b3fd62ea1a 6454 #define EXTI_IMR_IM3 EXTI_IMR_MR3
NYX 0:85b3fd62ea1a 6455 #define EXTI_IMR_IM4 EXTI_IMR_MR4
NYX 0:85b3fd62ea1a 6456 #define EXTI_IMR_IM5 EXTI_IMR_MR5
NYX 0:85b3fd62ea1a 6457 #define EXTI_IMR_IM6 EXTI_IMR_MR6
NYX 0:85b3fd62ea1a 6458 #define EXTI_IMR_IM7 EXTI_IMR_MR7
NYX 0:85b3fd62ea1a 6459 #define EXTI_IMR_IM8 EXTI_IMR_MR8
NYX 0:85b3fd62ea1a 6460 #define EXTI_IMR_IM9 EXTI_IMR_MR9
NYX 0:85b3fd62ea1a 6461 #define EXTI_IMR_IM10 EXTI_IMR_MR10
NYX 0:85b3fd62ea1a 6462 #define EXTI_IMR_IM11 EXTI_IMR_MR11
NYX 0:85b3fd62ea1a 6463 #define EXTI_IMR_IM12 EXTI_IMR_MR12
NYX 0:85b3fd62ea1a 6464 #define EXTI_IMR_IM13 EXTI_IMR_MR13
NYX 0:85b3fd62ea1a 6465 #define EXTI_IMR_IM14 EXTI_IMR_MR14
NYX 0:85b3fd62ea1a 6466 #define EXTI_IMR_IM15 EXTI_IMR_MR15
NYX 0:85b3fd62ea1a 6467 #define EXTI_IMR_IM16 EXTI_IMR_MR16
NYX 0:85b3fd62ea1a 6468 #define EXTI_IMR_IM17 EXTI_IMR_MR17
NYX 0:85b3fd62ea1a 6469 #define EXTI_IMR_IM18 EXTI_IMR_MR18
NYX 0:85b3fd62ea1a 6470 #define EXTI_IMR_IM19 EXTI_IMR_MR19
NYX 0:85b3fd62ea1a 6471 #define EXTI_IMR_IM20 EXTI_IMR_MR20
NYX 0:85b3fd62ea1a 6472 #define EXTI_IMR_IM21 EXTI_IMR_MR21
NYX 0:85b3fd62ea1a 6473 #define EXTI_IMR_IM22 EXTI_IMR_MR22
NYX 0:85b3fd62ea1a 6474 #define EXTI_IMR_IM_Pos (0U)
NYX 0:85b3fd62ea1a 6475 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
NYX 0:85b3fd62ea1a 6476 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
NYX 0:85b3fd62ea1a 6477
NYX 0:85b3fd62ea1a 6478 /******************* Bit definition for EXTI_EMR register *******************/
NYX 0:85b3fd62ea1a 6479 #define EXTI_EMR_MR0_Pos (0U)
NYX 0:85b3fd62ea1a 6480 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6481 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
NYX 0:85b3fd62ea1a 6482 #define EXTI_EMR_MR1_Pos (1U)
NYX 0:85b3fd62ea1a 6483 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6484 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
NYX 0:85b3fd62ea1a 6485 #define EXTI_EMR_MR2_Pos (2U)
NYX 0:85b3fd62ea1a 6486 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6487 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
NYX 0:85b3fd62ea1a 6488 #define EXTI_EMR_MR3_Pos (3U)
NYX 0:85b3fd62ea1a 6489 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6490 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
NYX 0:85b3fd62ea1a 6491 #define EXTI_EMR_MR4_Pos (4U)
NYX 0:85b3fd62ea1a 6492 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6493 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
NYX 0:85b3fd62ea1a 6494 #define EXTI_EMR_MR5_Pos (5U)
NYX 0:85b3fd62ea1a 6495 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6496 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
NYX 0:85b3fd62ea1a 6497 #define EXTI_EMR_MR6_Pos (6U)
NYX 0:85b3fd62ea1a 6498 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6499 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
NYX 0:85b3fd62ea1a 6500 #define EXTI_EMR_MR7_Pos (7U)
NYX 0:85b3fd62ea1a 6501 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6502 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
NYX 0:85b3fd62ea1a 6503 #define EXTI_EMR_MR8_Pos (8U)
NYX 0:85b3fd62ea1a 6504 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6505 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
NYX 0:85b3fd62ea1a 6506 #define EXTI_EMR_MR9_Pos (9U)
NYX 0:85b3fd62ea1a 6507 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6508 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
NYX 0:85b3fd62ea1a 6509 #define EXTI_EMR_MR10_Pos (10U)
NYX 0:85b3fd62ea1a 6510 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6511 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
NYX 0:85b3fd62ea1a 6512 #define EXTI_EMR_MR11_Pos (11U)
NYX 0:85b3fd62ea1a 6513 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6514 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
NYX 0:85b3fd62ea1a 6515 #define EXTI_EMR_MR12_Pos (12U)
NYX 0:85b3fd62ea1a 6516 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 6517 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
NYX 0:85b3fd62ea1a 6518 #define EXTI_EMR_MR13_Pos (13U)
NYX 0:85b3fd62ea1a 6519 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 6520 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
NYX 0:85b3fd62ea1a 6521 #define EXTI_EMR_MR14_Pos (14U)
NYX 0:85b3fd62ea1a 6522 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 6523 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
NYX 0:85b3fd62ea1a 6524 #define EXTI_EMR_MR15_Pos (15U)
NYX 0:85b3fd62ea1a 6525 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 6526 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
NYX 0:85b3fd62ea1a 6527 #define EXTI_EMR_MR16_Pos (16U)
NYX 0:85b3fd62ea1a 6528 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6529 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
NYX 0:85b3fd62ea1a 6530 #define EXTI_EMR_MR17_Pos (17U)
NYX 0:85b3fd62ea1a 6531 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 6532 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
NYX 0:85b3fd62ea1a 6533 #define EXTI_EMR_MR18_Pos (18U)
NYX 0:85b3fd62ea1a 6534 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6535 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
NYX 0:85b3fd62ea1a 6536 #define EXTI_EMR_MR19_Pos (19U)
NYX 0:85b3fd62ea1a 6537 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6538 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
NYX 0:85b3fd62ea1a 6539 #define EXTI_EMR_MR20_Pos (20U)
NYX 0:85b3fd62ea1a 6540 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6541 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
NYX 0:85b3fd62ea1a 6542 #define EXTI_EMR_MR21_Pos (21U)
NYX 0:85b3fd62ea1a 6543 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6544 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
NYX 0:85b3fd62ea1a 6545 #define EXTI_EMR_MR22_Pos (22U)
NYX 0:85b3fd62ea1a 6546 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6547 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
NYX 0:85b3fd62ea1a 6548
NYX 0:85b3fd62ea1a 6549 /* Reference Defines */
NYX 0:85b3fd62ea1a 6550 #define EXTI_EMR_EM0 EXTI_EMR_MR0
NYX 0:85b3fd62ea1a 6551 #define EXTI_EMR_EM1 EXTI_EMR_MR1
NYX 0:85b3fd62ea1a 6552 #define EXTI_EMR_EM2 EXTI_EMR_MR2
NYX 0:85b3fd62ea1a 6553 #define EXTI_EMR_EM3 EXTI_EMR_MR3
NYX 0:85b3fd62ea1a 6554 #define EXTI_EMR_EM4 EXTI_EMR_MR4
NYX 0:85b3fd62ea1a 6555 #define EXTI_EMR_EM5 EXTI_EMR_MR5
NYX 0:85b3fd62ea1a 6556 #define EXTI_EMR_EM6 EXTI_EMR_MR6
NYX 0:85b3fd62ea1a 6557 #define EXTI_EMR_EM7 EXTI_EMR_MR7
NYX 0:85b3fd62ea1a 6558 #define EXTI_EMR_EM8 EXTI_EMR_MR8
NYX 0:85b3fd62ea1a 6559 #define EXTI_EMR_EM9 EXTI_EMR_MR9
NYX 0:85b3fd62ea1a 6560 #define EXTI_EMR_EM10 EXTI_EMR_MR10
NYX 0:85b3fd62ea1a 6561 #define EXTI_EMR_EM11 EXTI_EMR_MR11
NYX 0:85b3fd62ea1a 6562 #define EXTI_EMR_EM12 EXTI_EMR_MR12
NYX 0:85b3fd62ea1a 6563 #define EXTI_EMR_EM13 EXTI_EMR_MR13
NYX 0:85b3fd62ea1a 6564 #define EXTI_EMR_EM14 EXTI_EMR_MR14
NYX 0:85b3fd62ea1a 6565 #define EXTI_EMR_EM15 EXTI_EMR_MR15
NYX 0:85b3fd62ea1a 6566 #define EXTI_EMR_EM16 EXTI_EMR_MR16
NYX 0:85b3fd62ea1a 6567 #define EXTI_EMR_EM17 EXTI_EMR_MR17
NYX 0:85b3fd62ea1a 6568 #define EXTI_EMR_EM18 EXTI_EMR_MR18
NYX 0:85b3fd62ea1a 6569 #define EXTI_EMR_EM19 EXTI_EMR_MR19
NYX 0:85b3fd62ea1a 6570 #define EXTI_EMR_EM20 EXTI_EMR_MR20
NYX 0:85b3fd62ea1a 6571 #define EXTI_EMR_EM21 EXTI_EMR_MR21
NYX 0:85b3fd62ea1a 6572 #define EXTI_EMR_EM22 EXTI_EMR_MR22
NYX 0:85b3fd62ea1a 6573
NYX 0:85b3fd62ea1a 6574 /****************** Bit definition for EXTI_RTSR register *******************/
NYX 0:85b3fd62ea1a 6575 #define EXTI_RTSR_TR0_Pos (0U)
NYX 0:85b3fd62ea1a 6576 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6577 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
NYX 0:85b3fd62ea1a 6578 #define EXTI_RTSR_TR1_Pos (1U)
NYX 0:85b3fd62ea1a 6579 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6580 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
NYX 0:85b3fd62ea1a 6581 #define EXTI_RTSR_TR2_Pos (2U)
NYX 0:85b3fd62ea1a 6582 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6583 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
NYX 0:85b3fd62ea1a 6584 #define EXTI_RTSR_TR3_Pos (3U)
NYX 0:85b3fd62ea1a 6585 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6586 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
NYX 0:85b3fd62ea1a 6587 #define EXTI_RTSR_TR4_Pos (4U)
NYX 0:85b3fd62ea1a 6588 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6589 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
NYX 0:85b3fd62ea1a 6590 #define EXTI_RTSR_TR5_Pos (5U)
NYX 0:85b3fd62ea1a 6591 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6592 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
NYX 0:85b3fd62ea1a 6593 #define EXTI_RTSR_TR6_Pos (6U)
NYX 0:85b3fd62ea1a 6594 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6595 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
NYX 0:85b3fd62ea1a 6596 #define EXTI_RTSR_TR7_Pos (7U)
NYX 0:85b3fd62ea1a 6597 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6598 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
NYX 0:85b3fd62ea1a 6599 #define EXTI_RTSR_TR8_Pos (8U)
NYX 0:85b3fd62ea1a 6600 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6601 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
NYX 0:85b3fd62ea1a 6602 #define EXTI_RTSR_TR9_Pos (9U)
NYX 0:85b3fd62ea1a 6603 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6604 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
NYX 0:85b3fd62ea1a 6605 #define EXTI_RTSR_TR10_Pos (10U)
NYX 0:85b3fd62ea1a 6606 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6607 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
NYX 0:85b3fd62ea1a 6608 #define EXTI_RTSR_TR11_Pos (11U)
NYX 0:85b3fd62ea1a 6609 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6610 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
NYX 0:85b3fd62ea1a 6611 #define EXTI_RTSR_TR12_Pos (12U)
NYX 0:85b3fd62ea1a 6612 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 6613 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
NYX 0:85b3fd62ea1a 6614 #define EXTI_RTSR_TR13_Pos (13U)
NYX 0:85b3fd62ea1a 6615 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 6616 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
NYX 0:85b3fd62ea1a 6617 #define EXTI_RTSR_TR14_Pos (14U)
NYX 0:85b3fd62ea1a 6618 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 6619 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
NYX 0:85b3fd62ea1a 6620 #define EXTI_RTSR_TR15_Pos (15U)
NYX 0:85b3fd62ea1a 6621 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 6622 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
NYX 0:85b3fd62ea1a 6623 #define EXTI_RTSR_TR16_Pos (16U)
NYX 0:85b3fd62ea1a 6624 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6625 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
NYX 0:85b3fd62ea1a 6626 #define EXTI_RTSR_TR17_Pos (17U)
NYX 0:85b3fd62ea1a 6627 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 6628 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
NYX 0:85b3fd62ea1a 6629 #define EXTI_RTSR_TR18_Pos (18U)
NYX 0:85b3fd62ea1a 6630 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6631 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
NYX 0:85b3fd62ea1a 6632 #define EXTI_RTSR_TR19_Pos (19U)
NYX 0:85b3fd62ea1a 6633 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6634 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
NYX 0:85b3fd62ea1a 6635 #define EXTI_RTSR_TR20_Pos (20U)
NYX 0:85b3fd62ea1a 6636 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6637 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
NYX 0:85b3fd62ea1a 6638 #define EXTI_RTSR_TR21_Pos (21U)
NYX 0:85b3fd62ea1a 6639 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6640 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
NYX 0:85b3fd62ea1a 6641 #define EXTI_RTSR_TR22_Pos (22U)
NYX 0:85b3fd62ea1a 6642 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6643 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
NYX 0:85b3fd62ea1a 6644
NYX 0:85b3fd62ea1a 6645 /****************** Bit definition for EXTI_FTSR register *******************/
NYX 0:85b3fd62ea1a 6646 #define EXTI_FTSR_TR0_Pos (0U)
NYX 0:85b3fd62ea1a 6647 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6648 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
NYX 0:85b3fd62ea1a 6649 #define EXTI_FTSR_TR1_Pos (1U)
NYX 0:85b3fd62ea1a 6650 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6651 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
NYX 0:85b3fd62ea1a 6652 #define EXTI_FTSR_TR2_Pos (2U)
NYX 0:85b3fd62ea1a 6653 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6654 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
NYX 0:85b3fd62ea1a 6655 #define EXTI_FTSR_TR3_Pos (3U)
NYX 0:85b3fd62ea1a 6656 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6657 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
NYX 0:85b3fd62ea1a 6658 #define EXTI_FTSR_TR4_Pos (4U)
NYX 0:85b3fd62ea1a 6659 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6660 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
NYX 0:85b3fd62ea1a 6661 #define EXTI_FTSR_TR5_Pos (5U)
NYX 0:85b3fd62ea1a 6662 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6663 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
NYX 0:85b3fd62ea1a 6664 #define EXTI_FTSR_TR6_Pos (6U)
NYX 0:85b3fd62ea1a 6665 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6666 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
NYX 0:85b3fd62ea1a 6667 #define EXTI_FTSR_TR7_Pos (7U)
NYX 0:85b3fd62ea1a 6668 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6669 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
NYX 0:85b3fd62ea1a 6670 #define EXTI_FTSR_TR8_Pos (8U)
NYX 0:85b3fd62ea1a 6671 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6672 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
NYX 0:85b3fd62ea1a 6673 #define EXTI_FTSR_TR9_Pos (9U)
NYX 0:85b3fd62ea1a 6674 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6675 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
NYX 0:85b3fd62ea1a 6676 #define EXTI_FTSR_TR10_Pos (10U)
NYX 0:85b3fd62ea1a 6677 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6678 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
NYX 0:85b3fd62ea1a 6679 #define EXTI_FTSR_TR11_Pos (11U)
NYX 0:85b3fd62ea1a 6680 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6681 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
NYX 0:85b3fd62ea1a 6682 #define EXTI_FTSR_TR12_Pos (12U)
NYX 0:85b3fd62ea1a 6683 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 6684 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
NYX 0:85b3fd62ea1a 6685 #define EXTI_FTSR_TR13_Pos (13U)
NYX 0:85b3fd62ea1a 6686 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 6687 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
NYX 0:85b3fd62ea1a 6688 #define EXTI_FTSR_TR14_Pos (14U)
NYX 0:85b3fd62ea1a 6689 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 6690 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
NYX 0:85b3fd62ea1a 6691 #define EXTI_FTSR_TR15_Pos (15U)
NYX 0:85b3fd62ea1a 6692 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 6693 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
NYX 0:85b3fd62ea1a 6694 #define EXTI_FTSR_TR16_Pos (16U)
NYX 0:85b3fd62ea1a 6695 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6696 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
NYX 0:85b3fd62ea1a 6697 #define EXTI_FTSR_TR17_Pos (17U)
NYX 0:85b3fd62ea1a 6698 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 6699 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
NYX 0:85b3fd62ea1a 6700 #define EXTI_FTSR_TR18_Pos (18U)
NYX 0:85b3fd62ea1a 6701 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6702 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
NYX 0:85b3fd62ea1a 6703 #define EXTI_FTSR_TR19_Pos (19U)
NYX 0:85b3fd62ea1a 6704 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6705 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
NYX 0:85b3fd62ea1a 6706 #define EXTI_FTSR_TR20_Pos (20U)
NYX 0:85b3fd62ea1a 6707 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6708 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
NYX 0:85b3fd62ea1a 6709 #define EXTI_FTSR_TR21_Pos (21U)
NYX 0:85b3fd62ea1a 6710 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6711 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
NYX 0:85b3fd62ea1a 6712 #define EXTI_FTSR_TR22_Pos (22U)
NYX 0:85b3fd62ea1a 6713 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6714 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
NYX 0:85b3fd62ea1a 6715
NYX 0:85b3fd62ea1a 6716 /****************** Bit definition for EXTI_SWIER register ******************/
NYX 0:85b3fd62ea1a 6717 #define EXTI_SWIER_SWIER0_Pos (0U)
NYX 0:85b3fd62ea1a 6718 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6719 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
NYX 0:85b3fd62ea1a 6720 #define EXTI_SWIER_SWIER1_Pos (1U)
NYX 0:85b3fd62ea1a 6721 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6722 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
NYX 0:85b3fd62ea1a 6723 #define EXTI_SWIER_SWIER2_Pos (2U)
NYX 0:85b3fd62ea1a 6724 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6725 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
NYX 0:85b3fd62ea1a 6726 #define EXTI_SWIER_SWIER3_Pos (3U)
NYX 0:85b3fd62ea1a 6727 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6728 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
NYX 0:85b3fd62ea1a 6729 #define EXTI_SWIER_SWIER4_Pos (4U)
NYX 0:85b3fd62ea1a 6730 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6731 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
NYX 0:85b3fd62ea1a 6732 #define EXTI_SWIER_SWIER5_Pos (5U)
NYX 0:85b3fd62ea1a 6733 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6734 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
NYX 0:85b3fd62ea1a 6735 #define EXTI_SWIER_SWIER6_Pos (6U)
NYX 0:85b3fd62ea1a 6736 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6737 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
NYX 0:85b3fd62ea1a 6738 #define EXTI_SWIER_SWIER7_Pos (7U)
NYX 0:85b3fd62ea1a 6739 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6740 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
NYX 0:85b3fd62ea1a 6741 #define EXTI_SWIER_SWIER8_Pos (8U)
NYX 0:85b3fd62ea1a 6742 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6743 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
NYX 0:85b3fd62ea1a 6744 #define EXTI_SWIER_SWIER9_Pos (9U)
NYX 0:85b3fd62ea1a 6745 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6746 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
NYX 0:85b3fd62ea1a 6747 #define EXTI_SWIER_SWIER10_Pos (10U)
NYX 0:85b3fd62ea1a 6748 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6749 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
NYX 0:85b3fd62ea1a 6750 #define EXTI_SWIER_SWIER11_Pos (11U)
NYX 0:85b3fd62ea1a 6751 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6752 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
NYX 0:85b3fd62ea1a 6753 #define EXTI_SWIER_SWIER12_Pos (12U)
NYX 0:85b3fd62ea1a 6754 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 6755 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
NYX 0:85b3fd62ea1a 6756 #define EXTI_SWIER_SWIER13_Pos (13U)
NYX 0:85b3fd62ea1a 6757 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 6758 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
NYX 0:85b3fd62ea1a 6759 #define EXTI_SWIER_SWIER14_Pos (14U)
NYX 0:85b3fd62ea1a 6760 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 6761 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
NYX 0:85b3fd62ea1a 6762 #define EXTI_SWIER_SWIER15_Pos (15U)
NYX 0:85b3fd62ea1a 6763 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 6764 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
NYX 0:85b3fd62ea1a 6765 #define EXTI_SWIER_SWIER16_Pos (16U)
NYX 0:85b3fd62ea1a 6766 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6767 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
NYX 0:85b3fd62ea1a 6768 #define EXTI_SWIER_SWIER17_Pos (17U)
NYX 0:85b3fd62ea1a 6769 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 6770 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
NYX 0:85b3fd62ea1a 6771 #define EXTI_SWIER_SWIER18_Pos (18U)
NYX 0:85b3fd62ea1a 6772 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6773 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
NYX 0:85b3fd62ea1a 6774 #define EXTI_SWIER_SWIER19_Pos (19U)
NYX 0:85b3fd62ea1a 6775 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6776 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
NYX 0:85b3fd62ea1a 6777 #define EXTI_SWIER_SWIER20_Pos (20U)
NYX 0:85b3fd62ea1a 6778 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6779 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
NYX 0:85b3fd62ea1a 6780 #define EXTI_SWIER_SWIER21_Pos (21U)
NYX 0:85b3fd62ea1a 6781 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6782 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
NYX 0:85b3fd62ea1a 6783 #define EXTI_SWIER_SWIER22_Pos (22U)
NYX 0:85b3fd62ea1a 6784 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6785 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
NYX 0:85b3fd62ea1a 6786
NYX 0:85b3fd62ea1a 6787 /******************* Bit definition for EXTI_PR register ********************/
NYX 0:85b3fd62ea1a 6788 #define EXTI_PR_PR0_Pos (0U)
NYX 0:85b3fd62ea1a 6789 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6790 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
NYX 0:85b3fd62ea1a 6791 #define EXTI_PR_PR1_Pos (1U)
NYX 0:85b3fd62ea1a 6792 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6793 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
NYX 0:85b3fd62ea1a 6794 #define EXTI_PR_PR2_Pos (2U)
NYX 0:85b3fd62ea1a 6795 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6796 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
NYX 0:85b3fd62ea1a 6797 #define EXTI_PR_PR3_Pos (3U)
NYX 0:85b3fd62ea1a 6798 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6799 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
NYX 0:85b3fd62ea1a 6800 #define EXTI_PR_PR4_Pos (4U)
NYX 0:85b3fd62ea1a 6801 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6802 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
NYX 0:85b3fd62ea1a 6803 #define EXTI_PR_PR5_Pos (5U)
NYX 0:85b3fd62ea1a 6804 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6805 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
NYX 0:85b3fd62ea1a 6806 #define EXTI_PR_PR6_Pos (6U)
NYX 0:85b3fd62ea1a 6807 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6808 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
NYX 0:85b3fd62ea1a 6809 #define EXTI_PR_PR7_Pos (7U)
NYX 0:85b3fd62ea1a 6810 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6811 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
NYX 0:85b3fd62ea1a 6812 #define EXTI_PR_PR8_Pos (8U)
NYX 0:85b3fd62ea1a 6813 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6814 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
NYX 0:85b3fd62ea1a 6815 #define EXTI_PR_PR9_Pos (9U)
NYX 0:85b3fd62ea1a 6816 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6817 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
NYX 0:85b3fd62ea1a 6818 #define EXTI_PR_PR10_Pos (10U)
NYX 0:85b3fd62ea1a 6819 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6820 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
NYX 0:85b3fd62ea1a 6821 #define EXTI_PR_PR11_Pos (11U)
NYX 0:85b3fd62ea1a 6822 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6823 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
NYX 0:85b3fd62ea1a 6824 #define EXTI_PR_PR12_Pos (12U)
NYX 0:85b3fd62ea1a 6825 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 6826 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
NYX 0:85b3fd62ea1a 6827 #define EXTI_PR_PR13_Pos (13U)
NYX 0:85b3fd62ea1a 6828 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 6829 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
NYX 0:85b3fd62ea1a 6830 #define EXTI_PR_PR14_Pos (14U)
NYX 0:85b3fd62ea1a 6831 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 6832 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
NYX 0:85b3fd62ea1a 6833 #define EXTI_PR_PR15_Pos (15U)
NYX 0:85b3fd62ea1a 6834 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 6835 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
NYX 0:85b3fd62ea1a 6836 #define EXTI_PR_PR16_Pos (16U)
NYX 0:85b3fd62ea1a 6837 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6838 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
NYX 0:85b3fd62ea1a 6839 #define EXTI_PR_PR17_Pos (17U)
NYX 0:85b3fd62ea1a 6840 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 6841 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
NYX 0:85b3fd62ea1a 6842 #define EXTI_PR_PR18_Pos (18U)
NYX 0:85b3fd62ea1a 6843 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 6844 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
NYX 0:85b3fd62ea1a 6845 #define EXTI_PR_PR19_Pos (19U)
NYX 0:85b3fd62ea1a 6846 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 6847 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
NYX 0:85b3fd62ea1a 6848 #define EXTI_PR_PR20_Pos (20U)
NYX 0:85b3fd62ea1a 6849 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 6850 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
NYX 0:85b3fd62ea1a 6851 #define EXTI_PR_PR21_Pos (21U)
NYX 0:85b3fd62ea1a 6852 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 6853 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
NYX 0:85b3fd62ea1a 6854 #define EXTI_PR_PR22_Pos (22U)
NYX 0:85b3fd62ea1a 6855 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 6856 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
NYX 0:85b3fd62ea1a 6857
NYX 0:85b3fd62ea1a 6858 /******************************************************************************/
NYX 0:85b3fd62ea1a 6859 /* */
NYX 0:85b3fd62ea1a 6860 /* FLASH */
NYX 0:85b3fd62ea1a 6861 /* */
NYX 0:85b3fd62ea1a 6862 /******************************************************************************/
NYX 0:85b3fd62ea1a 6863 /******************* Bits definition for FLASH_ACR register *****************/
NYX 0:85b3fd62ea1a 6864 #define FLASH_ACR_LATENCY_Pos (0U)
NYX 0:85b3fd62ea1a 6865 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 6866 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
NYX 0:85b3fd62ea1a 6867 #define FLASH_ACR_LATENCY_0WS 0x00000000U
NYX 0:85b3fd62ea1a 6868 #define FLASH_ACR_LATENCY_1WS 0x00000001U
NYX 0:85b3fd62ea1a 6869 #define FLASH_ACR_LATENCY_2WS 0x00000002U
NYX 0:85b3fd62ea1a 6870 #define FLASH_ACR_LATENCY_3WS 0x00000003U
NYX 0:85b3fd62ea1a 6871 #define FLASH_ACR_LATENCY_4WS 0x00000004U
NYX 0:85b3fd62ea1a 6872 #define FLASH_ACR_LATENCY_5WS 0x00000005U
NYX 0:85b3fd62ea1a 6873 #define FLASH_ACR_LATENCY_6WS 0x00000006U
NYX 0:85b3fd62ea1a 6874 #define FLASH_ACR_LATENCY_7WS 0x00000007U
NYX 0:85b3fd62ea1a 6875
NYX 0:85b3fd62ea1a 6876 #define FLASH_ACR_LATENCY_8WS 0x00000008U
NYX 0:85b3fd62ea1a 6877 #define FLASH_ACR_LATENCY_9WS 0x00000009U
NYX 0:85b3fd62ea1a 6878 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
NYX 0:85b3fd62ea1a 6879 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
NYX 0:85b3fd62ea1a 6880 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
NYX 0:85b3fd62ea1a 6881 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
NYX 0:85b3fd62ea1a 6882 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
NYX 0:85b3fd62ea1a 6883 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
NYX 0:85b3fd62ea1a 6884 #define FLASH_ACR_PRFTEN_Pos (8U)
NYX 0:85b3fd62ea1a 6885 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6886 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
NYX 0:85b3fd62ea1a 6887 #define FLASH_ACR_ICEN_Pos (9U)
NYX 0:85b3fd62ea1a 6888 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6889 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
NYX 0:85b3fd62ea1a 6890 #define FLASH_ACR_DCEN_Pos (10U)
NYX 0:85b3fd62ea1a 6891 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 6892 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
NYX 0:85b3fd62ea1a 6893 #define FLASH_ACR_ICRST_Pos (11U)
NYX 0:85b3fd62ea1a 6894 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 6895 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
NYX 0:85b3fd62ea1a 6896 #define FLASH_ACR_DCRST_Pos (12U)
NYX 0:85b3fd62ea1a 6897 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 6898 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
NYX 0:85b3fd62ea1a 6899 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
NYX 0:85b3fd62ea1a 6900 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
NYX 0:85b3fd62ea1a 6901 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
NYX 0:85b3fd62ea1a 6902 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
NYX 0:85b3fd62ea1a 6903 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
NYX 0:85b3fd62ea1a 6904 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
NYX 0:85b3fd62ea1a 6905
NYX 0:85b3fd62ea1a 6906 /******************* Bits definition for FLASH_SR register ******************/
NYX 0:85b3fd62ea1a 6907 #define FLASH_SR_EOP_Pos (0U)
NYX 0:85b3fd62ea1a 6908 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6909 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
NYX 0:85b3fd62ea1a 6910 #define FLASH_SR_SOP_Pos (1U)
NYX 0:85b3fd62ea1a 6911 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6912 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
NYX 0:85b3fd62ea1a 6913 #define FLASH_SR_WRPERR_Pos (4U)
NYX 0:85b3fd62ea1a 6914 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6915 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
NYX 0:85b3fd62ea1a 6916 #define FLASH_SR_PGAERR_Pos (5U)
NYX 0:85b3fd62ea1a 6917 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6918 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
NYX 0:85b3fd62ea1a 6919 #define FLASH_SR_PGPERR_Pos (6U)
NYX 0:85b3fd62ea1a 6920 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6921 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
NYX 0:85b3fd62ea1a 6922 #define FLASH_SR_PGSERR_Pos (7U)
NYX 0:85b3fd62ea1a 6923 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6924 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
NYX 0:85b3fd62ea1a 6925 #define FLASH_SR_RDERR_Pos (8U)
NYX 0:85b3fd62ea1a 6926 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6927 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
NYX 0:85b3fd62ea1a 6928 #define FLASH_SR_BSY_Pos (16U)
NYX 0:85b3fd62ea1a 6929 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6930 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
NYX 0:85b3fd62ea1a 6931
NYX 0:85b3fd62ea1a 6932 /******************* Bits definition for FLASH_CR register ******************/
NYX 0:85b3fd62ea1a 6933 #define FLASH_CR_PG_Pos (0U)
NYX 0:85b3fd62ea1a 6934 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6935 #define FLASH_CR_PG FLASH_CR_PG_Msk
NYX 0:85b3fd62ea1a 6936 #define FLASH_CR_SER_Pos (1U)
NYX 0:85b3fd62ea1a 6937 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6938 #define FLASH_CR_SER FLASH_CR_SER_Msk
NYX 0:85b3fd62ea1a 6939 #define FLASH_CR_MER_Pos (2U)
NYX 0:85b3fd62ea1a 6940 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 6941 #define FLASH_CR_MER FLASH_CR_MER_Msk
NYX 0:85b3fd62ea1a 6942 #define FLASH_CR_MER1 FLASH_CR_MER
NYX 0:85b3fd62ea1a 6943 #define FLASH_CR_SNB_Pos (3U)
NYX 0:85b3fd62ea1a 6944 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
NYX 0:85b3fd62ea1a 6945 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
NYX 0:85b3fd62ea1a 6946 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 6947 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6948 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6949 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6950 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6951 #define FLASH_CR_PSIZE_Pos (8U)
NYX 0:85b3fd62ea1a 6952 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 6953 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
NYX 0:85b3fd62ea1a 6954 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6955 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6956 #define FLASH_CR_MER2_Pos (15U)
NYX 0:85b3fd62ea1a 6957 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 6958 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
NYX 0:85b3fd62ea1a 6959 #define FLASH_CR_STRT_Pos (16U)
NYX 0:85b3fd62ea1a 6960 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 6961 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
NYX 0:85b3fd62ea1a 6962 #define FLASH_CR_EOPIE_Pos (24U)
NYX 0:85b3fd62ea1a 6963 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 6964 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
NYX 0:85b3fd62ea1a 6965 #define FLASH_CR_LOCK_Pos (31U)
NYX 0:85b3fd62ea1a 6966 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 6967 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
NYX 0:85b3fd62ea1a 6968
NYX 0:85b3fd62ea1a 6969 /******************* Bits definition for FLASH_OPTCR register ***************/
NYX 0:85b3fd62ea1a 6970 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
NYX 0:85b3fd62ea1a 6971 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 6972 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
NYX 0:85b3fd62ea1a 6973 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
NYX 0:85b3fd62ea1a 6974 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 6975 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
NYX 0:85b3fd62ea1a 6976
NYX 0:85b3fd62ea1a 6977 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
NYX 0:85b3fd62ea1a 6978 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
NYX 0:85b3fd62ea1a 6979 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
NYX 0:85b3fd62ea1a 6980 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 6981 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
NYX 0:85b3fd62ea1a 6982 #define FLASH_OPTCR_BFB2_Pos (4U)
NYX 0:85b3fd62ea1a 6983 #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 6984 #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
NYX 0:85b3fd62ea1a 6985 #define FLASH_OPTCR_WDG_SW_Pos (5U)
NYX 0:85b3fd62ea1a 6986 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 6987 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
NYX 0:85b3fd62ea1a 6988 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
NYX 0:85b3fd62ea1a 6989 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 6990 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
NYX 0:85b3fd62ea1a 6991 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
NYX 0:85b3fd62ea1a 6992 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 6993 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
NYX 0:85b3fd62ea1a 6994 #define FLASH_OPTCR_RDP_Pos (8U)
NYX 0:85b3fd62ea1a 6995 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 6996 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
NYX 0:85b3fd62ea1a 6997 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 6998 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 6999 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7000 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7001 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7002 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7003 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7004 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7005 #define FLASH_OPTCR_nWRP_Pos (16U)
NYX 0:85b3fd62ea1a 7006 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
NYX 0:85b3fd62ea1a 7007 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
NYX 0:85b3fd62ea1a 7008 #define FLASH_OPTCR_nWRP_0 0x00010000U
NYX 0:85b3fd62ea1a 7009 #define FLASH_OPTCR_nWRP_1 0x00020000U
NYX 0:85b3fd62ea1a 7010 #define FLASH_OPTCR_nWRP_2 0x00040000U
NYX 0:85b3fd62ea1a 7011 #define FLASH_OPTCR_nWRP_3 0x00080000U
NYX 0:85b3fd62ea1a 7012 #define FLASH_OPTCR_nWRP_4 0x00100000U
NYX 0:85b3fd62ea1a 7013 #define FLASH_OPTCR_nWRP_5 0x00200000U
NYX 0:85b3fd62ea1a 7014 #define FLASH_OPTCR_nWRP_6 0x00400000U
NYX 0:85b3fd62ea1a 7015 #define FLASH_OPTCR_nWRP_7 0x00800000U
NYX 0:85b3fd62ea1a 7016 #define FLASH_OPTCR_nWRP_8 0x01000000U
NYX 0:85b3fd62ea1a 7017 #define FLASH_OPTCR_nWRP_9 0x02000000U
NYX 0:85b3fd62ea1a 7018 #define FLASH_OPTCR_nWRP_10 0x04000000U
NYX 0:85b3fd62ea1a 7019 #define FLASH_OPTCR_nWRP_11 0x08000000U
NYX 0:85b3fd62ea1a 7020 #define FLASH_OPTCR_DB1M_Pos (30U)
NYX 0:85b3fd62ea1a 7021 #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 7022 #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
NYX 0:85b3fd62ea1a 7023 #define FLASH_OPTCR_SPRMOD_Pos (31U)
NYX 0:85b3fd62ea1a 7024 #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 7025 #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
NYX 0:85b3fd62ea1a 7026
NYX 0:85b3fd62ea1a 7027 /****************** Bits definition for FLASH_OPTCR1 register ***************/
NYX 0:85b3fd62ea1a 7028 #define FLASH_OPTCR1_nWRP_Pos (16U)
NYX 0:85b3fd62ea1a 7029 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
NYX 0:85b3fd62ea1a 7030 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
NYX 0:85b3fd62ea1a 7031 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7032 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7033 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7034 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7035 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 7036 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 7037 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 7038 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 7039 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 7040 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 7041 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 7042 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 7043
NYX 0:85b3fd62ea1a 7044 /******************************************************************************/
NYX 0:85b3fd62ea1a 7045 /* */
NYX 0:85b3fd62ea1a 7046 /* Flexible Memory Controller */
NYX 0:85b3fd62ea1a 7047 /* */
NYX 0:85b3fd62ea1a 7048 /******************************************************************************/
NYX 0:85b3fd62ea1a 7049 /****************** Bit definition for FMC_BCR1 register *******************/
NYX 0:85b3fd62ea1a 7050 #define FMC_BCR1_MBKEN_Pos (0U)
NYX 0:85b3fd62ea1a 7051 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7052 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
NYX 0:85b3fd62ea1a 7053 #define FMC_BCR1_MUXEN_Pos (1U)
NYX 0:85b3fd62ea1a 7054 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7055 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
NYX 0:85b3fd62ea1a 7056
NYX 0:85b3fd62ea1a 7057 #define FMC_BCR1_MTYP_Pos (2U)
NYX 0:85b3fd62ea1a 7058 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 7059 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
NYX 0:85b3fd62ea1a 7060 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7061 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7062
NYX 0:85b3fd62ea1a 7063 #define FMC_BCR1_MWID_Pos (4U)
NYX 0:85b3fd62ea1a 7064 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 7065 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
NYX 0:85b3fd62ea1a 7066 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7067 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7068
NYX 0:85b3fd62ea1a 7069 #define FMC_BCR1_FACCEN_Pos (6U)
NYX 0:85b3fd62ea1a 7070 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7071 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
NYX 0:85b3fd62ea1a 7072 #define FMC_BCR1_BURSTEN_Pos (8U)
NYX 0:85b3fd62ea1a 7073 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7074 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
NYX 0:85b3fd62ea1a 7075 #define FMC_BCR1_WAITPOL_Pos (9U)
NYX 0:85b3fd62ea1a 7076 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7077 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
NYX 0:85b3fd62ea1a 7078 #define FMC_BCR1_WAITCFG_Pos (11U)
NYX 0:85b3fd62ea1a 7079 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7080 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
NYX 0:85b3fd62ea1a 7081 #define FMC_BCR1_WREN_Pos (12U)
NYX 0:85b3fd62ea1a 7082 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7083 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
NYX 0:85b3fd62ea1a 7084 #define FMC_BCR1_WAITEN_Pos (13U)
NYX 0:85b3fd62ea1a 7085 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7086 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
NYX 0:85b3fd62ea1a 7087 #define FMC_BCR1_EXTMOD_Pos (14U)
NYX 0:85b3fd62ea1a 7088 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7089 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
NYX 0:85b3fd62ea1a 7090 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
NYX 0:85b3fd62ea1a 7091 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7092 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
NYX 0:85b3fd62ea1a 7093 #define FMC_BCR1_CPSIZE_Pos (16U)
NYX 0:85b3fd62ea1a 7094 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
NYX 0:85b3fd62ea1a 7095 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
NYX 0:85b3fd62ea1a 7096 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7097 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7098 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7099 #define FMC_BCR1_CBURSTRW_Pos (19U)
NYX 0:85b3fd62ea1a 7100 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7101 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
NYX 0:85b3fd62ea1a 7102 #define FMC_BCR1_CCLKEN_Pos (20U)
NYX 0:85b3fd62ea1a 7103 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 7104 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
NYX 0:85b3fd62ea1a 7105 #define FMC_BCR1_WFDIS_Pos (21U)
NYX 0:85b3fd62ea1a 7106 #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 7107 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
NYX 0:85b3fd62ea1a 7108
NYX 0:85b3fd62ea1a 7109 /****************** Bit definition for FMC_BCR2 register *******************/
NYX 0:85b3fd62ea1a 7110 #define FMC_BCR2_MBKEN_Pos (0U)
NYX 0:85b3fd62ea1a 7111 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7112 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
NYX 0:85b3fd62ea1a 7113 #define FMC_BCR2_MUXEN_Pos (1U)
NYX 0:85b3fd62ea1a 7114 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7115 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
NYX 0:85b3fd62ea1a 7116
NYX 0:85b3fd62ea1a 7117 #define FMC_BCR2_MTYP_Pos (2U)
NYX 0:85b3fd62ea1a 7118 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 7119 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
NYX 0:85b3fd62ea1a 7120 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7121 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7122
NYX 0:85b3fd62ea1a 7123 #define FMC_BCR2_MWID_Pos (4U)
NYX 0:85b3fd62ea1a 7124 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 7125 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
NYX 0:85b3fd62ea1a 7126 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7127 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7128
NYX 0:85b3fd62ea1a 7129 #define FMC_BCR2_FACCEN_Pos (6U)
NYX 0:85b3fd62ea1a 7130 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7131 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
NYX 0:85b3fd62ea1a 7132 #define FMC_BCR2_BURSTEN_Pos (8U)
NYX 0:85b3fd62ea1a 7133 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7134 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
NYX 0:85b3fd62ea1a 7135 #define FMC_BCR2_WAITPOL_Pos (9U)
NYX 0:85b3fd62ea1a 7136 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7137 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
NYX 0:85b3fd62ea1a 7138 #define FMC_BCR2_WAITCFG_Pos (11U)
NYX 0:85b3fd62ea1a 7139 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7140 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
NYX 0:85b3fd62ea1a 7141 #define FMC_BCR2_WREN_Pos (12U)
NYX 0:85b3fd62ea1a 7142 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7143 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
NYX 0:85b3fd62ea1a 7144 #define FMC_BCR2_WAITEN_Pos (13U)
NYX 0:85b3fd62ea1a 7145 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7146 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
NYX 0:85b3fd62ea1a 7147 #define FMC_BCR2_EXTMOD_Pos (14U)
NYX 0:85b3fd62ea1a 7148 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7149 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
NYX 0:85b3fd62ea1a 7150 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
NYX 0:85b3fd62ea1a 7151 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7152 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
NYX 0:85b3fd62ea1a 7153 #define FMC_BCR2_CBURSTRW_Pos (19U)
NYX 0:85b3fd62ea1a 7154 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7155 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
NYX 0:85b3fd62ea1a 7156
NYX 0:85b3fd62ea1a 7157 /****************** Bit definition for FMC_BCR3 register *******************/
NYX 0:85b3fd62ea1a 7158 #define FMC_BCR3_MBKEN_Pos (0U)
NYX 0:85b3fd62ea1a 7159 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7160 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
NYX 0:85b3fd62ea1a 7161 #define FMC_BCR3_MUXEN_Pos (1U)
NYX 0:85b3fd62ea1a 7162 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7163 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
NYX 0:85b3fd62ea1a 7164
NYX 0:85b3fd62ea1a 7165 #define FMC_BCR3_MTYP_Pos (2U)
NYX 0:85b3fd62ea1a 7166 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 7167 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
NYX 0:85b3fd62ea1a 7168 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7169 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7170
NYX 0:85b3fd62ea1a 7171 #define FMC_BCR3_MWID_Pos (4U)
NYX 0:85b3fd62ea1a 7172 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 7173 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
NYX 0:85b3fd62ea1a 7174 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7175 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7176
NYX 0:85b3fd62ea1a 7177 #define FMC_BCR3_FACCEN_Pos (6U)
NYX 0:85b3fd62ea1a 7178 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7179 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
NYX 0:85b3fd62ea1a 7180 #define FMC_BCR3_BURSTEN_Pos (8U)
NYX 0:85b3fd62ea1a 7181 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7182 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
NYX 0:85b3fd62ea1a 7183 #define FMC_BCR3_WAITPOL_Pos (9U)
NYX 0:85b3fd62ea1a 7184 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7185 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
NYX 0:85b3fd62ea1a 7186 #define FMC_BCR3_WAITCFG_Pos (11U)
NYX 0:85b3fd62ea1a 7187 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7188 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
NYX 0:85b3fd62ea1a 7189 #define FMC_BCR3_WREN_Pos (12U)
NYX 0:85b3fd62ea1a 7190 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7191 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
NYX 0:85b3fd62ea1a 7192 #define FMC_BCR3_WAITEN_Pos (13U)
NYX 0:85b3fd62ea1a 7193 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7194 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
NYX 0:85b3fd62ea1a 7195 #define FMC_BCR3_EXTMOD_Pos (14U)
NYX 0:85b3fd62ea1a 7196 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7197 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
NYX 0:85b3fd62ea1a 7198 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
NYX 0:85b3fd62ea1a 7199 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7200 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
NYX 0:85b3fd62ea1a 7201 #define FMC_BCR3_CBURSTRW_Pos (19U)
NYX 0:85b3fd62ea1a 7202 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7203 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
NYX 0:85b3fd62ea1a 7204
NYX 0:85b3fd62ea1a 7205 /****************** Bit definition for FMC_BCR4 register *******************/
NYX 0:85b3fd62ea1a 7206 #define FMC_BCR4_MBKEN_Pos (0U)
NYX 0:85b3fd62ea1a 7207 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7208 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
NYX 0:85b3fd62ea1a 7209 #define FMC_BCR4_MUXEN_Pos (1U)
NYX 0:85b3fd62ea1a 7210 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7211 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
NYX 0:85b3fd62ea1a 7212
NYX 0:85b3fd62ea1a 7213 #define FMC_BCR4_MTYP_Pos (2U)
NYX 0:85b3fd62ea1a 7214 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 7215 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
NYX 0:85b3fd62ea1a 7216 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7217 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7218
NYX 0:85b3fd62ea1a 7219 #define FMC_BCR4_MWID_Pos (4U)
NYX 0:85b3fd62ea1a 7220 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 7221 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
NYX 0:85b3fd62ea1a 7222 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7223 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7224
NYX 0:85b3fd62ea1a 7225 #define FMC_BCR4_FACCEN_Pos (6U)
NYX 0:85b3fd62ea1a 7226 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7227 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
NYX 0:85b3fd62ea1a 7228 #define FMC_BCR4_BURSTEN_Pos (8U)
NYX 0:85b3fd62ea1a 7229 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7230 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
NYX 0:85b3fd62ea1a 7231 #define FMC_BCR4_WAITPOL_Pos (9U)
NYX 0:85b3fd62ea1a 7232 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7233 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
NYX 0:85b3fd62ea1a 7234 #define FMC_BCR4_WAITCFG_Pos (11U)
NYX 0:85b3fd62ea1a 7235 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7236 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
NYX 0:85b3fd62ea1a 7237 #define FMC_BCR4_WREN_Pos (12U)
NYX 0:85b3fd62ea1a 7238 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7239 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
NYX 0:85b3fd62ea1a 7240 #define FMC_BCR4_WAITEN_Pos (13U)
NYX 0:85b3fd62ea1a 7241 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7242 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
NYX 0:85b3fd62ea1a 7243 #define FMC_BCR4_EXTMOD_Pos (14U)
NYX 0:85b3fd62ea1a 7244 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7245 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
NYX 0:85b3fd62ea1a 7246 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
NYX 0:85b3fd62ea1a 7247 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7248 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
NYX 0:85b3fd62ea1a 7249 #define FMC_BCR4_CBURSTRW_Pos (19U)
NYX 0:85b3fd62ea1a 7250 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7251 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
NYX 0:85b3fd62ea1a 7252
NYX 0:85b3fd62ea1a 7253 /****************** Bit definition for FMC_BTR1 register ******************/
NYX 0:85b3fd62ea1a 7254 #define FMC_BTR1_ADDSET_Pos (0U)
NYX 0:85b3fd62ea1a 7255 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7256 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
NYX 0:85b3fd62ea1a 7257 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7258 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7259 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7260 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7261
NYX 0:85b3fd62ea1a 7262 #define FMC_BTR1_ADDHLD_Pos (4U)
NYX 0:85b3fd62ea1a 7263 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7264 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
NYX 0:85b3fd62ea1a 7265 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7266 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7267 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7268 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7269
NYX 0:85b3fd62ea1a 7270 #define FMC_BTR1_DATAST_Pos (8U)
NYX 0:85b3fd62ea1a 7271 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7272 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
NYX 0:85b3fd62ea1a 7273 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7274 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7275 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7276 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7277 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7278 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7279 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7280 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7281
NYX 0:85b3fd62ea1a 7282 #define FMC_BTR1_BUSTURN_Pos (16U)
NYX 0:85b3fd62ea1a 7283 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 7284 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
NYX 0:85b3fd62ea1a 7285 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7286 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7287 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7288 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7289
NYX 0:85b3fd62ea1a 7290 #define FMC_BTR1_CLKDIV_Pos (20U)
NYX 0:85b3fd62ea1a 7291 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 7292 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
NYX 0:85b3fd62ea1a 7293 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 7294 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 7295 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 7296 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 7297
NYX 0:85b3fd62ea1a 7298 #define FMC_BTR1_DATLAT_Pos (24U)
NYX 0:85b3fd62ea1a 7299 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 7300 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
NYX 0:85b3fd62ea1a 7301 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 7302 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 7303 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 7304 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 7305
NYX 0:85b3fd62ea1a 7306 #define FMC_BTR1_ACCMOD_Pos (28U)
NYX 0:85b3fd62ea1a 7307 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 7308 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
NYX 0:85b3fd62ea1a 7309 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7310 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7311
NYX 0:85b3fd62ea1a 7312 /****************** Bit definition for FMC_BTR2 register *******************/
NYX 0:85b3fd62ea1a 7313 #define FMC_BTR2_ADDSET_Pos (0U)
NYX 0:85b3fd62ea1a 7314 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7315 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
NYX 0:85b3fd62ea1a 7316 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7317 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7318 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7319 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7320
NYX 0:85b3fd62ea1a 7321 #define FMC_BTR2_ADDHLD_Pos (4U)
NYX 0:85b3fd62ea1a 7322 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7323 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
NYX 0:85b3fd62ea1a 7324 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7325 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7326 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7327 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7328
NYX 0:85b3fd62ea1a 7329 #define FMC_BTR2_DATAST_Pos (8U)
NYX 0:85b3fd62ea1a 7330 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7331 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
NYX 0:85b3fd62ea1a 7332 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7333 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7334 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7335 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7336 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7337 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7338 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7339 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7340
NYX 0:85b3fd62ea1a 7341 #define FMC_BTR2_BUSTURN_Pos (16U)
NYX 0:85b3fd62ea1a 7342 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 7343 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
NYX 0:85b3fd62ea1a 7344 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7345 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7346 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7347 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7348
NYX 0:85b3fd62ea1a 7349 #define FMC_BTR2_CLKDIV_Pos (20U)
NYX 0:85b3fd62ea1a 7350 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 7351 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
NYX 0:85b3fd62ea1a 7352 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 7353 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 7354 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 7355 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 7356
NYX 0:85b3fd62ea1a 7357 #define FMC_BTR2_DATLAT_Pos (24U)
NYX 0:85b3fd62ea1a 7358 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 7359 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
NYX 0:85b3fd62ea1a 7360 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 7361 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 7362 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 7363 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 7364
NYX 0:85b3fd62ea1a 7365 #define FMC_BTR2_ACCMOD_Pos (28U)
NYX 0:85b3fd62ea1a 7366 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 7367 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
NYX 0:85b3fd62ea1a 7368 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7369 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7370
NYX 0:85b3fd62ea1a 7371 /******************* Bit definition for FMC_BTR3 register *******************/
NYX 0:85b3fd62ea1a 7372 #define FMC_BTR3_ADDSET_Pos (0U)
NYX 0:85b3fd62ea1a 7373 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7374 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
NYX 0:85b3fd62ea1a 7375 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7376 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7377 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7378 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7379
NYX 0:85b3fd62ea1a 7380 #define FMC_BTR3_ADDHLD_Pos (4U)
NYX 0:85b3fd62ea1a 7381 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7382 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
NYX 0:85b3fd62ea1a 7383 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7384 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7385 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7386 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7387
NYX 0:85b3fd62ea1a 7388 #define FMC_BTR3_DATAST_Pos (8U)
NYX 0:85b3fd62ea1a 7389 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7390 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
NYX 0:85b3fd62ea1a 7391 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7392 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7393 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7394 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7395 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7396 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7397 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7398 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7399
NYX 0:85b3fd62ea1a 7400 #define FMC_BTR3_BUSTURN_Pos (16U)
NYX 0:85b3fd62ea1a 7401 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 7402 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
NYX 0:85b3fd62ea1a 7403 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7404 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7405 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7406 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7407
NYX 0:85b3fd62ea1a 7408 #define FMC_BTR3_CLKDIV_Pos (20U)
NYX 0:85b3fd62ea1a 7409 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 7410 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
NYX 0:85b3fd62ea1a 7411 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 7412 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 7413 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 7414 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 7415
NYX 0:85b3fd62ea1a 7416 #define FMC_BTR3_DATLAT_Pos (24U)
NYX 0:85b3fd62ea1a 7417 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 7418 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
NYX 0:85b3fd62ea1a 7419 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 7420 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 7421 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 7422 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 7423
NYX 0:85b3fd62ea1a 7424 #define FMC_BTR3_ACCMOD_Pos (28U)
NYX 0:85b3fd62ea1a 7425 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 7426 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
NYX 0:85b3fd62ea1a 7427 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7428 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7429
NYX 0:85b3fd62ea1a 7430 /****************** Bit definition for FMC_BTR4 register *******************/
NYX 0:85b3fd62ea1a 7431 #define FMC_BTR4_ADDSET_Pos (0U)
NYX 0:85b3fd62ea1a 7432 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7433 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
NYX 0:85b3fd62ea1a 7434 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7435 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7436 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7437 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7438
NYX 0:85b3fd62ea1a 7439 #define FMC_BTR4_ADDHLD_Pos (4U)
NYX 0:85b3fd62ea1a 7440 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7441 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
NYX 0:85b3fd62ea1a 7442 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7443 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7444 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7445 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7446
NYX 0:85b3fd62ea1a 7447 #define FMC_BTR4_DATAST_Pos (8U)
NYX 0:85b3fd62ea1a 7448 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7449 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
NYX 0:85b3fd62ea1a 7450 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7451 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7452 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7453 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7454 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7455 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7456 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7457 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7458
NYX 0:85b3fd62ea1a 7459 #define FMC_BTR4_BUSTURN_Pos (16U)
NYX 0:85b3fd62ea1a 7460 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 7461 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
NYX 0:85b3fd62ea1a 7462 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7463 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7464 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7465 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7466
NYX 0:85b3fd62ea1a 7467 #define FMC_BTR4_CLKDIV_Pos (20U)
NYX 0:85b3fd62ea1a 7468 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 7469 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
NYX 0:85b3fd62ea1a 7470 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 7471 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 7472 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 7473 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 7474
NYX 0:85b3fd62ea1a 7475 #define FMC_BTR4_DATLAT_Pos (24U)
NYX 0:85b3fd62ea1a 7476 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 7477 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
NYX 0:85b3fd62ea1a 7478 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 7479 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 7480 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 7481 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 7482
NYX 0:85b3fd62ea1a 7483 #define FMC_BTR4_ACCMOD_Pos (28U)
NYX 0:85b3fd62ea1a 7484 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 7485 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
NYX 0:85b3fd62ea1a 7486 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7487 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7488
NYX 0:85b3fd62ea1a 7489 /****************** Bit definition for FMC_BWTR1 register ******************/
NYX 0:85b3fd62ea1a 7490 #define FMC_BWTR1_ADDSET_Pos (0U)
NYX 0:85b3fd62ea1a 7491 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7492 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
NYX 0:85b3fd62ea1a 7493 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7494 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7495 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7496 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7497
NYX 0:85b3fd62ea1a 7498 #define FMC_BWTR1_ADDHLD_Pos (4U)
NYX 0:85b3fd62ea1a 7499 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7500 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
NYX 0:85b3fd62ea1a 7501 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7502 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7503 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7504 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7505
NYX 0:85b3fd62ea1a 7506 #define FMC_BWTR1_DATAST_Pos (8U)
NYX 0:85b3fd62ea1a 7507 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7508 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
NYX 0:85b3fd62ea1a 7509 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7510 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7511 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7512 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7513 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7514 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7515 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7516 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7517
NYX 0:85b3fd62ea1a 7518 #define FMC_BWTR1_BUSTURN_Pos (16U)
NYX 0:85b3fd62ea1a 7519 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 7520 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
NYX 0:85b3fd62ea1a 7521 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7522 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7523 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7524 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7525
NYX 0:85b3fd62ea1a 7526 #define FMC_BWTR1_ACCMOD_Pos (28U)
NYX 0:85b3fd62ea1a 7527 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 7528 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
NYX 0:85b3fd62ea1a 7529 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7530 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7531
NYX 0:85b3fd62ea1a 7532 /****************** Bit definition for FMC_BWTR2 register ******************/
NYX 0:85b3fd62ea1a 7533 #define FMC_BWTR2_ADDSET_Pos (0U)
NYX 0:85b3fd62ea1a 7534 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7535 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
NYX 0:85b3fd62ea1a 7536 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7537 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7538 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7539 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7540
NYX 0:85b3fd62ea1a 7541 #define FMC_BWTR2_ADDHLD_Pos (4U)
NYX 0:85b3fd62ea1a 7542 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7543 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
NYX 0:85b3fd62ea1a 7544 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7545 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7546 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7547 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7548
NYX 0:85b3fd62ea1a 7549 #define FMC_BWTR2_DATAST_Pos (8U)
NYX 0:85b3fd62ea1a 7550 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7551 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
NYX 0:85b3fd62ea1a 7552 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7553 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7554 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7555 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7556 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7557 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7558 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7559 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7560
NYX 0:85b3fd62ea1a 7561 #define FMC_BWTR2_BUSTURN_Pos (16U)
NYX 0:85b3fd62ea1a 7562 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 7563 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
NYX 0:85b3fd62ea1a 7564 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7565 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7566 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7567 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7568
NYX 0:85b3fd62ea1a 7569 #define FMC_BWTR2_ACCMOD_Pos (28U)
NYX 0:85b3fd62ea1a 7570 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 7571 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
NYX 0:85b3fd62ea1a 7572 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7573 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7574
NYX 0:85b3fd62ea1a 7575 /****************** Bit definition for FMC_BWTR3 register ******************/
NYX 0:85b3fd62ea1a 7576 #define FMC_BWTR3_ADDSET_Pos (0U)
NYX 0:85b3fd62ea1a 7577 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7578 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
NYX 0:85b3fd62ea1a 7579 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7580 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7581 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7582 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7583
NYX 0:85b3fd62ea1a 7584 #define FMC_BWTR3_ADDHLD_Pos (4U)
NYX 0:85b3fd62ea1a 7585 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7586 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
NYX 0:85b3fd62ea1a 7587 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7588 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7589 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7590 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7591
NYX 0:85b3fd62ea1a 7592 #define FMC_BWTR3_DATAST_Pos (8U)
NYX 0:85b3fd62ea1a 7593 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7594 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
NYX 0:85b3fd62ea1a 7595 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7596 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7597 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7598 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7599 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7600 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7601 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7602 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7603
NYX 0:85b3fd62ea1a 7604 #define FMC_BWTR3_BUSTURN_Pos (16U)
NYX 0:85b3fd62ea1a 7605 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 7606 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
NYX 0:85b3fd62ea1a 7607 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7608 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7609 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7610 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7611
NYX 0:85b3fd62ea1a 7612 #define FMC_BWTR3_ACCMOD_Pos (28U)
NYX 0:85b3fd62ea1a 7613 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 7614 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
NYX 0:85b3fd62ea1a 7615 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7616 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7617
NYX 0:85b3fd62ea1a 7618 /****************** Bit definition for FMC_BWTR4 register ******************/
NYX 0:85b3fd62ea1a 7619 #define FMC_BWTR4_ADDSET_Pos (0U)
NYX 0:85b3fd62ea1a 7620 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7621 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
NYX 0:85b3fd62ea1a 7622 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7623 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7624 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7625 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7626
NYX 0:85b3fd62ea1a 7627 #define FMC_BWTR4_ADDHLD_Pos (4U)
NYX 0:85b3fd62ea1a 7628 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7629 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
NYX 0:85b3fd62ea1a 7630 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7631 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7632 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7633 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7634
NYX 0:85b3fd62ea1a 7635 #define FMC_BWTR4_DATAST_Pos (8U)
NYX 0:85b3fd62ea1a 7636 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7637 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
NYX 0:85b3fd62ea1a 7638 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7639 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7640 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7641 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7642 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7643 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7644 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7645 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7646
NYX 0:85b3fd62ea1a 7647 #define FMC_BWTR4_BUSTURN_Pos (16U)
NYX 0:85b3fd62ea1a 7648 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 7649 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
NYX 0:85b3fd62ea1a 7650 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7651 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7652 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7653 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7654
NYX 0:85b3fd62ea1a 7655 #define FMC_BWTR4_ACCMOD_Pos (28U)
NYX 0:85b3fd62ea1a 7656 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 7657 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
NYX 0:85b3fd62ea1a 7658 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7659 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7660
NYX 0:85b3fd62ea1a 7661 /****************** Bit definition for FMC_PCR register *******************/
NYX 0:85b3fd62ea1a 7662 #define FMC_PCR_PWAITEN_Pos (1U)
NYX 0:85b3fd62ea1a 7663 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7664 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
NYX 0:85b3fd62ea1a 7665 #define FMC_PCR_PBKEN_Pos (2U)
NYX 0:85b3fd62ea1a 7666 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7667 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
NYX 0:85b3fd62ea1a 7668 #define FMC_PCR_PTYP_Pos (3U)
NYX 0:85b3fd62ea1a 7669 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7670 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
NYX 0:85b3fd62ea1a 7671
NYX 0:85b3fd62ea1a 7672 #define FMC_PCR_PWID_Pos (4U)
NYX 0:85b3fd62ea1a 7673 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 7674 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
NYX 0:85b3fd62ea1a 7675 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7676 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7677
NYX 0:85b3fd62ea1a 7678 #define FMC_PCR_ECCEN_Pos (6U)
NYX 0:85b3fd62ea1a 7679 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7680 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
NYX 0:85b3fd62ea1a 7681
NYX 0:85b3fd62ea1a 7682 #define FMC_PCR_TCLR_Pos (9U)
NYX 0:85b3fd62ea1a 7683 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
NYX 0:85b3fd62ea1a 7684 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
NYX 0:85b3fd62ea1a 7685 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7686 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7687 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7688 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7689
NYX 0:85b3fd62ea1a 7690 #define FMC_PCR_TAR_Pos (13U)
NYX 0:85b3fd62ea1a 7691 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
NYX 0:85b3fd62ea1a 7692 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
NYX 0:85b3fd62ea1a 7693 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7694 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7695 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7696 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7697
NYX 0:85b3fd62ea1a 7698 #define FMC_PCR_ECCPS_Pos (17U)
NYX 0:85b3fd62ea1a 7699 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
NYX 0:85b3fd62ea1a 7700 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
NYX 0:85b3fd62ea1a 7701 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7702 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7703 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7704
NYX 0:85b3fd62ea1a 7705 /******************* Bit definition for FMC_SR register *******************/
NYX 0:85b3fd62ea1a 7706 #define FMC_SR_IRS_Pos (0U)
NYX 0:85b3fd62ea1a 7707 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7708 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
NYX 0:85b3fd62ea1a 7709 #define FMC_SR_ILS_Pos (1U)
NYX 0:85b3fd62ea1a 7710 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7711 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
NYX 0:85b3fd62ea1a 7712 #define FMC_SR_IFS_Pos (2U)
NYX 0:85b3fd62ea1a 7713 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7714 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
NYX 0:85b3fd62ea1a 7715 #define FMC_SR_IREN_Pos (3U)
NYX 0:85b3fd62ea1a 7716 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7717 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
NYX 0:85b3fd62ea1a 7718 #define FMC_SR_ILEN_Pos (4U)
NYX 0:85b3fd62ea1a 7719 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7720 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
NYX 0:85b3fd62ea1a 7721 #define FMC_SR_IFEN_Pos (5U)
NYX 0:85b3fd62ea1a 7722 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7723 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
NYX 0:85b3fd62ea1a 7724 #define FMC_SR_FEMPT_Pos (6U)
NYX 0:85b3fd62ea1a 7725 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7726 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
NYX 0:85b3fd62ea1a 7727
NYX 0:85b3fd62ea1a 7728 /****************** Bit definition for FMC_PMEM register ******************/
NYX 0:85b3fd62ea1a 7729 #define FMC_PMEM_MEMSET2_Pos (0U)
NYX 0:85b3fd62ea1a 7730 #define FMC_PMEM_MEMSET2_Msk (0xFFU << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 7731 #define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
NYX 0:85b3fd62ea1a 7732 #define FMC_PMEM_MEMSET2_0 (0x01U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7733 #define FMC_PMEM_MEMSET2_1 (0x02U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7734 #define FMC_PMEM_MEMSET2_2 (0x04U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7735 #define FMC_PMEM_MEMSET2_3 (0x08U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7736 #define FMC_PMEM_MEMSET2_4 (0x10U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7737 #define FMC_PMEM_MEMSET2_5 (0x20U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7738 #define FMC_PMEM_MEMSET2_6 (0x40U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7739 #define FMC_PMEM_MEMSET2_7 (0x80U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7740
NYX 0:85b3fd62ea1a 7741 #define FMC_PMEM_MEMWAIT2_Pos (8U)
NYX 0:85b3fd62ea1a 7742 #define FMC_PMEM_MEMWAIT2_Msk (0xFFU << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7743 #define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
NYX 0:85b3fd62ea1a 7744 #define FMC_PMEM_MEMWAIT2_0 (0x01U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7745 #define FMC_PMEM_MEMWAIT2_1 (0x02U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7746 #define FMC_PMEM_MEMWAIT2_2 (0x04U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7747 #define FMC_PMEM_MEMWAIT2_3 (0x08U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7748 #define FMC_PMEM_MEMWAIT2_4 (0x10U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7749 #define FMC_PMEM_MEMWAIT2_5 (0x20U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7750 #define FMC_PMEM_MEMWAIT2_6 (0x40U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7751 #define FMC_PMEM_MEMWAIT2_7 (0x80U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7752
NYX 0:85b3fd62ea1a 7753 #define FMC_PMEM_MEMHOLD2_Pos (16U)
NYX 0:85b3fd62ea1a 7754 #define FMC_PMEM_MEMHOLD2_Msk (0xFFU << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 7755 #define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
NYX 0:85b3fd62ea1a 7756 #define FMC_PMEM_MEMHOLD2_0 (0x01U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7757 #define FMC_PMEM_MEMHOLD2_1 (0x02U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7758 #define FMC_PMEM_MEMHOLD2_2 (0x04U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7759 #define FMC_PMEM_MEMHOLD2_3 (0x08U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7760 #define FMC_PMEM_MEMHOLD2_4 (0x10U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 7761 #define FMC_PMEM_MEMHOLD2_5 (0x20U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 7762 #define FMC_PMEM_MEMHOLD2_6 (0x40U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 7763 #define FMC_PMEM_MEMHOLD2_7 (0x80U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 7764
NYX 0:85b3fd62ea1a 7765 #define FMC_PMEM_MEMHIZ2_Pos (24U)
NYX 0:85b3fd62ea1a 7766 #define FMC_PMEM_MEMHIZ2_Msk (0xFFU << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 7767 #define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
NYX 0:85b3fd62ea1a 7768 #define FMC_PMEM_MEMHIZ2_0 (0x01U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 7769 #define FMC_PMEM_MEMHIZ2_1 (0x02U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 7770 #define FMC_PMEM_MEMHIZ2_2 (0x04U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 7771 #define FMC_PMEM_MEMHIZ2_3 (0x08U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 7772 #define FMC_PMEM_MEMHIZ2_4 (0x10U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7773 #define FMC_PMEM_MEMHIZ2_5 (0x20U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7774 #define FMC_PMEM_MEMHIZ2_6 (0x40U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 7775 #define FMC_PMEM_MEMHIZ2_7 (0x80U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 7776
NYX 0:85b3fd62ea1a 7777 /****************** Bit definition for FMC_PATT register ******************/
NYX 0:85b3fd62ea1a 7778 #define FMC_PATT_ATTSET2_Pos (0U)
NYX 0:85b3fd62ea1a 7779 #define FMC_PATT_ATTSET2_Msk (0xFFU << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 7780 #define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
NYX 0:85b3fd62ea1a 7781 #define FMC_PATT_ATTSET2_0 (0x01U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7782 #define FMC_PATT_ATTSET2_1 (0x02U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7783 #define FMC_PATT_ATTSET2_2 (0x04U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7784 #define FMC_PATT_ATTSET2_3 (0x08U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7785 #define FMC_PATT_ATTSET2_4 (0x10U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7786 #define FMC_PATT_ATTSET2_5 (0x20U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7787 #define FMC_PATT_ATTSET2_6 (0x40U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7788 #define FMC_PATT_ATTSET2_7 (0x80U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7789
NYX 0:85b3fd62ea1a 7790 #define FMC_PATT_ATTWAIT2_Pos (8U)
NYX 0:85b3fd62ea1a 7791 #define FMC_PATT_ATTWAIT2_Msk (0xFFU << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 7792 #define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
NYX 0:85b3fd62ea1a 7793 #define FMC_PATT_ATTWAIT2_0 (0x01U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7794 #define FMC_PATT_ATTWAIT2_1 (0x02U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7795 #define FMC_PATT_ATTWAIT2_2 (0x04U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7796 #define FMC_PATT_ATTWAIT2_3 (0x08U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7797 #define FMC_PATT_ATTWAIT2_4 (0x10U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7798 #define FMC_PATT_ATTWAIT2_5 (0x20U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7799 #define FMC_PATT_ATTWAIT2_6 (0x40U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7800 #define FMC_PATT_ATTWAIT2_7 (0x80U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 7801
NYX 0:85b3fd62ea1a 7802 #define FMC_PATT_ATTHOLD2_Pos (16U)
NYX 0:85b3fd62ea1a 7803 #define FMC_PATT_ATTHOLD2_Msk (0xFFU << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 7804 #define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
NYX 0:85b3fd62ea1a 7805 #define FMC_PATT_ATTHOLD2_0 (0x01U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7806 #define FMC_PATT_ATTHOLD2_1 (0x02U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7807 #define FMC_PATT_ATTHOLD2_2 (0x04U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7808 #define FMC_PATT_ATTHOLD2_3 (0x08U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 7809 #define FMC_PATT_ATTHOLD2_4 (0x10U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 7810 #define FMC_PATT_ATTHOLD2_5 (0x20U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 7811 #define FMC_PATT_ATTHOLD2_6 (0x40U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 7812 #define FMC_PATT_ATTHOLD2_7 (0x80U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 7813
NYX 0:85b3fd62ea1a 7814 #define FMC_PATT_ATTHIZ2_Pos (24U)
NYX 0:85b3fd62ea1a 7815 #define FMC_PATT_ATTHIZ2_Msk (0xFFU << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 7816 #define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
NYX 0:85b3fd62ea1a 7817 #define FMC_PATT_ATTHIZ2_0 (0x01U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 7818 #define FMC_PATT_ATTHIZ2_1 (0x02U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 7819 #define FMC_PATT_ATTHIZ2_2 (0x04U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 7820 #define FMC_PATT_ATTHIZ2_3 (0x08U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 7821 #define FMC_PATT_ATTHIZ2_4 (0x10U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 7822 #define FMC_PATT_ATTHIZ2_5 (0x20U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 7823 #define FMC_PATT_ATTHIZ2_6 (0x40U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 7824 #define FMC_PATT_ATTHIZ2_7 (0x80U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 7825
NYX 0:85b3fd62ea1a 7826 /****************** Bit definition for FMC_ECCR register ******************/
NYX 0:85b3fd62ea1a 7827 #define FMC_ECCR_ECC2_Pos (0U)
NYX 0:85b3fd62ea1a 7828 #define FMC_ECCR_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 7829 #define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */
NYX 0:85b3fd62ea1a 7830
NYX 0:85b3fd62ea1a 7831 /****************** Bit definition for FMC_SDCR1 register ******************/
NYX 0:85b3fd62ea1a 7832 #define FMC_SDCR1_NC_Pos (0U)
NYX 0:85b3fd62ea1a 7833 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 7834 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
NYX 0:85b3fd62ea1a 7835 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7836 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7837
NYX 0:85b3fd62ea1a 7838 #define FMC_SDCR1_NR_Pos (2U)
NYX 0:85b3fd62ea1a 7839 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 7840 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
NYX 0:85b3fd62ea1a 7841 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7842 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7843
NYX 0:85b3fd62ea1a 7844 #define FMC_SDCR1_MWID_Pos (4U)
NYX 0:85b3fd62ea1a 7845 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 7846 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
NYX 0:85b3fd62ea1a 7847 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7848 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7849
NYX 0:85b3fd62ea1a 7850 #define FMC_SDCR1_NB_Pos (6U)
NYX 0:85b3fd62ea1a 7851 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7852 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
NYX 0:85b3fd62ea1a 7853
NYX 0:85b3fd62ea1a 7854 #define FMC_SDCR1_CAS_Pos (7U)
NYX 0:85b3fd62ea1a 7855 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
NYX 0:85b3fd62ea1a 7856 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
NYX 0:85b3fd62ea1a 7857 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7858 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7859
NYX 0:85b3fd62ea1a 7860 #define FMC_SDCR1_WP_Pos (9U)
NYX 0:85b3fd62ea1a 7861 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7862 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
NYX 0:85b3fd62ea1a 7863
NYX 0:85b3fd62ea1a 7864 #define FMC_SDCR1_SDCLK_Pos (10U)
NYX 0:85b3fd62ea1a 7865 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 7866 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
NYX 0:85b3fd62ea1a 7867 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7868 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7869
NYX 0:85b3fd62ea1a 7870 #define FMC_SDCR1_RBURST_Pos (12U)
NYX 0:85b3fd62ea1a 7871 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7872 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
NYX 0:85b3fd62ea1a 7873
NYX 0:85b3fd62ea1a 7874 #define FMC_SDCR1_RPIPE_Pos (13U)
NYX 0:85b3fd62ea1a 7875 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
NYX 0:85b3fd62ea1a 7876 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
NYX 0:85b3fd62ea1a 7877 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7878 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7879
NYX 0:85b3fd62ea1a 7880 /****************** Bit definition for FMC_SDCR2 register ******************/
NYX 0:85b3fd62ea1a 7881 #define FMC_SDCR2_NC_Pos (0U)
NYX 0:85b3fd62ea1a 7882 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 7883 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
NYX 0:85b3fd62ea1a 7884 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7885 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7886
NYX 0:85b3fd62ea1a 7887 #define FMC_SDCR2_NR_Pos (2U)
NYX 0:85b3fd62ea1a 7888 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 7889 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
NYX 0:85b3fd62ea1a 7890 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7891 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7892
NYX 0:85b3fd62ea1a 7893 #define FMC_SDCR2_MWID_Pos (4U)
NYX 0:85b3fd62ea1a 7894 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 7895 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
NYX 0:85b3fd62ea1a 7896 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7897 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7898
NYX 0:85b3fd62ea1a 7899 #define FMC_SDCR2_NB_Pos (6U)
NYX 0:85b3fd62ea1a 7900 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7901 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
NYX 0:85b3fd62ea1a 7902
NYX 0:85b3fd62ea1a 7903 #define FMC_SDCR2_CAS_Pos (7U)
NYX 0:85b3fd62ea1a 7904 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
NYX 0:85b3fd62ea1a 7905 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
NYX 0:85b3fd62ea1a 7906 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7907 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7908
NYX 0:85b3fd62ea1a 7909 #define FMC_SDCR2_WP_Pos (9U)
NYX 0:85b3fd62ea1a 7910 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7911 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
NYX 0:85b3fd62ea1a 7912
NYX 0:85b3fd62ea1a 7913 #define FMC_SDCR2_SDCLK_Pos (10U)
NYX 0:85b3fd62ea1a 7914 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 7915 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
NYX 0:85b3fd62ea1a 7916 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7917 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7918
NYX 0:85b3fd62ea1a 7919 #define FMC_SDCR2_RBURST_Pos (12U)
NYX 0:85b3fd62ea1a 7920 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7921 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
NYX 0:85b3fd62ea1a 7922
NYX 0:85b3fd62ea1a 7923 #define FMC_SDCR2_RPIPE_Pos (13U)
NYX 0:85b3fd62ea1a 7924 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
NYX 0:85b3fd62ea1a 7925 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
NYX 0:85b3fd62ea1a 7926 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7927 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7928
NYX 0:85b3fd62ea1a 7929 /****************** Bit definition for FMC_SDTR1 register ******************/
NYX 0:85b3fd62ea1a 7930 #define FMC_SDTR1_TMRD_Pos (0U)
NYX 0:85b3fd62ea1a 7931 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7932 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
NYX 0:85b3fd62ea1a 7933 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7934 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7935 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7936 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7937
NYX 0:85b3fd62ea1a 7938 #define FMC_SDTR1_TXSR_Pos (4U)
NYX 0:85b3fd62ea1a 7939 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7940 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
NYX 0:85b3fd62ea1a 7941 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7942 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7943 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7944 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7945
NYX 0:85b3fd62ea1a 7946 #define FMC_SDTR1_TRAS_Pos (8U)
NYX 0:85b3fd62ea1a 7947 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 7948 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
NYX 0:85b3fd62ea1a 7949 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 7950 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 7951 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 7952 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 7953
NYX 0:85b3fd62ea1a 7954 #define FMC_SDTR1_TRC_Pos (12U)
NYX 0:85b3fd62ea1a 7955 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 7956 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
NYX 0:85b3fd62ea1a 7957 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 7958 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 7959 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 7960
NYX 0:85b3fd62ea1a 7961 #define FMC_SDTR1_TWR_Pos (16U)
NYX 0:85b3fd62ea1a 7962 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 7963 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
NYX 0:85b3fd62ea1a 7964 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 7965 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 7966 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 7967
NYX 0:85b3fd62ea1a 7968 #define FMC_SDTR1_TRP_Pos (20U)
NYX 0:85b3fd62ea1a 7969 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 7970 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
NYX 0:85b3fd62ea1a 7971 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 7972 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 7973 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 7974
NYX 0:85b3fd62ea1a 7975 #define FMC_SDTR1_TRCD_Pos (24U)
NYX 0:85b3fd62ea1a 7976 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 7977 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
NYX 0:85b3fd62ea1a 7978 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 7979 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 7980 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 7981
NYX 0:85b3fd62ea1a 7982 /****************** Bit definition for FMC_SDTR2 register ******************/
NYX 0:85b3fd62ea1a 7983 #define FMC_SDTR2_TMRD_Pos (0U)
NYX 0:85b3fd62ea1a 7984 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 7985 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
NYX 0:85b3fd62ea1a 7986 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 7987 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 7988 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 7989 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 7990
NYX 0:85b3fd62ea1a 7991 #define FMC_SDTR2_TXSR_Pos (4U)
NYX 0:85b3fd62ea1a 7992 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 7993 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
NYX 0:85b3fd62ea1a 7994 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 7995 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 7996 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 7997 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 7998
NYX 0:85b3fd62ea1a 7999 #define FMC_SDTR2_TRAS_Pos (8U)
NYX 0:85b3fd62ea1a 8000 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 8001 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
NYX 0:85b3fd62ea1a 8002 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8003 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8004 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8005 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8006
NYX 0:85b3fd62ea1a 8007 #define FMC_SDTR2_TRC_Pos (12U)
NYX 0:85b3fd62ea1a 8008 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 8009 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
NYX 0:85b3fd62ea1a 8010 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8011 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8012 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8013
NYX 0:85b3fd62ea1a 8014 #define FMC_SDTR2_TWR_Pos (16U)
NYX 0:85b3fd62ea1a 8015 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 8016 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
NYX 0:85b3fd62ea1a 8017 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 8018 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 8019 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 8020
NYX 0:85b3fd62ea1a 8021 #define FMC_SDTR2_TRP_Pos (20U)
NYX 0:85b3fd62ea1a 8022 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 8023 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
NYX 0:85b3fd62ea1a 8024 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 8025 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 8026 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 8027
NYX 0:85b3fd62ea1a 8028 #define FMC_SDTR2_TRCD_Pos (24U)
NYX 0:85b3fd62ea1a 8029 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 8030 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
NYX 0:85b3fd62ea1a 8031 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 8032 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 8033 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 8034
NYX 0:85b3fd62ea1a 8035 /****************** Bit definition for FMC_SDCMR register ******************/
NYX 0:85b3fd62ea1a 8036 #define FMC_SDCMR_MODE_Pos (0U)
NYX 0:85b3fd62ea1a 8037 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 8038 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
NYX 0:85b3fd62ea1a 8039 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8040 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8041 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8042
NYX 0:85b3fd62ea1a 8043 #define FMC_SDCMR_CTB2_Pos (3U)
NYX 0:85b3fd62ea1a 8044 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8045 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
NYX 0:85b3fd62ea1a 8046
NYX 0:85b3fd62ea1a 8047 #define FMC_SDCMR_CTB1_Pos (4U)
NYX 0:85b3fd62ea1a 8048 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8049 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
NYX 0:85b3fd62ea1a 8050
NYX 0:85b3fd62ea1a 8051 #define FMC_SDCMR_NRFS_Pos (5U)
NYX 0:85b3fd62ea1a 8052 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
NYX 0:85b3fd62ea1a 8053 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
NYX 0:85b3fd62ea1a 8054 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8055 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8056 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8057 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8058
NYX 0:85b3fd62ea1a 8059 #define FMC_SDCMR_MRD_Pos (9U)
NYX 0:85b3fd62ea1a 8060 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
NYX 0:85b3fd62ea1a 8061 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
NYX 0:85b3fd62ea1a 8062
NYX 0:85b3fd62ea1a 8063 /****************** Bit definition for FMC_SDRTR register ******************/
NYX 0:85b3fd62ea1a 8064 #define FMC_SDRTR_CRE_Pos (0U)
NYX 0:85b3fd62ea1a 8065 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8066 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
NYX 0:85b3fd62ea1a 8067
NYX 0:85b3fd62ea1a 8068 #define FMC_SDRTR_COUNT_Pos (1U)
NYX 0:85b3fd62ea1a 8069 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
NYX 0:85b3fd62ea1a 8070 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
NYX 0:85b3fd62ea1a 8071
NYX 0:85b3fd62ea1a 8072 #define FMC_SDRTR_REIE_Pos (14U)
NYX 0:85b3fd62ea1a 8073 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8074 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
NYX 0:85b3fd62ea1a 8075
NYX 0:85b3fd62ea1a 8076 /****************** Bit definition for FMC_SDSR register ******************/
NYX 0:85b3fd62ea1a 8077 #define FMC_SDSR_RE_Pos (0U)
NYX 0:85b3fd62ea1a 8078 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8079 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
NYX 0:85b3fd62ea1a 8080
NYX 0:85b3fd62ea1a 8081 #define FMC_SDSR_MODES1_Pos (1U)
NYX 0:85b3fd62ea1a 8082 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
NYX 0:85b3fd62ea1a 8083 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
NYX 0:85b3fd62ea1a 8084 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8085 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8086
NYX 0:85b3fd62ea1a 8087 #define FMC_SDSR_MODES2_Pos (3U)
NYX 0:85b3fd62ea1a 8088 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
NYX 0:85b3fd62ea1a 8089 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
NYX 0:85b3fd62ea1a 8090 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8091 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8092 #define FMC_SDSR_BUSY_Pos (5U)
NYX 0:85b3fd62ea1a 8093 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8094 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
NYX 0:85b3fd62ea1a 8095
NYX 0:85b3fd62ea1a 8096 /******************************************************************************/
NYX 0:85b3fd62ea1a 8097 /* */
NYX 0:85b3fd62ea1a 8098 /* General Purpose I/O */
NYX 0:85b3fd62ea1a 8099 /* */
NYX 0:85b3fd62ea1a 8100 /******************************************************************************/
NYX 0:85b3fd62ea1a 8101 /****************** Bits definition for GPIO_MODER register *****************/
NYX 0:85b3fd62ea1a 8102 #define GPIO_MODER_MODE0_Pos (0U)
NYX 0:85b3fd62ea1a 8103 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 8104 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
NYX 0:85b3fd62ea1a 8105 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8106 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8107 #define GPIO_MODER_MODE1_Pos (2U)
NYX 0:85b3fd62ea1a 8108 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 8109 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
NYX 0:85b3fd62ea1a 8110 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8111 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8112 #define GPIO_MODER_MODE2_Pos (4U)
NYX 0:85b3fd62ea1a 8113 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 8114 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
NYX 0:85b3fd62ea1a 8115 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8116 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8117 #define GPIO_MODER_MODE3_Pos (6U)
NYX 0:85b3fd62ea1a 8118 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 8119 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
NYX 0:85b3fd62ea1a 8120 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8121 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8122 #define GPIO_MODER_MODE4_Pos (8U)
NYX 0:85b3fd62ea1a 8123 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 8124 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
NYX 0:85b3fd62ea1a 8125 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8126 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8127 #define GPIO_MODER_MODE5_Pos (10U)
NYX 0:85b3fd62ea1a 8128 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 8129 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
NYX 0:85b3fd62ea1a 8130 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8131 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8132 #define GPIO_MODER_MODE6_Pos (12U)
NYX 0:85b3fd62ea1a 8133 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
NYX 0:85b3fd62ea1a 8134 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
NYX 0:85b3fd62ea1a 8135 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8136 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8137 #define GPIO_MODER_MODE7_Pos (14U)
NYX 0:85b3fd62ea1a 8138 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
NYX 0:85b3fd62ea1a 8139 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
NYX 0:85b3fd62ea1a 8140 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8141 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8142 #define GPIO_MODER_MODE8_Pos (16U)
NYX 0:85b3fd62ea1a 8143 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 8144 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
NYX 0:85b3fd62ea1a 8145 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 8146 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 8147 #define GPIO_MODER_MODE9_Pos (18U)
NYX 0:85b3fd62ea1a 8148 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
NYX 0:85b3fd62ea1a 8149 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
NYX 0:85b3fd62ea1a 8150 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 8151 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 8152 #define GPIO_MODER_MODE10_Pos (20U)
NYX 0:85b3fd62ea1a 8153 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 8154 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
NYX 0:85b3fd62ea1a 8155 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 8156 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 8157 #define GPIO_MODER_MODE11_Pos (22U)
NYX 0:85b3fd62ea1a 8158 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
NYX 0:85b3fd62ea1a 8159 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
NYX 0:85b3fd62ea1a 8160 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 8161 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 8162 #define GPIO_MODER_MODE12_Pos (24U)
NYX 0:85b3fd62ea1a 8163 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
NYX 0:85b3fd62ea1a 8164 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
NYX 0:85b3fd62ea1a 8165 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 8166 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 8167 #define GPIO_MODER_MODE13_Pos (26U)
NYX 0:85b3fd62ea1a 8168 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
NYX 0:85b3fd62ea1a 8169 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
NYX 0:85b3fd62ea1a 8170 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 8171 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 8172 #define GPIO_MODER_MODE14_Pos (28U)
NYX 0:85b3fd62ea1a 8173 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 8174 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
NYX 0:85b3fd62ea1a 8175 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 8176 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 8177 #define GPIO_MODER_MODE15_Pos (30U)
NYX 0:85b3fd62ea1a 8178 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
NYX 0:85b3fd62ea1a 8179 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
NYX 0:85b3fd62ea1a 8180 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 8181 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 8182
NYX 0:85b3fd62ea1a 8183 /* Legacy defines */
NYX 0:85b3fd62ea1a 8184 #define GPIO_MODER_MODER0_Pos (0U)
NYX 0:85b3fd62ea1a 8185 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 8186 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
NYX 0:85b3fd62ea1a 8187 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8188 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8189 #define GPIO_MODER_MODER1_Pos (2U)
NYX 0:85b3fd62ea1a 8190 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 8191 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
NYX 0:85b3fd62ea1a 8192 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8193 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8194 #define GPIO_MODER_MODER2_Pos (4U)
NYX 0:85b3fd62ea1a 8195 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 8196 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
NYX 0:85b3fd62ea1a 8197 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8198 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8199 #define GPIO_MODER_MODER3_Pos (6U)
NYX 0:85b3fd62ea1a 8200 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 8201 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
NYX 0:85b3fd62ea1a 8202 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8203 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8204 #define GPIO_MODER_MODER4_Pos (8U)
NYX 0:85b3fd62ea1a 8205 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 8206 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
NYX 0:85b3fd62ea1a 8207 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8208 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8209 #define GPIO_MODER_MODER5_Pos (10U)
NYX 0:85b3fd62ea1a 8210 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 8211 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
NYX 0:85b3fd62ea1a 8212 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8213 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8214 #define GPIO_MODER_MODER6_Pos (12U)
NYX 0:85b3fd62ea1a 8215 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
NYX 0:85b3fd62ea1a 8216 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
NYX 0:85b3fd62ea1a 8217 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8218 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8219 #define GPIO_MODER_MODER7_Pos (14U)
NYX 0:85b3fd62ea1a 8220 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
NYX 0:85b3fd62ea1a 8221 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
NYX 0:85b3fd62ea1a 8222 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8223 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8224 #define GPIO_MODER_MODER8_Pos (16U)
NYX 0:85b3fd62ea1a 8225 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 8226 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
NYX 0:85b3fd62ea1a 8227 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 8228 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 8229 #define GPIO_MODER_MODER9_Pos (18U)
NYX 0:85b3fd62ea1a 8230 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
NYX 0:85b3fd62ea1a 8231 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
NYX 0:85b3fd62ea1a 8232 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 8233 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 8234 #define GPIO_MODER_MODER10_Pos (20U)
NYX 0:85b3fd62ea1a 8235 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 8236 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
NYX 0:85b3fd62ea1a 8237 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 8238 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 8239 #define GPIO_MODER_MODER11_Pos (22U)
NYX 0:85b3fd62ea1a 8240 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
NYX 0:85b3fd62ea1a 8241 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
NYX 0:85b3fd62ea1a 8242 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 8243 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 8244 #define GPIO_MODER_MODER12_Pos (24U)
NYX 0:85b3fd62ea1a 8245 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
NYX 0:85b3fd62ea1a 8246 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
NYX 0:85b3fd62ea1a 8247 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 8248 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 8249 #define GPIO_MODER_MODER13_Pos (26U)
NYX 0:85b3fd62ea1a 8250 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
NYX 0:85b3fd62ea1a 8251 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
NYX 0:85b3fd62ea1a 8252 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 8253 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 8254 #define GPIO_MODER_MODER14_Pos (28U)
NYX 0:85b3fd62ea1a 8255 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 8256 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
NYX 0:85b3fd62ea1a 8257 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 8258 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 8259 #define GPIO_MODER_MODER15_Pos (30U)
NYX 0:85b3fd62ea1a 8260 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
NYX 0:85b3fd62ea1a 8261 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
NYX 0:85b3fd62ea1a 8262 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 8263 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 8264
NYX 0:85b3fd62ea1a 8265 /****************** Bits definition for GPIO_OTYPER register ****************/
NYX 0:85b3fd62ea1a 8266 #define GPIO_OTYPER_OT0_Pos (0U)
NYX 0:85b3fd62ea1a 8267 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8268 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
NYX 0:85b3fd62ea1a 8269 #define GPIO_OTYPER_OT1_Pos (1U)
NYX 0:85b3fd62ea1a 8270 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8271 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
NYX 0:85b3fd62ea1a 8272 #define GPIO_OTYPER_OT2_Pos (2U)
NYX 0:85b3fd62ea1a 8273 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8274 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
NYX 0:85b3fd62ea1a 8275 #define GPIO_OTYPER_OT3_Pos (3U)
NYX 0:85b3fd62ea1a 8276 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8277 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
NYX 0:85b3fd62ea1a 8278 #define GPIO_OTYPER_OT4_Pos (4U)
NYX 0:85b3fd62ea1a 8279 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8280 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
NYX 0:85b3fd62ea1a 8281 #define GPIO_OTYPER_OT5_Pos (5U)
NYX 0:85b3fd62ea1a 8282 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8283 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
NYX 0:85b3fd62ea1a 8284 #define GPIO_OTYPER_OT6_Pos (6U)
NYX 0:85b3fd62ea1a 8285 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8286 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
NYX 0:85b3fd62ea1a 8287 #define GPIO_OTYPER_OT7_Pos (7U)
NYX 0:85b3fd62ea1a 8288 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8289 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
NYX 0:85b3fd62ea1a 8290 #define GPIO_OTYPER_OT8_Pos (8U)
NYX 0:85b3fd62ea1a 8291 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8292 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
NYX 0:85b3fd62ea1a 8293 #define GPIO_OTYPER_OT9_Pos (9U)
NYX 0:85b3fd62ea1a 8294 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8295 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
NYX 0:85b3fd62ea1a 8296 #define GPIO_OTYPER_OT10_Pos (10U)
NYX 0:85b3fd62ea1a 8297 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8298 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
NYX 0:85b3fd62ea1a 8299 #define GPIO_OTYPER_OT11_Pos (11U)
NYX 0:85b3fd62ea1a 8300 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8301 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
NYX 0:85b3fd62ea1a 8302 #define GPIO_OTYPER_OT12_Pos (12U)
NYX 0:85b3fd62ea1a 8303 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8304 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
NYX 0:85b3fd62ea1a 8305 #define GPIO_OTYPER_OT13_Pos (13U)
NYX 0:85b3fd62ea1a 8306 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8307 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
NYX 0:85b3fd62ea1a 8308 #define GPIO_OTYPER_OT14_Pos (14U)
NYX 0:85b3fd62ea1a 8309 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8310 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
NYX 0:85b3fd62ea1a 8311 #define GPIO_OTYPER_OT15_Pos (15U)
NYX 0:85b3fd62ea1a 8312 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8313 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
NYX 0:85b3fd62ea1a 8314
NYX 0:85b3fd62ea1a 8315 /* Legacy defines */
NYX 0:85b3fd62ea1a 8316 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
NYX 0:85b3fd62ea1a 8317 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
NYX 0:85b3fd62ea1a 8318 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
NYX 0:85b3fd62ea1a 8319 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
NYX 0:85b3fd62ea1a 8320 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
NYX 0:85b3fd62ea1a 8321 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
NYX 0:85b3fd62ea1a 8322 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
NYX 0:85b3fd62ea1a 8323 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
NYX 0:85b3fd62ea1a 8324 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
NYX 0:85b3fd62ea1a 8325 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
NYX 0:85b3fd62ea1a 8326 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
NYX 0:85b3fd62ea1a 8327 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
NYX 0:85b3fd62ea1a 8328 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
NYX 0:85b3fd62ea1a 8329 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
NYX 0:85b3fd62ea1a 8330 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
NYX 0:85b3fd62ea1a 8331 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
NYX 0:85b3fd62ea1a 8332
NYX 0:85b3fd62ea1a 8333 /****************** Bits definition for GPIO_OSPEEDR register ***************/
NYX 0:85b3fd62ea1a 8334 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
NYX 0:85b3fd62ea1a 8335 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 8336 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
NYX 0:85b3fd62ea1a 8337 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8338 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8339 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
NYX 0:85b3fd62ea1a 8340 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 8341 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
NYX 0:85b3fd62ea1a 8342 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8343 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8344 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
NYX 0:85b3fd62ea1a 8345 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 8346 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
NYX 0:85b3fd62ea1a 8347 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8348 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8349 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
NYX 0:85b3fd62ea1a 8350 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 8351 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
NYX 0:85b3fd62ea1a 8352 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8353 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8354 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
NYX 0:85b3fd62ea1a 8355 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 8356 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
NYX 0:85b3fd62ea1a 8357 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8358 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8359 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
NYX 0:85b3fd62ea1a 8360 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 8361 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
NYX 0:85b3fd62ea1a 8362 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8363 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8364 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
NYX 0:85b3fd62ea1a 8365 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
NYX 0:85b3fd62ea1a 8366 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
NYX 0:85b3fd62ea1a 8367 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8368 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8369 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
NYX 0:85b3fd62ea1a 8370 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
NYX 0:85b3fd62ea1a 8371 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
NYX 0:85b3fd62ea1a 8372 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8373 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8374 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
NYX 0:85b3fd62ea1a 8375 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 8376 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
NYX 0:85b3fd62ea1a 8377 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 8378 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 8379 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
NYX 0:85b3fd62ea1a 8380 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
NYX 0:85b3fd62ea1a 8381 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
NYX 0:85b3fd62ea1a 8382 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 8383 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 8384 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
NYX 0:85b3fd62ea1a 8385 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 8386 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
NYX 0:85b3fd62ea1a 8387 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 8388 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 8389 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
NYX 0:85b3fd62ea1a 8390 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
NYX 0:85b3fd62ea1a 8391 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
NYX 0:85b3fd62ea1a 8392 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 8393 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 8394 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
NYX 0:85b3fd62ea1a 8395 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
NYX 0:85b3fd62ea1a 8396 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
NYX 0:85b3fd62ea1a 8397 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 8398 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 8399 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
NYX 0:85b3fd62ea1a 8400 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
NYX 0:85b3fd62ea1a 8401 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
NYX 0:85b3fd62ea1a 8402 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 8403 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 8404 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
NYX 0:85b3fd62ea1a 8405 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 8406 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
NYX 0:85b3fd62ea1a 8407 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 8408 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 8409 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
NYX 0:85b3fd62ea1a 8410 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
NYX 0:85b3fd62ea1a 8411 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
NYX 0:85b3fd62ea1a 8412 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 8413 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 8414
NYX 0:85b3fd62ea1a 8415 /* Legacy defines */
NYX 0:85b3fd62ea1a 8416 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
NYX 0:85b3fd62ea1a 8417 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
NYX 0:85b3fd62ea1a 8418 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
NYX 0:85b3fd62ea1a 8419 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
NYX 0:85b3fd62ea1a 8420 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
NYX 0:85b3fd62ea1a 8421 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
NYX 0:85b3fd62ea1a 8422 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
NYX 0:85b3fd62ea1a 8423 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
NYX 0:85b3fd62ea1a 8424 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
NYX 0:85b3fd62ea1a 8425 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
NYX 0:85b3fd62ea1a 8426 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
NYX 0:85b3fd62ea1a 8427 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
NYX 0:85b3fd62ea1a 8428 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
NYX 0:85b3fd62ea1a 8429 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
NYX 0:85b3fd62ea1a 8430 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
NYX 0:85b3fd62ea1a 8431 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
NYX 0:85b3fd62ea1a 8432 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
NYX 0:85b3fd62ea1a 8433 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
NYX 0:85b3fd62ea1a 8434 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
NYX 0:85b3fd62ea1a 8435 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
NYX 0:85b3fd62ea1a 8436 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
NYX 0:85b3fd62ea1a 8437 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
NYX 0:85b3fd62ea1a 8438 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
NYX 0:85b3fd62ea1a 8439 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
NYX 0:85b3fd62ea1a 8440 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
NYX 0:85b3fd62ea1a 8441 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
NYX 0:85b3fd62ea1a 8442 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
NYX 0:85b3fd62ea1a 8443 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
NYX 0:85b3fd62ea1a 8444 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
NYX 0:85b3fd62ea1a 8445 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
NYX 0:85b3fd62ea1a 8446 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
NYX 0:85b3fd62ea1a 8447 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
NYX 0:85b3fd62ea1a 8448 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
NYX 0:85b3fd62ea1a 8449 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
NYX 0:85b3fd62ea1a 8450 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
NYX 0:85b3fd62ea1a 8451 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
NYX 0:85b3fd62ea1a 8452 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
NYX 0:85b3fd62ea1a 8453 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
NYX 0:85b3fd62ea1a 8454 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
NYX 0:85b3fd62ea1a 8455 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
NYX 0:85b3fd62ea1a 8456 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
NYX 0:85b3fd62ea1a 8457 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
NYX 0:85b3fd62ea1a 8458 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
NYX 0:85b3fd62ea1a 8459 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
NYX 0:85b3fd62ea1a 8460 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
NYX 0:85b3fd62ea1a 8461 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
NYX 0:85b3fd62ea1a 8462 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
NYX 0:85b3fd62ea1a 8463 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
NYX 0:85b3fd62ea1a 8464
NYX 0:85b3fd62ea1a 8465 /****************** Bits definition for GPIO_PUPDR register *****************/
NYX 0:85b3fd62ea1a 8466 #define GPIO_PUPDR_PUPD0_Pos (0U)
NYX 0:85b3fd62ea1a 8467 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 8468 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
NYX 0:85b3fd62ea1a 8469 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8470 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8471 #define GPIO_PUPDR_PUPD1_Pos (2U)
NYX 0:85b3fd62ea1a 8472 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 8473 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
NYX 0:85b3fd62ea1a 8474 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8475 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8476 #define GPIO_PUPDR_PUPD2_Pos (4U)
NYX 0:85b3fd62ea1a 8477 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 8478 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
NYX 0:85b3fd62ea1a 8479 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8480 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8481 #define GPIO_PUPDR_PUPD3_Pos (6U)
NYX 0:85b3fd62ea1a 8482 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 8483 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
NYX 0:85b3fd62ea1a 8484 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8485 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8486 #define GPIO_PUPDR_PUPD4_Pos (8U)
NYX 0:85b3fd62ea1a 8487 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 8488 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
NYX 0:85b3fd62ea1a 8489 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8490 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8491 #define GPIO_PUPDR_PUPD5_Pos (10U)
NYX 0:85b3fd62ea1a 8492 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 8493 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
NYX 0:85b3fd62ea1a 8494 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8495 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8496 #define GPIO_PUPDR_PUPD6_Pos (12U)
NYX 0:85b3fd62ea1a 8497 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
NYX 0:85b3fd62ea1a 8498 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
NYX 0:85b3fd62ea1a 8499 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8500 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8501 #define GPIO_PUPDR_PUPD7_Pos (14U)
NYX 0:85b3fd62ea1a 8502 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
NYX 0:85b3fd62ea1a 8503 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
NYX 0:85b3fd62ea1a 8504 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8505 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8506 #define GPIO_PUPDR_PUPD8_Pos (16U)
NYX 0:85b3fd62ea1a 8507 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 8508 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
NYX 0:85b3fd62ea1a 8509 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 8510 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 8511 #define GPIO_PUPDR_PUPD9_Pos (18U)
NYX 0:85b3fd62ea1a 8512 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
NYX 0:85b3fd62ea1a 8513 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
NYX 0:85b3fd62ea1a 8514 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 8515 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 8516 #define GPIO_PUPDR_PUPD10_Pos (20U)
NYX 0:85b3fd62ea1a 8517 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 8518 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
NYX 0:85b3fd62ea1a 8519 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 8520 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 8521 #define GPIO_PUPDR_PUPD11_Pos (22U)
NYX 0:85b3fd62ea1a 8522 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
NYX 0:85b3fd62ea1a 8523 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
NYX 0:85b3fd62ea1a 8524 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 8525 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 8526 #define GPIO_PUPDR_PUPD12_Pos (24U)
NYX 0:85b3fd62ea1a 8527 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
NYX 0:85b3fd62ea1a 8528 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
NYX 0:85b3fd62ea1a 8529 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 8530 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 8531 #define GPIO_PUPDR_PUPD13_Pos (26U)
NYX 0:85b3fd62ea1a 8532 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
NYX 0:85b3fd62ea1a 8533 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
NYX 0:85b3fd62ea1a 8534 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 8535 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 8536 #define GPIO_PUPDR_PUPD14_Pos (28U)
NYX 0:85b3fd62ea1a 8537 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 8538 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
NYX 0:85b3fd62ea1a 8539 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 8540 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 8541 #define GPIO_PUPDR_PUPD15_Pos (30U)
NYX 0:85b3fd62ea1a 8542 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
NYX 0:85b3fd62ea1a 8543 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
NYX 0:85b3fd62ea1a 8544 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 8545 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 8546
NYX 0:85b3fd62ea1a 8547 /* Legacy defines */
NYX 0:85b3fd62ea1a 8548 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
NYX 0:85b3fd62ea1a 8549 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
NYX 0:85b3fd62ea1a 8550 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
NYX 0:85b3fd62ea1a 8551 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
NYX 0:85b3fd62ea1a 8552 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
NYX 0:85b3fd62ea1a 8553 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
NYX 0:85b3fd62ea1a 8554 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
NYX 0:85b3fd62ea1a 8555 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
NYX 0:85b3fd62ea1a 8556 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
NYX 0:85b3fd62ea1a 8557 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
NYX 0:85b3fd62ea1a 8558 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
NYX 0:85b3fd62ea1a 8559 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
NYX 0:85b3fd62ea1a 8560 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
NYX 0:85b3fd62ea1a 8561 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
NYX 0:85b3fd62ea1a 8562 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
NYX 0:85b3fd62ea1a 8563 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
NYX 0:85b3fd62ea1a 8564 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
NYX 0:85b3fd62ea1a 8565 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
NYX 0:85b3fd62ea1a 8566 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
NYX 0:85b3fd62ea1a 8567 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
NYX 0:85b3fd62ea1a 8568 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
NYX 0:85b3fd62ea1a 8569 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
NYX 0:85b3fd62ea1a 8570 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
NYX 0:85b3fd62ea1a 8571 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
NYX 0:85b3fd62ea1a 8572 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
NYX 0:85b3fd62ea1a 8573 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
NYX 0:85b3fd62ea1a 8574 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
NYX 0:85b3fd62ea1a 8575 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
NYX 0:85b3fd62ea1a 8576 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
NYX 0:85b3fd62ea1a 8577 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
NYX 0:85b3fd62ea1a 8578 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
NYX 0:85b3fd62ea1a 8579 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
NYX 0:85b3fd62ea1a 8580 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
NYX 0:85b3fd62ea1a 8581 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
NYX 0:85b3fd62ea1a 8582 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
NYX 0:85b3fd62ea1a 8583 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
NYX 0:85b3fd62ea1a 8584 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
NYX 0:85b3fd62ea1a 8585 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
NYX 0:85b3fd62ea1a 8586 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
NYX 0:85b3fd62ea1a 8587 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
NYX 0:85b3fd62ea1a 8588 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
NYX 0:85b3fd62ea1a 8589 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
NYX 0:85b3fd62ea1a 8590 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
NYX 0:85b3fd62ea1a 8591 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
NYX 0:85b3fd62ea1a 8592 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
NYX 0:85b3fd62ea1a 8593 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
NYX 0:85b3fd62ea1a 8594 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
NYX 0:85b3fd62ea1a 8595 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
NYX 0:85b3fd62ea1a 8596
NYX 0:85b3fd62ea1a 8597 /****************** Bits definition for GPIO_IDR register *******************/
NYX 0:85b3fd62ea1a 8598 #define GPIO_IDR_ID0_Pos (0U)
NYX 0:85b3fd62ea1a 8599 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8600 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
NYX 0:85b3fd62ea1a 8601 #define GPIO_IDR_ID1_Pos (1U)
NYX 0:85b3fd62ea1a 8602 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8603 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
NYX 0:85b3fd62ea1a 8604 #define GPIO_IDR_ID2_Pos (2U)
NYX 0:85b3fd62ea1a 8605 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8606 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
NYX 0:85b3fd62ea1a 8607 #define GPIO_IDR_ID3_Pos (3U)
NYX 0:85b3fd62ea1a 8608 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8609 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
NYX 0:85b3fd62ea1a 8610 #define GPIO_IDR_ID4_Pos (4U)
NYX 0:85b3fd62ea1a 8611 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8612 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
NYX 0:85b3fd62ea1a 8613 #define GPIO_IDR_ID5_Pos (5U)
NYX 0:85b3fd62ea1a 8614 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8615 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
NYX 0:85b3fd62ea1a 8616 #define GPIO_IDR_ID6_Pos (6U)
NYX 0:85b3fd62ea1a 8617 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8618 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
NYX 0:85b3fd62ea1a 8619 #define GPIO_IDR_ID7_Pos (7U)
NYX 0:85b3fd62ea1a 8620 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8621 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
NYX 0:85b3fd62ea1a 8622 #define GPIO_IDR_ID8_Pos (8U)
NYX 0:85b3fd62ea1a 8623 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8624 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
NYX 0:85b3fd62ea1a 8625 #define GPIO_IDR_ID9_Pos (9U)
NYX 0:85b3fd62ea1a 8626 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8627 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
NYX 0:85b3fd62ea1a 8628 #define GPIO_IDR_ID10_Pos (10U)
NYX 0:85b3fd62ea1a 8629 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8630 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
NYX 0:85b3fd62ea1a 8631 #define GPIO_IDR_ID11_Pos (11U)
NYX 0:85b3fd62ea1a 8632 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8633 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
NYX 0:85b3fd62ea1a 8634 #define GPIO_IDR_ID12_Pos (12U)
NYX 0:85b3fd62ea1a 8635 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8636 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
NYX 0:85b3fd62ea1a 8637 #define GPIO_IDR_ID13_Pos (13U)
NYX 0:85b3fd62ea1a 8638 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8639 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
NYX 0:85b3fd62ea1a 8640 #define GPIO_IDR_ID14_Pos (14U)
NYX 0:85b3fd62ea1a 8641 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8642 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
NYX 0:85b3fd62ea1a 8643 #define GPIO_IDR_ID15_Pos (15U)
NYX 0:85b3fd62ea1a 8644 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8645 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
NYX 0:85b3fd62ea1a 8646
NYX 0:85b3fd62ea1a 8647 /* Legacy defines */
NYX 0:85b3fd62ea1a 8648 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
NYX 0:85b3fd62ea1a 8649 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
NYX 0:85b3fd62ea1a 8650 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
NYX 0:85b3fd62ea1a 8651 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
NYX 0:85b3fd62ea1a 8652 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
NYX 0:85b3fd62ea1a 8653 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
NYX 0:85b3fd62ea1a 8654 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
NYX 0:85b3fd62ea1a 8655 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
NYX 0:85b3fd62ea1a 8656 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
NYX 0:85b3fd62ea1a 8657 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
NYX 0:85b3fd62ea1a 8658 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
NYX 0:85b3fd62ea1a 8659 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
NYX 0:85b3fd62ea1a 8660 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
NYX 0:85b3fd62ea1a 8661 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
NYX 0:85b3fd62ea1a 8662 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
NYX 0:85b3fd62ea1a 8663 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
NYX 0:85b3fd62ea1a 8664
NYX 0:85b3fd62ea1a 8665 /****************** Bits definition for GPIO_ODR register *******************/
NYX 0:85b3fd62ea1a 8666 #define GPIO_ODR_OD0_Pos (0U)
NYX 0:85b3fd62ea1a 8667 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8668 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
NYX 0:85b3fd62ea1a 8669 #define GPIO_ODR_OD1_Pos (1U)
NYX 0:85b3fd62ea1a 8670 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8671 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
NYX 0:85b3fd62ea1a 8672 #define GPIO_ODR_OD2_Pos (2U)
NYX 0:85b3fd62ea1a 8673 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8674 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
NYX 0:85b3fd62ea1a 8675 #define GPIO_ODR_OD3_Pos (3U)
NYX 0:85b3fd62ea1a 8676 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8677 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
NYX 0:85b3fd62ea1a 8678 #define GPIO_ODR_OD4_Pos (4U)
NYX 0:85b3fd62ea1a 8679 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8680 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
NYX 0:85b3fd62ea1a 8681 #define GPIO_ODR_OD5_Pos (5U)
NYX 0:85b3fd62ea1a 8682 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8683 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
NYX 0:85b3fd62ea1a 8684 #define GPIO_ODR_OD6_Pos (6U)
NYX 0:85b3fd62ea1a 8685 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8686 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
NYX 0:85b3fd62ea1a 8687 #define GPIO_ODR_OD7_Pos (7U)
NYX 0:85b3fd62ea1a 8688 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8689 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
NYX 0:85b3fd62ea1a 8690 #define GPIO_ODR_OD8_Pos (8U)
NYX 0:85b3fd62ea1a 8691 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8692 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
NYX 0:85b3fd62ea1a 8693 #define GPIO_ODR_OD9_Pos (9U)
NYX 0:85b3fd62ea1a 8694 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8695 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
NYX 0:85b3fd62ea1a 8696 #define GPIO_ODR_OD10_Pos (10U)
NYX 0:85b3fd62ea1a 8697 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8698 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
NYX 0:85b3fd62ea1a 8699 #define GPIO_ODR_OD11_Pos (11U)
NYX 0:85b3fd62ea1a 8700 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8701 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
NYX 0:85b3fd62ea1a 8702 #define GPIO_ODR_OD12_Pos (12U)
NYX 0:85b3fd62ea1a 8703 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8704 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
NYX 0:85b3fd62ea1a 8705 #define GPIO_ODR_OD13_Pos (13U)
NYX 0:85b3fd62ea1a 8706 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8707 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
NYX 0:85b3fd62ea1a 8708 #define GPIO_ODR_OD14_Pos (14U)
NYX 0:85b3fd62ea1a 8709 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8710 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
NYX 0:85b3fd62ea1a 8711 #define GPIO_ODR_OD15_Pos (15U)
NYX 0:85b3fd62ea1a 8712 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8713 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
NYX 0:85b3fd62ea1a 8714 /* Legacy defines */
NYX 0:85b3fd62ea1a 8715 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
NYX 0:85b3fd62ea1a 8716 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
NYX 0:85b3fd62ea1a 8717 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
NYX 0:85b3fd62ea1a 8718 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
NYX 0:85b3fd62ea1a 8719 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
NYX 0:85b3fd62ea1a 8720 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
NYX 0:85b3fd62ea1a 8721 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
NYX 0:85b3fd62ea1a 8722 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
NYX 0:85b3fd62ea1a 8723 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
NYX 0:85b3fd62ea1a 8724 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
NYX 0:85b3fd62ea1a 8725 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
NYX 0:85b3fd62ea1a 8726 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
NYX 0:85b3fd62ea1a 8727 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
NYX 0:85b3fd62ea1a 8728 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
NYX 0:85b3fd62ea1a 8729 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
NYX 0:85b3fd62ea1a 8730 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
NYX 0:85b3fd62ea1a 8731
NYX 0:85b3fd62ea1a 8732 /****************** Bits definition for GPIO_BSRR register ******************/
NYX 0:85b3fd62ea1a 8733 #define GPIO_BSRR_BS0_Pos (0U)
NYX 0:85b3fd62ea1a 8734 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8735 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
NYX 0:85b3fd62ea1a 8736 #define GPIO_BSRR_BS1_Pos (1U)
NYX 0:85b3fd62ea1a 8737 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8738 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
NYX 0:85b3fd62ea1a 8739 #define GPIO_BSRR_BS2_Pos (2U)
NYX 0:85b3fd62ea1a 8740 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8741 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
NYX 0:85b3fd62ea1a 8742 #define GPIO_BSRR_BS3_Pos (3U)
NYX 0:85b3fd62ea1a 8743 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8744 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
NYX 0:85b3fd62ea1a 8745 #define GPIO_BSRR_BS4_Pos (4U)
NYX 0:85b3fd62ea1a 8746 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8747 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
NYX 0:85b3fd62ea1a 8748 #define GPIO_BSRR_BS5_Pos (5U)
NYX 0:85b3fd62ea1a 8749 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8750 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
NYX 0:85b3fd62ea1a 8751 #define GPIO_BSRR_BS6_Pos (6U)
NYX 0:85b3fd62ea1a 8752 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8753 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
NYX 0:85b3fd62ea1a 8754 #define GPIO_BSRR_BS7_Pos (7U)
NYX 0:85b3fd62ea1a 8755 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8756 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
NYX 0:85b3fd62ea1a 8757 #define GPIO_BSRR_BS8_Pos (8U)
NYX 0:85b3fd62ea1a 8758 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8759 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
NYX 0:85b3fd62ea1a 8760 #define GPIO_BSRR_BS9_Pos (9U)
NYX 0:85b3fd62ea1a 8761 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8762 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
NYX 0:85b3fd62ea1a 8763 #define GPIO_BSRR_BS10_Pos (10U)
NYX 0:85b3fd62ea1a 8764 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8765 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
NYX 0:85b3fd62ea1a 8766 #define GPIO_BSRR_BS11_Pos (11U)
NYX 0:85b3fd62ea1a 8767 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8768 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
NYX 0:85b3fd62ea1a 8769 #define GPIO_BSRR_BS12_Pos (12U)
NYX 0:85b3fd62ea1a 8770 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8771 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
NYX 0:85b3fd62ea1a 8772 #define GPIO_BSRR_BS13_Pos (13U)
NYX 0:85b3fd62ea1a 8773 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8774 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
NYX 0:85b3fd62ea1a 8775 #define GPIO_BSRR_BS14_Pos (14U)
NYX 0:85b3fd62ea1a 8776 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8777 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
NYX 0:85b3fd62ea1a 8778 #define GPIO_BSRR_BS15_Pos (15U)
NYX 0:85b3fd62ea1a 8779 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8780 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
NYX 0:85b3fd62ea1a 8781 #define GPIO_BSRR_BR0_Pos (16U)
NYX 0:85b3fd62ea1a 8782 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 8783 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
NYX 0:85b3fd62ea1a 8784 #define GPIO_BSRR_BR1_Pos (17U)
NYX 0:85b3fd62ea1a 8785 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 8786 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
NYX 0:85b3fd62ea1a 8787 #define GPIO_BSRR_BR2_Pos (18U)
NYX 0:85b3fd62ea1a 8788 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 8789 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
NYX 0:85b3fd62ea1a 8790 #define GPIO_BSRR_BR3_Pos (19U)
NYX 0:85b3fd62ea1a 8791 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 8792 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
NYX 0:85b3fd62ea1a 8793 #define GPIO_BSRR_BR4_Pos (20U)
NYX 0:85b3fd62ea1a 8794 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 8795 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
NYX 0:85b3fd62ea1a 8796 #define GPIO_BSRR_BR5_Pos (21U)
NYX 0:85b3fd62ea1a 8797 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 8798 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
NYX 0:85b3fd62ea1a 8799 #define GPIO_BSRR_BR6_Pos (22U)
NYX 0:85b3fd62ea1a 8800 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 8801 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
NYX 0:85b3fd62ea1a 8802 #define GPIO_BSRR_BR7_Pos (23U)
NYX 0:85b3fd62ea1a 8803 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 8804 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
NYX 0:85b3fd62ea1a 8805 #define GPIO_BSRR_BR8_Pos (24U)
NYX 0:85b3fd62ea1a 8806 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 8807 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
NYX 0:85b3fd62ea1a 8808 #define GPIO_BSRR_BR9_Pos (25U)
NYX 0:85b3fd62ea1a 8809 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 8810 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
NYX 0:85b3fd62ea1a 8811 #define GPIO_BSRR_BR10_Pos (26U)
NYX 0:85b3fd62ea1a 8812 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 8813 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
NYX 0:85b3fd62ea1a 8814 #define GPIO_BSRR_BR11_Pos (27U)
NYX 0:85b3fd62ea1a 8815 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 8816 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
NYX 0:85b3fd62ea1a 8817 #define GPIO_BSRR_BR12_Pos (28U)
NYX 0:85b3fd62ea1a 8818 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 8819 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
NYX 0:85b3fd62ea1a 8820 #define GPIO_BSRR_BR13_Pos (29U)
NYX 0:85b3fd62ea1a 8821 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 8822 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
NYX 0:85b3fd62ea1a 8823 #define GPIO_BSRR_BR14_Pos (30U)
NYX 0:85b3fd62ea1a 8824 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 8825 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
NYX 0:85b3fd62ea1a 8826 #define GPIO_BSRR_BR15_Pos (31U)
NYX 0:85b3fd62ea1a 8827 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 8828 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
NYX 0:85b3fd62ea1a 8829
NYX 0:85b3fd62ea1a 8830 /* Legacy defines */
NYX 0:85b3fd62ea1a 8831 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
NYX 0:85b3fd62ea1a 8832 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
NYX 0:85b3fd62ea1a 8833 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
NYX 0:85b3fd62ea1a 8834 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
NYX 0:85b3fd62ea1a 8835 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
NYX 0:85b3fd62ea1a 8836 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
NYX 0:85b3fd62ea1a 8837 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
NYX 0:85b3fd62ea1a 8838 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
NYX 0:85b3fd62ea1a 8839 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
NYX 0:85b3fd62ea1a 8840 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
NYX 0:85b3fd62ea1a 8841 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
NYX 0:85b3fd62ea1a 8842 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
NYX 0:85b3fd62ea1a 8843 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
NYX 0:85b3fd62ea1a 8844 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
NYX 0:85b3fd62ea1a 8845 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
NYX 0:85b3fd62ea1a 8846 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
NYX 0:85b3fd62ea1a 8847 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
NYX 0:85b3fd62ea1a 8848 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
NYX 0:85b3fd62ea1a 8849 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
NYX 0:85b3fd62ea1a 8850 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
NYX 0:85b3fd62ea1a 8851 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
NYX 0:85b3fd62ea1a 8852 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
NYX 0:85b3fd62ea1a 8853 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
NYX 0:85b3fd62ea1a 8854 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
NYX 0:85b3fd62ea1a 8855 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
NYX 0:85b3fd62ea1a 8856 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
NYX 0:85b3fd62ea1a 8857 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
NYX 0:85b3fd62ea1a 8858 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
NYX 0:85b3fd62ea1a 8859 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
NYX 0:85b3fd62ea1a 8860 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
NYX 0:85b3fd62ea1a 8861 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
NYX 0:85b3fd62ea1a 8862 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
NYX 0:85b3fd62ea1a 8863 /****************** Bit definition for GPIO_LCKR register *********************/
NYX 0:85b3fd62ea1a 8864 #define GPIO_LCKR_LCK0_Pos (0U)
NYX 0:85b3fd62ea1a 8865 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8866 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
NYX 0:85b3fd62ea1a 8867 #define GPIO_LCKR_LCK1_Pos (1U)
NYX 0:85b3fd62ea1a 8868 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8869 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
NYX 0:85b3fd62ea1a 8870 #define GPIO_LCKR_LCK2_Pos (2U)
NYX 0:85b3fd62ea1a 8871 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8872 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
NYX 0:85b3fd62ea1a 8873 #define GPIO_LCKR_LCK3_Pos (3U)
NYX 0:85b3fd62ea1a 8874 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8875 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
NYX 0:85b3fd62ea1a 8876 #define GPIO_LCKR_LCK4_Pos (4U)
NYX 0:85b3fd62ea1a 8877 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8878 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
NYX 0:85b3fd62ea1a 8879 #define GPIO_LCKR_LCK5_Pos (5U)
NYX 0:85b3fd62ea1a 8880 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8881 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
NYX 0:85b3fd62ea1a 8882 #define GPIO_LCKR_LCK6_Pos (6U)
NYX 0:85b3fd62ea1a 8883 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8884 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
NYX 0:85b3fd62ea1a 8885 #define GPIO_LCKR_LCK7_Pos (7U)
NYX 0:85b3fd62ea1a 8886 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8887 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
NYX 0:85b3fd62ea1a 8888 #define GPIO_LCKR_LCK8_Pos (8U)
NYX 0:85b3fd62ea1a 8889 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8890 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
NYX 0:85b3fd62ea1a 8891 #define GPIO_LCKR_LCK9_Pos (9U)
NYX 0:85b3fd62ea1a 8892 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8893 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
NYX 0:85b3fd62ea1a 8894 #define GPIO_LCKR_LCK10_Pos (10U)
NYX 0:85b3fd62ea1a 8895 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8896 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
NYX 0:85b3fd62ea1a 8897 #define GPIO_LCKR_LCK11_Pos (11U)
NYX 0:85b3fd62ea1a 8898 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8899 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
NYX 0:85b3fd62ea1a 8900 #define GPIO_LCKR_LCK12_Pos (12U)
NYX 0:85b3fd62ea1a 8901 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8902 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
NYX 0:85b3fd62ea1a 8903 #define GPIO_LCKR_LCK13_Pos (13U)
NYX 0:85b3fd62ea1a 8904 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8905 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
NYX 0:85b3fd62ea1a 8906 #define GPIO_LCKR_LCK14_Pos (14U)
NYX 0:85b3fd62ea1a 8907 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8908 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
NYX 0:85b3fd62ea1a 8909 #define GPIO_LCKR_LCK15_Pos (15U)
NYX 0:85b3fd62ea1a 8910 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8911 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
NYX 0:85b3fd62ea1a 8912 #define GPIO_LCKR_LCKK_Pos (16U)
NYX 0:85b3fd62ea1a 8913 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 8914 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
NYX 0:85b3fd62ea1a 8915 /****************** Bit definition for GPIO_AFRL register *********************/
NYX 0:85b3fd62ea1a 8916 #define GPIO_AFRL_AFSEL0_Pos (0U)
NYX 0:85b3fd62ea1a 8917 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 8918 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
NYX 0:85b3fd62ea1a 8919 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 8920 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 8921 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 8922 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 8923 #define GPIO_AFRL_AFSEL1_Pos (4U)
NYX 0:85b3fd62ea1a 8924 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 8925 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
NYX 0:85b3fd62ea1a 8926 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 8927 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 8928 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 8929 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 8930 #define GPIO_AFRL_AFSEL2_Pos (8U)
NYX 0:85b3fd62ea1a 8931 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 8932 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
NYX 0:85b3fd62ea1a 8933 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 8934 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 8935 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 8936 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 8937 #define GPIO_AFRL_AFSEL3_Pos (12U)
NYX 0:85b3fd62ea1a 8938 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 8939 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
NYX 0:85b3fd62ea1a 8940 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 8941 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 8942 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 8943 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 8944 #define GPIO_AFRL_AFSEL4_Pos (16U)
NYX 0:85b3fd62ea1a 8945 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 8946 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
NYX 0:85b3fd62ea1a 8947 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 8948 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 8949 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 8950 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 8951 #define GPIO_AFRL_AFSEL5_Pos (20U)
NYX 0:85b3fd62ea1a 8952 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 8953 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
NYX 0:85b3fd62ea1a 8954 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 8955 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 8956 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 8957 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 8958 #define GPIO_AFRL_AFSEL6_Pos (24U)
NYX 0:85b3fd62ea1a 8959 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 8960 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
NYX 0:85b3fd62ea1a 8961 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 8962 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 8963 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 8964 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 8965 #define GPIO_AFRL_AFSEL7_Pos (28U)
NYX 0:85b3fd62ea1a 8966 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
NYX 0:85b3fd62ea1a 8967 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
NYX 0:85b3fd62ea1a 8968 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 8969 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 8970 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 8971 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 8972
NYX 0:85b3fd62ea1a 8973 /* Legacy defines */
NYX 0:85b3fd62ea1a 8974 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
NYX 0:85b3fd62ea1a 8975 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
NYX 0:85b3fd62ea1a 8976 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
NYX 0:85b3fd62ea1a 8977 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
NYX 0:85b3fd62ea1a 8978 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
NYX 0:85b3fd62ea1a 8979 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
NYX 0:85b3fd62ea1a 8980 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
NYX 0:85b3fd62ea1a 8981 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
NYX 0:85b3fd62ea1a 8982 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
NYX 0:85b3fd62ea1a 8983 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
NYX 0:85b3fd62ea1a 8984 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
NYX 0:85b3fd62ea1a 8985 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
NYX 0:85b3fd62ea1a 8986 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
NYX 0:85b3fd62ea1a 8987 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
NYX 0:85b3fd62ea1a 8988 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
NYX 0:85b3fd62ea1a 8989 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
NYX 0:85b3fd62ea1a 8990 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
NYX 0:85b3fd62ea1a 8991 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
NYX 0:85b3fd62ea1a 8992 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
NYX 0:85b3fd62ea1a 8993 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
NYX 0:85b3fd62ea1a 8994 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
NYX 0:85b3fd62ea1a 8995 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
NYX 0:85b3fd62ea1a 8996 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
NYX 0:85b3fd62ea1a 8997 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
NYX 0:85b3fd62ea1a 8998 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
NYX 0:85b3fd62ea1a 8999 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
NYX 0:85b3fd62ea1a 9000 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
NYX 0:85b3fd62ea1a 9001 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
NYX 0:85b3fd62ea1a 9002 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
NYX 0:85b3fd62ea1a 9003 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
NYX 0:85b3fd62ea1a 9004 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
NYX 0:85b3fd62ea1a 9005 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
NYX 0:85b3fd62ea1a 9006 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
NYX 0:85b3fd62ea1a 9007 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
NYX 0:85b3fd62ea1a 9008 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
NYX 0:85b3fd62ea1a 9009 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
NYX 0:85b3fd62ea1a 9010 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
NYX 0:85b3fd62ea1a 9011 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
NYX 0:85b3fd62ea1a 9012 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
NYX 0:85b3fd62ea1a 9013 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
NYX 0:85b3fd62ea1a 9014
NYX 0:85b3fd62ea1a 9015 /****************** Bit definition for GPIO_AFRH register *********************/
NYX 0:85b3fd62ea1a 9016 #define GPIO_AFRH_AFSEL8_Pos (0U)
NYX 0:85b3fd62ea1a 9017 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 9018 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
NYX 0:85b3fd62ea1a 9019 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9020 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9021 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9022 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9023 #define GPIO_AFRH_AFSEL9_Pos (4U)
NYX 0:85b3fd62ea1a 9024 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 9025 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
NYX 0:85b3fd62ea1a 9026 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9027 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9028 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9029 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9030 #define GPIO_AFRH_AFSEL10_Pos (8U)
NYX 0:85b3fd62ea1a 9031 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 9032 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
NYX 0:85b3fd62ea1a 9033 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9034 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9035 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9036 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9037 #define GPIO_AFRH_AFSEL11_Pos (12U)
NYX 0:85b3fd62ea1a 9038 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 9039 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
NYX 0:85b3fd62ea1a 9040 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9041 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 9042 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 9043 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9044 #define GPIO_AFRH_AFSEL12_Pos (16U)
NYX 0:85b3fd62ea1a 9045 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 9046 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
NYX 0:85b3fd62ea1a 9047 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 9048 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 9049 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 9050 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 9051 #define GPIO_AFRH_AFSEL13_Pos (20U)
NYX 0:85b3fd62ea1a 9052 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 9053 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
NYX 0:85b3fd62ea1a 9054 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 9055 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 9056 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 9057 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 9058 #define GPIO_AFRH_AFSEL14_Pos (24U)
NYX 0:85b3fd62ea1a 9059 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 9060 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
NYX 0:85b3fd62ea1a 9061 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 9062 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 9063 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 9064 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 9065 #define GPIO_AFRH_AFSEL15_Pos (28U)
NYX 0:85b3fd62ea1a 9066 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
NYX 0:85b3fd62ea1a 9067 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
NYX 0:85b3fd62ea1a 9068 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 9069 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 9070 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 9071 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 9072
NYX 0:85b3fd62ea1a 9073 /* Legacy defines */
NYX 0:85b3fd62ea1a 9074 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
NYX 0:85b3fd62ea1a 9075 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
NYX 0:85b3fd62ea1a 9076 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
NYX 0:85b3fd62ea1a 9077 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
NYX 0:85b3fd62ea1a 9078 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
NYX 0:85b3fd62ea1a 9079 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
NYX 0:85b3fd62ea1a 9080 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
NYX 0:85b3fd62ea1a 9081 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
NYX 0:85b3fd62ea1a 9082 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
NYX 0:85b3fd62ea1a 9083 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
NYX 0:85b3fd62ea1a 9084 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
NYX 0:85b3fd62ea1a 9085 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
NYX 0:85b3fd62ea1a 9086 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
NYX 0:85b3fd62ea1a 9087 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
NYX 0:85b3fd62ea1a 9088 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
NYX 0:85b3fd62ea1a 9089 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
NYX 0:85b3fd62ea1a 9090 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
NYX 0:85b3fd62ea1a 9091 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
NYX 0:85b3fd62ea1a 9092 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
NYX 0:85b3fd62ea1a 9093 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
NYX 0:85b3fd62ea1a 9094 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
NYX 0:85b3fd62ea1a 9095 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
NYX 0:85b3fd62ea1a 9096 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
NYX 0:85b3fd62ea1a 9097 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
NYX 0:85b3fd62ea1a 9098 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
NYX 0:85b3fd62ea1a 9099 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
NYX 0:85b3fd62ea1a 9100 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
NYX 0:85b3fd62ea1a 9101 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
NYX 0:85b3fd62ea1a 9102 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
NYX 0:85b3fd62ea1a 9103 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
NYX 0:85b3fd62ea1a 9104 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
NYX 0:85b3fd62ea1a 9105 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
NYX 0:85b3fd62ea1a 9106 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
NYX 0:85b3fd62ea1a 9107 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
NYX 0:85b3fd62ea1a 9108 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
NYX 0:85b3fd62ea1a 9109 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
NYX 0:85b3fd62ea1a 9110 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
NYX 0:85b3fd62ea1a 9111 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
NYX 0:85b3fd62ea1a 9112 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
NYX 0:85b3fd62ea1a 9113 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
NYX 0:85b3fd62ea1a 9114
NYX 0:85b3fd62ea1a 9115 /****************** Bits definition for GPIO_BRR register ******************/
NYX 0:85b3fd62ea1a 9116 #define GPIO_BRR_BR0_Pos (0U)
NYX 0:85b3fd62ea1a 9117 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9118 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
NYX 0:85b3fd62ea1a 9119 #define GPIO_BRR_BR1_Pos (1U)
NYX 0:85b3fd62ea1a 9120 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9121 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
NYX 0:85b3fd62ea1a 9122 #define GPIO_BRR_BR2_Pos (2U)
NYX 0:85b3fd62ea1a 9123 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9124 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
NYX 0:85b3fd62ea1a 9125 #define GPIO_BRR_BR3_Pos (3U)
NYX 0:85b3fd62ea1a 9126 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9127 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
NYX 0:85b3fd62ea1a 9128 #define GPIO_BRR_BR4_Pos (4U)
NYX 0:85b3fd62ea1a 9129 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9130 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
NYX 0:85b3fd62ea1a 9131 #define GPIO_BRR_BR5_Pos (5U)
NYX 0:85b3fd62ea1a 9132 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9133 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
NYX 0:85b3fd62ea1a 9134 #define GPIO_BRR_BR6_Pos (6U)
NYX 0:85b3fd62ea1a 9135 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9136 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
NYX 0:85b3fd62ea1a 9137 #define GPIO_BRR_BR7_Pos (7U)
NYX 0:85b3fd62ea1a 9138 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9139 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
NYX 0:85b3fd62ea1a 9140 #define GPIO_BRR_BR8_Pos (8U)
NYX 0:85b3fd62ea1a 9141 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9142 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
NYX 0:85b3fd62ea1a 9143 #define GPIO_BRR_BR9_Pos (9U)
NYX 0:85b3fd62ea1a 9144 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9145 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
NYX 0:85b3fd62ea1a 9146 #define GPIO_BRR_BR10_Pos (10U)
NYX 0:85b3fd62ea1a 9147 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9148 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
NYX 0:85b3fd62ea1a 9149 #define GPIO_BRR_BR11_Pos (11U)
NYX 0:85b3fd62ea1a 9150 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9151 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
NYX 0:85b3fd62ea1a 9152 #define GPIO_BRR_BR12_Pos (12U)
NYX 0:85b3fd62ea1a 9153 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9154 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
NYX 0:85b3fd62ea1a 9155 #define GPIO_BRR_BR13_Pos (13U)
NYX 0:85b3fd62ea1a 9156 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 9157 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
NYX 0:85b3fd62ea1a 9158 #define GPIO_BRR_BR14_Pos (14U)
NYX 0:85b3fd62ea1a 9159 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 9160 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
NYX 0:85b3fd62ea1a 9161 #define GPIO_BRR_BR15_Pos (15U)
NYX 0:85b3fd62ea1a 9162 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9163 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
NYX 0:85b3fd62ea1a 9164
NYX 0:85b3fd62ea1a 9165
NYX 0:85b3fd62ea1a 9166 /******************************************************************************/
NYX 0:85b3fd62ea1a 9167 /* */
NYX 0:85b3fd62ea1a 9168 /* Inter-integrated Circuit Interface */
NYX 0:85b3fd62ea1a 9169 /* */
NYX 0:85b3fd62ea1a 9170 /******************************************************************************/
NYX 0:85b3fd62ea1a 9171 /******************* Bit definition for I2C_CR1 register ********************/
NYX 0:85b3fd62ea1a 9172 #define I2C_CR1_PE_Pos (0U)
NYX 0:85b3fd62ea1a 9173 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9174 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
NYX 0:85b3fd62ea1a 9175 #define I2C_CR1_SMBUS_Pos (1U)
NYX 0:85b3fd62ea1a 9176 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9177 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
NYX 0:85b3fd62ea1a 9178 #define I2C_CR1_SMBTYPE_Pos (3U)
NYX 0:85b3fd62ea1a 9179 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9180 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
NYX 0:85b3fd62ea1a 9181 #define I2C_CR1_ENARP_Pos (4U)
NYX 0:85b3fd62ea1a 9182 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9183 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
NYX 0:85b3fd62ea1a 9184 #define I2C_CR1_ENPEC_Pos (5U)
NYX 0:85b3fd62ea1a 9185 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9186 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
NYX 0:85b3fd62ea1a 9187 #define I2C_CR1_ENGC_Pos (6U)
NYX 0:85b3fd62ea1a 9188 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9189 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
NYX 0:85b3fd62ea1a 9190 #define I2C_CR1_NOSTRETCH_Pos (7U)
NYX 0:85b3fd62ea1a 9191 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9192 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
NYX 0:85b3fd62ea1a 9193 #define I2C_CR1_START_Pos (8U)
NYX 0:85b3fd62ea1a 9194 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9195 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
NYX 0:85b3fd62ea1a 9196 #define I2C_CR1_STOP_Pos (9U)
NYX 0:85b3fd62ea1a 9197 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9198 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
NYX 0:85b3fd62ea1a 9199 #define I2C_CR1_ACK_Pos (10U)
NYX 0:85b3fd62ea1a 9200 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9201 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
NYX 0:85b3fd62ea1a 9202 #define I2C_CR1_POS_Pos (11U)
NYX 0:85b3fd62ea1a 9203 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9204 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
NYX 0:85b3fd62ea1a 9205 #define I2C_CR1_PEC_Pos (12U)
NYX 0:85b3fd62ea1a 9206 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9207 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
NYX 0:85b3fd62ea1a 9208 #define I2C_CR1_ALERT_Pos (13U)
NYX 0:85b3fd62ea1a 9209 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 9210 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
NYX 0:85b3fd62ea1a 9211 #define I2C_CR1_SWRST_Pos (15U)
NYX 0:85b3fd62ea1a 9212 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9213 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
NYX 0:85b3fd62ea1a 9214
NYX 0:85b3fd62ea1a 9215 /******************* Bit definition for I2C_CR2 register ********************/
NYX 0:85b3fd62ea1a 9216 #define I2C_CR2_FREQ_Pos (0U)
NYX 0:85b3fd62ea1a 9217 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
NYX 0:85b3fd62ea1a 9218 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
NYX 0:85b3fd62ea1a 9219 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9220 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9221 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9222 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9223 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9224 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9225
NYX 0:85b3fd62ea1a 9226 #define I2C_CR2_ITERREN_Pos (8U)
NYX 0:85b3fd62ea1a 9227 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9228 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
NYX 0:85b3fd62ea1a 9229 #define I2C_CR2_ITEVTEN_Pos (9U)
NYX 0:85b3fd62ea1a 9230 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9231 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
NYX 0:85b3fd62ea1a 9232 #define I2C_CR2_ITBUFEN_Pos (10U)
NYX 0:85b3fd62ea1a 9233 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9234 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
NYX 0:85b3fd62ea1a 9235 #define I2C_CR2_DMAEN_Pos (11U)
NYX 0:85b3fd62ea1a 9236 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9237 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
NYX 0:85b3fd62ea1a 9238 #define I2C_CR2_LAST_Pos (12U)
NYX 0:85b3fd62ea1a 9239 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9240 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
NYX 0:85b3fd62ea1a 9241
NYX 0:85b3fd62ea1a 9242 /******************* Bit definition for I2C_OAR1 register *******************/
NYX 0:85b3fd62ea1a 9243 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
NYX 0:85b3fd62ea1a 9244 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
NYX 0:85b3fd62ea1a 9245
NYX 0:85b3fd62ea1a 9246 #define I2C_OAR1_ADD0_Pos (0U)
NYX 0:85b3fd62ea1a 9247 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9248 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
NYX 0:85b3fd62ea1a 9249 #define I2C_OAR1_ADD1_Pos (1U)
NYX 0:85b3fd62ea1a 9250 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9251 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
NYX 0:85b3fd62ea1a 9252 #define I2C_OAR1_ADD2_Pos (2U)
NYX 0:85b3fd62ea1a 9253 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9254 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
NYX 0:85b3fd62ea1a 9255 #define I2C_OAR1_ADD3_Pos (3U)
NYX 0:85b3fd62ea1a 9256 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9257 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
NYX 0:85b3fd62ea1a 9258 #define I2C_OAR1_ADD4_Pos (4U)
NYX 0:85b3fd62ea1a 9259 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9260 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
NYX 0:85b3fd62ea1a 9261 #define I2C_OAR1_ADD5_Pos (5U)
NYX 0:85b3fd62ea1a 9262 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9263 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
NYX 0:85b3fd62ea1a 9264 #define I2C_OAR1_ADD6_Pos (6U)
NYX 0:85b3fd62ea1a 9265 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9266 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
NYX 0:85b3fd62ea1a 9267 #define I2C_OAR1_ADD7_Pos (7U)
NYX 0:85b3fd62ea1a 9268 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9269 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
NYX 0:85b3fd62ea1a 9270 #define I2C_OAR1_ADD8_Pos (8U)
NYX 0:85b3fd62ea1a 9271 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9272 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
NYX 0:85b3fd62ea1a 9273 #define I2C_OAR1_ADD9_Pos (9U)
NYX 0:85b3fd62ea1a 9274 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9275 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
NYX 0:85b3fd62ea1a 9276
NYX 0:85b3fd62ea1a 9277 #define I2C_OAR1_ADDMODE_Pos (15U)
NYX 0:85b3fd62ea1a 9278 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9279 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
NYX 0:85b3fd62ea1a 9280
NYX 0:85b3fd62ea1a 9281 /******************* Bit definition for I2C_OAR2 register *******************/
NYX 0:85b3fd62ea1a 9282 #define I2C_OAR2_ENDUAL_Pos (0U)
NYX 0:85b3fd62ea1a 9283 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9284 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
NYX 0:85b3fd62ea1a 9285 #define I2C_OAR2_ADD2_Pos (1U)
NYX 0:85b3fd62ea1a 9286 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
NYX 0:85b3fd62ea1a 9287 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
NYX 0:85b3fd62ea1a 9288
NYX 0:85b3fd62ea1a 9289 /******************** Bit definition for I2C_DR register ********************/
NYX 0:85b3fd62ea1a 9290 #define I2C_DR_DR_Pos (0U)
NYX 0:85b3fd62ea1a 9291 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 9292 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
NYX 0:85b3fd62ea1a 9293
NYX 0:85b3fd62ea1a 9294 /******************* Bit definition for I2C_SR1 register ********************/
NYX 0:85b3fd62ea1a 9295 #define I2C_SR1_SB_Pos (0U)
NYX 0:85b3fd62ea1a 9296 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9297 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
NYX 0:85b3fd62ea1a 9298 #define I2C_SR1_ADDR_Pos (1U)
NYX 0:85b3fd62ea1a 9299 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9300 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
NYX 0:85b3fd62ea1a 9301 #define I2C_SR1_BTF_Pos (2U)
NYX 0:85b3fd62ea1a 9302 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9303 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
NYX 0:85b3fd62ea1a 9304 #define I2C_SR1_ADD10_Pos (3U)
NYX 0:85b3fd62ea1a 9305 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9306 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
NYX 0:85b3fd62ea1a 9307 #define I2C_SR1_STOPF_Pos (4U)
NYX 0:85b3fd62ea1a 9308 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9309 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
NYX 0:85b3fd62ea1a 9310 #define I2C_SR1_RXNE_Pos (6U)
NYX 0:85b3fd62ea1a 9311 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9312 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
NYX 0:85b3fd62ea1a 9313 #define I2C_SR1_TXE_Pos (7U)
NYX 0:85b3fd62ea1a 9314 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9315 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
NYX 0:85b3fd62ea1a 9316 #define I2C_SR1_BERR_Pos (8U)
NYX 0:85b3fd62ea1a 9317 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9318 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
NYX 0:85b3fd62ea1a 9319 #define I2C_SR1_ARLO_Pos (9U)
NYX 0:85b3fd62ea1a 9320 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9321 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
NYX 0:85b3fd62ea1a 9322 #define I2C_SR1_AF_Pos (10U)
NYX 0:85b3fd62ea1a 9323 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9324 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
NYX 0:85b3fd62ea1a 9325 #define I2C_SR1_OVR_Pos (11U)
NYX 0:85b3fd62ea1a 9326 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9327 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
NYX 0:85b3fd62ea1a 9328 #define I2C_SR1_PECERR_Pos (12U)
NYX 0:85b3fd62ea1a 9329 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9330 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
NYX 0:85b3fd62ea1a 9331 #define I2C_SR1_TIMEOUT_Pos (14U)
NYX 0:85b3fd62ea1a 9332 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 9333 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
NYX 0:85b3fd62ea1a 9334 #define I2C_SR1_SMBALERT_Pos (15U)
NYX 0:85b3fd62ea1a 9335 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9336 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
NYX 0:85b3fd62ea1a 9337
NYX 0:85b3fd62ea1a 9338 /******************* Bit definition for I2C_SR2 register ********************/
NYX 0:85b3fd62ea1a 9339 #define I2C_SR2_MSL_Pos (0U)
NYX 0:85b3fd62ea1a 9340 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9341 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
NYX 0:85b3fd62ea1a 9342 #define I2C_SR2_BUSY_Pos (1U)
NYX 0:85b3fd62ea1a 9343 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9344 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
NYX 0:85b3fd62ea1a 9345 #define I2C_SR2_TRA_Pos (2U)
NYX 0:85b3fd62ea1a 9346 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9347 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
NYX 0:85b3fd62ea1a 9348 #define I2C_SR2_GENCALL_Pos (4U)
NYX 0:85b3fd62ea1a 9349 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9350 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
NYX 0:85b3fd62ea1a 9351 #define I2C_SR2_SMBDEFAULT_Pos (5U)
NYX 0:85b3fd62ea1a 9352 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9353 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
NYX 0:85b3fd62ea1a 9354 #define I2C_SR2_SMBHOST_Pos (6U)
NYX 0:85b3fd62ea1a 9355 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9356 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
NYX 0:85b3fd62ea1a 9357 #define I2C_SR2_DUALF_Pos (7U)
NYX 0:85b3fd62ea1a 9358 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9359 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
NYX 0:85b3fd62ea1a 9360 #define I2C_SR2_PEC_Pos (8U)
NYX 0:85b3fd62ea1a 9361 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 9362 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
NYX 0:85b3fd62ea1a 9363
NYX 0:85b3fd62ea1a 9364 /******************* Bit definition for I2C_CCR register ********************/
NYX 0:85b3fd62ea1a 9365 #define I2C_CCR_CCR_Pos (0U)
NYX 0:85b3fd62ea1a 9366 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 9367 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
NYX 0:85b3fd62ea1a 9368 #define I2C_CCR_DUTY_Pos (14U)
NYX 0:85b3fd62ea1a 9369 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 9370 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
NYX 0:85b3fd62ea1a 9371 #define I2C_CCR_FS_Pos (15U)
NYX 0:85b3fd62ea1a 9372 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9373 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
NYX 0:85b3fd62ea1a 9374
NYX 0:85b3fd62ea1a 9375 /****************** Bit definition for I2C_TRISE register *******************/
NYX 0:85b3fd62ea1a 9376 #define I2C_TRISE_TRISE_Pos (0U)
NYX 0:85b3fd62ea1a 9377 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
NYX 0:85b3fd62ea1a 9378 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
NYX 0:85b3fd62ea1a 9379
NYX 0:85b3fd62ea1a 9380 /****************** Bit definition for I2C_FLTR register *******************/
NYX 0:85b3fd62ea1a 9381 #define I2C_FLTR_DNF_Pos (0U)
NYX 0:85b3fd62ea1a 9382 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 9383 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
NYX 0:85b3fd62ea1a 9384 #define I2C_FLTR_ANOFF_Pos (4U)
NYX 0:85b3fd62ea1a 9385 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9386 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
NYX 0:85b3fd62ea1a 9387
NYX 0:85b3fd62ea1a 9388 /******************************************************************************/
NYX 0:85b3fd62ea1a 9389 /* */
NYX 0:85b3fd62ea1a 9390 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
NYX 0:85b3fd62ea1a 9391 /* */
NYX 0:85b3fd62ea1a 9392 /******************************************************************************/
NYX 0:85b3fd62ea1a 9393 /******************* Bit definition for I2C_CR1 register *******************/
NYX 0:85b3fd62ea1a 9394 #define FMPI2C_CR1_PE_Pos (0U)
NYX 0:85b3fd62ea1a 9395 #define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9396 #define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
NYX 0:85b3fd62ea1a 9397 #define FMPI2C_CR1_TXIE_Pos (1U)
NYX 0:85b3fd62ea1a 9398 #define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9399 #define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
NYX 0:85b3fd62ea1a 9400 #define FMPI2C_CR1_RXIE_Pos (2U)
NYX 0:85b3fd62ea1a 9401 #define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9402 #define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
NYX 0:85b3fd62ea1a 9403 #define FMPI2C_CR1_ADDRIE_Pos (3U)
NYX 0:85b3fd62ea1a 9404 #define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9405 #define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
NYX 0:85b3fd62ea1a 9406 #define FMPI2C_CR1_NACKIE_Pos (4U)
NYX 0:85b3fd62ea1a 9407 #define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9408 #define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
NYX 0:85b3fd62ea1a 9409 #define FMPI2C_CR1_STOPIE_Pos (5U)
NYX 0:85b3fd62ea1a 9410 #define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9411 #define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
NYX 0:85b3fd62ea1a 9412 #define FMPI2C_CR1_TCIE_Pos (6U)
NYX 0:85b3fd62ea1a 9413 #define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9414 #define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
NYX 0:85b3fd62ea1a 9415 #define FMPI2C_CR1_ERRIE_Pos (7U)
NYX 0:85b3fd62ea1a 9416 #define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9417 #define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
NYX 0:85b3fd62ea1a 9418 #define FMPI2C_CR1_DFN_Pos (8U)
NYX 0:85b3fd62ea1a 9419 #define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 9420 #define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
NYX 0:85b3fd62ea1a 9421 #define FMPI2C_CR1_ANFOFF_Pos (12U)
NYX 0:85b3fd62ea1a 9422 #define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9423 #define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
NYX 0:85b3fd62ea1a 9424 #define FMPI2C_CR1_TXDMAEN_Pos (14U)
NYX 0:85b3fd62ea1a 9425 #define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 9426 #define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
NYX 0:85b3fd62ea1a 9427 #define FMPI2C_CR1_RXDMAEN_Pos (15U)
NYX 0:85b3fd62ea1a 9428 #define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9429 #define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
NYX 0:85b3fd62ea1a 9430 #define FMPI2C_CR1_SBC_Pos (16U)
NYX 0:85b3fd62ea1a 9431 #define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 9432 #define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
NYX 0:85b3fd62ea1a 9433 #define FMPI2C_CR1_NOSTRETCH_Pos (17U)
NYX 0:85b3fd62ea1a 9434 #define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 9435 #define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
NYX 0:85b3fd62ea1a 9436 #define FMPI2C_CR1_GCEN_Pos (19U)
NYX 0:85b3fd62ea1a 9437 #define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 9438 #define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
NYX 0:85b3fd62ea1a 9439 #define FMPI2C_CR1_SMBHEN_Pos (20U)
NYX 0:85b3fd62ea1a 9440 #define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 9441 #define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
NYX 0:85b3fd62ea1a 9442 #define FMPI2C_CR1_SMBDEN_Pos (21U)
NYX 0:85b3fd62ea1a 9443 #define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 9444 #define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
NYX 0:85b3fd62ea1a 9445 #define FMPI2C_CR1_ALERTEN_Pos (22U)
NYX 0:85b3fd62ea1a 9446 #define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 9447 #define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
NYX 0:85b3fd62ea1a 9448 #define FMPI2C_CR1_PECEN_Pos (23U)
NYX 0:85b3fd62ea1a 9449 #define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 9450 #define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
NYX 0:85b3fd62ea1a 9451
NYX 0:85b3fd62ea1a 9452 /****************** Bit definition for I2C_CR2 register ********************/
NYX 0:85b3fd62ea1a 9453 #define FMPI2C_CR2_SADD_Pos (0U)
NYX 0:85b3fd62ea1a 9454 #define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
NYX 0:85b3fd62ea1a 9455 #define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
NYX 0:85b3fd62ea1a 9456 #define FMPI2C_CR2_RD_WRN_Pos (10U)
NYX 0:85b3fd62ea1a 9457 #define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9458 #define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
NYX 0:85b3fd62ea1a 9459 #define FMPI2C_CR2_ADD10_Pos (11U)
NYX 0:85b3fd62ea1a 9460 #define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9461 #define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
NYX 0:85b3fd62ea1a 9462 #define FMPI2C_CR2_HEAD10R_Pos (12U)
NYX 0:85b3fd62ea1a 9463 #define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9464 #define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
NYX 0:85b3fd62ea1a 9465 #define FMPI2C_CR2_START_Pos (13U)
NYX 0:85b3fd62ea1a 9466 #define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 9467 #define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
NYX 0:85b3fd62ea1a 9468 #define FMPI2C_CR2_STOP_Pos (14U)
NYX 0:85b3fd62ea1a 9469 #define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 9470 #define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
NYX 0:85b3fd62ea1a 9471 #define FMPI2C_CR2_NACK_Pos (15U)
NYX 0:85b3fd62ea1a 9472 #define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9473 #define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
NYX 0:85b3fd62ea1a 9474 #define FMPI2C_CR2_NBYTES_Pos (16U)
NYX 0:85b3fd62ea1a 9475 #define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 9476 #define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
NYX 0:85b3fd62ea1a 9477 #define FMPI2C_CR2_RELOAD_Pos (24U)
NYX 0:85b3fd62ea1a 9478 #define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 9479 #define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
NYX 0:85b3fd62ea1a 9480 #define FMPI2C_CR2_AUTOEND_Pos (25U)
NYX 0:85b3fd62ea1a 9481 #define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 9482 #define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
NYX 0:85b3fd62ea1a 9483 #define FMPI2C_CR2_PECBYTE_Pos (26U)
NYX 0:85b3fd62ea1a 9484 #define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 9485 #define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
NYX 0:85b3fd62ea1a 9486
NYX 0:85b3fd62ea1a 9487 /******************* Bit definition for I2C_OAR1 register ******************/
NYX 0:85b3fd62ea1a 9488 #define FMPI2C_OAR1_OA1_Pos (0U)
NYX 0:85b3fd62ea1a 9489 #define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
NYX 0:85b3fd62ea1a 9490 #define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
NYX 0:85b3fd62ea1a 9491 #define FMPI2C_OAR1_OA1MODE_Pos (10U)
NYX 0:85b3fd62ea1a 9492 #define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9493 #define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
NYX 0:85b3fd62ea1a 9494 #define FMPI2C_OAR1_OA1EN_Pos (15U)
NYX 0:85b3fd62ea1a 9495 #define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9496 #define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
NYX 0:85b3fd62ea1a 9497
NYX 0:85b3fd62ea1a 9498 /******************* Bit definition for I2C_OAR2 register ******************/
NYX 0:85b3fd62ea1a 9499 #define FMPI2C_OAR2_OA2_Pos (1U)
NYX 0:85b3fd62ea1a 9500 #define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
NYX 0:85b3fd62ea1a 9501 #define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
NYX 0:85b3fd62ea1a 9502 #define FMPI2C_OAR2_OA2MSK_Pos (8U)
NYX 0:85b3fd62ea1a 9503 #define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
NYX 0:85b3fd62ea1a 9504 #define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
NYX 0:85b3fd62ea1a 9505 #define FMPI2C_OAR2_OA2EN_Pos (15U)
NYX 0:85b3fd62ea1a 9506 #define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9507 #define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
NYX 0:85b3fd62ea1a 9508
NYX 0:85b3fd62ea1a 9509 /******************* Bit definition for I2C_TIMINGR register *******************/
NYX 0:85b3fd62ea1a 9510 #define FMPI2C_TIMINGR_SCLL_Pos (0U)
NYX 0:85b3fd62ea1a 9511 #define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 9512 #define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
NYX 0:85b3fd62ea1a 9513 #define FMPI2C_TIMINGR_SCLH_Pos (8U)
NYX 0:85b3fd62ea1a 9514 #define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 9515 #define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
NYX 0:85b3fd62ea1a 9516 #define FMPI2C_TIMINGR_SDADEL_Pos (16U)
NYX 0:85b3fd62ea1a 9517 #define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 9518 #define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
NYX 0:85b3fd62ea1a 9519 #define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
NYX 0:85b3fd62ea1a 9520 #define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 9521 #define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
NYX 0:85b3fd62ea1a 9522 #define FMPI2C_TIMINGR_PRESC_Pos (28U)
NYX 0:85b3fd62ea1a 9523 #define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
NYX 0:85b3fd62ea1a 9524 #define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
NYX 0:85b3fd62ea1a 9525
NYX 0:85b3fd62ea1a 9526 /******************* Bit definition for I2C_TIMEOUTR register *******************/
NYX 0:85b3fd62ea1a 9527 #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
NYX 0:85b3fd62ea1a 9528 #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 9529 #define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
NYX 0:85b3fd62ea1a 9530 #define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
NYX 0:85b3fd62ea1a 9531 #define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9532 #define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
NYX 0:85b3fd62ea1a 9533 #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
NYX 0:85b3fd62ea1a 9534 #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9535 #define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
NYX 0:85b3fd62ea1a 9536 #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
NYX 0:85b3fd62ea1a 9537 #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
NYX 0:85b3fd62ea1a 9538 #define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
NYX 0:85b3fd62ea1a 9539 #define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
NYX 0:85b3fd62ea1a 9540 #define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 9541 #define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
NYX 0:85b3fd62ea1a 9542
NYX 0:85b3fd62ea1a 9543 /****************** Bit definition for I2C_ISR register *********************/
NYX 0:85b3fd62ea1a 9544 #define FMPI2C_ISR_TXE_Pos (0U)
NYX 0:85b3fd62ea1a 9545 #define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9546 #define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
NYX 0:85b3fd62ea1a 9547 #define FMPI2C_ISR_TXIS_Pos (1U)
NYX 0:85b3fd62ea1a 9548 #define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9549 #define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
NYX 0:85b3fd62ea1a 9550 #define FMPI2C_ISR_RXNE_Pos (2U)
NYX 0:85b3fd62ea1a 9551 #define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9552 #define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
NYX 0:85b3fd62ea1a 9553 #define FMPI2C_ISR_ADDR_Pos (3U)
NYX 0:85b3fd62ea1a 9554 #define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9555 #define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
NYX 0:85b3fd62ea1a 9556 #define FMPI2C_ISR_NACKF_Pos (4U)
NYX 0:85b3fd62ea1a 9557 #define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9558 #define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
NYX 0:85b3fd62ea1a 9559 #define FMPI2C_ISR_STOPF_Pos (5U)
NYX 0:85b3fd62ea1a 9560 #define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9561 #define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
NYX 0:85b3fd62ea1a 9562 #define FMPI2C_ISR_TC_Pos (6U)
NYX 0:85b3fd62ea1a 9563 #define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9564 #define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
NYX 0:85b3fd62ea1a 9565 #define FMPI2C_ISR_TCR_Pos (7U)
NYX 0:85b3fd62ea1a 9566 #define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9567 #define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
NYX 0:85b3fd62ea1a 9568 #define FMPI2C_ISR_BERR_Pos (8U)
NYX 0:85b3fd62ea1a 9569 #define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9570 #define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
NYX 0:85b3fd62ea1a 9571 #define FMPI2C_ISR_ARLO_Pos (9U)
NYX 0:85b3fd62ea1a 9572 #define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9573 #define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
NYX 0:85b3fd62ea1a 9574 #define FMPI2C_ISR_OVR_Pos (10U)
NYX 0:85b3fd62ea1a 9575 #define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9576 #define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
NYX 0:85b3fd62ea1a 9577 #define FMPI2C_ISR_PECERR_Pos (11U)
NYX 0:85b3fd62ea1a 9578 #define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9579 #define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
NYX 0:85b3fd62ea1a 9580 #define FMPI2C_ISR_TIMEOUT_Pos (12U)
NYX 0:85b3fd62ea1a 9581 #define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9582 #define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
NYX 0:85b3fd62ea1a 9583 #define FMPI2C_ISR_ALERT_Pos (13U)
NYX 0:85b3fd62ea1a 9584 #define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 9585 #define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
NYX 0:85b3fd62ea1a 9586 #define FMPI2C_ISR_BUSY_Pos (15U)
NYX 0:85b3fd62ea1a 9587 #define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9588 #define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
NYX 0:85b3fd62ea1a 9589 #define FMPI2C_ISR_DIR_Pos (16U)
NYX 0:85b3fd62ea1a 9590 #define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 9591 #define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
NYX 0:85b3fd62ea1a 9592 #define FMPI2C_ISR_ADDCODE_Pos (17U)
NYX 0:85b3fd62ea1a 9593 #define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
NYX 0:85b3fd62ea1a 9594 #define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
NYX 0:85b3fd62ea1a 9595
NYX 0:85b3fd62ea1a 9596 /****************** Bit definition for I2C_ICR register *********************/
NYX 0:85b3fd62ea1a 9597 #define FMPI2C_ICR_ADDRCF_Pos (3U)
NYX 0:85b3fd62ea1a 9598 #define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9599 #define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
NYX 0:85b3fd62ea1a 9600 #define FMPI2C_ICR_NACKCF_Pos (4U)
NYX 0:85b3fd62ea1a 9601 #define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9602 #define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
NYX 0:85b3fd62ea1a 9603 #define FMPI2C_ICR_STOPCF_Pos (5U)
NYX 0:85b3fd62ea1a 9604 #define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9605 #define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
NYX 0:85b3fd62ea1a 9606 #define FMPI2C_ICR_BERRCF_Pos (8U)
NYX 0:85b3fd62ea1a 9607 #define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9608 #define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
NYX 0:85b3fd62ea1a 9609 #define FMPI2C_ICR_ARLOCF_Pos (9U)
NYX 0:85b3fd62ea1a 9610 #define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9611 #define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
NYX 0:85b3fd62ea1a 9612 #define FMPI2C_ICR_OVRCF_Pos (10U)
NYX 0:85b3fd62ea1a 9613 #define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9614 #define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
NYX 0:85b3fd62ea1a 9615 #define FMPI2C_ICR_PECCF_Pos (11U)
NYX 0:85b3fd62ea1a 9616 #define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9617 #define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
NYX 0:85b3fd62ea1a 9618 #define FMPI2C_ICR_TIMOUTCF_Pos (12U)
NYX 0:85b3fd62ea1a 9619 #define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9620 #define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
NYX 0:85b3fd62ea1a 9621 #define FMPI2C_ICR_ALERTCF_Pos (13U)
NYX 0:85b3fd62ea1a 9622 #define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 9623 #define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
NYX 0:85b3fd62ea1a 9624
NYX 0:85b3fd62ea1a 9625 /****************** Bit definition for I2C_PECR register *********************/
NYX 0:85b3fd62ea1a 9626 #define FMPI2C_PECR_PEC_Pos (0U)
NYX 0:85b3fd62ea1a 9627 #define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 9628 #define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
NYX 0:85b3fd62ea1a 9629
NYX 0:85b3fd62ea1a 9630 /****************** Bit definition for I2C_RXDR register *********************/
NYX 0:85b3fd62ea1a 9631 #define FMPI2C_RXDR_RXDATA_Pos (0U)
NYX 0:85b3fd62ea1a 9632 #define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 9633 #define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
NYX 0:85b3fd62ea1a 9634
NYX 0:85b3fd62ea1a 9635 /****************** Bit definition for I2C_TXDR register *********************/
NYX 0:85b3fd62ea1a 9636 #define FMPI2C_TXDR_TXDATA_Pos (0U)
NYX 0:85b3fd62ea1a 9637 #define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 9638 #define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
NYX 0:85b3fd62ea1a 9639
NYX 0:85b3fd62ea1a 9640
NYX 0:85b3fd62ea1a 9641
NYX 0:85b3fd62ea1a 9642 /******************************************************************************/
NYX 0:85b3fd62ea1a 9643 /* */
NYX 0:85b3fd62ea1a 9644 /* Independent WATCHDOG */
NYX 0:85b3fd62ea1a 9645 /* */
NYX 0:85b3fd62ea1a 9646 /******************************************************************************/
NYX 0:85b3fd62ea1a 9647 /******************* Bit definition for IWDG_KR register ********************/
NYX 0:85b3fd62ea1a 9648 #define IWDG_KR_KEY_Pos (0U)
NYX 0:85b3fd62ea1a 9649 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 9650 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
NYX 0:85b3fd62ea1a 9651
NYX 0:85b3fd62ea1a 9652 /******************* Bit definition for IWDG_PR register ********************/
NYX 0:85b3fd62ea1a 9653 #define IWDG_PR_PR_Pos (0U)
NYX 0:85b3fd62ea1a 9654 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 9655 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
NYX 0:85b3fd62ea1a 9656 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
NYX 0:85b3fd62ea1a 9657 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
NYX 0:85b3fd62ea1a 9658 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
NYX 0:85b3fd62ea1a 9659
NYX 0:85b3fd62ea1a 9660 /******************* Bit definition for IWDG_RLR register *******************/
NYX 0:85b3fd62ea1a 9661 #define IWDG_RLR_RL_Pos (0U)
NYX 0:85b3fd62ea1a 9662 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 9663 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
NYX 0:85b3fd62ea1a 9664
NYX 0:85b3fd62ea1a 9665 /******************* Bit definition for IWDG_SR register ********************/
NYX 0:85b3fd62ea1a 9666 #define IWDG_SR_PVU_Pos (0U)
NYX 0:85b3fd62ea1a 9667 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9668 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
NYX 0:85b3fd62ea1a 9669 #define IWDG_SR_RVU_Pos (1U)
NYX 0:85b3fd62ea1a 9670 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9671 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
NYX 0:85b3fd62ea1a 9672
NYX 0:85b3fd62ea1a 9673
NYX 0:85b3fd62ea1a 9674
NYX 0:85b3fd62ea1a 9675 /******************************************************************************/
NYX 0:85b3fd62ea1a 9676 /* */
NYX 0:85b3fd62ea1a 9677 /* Power Control */
NYX 0:85b3fd62ea1a 9678 /* */
NYX 0:85b3fd62ea1a 9679 /******************************************************************************/
NYX 0:85b3fd62ea1a 9680 /******************** Bit definition for PWR_CR register ********************/
NYX 0:85b3fd62ea1a 9681 #define PWR_CR_LPDS_Pos (0U)
NYX 0:85b3fd62ea1a 9682 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9683 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
NYX 0:85b3fd62ea1a 9684 #define PWR_CR_PDDS_Pos (1U)
NYX 0:85b3fd62ea1a 9685 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9686 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
NYX 0:85b3fd62ea1a 9687 #define PWR_CR_CWUF_Pos (2U)
NYX 0:85b3fd62ea1a 9688 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9689 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
NYX 0:85b3fd62ea1a 9690 #define PWR_CR_CSBF_Pos (3U)
NYX 0:85b3fd62ea1a 9691 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9692 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
NYX 0:85b3fd62ea1a 9693 #define PWR_CR_PVDE_Pos (4U)
NYX 0:85b3fd62ea1a 9694 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9695 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
NYX 0:85b3fd62ea1a 9696
NYX 0:85b3fd62ea1a 9697 #define PWR_CR_PLS_Pos (5U)
NYX 0:85b3fd62ea1a 9698 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
NYX 0:85b3fd62ea1a 9699 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
NYX 0:85b3fd62ea1a 9700 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9701 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9702 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9703
NYX 0:85b3fd62ea1a 9704 /*!< PVD level configuration */
NYX 0:85b3fd62ea1a 9705 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
NYX 0:85b3fd62ea1a 9706 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
NYX 0:85b3fd62ea1a 9707 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
NYX 0:85b3fd62ea1a 9708 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
NYX 0:85b3fd62ea1a 9709 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
NYX 0:85b3fd62ea1a 9710 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
NYX 0:85b3fd62ea1a 9711 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
NYX 0:85b3fd62ea1a 9712 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
NYX 0:85b3fd62ea1a 9713 #define PWR_CR_DBP_Pos (8U)
NYX 0:85b3fd62ea1a 9714 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9715 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
NYX 0:85b3fd62ea1a 9716 #define PWR_CR_FPDS_Pos (9U)
NYX 0:85b3fd62ea1a 9717 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9718 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
NYX 0:85b3fd62ea1a 9719 #define PWR_CR_LPLVDS_Pos (10U)
NYX 0:85b3fd62ea1a 9720 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9721 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
NYX 0:85b3fd62ea1a 9722 #define PWR_CR_MRLVDS_Pos (11U)
NYX 0:85b3fd62ea1a 9723 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9724 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
NYX 0:85b3fd62ea1a 9725 #define PWR_CR_ADCDC1_Pos (13U)
NYX 0:85b3fd62ea1a 9726 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 9727 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
NYX 0:85b3fd62ea1a 9728 #define PWR_CR_VOS_Pos (14U)
NYX 0:85b3fd62ea1a 9729 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
NYX 0:85b3fd62ea1a 9730 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
NYX 0:85b3fd62ea1a 9731 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
NYX 0:85b3fd62ea1a 9732 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
NYX 0:85b3fd62ea1a 9733 #define PWR_CR_ODEN_Pos (16U)
NYX 0:85b3fd62ea1a 9734 #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 9735 #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
NYX 0:85b3fd62ea1a 9736 #define PWR_CR_ODSWEN_Pos (17U)
NYX 0:85b3fd62ea1a 9737 #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 9738 #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
NYX 0:85b3fd62ea1a 9739 #define PWR_CR_UDEN_Pos (18U)
NYX 0:85b3fd62ea1a 9740 #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
NYX 0:85b3fd62ea1a 9741 #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
NYX 0:85b3fd62ea1a 9742 #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 9743 #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 9744 #define PWR_CR_FMSSR_Pos (20U)
NYX 0:85b3fd62ea1a 9745 #define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 9746 #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
NYX 0:85b3fd62ea1a 9747 #define PWR_CR_FISSR_Pos (21U)
NYX 0:85b3fd62ea1a 9748 #define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 9749 #define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
NYX 0:85b3fd62ea1a 9750
NYX 0:85b3fd62ea1a 9751 /* Legacy define */
NYX 0:85b3fd62ea1a 9752 #define PWR_CR_PMODE PWR_CR_VOS
NYX 0:85b3fd62ea1a 9753 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
NYX 0:85b3fd62ea1a 9754 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
NYX 0:85b3fd62ea1a 9755
NYX 0:85b3fd62ea1a 9756 /******************* Bit definition for PWR_CSR register ********************/
NYX 0:85b3fd62ea1a 9757 #define PWR_CSR_WUF_Pos (0U)
NYX 0:85b3fd62ea1a 9758 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9759 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
NYX 0:85b3fd62ea1a 9760 #define PWR_CSR_SBF_Pos (1U)
NYX 0:85b3fd62ea1a 9761 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9762 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
NYX 0:85b3fd62ea1a 9763 #define PWR_CSR_PVDO_Pos (2U)
NYX 0:85b3fd62ea1a 9764 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9765 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
NYX 0:85b3fd62ea1a 9766 #define PWR_CSR_BRR_Pos (3U)
NYX 0:85b3fd62ea1a 9767 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9768 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
NYX 0:85b3fd62ea1a 9769 #define PWR_CSR_EWUP2_Pos (7U)
NYX 0:85b3fd62ea1a 9770 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9771 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
NYX 0:85b3fd62ea1a 9772 #define PWR_CSR_EWUP1_Pos (8U)
NYX 0:85b3fd62ea1a 9773 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9774 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
NYX 0:85b3fd62ea1a 9775 #define PWR_CSR_BRE_Pos (9U)
NYX 0:85b3fd62ea1a 9776 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9777 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
NYX 0:85b3fd62ea1a 9778 #define PWR_CSR_VOSRDY_Pos (14U)
NYX 0:85b3fd62ea1a 9779 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 9780 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
NYX 0:85b3fd62ea1a 9781 #define PWR_CSR_ODRDY_Pos (16U)
NYX 0:85b3fd62ea1a 9782 #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 9783 #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
NYX 0:85b3fd62ea1a 9784 #define PWR_CSR_ODSWRDY_Pos (17U)
NYX 0:85b3fd62ea1a 9785 #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 9786 #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
NYX 0:85b3fd62ea1a 9787 #define PWR_CSR_UDRDY_Pos (18U)
NYX 0:85b3fd62ea1a 9788 #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
NYX 0:85b3fd62ea1a 9789 #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
NYX 0:85b3fd62ea1a 9790 /* Legacy define */
NYX 0:85b3fd62ea1a 9791 #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
NYX 0:85b3fd62ea1a 9792
NYX 0:85b3fd62ea1a 9793 /* Legacy define */
NYX 0:85b3fd62ea1a 9794 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
NYX 0:85b3fd62ea1a 9795
NYX 0:85b3fd62ea1a 9796 /******************************************************************************/
NYX 0:85b3fd62ea1a 9797 /* */
NYX 0:85b3fd62ea1a 9798 /* QUADSPI */
NYX 0:85b3fd62ea1a 9799 /* */
NYX 0:85b3fd62ea1a 9800 /******************************************************************************/
NYX 0:85b3fd62ea1a 9801 /***************** Bit definition for QUADSPI_CR register *******************/
NYX 0:85b3fd62ea1a 9802 #define QUADSPI_CR_EN_Pos (0U)
NYX 0:85b3fd62ea1a 9803 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9804 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
NYX 0:85b3fd62ea1a 9805 #define QUADSPI_CR_ABORT_Pos (1U)
NYX 0:85b3fd62ea1a 9806 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9807 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
NYX 0:85b3fd62ea1a 9808 #define QUADSPI_CR_DMAEN_Pos (2U)
NYX 0:85b3fd62ea1a 9809 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9810 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
NYX 0:85b3fd62ea1a 9811 #define QUADSPI_CR_TCEN_Pos (3U)
NYX 0:85b3fd62ea1a 9812 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9813 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
NYX 0:85b3fd62ea1a 9814 #define QUADSPI_CR_SSHIFT_Pos (4U)
NYX 0:85b3fd62ea1a 9815 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9816 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
NYX 0:85b3fd62ea1a 9817 #define QUADSPI_CR_DFM_Pos (6U)
NYX 0:85b3fd62ea1a 9818 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9819 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
NYX 0:85b3fd62ea1a 9820 #define QUADSPI_CR_FSEL_Pos (7U)
NYX 0:85b3fd62ea1a 9821 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9822 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
NYX 0:85b3fd62ea1a 9823 #define QUADSPI_CR_FTHRES_Pos (8U)
NYX 0:85b3fd62ea1a 9824 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
NYX 0:85b3fd62ea1a 9825 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
NYX 0:85b3fd62ea1a 9826 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9827 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9828 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9829 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9830 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9831 #define QUADSPI_CR_TEIE_Pos (16U)
NYX 0:85b3fd62ea1a 9832 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 9833 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
NYX 0:85b3fd62ea1a 9834 #define QUADSPI_CR_TCIE_Pos (17U)
NYX 0:85b3fd62ea1a 9835 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 9836 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
NYX 0:85b3fd62ea1a 9837 #define QUADSPI_CR_FTIE_Pos (18U)
NYX 0:85b3fd62ea1a 9838 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 9839 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
NYX 0:85b3fd62ea1a 9840 #define QUADSPI_CR_SMIE_Pos (19U)
NYX 0:85b3fd62ea1a 9841 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 9842 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
NYX 0:85b3fd62ea1a 9843 #define QUADSPI_CR_TOIE_Pos (20U)
NYX 0:85b3fd62ea1a 9844 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 9845 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
NYX 0:85b3fd62ea1a 9846 #define QUADSPI_CR_APMS_Pos (22U)
NYX 0:85b3fd62ea1a 9847 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 9848 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
NYX 0:85b3fd62ea1a 9849 #define QUADSPI_CR_PMM_Pos (23U)
NYX 0:85b3fd62ea1a 9850 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 9851 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
NYX 0:85b3fd62ea1a 9852 #define QUADSPI_CR_PRESCALER_Pos (24U)
NYX 0:85b3fd62ea1a 9853 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 9854 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
NYX 0:85b3fd62ea1a 9855 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 9856 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 9857 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 9858 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 9859 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 9860 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 9861 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 9862 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 9863
NYX 0:85b3fd62ea1a 9864 /***************** Bit definition for QUADSPI_DCR register ******************/
NYX 0:85b3fd62ea1a 9865 #define QUADSPI_DCR_CKMODE_Pos (0U)
NYX 0:85b3fd62ea1a 9866 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9867 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
NYX 0:85b3fd62ea1a 9868 #define QUADSPI_DCR_CSHT_Pos (8U)
NYX 0:85b3fd62ea1a 9869 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
NYX 0:85b3fd62ea1a 9870 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
NYX 0:85b3fd62ea1a 9871 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9872 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9873 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9874 #define QUADSPI_DCR_FSIZE_Pos (16U)
NYX 0:85b3fd62ea1a 9875 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
NYX 0:85b3fd62ea1a 9876 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
NYX 0:85b3fd62ea1a 9877 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 9878 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 9879 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 9880 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 9881 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 9882
NYX 0:85b3fd62ea1a 9883 /****************** Bit definition for QUADSPI_SR register *******************/
NYX 0:85b3fd62ea1a 9884 #define QUADSPI_SR_TEF_Pos (0U)
NYX 0:85b3fd62ea1a 9885 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9886 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
NYX 0:85b3fd62ea1a 9887 #define QUADSPI_SR_TCF_Pos (1U)
NYX 0:85b3fd62ea1a 9888 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9889 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
NYX 0:85b3fd62ea1a 9890 #define QUADSPI_SR_FTF_Pos (2U)
NYX 0:85b3fd62ea1a 9891 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9892 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
NYX 0:85b3fd62ea1a 9893 #define QUADSPI_SR_SMF_Pos (3U)
NYX 0:85b3fd62ea1a 9894 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9895 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
NYX 0:85b3fd62ea1a 9896 #define QUADSPI_SR_TOF_Pos (4U)
NYX 0:85b3fd62ea1a 9897 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9898 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
NYX 0:85b3fd62ea1a 9899 #define QUADSPI_SR_BUSY_Pos (5U)
NYX 0:85b3fd62ea1a 9900 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9901 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
NYX 0:85b3fd62ea1a 9902 #define QUADSPI_SR_FLEVEL_Pos (8U)
NYX 0:85b3fd62ea1a 9903 #define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
NYX 0:85b3fd62ea1a 9904 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
NYX 0:85b3fd62ea1a 9905 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9906 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9907 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9908 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9909 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9910 #define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 9911
NYX 0:85b3fd62ea1a 9912 /****************** Bit definition for QUADSPI_FCR register ******************/
NYX 0:85b3fd62ea1a 9913 #define QUADSPI_FCR_CTEF_Pos (0U)
NYX 0:85b3fd62ea1a 9914 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9915 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
NYX 0:85b3fd62ea1a 9916 #define QUADSPI_FCR_CTCF_Pos (1U)
NYX 0:85b3fd62ea1a 9917 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9918 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
NYX 0:85b3fd62ea1a 9919 #define QUADSPI_FCR_CSMF_Pos (3U)
NYX 0:85b3fd62ea1a 9920 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9921 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
NYX 0:85b3fd62ea1a 9922 #define QUADSPI_FCR_CTOF_Pos (4U)
NYX 0:85b3fd62ea1a 9923 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9924 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
NYX 0:85b3fd62ea1a 9925
NYX 0:85b3fd62ea1a 9926 /****************** Bit definition for QUADSPI_DLR register ******************/
NYX 0:85b3fd62ea1a 9927 #define QUADSPI_DLR_DL_Pos (0U)
NYX 0:85b3fd62ea1a 9928 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 9929 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
NYX 0:85b3fd62ea1a 9930
NYX 0:85b3fd62ea1a 9931 /****************** Bit definition for QUADSPI_CCR register ******************/
NYX 0:85b3fd62ea1a 9932 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
NYX 0:85b3fd62ea1a 9933 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 9934 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
NYX 0:85b3fd62ea1a 9935 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 9936 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 9937 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 9938 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 9939 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 9940 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 9941 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 9942 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 9943 #define QUADSPI_CCR_IMODE_Pos (8U)
NYX 0:85b3fd62ea1a 9944 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 9945 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
NYX 0:85b3fd62ea1a 9946 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 9947 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 9948 #define QUADSPI_CCR_ADMODE_Pos (10U)
NYX 0:85b3fd62ea1a 9949 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 9950 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
NYX 0:85b3fd62ea1a 9951 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 9952 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 9953 #define QUADSPI_CCR_ADSIZE_Pos (12U)
NYX 0:85b3fd62ea1a 9954 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
NYX 0:85b3fd62ea1a 9955 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
NYX 0:85b3fd62ea1a 9956 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 9957 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 9958 #define QUADSPI_CCR_ABMODE_Pos (14U)
NYX 0:85b3fd62ea1a 9959 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
NYX 0:85b3fd62ea1a 9960 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
NYX 0:85b3fd62ea1a 9961 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 9962 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 9963 #define QUADSPI_CCR_ABSIZE_Pos (16U)
NYX 0:85b3fd62ea1a 9964 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 9965 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
NYX 0:85b3fd62ea1a 9966 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 9967 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 9968 #define QUADSPI_CCR_DCYC_Pos (18U)
NYX 0:85b3fd62ea1a 9969 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
NYX 0:85b3fd62ea1a 9970 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
NYX 0:85b3fd62ea1a 9971 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 9972 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 9973 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 9974 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 9975 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 9976 #define QUADSPI_CCR_DMODE_Pos (24U)
NYX 0:85b3fd62ea1a 9977 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
NYX 0:85b3fd62ea1a 9978 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
NYX 0:85b3fd62ea1a 9979 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 9980 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 9981 #define QUADSPI_CCR_FMODE_Pos (26U)
NYX 0:85b3fd62ea1a 9982 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
NYX 0:85b3fd62ea1a 9983 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
NYX 0:85b3fd62ea1a 9984 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 9985 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 9986 #define QUADSPI_CCR_SIOO_Pos (28U)
NYX 0:85b3fd62ea1a 9987 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 9988 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
NYX 0:85b3fd62ea1a 9989 #define QUADSPI_CCR_DHHC_Pos (30U)
NYX 0:85b3fd62ea1a 9990 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 9991 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
NYX 0:85b3fd62ea1a 9992 #define QUADSPI_CCR_DDRM_Pos (31U)
NYX 0:85b3fd62ea1a 9993 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 9994 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
NYX 0:85b3fd62ea1a 9995 /****************** Bit definition for QUADSPI_AR register *******************/
NYX 0:85b3fd62ea1a 9996 #define QUADSPI_AR_ADDRESS_Pos (0U)
NYX 0:85b3fd62ea1a 9997 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 9998 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
NYX 0:85b3fd62ea1a 9999
NYX 0:85b3fd62ea1a 10000 /****************** Bit definition for QUADSPI_ABR register ******************/
NYX 0:85b3fd62ea1a 10001 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
NYX 0:85b3fd62ea1a 10002 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 10003 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
NYX 0:85b3fd62ea1a 10004
NYX 0:85b3fd62ea1a 10005 /****************** Bit definition for QUADSPI_DR register *******************/
NYX 0:85b3fd62ea1a 10006 #define QUADSPI_DR_DATA_Pos (0U)
NYX 0:85b3fd62ea1a 10007 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 10008 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
NYX 0:85b3fd62ea1a 10009
NYX 0:85b3fd62ea1a 10010 /****************** Bit definition for QUADSPI_PSMKR register ****************/
NYX 0:85b3fd62ea1a 10011 #define QUADSPI_PSMKR_MASK_Pos (0U)
NYX 0:85b3fd62ea1a 10012 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 10013 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
NYX 0:85b3fd62ea1a 10014
NYX 0:85b3fd62ea1a 10015 /****************** Bit definition for QUADSPI_PSMAR register ****************/
NYX 0:85b3fd62ea1a 10016 #define QUADSPI_PSMAR_MATCH_Pos (0U)
NYX 0:85b3fd62ea1a 10017 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 10018 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
NYX 0:85b3fd62ea1a 10019
NYX 0:85b3fd62ea1a 10020 /****************** Bit definition for QUADSPI_PIR register *****************/
NYX 0:85b3fd62ea1a 10021 #define QUADSPI_PIR_INTERVAL_Pos (0U)
NYX 0:85b3fd62ea1a 10022 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 10023 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
NYX 0:85b3fd62ea1a 10024
NYX 0:85b3fd62ea1a 10025 /****************** Bit definition for QUADSPI_LPTR register *****************/
NYX 0:85b3fd62ea1a 10026 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
NYX 0:85b3fd62ea1a 10027 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 10028 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
NYX 0:85b3fd62ea1a 10029
NYX 0:85b3fd62ea1a 10030 /******************************************************************************/
NYX 0:85b3fd62ea1a 10031 /* */
NYX 0:85b3fd62ea1a 10032 /* Reset and Clock Control */
NYX 0:85b3fd62ea1a 10033 /* */
NYX 0:85b3fd62ea1a 10034 /******************************************************************************/
NYX 0:85b3fd62ea1a 10035 /******************** Bit definition for RCC_CR register ********************/
NYX 0:85b3fd62ea1a 10036 #define RCC_CR_HSION_Pos (0U)
NYX 0:85b3fd62ea1a 10037 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10038 #define RCC_CR_HSION RCC_CR_HSION_Msk
NYX 0:85b3fd62ea1a 10039 #define RCC_CR_HSIRDY_Pos (1U)
NYX 0:85b3fd62ea1a 10040 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10041 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
NYX 0:85b3fd62ea1a 10042
NYX 0:85b3fd62ea1a 10043 #define RCC_CR_HSITRIM_Pos (3U)
NYX 0:85b3fd62ea1a 10044 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
NYX 0:85b3fd62ea1a 10045 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
NYX 0:85b3fd62ea1a 10046 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10047 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10048 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10049 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10050 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10051
NYX 0:85b3fd62ea1a 10052 #define RCC_CR_HSICAL_Pos (8U)
NYX 0:85b3fd62ea1a 10053 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 10054 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
NYX 0:85b3fd62ea1a 10055 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10056 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 10057 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 10058 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10059 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10060 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 10061 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10062 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 10063
NYX 0:85b3fd62ea1a 10064 #define RCC_CR_HSEON_Pos (16U)
NYX 0:85b3fd62ea1a 10065 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10066 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
NYX 0:85b3fd62ea1a 10067 #define RCC_CR_HSERDY_Pos (17U)
NYX 0:85b3fd62ea1a 10068 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10069 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
NYX 0:85b3fd62ea1a 10070 #define RCC_CR_HSEBYP_Pos (18U)
NYX 0:85b3fd62ea1a 10071 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10072 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
NYX 0:85b3fd62ea1a 10073 #define RCC_CR_CSSON_Pos (19U)
NYX 0:85b3fd62ea1a 10074 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 10075 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
NYX 0:85b3fd62ea1a 10076 #define RCC_CR_PLLON_Pos (24U)
NYX 0:85b3fd62ea1a 10077 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 10078 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
NYX 0:85b3fd62ea1a 10079 #define RCC_CR_PLLRDY_Pos (25U)
NYX 0:85b3fd62ea1a 10080 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 10081 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
NYX 0:85b3fd62ea1a 10082 /*
NYX 0:85b3fd62ea1a 10083 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
NYX 0:85b3fd62ea1a 10084 */
NYX 0:85b3fd62ea1a 10085 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
NYX 0:85b3fd62ea1a 10086
NYX 0:85b3fd62ea1a 10087 #define RCC_CR_PLLI2SON_Pos (26U)
NYX 0:85b3fd62ea1a 10088 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 10089 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
NYX 0:85b3fd62ea1a 10090 #define RCC_CR_PLLI2SRDY_Pos (27U)
NYX 0:85b3fd62ea1a 10091 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 10092 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
NYX 0:85b3fd62ea1a 10093 /*
NYX 0:85b3fd62ea1a 10094 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
NYX 0:85b3fd62ea1a 10095 */
NYX 0:85b3fd62ea1a 10096 #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
NYX 0:85b3fd62ea1a 10097
NYX 0:85b3fd62ea1a 10098 #define RCC_CR_PLLSAION_Pos (28U)
NYX 0:85b3fd62ea1a 10099 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 10100 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
NYX 0:85b3fd62ea1a 10101 #define RCC_CR_PLLSAIRDY_Pos (29U)
NYX 0:85b3fd62ea1a 10102 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10103 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
NYX 0:85b3fd62ea1a 10104
NYX 0:85b3fd62ea1a 10105 /******************** Bit definition for RCC_PLLCFGR register ***************/
NYX 0:85b3fd62ea1a 10106 #define RCC_PLLCFGR_PLLM_Pos (0U)
NYX 0:85b3fd62ea1a 10107 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
NYX 0:85b3fd62ea1a 10108 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
NYX 0:85b3fd62ea1a 10109 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10110 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10111 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10112 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10113 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10114 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10115
NYX 0:85b3fd62ea1a 10116 #define RCC_PLLCFGR_PLLN_Pos (6U)
NYX 0:85b3fd62ea1a 10117 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
NYX 0:85b3fd62ea1a 10118 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
NYX 0:85b3fd62ea1a 10119 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10120 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10121 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10122 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 10123 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 10124 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10125 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10126 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 10127 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10128
NYX 0:85b3fd62ea1a 10129 #define RCC_PLLCFGR_PLLP_Pos (16U)
NYX 0:85b3fd62ea1a 10130 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 10131 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
NYX 0:85b3fd62ea1a 10132 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10133 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10134
NYX 0:85b3fd62ea1a 10135 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
NYX 0:85b3fd62ea1a 10136 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10137 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
NYX 0:85b3fd62ea1a 10138 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
NYX 0:85b3fd62ea1a 10139 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10140 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
NYX 0:85b3fd62ea1a 10141 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
NYX 0:85b3fd62ea1a 10142
NYX 0:85b3fd62ea1a 10143 #define RCC_PLLCFGR_PLLQ_Pos (24U)
NYX 0:85b3fd62ea1a 10144 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 10145 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
NYX 0:85b3fd62ea1a 10146 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 10147 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 10148 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 10149 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 10150 /*
NYX 0:85b3fd62ea1a 10151 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
NYX 0:85b3fd62ea1a 10152 */
NYX 0:85b3fd62ea1a 10153 #define RCC_PLLR_SYSCLK_SUPPORT /*!< Support PLLR as system clock */
NYX 0:85b3fd62ea1a 10154 #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
NYX 0:85b3fd62ea1a 10155
NYX 0:85b3fd62ea1a 10156 #define RCC_PLLCFGR_PLLR_Pos (28U)
NYX 0:85b3fd62ea1a 10157 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
NYX 0:85b3fd62ea1a 10158 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
NYX 0:85b3fd62ea1a 10159 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 10160 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10161 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 10162
NYX 0:85b3fd62ea1a 10163 /******************** Bit definition for RCC_CFGR register ******************/
NYX 0:85b3fd62ea1a 10164 /*!< SW configuration */
NYX 0:85b3fd62ea1a 10165 #define RCC_CFGR_SW_Pos (0U)
NYX 0:85b3fd62ea1a 10166 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 10167 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
NYX 0:85b3fd62ea1a 10168 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10169 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10170
NYX 0:85b3fd62ea1a 10171 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
NYX 0:85b3fd62ea1a 10172 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
NYX 0:85b3fd62ea1a 10173 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
NYX 0:85b3fd62ea1a 10174 #define RCC_CFGR_SW_PLLR 0x00000003U /*!< PLL/PLLR selected as system clock */
NYX 0:85b3fd62ea1a 10175
NYX 0:85b3fd62ea1a 10176 /*!< SWS configuration */
NYX 0:85b3fd62ea1a 10177 #define RCC_CFGR_SWS_Pos (2U)
NYX 0:85b3fd62ea1a 10178 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 10179 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
NYX 0:85b3fd62ea1a 10180 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10181 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10182
NYX 0:85b3fd62ea1a 10183 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
NYX 0:85b3fd62ea1a 10184 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
NYX 0:85b3fd62ea1a 10185 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
NYX 0:85b3fd62ea1a 10186 #define RCC_CFGR_SWS_PLLR 0x0000000CU /*!< PLL/PLLR used as system clock */
NYX 0:85b3fd62ea1a 10187
NYX 0:85b3fd62ea1a 10188 /*!< HPRE configuration */
NYX 0:85b3fd62ea1a 10189 #define RCC_CFGR_HPRE_Pos (4U)
NYX 0:85b3fd62ea1a 10190 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 10191 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
NYX 0:85b3fd62ea1a 10192 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10193 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10194 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10195 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10196
NYX 0:85b3fd62ea1a 10197 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
NYX 0:85b3fd62ea1a 10198 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
NYX 0:85b3fd62ea1a 10199 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
NYX 0:85b3fd62ea1a 10200 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
NYX 0:85b3fd62ea1a 10201 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
NYX 0:85b3fd62ea1a 10202 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
NYX 0:85b3fd62ea1a 10203 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
NYX 0:85b3fd62ea1a 10204 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
NYX 0:85b3fd62ea1a 10205 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
NYX 0:85b3fd62ea1a 10206
NYX 0:85b3fd62ea1a 10207 /*!< PPRE1 configuration */
NYX 0:85b3fd62ea1a 10208 #define RCC_CFGR_PPRE1_Pos (10U)
NYX 0:85b3fd62ea1a 10209 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
NYX 0:85b3fd62ea1a 10210 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
NYX 0:85b3fd62ea1a 10211 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 10212 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10213 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10214
NYX 0:85b3fd62ea1a 10215 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
NYX 0:85b3fd62ea1a 10216 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
NYX 0:85b3fd62ea1a 10217 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
NYX 0:85b3fd62ea1a 10218 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
NYX 0:85b3fd62ea1a 10219 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
NYX 0:85b3fd62ea1a 10220
NYX 0:85b3fd62ea1a 10221 /*!< PPRE2 configuration */
NYX 0:85b3fd62ea1a 10222 #define RCC_CFGR_PPRE2_Pos (13U)
NYX 0:85b3fd62ea1a 10223 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
NYX 0:85b3fd62ea1a 10224 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
NYX 0:85b3fd62ea1a 10225 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 10226 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10227 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 10228
NYX 0:85b3fd62ea1a 10229 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
NYX 0:85b3fd62ea1a 10230 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
NYX 0:85b3fd62ea1a 10231 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
NYX 0:85b3fd62ea1a 10232 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
NYX 0:85b3fd62ea1a 10233 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
NYX 0:85b3fd62ea1a 10234
NYX 0:85b3fd62ea1a 10235 /*!< RTCPRE configuration */
NYX 0:85b3fd62ea1a 10236 #define RCC_CFGR_RTCPRE_Pos (16U)
NYX 0:85b3fd62ea1a 10237 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
NYX 0:85b3fd62ea1a 10238 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
NYX 0:85b3fd62ea1a 10239 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10240 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10241 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10242 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 10243 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 10244
NYX 0:85b3fd62ea1a 10245 /*!< MCO1 configuration */
NYX 0:85b3fd62ea1a 10246 #define RCC_CFGR_MCO1_Pos (21U)
NYX 0:85b3fd62ea1a 10247 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
NYX 0:85b3fd62ea1a 10248 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
NYX 0:85b3fd62ea1a 10249 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 10250 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10251
NYX 0:85b3fd62ea1a 10252
NYX 0:85b3fd62ea1a 10253 #define RCC_CFGR_MCO1PRE_Pos (24U)
NYX 0:85b3fd62ea1a 10254 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
NYX 0:85b3fd62ea1a 10255 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
NYX 0:85b3fd62ea1a 10256 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 10257 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 10258 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 10259
NYX 0:85b3fd62ea1a 10260 #define RCC_CFGR_MCO2PRE_Pos (27U)
NYX 0:85b3fd62ea1a 10261 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
NYX 0:85b3fd62ea1a 10262 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
NYX 0:85b3fd62ea1a 10263 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 10264 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 10265 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10266
NYX 0:85b3fd62ea1a 10267 #define RCC_CFGR_MCO2_Pos (30U)
NYX 0:85b3fd62ea1a 10268 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
NYX 0:85b3fd62ea1a 10269 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
NYX 0:85b3fd62ea1a 10270 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 10271 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 10272
NYX 0:85b3fd62ea1a 10273 /******************** Bit definition for RCC_CIR register *******************/
NYX 0:85b3fd62ea1a 10274 #define RCC_CIR_LSIRDYF_Pos (0U)
NYX 0:85b3fd62ea1a 10275 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10276 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
NYX 0:85b3fd62ea1a 10277 #define RCC_CIR_LSERDYF_Pos (1U)
NYX 0:85b3fd62ea1a 10278 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10279 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
NYX 0:85b3fd62ea1a 10280 #define RCC_CIR_HSIRDYF_Pos (2U)
NYX 0:85b3fd62ea1a 10281 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10282 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
NYX 0:85b3fd62ea1a 10283 #define RCC_CIR_HSERDYF_Pos (3U)
NYX 0:85b3fd62ea1a 10284 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10285 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
NYX 0:85b3fd62ea1a 10286 #define RCC_CIR_PLLRDYF_Pos (4U)
NYX 0:85b3fd62ea1a 10287 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10288 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
NYX 0:85b3fd62ea1a 10289 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
NYX 0:85b3fd62ea1a 10290 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10291 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
NYX 0:85b3fd62ea1a 10292
NYX 0:85b3fd62ea1a 10293 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
NYX 0:85b3fd62ea1a 10294 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10295 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
NYX 0:85b3fd62ea1a 10296 #define RCC_CIR_CSSF_Pos (7U)
NYX 0:85b3fd62ea1a 10297 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10298 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
NYX 0:85b3fd62ea1a 10299 #define RCC_CIR_LSIRDYIE_Pos (8U)
NYX 0:85b3fd62ea1a 10300 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10301 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
NYX 0:85b3fd62ea1a 10302 #define RCC_CIR_LSERDYIE_Pos (9U)
NYX 0:85b3fd62ea1a 10303 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 10304 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
NYX 0:85b3fd62ea1a 10305 #define RCC_CIR_HSIRDYIE_Pos (10U)
NYX 0:85b3fd62ea1a 10306 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 10307 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
NYX 0:85b3fd62ea1a 10308 #define RCC_CIR_HSERDYIE_Pos (11U)
NYX 0:85b3fd62ea1a 10309 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10310 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
NYX 0:85b3fd62ea1a 10311 #define RCC_CIR_PLLRDYIE_Pos (12U)
NYX 0:85b3fd62ea1a 10312 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10313 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
NYX 0:85b3fd62ea1a 10314 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
NYX 0:85b3fd62ea1a 10315 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 10316 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
NYX 0:85b3fd62ea1a 10317
NYX 0:85b3fd62ea1a 10318 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
NYX 0:85b3fd62ea1a 10319 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10320 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
NYX 0:85b3fd62ea1a 10321 #define RCC_CIR_LSIRDYC_Pos (16U)
NYX 0:85b3fd62ea1a 10322 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10323 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
NYX 0:85b3fd62ea1a 10324 #define RCC_CIR_LSERDYC_Pos (17U)
NYX 0:85b3fd62ea1a 10325 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10326 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
NYX 0:85b3fd62ea1a 10327 #define RCC_CIR_HSIRDYC_Pos (18U)
NYX 0:85b3fd62ea1a 10328 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10329 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
NYX 0:85b3fd62ea1a 10330 #define RCC_CIR_HSERDYC_Pos (19U)
NYX 0:85b3fd62ea1a 10331 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 10332 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
NYX 0:85b3fd62ea1a 10333 #define RCC_CIR_PLLRDYC_Pos (20U)
NYX 0:85b3fd62ea1a 10334 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 10335 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
NYX 0:85b3fd62ea1a 10336 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
NYX 0:85b3fd62ea1a 10337 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 10338 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
NYX 0:85b3fd62ea1a 10339 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
NYX 0:85b3fd62ea1a 10340 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10341 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
NYX 0:85b3fd62ea1a 10342
NYX 0:85b3fd62ea1a 10343 #define RCC_CIR_CSSC_Pos (23U)
NYX 0:85b3fd62ea1a 10344 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 10345 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
NYX 0:85b3fd62ea1a 10346
NYX 0:85b3fd62ea1a 10347 /******************** Bit definition for RCC_AHB1RSTR register **************/
NYX 0:85b3fd62ea1a 10348 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
NYX 0:85b3fd62ea1a 10349 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10350 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
NYX 0:85b3fd62ea1a 10351 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
NYX 0:85b3fd62ea1a 10352 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10353 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
NYX 0:85b3fd62ea1a 10354 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
NYX 0:85b3fd62ea1a 10355 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10356 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
NYX 0:85b3fd62ea1a 10357 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
NYX 0:85b3fd62ea1a 10358 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10359 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
NYX 0:85b3fd62ea1a 10360 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
NYX 0:85b3fd62ea1a 10361 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10362 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
NYX 0:85b3fd62ea1a 10363 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
NYX 0:85b3fd62ea1a 10364 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10365 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
NYX 0:85b3fd62ea1a 10366 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
NYX 0:85b3fd62ea1a 10367 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10368 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
NYX 0:85b3fd62ea1a 10369 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
NYX 0:85b3fd62ea1a 10370 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10371 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
NYX 0:85b3fd62ea1a 10372 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
NYX 0:85b3fd62ea1a 10373 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10374 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
NYX 0:85b3fd62ea1a 10375 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
NYX 0:85b3fd62ea1a 10376 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 10377 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
NYX 0:85b3fd62ea1a 10378 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
NYX 0:85b3fd62ea1a 10379 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10380 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
NYX 0:85b3fd62ea1a 10381 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
NYX 0:85b3fd62ea1a 10382 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10383 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
NYX 0:85b3fd62ea1a 10384
NYX 0:85b3fd62ea1a 10385 /******************** Bit definition for RCC_AHB2RSTR register **************/
NYX 0:85b3fd62ea1a 10386 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
NYX 0:85b3fd62ea1a 10387 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10388 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
NYX 0:85b3fd62ea1a 10389 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
NYX 0:85b3fd62ea1a 10390 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10391 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
NYX 0:85b3fd62ea1a 10392 /******************** Bit definition for RCC_AHB3RSTR register **************/
NYX 0:85b3fd62ea1a 10393 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
NYX 0:85b3fd62ea1a 10394 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10395 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
NYX 0:85b3fd62ea1a 10396 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
NYX 0:85b3fd62ea1a 10397 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10398 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
NYX 0:85b3fd62ea1a 10399
NYX 0:85b3fd62ea1a 10400
NYX 0:85b3fd62ea1a 10401 /******************** Bit definition for RCC_APB1RSTR register **************/
NYX 0:85b3fd62ea1a 10402 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
NYX 0:85b3fd62ea1a 10403 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10404 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
NYX 0:85b3fd62ea1a 10405 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
NYX 0:85b3fd62ea1a 10406 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10407 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
NYX 0:85b3fd62ea1a 10408 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
NYX 0:85b3fd62ea1a 10409 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10410 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
NYX 0:85b3fd62ea1a 10411 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
NYX 0:85b3fd62ea1a 10412 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10413 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
NYX 0:85b3fd62ea1a 10414 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
NYX 0:85b3fd62ea1a 10415 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10416 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
NYX 0:85b3fd62ea1a 10417 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
NYX 0:85b3fd62ea1a 10418 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10419 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
NYX 0:85b3fd62ea1a 10420 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
NYX 0:85b3fd62ea1a 10421 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10422 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
NYX 0:85b3fd62ea1a 10423 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
NYX 0:85b3fd62ea1a 10424 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10425 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
NYX 0:85b3fd62ea1a 10426 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
NYX 0:85b3fd62ea1a 10427 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10428 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
NYX 0:85b3fd62ea1a 10429 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
NYX 0:85b3fd62ea1a 10430 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10431 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
NYX 0:85b3fd62ea1a 10432 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
NYX 0:85b3fd62ea1a 10433 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10434 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
NYX 0:85b3fd62ea1a 10435 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
NYX 0:85b3fd62ea1a 10436 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 10437 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
NYX 0:85b3fd62ea1a 10438 #define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
NYX 0:85b3fd62ea1a 10439 #define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1U << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10440 #define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
NYX 0:85b3fd62ea1a 10441 #define RCC_APB1RSTR_USART2RST_Pos (17U)
NYX 0:85b3fd62ea1a 10442 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10443 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
NYX 0:85b3fd62ea1a 10444 #define RCC_APB1RSTR_USART3RST_Pos (18U)
NYX 0:85b3fd62ea1a 10445 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10446 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
NYX 0:85b3fd62ea1a 10447 #define RCC_APB1RSTR_UART4RST_Pos (19U)
NYX 0:85b3fd62ea1a 10448 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 10449 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
NYX 0:85b3fd62ea1a 10450 #define RCC_APB1RSTR_UART5RST_Pos (20U)
NYX 0:85b3fd62ea1a 10451 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 10452 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
NYX 0:85b3fd62ea1a 10453 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
NYX 0:85b3fd62ea1a 10454 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 10455 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
NYX 0:85b3fd62ea1a 10456 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
NYX 0:85b3fd62ea1a 10457 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10458 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
NYX 0:85b3fd62ea1a 10459 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
NYX 0:85b3fd62ea1a 10460 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 10461 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
NYX 0:85b3fd62ea1a 10462 #define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
NYX 0:85b3fd62ea1a 10463 #define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 10464 #define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
NYX 0:85b3fd62ea1a 10465 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
NYX 0:85b3fd62ea1a 10466 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 10467 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
NYX 0:85b3fd62ea1a 10468 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
NYX 0:85b3fd62ea1a 10469 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 10470 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
NYX 0:85b3fd62ea1a 10471 #define RCC_APB1RSTR_CECRST_Pos (27U)
NYX 0:85b3fd62ea1a 10472 #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 10473 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
NYX 0:85b3fd62ea1a 10474 #define RCC_APB1RSTR_PWRRST_Pos (28U)
NYX 0:85b3fd62ea1a 10475 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 10476 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
NYX 0:85b3fd62ea1a 10477 #define RCC_APB1RSTR_DACRST_Pos (29U)
NYX 0:85b3fd62ea1a 10478 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10479 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
NYX 0:85b3fd62ea1a 10480
NYX 0:85b3fd62ea1a 10481 /******************** Bit definition for RCC_APB2RSTR register **************/
NYX 0:85b3fd62ea1a 10482 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
NYX 0:85b3fd62ea1a 10483 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10484 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
NYX 0:85b3fd62ea1a 10485 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
NYX 0:85b3fd62ea1a 10486 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10487 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
NYX 0:85b3fd62ea1a 10488 #define RCC_APB2RSTR_USART1RST_Pos (4U)
NYX 0:85b3fd62ea1a 10489 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10490 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
NYX 0:85b3fd62ea1a 10491 #define RCC_APB2RSTR_USART6RST_Pos (5U)
NYX 0:85b3fd62ea1a 10492 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10493 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
NYX 0:85b3fd62ea1a 10494 #define RCC_APB2RSTR_ADCRST_Pos (8U)
NYX 0:85b3fd62ea1a 10495 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10496 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
NYX 0:85b3fd62ea1a 10497 #define RCC_APB2RSTR_SDIORST_Pos (11U)
NYX 0:85b3fd62ea1a 10498 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10499 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
NYX 0:85b3fd62ea1a 10500 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
NYX 0:85b3fd62ea1a 10501 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10502 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
NYX 0:85b3fd62ea1a 10503 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
NYX 0:85b3fd62ea1a 10504 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 10505 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
NYX 0:85b3fd62ea1a 10506 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
NYX 0:85b3fd62ea1a 10507 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10508 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
NYX 0:85b3fd62ea1a 10509 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
NYX 0:85b3fd62ea1a 10510 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10511 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
NYX 0:85b3fd62ea1a 10512 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
NYX 0:85b3fd62ea1a 10513 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10514 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
NYX 0:85b3fd62ea1a 10515 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
NYX 0:85b3fd62ea1a 10516 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10517 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
NYX 0:85b3fd62ea1a 10518 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
NYX 0:85b3fd62ea1a 10519 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10520 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
NYX 0:85b3fd62ea1a 10521 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
NYX 0:85b3fd62ea1a 10522 #define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 10523 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
NYX 0:85b3fd62ea1a 10524
NYX 0:85b3fd62ea1a 10525 /* Old SPI1RST bit definition, maintained for legacy purpose */
NYX 0:85b3fd62ea1a 10526 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
NYX 0:85b3fd62ea1a 10527
NYX 0:85b3fd62ea1a 10528 /******************** Bit definition for RCC_AHB1ENR register ***************/
NYX 0:85b3fd62ea1a 10529 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
NYX 0:85b3fd62ea1a 10530 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10531 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
NYX 0:85b3fd62ea1a 10532 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
NYX 0:85b3fd62ea1a 10533 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10534 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
NYX 0:85b3fd62ea1a 10535 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
NYX 0:85b3fd62ea1a 10536 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10537 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
NYX 0:85b3fd62ea1a 10538 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
NYX 0:85b3fd62ea1a 10539 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10540 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
NYX 0:85b3fd62ea1a 10541 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
NYX 0:85b3fd62ea1a 10542 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10543 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
NYX 0:85b3fd62ea1a 10544 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
NYX 0:85b3fd62ea1a 10545 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10546 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
NYX 0:85b3fd62ea1a 10547 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
NYX 0:85b3fd62ea1a 10548 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10549 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
NYX 0:85b3fd62ea1a 10550 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
NYX 0:85b3fd62ea1a 10551 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10552 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
NYX 0:85b3fd62ea1a 10553 #define RCC_AHB1ENR_CRCEN_Pos (12U)
NYX 0:85b3fd62ea1a 10554 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10555 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
NYX 0:85b3fd62ea1a 10556 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
NYX 0:85b3fd62ea1a 10557 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10558 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
NYX 0:85b3fd62ea1a 10559 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
NYX 0:85b3fd62ea1a 10560 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 10561 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
NYX 0:85b3fd62ea1a 10562 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
NYX 0:85b3fd62ea1a 10563 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10564 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
NYX 0:85b3fd62ea1a 10565 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
NYX 0:85b3fd62ea1a 10566 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10567 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
NYX 0:85b3fd62ea1a 10568 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
NYX 0:85b3fd62ea1a 10569 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 10570 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
NYX 0:85b3fd62ea1a 10571 /******************** Bit definition for RCC_AHB2ENR register ***************/
NYX 0:85b3fd62ea1a 10572 /*
NYX 0:85b3fd62ea1a 10573 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
NYX 0:85b3fd62ea1a 10574 */
NYX 0:85b3fd62ea1a 10575 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
NYX 0:85b3fd62ea1a 10576
NYX 0:85b3fd62ea1a 10577 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
NYX 0:85b3fd62ea1a 10578 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10579 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
NYX 0:85b3fd62ea1a 10580 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
NYX 0:85b3fd62ea1a 10581 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10582 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
NYX 0:85b3fd62ea1a 10583
NYX 0:85b3fd62ea1a 10584 /******************** Bit definition for RCC_AHB3ENR register ***************/
NYX 0:85b3fd62ea1a 10585 /*
NYX 0:85b3fd62ea1a 10586 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
NYX 0:85b3fd62ea1a 10587 */
NYX 0:85b3fd62ea1a 10588 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
NYX 0:85b3fd62ea1a 10589
NYX 0:85b3fd62ea1a 10590 #define RCC_AHB3ENR_FMCEN_Pos (0U)
NYX 0:85b3fd62ea1a 10591 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10592 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
NYX 0:85b3fd62ea1a 10593 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
NYX 0:85b3fd62ea1a 10594 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10595 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
NYX 0:85b3fd62ea1a 10596
NYX 0:85b3fd62ea1a 10597 /******************** Bit definition for RCC_APB1ENR register ***************/
NYX 0:85b3fd62ea1a 10598 #define RCC_APB1ENR_TIM2EN_Pos (0U)
NYX 0:85b3fd62ea1a 10599 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10600 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
NYX 0:85b3fd62ea1a 10601 #define RCC_APB1ENR_TIM3EN_Pos (1U)
NYX 0:85b3fd62ea1a 10602 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10603 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
NYX 0:85b3fd62ea1a 10604 #define RCC_APB1ENR_TIM4EN_Pos (2U)
NYX 0:85b3fd62ea1a 10605 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10606 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
NYX 0:85b3fd62ea1a 10607 #define RCC_APB1ENR_TIM5EN_Pos (3U)
NYX 0:85b3fd62ea1a 10608 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10609 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
NYX 0:85b3fd62ea1a 10610 #define RCC_APB1ENR_TIM6EN_Pos (4U)
NYX 0:85b3fd62ea1a 10611 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10612 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
NYX 0:85b3fd62ea1a 10613 #define RCC_APB1ENR_TIM7EN_Pos (5U)
NYX 0:85b3fd62ea1a 10614 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10615 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
NYX 0:85b3fd62ea1a 10616 #define RCC_APB1ENR_TIM12EN_Pos (6U)
NYX 0:85b3fd62ea1a 10617 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10618 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
NYX 0:85b3fd62ea1a 10619 #define RCC_APB1ENR_TIM13EN_Pos (7U)
NYX 0:85b3fd62ea1a 10620 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10621 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
NYX 0:85b3fd62ea1a 10622 #define RCC_APB1ENR_TIM14EN_Pos (8U)
NYX 0:85b3fd62ea1a 10623 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10624 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
NYX 0:85b3fd62ea1a 10625 #define RCC_APB1ENR_WWDGEN_Pos (11U)
NYX 0:85b3fd62ea1a 10626 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10627 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
NYX 0:85b3fd62ea1a 10628 #define RCC_APB1ENR_SPI2EN_Pos (14U)
NYX 0:85b3fd62ea1a 10629 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10630 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
NYX 0:85b3fd62ea1a 10631 #define RCC_APB1ENR_SPI3EN_Pos (15U)
NYX 0:85b3fd62ea1a 10632 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 10633 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
NYX 0:85b3fd62ea1a 10634 #define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
NYX 0:85b3fd62ea1a 10635 #define RCC_APB1ENR_SPDIFRXEN_Msk (0x1U << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10636 #define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
NYX 0:85b3fd62ea1a 10637 #define RCC_APB1ENR_USART2EN_Pos (17U)
NYX 0:85b3fd62ea1a 10638 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10639 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
NYX 0:85b3fd62ea1a 10640 #define RCC_APB1ENR_USART3EN_Pos (18U)
NYX 0:85b3fd62ea1a 10641 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10642 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
NYX 0:85b3fd62ea1a 10643 #define RCC_APB1ENR_UART4EN_Pos (19U)
NYX 0:85b3fd62ea1a 10644 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 10645 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
NYX 0:85b3fd62ea1a 10646 #define RCC_APB1ENR_UART5EN_Pos (20U)
NYX 0:85b3fd62ea1a 10647 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 10648 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
NYX 0:85b3fd62ea1a 10649 #define RCC_APB1ENR_I2C1EN_Pos (21U)
NYX 0:85b3fd62ea1a 10650 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 10651 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
NYX 0:85b3fd62ea1a 10652 #define RCC_APB1ENR_I2C2EN_Pos (22U)
NYX 0:85b3fd62ea1a 10653 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10654 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
NYX 0:85b3fd62ea1a 10655 #define RCC_APB1ENR_I2C3EN_Pos (23U)
NYX 0:85b3fd62ea1a 10656 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 10657 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
NYX 0:85b3fd62ea1a 10658 #define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
NYX 0:85b3fd62ea1a 10659 #define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 10660 #define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
NYX 0:85b3fd62ea1a 10661 #define RCC_APB1ENR_CAN1EN_Pos (25U)
NYX 0:85b3fd62ea1a 10662 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 10663 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
NYX 0:85b3fd62ea1a 10664 #define RCC_APB1ENR_CAN2EN_Pos (26U)
NYX 0:85b3fd62ea1a 10665 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 10666 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
NYX 0:85b3fd62ea1a 10667 #define RCC_APB1ENR_CECEN_Pos (27U)
NYX 0:85b3fd62ea1a 10668 #define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 10669 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
NYX 0:85b3fd62ea1a 10670 #define RCC_APB1ENR_PWREN_Pos (28U)
NYX 0:85b3fd62ea1a 10671 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 10672 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
NYX 0:85b3fd62ea1a 10673 #define RCC_APB1ENR_DACEN_Pos (29U)
NYX 0:85b3fd62ea1a 10674 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10675 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
NYX 0:85b3fd62ea1a 10676
NYX 0:85b3fd62ea1a 10677 /******************** Bit definition for RCC_APB2ENR register ***************/
NYX 0:85b3fd62ea1a 10678 #define RCC_APB2ENR_TIM1EN_Pos (0U)
NYX 0:85b3fd62ea1a 10679 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10680 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
NYX 0:85b3fd62ea1a 10681 #define RCC_APB2ENR_TIM8EN_Pos (1U)
NYX 0:85b3fd62ea1a 10682 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10683 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
NYX 0:85b3fd62ea1a 10684 #define RCC_APB2ENR_USART1EN_Pos (4U)
NYX 0:85b3fd62ea1a 10685 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10686 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
NYX 0:85b3fd62ea1a 10687 #define RCC_APB2ENR_USART6EN_Pos (5U)
NYX 0:85b3fd62ea1a 10688 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10689 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
NYX 0:85b3fd62ea1a 10690 #define RCC_APB2ENR_ADC1EN_Pos (8U)
NYX 0:85b3fd62ea1a 10691 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10692 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
NYX 0:85b3fd62ea1a 10693 #define RCC_APB2ENR_ADC2EN_Pos (9U)
NYX 0:85b3fd62ea1a 10694 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 10695 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
NYX 0:85b3fd62ea1a 10696 #define RCC_APB2ENR_ADC3EN_Pos (10U)
NYX 0:85b3fd62ea1a 10697 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 10698 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
NYX 0:85b3fd62ea1a 10699 #define RCC_APB2ENR_SDIOEN_Pos (11U)
NYX 0:85b3fd62ea1a 10700 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10701 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
NYX 0:85b3fd62ea1a 10702 #define RCC_APB2ENR_SPI1EN_Pos (12U)
NYX 0:85b3fd62ea1a 10703 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10704 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
NYX 0:85b3fd62ea1a 10705 #define RCC_APB2ENR_SPI4EN_Pos (13U)
NYX 0:85b3fd62ea1a 10706 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 10707 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
NYX 0:85b3fd62ea1a 10708 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
NYX 0:85b3fd62ea1a 10709 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10710 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
NYX 0:85b3fd62ea1a 10711 #define RCC_APB2ENR_TIM9EN_Pos (16U)
NYX 0:85b3fd62ea1a 10712 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10713 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
NYX 0:85b3fd62ea1a 10714 #define RCC_APB2ENR_TIM10EN_Pos (17U)
NYX 0:85b3fd62ea1a 10715 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10716 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
NYX 0:85b3fd62ea1a 10717 #define RCC_APB2ENR_TIM11EN_Pos (18U)
NYX 0:85b3fd62ea1a 10718 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10719 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
NYX 0:85b3fd62ea1a 10720 #define RCC_APB2ENR_SAI1EN_Pos (22U)
NYX 0:85b3fd62ea1a 10721 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10722 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
NYX 0:85b3fd62ea1a 10723 #define RCC_APB2ENR_SAI2EN_Pos (23U)
NYX 0:85b3fd62ea1a 10724 #define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 10725 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
NYX 0:85b3fd62ea1a 10726
NYX 0:85b3fd62ea1a 10727 /******************** Bit definition for RCC_AHB1LPENR register *************/
NYX 0:85b3fd62ea1a 10728 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
NYX 0:85b3fd62ea1a 10729 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10730 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
NYX 0:85b3fd62ea1a 10731 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
NYX 0:85b3fd62ea1a 10732 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10733 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
NYX 0:85b3fd62ea1a 10734 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
NYX 0:85b3fd62ea1a 10735 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10736 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
NYX 0:85b3fd62ea1a 10737 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
NYX 0:85b3fd62ea1a 10738 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10739 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
NYX 0:85b3fd62ea1a 10740 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
NYX 0:85b3fd62ea1a 10741 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10742 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
NYX 0:85b3fd62ea1a 10743 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
NYX 0:85b3fd62ea1a 10744 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10745 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
NYX 0:85b3fd62ea1a 10746 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
NYX 0:85b3fd62ea1a 10747 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10748 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
NYX 0:85b3fd62ea1a 10749 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
NYX 0:85b3fd62ea1a 10750 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10751 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
NYX 0:85b3fd62ea1a 10752 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
NYX 0:85b3fd62ea1a 10753 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10754 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
NYX 0:85b3fd62ea1a 10755 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
NYX 0:85b3fd62ea1a 10756 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 10757 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
NYX 0:85b3fd62ea1a 10758 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
NYX 0:85b3fd62ea1a 10759 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10760 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
NYX 0:85b3fd62ea1a 10761 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
NYX 0:85b3fd62ea1a 10762 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10763 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
NYX 0:85b3fd62ea1a 10764 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
NYX 0:85b3fd62ea1a 10765 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10766 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
NYX 0:85b3fd62ea1a 10767 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
NYX 0:85b3fd62ea1a 10768 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 10769 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
NYX 0:85b3fd62ea1a 10770 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
NYX 0:85b3fd62ea1a 10771 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10772 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
NYX 0:85b3fd62ea1a 10773
NYX 0:85b3fd62ea1a 10774 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
NYX 0:85b3fd62ea1a 10775 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10776 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
NYX 0:85b3fd62ea1a 10777 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
NYX 0:85b3fd62ea1a 10778 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 10779 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
NYX 0:85b3fd62ea1a 10780
NYX 0:85b3fd62ea1a 10781 /******************** Bit definition for RCC_AHB2LPENR register *************/
NYX 0:85b3fd62ea1a 10782 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
NYX 0:85b3fd62ea1a 10783 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10784 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
NYX 0:85b3fd62ea1a 10785 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
NYX 0:85b3fd62ea1a 10786 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10787 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
NYX 0:85b3fd62ea1a 10788
NYX 0:85b3fd62ea1a 10789 /******************** Bit definition for RCC_AHB3LPENR register *************/
NYX 0:85b3fd62ea1a 10790 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
NYX 0:85b3fd62ea1a 10791 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10792 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
NYX 0:85b3fd62ea1a 10793 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
NYX 0:85b3fd62ea1a 10794 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10795 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
NYX 0:85b3fd62ea1a 10796
NYX 0:85b3fd62ea1a 10797 /******************** Bit definition for RCC_APB1LPENR register *************/
NYX 0:85b3fd62ea1a 10798 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
NYX 0:85b3fd62ea1a 10799 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10800 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
NYX 0:85b3fd62ea1a 10801 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
NYX 0:85b3fd62ea1a 10802 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10803 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
NYX 0:85b3fd62ea1a 10804 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
NYX 0:85b3fd62ea1a 10805 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10806 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
NYX 0:85b3fd62ea1a 10807 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
NYX 0:85b3fd62ea1a 10808 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10809 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
NYX 0:85b3fd62ea1a 10810 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
NYX 0:85b3fd62ea1a 10811 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10812 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
NYX 0:85b3fd62ea1a 10813 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
NYX 0:85b3fd62ea1a 10814 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10815 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
NYX 0:85b3fd62ea1a 10816 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
NYX 0:85b3fd62ea1a 10817 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 10818 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
NYX 0:85b3fd62ea1a 10819 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
NYX 0:85b3fd62ea1a 10820 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 10821 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
NYX 0:85b3fd62ea1a 10822 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
NYX 0:85b3fd62ea1a 10823 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10824 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
NYX 0:85b3fd62ea1a 10825 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
NYX 0:85b3fd62ea1a 10826 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10827 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
NYX 0:85b3fd62ea1a 10828 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
NYX 0:85b3fd62ea1a 10829 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10830 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
NYX 0:85b3fd62ea1a 10831 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
NYX 0:85b3fd62ea1a 10832 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 10833 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
NYX 0:85b3fd62ea1a 10834 #define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
NYX 0:85b3fd62ea1a 10835 #define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1U << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10836 #define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
NYX 0:85b3fd62ea1a 10837 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
NYX 0:85b3fd62ea1a 10838 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10839 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
NYX 0:85b3fd62ea1a 10840 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
NYX 0:85b3fd62ea1a 10841 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10842 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
NYX 0:85b3fd62ea1a 10843 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
NYX 0:85b3fd62ea1a 10844 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 10845 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
NYX 0:85b3fd62ea1a 10846 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
NYX 0:85b3fd62ea1a 10847 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 10848 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
NYX 0:85b3fd62ea1a 10849 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
NYX 0:85b3fd62ea1a 10850 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 10851 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
NYX 0:85b3fd62ea1a 10852 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
NYX 0:85b3fd62ea1a 10853 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10854 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
NYX 0:85b3fd62ea1a 10855 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
NYX 0:85b3fd62ea1a 10856 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 10857 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
NYX 0:85b3fd62ea1a 10858 #define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
NYX 0:85b3fd62ea1a 10859 #define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 10860 #define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
NYX 0:85b3fd62ea1a 10861 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
NYX 0:85b3fd62ea1a 10862 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 10863 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
NYX 0:85b3fd62ea1a 10864 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
NYX 0:85b3fd62ea1a 10865 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 10866 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
NYX 0:85b3fd62ea1a 10867 #define RCC_APB1LPENR_CECLPEN_Pos (27U)
NYX 0:85b3fd62ea1a 10868 #define RCC_APB1LPENR_CECLPEN_Msk (0x1U << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 10869 #define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
NYX 0:85b3fd62ea1a 10870 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
NYX 0:85b3fd62ea1a 10871 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 10872 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
NYX 0:85b3fd62ea1a 10873 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
NYX 0:85b3fd62ea1a 10874 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10875 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
NYX 0:85b3fd62ea1a 10876
NYX 0:85b3fd62ea1a 10877 /******************** Bit definition for RCC_APB2LPENR register *************/
NYX 0:85b3fd62ea1a 10878 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
NYX 0:85b3fd62ea1a 10879 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10880 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
NYX 0:85b3fd62ea1a 10881 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
NYX 0:85b3fd62ea1a 10882 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10883 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
NYX 0:85b3fd62ea1a 10884 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
NYX 0:85b3fd62ea1a 10885 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 10886 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
NYX 0:85b3fd62ea1a 10887 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
NYX 0:85b3fd62ea1a 10888 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 10889 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
NYX 0:85b3fd62ea1a 10890 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
NYX 0:85b3fd62ea1a 10891 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10892 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
NYX 0:85b3fd62ea1a 10893 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
NYX 0:85b3fd62ea1a 10894 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 10895 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
NYX 0:85b3fd62ea1a 10896 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
NYX 0:85b3fd62ea1a 10897 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 10898 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
NYX 0:85b3fd62ea1a 10899 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
NYX 0:85b3fd62ea1a 10900 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 10901 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
NYX 0:85b3fd62ea1a 10902 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
NYX 0:85b3fd62ea1a 10903 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 10904 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
NYX 0:85b3fd62ea1a 10905 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
NYX 0:85b3fd62ea1a 10906 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 10907 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
NYX 0:85b3fd62ea1a 10908 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
NYX 0:85b3fd62ea1a 10909 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 10910 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
NYX 0:85b3fd62ea1a 10911 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
NYX 0:85b3fd62ea1a 10912 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10913 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
NYX 0:85b3fd62ea1a 10914 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
NYX 0:85b3fd62ea1a 10915 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 10916 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
NYX 0:85b3fd62ea1a 10917 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
NYX 0:85b3fd62ea1a 10918 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 10919 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
NYX 0:85b3fd62ea1a 10920 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
NYX 0:85b3fd62ea1a 10921 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 10922 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
NYX 0:85b3fd62ea1a 10923 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
NYX 0:85b3fd62ea1a 10924 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1U << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 10925 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
NYX 0:85b3fd62ea1a 10926
NYX 0:85b3fd62ea1a 10927 /******************** Bit definition for RCC_BDCR register ******************/
NYX 0:85b3fd62ea1a 10928 #define RCC_BDCR_LSEON_Pos (0U)
NYX 0:85b3fd62ea1a 10929 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10930 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
NYX 0:85b3fd62ea1a 10931 #define RCC_BDCR_LSERDY_Pos (1U)
NYX 0:85b3fd62ea1a 10932 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10933 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
NYX 0:85b3fd62ea1a 10934 #define RCC_BDCR_LSEBYP_Pos (2U)
NYX 0:85b3fd62ea1a 10935 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 10936 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
NYX 0:85b3fd62ea1a 10937 #define RCC_BDCR_LSEMOD_Pos (3U)
NYX 0:85b3fd62ea1a 10938 #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 10939 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
NYX 0:85b3fd62ea1a 10940
NYX 0:85b3fd62ea1a 10941 #define RCC_BDCR_RTCSEL_Pos (8U)
NYX 0:85b3fd62ea1a 10942 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 10943 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
NYX 0:85b3fd62ea1a 10944 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 10945 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 10946
NYX 0:85b3fd62ea1a 10947 #define RCC_BDCR_RTCEN_Pos (15U)
NYX 0:85b3fd62ea1a 10948 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 10949 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
NYX 0:85b3fd62ea1a 10950 #define RCC_BDCR_BDRST_Pos (16U)
NYX 0:85b3fd62ea1a 10951 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 10952 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
NYX 0:85b3fd62ea1a 10953
NYX 0:85b3fd62ea1a 10954 /******************** Bit definition for RCC_CSR register *******************/
NYX 0:85b3fd62ea1a 10955 #define RCC_CSR_LSION_Pos (0U)
NYX 0:85b3fd62ea1a 10956 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 10957 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
NYX 0:85b3fd62ea1a 10958 #define RCC_CSR_LSIRDY_Pos (1U)
NYX 0:85b3fd62ea1a 10959 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 10960 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
NYX 0:85b3fd62ea1a 10961 #define RCC_CSR_RMVF_Pos (24U)
NYX 0:85b3fd62ea1a 10962 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 10963 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
NYX 0:85b3fd62ea1a 10964 #define RCC_CSR_BORRSTF_Pos (25U)
NYX 0:85b3fd62ea1a 10965 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 10966 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
NYX 0:85b3fd62ea1a 10967 #define RCC_CSR_PINRSTF_Pos (26U)
NYX 0:85b3fd62ea1a 10968 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 10969 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
NYX 0:85b3fd62ea1a 10970 #define RCC_CSR_PORRSTF_Pos (27U)
NYX 0:85b3fd62ea1a 10971 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 10972 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
NYX 0:85b3fd62ea1a 10973 #define RCC_CSR_SFTRSTF_Pos (28U)
NYX 0:85b3fd62ea1a 10974 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 10975 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
NYX 0:85b3fd62ea1a 10976 #define RCC_CSR_IWDGRSTF_Pos (29U)
NYX 0:85b3fd62ea1a 10977 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 10978 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
NYX 0:85b3fd62ea1a 10979 #define RCC_CSR_WWDGRSTF_Pos (30U)
NYX 0:85b3fd62ea1a 10980 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 10981 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
NYX 0:85b3fd62ea1a 10982 #define RCC_CSR_LPWRRSTF_Pos (31U)
NYX 0:85b3fd62ea1a 10983 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 10984 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
NYX 0:85b3fd62ea1a 10985 /* Legacy defines */
NYX 0:85b3fd62ea1a 10986 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
NYX 0:85b3fd62ea1a 10987 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
NYX 0:85b3fd62ea1a 10988
NYX 0:85b3fd62ea1a 10989 /******************** Bit definition for RCC_SSCGR register *****************/
NYX 0:85b3fd62ea1a 10990 #define RCC_SSCGR_MODPER_Pos (0U)
NYX 0:85b3fd62ea1a 10991 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
NYX 0:85b3fd62ea1a 10992 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
NYX 0:85b3fd62ea1a 10993 #define RCC_SSCGR_INCSTEP_Pos (13U)
NYX 0:85b3fd62ea1a 10994 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
NYX 0:85b3fd62ea1a 10995 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
NYX 0:85b3fd62ea1a 10996 #define RCC_SSCGR_SPREADSEL_Pos (30U)
NYX 0:85b3fd62ea1a 10997 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 10998 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
NYX 0:85b3fd62ea1a 10999 #define RCC_SSCGR_SSCGEN_Pos (31U)
NYX 0:85b3fd62ea1a 11000 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 11001 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
NYX 0:85b3fd62ea1a 11002
NYX 0:85b3fd62ea1a 11003 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
NYX 0:85b3fd62ea1a 11004 #define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
NYX 0:85b3fd62ea1a 11005 #define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
NYX 0:85b3fd62ea1a 11006 #define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
NYX 0:85b3fd62ea1a 11007 #define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11008 #define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11009 #define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11010 #define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11011 #define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11012 #define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11013
NYX 0:85b3fd62ea1a 11014 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
NYX 0:85b3fd62ea1a 11015 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
NYX 0:85b3fd62ea1a 11016 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
NYX 0:85b3fd62ea1a 11017 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11018 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11019 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11020 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11021 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11022 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11023 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11024 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11025 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11026
NYX 0:85b3fd62ea1a 11027 #define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
NYX 0:85b3fd62ea1a 11028 #define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 11029 #define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
NYX 0:85b3fd62ea1a 11030 #define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11031 #define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11032 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
NYX 0:85b3fd62ea1a 11033 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 11034 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
NYX 0:85b3fd62ea1a 11035 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 11036 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 11037 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 11038 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 11039 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
NYX 0:85b3fd62ea1a 11040 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
NYX 0:85b3fd62ea1a 11041 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
NYX 0:85b3fd62ea1a 11042 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 11043 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 11044 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 11045
NYX 0:85b3fd62ea1a 11046 /******************** Bit definition for RCC_PLLSAICFGR register ************/
NYX 0:85b3fd62ea1a 11047 #define RCC_PLLSAICFGR_PLLSAIM_Pos (0U)
NYX 0:85b3fd62ea1a 11048 #define RCC_PLLSAICFGR_PLLSAIM_Msk (0x3FU << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x0000003F */
NYX 0:85b3fd62ea1a 11049 #define RCC_PLLSAICFGR_PLLSAIM RCC_PLLSAICFGR_PLLSAIM_Msk
NYX 0:85b3fd62ea1a 11050 #define RCC_PLLSAICFGR_PLLSAIM_0 (0x01U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11051 #define RCC_PLLSAICFGR_PLLSAIM_1 (0x02U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11052 #define RCC_PLLSAICFGR_PLLSAIM_2 (0x04U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11053 #define RCC_PLLSAICFGR_PLLSAIM_3 (0x08U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11054 #define RCC_PLLSAICFGR_PLLSAIM_4 (0x10U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11055 #define RCC_PLLSAICFGR_PLLSAIM_5 (0x20U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11056 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
NYX 0:85b3fd62ea1a 11057 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
NYX 0:85b3fd62ea1a 11058 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
NYX 0:85b3fd62ea1a 11059 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11060 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11061 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11062 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11063 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11064 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11065 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11066 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11067 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11068
NYX 0:85b3fd62ea1a 11069 #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
NYX 0:85b3fd62ea1a 11070 #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
NYX 0:85b3fd62ea1a 11071 #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
NYX 0:85b3fd62ea1a 11072 #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11073 #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11074
NYX 0:85b3fd62ea1a 11075 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
NYX 0:85b3fd62ea1a 11076 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 11077 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
NYX 0:85b3fd62ea1a 11078 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 11079 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 11080 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 11081 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 11082
NYX 0:85b3fd62ea1a 11083
NYX 0:85b3fd62ea1a 11084 /******************** Bit definition for RCC_DCKCFGR register ***************/
NYX 0:85b3fd62ea1a 11085 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
NYX 0:85b3fd62ea1a 11086 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 11087 #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
NYX 0:85b3fd62ea1a 11088 #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11089 #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11090 #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11091 #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11092 #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11093
NYX 0:85b3fd62ea1a 11094 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
NYX 0:85b3fd62ea1a 11095 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
NYX 0:85b3fd62ea1a 11096 #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
NYX 0:85b3fd62ea1a 11097 #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11098 #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11099 #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11100 #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11101 #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11102 #define RCC_DCKCFGR_SAI1SRC_Pos (20U)
NYX 0:85b3fd62ea1a 11103 #define RCC_DCKCFGR_SAI1SRC_Msk (0x3U << RCC_DCKCFGR_SAI1SRC_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 11104 #define RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_Msk
NYX 0:85b3fd62ea1a 11105 #define RCC_DCKCFGR_SAI1SRC_0 (0x1U << RCC_DCKCFGR_SAI1SRC_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 11106 #define RCC_DCKCFGR_SAI1SRC_1 (0x2U << RCC_DCKCFGR_SAI1SRC_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 11107 #define RCC_DCKCFGR_SAI2SRC_Pos (22U)
NYX 0:85b3fd62ea1a 11108 #define RCC_DCKCFGR_SAI2SRC_Msk (0x3U << RCC_DCKCFGR_SAI2SRC_Pos) /*!< 0x00C00000 */
NYX 0:85b3fd62ea1a 11109 #define RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_Msk
NYX 0:85b3fd62ea1a 11110 #define RCC_DCKCFGR_SAI2SRC_0 (0x1U << RCC_DCKCFGR_SAI2SRC_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 11111 #define RCC_DCKCFGR_SAI2SRC_1 (0x2U << RCC_DCKCFGR_SAI2SRC_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 11112
NYX 0:85b3fd62ea1a 11113 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
NYX 0:85b3fd62ea1a 11114 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 11115 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
NYX 0:85b3fd62ea1a 11116 #define RCC_DCKCFGR_I2S1SRC_Pos (25U)
NYX 0:85b3fd62ea1a 11117 #define RCC_DCKCFGR_I2S1SRC_Msk (0x3U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x06000000 */
NYX 0:85b3fd62ea1a 11118 #define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
NYX 0:85b3fd62ea1a 11119 #define RCC_DCKCFGR_I2S1SRC_0 (0x1U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 11120 #define RCC_DCKCFGR_I2S1SRC_1 (0x2U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 11121
NYX 0:85b3fd62ea1a 11122 #define RCC_DCKCFGR_I2S2SRC_Pos (27U)
NYX 0:85b3fd62ea1a 11123 #define RCC_DCKCFGR_I2S2SRC_Msk (0x3U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x18000000 */
NYX 0:85b3fd62ea1a 11124 #define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
NYX 0:85b3fd62ea1a 11125 #define RCC_DCKCFGR_I2S2SRC_0 (0x1U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 11126 #define RCC_DCKCFGR_I2S2SRC_1 (0x2U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 11127
NYX 0:85b3fd62ea1a 11128 /******************** Bit definition for RCC_CKGATENR register ***************/
NYX 0:85b3fd62ea1a 11129 #define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
NYX 0:85b3fd62ea1a 11130 #define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11131 #define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
NYX 0:85b3fd62ea1a 11132 #define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
NYX 0:85b3fd62ea1a 11133 #define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11134 #define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
NYX 0:85b3fd62ea1a 11135 #define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
NYX 0:85b3fd62ea1a 11136 #define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1U << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11137 #define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
NYX 0:85b3fd62ea1a 11138 #define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
NYX 0:85b3fd62ea1a 11139 #define RCC_CKGATENR_SPARE_CKEN_Msk (0x1U << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11140 #define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
NYX 0:85b3fd62ea1a 11141 #define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
NYX 0:85b3fd62ea1a 11142 #define RCC_CKGATENR_SRAM_CKEN_Msk (0x1U << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11143 #define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
NYX 0:85b3fd62ea1a 11144 #define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
NYX 0:85b3fd62ea1a 11145 #define RCC_CKGATENR_FLITF_CKEN_Msk (0x1U << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11146 #define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
NYX 0:85b3fd62ea1a 11147 #define RCC_CKGATENR_RCC_CKEN_Pos (6U)
NYX 0:85b3fd62ea1a 11148 #define RCC_CKGATENR_RCC_CKEN_Msk (0x1U << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11149 #define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
NYX 0:85b3fd62ea1a 11150
NYX 0:85b3fd62ea1a 11151 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
NYX 0:85b3fd62ea1a 11152 #define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
NYX 0:85b3fd62ea1a 11153 #define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
NYX 0:85b3fd62ea1a 11154 #define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
NYX 0:85b3fd62ea1a 11155 #define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 11156 #define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 11157 #define RCC_DCKCFGR2_CECSEL_Pos (26U)
NYX 0:85b3fd62ea1a 11158 #define RCC_DCKCFGR2_CECSEL_Msk (0x1U << RCC_DCKCFGR2_CECSEL_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 11159 #define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
NYX 0:85b3fd62ea1a 11160 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
NYX 0:85b3fd62ea1a 11161 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 11162 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
NYX 0:85b3fd62ea1a 11163 #define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
NYX 0:85b3fd62ea1a 11164 #define RCC_DCKCFGR2_SDIOSEL_Msk (0x1U << RCC_DCKCFGR2_SDIOSEL_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 11165 #define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
NYX 0:85b3fd62ea1a 11166 #define RCC_DCKCFGR2_SPDIFRXSEL_Pos (29U)
NYX 0:85b3fd62ea1a 11167 #define RCC_DCKCFGR2_SPDIFRXSEL_Msk (0x1U << RCC_DCKCFGR2_SPDIFRXSEL_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 11168 #define RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_Msk
NYX 0:85b3fd62ea1a 11169
NYX 0:85b3fd62ea1a 11170
NYX 0:85b3fd62ea1a 11171 /******************************************************************************/
NYX 0:85b3fd62ea1a 11172 /* */
NYX 0:85b3fd62ea1a 11173 /* Real-Time Clock (RTC) */
NYX 0:85b3fd62ea1a 11174 /* */
NYX 0:85b3fd62ea1a 11175 /******************************************************************************/
NYX 0:85b3fd62ea1a 11176 /*
NYX 0:85b3fd62ea1a 11177 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
NYX 0:85b3fd62ea1a 11178 */
NYX 0:85b3fd62ea1a 11179 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
NYX 0:85b3fd62ea1a 11180 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
NYX 0:85b3fd62ea1a 11181 /******************** Bits definition for RTC_TR register *******************/
NYX 0:85b3fd62ea1a 11182 #define RTC_TR_PM_Pos (22U)
NYX 0:85b3fd62ea1a 11183 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 11184 #define RTC_TR_PM RTC_TR_PM_Msk
NYX 0:85b3fd62ea1a 11185 #define RTC_TR_HT_Pos (20U)
NYX 0:85b3fd62ea1a 11186 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 11187 #define RTC_TR_HT RTC_TR_HT_Msk
NYX 0:85b3fd62ea1a 11188 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 11189 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 11190 #define RTC_TR_HU_Pos (16U)
NYX 0:85b3fd62ea1a 11191 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 11192 #define RTC_TR_HU RTC_TR_HU_Msk
NYX 0:85b3fd62ea1a 11193 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11194 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11195 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 11196 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 11197 #define RTC_TR_MNT_Pos (12U)
NYX 0:85b3fd62ea1a 11198 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
NYX 0:85b3fd62ea1a 11199 #define RTC_TR_MNT RTC_TR_MNT_Msk
NYX 0:85b3fd62ea1a 11200 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11201 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11202 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11203 #define RTC_TR_MNU_Pos (8U)
NYX 0:85b3fd62ea1a 11204 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 11205 #define RTC_TR_MNU RTC_TR_MNU_Msk
NYX 0:85b3fd62ea1a 11206 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11207 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11208 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11209 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11210 #define RTC_TR_ST_Pos (4U)
NYX 0:85b3fd62ea1a 11211 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 11212 #define RTC_TR_ST RTC_TR_ST_Msk
NYX 0:85b3fd62ea1a 11213 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11214 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11215 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11216 #define RTC_TR_SU_Pos (0U)
NYX 0:85b3fd62ea1a 11217 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 11218 #define RTC_TR_SU RTC_TR_SU_Msk
NYX 0:85b3fd62ea1a 11219 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11220 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11221 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11222 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11223
NYX 0:85b3fd62ea1a 11224 /******************** Bits definition for RTC_DR register *******************/
NYX 0:85b3fd62ea1a 11225 #define RTC_DR_YT_Pos (20U)
NYX 0:85b3fd62ea1a 11226 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 11227 #define RTC_DR_YT RTC_DR_YT_Msk
NYX 0:85b3fd62ea1a 11228 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 11229 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 11230 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 11231 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 11232 #define RTC_DR_YU_Pos (16U)
NYX 0:85b3fd62ea1a 11233 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 11234 #define RTC_DR_YU RTC_DR_YU_Msk
NYX 0:85b3fd62ea1a 11235 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11236 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11237 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 11238 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 11239 #define RTC_DR_WDU_Pos (13U)
NYX 0:85b3fd62ea1a 11240 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
NYX 0:85b3fd62ea1a 11241 #define RTC_DR_WDU RTC_DR_WDU_Msk
NYX 0:85b3fd62ea1a 11242 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11243 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11244 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 11245 #define RTC_DR_MT_Pos (12U)
NYX 0:85b3fd62ea1a 11246 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11247 #define RTC_DR_MT RTC_DR_MT_Msk
NYX 0:85b3fd62ea1a 11248 #define RTC_DR_MU_Pos (8U)
NYX 0:85b3fd62ea1a 11249 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 11250 #define RTC_DR_MU RTC_DR_MU_Msk
NYX 0:85b3fd62ea1a 11251 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11252 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11253 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11254 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11255 #define RTC_DR_DT_Pos (4U)
NYX 0:85b3fd62ea1a 11256 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 11257 #define RTC_DR_DT RTC_DR_DT_Msk
NYX 0:85b3fd62ea1a 11258 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11259 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11260 #define RTC_DR_DU_Pos (0U)
NYX 0:85b3fd62ea1a 11261 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 11262 #define RTC_DR_DU RTC_DR_DU_Msk
NYX 0:85b3fd62ea1a 11263 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11264 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11265 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11266 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11267
NYX 0:85b3fd62ea1a 11268 /******************** Bits definition for RTC_CR register *******************/
NYX 0:85b3fd62ea1a 11269 #define RTC_CR_COE_Pos (23U)
NYX 0:85b3fd62ea1a 11270 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 11271 #define RTC_CR_COE RTC_CR_COE_Msk
NYX 0:85b3fd62ea1a 11272 #define RTC_CR_OSEL_Pos (21U)
NYX 0:85b3fd62ea1a 11273 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
NYX 0:85b3fd62ea1a 11274 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
NYX 0:85b3fd62ea1a 11275 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 11276 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 11277 #define RTC_CR_POL_Pos (20U)
NYX 0:85b3fd62ea1a 11278 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 11279 #define RTC_CR_POL RTC_CR_POL_Msk
NYX 0:85b3fd62ea1a 11280 #define RTC_CR_COSEL_Pos (19U)
NYX 0:85b3fd62ea1a 11281 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 11282 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
NYX 0:85b3fd62ea1a 11283 #define RTC_CR_BKP_Pos (18U)
NYX 0:85b3fd62ea1a 11284 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 11285 #define RTC_CR_BKP RTC_CR_BKP_Msk
NYX 0:85b3fd62ea1a 11286 #define RTC_CR_SUB1H_Pos (17U)
NYX 0:85b3fd62ea1a 11287 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11288 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
NYX 0:85b3fd62ea1a 11289 #define RTC_CR_ADD1H_Pos (16U)
NYX 0:85b3fd62ea1a 11290 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11291 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
NYX 0:85b3fd62ea1a 11292 #define RTC_CR_TSIE_Pos (15U)
NYX 0:85b3fd62ea1a 11293 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 11294 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
NYX 0:85b3fd62ea1a 11295 #define RTC_CR_WUTIE_Pos (14U)
NYX 0:85b3fd62ea1a 11296 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11297 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
NYX 0:85b3fd62ea1a 11298 #define RTC_CR_ALRBIE_Pos (13U)
NYX 0:85b3fd62ea1a 11299 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11300 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
NYX 0:85b3fd62ea1a 11301 #define RTC_CR_ALRAIE_Pos (12U)
NYX 0:85b3fd62ea1a 11302 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11303 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
NYX 0:85b3fd62ea1a 11304 #define RTC_CR_TSE_Pos (11U)
NYX 0:85b3fd62ea1a 11305 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11306 #define RTC_CR_TSE RTC_CR_TSE_Msk
NYX 0:85b3fd62ea1a 11307 #define RTC_CR_WUTE_Pos (10U)
NYX 0:85b3fd62ea1a 11308 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11309 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
NYX 0:85b3fd62ea1a 11310 #define RTC_CR_ALRBE_Pos (9U)
NYX 0:85b3fd62ea1a 11311 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11312 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
NYX 0:85b3fd62ea1a 11313 #define RTC_CR_ALRAE_Pos (8U)
NYX 0:85b3fd62ea1a 11314 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11315 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
NYX 0:85b3fd62ea1a 11316 #define RTC_CR_DCE_Pos (7U)
NYX 0:85b3fd62ea1a 11317 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11318 #define RTC_CR_DCE RTC_CR_DCE_Msk
NYX 0:85b3fd62ea1a 11319 #define RTC_CR_FMT_Pos (6U)
NYX 0:85b3fd62ea1a 11320 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11321 #define RTC_CR_FMT RTC_CR_FMT_Msk
NYX 0:85b3fd62ea1a 11322 #define RTC_CR_BYPSHAD_Pos (5U)
NYX 0:85b3fd62ea1a 11323 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11324 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
NYX 0:85b3fd62ea1a 11325 #define RTC_CR_REFCKON_Pos (4U)
NYX 0:85b3fd62ea1a 11326 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11327 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
NYX 0:85b3fd62ea1a 11328 #define RTC_CR_TSEDGE_Pos (3U)
NYX 0:85b3fd62ea1a 11329 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11330 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
NYX 0:85b3fd62ea1a 11331 #define RTC_CR_WUCKSEL_Pos (0U)
NYX 0:85b3fd62ea1a 11332 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 11333 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
NYX 0:85b3fd62ea1a 11334 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11335 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11336 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11337
NYX 0:85b3fd62ea1a 11338 /* Legacy defines */
NYX 0:85b3fd62ea1a 11339 #define RTC_CR_BCK RTC_CR_BKP
NYX 0:85b3fd62ea1a 11340
NYX 0:85b3fd62ea1a 11341 /******************** Bits definition for RTC_ISR register ******************/
NYX 0:85b3fd62ea1a 11342 #define RTC_ISR_RECALPF_Pos (16U)
NYX 0:85b3fd62ea1a 11343 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11344 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
NYX 0:85b3fd62ea1a 11345 #define RTC_ISR_TAMP1F_Pos (13U)
NYX 0:85b3fd62ea1a 11346 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11347 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
NYX 0:85b3fd62ea1a 11348 #define RTC_ISR_TAMP2F_Pos (14U)
NYX 0:85b3fd62ea1a 11349 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11350 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
NYX 0:85b3fd62ea1a 11351 #define RTC_ISR_TSOVF_Pos (12U)
NYX 0:85b3fd62ea1a 11352 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11353 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
NYX 0:85b3fd62ea1a 11354 #define RTC_ISR_TSF_Pos (11U)
NYX 0:85b3fd62ea1a 11355 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11356 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
NYX 0:85b3fd62ea1a 11357 #define RTC_ISR_WUTF_Pos (10U)
NYX 0:85b3fd62ea1a 11358 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11359 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
NYX 0:85b3fd62ea1a 11360 #define RTC_ISR_ALRBF_Pos (9U)
NYX 0:85b3fd62ea1a 11361 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11362 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
NYX 0:85b3fd62ea1a 11363 #define RTC_ISR_ALRAF_Pos (8U)
NYX 0:85b3fd62ea1a 11364 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11365 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
NYX 0:85b3fd62ea1a 11366 #define RTC_ISR_INIT_Pos (7U)
NYX 0:85b3fd62ea1a 11367 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11368 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
NYX 0:85b3fd62ea1a 11369 #define RTC_ISR_INITF_Pos (6U)
NYX 0:85b3fd62ea1a 11370 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11371 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
NYX 0:85b3fd62ea1a 11372 #define RTC_ISR_RSF_Pos (5U)
NYX 0:85b3fd62ea1a 11373 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11374 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
NYX 0:85b3fd62ea1a 11375 #define RTC_ISR_INITS_Pos (4U)
NYX 0:85b3fd62ea1a 11376 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11377 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
NYX 0:85b3fd62ea1a 11378 #define RTC_ISR_SHPF_Pos (3U)
NYX 0:85b3fd62ea1a 11379 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11380 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
NYX 0:85b3fd62ea1a 11381 #define RTC_ISR_WUTWF_Pos (2U)
NYX 0:85b3fd62ea1a 11382 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11383 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
NYX 0:85b3fd62ea1a 11384 #define RTC_ISR_ALRBWF_Pos (1U)
NYX 0:85b3fd62ea1a 11385 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11386 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
NYX 0:85b3fd62ea1a 11387 #define RTC_ISR_ALRAWF_Pos (0U)
NYX 0:85b3fd62ea1a 11388 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11389 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
NYX 0:85b3fd62ea1a 11390
NYX 0:85b3fd62ea1a 11391 /******************** Bits definition for RTC_PRER register *****************/
NYX 0:85b3fd62ea1a 11392 #define RTC_PRER_PREDIV_A_Pos (16U)
NYX 0:85b3fd62ea1a 11393 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
NYX 0:85b3fd62ea1a 11394 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
NYX 0:85b3fd62ea1a 11395 #define RTC_PRER_PREDIV_S_Pos (0U)
NYX 0:85b3fd62ea1a 11396 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
NYX 0:85b3fd62ea1a 11397 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
NYX 0:85b3fd62ea1a 11398
NYX 0:85b3fd62ea1a 11399 /******************** Bits definition for RTC_WUTR register *****************/
NYX 0:85b3fd62ea1a 11400 #define RTC_WUTR_WUT_Pos (0U)
NYX 0:85b3fd62ea1a 11401 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 11402 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
NYX 0:85b3fd62ea1a 11403
NYX 0:85b3fd62ea1a 11404 /******************** Bits definition for RTC_CALIBR register ***************/
NYX 0:85b3fd62ea1a 11405 #define RTC_CALIBR_DCS_Pos (7U)
NYX 0:85b3fd62ea1a 11406 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11407 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
NYX 0:85b3fd62ea1a 11408 #define RTC_CALIBR_DC_Pos (0U)
NYX 0:85b3fd62ea1a 11409 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 11410 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
NYX 0:85b3fd62ea1a 11411
NYX 0:85b3fd62ea1a 11412 /******************** Bits definition for RTC_ALRMAR register ***************/
NYX 0:85b3fd62ea1a 11413 #define RTC_ALRMAR_MSK4_Pos (31U)
NYX 0:85b3fd62ea1a 11414 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 11415 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
NYX 0:85b3fd62ea1a 11416 #define RTC_ALRMAR_WDSEL_Pos (30U)
NYX 0:85b3fd62ea1a 11417 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 11418 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
NYX 0:85b3fd62ea1a 11419 #define RTC_ALRMAR_DT_Pos (28U)
NYX 0:85b3fd62ea1a 11420 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 11421 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
NYX 0:85b3fd62ea1a 11422 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 11423 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 11424 #define RTC_ALRMAR_DU_Pos (24U)
NYX 0:85b3fd62ea1a 11425 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 11426 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
NYX 0:85b3fd62ea1a 11427 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 11428 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 11429 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 11430 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 11431 #define RTC_ALRMAR_MSK3_Pos (23U)
NYX 0:85b3fd62ea1a 11432 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 11433 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
NYX 0:85b3fd62ea1a 11434 #define RTC_ALRMAR_PM_Pos (22U)
NYX 0:85b3fd62ea1a 11435 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 11436 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
NYX 0:85b3fd62ea1a 11437 #define RTC_ALRMAR_HT_Pos (20U)
NYX 0:85b3fd62ea1a 11438 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 11439 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
NYX 0:85b3fd62ea1a 11440 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 11441 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 11442 #define RTC_ALRMAR_HU_Pos (16U)
NYX 0:85b3fd62ea1a 11443 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 11444 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
NYX 0:85b3fd62ea1a 11445 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11446 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11447 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 11448 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 11449 #define RTC_ALRMAR_MSK2_Pos (15U)
NYX 0:85b3fd62ea1a 11450 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 11451 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
NYX 0:85b3fd62ea1a 11452 #define RTC_ALRMAR_MNT_Pos (12U)
NYX 0:85b3fd62ea1a 11453 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
NYX 0:85b3fd62ea1a 11454 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
NYX 0:85b3fd62ea1a 11455 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11456 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11457 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11458 #define RTC_ALRMAR_MNU_Pos (8U)
NYX 0:85b3fd62ea1a 11459 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 11460 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
NYX 0:85b3fd62ea1a 11461 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11462 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11463 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11464 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11465 #define RTC_ALRMAR_MSK1_Pos (7U)
NYX 0:85b3fd62ea1a 11466 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11467 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
NYX 0:85b3fd62ea1a 11468 #define RTC_ALRMAR_ST_Pos (4U)
NYX 0:85b3fd62ea1a 11469 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 11470 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
NYX 0:85b3fd62ea1a 11471 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11472 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11473 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11474 #define RTC_ALRMAR_SU_Pos (0U)
NYX 0:85b3fd62ea1a 11475 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 11476 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
NYX 0:85b3fd62ea1a 11477 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11478 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11479 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11480 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11481
NYX 0:85b3fd62ea1a 11482 /******************** Bits definition for RTC_ALRMBR register ***************/
NYX 0:85b3fd62ea1a 11483 #define RTC_ALRMBR_MSK4_Pos (31U)
NYX 0:85b3fd62ea1a 11484 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 11485 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
NYX 0:85b3fd62ea1a 11486 #define RTC_ALRMBR_WDSEL_Pos (30U)
NYX 0:85b3fd62ea1a 11487 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 11488 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
NYX 0:85b3fd62ea1a 11489 #define RTC_ALRMBR_DT_Pos (28U)
NYX 0:85b3fd62ea1a 11490 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 11491 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
NYX 0:85b3fd62ea1a 11492 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 11493 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 11494 #define RTC_ALRMBR_DU_Pos (24U)
NYX 0:85b3fd62ea1a 11495 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 11496 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
NYX 0:85b3fd62ea1a 11497 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 11498 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 11499 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 11500 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 11501 #define RTC_ALRMBR_MSK3_Pos (23U)
NYX 0:85b3fd62ea1a 11502 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 11503 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
NYX 0:85b3fd62ea1a 11504 #define RTC_ALRMBR_PM_Pos (22U)
NYX 0:85b3fd62ea1a 11505 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 11506 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
NYX 0:85b3fd62ea1a 11507 #define RTC_ALRMBR_HT_Pos (20U)
NYX 0:85b3fd62ea1a 11508 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 11509 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
NYX 0:85b3fd62ea1a 11510 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 11511 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 11512 #define RTC_ALRMBR_HU_Pos (16U)
NYX 0:85b3fd62ea1a 11513 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 11514 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
NYX 0:85b3fd62ea1a 11515 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11516 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11517 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 11518 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 11519 #define RTC_ALRMBR_MSK2_Pos (15U)
NYX 0:85b3fd62ea1a 11520 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 11521 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
NYX 0:85b3fd62ea1a 11522 #define RTC_ALRMBR_MNT_Pos (12U)
NYX 0:85b3fd62ea1a 11523 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
NYX 0:85b3fd62ea1a 11524 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
NYX 0:85b3fd62ea1a 11525 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11526 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11527 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11528 #define RTC_ALRMBR_MNU_Pos (8U)
NYX 0:85b3fd62ea1a 11529 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 11530 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
NYX 0:85b3fd62ea1a 11531 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11532 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11533 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11534 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11535 #define RTC_ALRMBR_MSK1_Pos (7U)
NYX 0:85b3fd62ea1a 11536 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11537 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
NYX 0:85b3fd62ea1a 11538 #define RTC_ALRMBR_ST_Pos (4U)
NYX 0:85b3fd62ea1a 11539 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 11540 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
NYX 0:85b3fd62ea1a 11541 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11542 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11543 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11544 #define RTC_ALRMBR_SU_Pos (0U)
NYX 0:85b3fd62ea1a 11545 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 11546 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
NYX 0:85b3fd62ea1a 11547 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11548 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11549 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11550 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11551
NYX 0:85b3fd62ea1a 11552 /******************** Bits definition for RTC_WPR register ******************/
NYX 0:85b3fd62ea1a 11553 #define RTC_WPR_KEY_Pos (0U)
NYX 0:85b3fd62ea1a 11554 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 11555 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
NYX 0:85b3fd62ea1a 11556
NYX 0:85b3fd62ea1a 11557 /******************** Bits definition for RTC_SSR register ******************/
NYX 0:85b3fd62ea1a 11558 #define RTC_SSR_SS_Pos (0U)
NYX 0:85b3fd62ea1a 11559 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 11560 #define RTC_SSR_SS RTC_SSR_SS_Msk
NYX 0:85b3fd62ea1a 11561
NYX 0:85b3fd62ea1a 11562 /******************** Bits definition for RTC_SHIFTR register ***************/
NYX 0:85b3fd62ea1a 11563 #define RTC_SHIFTR_SUBFS_Pos (0U)
NYX 0:85b3fd62ea1a 11564 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
NYX 0:85b3fd62ea1a 11565 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
NYX 0:85b3fd62ea1a 11566 #define RTC_SHIFTR_ADD1S_Pos (31U)
NYX 0:85b3fd62ea1a 11567 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 11568 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
NYX 0:85b3fd62ea1a 11569
NYX 0:85b3fd62ea1a 11570 /******************** Bits definition for RTC_TSTR register *****************/
NYX 0:85b3fd62ea1a 11571 #define RTC_TSTR_PM_Pos (22U)
NYX 0:85b3fd62ea1a 11572 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 11573 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
NYX 0:85b3fd62ea1a 11574 #define RTC_TSTR_HT_Pos (20U)
NYX 0:85b3fd62ea1a 11575 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 11576 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
NYX 0:85b3fd62ea1a 11577 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 11578 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 11579 #define RTC_TSTR_HU_Pos (16U)
NYX 0:85b3fd62ea1a 11580 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
NYX 0:85b3fd62ea1a 11581 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
NYX 0:85b3fd62ea1a 11582 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11583 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11584 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 11585 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 11586 #define RTC_TSTR_MNT_Pos (12U)
NYX 0:85b3fd62ea1a 11587 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
NYX 0:85b3fd62ea1a 11588 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
NYX 0:85b3fd62ea1a 11589 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11590 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11591 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11592 #define RTC_TSTR_MNU_Pos (8U)
NYX 0:85b3fd62ea1a 11593 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 11594 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
NYX 0:85b3fd62ea1a 11595 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11596 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11597 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11598 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11599 #define RTC_TSTR_ST_Pos (4U)
NYX 0:85b3fd62ea1a 11600 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 11601 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
NYX 0:85b3fd62ea1a 11602 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11603 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11604 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11605 #define RTC_TSTR_SU_Pos (0U)
NYX 0:85b3fd62ea1a 11606 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 11607 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
NYX 0:85b3fd62ea1a 11608 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11609 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11610 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11611 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11612
NYX 0:85b3fd62ea1a 11613 /******************** Bits definition for RTC_TSDR register *****************/
NYX 0:85b3fd62ea1a 11614 #define RTC_TSDR_WDU_Pos (13U)
NYX 0:85b3fd62ea1a 11615 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
NYX 0:85b3fd62ea1a 11616 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
NYX 0:85b3fd62ea1a 11617 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11618 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11619 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 11620 #define RTC_TSDR_MT_Pos (12U)
NYX 0:85b3fd62ea1a 11621 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11622 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
NYX 0:85b3fd62ea1a 11623 #define RTC_TSDR_MU_Pos (8U)
NYX 0:85b3fd62ea1a 11624 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 11625 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
NYX 0:85b3fd62ea1a 11626 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11627 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11628 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11629 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11630 #define RTC_TSDR_DT_Pos (4U)
NYX 0:85b3fd62ea1a 11631 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 11632 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
NYX 0:85b3fd62ea1a 11633 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11634 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11635 #define RTC_TSDR_DU_Pos (0U)
NYX 0:85b3fd62ea1a 11636 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 11637 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
NYX 0:85b3fd62ea1a 11638 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11639 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11640 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11641 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11642
NYX 0:85b3fd62ea1a 11643 /******************** Bits definition for RTC_TSSSR register ****************/
NYX 0:85b3fd62ea1a 11644 #define RTC_TSSSR_SS_Pos (0U)
NYX 0:85b3fd62ea1a 11645 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 11646 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
NYX 0:85b3fd62ea1a 11647
NYX 0:85b3fd62ea1a 11648 /******************** Bits definition for RTC_CAL register *****************/
NYX 0:85b3fd62ea1a 11649 #define RTC_CALR_CALP_Pos (15U)
NYX 0:85b3fd62ea1a 11650 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 11651 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
NYX 0:85b3fd62ea1a 11652 #define RTC_CALR_CALW8_Pos (14U)
NYX 0:85b3fd62ea1a 11653 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11654 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
NYX 0:85b3fd62ea1a 11655 #define RTC_CALR_CALW16_Pos (13U)
NYX 0:85b3fd62ea1a 11656 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11657 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
NYX 0:85b3fd62ea1a 11658 #define RTC_CALR_CALM_Pos (0U)
NYX 0:85b3fd62ea1a 11659 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
NYX 0:85b3fd62ea1a 11660 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
NYX 0:85b3fd62ea1a 11661 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11662 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11663 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11664 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11665 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11666 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11667 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11668 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11669 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11670
NYX 0:85b3fd62ea1a 11671 /******************** Bits definition for RTC_TAFCR register ****************/
NYX 0:85b3fd62ea1a 11672 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
NYX 0:85b3fd62ea1a 11673 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 11674 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
NYX 0:85b3fd62ea1a 11675 #define RTC_TAFCR_TSINSEL_Pos (17U)
NYX 0:85b3fd62ea1a 11676 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11677 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
NYX 0:85b3fd62ea1a 11678 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
NYX 0:85b3fd62ea1a 11679 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11680 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
NYX 0:85b3fd62ea1a 11681 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
NYX 0:85b3fd62ea1a 11682 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 11683 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
NYX 0:85b3fd62ea1a 11684 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
NYX 0:85b3fd62ea1a 11685 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
NYX 0:85b3fd62ea1a 11686 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
NYX 0:85b3fd62ea1a 11687 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11688 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11689 #define RTC_TAFCR_TAMPFLT_Pos (11U)
NYX 0:85b3fd62ea1a 11690 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
NYX 0:85b3fd62ea1a 11691 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
NYX 0:85b3fd62ea1a 11692 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11693 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11694 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
NYX 0:85b3fd62ea1a 11695 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
NYX 0:85b3fd62ea1a 11696 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
NYX 0:85b3fd62ea1a 11697 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11698 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11699 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11700 #define RTC_TAFCR_TAMPTS_Pos (7U)
NYX 0:85b3fd62ea1a 11701 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11702 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
NYX 0:85b3fd62ea1a 11703 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
NYX 0:85b3fd62ea1a 11704 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11705 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
NYX 0:85b3fd62ea1a 11706 #define RTC_TAFCR_TAMP2E_Pos (3U)
NYX 0:85b3fd62ea1a 11707 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11708 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
NYX 0:85b3fd62ea1a 11709 #define RTC_TAFCR_TAMPIE_Pos (2U)
NYX 0:85b3fd62ea1a 11710 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11711 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
NYX 0:85b3fd62ea1a 11712 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
NYX 0:85b3fd62ea1a 11713 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11714 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
NYX 0:85b3fd62ea1a 11715 #define RTC_TAFCR_TAMP1E_Pos (0U)
NYX 0:85b3fd62ea1a 11716 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11717 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
NYX 0:85b3fd62ea1a 11718
NYX 0:85b3fd62ea1a 11719 /* Legacy defines */
NYX 0:85b3fd62ea1a 11720 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
NYX 0:85b3fd62ea1a 11721
NYX 0:85b3fd62ea1a 11722 /******************** Bits definition for RTC_ALRMASSR register *************/
NYX 0:85b3fd62ea1a 11723 #define RTC_ALRMASSR_MASKSS_Pos (24U)
NYX 0:85b3fd62ea1a 11724 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 11725 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
NYX 0:85b3fd62ea1a 11726 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 11727 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 11728 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 11729 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 11730 #define RTC_ALRMASSR_SS_Pos (0U)
NYX 0:85b3fd62ea1a 11731 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
NYX 0:85b3fd62ea1a 11732 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
NYX 0:85b3fd62ea1a 11733
NYX 0:85b3fd62ea1a 11734 /******************** Bits definition for RTC_ALRMBSSR register *************/
NYX 0:85b3fd62ea1a 11735 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
NYX 0:85b3fd62ea1a 11736 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
NYX 0:85b3fd62ea1a 11737 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
NYX 0:85b3fd62ea1a 11738 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 11739 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 11740 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 11741 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 11742 #define RTC_ALRMBSSR_SS_Pos (0U)
NYX 0:85b3fd62ea1a 11743 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
NYX 0:85b3fd62ea1a 11744 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
NYX 0:85b3fd62ea1a 11745
NYX 0:85b3fd62ea1a 11746 /******************** Bits definition for RTC_BKP0R register ****************/
NYX 0:85b3fd62ea1a 11747 #define RTC_BKP0R_Pos (0U)
NYX 0:85b3fd62ea1a 11748 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11749 #define RTC_BKP0R RTC_BKP0R_Msk
NYX 0:85b3fd62ea1a 11750
NYX 0:85b3fd62ea1a 11751 /******************** Bits definition for RTC_BKP1R register ****************/
NYX 0:85b3fd62ea1a 11752 #define RTC_BKP1R_Pos (0U)
NYX 0:85b3fd62ea1a 11753 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11754 #define RTC_BKP1R RTC_BKP1R_Msk
NYX 0:85b3fd62ea1a 11755
NYX 0:85b3fd62ea1a 11756 /******************** Bits definition for RTC_BKP2R register ****************/
NYX 0:85b3fd62ea1a 11757 #define RTC_BKP2R_Pos (0U)
NYX 0:85b3fd62ea1a 11758 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11759 #define RTC_BKP2R RTC_BKP2R_Msk
NYX 0:85b3fd62ea1a 11760
NYX 0:85b3fd62ea1a 11761 /******************** Bits definition for RTC_BKP3R register ****************/
NYX 0:85b3fd62ea1a 11762 #define RTC_BKP3R_Pos (0U)
NYX 0:85b3fd62ea1a 11763 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11764 #define RTC_BKP3R RTC_BKP3R_Msk
NYX 0:85b3fd62ea1a 11765
NYX 0:85b3fd62ea1a 11766 /******************** Bits definition for RTC_BKP4R register ****************/
NYX 0:85b3fd62ea1a 11767 #define RTC_BKP4R_Pos (0U)
NYX 0:85b3fd62ea1a 11768 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11769 #define RTC_BKP4R RTC_BKP4R_Msk
NYX 0:85b3fd62ea1a 11770
NYX 0:85b3fd62ea1a 11771 /******************** Bits definition for RTC_BKP5R register ****************/
NYX 0:85b3fd62ea1a 11772 #define RTC_BKP5R_Pos (0U)
NYX 0:85b3fd62ea1a 11773 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11774 #define RTC_BKP5R RTC_BKP5R_Msk
NYX 0:85b3fd62ea1a 11775
NYX 0:85b3fd62ea1a 11776 /******************** Bits definition for RTC_BKP6R register ****************/
NYX 0:85b3fd62ea1a 11777 #define RTC_BKP6R_Pos (0U)
NYX 0:85b3fd62ea1a 11778 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11779 #define RTC_BKP6R RTC_BKP6R_Msk
NYX 0:85b3fd62ea1a 11780
NYX 0:85b3fd62ea1a 11781 /******************** Bits definition for RTC_BKP7R register ****************/
NYX 0:85b3fd62ea1a 11782 #define RTC_BKP7R_Pos (0U)
NYX 0:85b3fd62ea1a 11783 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11784 #define RTC_BKP7R RTC_BKP7R_Msk
NYX 0:85b3fd62ea1a 11785
NYX 0:85b3fd62ea1a 11786 /******************** Bits definition for RTC_BKP8R register ****************/
NYX 0:85b3fd62ea1a 11787 #define RTC_BKP8R_Pos (0U)
NYX 0:85b3fd62ea1a 11788 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11789 #define RTC_BKP8R RTC_BKP8R_Msk
NYX 0:85b3fd62ea1a 11790
NYX 0:85b3fd62ea1a 11791 /******************** Bits definition for RTC_BKP9R register ****************/
NYX 0:85b3fd62ea1a 11792 #define RTC_BKP9R_Pos (0U)
NYX 0:85b3fd62ea1a 11793 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11794 #define RTC_BKP9R RTC_BKP9R_Msk
NYX 0:85b3fd62ea1a 11795
NYX 0:85b3fd62ea1a 11796 /******************** Bits definition for RTC_BKP10R register ***************/
NYX 0:85b3fd62ea1a 11797 #define RTC_BKP10R_Pos (0U)
NYX 0:85b3fd62ea1a 11798 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11799 #define RTC_BKP10R RTC_BKP10R_Msk
NYX 0:85b3fd62ea1a 11800
NYX 0:85b3fd62ea1a 11801 /******************** Bits definition for RTC_BKP11R register ***************/
NYX 0:85b3fd62ea1a 11802 #define RTC_BKP11R_Pos (0U)
NYX 0:85b3fd62ea1a 11803 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11804 #define RTC_BKP11R RTC_BKP11R_Msk
NYX 0:85b3fd62ea1a 11805
NYX 0:85b3fd62ea1a 11806 /******************** Bits definition for RTC_BKP12R register ***************/
NYX 0:85b3fd62ea1a 11807 #define RTC_BKP12R_Pos (0U)
NYX 0:85b3fd62ea1a 11808 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11809 #define RTC_BKP12R RTC_BKP12R_Msk
NYX 0:85b3fd62ea1a 11810
NYX 0:85b3fd62ea1a 11811 /******************** Bits definition for RTC_BKP13R register ***************/
NYX 0:85b3fd62ea1a 11812 #define RTC_BKP13R_Pos (0U)
NYX 0:85b3fd62ea1a 11813 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11814 #define RTC_BKP13R RTC_BKP13R_Msk
NYX 0:85b3fd62ea1a 11815
NYX 0:85b3fd62ea1a 11816 /******************** Bits definition for RTC_BKP14R register ***************/
NYX 0:85b3fd62ea1a 11817 #define RTC_BKP14R_Pos (0U)
NYX 0:85b3fd62ea1a 11818 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11819 #define RTC_BKP14R RTC_BKP14R_Msk
NYX 0:85b3fd62ea1a 11820
NYX 0:85b3fd62ea1a 11821 /******************** Bits definition for RTC_BKP15R register ***************/
NYX 0:85b3fd62ea1a 11822 #define RTC_BKP15R_Pos (0U)
NYX 0:85b3fd62ea1a 11823 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11824 #define RTC_BKP15R RTC_BKP15R_Msk
NYX 0:85b3fd62ea1a 11825
NYX 0:85b3fd62ea1a 11826 /******************** Bits definition for RTC_BKP16R register ***************/
NYX 0:85b3fd62ea1a 11827 #define RTC_BKP16R_Pos (0U)
NYX 0:85b3fd62ea1a 11828 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11829 #define RTC_BKP16R RTC_BKP16R_Msk
NYX 0:85b3fd62ea1a 11830
NYX 0:85b3fd62ea1a 11831 /******************** Bits definition for RTC_BKP17R register ***************/
NYX 0:85b3fd62ea1a 11832 #define RTC_BKP17R_Pos (0U)
NYX 0:85b3fd62ea1a 11833 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11834 #define RTC_BKP17R RTC_BKP17R_Msk
NYX 0:85b3fd62ea1a 11835
NYX 0:85b3fd62ea1a 11836 /******************** Bits definition for RTC_BKP18R register ***************/
NYX 0:85b3fd62ea1a 11837 #define RTC_BKP18R_Pos (0U)
NYX 0:85b3fd62ea1a 11838 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11839 #define RTC_BKP18R RTC_BKP18R_Msk
NYX 0:85b3fd62ea1a 11840
NYX 0:85b3fd62ea1a 11841 /******************** Bits definition for RTC_BKP19R register ***************/
NYX 0:85b3fd62ea1a 11842 #define RTC_BKP19R_Pos (0U)
NYX 0:85b3fd62ea1a 11843 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 11844 #define RTC_BKP19R RTC_BKP19R_Msk
NYX 0:85b3fd62ea1a 11845
NYX 0:85b3fd62ea1a 11846 /******************** Number of backup registers ******************************/
NYX 0:85b3fd62ea1a 11847 #define RTC_BKP_NUMBER 0x000000014U
NYX 0:85b3fd62ea1a 11848
NYX 0:85b3fd62ea1a 11849 /******************************************************************************/
NYX 0:85b3fd62ea1a 11850 /* */
NYX 0:85b3fd62ea1a 11851 /* Serial Audio Interface */
NYX 0:85b3fd62ea1a 11852 /* */
NYX 0:85b3fd62ea1a 11853 /******************************************************************************/
NYX 0:85b3fd62ea1a 11854 /******************** Bit definition for SAI_GCR register *******************/
NYX 0:85b3fd62ea1a 11855 #define SAI_GCR_SYNCIN_Pos (0U)
NYX 0:85b3fd62ea1a 11856 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 11857 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
NYX 0:85b3fd62ea1a 11858 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11859 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11860
NYX 0:85b3fd62ea1a 11861 #define SAI_GCR_SYNCOUT_Pos (4U)
NYX 0:85b3fd62ea1a 11862 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 11863 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
NYX 0:85b3fd62ea1a 11864 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11865 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11866
NYX 0:85b3fd62ea1a 11867 /******************* Bit definition for SAI_xCR1 register *******************/
NYX 0:85b3fd62ea1a 11868 #define SAI_xCR1_MODE_Pos (0U)
NYX 0:85b3fd62ea1a 11869 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 11870 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
NYX 0:85b3fd62ea1a 11871 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11872 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11873
NYX 0:85b3fd62ea1a 11874 #define SAI_xCR1_PRTCFG_Pos (2U)
NYX 0:85b3fd62ea1a 11875 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 11876 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
NYX 0:85b3fd62ea1a 11877 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11878 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11879
NYX 0:85b3fd62ea1a 11880 #define SAI_xCR1_DS_Pos (5U)
NYX 0:85b3fd62ea1a 11881 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
NYX 0:85b3fd62ea1a 11882 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
NYX 0:85b3fd62ea1a 11883 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11884 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11885 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11886
NYX 0:85b3fd62ea1a 11887 #define SAI_xCR1_LSBFIRST_Pos (8U)
NYX 0:85b3fd62ea1a 11888 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11889 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
NYX 0:85b3fd62ea1a 11890 #define SAI_xCR1_CKSTR_Pos (9U)
NYX 0:85b3fd62ea1a 11891 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11892 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
NYX 0:85b3fd62ea1a 11893
NYX 0:85b3fd62ea1a 11894 #define SAI_xCR1_SYNCEN_Pos (10U)
NYX 0:85b3fd62ea1a 11895 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 11896 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
NYX 0:85b3fd62ea1a 11897 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11898 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11899
NYX 0:85b3fd62ea1a 11900 #define SAI_xCR1_MONO_Pos (12U)
NYX 0:85b3fd62ea1a 11901 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11902 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
NYX 0:85b3fd62ea1a 11903 #define SAI_xCR1_OUTDRIV_Pos (13U)
NYX 0:85b3fd62ea1a 11904 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11905 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
NYX 0:85b3fd62ea1a 11906 #define SAI_xCR1_SAIEN_Pos (16U)
NYX 0:85b3fd62ea1a 11907 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11908 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
NYX 0:85b3fd62ea1a 11909 #define SAI_xCR1_DMAEN_Pos (17U)
NYX 0:85b3fd62ea1a 11910 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11911 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
NYX 0:85b3fd62ea1a 11912 #define SAI_xCR1_NODIV_Pos (19U)
NYX 0:85b3fd62ea1a 11913 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 11914 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
NYX 0:85b3fd62ea1a 11915
NYX 0:85b3fd62ea1a 11916 #define SAI_xCR1_MCKDIV_Pos (20U)
NYX 0:85b3fd62ea1a 11917 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
NYX 0:85b3fd62ea1a 11918 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
NYX 0:85b3fd62ea1a 11919 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 11920 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 11921 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 11922 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 11923
NYX 0:85b3fd62ea1a 11924 /******************* Bit definition for SAI_xCR2 register *******************/
NYX 0:85b3fd62ea1a 11925 #define SAI_xCR2_FTH_Pos (0U)
NYX 0:85b3fd62ea1a 11926 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 11927 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
NYX 0:85b3fd62ea1a 11928 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11929 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11930 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11931
NYX 0:85b3fd62ea1a 11932 #define SAI_xCR2_FFLUSH_Pos (3U)
NYX 0:85b3fd62ea1a 11933 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11934 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
NYX 0:85b3fd62ea1a 11935 #define SAI_xCR2_TRIS_Pos (4U)
NYX 0:85b3fd62ea1a 11936 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11937 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
NYX 0:85b3fd62ea1a 11938 #define SAI_xCR2_MUTE_Pos (5U)
NYX 0:85b3fd62ea1a 11939 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11940 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
NYX 0:85b3fd62ea1a 11941 #define SAI_xCR2_MUTEVAL_Pos (6U)
NYX 0:85b3fd62ea1a 11942 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11943 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
NYX 0:85b3fd62ea1a 11944
NYX 0:85b3fd62ea1a 11945 #define SAI_xCR2_MUTECNT_Pos (7U)
NYX 0:85b3fd62ea1a 11946 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
NYX 0:85b3fd62ea1a 11947 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
NYX 0:85b3fd62ea1a 11948 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11949 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11950 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11951 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11952 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11953 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11954
NYX 0:85b3fd62ea1a 11955 #define SAI_xCR2_CPL_Pos (13U)
NYX 0:85b3fd62ea1a 11956 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11957 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
NYX 0:85b3fd62ea1a 11958
NYX 0:85b3fd62ea1a 11959 #define SAI_xCR2_COMP_Pos (14U)
NYX 0:85b3fd62ea1a 11960 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
NYX 0:85b3fd62ea1a 11961 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
NYX 0:85b3fd62ea1a 11962 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11963 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 11964
NYX 0:85b3fd62ea1a 11965 /****************** Bit definition for SAI_xFRCR register *******************/
NYX 0:85b3fd62ea1a 11966 #define SAI_xFRCR_FRL_Pos (0U)
NYX 0:85b3fd62ea1a 11967 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 11968 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
NYX 0:85b3fd62ea1a 11969 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 11970 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 11971 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 11972 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 11973 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 11974 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 11975 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 11976 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 11977
NYX 0:85b3fd62ea1a 11978 #define SAI_xFRCR_FSALL_Pos (8U)
NYX 0:85b3fd62ea1a 11979 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
NYX 0:85b3fd62ea1a 11980 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
NYX 0:85b3fd62ea1a 11981 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 11982 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 11983 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 11984 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 11985 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 11986 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 11987 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 11988
NYX 0:85b3fd62ea1a 11989 #define SAI_xFRCR_FSDEF_Pos (16U)
NYX 0:85b3fd62ea1a 11990 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 11991 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
NYX 0:85b3fd62ea1a 11992 #define SAI_xFRCR_FSPOL_Pos (17U)
NYX 0:85b3fd62ea1a 11993 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 11994 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
NYX 0:85b3fd62ea1a 11995 #define SAI_xFRCR_FSOFF_Pos (18U)
NYX 0:85b3fd62ea1a 11996 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 11997 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
NYX 0:85b3fd62ea1a 11998 /* Legacy defines */
NYX 0:85b3fd62ea1a 11999 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
NYX 0:85b3fd62ea1a 12000
NYX 0:85b3fd62ea1a 12001 /****************** Bit definition for SAI_xSLOTR register *******************/
NYX 0:85b3fd62ea1a 12002 #define SAI_xSLOTR_FBOFF_Pos (0U)
NYX 0:85b3fd62ea1a 12003 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 12004 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
NYX 0:85b3fd62ea1a 12005 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12006 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12007 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12008 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12009 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12010
NYX 0:85b3fd62ea1a 12011 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
NYX 0:85b3fd62ea1a 12012 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 12013 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
NYX 0:85b3fd62ea1a 12014 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12015 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12016
NYX 0:85b3fd62ea1a 12017 #define SAI_xSLOTR_NBSLOT_Pos (8U)
NYX 0:85b3fd62ea1a 12018 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 12019 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
NYX 0:85b3fd62ea1a 12020 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12021 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 12022 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12023 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 12024
NYX 0:85b3fd62ea1a 12025 #define SAI_xSLOTR_SLOTEN_Pos (16U)
NYX 0:85b3fd62ea1a 12026 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 12027 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
NYX 0:85b3fd62ea1a 12028
NYX 0:85b3fd62ea1a 12029 /******************* Bit definition for SAI_xIMR register *******************/
NYX 0:85b3fd62ea1a 12030 #define SAI_xIMR_OVRUDRIE_Pos (0U)
NYX 0:85b3fd62ea1a 12031 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12032 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
NYX 0:85b3fd62ea1a 12033 #define SAI_xIMR_MUTEDETIE_Pos (1U)
NYX 0:85b3fd62ea1a 12034 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12035 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
NYX 0:85b3fd62ea1a 12036 #define SAI_xIMR_WCKCFGIE_Pos (2U)
NYX 0:85b3fd62ea1a 12037 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12038 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
NYX 0:85b3fd62ea1a 12039 #define SAI_xIMR_FREQIE_Pos (3U)
NYX 0:85b3fd62ea1a 12040 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12041 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
NYX 0:85b3fd62ea1a 12042 #define SAI_xIMR_CNRDYIE_Pos (4U)
NYX 0:85b3fd62ea1a 12043 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12044 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
NYX 0:85b3fd62ea1a 12045 #define SAI_xIMR_AFSDETIE_Pos (5U)
NYX 0:85b3fd62ea1a 12046 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12047 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
NYX 0:85b3fd62ea1a 12048 #define SAI_xIMR_LFSDETIE_Pos (6U)
NYX 0:85b3fd62ea1a 12049 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12050 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
NYX 0:85b3fd62ea1a 12051
NYX 0:85b3fd62ea1a 12052 /******************** Bit definition for SAI_xSR register *******************/
NYX 0:85b3fd62ea1a 12053 #define SAI_xSR_OVRUDR_Pos (0U)
NYX 0:85b3fd62ea1a 12054 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12055 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
NYX 0:85b3fd62ea1a 12056 #define SAI_xSR_MUTEDET_Pos (1U)
NYX 0:85b3fd62ea1a 12057 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12058 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
NYX 0:85b3fd62ea1a 12059 #define SAI_xSR_WCKCFG_Pos (2U)
NYX 0:85b3fd62ea1a 12060 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12061 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
NYX 0:85b3fd62ea1a 12062 #define SAI_xSR_FREQ_Pos (3U)
NYX 0:85b3fd62ea1a 12063 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12064 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
NYX 0:85b3fd62ea1a 12065 #define SAI_xSR_CNRDY_Pos (4U)
NYX 0:85b3fd62ea1a 12066 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12067 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
NYX 0:85b3fd62ea1a 12068 #define SAI_xSR_AFSDET_Pos (5U)
NYX 0:85b3fd62ea1a 12069 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12070 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
NYX 0:85b3fd62ea1a 12071 #define SAI_xSR_LFSDET_Pos (6U)
NYX 0:85b3fd62ea1a 12072 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12073 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
NYX 0:85b3fd62ea1a 12074
NYX 0:85b3fd62ea1a 12075 #define SAI_xSR_FLVL_Pos (16U)
NYX 0:85b3fd62ea1a 12076 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
NYX 0:85b3fd62ea1a 12077 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
NYX 0:85b3fd62ea1a 12078 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 12079 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 12080 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 12081
NYX 0:85b3fd62ea1a 12082 /****************** Bit definition for SAI_xCLRFR register ******************/
NYX 0:85b3fd62ea1a 12083 #define SAI_xCLRFR_COVRUDR_Pos (0U)
NYX 0:85b3fd62ea1a 12084 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12085 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
NYX 0:85b3fd62ea1a 12086 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
NYX 0:85b3fd62ea1a 12087 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12088 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
NYX 0:85b3fd62ea1a 12089 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
NYX 0:85b3fd62ea1a 12090 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12091 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
NYX 0:85b3fd62ea1a 12092 #define SAI_xCLRFR_CFREQ_Pos (3U)
NYX 0:85b3fd62ea1a 12093 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12094 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
NYX 0:85b3fd62ea1a 12095 #define SAI_xCLRFR_CCNRDY_Pos (4U)
NYX 0:85b3fd62ea1a 12096 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12097 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
NYX 0:85b3fd62ea1a 12098 #define SAI_xCLRFR_CAFSDET_Pos (5U)
NYX 0:85b3fd62ea1a 12099 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12100 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
NYX 0:85b3fd62ea1a 12101 #define SAI_xCLRFR_CLFSDET_Pos (6U)
NYX 0:85b3fd62ea1a 12102 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12103 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
NYX 0:85b3fd62ea1a 12104
NYX 0:85b3fd62ea1a 12105 /****************** Bit definition for SAI_xDR register ******************/
NYX 0:85b3fd62ea1a 12106 #define SAI_xDR_DATA_Pos (0U)
NYX 0:85b3fd62ea1a 12107 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 12108 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
NYX 0:85b3fd62ea1a 12109
NYX 0:85b3fd62ea1a 12110 /******************************************************************************/
NYX 0:85b3fd62ea1a 12111 /* */
NYX 0:85b3fd62ea1a 12112 /* SPDIF-RX Interface */
NYX 0:85b3fd62ea1a 12113 /* */
NYX 0:85b3fd62ea1a 12114 /******************************************************************************/
NYX 0:85b3fd62ea1a 12115 /******************** Bit definition for SPDIFRX_CR register *******************/
NYX 0:85b3fd62ea1a 12116 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
NYX 0:85b3fd62ea1a 12117 #define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 12118 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
NYX 0:85b3fd62ea1a 12119 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
NYX 0:85b3fd62ea1a 12120 #define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12121 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
NYX 0:85b3fd62ea1a 12122 #define SPDIFRX_CR_RXSTEO_Pos (3U)
NYX 0:85b3fd62ea1a 12123 #define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12124 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
NYX 0:85b3fd62ea1a 12125 #define SPDIFRX_CR_DRFMT_Pos (4U)
NYX 0:85b3fd62ea1a 12126 #define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 12127 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
NYX 0:85b3fd62ea1a 12128 #define SPDIFRX_CR_PMSK_Pos (6U)
NYX 0:85b3fd62ea1a 12129 #define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12130 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
NYX 0:85b3fd62ea1a 12131 #define SPDIFRX_CR_VMSK_Pos (7U)
NYX 0:85b3fd62ea1a 12132 #define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12133 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
NYX 0:85b3fd62ea1a 12134 #define SPDIFRX_CR_CUMSK_Pos (8U)
NYX 0:85b3fd62ea1a 12135 #define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12136 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
NYX 0:85b3fd62ea1a 12137 #define SPDIFRX_CR_PTMSK_Pos (9U)
NYX 0:85b3fd62ea1a 12138 #define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 12139 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
NYX 0:85b3fd62ea1a 12140 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
NYX 0:85b3fd62ea1a 12141 #define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12142 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
NYX 0:85b3fd62ea1a 12143 #define SPDIFRX_CR_CHSEL_Pos (11U)
NYX 0:85b3fd62ea1a 12144 #define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 12145 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
NYX 0:85b3fd62ea1a 12146 #define SPDIFRX_CR_NBTR_Pos (12U)
NYX 0:85b3fd62ea1a 12147 #define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
NYX 0:85b3fd62ea1a 12148 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
NYX 0:85b3fd62ea1a 12149 #define SPDIFRX_CR_WFA_Pos (14U)
NYX 0:85b3fd62ea1a 12150 #define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 12151 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
NYX 0:85b3fd62ea1a 12152 #define SPDIFRX_CR_INSEL_Pos (16U)
NYX 0:85b3fd62ea1a 12153 #define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
NYX 0:85b3fd62ea1a 12154 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIFRX input selection */
NYX 0:85b3fd62ea1a 12155
NYX 0:85b3fd62ea1a 12156 /******************* Bit definition for SPDIFRX_IMR register *******************/
NYX 0:85b3fd62ea1a 12157 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
NYX 0:85b3fd62ea1a 12158 #define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12159 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
NYX 0:85b3fd62ea1a 12160 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
NYX 0:85b3fd62ea1a 12161 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12162 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
NYX 0:85b3fd62ea1a 12163 #define SPDIFRX_IMR_PERRIE_Pos (2U)
NYX 0:85b3fd62ea1a 12164 #define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12165 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
NYX 0:85b3fd62ea1a 12166 #define SPDIFRX_IMR_OVRIE_Pos (3U)
NYX 0:85b3fd62ea1a 12167 #define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12168 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
NYX 0:85b3fd62ea1a 12169 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
NYX 0:85b3fd62ea1a 12170 #define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12171 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
NYX 0:85b3fd62ea1a 12172 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
NYX 0:85b3fd62ea1a 12173 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12174 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
NYX 0:85b3fd62ea1a 12175 #define SPDIFRX_IMR_IFEIE_Pos (6U)
NYX 0:85b3fd62ea1a 12176 #define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12177 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
NYX 0:85b3fd62ea1a 12178
NYX 0:85b3fd62ea1a 12179 /******************* Bit definition for SPDIFRX_SR register *******************/
NYX 0:85b3fd62ea1a 12180 #define SPDIFRX_SR_RXNE_Pos (0U)
NYX 0:85b3fd62ea1a 12181 #define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12182 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
NYX 0:85b3fd62ea1a 12183 #define SPDIFRX_SR_CSRNE_Pos (1U)
NYX 0:85b3fd62ea1a 12184 #define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12185 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
NYX 0:85b3fd62ea1a 12186 #define SPDIFRX_SR_PERR_Pos (2U)
NYX 0:85b3fd62ea1a 12187 #define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12188 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
NYX 0:85b3fd62ea1a 12189 #define SPDIFRX_SR_OVR_Pos (3U)
NYX 0:85b3fd62ea1a 12190 #define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12191 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
NYX 0:85b3fd62ea1a 12192 #define SPDIFRX_SR_SBD_Pos (4U)
NYX 0:85b3fd62ea1a 12193 #define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12194 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
NYX 0:85b3fd62ea1a 12195 #define SPDIFRX_SR_SYNCD_Pos (5U)
NYX 0:85b3fd62ea1a 12196 #define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12197 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
NYX 0:85b3fd62ea1a 12198 #define SPDIFRX_SR_FERR_Pos (6U)
NYX 0:85b3fd62ea1a 12199 #define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12200 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
NYX 0:85b3fd62ea1a 12201 #define SPDIFRX_SR_SERR_Pos (7U)
NYX 0:85b3fd62ea1a 12202 #define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12203 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
NYX 0:85b3fd62ea1a 12204 #define SPDIFRX_SR_TERR_Pos (8U)
NYX 0:85b3fd62ea1a 12205 #define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12206 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
NYX 0:85b3fd62ea1a 12207 #define SPDIFRX_SR_WIDTH5_Pos (16U)
NYX 0:85b3fd62ea1a 12208 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
NYX 0:85b3fd62ea1a 12209 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with SPDIFRX_clk */
NYX 0:85b3fd62ea1a 12210
NYX 0:85b3fd62ea1a 12211 /******************* Bit definition for SPDIFRX_IFCR register *******************/
NYX 0:85b3fd62ea1a 12212 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
NYX 0:85b3fd62ea1a 12213 #define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12214 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
NYX 0:85b3fd62ea1a 12215 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
NYX 0:85b3fd62ea1a 12216 #define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12217 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
NYX 0:85b3fd62ea1a 12218 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
NYX 0:85b3fd62ea1a 12219 #define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12220 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
NYX 0:85b3fd62ea1a 12221 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
NYX 0:85b3fd62ea1a 12222 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12223 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
NYX 0:85b3fd62ea1a 12224
NYX 0:85b3fd62ea1a 12225 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
NYX 0:85b3fd62ea1a 12226 #define SPDIFRX_DR0_DR_Pos (0U)
NYX 0:85b3fd62ea1a 12227 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
NYX 0:85b3fd62ea1a 12228 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
NYX 0:85b3fd62ea1a 12229 #define SPDIFRX_DR0_PE_Pos (24U)
NYX 0:85b3fd62ea1a 12230 #define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 12231 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
NYX 0:85b3fd62ea1a 12232 #define SPDIFRX_DR0_V_Pos (25U)
NYX 0:85b3fd62ea1a 12233 #define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 12234 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
NYX 0:85b3fd62ea1a 12235 #define SPDIFRX_DR0_U_Pos (26U)
NYX 0:85b3fd62ea1a 12236 #define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 12237 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
NYX 0:85b3fd62ea1a 12238 #define SPDIFRX_DR0_C_Pos (27U)
NYX 0:85b3fd62ea1a 12239 #define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 12240 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
NYX 0:85b3fd62ea1a 12241 #define SPDIFRX_DR0_PT_Pos (28U)
NYX 0:85b3fd62ea1a 12242 #define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
NYX 0:85b3fd62ea1a 12243 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
NYX 0:85b3fd62ea1a 12244
NYX 0:85b3fd62ea1a 12245 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
NYX 0:85b3fd62ea1a 12246 #define SPDIFRX_DR1_DR_Pos (8U)
NYX 0:85b3fd62ea1a 12247 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
NYX 0:85b3fd62ea1a 12248 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
NYX 0:85b3fd62ea1a 12249 #define SPDIFRX_DR1_PT_Pos (4U)
NYX 0:85b3fd62ea1a 12250 #define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 12251 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
NYX 0:85b3fd62ea1a 12252 #define SPDIFRX_DR1_C_Pos (3U)
NYX 0:85b3fd62ea1a 12253 #define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12254 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
NYX 0:85b3fd62ea1a 12255 #define SPDIFRX_DR1_U_Pos (2U)
NYX 0:85b3fd62ea1a 12256 #define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12257 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
NYX 0:85b3fd62ea1a 12258 #define SPDIFRX_DR1_V_Pos (1U)
NYX 0:85b3fd62ea1a 12259 #define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12260 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
NYX 0:85b3fd62ea1a 12261 #define SPDIFRX_DR1_PE_Pos (0U)
NYX 0:85b3fd62ea1a 12262 #define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12263 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
NYX 0:85b3fd62ea1a 12264
NYX 0:85b3fd62ea1a 12265 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
NYX 0:85b3fd62ea1a 12266 #define SPDIFRX_DR1_DRNL1_Pos (16U)
NYX 0:85b3fd62ea1a 12267 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 12268 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
NYX 0:85b3fd62ea1a 12269 #define SPDIFRX_DR1_DRNL2_Pos (0U)
NYX 0:85b3fd62ea1a 12270 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 12271 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
NYX 0:85b3fd62ea1a 12272
NYX 0:85b3fd62ea1a 12273 /******************* Bit definition for SPDIFRX_CSR register *******************/
NYX 0:85b3fd62ea1a 12274 #define SPDIFRX_CSR_USR_Pos (0U)
NYX 0:85b3fd62ea1a 12275 #define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 12276 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
NYX 0:85b3fd62ea1a 12277 #define SPDIFRX_CSR_CS_Pos (16U)
NYX 0:85b3fd62ea1a 12278 #define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 12279 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
NYX 0:85b3fd62ea1a 12280 #define SPDIFRX_CSR_SOB_Pos (24U)
NYX 0:85b3fd62ea1a 12281 #define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 12282 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
NYX 0:85b3fd62ea1a 12283
NYX 0:85b3fd62ea1a 12284 /******************* Bit definition for SPDIFRX_DIR register *******************/
NYX 0:85b3fd62ea1a 12285 #define SPDIFRX_DIR_THI_Pos (0U)
NYX 0:85b3fd62ea1a 12286 #define SPDIFRX_DIR_THI_Msk (0x13FFU << SPDIFRX_DIR_THI_Pos) /*!< 0x000013FF */
NYX 0:85b3fd62ea1a 12287 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
NYX 0:85b3fd62ea1a 12288 #define SPDIFRX_DIR_TLO_Pos (16U)
NYX 0:85b3fd62ea1a 12289 #define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
NYX 0:85b3fd62ea1a 12290 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
NYX 0:85b3fd62ea1a 12291
NYX 0:85b3fd62ea1a 12292
NYX 0:85b3fd62ea1a 12293 /******************************************************************************/
NYX 0:85b3fd62ea1a 12294 /* */
NYX 0:85b3fd62ea1a 12295 /* SD host Interface */
NYX 0:85b3fd62ea1a 12296 /* */
NYX 0:85b3fd62ea1a 12297 /******************************************************************************/
NYX 0:85b3fd62ea1a 12298 /****************** Bit definition for SDIO_POWER register ******************/
NYX 0:85b3fd62ea1a 12299 #define SDIO_POWER_PWRCTRL_Pos (0U)
NYX 0:85b3fd62ea1a 12300 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 12301 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
NYX 0:85b3fd62ea1a 12302 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
NYX 0:85b3fd62ea1a 12303 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
NYX 0:85b3fd62ea1a 12304
NYX 0:85b3fd62ea1a 12305 /****************** Bit definition for SDIO_CLKCR register ******************/
NYX 0:85b3fd62ea1a 12306 #define SDIO_CLKCR_CLKDIV_Pos (0U)
NYX 0:85b3fd62ea1a 12307 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 12308 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
NYX 0:85b3fd62ea1a 12309 #define SDIO_CLKCR_CLKEN_Pos (8U)
NYX 0:85b3fd62ea1a 12310 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12311 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
NYX 0:85b3fd62ea1a 12312 #define SDIO_CLKCR_PWRSAV_Pos (9U)
NYX 0:85b3fd62ea1a 12313 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 12314 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
NYX 0:85b3fd62ea1a 12315 #define SDIO_CLKCR_BYPASS_Pos (10U)
NYX 0:85b3fd62ea1a 12316 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12317 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
NYX 0:85b3fd62ea1a 12318
NYX 0:85b3fd62ea1a 12319 #define SDIO_CLKCR_WIDBUS_Pos (11U)
NYX 0:85b3fd62ea1a 12320 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
NYX 0:85b3fd62ea1a 12321 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
NYX 0:85b3fd62ea1a 12322 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
NYX 0:85b3fd62ea1a 12323 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
NYX 0:85b3fd62ea1a 12324
NYX 0:85b3fd62ea1a 12325 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
NYX 0:85b3fd62ea1a 12326 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 12327 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
NYX 0:85b3fd62ea1a 12328 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
NYX 0:85b3fd62ea1a 12329 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 12330 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
NYX 0:85b3fd62ea1a 12331
NYX 0:85b3fd62ea1a 12332 /******************* Bit definition for SDIO_ARG register *******************/
NYX 0:85b3fd62ea1a 12333 #define SDIO_ARG_CMDARG_Pos (0U)
NYX 0:85b3fd62ea1a 12334 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 12335 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
NYX 0:85b3fd62ea1a 12336
NYX 0:85b3fd62ea1a 12337 /******************* Bit definition for SDIO_CMD register *******************/
NYX 0:85b3fd62ea1a 12338 #define SDIO_CMD_CMDINDEX_Pos (0U)
NYX 0:85b3fd62ea1a 12339 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
NYX 0:85b3fd62ea1a 12340 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
NYX 0:85b3fd62ea1a 12341
NYX 0:85b3fd62ea1a 12342 #define SDIO_CMD_WAITRESP_Pos (6U)
NYX 0:85b3fd62ea1a 12343 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 12344 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
NYX 0:85b3fd62ea1a 12345 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 12346 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
NYX 0:85b3fd62ea1a 12347
NYX 0:85b3fd62ea1a 12348 #define SDIO_CMD_WAITINT_Pos (8U)
NYX 0:85b3fd62ea1a 12349 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12350 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
NYX 0:85b3fd62ea1a 12351 #define SDIO_CMD_WAITPEND_Pos (9U)
NYX 0:85b3fd62ea1a 12352 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 12353 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
NYX 0:85b3fd62ea1a 12354 #define SDIO_CMD_CPSMEN_Pos (10U)
NYX 0:85b3fd62ea1a 12355 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12356 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
NYX 0:85b3fd62ea1a 12357 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
NYX 0:85b3fd62ea1a 12358 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 12359 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
NYX 0:85b3fd62ea1a 12360
NYX 0:85b3fd62ea1a 12361 /***************** Bit definition for SDIO_RESPCMD register *****************/
NYX 0:85b3fd62ea1a 12362 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
NYX 0:85b3fd62ea1a 12363 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
NYX 0:85b3fd62ea1a 12364 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
NYX 0:85b3fd62ea1a 12365
NYX 0:85b3fd62ea1a 12366 /****************** Bit definition for SDIO_RESP0 register ******************/
NYX 0:85b3fd62ea1a 12367 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
NYX 0:85b3fd62ea1a 12368 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 12369 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
NYX 0:85b3fd62ea1a 12370
NYX 0:85b3fd62ea1a 12371 /****************** Bit definition for SDIO_RESP1 register ******************/
NYX 0:85b3fd62ea1a 12372 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
NYX 0:85b3fd62ea1a 12373 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 12374 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
NYX 0:85b3fd62ea1a 12375
NYX 0:85b3fd62ea1a 12376 /****************** Bit definition for SDIO_RESP2 register ******************/
NYX 0:85b3fd62ea1a 12377 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
NYX 0:85b3fd62ea1a 12378 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 12379 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
NYX 0:85b3fd62ea1a 12380
NYX 0:85b3fd62ea1a 12381 /****************** Bit definition for SDIO_RESP3 register ******************/
NYX 0:85b3fd62ea1a 12382 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
NYX 0:85b3fd62ea1a 12383 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 12384 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
NYX 0:85b3fd62ea1a 12385
NYX 0:85b3fd62ea1a 12386 /****************** Bit definition for SDIO_RESP4 register ******************/
NYX 0:85b3fd62ea1a 12387 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
NYX 0:85b3fd62ea1a 12388 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 12389 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
NYX 0:85b3fd62ea1a 12390
NYX 0:85b3fd62ea1a 12391 /****************** Bit definition for SDIO_DTIMER register *****************/
NYX 0:85b3fd62ea1a 12392 #define SDIO_DTIMER_DATATIME_Pos (0U)
NYX 0:85b3fd62ea1a 12393 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 12394 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
NYX 0:85b3fd62ea1a 12395
NYX 0:85b3fd62ea1a 12396 /****************** Bit definition for SDIO_DLEN register *******************/
NYX 0:85b3fd62ea1a 12397 #define SDIO_DLEN_DATALENGTH_Pos (0U)
NYX 0:85b3fd62ea1a 12398 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
NYX 0:85b3fd62ea1a 12399 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
NYX 0:85b3fd62ea1a 12400
NYX 0:85b3fd62ea1a 12401 /****************** Bit definition for SDIO_DCTRL register ******************/
NYX 0:85b3fd62ea1a 12402 #define SDIO_DCTRL_DTEN_Pos (0U)
NYX 0:85b3fd62ea1a 12403 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12404 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
NYX 0:85b3fd62ea1a 12405 #define SDIO_DCTRL_DTDIR_Pos (1U)
NYX 0:85b3fd62ea1a 12406 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12407 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
NYX 0:85b3fd62ea1a 12408 #define SDIO_DCTRL_DTMODE_Pos (2U)
NYX 0:85b3fd62ea1a 12409 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12410 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
NYX 0:85b3fd62ea1a 12411 #define SDIO_DCTRL_DMAEN_Pos (3U)
NYX 0:85b3fd62ea1a 12412 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12413 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
NYX 0:85b3fd62ea1a 12414
NYX 0:85b3fd62ea1a 12415 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
NYX 0:85b3fd62ea1a 12416 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 12417 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
NYX 0:85b3fd62ea1a 12418 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 12419 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 12420 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 12421 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
NYX 0:85b3fd62ea1a 12422
NYX 0:85b3fd62ea1a 12423 #define SDIO_DCTRL_RWSTART_Pos (8U)
NYX 0:85b3fd62ea1a 12424 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12425 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
NYX 0:85b3fd62ea1a 12426 #define SDIO_DCTRL_RWSTOP_Pos (9U)
NYX 0:85b3fd62ea1a 12427 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 12428 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
NYX 0:85b3fd62ea1a 12429 #define SDIO_DCTRL_RWMOD_Pos (10U)
NYX 0:85b3fd62ea1a 12430 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12431 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
NYX 0:85b3fd62ea1a 12432 #define SDIO_DCTRL_SDIOEN_Pos (11U)
NYX 0:85b3fd62ea1a 12433 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 12434 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
NYX 0:85b3fd62ea1a 12435
NYX 0:85b3fd62ea1a 12436 /****************** Bit definition for SDIO_DCOUNT register *****************/
NYX 0:85b3fd62ea1a 12437 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
NYX 0:85b3fd62ea1a 12438 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
NYX 0:85b3fd62ea1a 12439 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
NYX 0:85b3fd62ea1a 12440
NYX 0:85b3fd62ea1a 12441 /****************** Bit definition for SDIO_STA register ********************/
NYX 0:85b3fd62ea1a 12442 #define SDIO_STA_CCRCFAIL_Pos (0U)
NYX 0:85b3fd62ea1a 12443 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12444 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
NYX 0:85b3fd62ea1a 12445 #define SDIO_STA_DCRCFAIL_Pos (1U)
NYX 0:85b3fd62ea1a 12446 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12447 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
NYX 0:85b3fd62ea1a 12448 #define SDIO_STA_CTIMEOUT_Pos (2U)
NYX 0:85b3fd62ea1a 12449 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12450 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
NYX 0:85b3fd62ea1a 12451 #define SDIO_STA_DTIMEOUT_Pos (3U)
NYX 0:85b3fd62ea1a 12452 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12453 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
NYX 0:85b3fd62ea1a 12454 #define SDIO_STA_TXUNDERR_Pos (4U)
NYX 0:85b3fd62ea1a 12455 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12456 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
NYX 0:85b3fd62ea1a 12457 #define SDIO_STA_RXOVERR_Pos (5U)
NYX 0:85b3fd62ea1a 12458 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12459 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
NYX 0:85b3fd62ea1a 12460 #define SDIO_STA_CMDREND_Pos (6U)
NYX 0:85b3fd62ea1a 12461 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12462 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
NYX 0:85b3fd62ea1a 12463 #define SDIO_STA_CMDSENT_Pos (7U)
NYX 0:85b3fd62ea1a 12464 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12465 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
NYX 0:85b3fd62ea1a 12466 #define SDIO_STA_DATAEND_Pos (8U)
NYX 0:85b3fd62ea1a 12467 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12468 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
NYX 0:85b3fd62ea1a 12469 #define SDIO_STA_DBCKEND_Pos (10U)
NYX 0:85b3fd62ea1a 12470 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12471 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
NYX 0:85b3fd62ea1a 12472 #define SDIO_STA_CMDACT_Pos (11U)
NYX 0:85b3fd62ea1a 12473 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 12474 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
NYX 0:85b3fd62ea1a 12475 #define SDIO_STA_TXACT_Pos (12U)
NYX 0:85b3fd62ea1a 12476 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 12477 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
NYX 0:85b3fd62ea1a 12478 #define SDIO_STA_RXACT_Pos (13U)
NYX 0:85b3fd62ea1a 12479 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 12480 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
NYX 0:85b3fd62ea1a 12481 #define SDIO_STA_TXFIFOHE_Pos (14U)
NYX 0:85b3fd62ea1a 12482 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 12483 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
NYX 0:85b3fd62ea1a 12484 #define SDIO_STA_RXFIFOHF_Pos (15U)
NYX 0:85b3fd62ea1a 12485 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 12486 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
NYX 0:85b3fd62ea1a 12487 #define SDIO_STA_TXFIFOF_Pos (16U)
NYX 0:85b3fd62ea1a 12488 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 12489 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
NYX 0:85b3fd62ea1a 12490 #define SDIO_STA_RXFIFOF_Pos (17U)
NYX 0:85b3fd62ea1a 12491 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 12492 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
NYX 0:85b3fd62ea1a 12493 #define SDIO_STA_TXFIFOE_Pos (18U)
NYX 0:85b3fd62ea1a 12494 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 12495 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
NYX 0:85b3fd62ea1a 12496 #define SDIO_STA_RXFIFOE_Pos (19U)
NYX 0:85b3fd62ea1a 12497 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 12498 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
NYX 0:85b3fd62ea1a 12499 #define SDIO_STA_TXDAVL_Pos (20U)
NYX 0:85b3fd62ea1a 12500 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 12501 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
NYX 0:85b3fd62ea1a 12502 #define SDIO_STA_RXDAVL_Pos (21U)
NYX 0:85b3fd62ea1a 12503 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 12504 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
NYX 0:85b3fd62ea1a 12505 #define SDIO_STA_SDIOIT_Pos (22U)
NYX 0:85b3fd62ea1a 12506 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 12507 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
NYX 0:85b3fd62ea1a 12508
NYX 0:85b3fd62ea1a 12509 /******************* Bit definition for SDIO_ICR register *******************/
NYX 0:85b3fd62ea1a 12510 #define SDIO_ICR_CCRCFAILC_Pos (0U)
NYX 0:85b3fd62ea1a 12511 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12512 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
NYX 0:85b3fd62ea1a 12513 #define SDIO_ICR_DCRCFAILC_Pos (1U)
NYX 0:85b3fd62ea1a 12514 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12515 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
NYX 0:85b3fd62ea1a 12516 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
NYX 0:85b3fd62ea1a 12517 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12518 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
NYX 0:85b3fd62ea1a 12519 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
NYX 0:85b3fd62ea1a 12520 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12521 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
NYX 0:85b3fd62ea1a 12522 #define SDIO_ICR_TXUNDERRC_Pos (4U)
NYX 0:85b3fd62ea1a 12523 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12524 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
NYX 0:85b3fd62ea1a 12525 #define SDIO_ICR_RXOVERRC_Pos (5U)
NYX 0:85b3fd62ea1a 12526 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12527 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
NYX 0:85b3fd62ea1a 12528 #define SDIO_ICR_CMDRENDC_Pos (6U)
NYX 0:85b3fd62ea1a 12529 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12530 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
NYX 0:85b3fd62ea1a 12531 #define SDIO_ICR_CMDSENTC_Pos (7U)
NYX 0:85b3fd62ea1a 12532 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12533 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
NYX 0:85b3fd62ea1a 12534 #define SDIO_ICR_DATAENDC_Pos (8U)
NYX 0:85b3fd62ea1a 12535 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12536 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
NYX 0:85b3fd62ea1a 12537 #define SDIO_ICR_DBCKENDC_Pos (10U)
NYX 0:85b3fd62ea1a 12538 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12539 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
NYX 0:85b3fd62ea1a 12540 #define SDIO_ICR_SDIOITC_Pos (22U)
NYX 0:85b3fd62ea1a 12541 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 12542 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
NYX 0:85b3fd62ea1a 12543
NYX 0:85b3fd62ea1a 12544 /****************** Bit definition for SDIO_MASK register *******************/
NYX 0:85b3fd62ea1a 12545 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
NYX 0:85b3fd62ea1a 12546 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12547 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
NYX 0:85b3fd62ea1a 12548 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
NYX 0:85b3fd62ea1a 12549 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12550 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
NYX 0:85b3fd62ea1a 12551 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
NYX 0:85b3fd62ea1a 12552 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12553 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
NYX 0:85b3fd62ea1a 12554 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
NYX 0:85b3fd62ea1a 12555 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12556 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
NYX 0:85b3fd62ea1a 12557 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
NYX 0:85b3fd62ea1a 12558 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12559 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
NYX 0:85b3fd62ea1a 12560 #define SDIO_MASK_RXOVERRIE_Pos (5U)
NYX 0:85b3fd62ea1a 12561 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12562 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
NYX 0:85b3fd62ea1a 12563 #define SDIO_MASK_CMDRENDIE_Pos (6U)
NYX 0:85b3fd62ea1a 12564 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12565 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
NYX 0:85b3fd62ea1a 12566 #define SDIO_MASK_CMDSENTIE_Pos (7U)
NYX 0:85b3fd62ea1a 12567 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12568 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
NYX 0:85b3fd62ea1a 12569 #define SDIO_MASK_DATAENDIE_Pos (8U)
NYX 0:85b3fd62ea1a 12570 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12571 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
NYX 0:85b3fd62ea1a 12572 #define SDIO_MASK_DBCKENDIE_Pos (10U)
NYX 0:85b3fd62ea1a 12573 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12574 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
NYX 0:85b3fd62ea1a 12575 #define SDIO_MASK_CMDACTIE_Pos (11U)
NYX 0:85b3fd62ea1a 12576 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 12577 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
NYX 0:85b3fd62ea1a 12578 #define SDIO_MASK_TXACTIE_Pos (12U)
NYX 0:85b3fd62ea1a 12579 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 12580 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
NYX 0:85b3fd62ea1a 12581 #define SDIO_MASK_RXACTIE_Pos (13U)
NYX 0:85b3fd62ea1a 12582 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 12583 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
NYX 0:85b3fd62ea1a 12584 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
NYX 0:85b3fd62ea1a 12585 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 12586 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
NYX 0:85b3fd62ea1a 12587 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
NYX 0:85b3fd62ea1a 12588 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 12589 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
NYX 0:85b3fd62ea1a 12590 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
NYX 0:85b3fd62ea1a 12591 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 12592 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
NYX 0:85b3fd62ea1a 12593 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
NYX 0:85b3fd62ea1a 12594 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 12595 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
NYX 0:85b3fd62ea1a 12596 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
NYX 0:85b3fd62ea1a 12597 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 12598 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
NYX 0:85b3fd62ea1a 12599 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
NYX 0:85b3fd62ea1a 12600 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 12601 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
NYX 0:85b3fd62ea1a 12602 #define SDIO_MASK_TXDAVLIE_Pos (20U)
NYX 0:85b3fd62ea1a 12603 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 12604 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
NYX 0:85b3fd62ea1a 12605 #define SDIO_MASK_RXDAVLIE_Pos (21U)
NYX 0:85b3fd62ea1a 12606 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 12607 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
NYX 0:85b3fd62ea1a 12608 #define SDIO_MASK_SDIOITIE_Pos (22U)
NYX 0:85b3fd62ea1a 12609 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 12610 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
NYX 0:85b3fd62ea1a 12611
NYX 0:85b3fd62ea1a 12612 /***************** Bit definition for SDIO_FIFOCNT register *****************/
NYX 0:85b3fd62ea1a 12613 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
NYX 0:85b3fd62ea1a 12614 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
NYX 0:85b3fd62ea1a 12615 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
NYX 0:85b3fd62ea1a 12616
NYX 0:85b3fd62ea1a 12617 /****************** Bit definition for SDIO_FIFO register *******************/
NYX 0:85b3fd62ea1a 12618 #define SDIO_FIFO_FIFODATA_Pos (0U)
NYX 0:85b3fd62ea1a 12619 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 12620 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
NYX 0:85b3fd62ea1a 12621
NYX 0:85b3fd62ea1a 12622 /******************************************************************************/
NYX 0:85b3fd62ea1a 12623 /* */
NYX 0:85b3fd62ea1a 12624 /* Serial Peripheral Interface */
NYX 0:85b3fd62ea1a 12625 /* */
NYX 0:85b3fd62ea1a 12626 /******************************************************************************/
NYX 0:85b3fd62ea1a 12627 #define I2S_APB1_APB2_FEATURE /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
NYX 0:85b3fd62ea1a 12628
NYX 0:85b3fd62ea1a 12629 /******************* Bit definition for SPI_CR1 register ********************/
NYX 0:85b3fd62ea1a 12630 #define SPI_CR1_CPHA_Pos (0U)
NYX 0:85b3fd62ea1a 12631 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12632 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
NYX 0:85b3fd62ea1a 12633 #define SPI_CR1_CPOL_Pos (1U)
NYX 0:85b3fd62ea1a 12634 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12635 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
NYX 0:85b3fd62ea1a 12636 #define SPI_CR1_MSTR_Pos (2U)
NYX 0:85b3fd62ea1a 12637 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12638 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
NYX 0:85b3fd62ea1a 12639
NYX 0:85b3fd62ea1a 12640 #define SPI_CR1_BR_Pos (3U)
NYX 0:85b3fd62ea1a 12641 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
NYX 0:85b3fd62ea1a 12642 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
NYX 0:85b3fd62ea1a 12643 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12644 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12645 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12646
NYX 0:85b3fd62ea1a 12647 #define SPI_CR1_SPE_Pos (6U)
NYX 0:85b3fd62ea1a 12648 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12649 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
NYX 0:85b3fd62ea1a 12650 #define SPI_CR1_LSBFIRST_Pos (7U)
NYX 0:85b3fd62ea1a 12651 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12652 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
NYX 0:85b3fd62ea1a 12653 #define SPI_CR1_SSI_Pos (8U)
NYX 0:85b3fd62ea1a 12654 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12655 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
NYX 0:85b3fd62ea1a 12656 #define SPI_CR1_SSM_Pos (9U)
NYX 0:85b3fd62ea1a 12657 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 12658 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
NYX 0:85b3fd62ea1a 12659 #define SPI_CR1_RXONLY_Pos (10U)
NYX 0:85b3fd62ea1a 12660 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12661 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
NYX 0:85b3fd62ea1a 12662 #define SPI_CR1_DFF_Pos (11U)
NYX 0:85b3fd62ea1a 12663 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 12664 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
NYX 0:85b3fd62ea1a 12665 #define SPI_CR1_CRCNEXT_Pos (12U)
NYX 0:85b3fd62ea1a 12666 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 12667 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
NYX 0:85b3fd62ea1a 12668 #define SPI_CR1_CRCEN_Pos (13U)
NYX 0:85b3fd62ea1a 12669 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 12670 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
NYX 0:85b3fd62ea1a 12671 #define SPI_CR1_BIDIOE_Pos (14U)
NYX 0:85b3fd62ea1a 12672 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 12673 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
NYX 0:85b3fd62ea1a 12674 #define SPI_CR1_BIDIMODE_Pos (15U)
NYX 0:85b3fd62ea1a 12675 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 12676 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
NYX 0:85b3fd62ea1a 12677
NYX 0:85b3fd62ea1a 12678 /******************* Bit definition for SPI_CR2 register ********************/
NYX 0:85b3fd62ea1a 12679 #define SPI_CR2_RXDMAEN_Pos (0U)
NYX 0:85b3fd62ea1a 12680 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12681 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
NYX 0:85b3fd62ea1a 12682 #define SPI_CR2_TXDMAEN_Pos (1U)
NYX 0:85b3fd62ea1a 12683 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12684 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
NYX 0:85b3fd62ea1a 12685 #define SPI_CR2_SSOE_Pos (2U)
NYX 0:85b3fd62ea1a 12686 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12687 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
NYX 0:85b3fd62ea1a 12688 #define SPI_CR2_FRF_Pos (4U)
NYX 0:85b3fd62ea1a 12689 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12690 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
NYX 0:85b3fd62ea1a 12691 #define SPI_CR2_ERRIE_Pos (5U)
NYX 0:85b3fd62ea1a 12692 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12693 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
NYX 0:85b3fd62ea1a 12694 #define SPI_CR2_RXNEIE_Pos (6U)
NYX 0:85b3fd62ea1a 12695 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12696 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
NYX 0:85b3fd62ea1a 12697 #define SPI_CR2_TXEIE_Pos (7U)
NYX 0:85b3fd62ea1a 12698 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12699 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
NYX 0:85b3fd62ea1a 12700
NYX 0:85b3fd62ea1a 12701 /******************** Bit definition for SPI_SR register ********************/
NYX 0:85b3fd62ea1a 12702 #define SPI_SR_RXNE_Pos (0U)
NYX 0:85b3fd62ea1a 12703 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12704 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
NYX 0:85b3fd62ea1a 12705 #define SPI_SR_TXE_Pos (1U)
NYX 0:85b3fd62ea1a 12706 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12707 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
NYX 0:85b3fd62ea1a 12708 #define SPI_SR_CHSIDE_Pos (2U)
NYX 0:85b3fd62ea1a 12709 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12710 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
NYX 0:85b3fd62ea1a 12711 #define SPI_SR_UDR_Pos (3U)
NYX 0:85b3fd62ea1a 12712 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12713 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
NYX 0:85b3fd62ea1a 12714 #define SPI_SR_CRCERR_Pos (4U)
NYX 0:85b3fd62ea1a 12715 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12716 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
NYX 0:85b3fd62ea1a 12717 #define SPI_SR_MODF_Pos (5U)
NYX 0:85b3fd62ea1a 12718 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12719 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
NYX 0:85b3fd62ea1a 12720 #define SPI_SR_OVR_Pos (6U)
NYX 0:85b3fd62ea1a 12721 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 12722 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
NYX 0:85b3fd62ea1a 12723 #define SPI_SR_BSY_Pos (7U)
NYX 0:85b3fd62ea1a 12724 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12725 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
NYX 0:85b3fd62ea1a 12726 #define SPI_SR_FRE_Pos (8U)
NYX 0:85b3fd62ea1a 12727 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12728 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
NYX 0:85b3fd62ea1a 12729
NYX 0:85b3fd62ea1a 12730 /******************** Bit definition for SPI_DR register ********************/
NYX 0:85b3fd62ea1a 12731 #define SPI_DR_DR_Pos (0U)
NYX 0:85b3fd62ea1a 12732 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 12733 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
NYX 0:85b3fd62ea1a 12734
NYX 0:85b3fd62ea1a 12735 /******************* Bit definition for SPI_CRCPR register ******************/
NYX 0:85b3fd62ea1a 12736 #define SPI_CRCPR_CRCPOLY_Pos (0U)
NYX 0:85b3fd62ea1a 12737 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 12738 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
NYX 0:85b3fd62ea1a 12739
NYX 0:85b3fd62ea1a 12740 /****************** Bit definition for SPI_RXCRCR register ******************/
NYX 0:85b3fd62ea1a 12741 #define SPI_RXCRCR_RXCRC_Pos (0U)
NYX 0:85b3fd62ea1a 12742 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 12743 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
NYX 0:85b3fd62ea1a 12744
NYX 0:85b3fd62ea1a 12745 /****************** Bit definition for SPI_TXCRCR register ******************/
NYX 0:85b3fd62ea1a 12746 #define SPI_TXCRCR_TXCRC_Pos (0U)
NYX 0:85b3fd62ea1a 12747 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 12748 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
NYX 0:85b3fd62ea1a 12749
NYX 0:85b3fd62ea1a 12750 /****************** Bit definition for SPI_I2SCFGR register *****************/
NYX 0:85b3fd62ea1a 12751 #define SPI_I2SCFGR_CHLEN_Pos (0U)
NYX 0:85b3fd62ea1a 12752 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12753 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
NYX 0:85b3fd62ea1a 12754
NYX 0:85b3fd62ea1a 12755 #define SPI_I2SCFGR_DATLEN_Pos (1U)
NYX 0:85b3fd62ea1a 12756 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
NYX 0:85b3fd62ea1a 12757 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
NYX 0:85b3fd62ea1a 12758 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12759 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12760
NYX 0:85b3fd62ea1a 12761 #define SPI_I2SCFGR_CKPOL_Pos (3U)
NYX 0:85b3fd62ea1a 12762 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 12763 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
NYX 0:85b3fd62ea1a 12764
NYX 0:85b3fd62ea1a 12765 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
NYX 0:85b3fd62ea1a 12766 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
NYX 0:85b3fd62ea1a 12767 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
NYX 0:85b3fd62ea1a 12768 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 12769 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 12770
NYX 0:85b3fd62ea1a 12771 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
NYX 0:85b3fd62ea1a 12772 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 12773 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
NYX 0:85b3fd62ea1a 12774
NYX 0:85b3fd62ea1a 12775 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
NYX 0:85b3fd62ea1a 12776 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 12777 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
NYX 0:85b3fd62ea1a 12778 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12779 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 12780
NYX 0:85b3fd62ea1a 12781 #define SPI_I2SCFGR_I2SE_Pos (10U)
NYX 0:85b3fd62ea1a 12782 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12783 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
NYX 0:85b3fd62ea1a 12784 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
NYX 0:85b3fd62ea1a 12785 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 12786 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
NYX 0:85b3fd62ea1a 12787 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
NYX 0:85b3fd62ea1a 12788 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 12789 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
NYX 0:85b3fd62ea1a 12790
NYX 0:85b3fd62ea1a 12791 /****************** Bit definition for SPI_I2SPR register *******************/
NYX 0:85b3fd62ea1a 12792 #define SPI_I2SPR_I2SDIV_Pos (0U)
NYX 0:85b3fd62ea1a 12793 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 12794 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
NYX 0:85b3fd62ea1a 12795 #define SPI_I2SPR_ODD_Pos (8U)
NYX 0:85b3fd62ea1a 12796 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12797 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
NYX 0:85b3fd62ea1a 12798 #define SPI_I2SPR_MCKOE_Pos (9U)
NYX 0:85b3fd62ea1a 12799 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 12800 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
NYX 0:85b3fd62ea1a 12801
NYX 0:85b3fd62ea1a 12802 /******************************************************************************/
NYX 0:85b3fd62ea1a 12803 /* */
NYX 0:85b3fd62ea1a 12804 /* SYSCFG */
NYX 0:85b3fd62ea1a 12805 /* */
NYX 0:85b3fd62ea1a 12806 /******************************************************************************/
NYX 0:85b3fd62ea1a 12807 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
NYX 0:85b3fd62ea1a 12808 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
NYX 0:85b3fd62ea1a 12809 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 12810 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
NYX 0:85b3fd62ea1a 12811 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 12812 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 12813 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 12814 #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
NYX 0:85b3fd62ea1a 12815 #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 12816 #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
NYX 0:85b3fd62ea1a 12817 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
NYX 0:85b3fd62ea1a 12818 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 12819 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
NYX 0:85b3fd62ea1a 12820 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 12821 /* Legacy Defines */
NYX 0:85b3fd62ea1a 12822 #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
NYX 0:85b3fd62ea1a 12823 /****************** Bit definition for SYSCFG_PMC register ******************/
NYX 0:85b3fd62ea1a 12824 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
NYX 0:85b3fd62ea1a 12825 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
NYX 0:85b3fd62ea1a 12826 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
NYX 0:85b3fd62ea1a 12827 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
NYX 0:85b3fd62ea1a 12828 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 12829 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
NYX 0:85b3fd62ea1a 12830 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
NYX 0:85b3fd62ea1a 12831 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 12832 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
NYX 0:85b3fd62ea1a 12833 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
NYX 0:85b3fd62ea1a 12834 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 12835 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
NYX 0:85b3fd62ea1a 12836
NYX 0:85b3fd62ea1a 12837 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
NYX 0:85b3fd62ea1a 12838 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
NYX 0:85b3fd62ea1a 12839 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 12840 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
NYX 0:85b3fd62ea1a 12841 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
NYX 0:85b3fd62ea1a 12842 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 12843 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
NYX 0:85b3fd62ea1a 12844 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
NYX 0:85b3fd62ea1a 12845 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 12846 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
NYX 0:85b3fd62ea1a 12847 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
NYX 0:85b3fd62ea1a 12848 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 12849 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
NYX 0:85b3fd62ea1a 12850 /**
NYX 0:85b3fd62ea1a 12851 * @brief EXTI0 configuration
NYX 0:85b3fd62ea1a 12852 */
NYX 0:85b3fd62ea1a 12853 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
NYX 0:85b3fd62ea1a 12854 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
NYX 0:85b3fd62ea1a 12855 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
NYX 0:85b3fd62ea1a 12856 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
NYX 0:85b3fd62ea1a 12857 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
NYX 0:85b3fd62ea1a 12858 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
NYX 0:85b3fd62ea1a 12859 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
NYX 0:85b3fd62ea1a 12860 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
NYX 0:85b3fd62ea1a 12861 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
NYX 0:85b3fd62ea1a 12862 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
NYX 0:85b3fd62ea1a 12863 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
NYX 0:85b3fd62ea1a 12864
NYX 0:85b3fd62ea1a 12865 /**
NYX 0:85b3fd62ea1a 12866 * @brief EXTI1 configuration
NYX 0:85b3fd62ea1a 12867 */
NYX 0:85b3fd62ea1a 12868 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
NYX 0:85b3fd62ea1a 12869 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
NYX 0:85b3fd62ea1a 12870 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
NYX 0:85b3fd62ea1a 12871 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
NYX 0:85b3fd62ea1a 12872 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
NYX 0:85b3fd62ea1a 12873 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
NYX 0:85b3fd62ea1a 12874 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
NYX 0:85b3fd62ea1a 12875 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
NYX 0:85b3fd62ea1a 12876 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
NYX 0:85b3fd62ea1a 12877 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
NYX 0:85b3fd62ea1a 12878 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
NYX 0:85b3fd62ea1a 12879
NYX 0:85b3fd62ea1a 12880 /**
NYX 0:85b3fd62ea1a 12881 * @brief EXTI2 configuration
NYX 0:85b3fd62ea1a 12882 */
NYX 0:85b3fd62ea1a 12883 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
NYX 0:85b3fd62ea1a 12884 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
NYX 0:85b3fd62ea1a 12885 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
NYX 0:85b3fd62ea1a 12886 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
NYX 0:85b3fd62ea1a 12887 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
NYX 0:85b3fd62ea1a 12888 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
NYX 0:85b3fd62ea1a 12889 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
NYX 0:85b3fd62ea1a 12890 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
NYX 0:85b3fd62ea1a 12891 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
NYX 0:85b3fd62ea1a 12892 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
NYX 0:85b3fd62ea1a 12893 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
NYX 0:85b3fd62ea1a 12894
NYX 0:85b3fd62ea1a 12895 /**
NYX 0:85b3fd62ea1a 12896 * @brief EXTI3 configuration
NYX 0:85b3fd62ea1a 12897 */
NYX 0:85b3fd62ea1a 12898 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
NYX 0:85b3fd62ea1a 12899 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
NYX 0:85b3fd62ea1a 12900 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
NYX 0:85b3fd62ea1a 12901 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
NYX 0:85b3fd62ea1a 12902 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
NYX 0:85b3fd62ea1a 12903 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
NYX 0:85b3fd62ea1a 12904 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
NYX 0:85b3fd62ea1a 12905 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
NYX 0:85b3fd62ea1a 12906 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
NYX 0:85b3fd62ea1a 12907 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
NYX 0:85b3fd62ea1a 12908 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
NYX 0:85b3fd62ea1a 12909
NYX 0:85b3fd62ea1a 12910 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
NYX 0:85b3fd62ea1a 12911 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
NYX 0:85b3fd62ea1a 12912 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 12913 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
NYX 0:85b3fd62ea1a 12914 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
NYX 0:85b3fd62ea1a 12915 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 12916 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
NYX 0:85b3fd62ea1a 12917 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
NYX 0:85b3fd62ea1a 12918 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 12919 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
NYX 0:85b3fd62ea1a 12920 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
NYX 0:85b3fd62ea1a 12921 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 12922 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
NYX 0:85b3fd62ea1a 12923
NYX 0:85b3fd62ea1a 12924 /**
NYX 0:85b3fd62ea1a 12925 * @brief EXTI4 configuration
NYX 0:85b3fd62ea1a 12926 */
NYX 0:85b3fd62ea1a 12927 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
NYX 0:85b3fd62ea1a 12928 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
NYX 0:85b3fd62ea1a 12929 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
NYX 0:85b3fd62ea1a 12930 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
NYX 0:85b3fd62ea1a 12931 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
NYX 0:85b3fd62ea1a 12932 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
NYX 0:85b3fd62ea1a 12933 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
NYX 0:85b3fd62ea1a 12934 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
NYX 0:85b3fd62ea1a 12935 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
NYX 0:85b3fd62ea1a 12936 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
NYX 0:85b3fd62ea1a 12937 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
NYX 0:85b3fd62ea1a 12938
NYX 0:85b3fd62ea1a 12939 /**
NYX 0:85b3fd62ea1a 12940 * @brief EXTI5 configuration
NYX 0:85b3fd62ea1a 12941 */
NYX 0:85b3fd62ea1a 12942 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
NYX 0:85b3fd62ea1a 12943 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
NYX 0:85b3fd62ea1a 12944 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
NYX 0:85b3fd62ea1a 12945 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
NYX 0:85b3fd62ea1a 12946 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
NYX 0:85b3fd62ea1a 12947 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
NYX 0:85b3fd62ea1a 12948 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
NYX 0:85b3fd62ea1a 12949 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
NYX 0:85b3fd62ea1a 12950 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
NYX 0:85b3fd62ea1a 12951 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
NYX 0:85b3fd62ea1a 12952 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
NYX 0:85b3fd62ea1a 12953
NYX 0:85b3fd62ea1a 12954 /**
NYX 0:85b3fd62ea1a 12955 * @brief EXTI6 configuration
NYX 0:85b3fd62ea1a 12956 */
NYX 0:85b3fd62ea1a 12957 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
NYX 0:85b3fd62ea1a 12958 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
NYX 0:85b3fd62ea1a 12959 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
NYX 0:85b3fd62ea1a 12960 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
NYX 0:85b3fd62ea1a 12961 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
NYX 0:85b3fd62ea1a 12962 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
NYX 0:85b3fd62ea1a 12963 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
NYX 0:85b3fd62ea1a 12964 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
NYX 0:85b3fd62ea1a 12965 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
NYX 0:85b3fd62ea1a 12966 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
NYX 0:85b3fd62ea1a 12967 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
NYX 0:85b3fd62ea1a 12968
NYX 0:85b3fd62ea1a 12969 /**
NYX 0:85b3fd62ea1a 12970 * @brief EXTI7 configuration
NYX 0:85b3fd62ea1a 12971 */
NYX 0:85b3fd62ea1a 12972 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
NYX 0:85b3fd62ea1a 12973 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
NYX 0:85b3fd62ea1a 12974 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
NYX 0:85b3fd62ea1a 12975 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
NYX 0:85b3fd62ea1a 12976 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
NYX 0:85b3fd62ea1a 12977 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
NYX 0:85b3fd62ea1a 12978 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
NYX 0:85b3fd62ea1a 12979 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
NYX 0:85b3fd62ea1a 12980 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
NYX 0:85b3fd62ea1a 12981 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
NYX 0:85b3fd62ea1a 12982 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
NYX 0:85b3fd62ea1a 12983
NYX 0:85b3fd62ea1a 12984 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
NYX 0:85b3fd62ea1a 12985 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
NYX 0:85b3fd62ea1a 12986 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 12987 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
NYX 0:85b3fd62ea1a 12988 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
NYX 0:85b3fd62ea1a 12989 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 12990 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
NYX 0:85b3fd62ea1a 12991 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
NYX 0:85b3fd62ea1a 12992 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 12993 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
NYX 0:85b3fd62ea1a 12994 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
NYX 0:85b3fd62ea1a 12995 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 12996 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
NYX 0:85b3fd62ea1a 12997
NYX 0:85b3fd62ea1a 12998 /**
NYX 0:85b3fd62ea1a 12999 * @brief EXTI8 configuration
NYX 0:85b3fd62ea1a 13000 */
NYX 0:85b3fd62ea1a 13001 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
NYX 0:85b3fd62ea1a 13002 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
NYX 0:85b3fd62ea1a 13003 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
NYX 0:85b3fd62ea1a 13004 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
NYX 0:85b3fd62ea1a 13005 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
NYX 0:85b3fd62ea1a 13006 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
NYX 0:85b3fd62ea1a 13007 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
NYX 0:85b3fd62ea1a 13008 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
NYX 0:85b3fd62ea1a 13009 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
NYX 0:85b3fd62ea1a 13010 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
NYX 0:85b3fd62ea1a 13011
NYX 0:85b3fd62ea1a 13012 /**
NYX 0:85b3fd62ea1a 13013 * @brief EXTI9 configuration
NYX 0:85b3fd62ea1a 13014 */
NYX 0:85b3fd62ea1a 13015 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
NYX 0:85b3fd62ea1a 13016 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
NYX 0:85b3fd62ea1a 13017 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
NYX 0:85b3fd62ea1a 13018 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
NYX 0:85b3fd62ea1a 13019 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
NYX 0:85b3fd62ea1a 13020 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
NYX 0:85b3fd62ea1a 13021 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
NYX 0:85b3fd62ea1a 13022 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
NYX 0:85b3fd62ea1a 13023 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
NYX 0:85b3fd62ea1a 13024 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
NYX 0:85b3fd62ea1a 13025
NYX 0:85b3fd62ea1a 13026 /**
NYX 0:85b3fd62ea1a 13027 * @brief EXTI10 configuration
NYX 0:85b3fd62ea1a 13028 */
NYX 0:85b3fd62ea1a 13029 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
NYX 0:85b3fd62ea1a 13030 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
NYX 0:85b3fd62ea1a 13031 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
NYX 0:85b3fd62ea1a 13032 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
NYX 0:85b3fd62ea1a 13033 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
NYX 0:85b3fd62ea1a 13034 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
NYX 0:85b3fd62ea1a 13035 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
NYX 0:85b3fd62ea1a 13036 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
NYX 0:85b3fd62ea1a 13037 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
NYX 0:85b3fd62ea1a 13038 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
NYX 0:85b3fd62ea1a 13039
NYX 0:85b3fd62ea1a 13040 /**
NYX 0:85b3fd62ea1a 13041 * @brief EXTI11 configuration
NYX 0:85b3fd62ea1a 13042 */
NYX 0:85b3fd62ea1a 13043 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
NYX 0:85b3fd62ea1a 13044 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
NYX 0:85b3fd62ea1a 13045 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
NYX 0:85b3fd62ea1a 13046 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
NYX 0:85b3fd62ea1a 13047 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
NYX 0:85b3fd62ea1a 13048 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
NYX 0:85b3fd62ea1a 13049 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
NYX 0:85b3fd62ea1a 13050 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
NYX 0:85b3fd62ea1a 13051 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
NYX 0:85b3fd62ea1a 13052 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
NYX 0:85b3fd62ea1a 13053
NYX 0:85b3fd62ea1a 13054
NYX 0:85b3fd62ea1a 13055 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
NYX 0:85b3fd62ea1a 13056 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
NYX 0:85b3fd62ea1a 13057 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 13058 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
NYX 0:85b3fd62ea1a 13059 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
NYX 0:85b3fd62ea1a 13060 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 13061 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
NYX 0:85b3fd62ea1a 13062 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
NYX 0:85b3fd62ea1a 13063 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 13064 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
NYX 0:85b3fd62ea1a 13065 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
NYX 0:85b3fd62ea1a 13066 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 13067 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
NYX 0:85b3fd62ea1a 13068
NYX 0:85b3fd62ea1a 13069 /**
NYX 0:85b3fd62ea1a 13070 * @brief EXTI12 configuration
NYX 0:85b3fd62ea1a 13071 */
NYX 0:85b3fd62ea1a 13072 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
NYX 0:85b3fd62ea1a 13073 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
NYX 0:85b3fd62ea1a 13074 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
NYX 0:85b3fd62ea1a 13075 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
NYX 0:85b3fd62ea1a 13076 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
NYX 0:85b3fd62ea1a 13077 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
NYX 0:85b3fd62ea1a 13078 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
NYX 0:85b3fd62ea1a 13079 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
NYX 0:85b3fd62ea1a 13080 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
NYX 0:85b3fd62ea1a 13081 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
NYX 0:85b3fd62ea1a 13082
NYX 0:85b3fd62ea1a 13083 /**
NYX 0:85b3fd62ea1a 13084 * @brief EXTI13 configuration
NYX 0:85b3fd62ea1a 13085 */
NYX 0:85b3fd62ea1a 13086 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
NYX 0:85b3fd62ea1a 13087 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
NYX 0:85b3fd62ea1a 13088 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
NYX 0:85b3fd62ea1a 13089 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
NYX 0:85b3fd62ea1a 13090 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
NYX 0:85b3fd62ea1a 13091 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
NYX 0:85b3fd62ea1a 13092 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
NYX 0:85b3fd62ea1a 13093 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
NYX 0:85b3fd62ea1a 13094 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
NYX 0:85b3fd62ea1a 13095 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
NYX 0:85b3fd62ea1a 13096
NYX 0:85b3fd62ea1a 13097 /**
NYX 0:85b3fd62ea1a 13098 * @brief EXTI14 configuration
NYX 0:85b3fd62ea1a 13099 */
NYX 0:85b3fd62ea1a 13100 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
NYX 0:85b3fd62ea1a 13101 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
NYX 0:85b3fd62ea1a 13102 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
NYX 0:85b3fd62ea1a 13103 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
NYX 0:85b3fd62ea1a 13104 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
NYX 0:85b3fd62ea1a 13105 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
NYX 0:85b3fd62ea1a 13106 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
NYX 0:85b3fd62ea1a 13107 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
NYX 0:85b3fd62ea1a 13108 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
NYX 0:85b3fd62ea1a 13109 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
NYX 0:85b3fd62ea1a 13110
NYX 0:85b3fd62ea1a 13111 /**
NYX 0:85b3fd62ea1a 13112 * @brief EXTI15 configuration
NYX 0:85b3fd62ea1a 13113 */
NYX 0:85b3fd62ea1a 13114 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
NYX 0:85b3fd62ea1a 13115 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
NYX 0:85b3fd62ea1a 13116 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
NYX 0:85b3fd62ea1a 13117 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
NYX 0:85b3fd62ea1a 13118 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
NYX 0:85b3fd62ea1a 13119 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
NYX 0:85b3fd62ea1a 13120 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
NYX 0:85b3fd62ea1a 13121 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
NYX 0:85b3fd62ea1a 13122 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
NYX 0:85b3fd62ea1a 13123 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
NYX 0:85b3fd62ea1a 13124
NYX 0:85b3fd62ea1a 13125 /****************** Bit definition for SYSCFG_CMPCR register ****************/
NYX 0:85b3fd62ea1a 13126 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
NYX 0:85b3fd62ea1a 13127 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13128 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
NYX 0:85b3fd62ea1a 13129 #define SYSCFG_CMPCR_READY_Pos (8U)
NYX 0:85b3fd62ea1a 13130 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 13131 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
NYX 0:85b3fd62ea1a 13132 /****************** Bit definition for SYSCFG_CFGR register ****************/
NYX 0:85b3fd62ea1a 13133 #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
NYX 0:85b3fd62ea1a 13134 #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13135 #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
NYX 0:85b3fd62ea1a 13136 #define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
NYX 0:85b3fd62ea1a 13137 #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13138 #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
NYX 0:85b3fd62ea1a 13139
NYX 0:85b3fd62ea1a 13140
NYX 0:85b3fd62ea1a 13141 /******************************************************************************/
NYX 0:85b3fd62ea1a 13142 /* */
NYX 0:85b3fd62ea1a 13143 /* TIM */
NYX 0:85b3fd62ea1a 13144 /* */
NYX 0:85b3fd62ea1a 13145 /******************************************************************************/
NYX 0:85b3fd62ea1a 13146 /******************* Bit definition for TIM_CR1 register ********************/
NYX 0:85b3fd62ea1a 13147 #define TIM_CR1_CEN_Pos (0U)
NYX 0:85b3fd62ea1a 13148 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13149 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
NYX 0:85b3fd62ea1a 13150 #define TIM_CR1_UDIS_Pos (1U)
NYX 0:85b3fd62ea1a 13151 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13152 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
NYX 0:85b3fd62ea1a 13153 #define TIM_CR1_URS_Pos (2U)
NYX 0:85b3fd62ea1a 13154 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13155 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
NYX 0:85b3fd62ea1a 13156 #define TIM_CR1_OPM_Pos (3U)
NYX 0:85b3fd62ea1a 13157 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13158 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
NYX 0:85b3fd62ea1a 13159 #define TIM_CR1_DIR_Pos (4U)
NYX 0:85b3fd62ea1a 13160 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 13161 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
NYX 0:85b3fd62ea1a 13162
NYX 0:85b3fd62ea1a 13163 #define TIM_CR1_CMS_Pos (5U)
NYX 0:85b3fd62ea1a 13164 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
NYX 0:85b3fd62ea1a 13165 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
NYX 0:85b3fd62ea1a 13166 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13167 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13168
NYX 0:85b3fd62ea1a 13169 #define TIM_CR1_ARPE_Pos (7U)
NYX 0:85b3fd62ea1a 13170 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13171 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
NYX 0:85b3fd62ea1a 13172
NYX 0:85b3fd62ea1a 13173 #define TIM_CR1_CKD_Pos (8U)
NYX 0:85b3fd62ea1a 13174 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 13175 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
NYX 0:85b3fd62ea1a 13176 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
NYX 0:85b3fd62ea1a 13177 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
NYX 0:85b3fd62ea1a 13178
NYX 0:85b3fd62ea1a 13179 /******************* Bit definition for TIM_CR2 register ********************/
NYX 0:85b3fd62ea1a 13180 #define TIM_CR2_CCPC_Pos (0U)
NYX 0:85b3fd62ea1a 13181 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13182 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
NYX 0:85b3fd62ea1a 13183 #define TIM_CR2_CCUS_Pos (2U)
NYX 0:85b3fd62ea1a 13184 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13185 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
NYX 0:85b3fd62ea1a 13186 #define TIM_CR2_CCDS_Pos (3U)
NYX 0:85b3fd62ea1a 13187 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13188 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
NYX 0:85b3fd62ea1a 13189
NYX 0:85b3fd62ea1a 13190 #define TIM_CR2_MMS_Pos (4U)
NYX 0:85b3fd62ea1a 13191 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 13192 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
NYX 0:85b3fd62ea1a 13193 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13194 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13195 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13196
NYX 0:85b3fd62ea1a 13197 #define TIM_CR2_TI1S_Pos (7U)
NYX 0:85b3fd62ea1a 13198 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13199 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
NYX 0:85b3fd62ea1a 13200 #define TIM_CR2_OIS1_Pos (8U)
NYX 0:85b3fd62ea1a 13201 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 13202 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
NYX 0:85b3fd62ea1a 13203 #define TIM_CR2_OIS1N_Pos (9U)
NYX 0:85b3fd62ea1a 13204 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 13205 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
NYX 0:85b3fd62ea1a 13206 #define TIM_CR2_OIS2_Pos (10U)
NYX 0:85b3fd62ea1a 13207 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13208 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
NYX 0:85b3fd62ea1a 13209 #define TIM_CR2_OIS2N_Pos (11U)
NYX 0:85b3fd62ea1a 13210 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13211 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
NYX 0:85b3fd62ea1a 13212 #define TIM_CR2_OIS3_Pos (12U)
NYX 0:85b3fd62ea1a 13213 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 13214 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
NYX 0:85b3fd62ea1a 13215 #define TIM_CR2_OIS3N_Pos (13U)
NYX 0:85b3fd62ea1a 13216 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 13217 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
NYX 0:85b3fd62ea1a 13218 #define TIM_CR2_OIS4_Pos (14U)
NYX 0:85b3fd62ea1a 13219 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 13220 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
NYX 0:85b3fd62ea1a 13221
NYX 0:85b3fd62ea1a 13222 /******************* Bit definition for TIM_SMCR register *******************/
NYX 0:85b3fd62ea1a 13223 #define TIM_SMCR_SMS_Pos (0U)
NYX 0:85b3fd62ea1a 13224 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 13225 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
NYX 0:85b3fd62ea1a 13226 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
NYX 0:85b3fd62ea1a 13227 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
NYX 0:85b3fd62ea1a 13228 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
NYX 0:85b3fd62ea1a 13229
NYX 0:85b3fd62ea1a 13230 #define TIM_SMCR_TS_Pos (4U)
NYX 0:85b3fd62ea1a 13231 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 13232 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
NYX 0:85b3fd62ea1a 13233 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13234 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13235 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13236
NYX 0:85b3fd62ea1a 13237 #define TIM_SMCR_MSM_Pos (7U)
NYX 0:85b3fd62ea1a 13238 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13239 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
NYX 0:85b3fd62ea1a 13240
NYX 0:85b3fd62ea1a 13241 #define TIM_SMCR_ETF_Pos (8U)
NYX 0:85b3fd62ea1a 13242 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 13243 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
NYX 0:85b3fd62ea1a 13244 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
NYX 0:85b3fd62ea1a 13245 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
NYX 0:85b3fd62ea1a 13246 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
NYX 0:85b3fd62ea1a 13247 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
NYX 0:85b3fd62ea1a 13248
NYX 0:85b3fd62ea1a 13249 #define TIM_SMCR_ETPS_Pos (12U)
NYX 0:85b3fd62ea1a 13250 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
NYX 0:85b3fd62ea1a 13251 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
NYX 0:85b3fd62ea1a 13252 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
NYX 0:85b3fd62ea1a 13253 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
NYX 0:85b3fd62ea1a 13254
NYX 0:85b3fd62ea1a 13255 #define TIM_SMCR_ECE_Pos (14U)
NYX 0:85b3fd62ea1a 13256 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 13257 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
NYX 0:85b3fd62ea1a 13258 #define TIM_SMCR_ETP_Pos (15U)
NYX 0:85b3fd62ea1a 13259 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 13260 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
NYX 0:85b3fd62ea1a 13261
NYX 0:85b3fd62ea1a 13262 /******************* Bit definition for TIM_DIER register *******************/
NYX 0:85b3fd62ea1a 13263 #define TIM_DIER_UIE_Pos (0U)
NYX 0:85b3fd62ea1a 13264 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13265 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
NYX 0:85b3fd62ea1a 13266 #define TIM_DIER_CC1IE_Pos (1U)
NYX 0:85b3fd62ea1a 13267 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13268 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
NYX 0:85b3fd62ea1a 13269 #define TIM_DIER_CC2IE_Pos (2U)
NYX 0:85b3fd62ea1a 13270 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13271 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
NYX 0:85b3fd62ea1a 13272 #define TIM_DIER_CC3IE_Pos (3U)
NYX 0:85b3fd62ea1a 13273 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13274 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
NYX 0:85b3fd62ea1a 13275 #define TIM_DIER_CC4IE_Pos (4U)
NYX 0:85b3fd62ea1a 13276 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 13277 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
NYX 0:85b3fd62ea1a 13278 #define TIM_DIER_COMIE_Pos (5U)
NYX 0:85b3fd62ea1a 13279 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 13280 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
NYX 0:85b3fd62ea1a 13281 #define TIM_DIER_TIE_Pos (6U)
NYX 0:85b3fd62ea1a 13282 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 13283 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
NYX 0:85b3fd62ea1a 13284 #define TIM_DIER_BIE_Pos (7U)
NYX 0:85b3fd62ea1a 13285 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13286 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
NYX 0:85b3fd62ea1a 13287 #define TIM_DIER_UDE_Pos (8U)
NYX 0:85b3fd62ea1a 13288 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 13289 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
NYX 0:85b3fd62ea1a 13290 #define TIM_DIER_CC1DE_Pos (9U)
NYX 0:85b3fd62ea1a 13291 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 13292 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
NYX 0:85b3fd62ea1a 13293 #define TIM_DIER_CC2DE_Pos (10U)
NYX 0:85b3fd62ea1a 13294 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13295 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
NYX 0:85b3fd62ea1a 13296 #define TIM_DIER_CC3DE_Pos (11U)
NYX 0:85b3fd62ea1a 13297 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13298 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
NYX 0:85b3fd62ea1a 13299 #define TIM_DIER_CC4DE_Pos (12U)
NYX 0:85b3fd62ea1a 13300 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 13301 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
NYX 0:85b3fd62ea1a 13302 #define TIM_DIER_COMDE_Pos (13U)
NYX 0:85b3fd62ea1a 13303 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 13304 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
NYX 0:85b3fd62ea1a 13305 #define TIM_DIER_TDE_Pos (14U)
NYX 0:85b3fd62ea1a 13306 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 13307 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
NYX 0:85b3fd62ea1a 13308
NYX 0:85b3fd62ea1a 13309 /******************** Bit definition for TIM_SR register ********************/
NYX 0:85b3fd62ea1a 13310 #define TIM_SR_UIF_Pos (0U)
NYX 0:85b3fd62ea1a 13311 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13312 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
NYX 0:85b3fd62ea1a 13313 #define TIM_SR_CC1IF_Pos (1U)
NYX 0:85b3fd62ea1a 13314 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13315 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
NYX 0:85b3fd62ea1a 13316 #define TIM_SR_CC2IF_Pos (2U)
NYX 0:85b3fd62ea1a 13317 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13318 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
NYX 0:85b3fd62ea1a 13319 #define TIM_SR_CC3IF_Pos (3U)
NYX 0:85b3fd62ea1a 13320 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13321 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
NYX 0:85b3fd62ea1a 13322 #define TIM_SR_CC4IF_Pos (4U)
NYX 0:85b3fd62ea1a 13323 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 13324 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
NYX 0:85b3fd62ea1a 13325 #define TIM_SR_COMIF_Pos (5U)
NYX 0:85b3fd62ea1a 13326 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 13327 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
NYX 0:85b3fd62ea1a 13328 #define TIM_SR_TIF_Pos (6U)
NYX 0:85b3fd62ea1a 13329 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 13330 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
NYX 0:85b3fd62ea1a 13331 #define TIM_SR_BIF_Pos (7U)
NYX 0:85b3fd62ea1a 13332 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13333 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
NYX 0:85b3fd62ea1a 13334 #define TIM_SR_CC1OF_Pos (9U)
NYX 0:85b3fd62ea1a 13335 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 13336 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
NYX 0:85b3fd62ea1a 13337 #define TIM_SR_CC2OF_Pos (10U)
NYX 0:85b3fd62ea1a 13338 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13339 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
NYX 0:85b3fd62ea1a 13340 #define TIM_SR_CC3OF_Pos (11U)
NYX 0:85b3fd62ea1a 13341 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13342 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
NYX 0:85b3fd62ea1a 13343 #define TIM_SR_CC4OF_Pos (12U)
NYX 0:85b3fd62ea1a 13344 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 13345 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
NYX 0:85b3fd62ea1a 13346
NYX 0:85b3fd62ea1a 13347 /******************* Bit definition for TIM_EGR register ********************/
NYX 0:85b3fd62ea1a 13348 #define TIM_EGR_UG_Pos (0U)
NYX 0:85b3fd62ea1a 13349 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13350 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
NYX 0:85b3fd62ea1a 13351 #define TIM_EGR_CC1G_Pos (1U)
NYX 0:85b3fd62ea1a 13352 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13353 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
NYX 0:85b3fd62ea1a 13354 #define TIM_EGR_CC2G_Pos (2U)
NYX 0:85b3fd62ea1a 13355 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13356 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
NYX 0:85b3fd62ea1a 13357 #define TIM_EGR_CC3G_Pos (3U)
NYX 0:85b3fd62ea1a 13358 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13359 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
NYX 0:85b3fd62ea1a 13360 #define TIM_EGR_CC4G_Pos (4U)
NYX 0:85b3fd62ea1a 13361 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 13362 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
NYX 0:85b3fd62ea1a 13363 #define TIM_EGR_COMG_Pos (5U)
NYX 0:85b3fd62ea1a 13364 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 13365 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
NYX 0:85b3fd62ea1a 13366 #define TIM_EGR_TG_Pos (6U)
NYX 0:85b3fd62ea1a 13367 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 13368 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
NYX 0:85b3fd62ea1a 13369 #define TIM_EGR_BG_Pos (7U)
NYX 0:85b3fd62ea1a 13370 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13371 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
NYX 0:85b3fd62ea1a 13372
NYX 0:85b3fd62ea1a 13373 /****************** Bit definition for TIM_CCMR1 register *******************/
NYX 0:85b3fd62ea1a 13374 #define TIM_CCMR1_CC1S_Pos (0U)
NYX 0:85b3fd62ea1a 13375 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 13376 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
NYX 0:85b3fd62ea1a 13377 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
NYX 0:85b3fd62ea1a 13378 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
NYX 0:85b3fd62ea1a 13379
NYX 0:85b3fd62ea1a 13380 #define TIM_CCMR1_OC1FE_Pos (2U)
NYX 0:85b3fd62ea1a 13381 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13382 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
NYX 0:85b3fd62ea1a 13383 #define TIM_CCMR1_OC1PE_Pos (3U)
NYX 0:85b3fd62ea1a 13384 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13385 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
NYX 0:85b3fd62ea1a 13386
NYX 0:85b3fd62ea1a 13387 #define TIM_CCMR1_OC1M_Pos (4U)
NYX 0:85b3fd62ea1a 13388 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 13389 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
NYX 0:85b3fd62ea1a 13390 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13391 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13392 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13393
NYX 0:85b3fd62ea1a 13394 #define TIM_CCMR1_OC1CE_Pos (7U)
NYX 0:85b3fd62ea1a 13395 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13396 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
NYX 0:85b3fd62ea1a 13397
NYX 0:85b3fd62ea1a 13398 #define TIM_CCMR1_CC2S_Pos (8U)
NYX 0:85b3fd62ea1a 13399 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 13400 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
NYX 0:85b3fd62ea1a 13401 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
NYX 0:85b3fd62ea1a 13402 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
NYX 0:85b3fd62ea1a 13403
NYX 0:85b3fd62ea1a 13404 #define TIM_CCMR1_OC2FE_Pos (10U)
NYX 0:85b3fd62ea1a 13405 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13406 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
NYX 0:85b3fd62ea1a 13407 #define TIM_CCMR1_OC2PE_Pos (11U)
NYX 0:85b3fd62ea1a 13408 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13409 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
NYX 0:85b3fd62ea1a 13410
NYX 0:85b3fd62ea1a 13411 #define TIM_CCMR1_OC2M_Pos (12U)
NYX 0:85b3fd62ea1a 13412 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
NYX 0:85b3fd62ea1a 13413 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
NYX 0:85b3fd62ea1a 13414 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
NYX 0:85b3fd62ea1a 13415 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
NYX 0:85b3fd62ea1a 13416 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
NYX 0:85b3fd62ea1a 13417
NYX 0:85b3fd62ea1a 13418 #define TIM_CCMR1_OC2CE_Pos (15U)
NYX 0:85b3fd62ea1a 13419 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 13420 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
NYX 0:85b3fd62ea1a 13421
NYX 0:85b3fd62ea1a 13422 /*----------------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 13423
NYX 0:85b3fd62ea1a 13424 #define TIM_CCMR1_IC1PSC_Pos (2U)
NYX 0:85b3fd62ea1a 13425 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 13426 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
NYX 0:85b3fd62ea1a 13427 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
NYX 0:85b3fd62ea1a 13428 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
NYX 0:85b3fd62ea1a 13429
NYX 0:85b3fd62ea1a 13430 #define TIM_CCMR1_IC1F_Pos (4U)
NYX 0:85b3fd62ea1a 13431 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 13432 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
NYX 0:85b3fd62ea1a 13433 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13434 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13435 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13436 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
NYX 0:85b3fd62ea1a 13437
NYX 0:85b3fd62ea1a 13438 #define TIM_CCMR1_IC2PSC_Pos (10U)
NYX 0:85b3fd62ea1a 13439 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 13440 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
NYX 0:85b3fd62ea1a 13441 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
NYX 0:85b3fd62ea1a 13442 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
NYX 0:85b3fd62ea1a 13443
NYX 0:85b3fd62ea1a 13444 #define TIM_CCMR1_IC2F_Pos (12U)
NYX 0:85b3fd62ea1a 13445 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 13446 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
NYX 0:85b3fd62ea1a 13447 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
NYX 0:85b3fd62ea1a 13448 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
NYX 0:85b3fd62ea1a 13449 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
NYX 0:85b3fd62ea1a 13450 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
NYX 0:85b3fd62ea1a 13451
NYX 0:85b3fd62ea1a 13452 /****************** Bit definition for TIM_CCMR2 register *******************/
NYX 0:85b3fd62ea1a 13453 #define TIM_CCMR2_CC3S_Pos (0U)
NYX 0:85b3fd62ea1a 13454 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 13455 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
NYX 0:85b3fd62ea1a 13456 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
NYX 0:85b3fd62ea1a 13457 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
NYX 0:85b3fd62ea1a 13458
NYX 0:85b3fd62ea1a 13459 #define TIM_CCMR2_OC3FE_Pos (2U)
NYX 0:85b3fd62ea1a 13460 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13461 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
NYX 0:85b3fd62ea1a 13462 #define TIM_CCMR2_OC3PE_Pos (3U)
NYX 0:85b3fd62ea1a 13463 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13464 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
NYX 0:85b3fd62ea1a 13465
NYX 0:85b3fd62ea1a 13466 #define TIM_CCMR2_OC3M_Pos (4U)
NYX 0:85b3fd62ea1a 13467 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 13468 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
NYX 0:85b3fd62ea1a 13469 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13470 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13471 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13472
NYX 0:85b3fd62ea1a 13473 #define TIM_CCMR2_OC3CE_Pos (7U)
NYX 0:85b3fd62ea1a 13474 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13475 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
NYX 0:85b3fd62ea1a 13476
NYX 0:85b3fd62ea1a 13477 #define TIM_CCMR2_CC4S_Pos (8U)
NYX 0:85b3fd62ea1a 13478 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 13479 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
NYX 0:85b3fd62ea1a 13480 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
NYX 0:85b3fd62ea1a 13481 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
NYX 0:85b3fd62ea1a 13482
NYX 0:85b3fd62ea1a 13483 #define TIM_CCMR2_OC4FE_Pos (10U)
NYX 0:85b3fd62ea1a 13484 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13485 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
NYX 0:85b3fd62ea1a 13486 #define TIM_CCMR2_OC4PE_Pos (11U)
NYX 0:85b3fd62ea1a 13487 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13488 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
NYX 0:85b3fd62ea1a 13489
NYX 0:85b3fd62ea1a 13490 #define TIM_CCMR2_OC4M_Pos (12U)
NYX 0:85b3fd62ea1a 13491 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
NYX 0:85b3fd62ea1a 13492 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
NYX 0:85b3fd62ea1a 13493 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
NYX 0:85b3fd62ea1a 13494 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
NYX 0:85b3fd62ea1a 13495 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
NYX 0:85b3fd62ea1a 13496
NYX 0:85b3fd62ea1a 13497 #define TIM_CCMR2_OC4CE_Pos (15U)
NYX 0:85b3fd62ea1a 13498 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 13499 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
NYX 0:85b3fd62ea1a 13500
NYX 0:85b3fd62ea1a 13501 /*----------------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 13502
NYX 0:85b3fd62ea1a 13503 #define TIM_CCMR2_IC3PSC_Pos (2U)
NYX 0:85b3fd62ea1a 13504 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
NYX 0:85b3fd62ea1a 13505 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
NYX 0:85b3fd62ea1a 13506 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
NYX 0:85b3fd62ea1a 13507 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
NYX 0:85b3fd62ea1a 13508
NYX 0:85b3fd62ea1a 13509 #define TIM_CCMR2_IC3F_Pos (4U)
NYX 0:85b3fd62ea1a 13510 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
NYX 0:85b3fd62ea1a 13511 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
NYX 0:85b3fd62ea1a 13512 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13513 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13514 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13515 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
NYX 0:85b3fd62ea1a 13516
NYX 0:85b3fd62ea1a 13517 #define TIM_CCMR2_IC4PSC_Pos (10U)
NYX 0:85b3fd62ea1a 13518 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 13519 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
NYX 0:85b3fd62ea1a 13520 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
NYX 0:85b3fd62ea1a 13521 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
NYX 0:85b3fd62ea1a 13522
NYX 0:85b3fd62ea1a 13523 #define TIM_CCMR2_IC4F_Pos (12U)
NYX 0:85b3fd62ea1a 13524 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
NYX 0:85b3fd62ea1a 13525 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
NYX 0:85b3fd62ea1a 13526 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
NYX 0:85b3fd62ea1a 13527 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
NYX 0:85b3fd62ea1a 13528 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
NYX 0:85b3fd62ea1a 13529 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
NYX 0:85b3fd62ea1a 13530
NYX 0:85b3fd62ea1a 13531 /******************* Bit definition for TIM_CCER register *******************/
NYX 0:85b3fd62ea1a 13532 #define TIM_CCER_CC1E_Pos (0U)
NYX 0:85b3fd62ea1a 13533 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13534 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
NYX 0:85b3fd62ea1a 13535 #define TIM_CCER_CC1P_Pos (1U)
NYX 0:85b3fd62ea1a 13536 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13537 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
NYX 0:85b3fd62ea1a 13538 #define TIM_CCER_CC1NE_Pos (2U)
NYX 0:85b3fd62ea1a 13539 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13540 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
NYX 0:85b3fd62ea1a 13541 #define TIM_CCER_CC1NP_Pos (3U)
NYX 0:85b3fd62ea1a 13542 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13543 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
NYX 0:85b3fd62ea1a 13544 #define TIM_CCER_CC2E_Pos (4U)
NYX 0:85b3fd62ea1a 13545 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 13546 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
NYX 0:85b3fd62ea1a 13547 #define TIM_CCER_CC2P_Pos (5U)
NYX 0:85b3fd62ea1a 13548 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 13549 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
NYX 0:85b3fd62ea1a 13550 #define TIM_CCER_CC2NE_Pos (6U)
NYX 0:85b3fd62ea1a 13551 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 13552 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
NYX 0:85b3fd62ea1a 13553 #define TIM_CCER_CC2NP_Pos (7U)
NYX 0:85b3fd62ea1a 13554 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13555 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
NYX 0:85b3fd62ea1a 13556 #define TIM_CCER_CC3E_Pos (8U)
NYX 0:85b3fd62ea1a 13557 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 13558 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
NYX 0:85b3fd62ea1a 13559 #define TIM_CCER_CC3P_Pos (9U)
NYX 0:85b3fd62ea1a 13560 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 13561 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
NYX 0:85b3fd62ea1a 13562 #define TIM_CCER_CC3NE_Pos (10U)
NYX 0:85b3fd62ea1a 13563 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13564 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
NYX 0:85b3fd62ea1a 13565 #define TIM_CCER_CC3NP_Pos (11U)
NYX 0:85b3fd62ea1a 13566 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13567 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
NYX 0:85b3fd62ea1a 13568 #define TIM_CCER_CC4E_Pos (12U)
NYX 0:85b3fd62ea1a 13569 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 13570 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
NYX 0:85b3fd62ea1a 13571 #define TIM_CCER_CC4P_Pos (13U)
NYX 0:85b3fd62ea1a 13572 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 13573 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
NYX 0:85b3fd62ea1a 13574 #define TIM_CCER_CC4NP_Pos (15U)
NYX 0:85b3fd62ea1a 13575 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 13576 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
NYX 0:85b3fd62ea1a 13577
NYX 0:85b3fd62ea1a 13578 /******************* Bit definition for TIM_CNT register ********************/
NYX 0:85b3fd62ea1a 13579 #define TIM_CNT_CNT_Pos (0U)
NYX 0:85b3fd62ea1a 13580 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 13581 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
NYX 0:85b3fd62ea1a 13582
NYX 0:85b3fd62ea1a 13583 /******************* Bit definition for TIM_PSC register ********************/
NYX 0:85b3fd62ea1a 13584 #define TIM_PSC_PSC_Pos (0U)
NYX 0:85b3fd62ea1a 13585 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 13586 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
NYX 0:85b3fd62ea1a 13587
NYX 0:85b3fd62ea1a 13588 /******************* Bit definition for TIM_ARR register ********************/
NYX 0:85b3fd62ea1a 13589 #define TIM_ARR_ARR_Pos (0U)
NYX 0:85b3fd62ea1a 13590 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 13591 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
NYX 0:85b3fd62ea1a 13592
NYX 0:85b3fd62ea1a 13593 /******************* Bit definition for TIM_RCR register ********************/
NYX 0:85b3fd62ea1a 13594 #define TIM_RCR_REP_Pos (0U)
NYX 0:85b3fd62ea1a 13595 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 13596 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
NYX 0:85b3fd62ea1a 13597
NYX 0:85b3fd62ea1a 13598 /******************* Bit definition for TIM_CCR1 register *******************/
NYX 0:85b3fd62ea1a 13599 #define TIM_CCR1_CCR1_Pos (0U)
NYX 0:85b3fd62ea1a 13600 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 13601 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
NYX 0:85b3fd62ea1a 13602
NYX 0:85b3fd62ea1a 13603 /******************* Bit definition for TIM_CCR2 register *******************/
NYX 0:85b3fd62ea1a 13604 #define TIM_CCR2_CCR2_Pos (0U)
NYX 0:85b3fd62ea1a 13605 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 13606 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
NYX 0:85b3fd62ea1a 13607
NYX 0:85b3fd62ea1a 13608 /******************* Bit definition for TIM_CCR3 register *******************/
NYX 0:85b3fd62ea1a 13609 #define TIM_CCR3_CCR3_Pos (0U)
NYX 0:85b3fd62ea1a 13610 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 13611 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
NYX 0:85b3fd62ea1a 13612
NYX 0:85b3fd62ea1a 13613 /******************* Bit definition for TIM_CCR4 register *******************/
NYX 0:85b3fd62ea1a 13614 #define TIM_CCR4_CCR4_Pos (0U)
NYX 0:85b3fd62ea1a 13615 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 13616 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
NYX 0:85b3fd62ea1a 13617
NYX 0:85b3fd62ea1a 13618 /******************* Bit definition for TIM_BDTR register *******************/
NYX 0:85b3fd62ea1a 13619 #define TIM_BDTR_DTG_Pos (0U)
NYX 0:85b3fd62ea1a 13620 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 13621 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
NYX 0:85b3fd62ea1a 13622 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
NYX 0:85b3fd62ea1a 13623 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
NYX 0:85b3fd62ea1a 13624 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
NYX 0:85b3fd62ea1a 13625 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
NYX 0:85b3fd62ea1a 13626 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13627 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13628 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13629 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
NYX 0:85b3fd62ea1a 13630
NYX 0:85b3fd62ea1a 13631 #define TIM_BDTR_LOCK_Pos (8U)
NYX 0:85b3fd62ea1a 13632 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
NYX 0:85b3fd62ea1a 13633 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
NYX 0:85b3fd62ea1a 13634 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
NYX 0:85b3fd62ea1a 13635 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
NYX 0:85b3fd62ea1a 13636
NYX 0:85b3fd62ea1a 13637 #define TIM_BDTR_OSSI_Pos (10U)
NYX 0:85b3fd62ea1a 13638 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13639 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
NYX 0:85b3fd62ea1a 13640 #define TIM_BDTR_OSSR_Pos (11U)
NYX 0:85b3fd62ea1a 13641 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13642 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
NYX 0:85b3fd62ea1a 13643 #define TIM_BDTR_BKE_Pos (12U)
NYX 0:85b3fd62ea1a 13644 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 13645 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
NYX 0:85b3fd62ea1a 13646 #define TIM_BDTR_BKP_Pos (13U)
NYX 0:85b3fd62ea1a 13647 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 13648 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
NYX 0:85b3fd62ea1a 13649 #define TIM_BDTR_AOE_Pos (14U)
NYX 0:85b3fd62ea1a 13650 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 13651 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
NYX 0:85b3fd62ea1a 13652 #define TIM_BDTR_MOE_Pos (15U)
NYX 0:85b3fd62ea1a 13653 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 13654 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
NYX 0:85b3fd62ea1a 13655
NYX 0:85b3fd62ea1a 13656 /******************* Bit definition for TIM_DCR register ********************/
NYX 0:85b3fd62ea1a 13657 #define TIM_DCR_DBA_Pos (0U)
NYX 0:85b3fd62ea1a 13658 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
NYX 0:85b3fd62ea1a 13659 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
NYX 0:85b3fd62ea1a 13660 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
NYX 0:85b3fd62ea1a 13661 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
NYX 0:85b3fd62ea1a 13662 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
NYX 0:85b3fd62ea1a 13663 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
NYX 0:85b3fd62ea1a 13664 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13665
NYX 0:85b3fd62ea1a 13666 #define TIM_DCR_DBL_Pos (8U)
NYX 0:85b3fd62ea1a 13667 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
NYX 0:85b3fd62ea1a 13668 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
NYX 0:85b3fd62ea1a 13669 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
NYX 0:85b3fd62ea1a 13670 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
NYX 0:85b3fd62ea1a 13671 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
NYX 0:85b3fd62ea1a 13672 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
NYX 0:85b3fd62ea1a 13673 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
NYX 0:85b3fd62ea1a 13674
NYX 0:85b3fd62ea1a 13675 /******************* Bit definition for TIM_DMAR register *******************/
NYX 0:85b3fd62ea1a 13676 #define TIM_DMAR_DMAB_Pos (0U)
NYX 0:85b3fd62ea1a 13677 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 13678 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
NYX 0:85b3fd62ea1a 13679
NYX 0:85b3fd62ea1a 13680 /******************* Bit definition for TIM_OR register *********************/
NYX 0:85b3fd62ea1a 13681 #define TIM_OR_TI1_RMP_Pos (0U)
NYX 0:85b3fd62ea1a 13682 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 13683 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
NYX 0:85b3fd62ea1a 13684 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13685 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13686
NYX 0:85b3fd62ea1a 13687 #define TIM_OR_TI4_RMP_Pos (6U)
NYX 0:85b3fd62ea1a 13688 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 13689 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
NYX 0:85b3fd62ea1a 13690 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13691 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
NYX 0:85b3fd62ea1a 13692 #define TIM_OR_ITR1_RMP_Pos (10U)
NYX 0:85b3fd62ea1a 13693 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 13694 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
NYX 0:85b3fd62ea1a 13695 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
NYX 0:85b3fd62ea1a 13696 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
NYX 0:85b3fd62ea1a 13697
NYX 0:85b3fd62ea1a 13698
NYX 0:85b3fd62ea1a 13699 /******************************************************************************/
NYX 0:85b3fd62ea1a 13700 /* */
NYX 0:85b3fd62ea1a 13701 /* Universal Synchronous Asynchronous Receiver Transmitter */
NYX 0:85b3fd62ea1a 13702 /* */
NYX 0:85b3fd62ea1a 13703 /******************************************************************************/
NYX 0:85b3fd62ea1a 13704 /******************* Bit definition for USART_SR register *******************/
NYX 0:85b3fd62ea1a 13705 #define USART_SR_PE_Pos (0U)
NYX 0:85b3fd62ea1a 13706 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13707 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
NYX 0:85b3fd62ea1a 13708 #define USART_SR_FE_Pos (1U)
NYX 0:85b3fd62ea1a 13709 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13710 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
NYX 0:85b3fd62ea1a 13711 #define USART_SR_NE_Pos (2U)
NYX 0:85b3fd62ea1a 13712 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13713 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
NYX 0:85b3fd62ea1a 13714 #define USART_SR_ORE_Pos (3U)
NYX 0:85b3fd62ea1a 13715 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13716 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
NYX 0:85b3fd62ea1a 13717 #define USART_SR_IDLE_Pos (4U)
NYX 0:85b3fd62ea1a 13718 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 13719 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
NYX 0:85b3fd62ea1a 13720 #define USART_SR_RXNE_Pos (5U)
NYX 0:85b3fd62ea1a 13721 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 13722 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
NYX 0:85b3fd62ea1a 13723 #define USART_SR_TC_Pos (6U)
NYX 0:85b3fd62ea1a 13724 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 13725 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
NYX 0:85b3fd62ea1a 13726 #define USART_SR_TXE_Pos (7U)
NYX 0:85b3fd62ea1a 13727 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13728 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
NYX 0:85b3fd62ea1a 13729 #define USART_SR_LBD_Pos (8U)
NYX 0:85b3fd62ea1a 13730 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 13731 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
NYX 0:85b3fd62ea1a 13732 #define USART_SR_CTS_Pos (9U)
NYX 0:85b3fd62ea1a 13733 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 13734 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
NYX 0:85b3fd62ea1a 13735
NYX 0:85b3fd62ea1a 13736 /******************* Bit definition for USART_DR register *******************/
NYX 0:85b3fd62ea1a 13737 #define USART_DR_DR_Pos (0U)
NYX 0:85b3fd62ea1a 13738 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
NYX 0:85b3fd62ea1a 13739 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
NYX 0:85b3fd62ea1a 13740
NYX 0:85b3fd62ea1a 13741 /****************** Bit definition for USART_BRR register *******************/
NYX 0:85b3fd62ea1a 13742 #define USART_BRR_DIV_Fraction_Pos (0U)
NYX 0:85b3fd62ea1a 13743 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 13744 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
NYX 0:85b3fd62ea1a 13745 #define USART_BRR_DIV_Mantissa_Pos (4U)
NYX 0:85b3fd62ea1a 13746 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
NYX 0:85b3fd62ea1a 13747 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
NYX 0:85b3fd62ea1a 13748
NYX 0:85b3fd62ea1a 13749 /****************** Bit definition for USART_CR1 register *******************/
NYX 0:85b3fd62ea1a 13750 #define USART_CR1_SBK_Pos (0U)
NYX 0:85b3fd62ea1a 13751 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13752 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
NYX 0:85b3fd62ea1a 13753 #define USART_CR1_RWU_Pos (1U)
NYX 0:85b3fd62ea1a 13754 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13755 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
NYX 0:85b3fd62ea1a 13756 #define USART_CR1_RE_Pos (2U)
NYX 0:85b3fd62ea1a 13757 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13758 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
NYX 0:85b3fd62ea1a 13759 #define USART_CR1_TE_Pos (3U)
NYX 0:85b3fd62ea1a 13760 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13761 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
NYX 0:85b3fd62ea1a 13762 #define USART_CR1_IDLEIE_Pos (4U)
NYX 0:85b3fd62ea1a 13763 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 13764 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
NYX 0:85b3fd62ea1a 13765 #define USART_CR1_RXNEIE_Pos (5U)
NYX 0:85b3fd62ea1a 13766 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 13767 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
NYX 0:85b3fd62ea1a 13768 #define USART_CR1_TCIE_Pos (6U)
NYX 0:85b3fd62ea1a 13769 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 13770 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
NYX 0:85b3fd62ea1a 13771 #define USART_CR1_TXEIE_Pos (7U)
NYX 0:85b3fd62ea1a 13772 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13773 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
NYX 0:85b3fd62ea1a 13774 #define USART_CR1_PEIE_Pos (8U)
NYX 0:85b3fd62ea1a 13775 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 13776 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
NYX 0:85b3fd62ea1a 13777 #define USART_CR1_PS_Pos (9U)
NYX 0:85b3fd62ea1a 13778 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 13779 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
NYX 0:85b3fd62ea1a 13780 #define USART_CR1_PCE_Pos (10U)
NYX 0:85b3fd62ea1a 13781 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13782 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
NYX 0:85b3fd62ea1a 13783 #define USART_CR1_WAKE_Pos (11U)
NYX 0:85b3fd62ea1a 13784 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13785 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
NYX 0:85b3fd62ea1a 13786 #define USART_CR1_M_Pos (12U)
NYX 0:85b3fd62ea1a 13787 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 13788 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
NYX 0:85b3fd62ea1a 13789 #define USART_CR1_UE_Pos (13U)
NYX 0:85b3fd62ea1a 13790 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 13791 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
NYX 0:85b3fd62ea1a 13792 #define USART_CR1_OVER8_Pos (15U)
NYX 0:85b3fd62ea1a 13793 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 13794 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
NYX 0:85b3fd62ea1a 13795
NYX 0:85b3fd62ea1a 13796 /****************** Bit definition for USART_CR2 register *******************/
NYX 0:85b3fd62ea1a 13797 #define USART_CR2_ADD_Pos (0U)
NYX 0:85b3fd62ea1a 13798 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 13799 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
NYX 0:85b3fd62ea1a 13800 #define USART_CR2_LBDL_Pos (5U)
NYX 0:85b3fd62ea1a 13801 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 13802 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
NYX 0:85b3fd62ea1a 13803 #define USART_CR2_LBDIE_Pos (6U)
NYX 0:85b3fd62ea1a 13804 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 13805 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
NYX 0:85b3fd62ea1a 13806 #define USART_CR2_LBCL_Pos (8U)
NYX 0:85b3fd62ea1a 13807 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 13808 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
NYX 0:85b3fd62ea1a 13809 #define USART_CR2_CPHA_Pos (9U)
NYX 0:85b3fd62ea1a 13810 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 13811 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
NYX 0:85b3fd62ea1a 13812 #define USART_CR2_CPOL_Pos (10U)
NYX 0:85b3fd62ea1a 13813 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13814 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
NYX 0:85b3fd62ea1a 13815 #define USART_CR2_CLKEN_Pos (11U)
NYX 0:85b3fd62ea1a 13816 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13817 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
NYX 0:85b3fd62ea1a 13818
NYX 0:85b3fd62ea1a 13819 #define USART_CR2_STOP_Pos (12U)
NYX 0:85b3fd62ea1a 13820 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
NYX 0:85b3fd62ea1a 13821 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
NYX 0:85b3fd62ea1a 13822 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
NYX 0:85b3fd62ea1a 13823 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
NYX 0:85b3fd62ea1a 13824
NYX 0:85b3fd62ea1a 13825 #define USART_CR2_LINEN_Pos (14U)
NYX 0:85b3fd62ea1a 13826 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 13827 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
NYX 0:85b3fd62ea1a 13828
NYX 0:85b3fd62ea1a 13829 /****************** Bit definition for USART_CR3 register *******************/
NYX 0:85b3fd62ea1a 13830 #define USART_CR3_EIE_Pos (0U)
NYX 0:85b3fd62ea1a 13831 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13832 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
NYX 0:85b3fd62ea1a 13833 #define USART_CR3_IREN_Pos (1U)
NYX 0:85b3fd62ea1a 13834 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13835 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
NYX 0:85b3fd62ea1a 13836 #define USART_CR3_IRLP_Pos (2U)
NYX 0:85b3fd62ea1a 13837 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13838 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
NYX 0:85b3fd62ea1a 13839 #define USART_CR3_HDSEL_Pos (3U)
NYX 0:85b3fd62ea1a 13840 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13841 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
NYX 0:85b3fd62ea1a 13842 #define USART_CR3_NACK_Pos (4U)
NYX 0:85b3fd62ea1a 13843 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 13844 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
NYX 0:85b3fd62ea1a 13845 #define USART_CR3_SCEN_Pos (5U)
NYX 0:85b3fd62ea1a 13846 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 13847 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
NYX 0:85b3fd62ea1a 13848 #define USART_CR3_DMAR_Pos (6U)
NYX 0:85b3fd62ea1a 13849 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 13850 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
NYX 0:85b3fd62ea1a 13851 #define USART_CR3_DMAT_Pos (7U)
NYX 0:85b3fd62ea1a 13852 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13853 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
NYX 0:85b3fd62ea1a 13854 #define USART_CR3_RTSE_Pos (8U)
NYX 0:85b3fd62ea1a 13855 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 13856 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
NYX 0:85b3fd62ea1a 13857 #define USART_CR3_CTSE_Pos (9U)
NYX 0:85b3fd62ea1a 13858 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 13859 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
NYX 0:85b3fd62ea1a 13860 #define USART_CR3_CTSIE_Pos (10U)
NYX 0:85b3fd62ea1a 13861 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 13862 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
NYX 0:85b3fd62ea1a 13863 #define USART_CR3_ONEBIT_Pos (11U)
NYX 0:85b3fd62ea1a 13864 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 13865 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
NYX 0:85b3fd62ea1a 13866
NYX 0:85b3fd62ea1a 13867 /****************** Bit definition for USART_GTPR register ******************/
NYX 0:85b3fd62ea1a 13868 #define USART_GTPR_PSC_Pos (0U)
NYX 0:85b3fd62ea1a 13869 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
NYX 0:85b3fd62ea1a 13870 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
NYX 0:85b3fd62ea1a 13871 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
NYX 0:85b3fd62ea1a 13872 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
NYX 0:85b3fd62ea1a 13873 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
NYX 0:85b3fd62ea1a 13874 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
NYX 0:85b3fd62ea1a 13875 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13876 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13877 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13878 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
NYX 0:85b3fd62ea1a 13879
NYX 0:85b3fd62ea1a 13880 #define USART_GTPR_GT_Pos (8U)
NYX 0:85b3fd62ea1a 13881 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
NYX 0:85b3fd62ea1a 13882 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
NYX 0:85b3fd62ea1a 13883
NYX 0:85b3fd62ea1a 13884 /******************************************************************************/
NYX 0:85b3fd62ea1a 13885 /* */
NYX 0:85b3fd62ea1a 13886 /* Window WATCHDOG */
NYX 0:85b3fd62ea1a 13887 /* */
NYX 0:85b3fd62ea1a 13888 /******************************************************************************/
NYX 0:85b3fd62ea1a 13889 /******************* Bit definition for WWDG_CR register ********************/
NYX 0:85b3fd62ea1a 13890 #define WWDG_CR_T_Pos (0U)
NYX 0:85b3fd62ea1a 13891 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
NYX 0:85b3fd62ea1a 13892 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
NYX 0:85b3fd62ea1a 13893 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
NYX 0:85b3fd62ea1a 13894 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
NYX 0:85b3fd62ea1a 13895 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
NYX 0:85b3fd62ea1a 13896 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
NYX 0:85b3fd62ea1a 13897 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
NYX 0:85b3fd62ea1a 13898 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
NYX 0:85b3fd62ea1a 13899 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
NYX 0:85b3fd62ea1a 13900 /* Legacy defines */
NYX 0:85b3fd62ea1a 13901 #define WWDG_CR_T0 WWDG_CR_T_0
NYX 0:85b3fd62ea1a 13902 #define WWDG_CR_T1 WWDG_CR_T_1
NYX 0:85b3fd62ea1a 13903 #define WWDG_CR_T2 WWDG_CR_T_2
NYX 0:85b3fd62ea1a 13904 #define WWDG_CR_T3 WWDG_CR_T_3
NYX 0:85b3fd62ea1a 13905 #define WWDG_CR_T4 WWDG_CR_T_4
NYX 0:85b3fd62ea1a 13906 #define WWDG_CR_T5 WWDG_CR_T_5
NYX 0:85b3fd62ea1a 13907 #define WWDG_CR_T6 WWDG_CR_T_6
NYX 0:85b3fd62ea1a 13908
NYX 0:85b3fd62ea1a 13909 #define WWDG_CR_WDGA_Pos (7U)
NYX 0:85b3fd62ea1a 13910 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13911 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
NYX 0:85b3fd62ea1a 13912
NYX 0:85b3fd62ea1a 13913 /******************* Bit definition for WWDG_CFR register *******************/
NYX 0:85b3fd62ea1a 13914 #define WWDG_CFR_W_Pos (0U)
NYX 0:85b3fd62ea1a 13915 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
NYX 0:85b3fd62ea1a 13916 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
NYX 0:85b3fd62ea1a 13917 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
NYX 0:85b3fd62ea1a 13918 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
NYX 0:85b3fd62ea1a 13919 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
NYX 0:85b3fd62ea1a 13920 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
NYX 0:85b3fd62ea1a 13921 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
NYX 0:85b3fd62ea1a 13922 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
NYX 0:85b3fd62ea1a 13923 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
NYX 0:85b3fd62ea1a 13924 /* Legacy defines */
NYX 0:85b3fd62ea1a 13925 #define WWDG_CFR_W0 WWDG_CFR_W_0
NYX 0:85b3fd62ea1a 13926 #define WWDG_CFR_W1 WWDG_CFR_W_1
NYX 0:85b3fd62ea1a 13927 #define WWDG_CFR_W2 WWDG_CFR_W_2
NYX 0:85b3fd62ea1a 13928 #define WWDG_CFR_W3 WWDG_CFR_W_3
NYX 0:85b3fd62ea1a 13929 #define WWDG_CFR_W4 WWDG_CFR_W_4
NYX 0:85b3fd62ea1a 13930 #define WWDG_CFR_W5 WWDG_CFR_W_5
NYX 0:85b3fd62ea1a 13931 #define WWDG_CFR_W6 WWDG_CFR_W_6
NYX 0:85b3fd62ea1a 13932
NYX 0:85b3fd62ea1a 13933 #define WWDG_CFR_WDGTB_Pos (7U)
NYX 0:85b3fd62ea1a 13934 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
NYX 0:85b3fd62ea1a 13935 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
NYX 0:85b3fd62ea1a 13936 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
NYX 0:85b3fd62ea1a 13937 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
NYX 0:85b3fd62ea1a 13938 /* Legacy defines */
NYX 0:85b3fd62ea1a 13939 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
NYX 0:85b3fd62ea1a 13940 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
NYX 0:85b3fd62ea1a 13941
NYX 0:85b3fd62ea1a 13942 #define WWDG_CFR_EWI_Pos (9U)
NYX 0:85b3fd62ea1a 13943 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 13944 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
NYX 0:85b3fd62ea1a 13945
NYX 0:85b3fd62ea1a 13946 /******************* Bit definition for WWDG_SR register ********************/
NYX 0:85b3fd62ea1a 13947 #define WWDG_SR_EWIF_Pos (0U)
NYX 0:85b3fd62ea1a 13948 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13949 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
NYX 0:85b3fd62ea1a 13950
NYX 0:85b3fd62ea1a 13951
NYX 0:85b3fd62ea1a 13952 /******************************************************************************/
NYX 0:85b3fd62ea1a 13953 /* */
NYX 0:85b3fd62ea1a 13954 /* DBG */
NYX 0:85b3fd62ea1a 13955 /* */
NYX 0:85b3fd62ea1a 13956 /******************************************************************************/
NYX 0:85b3fd62ea1a 13957 /******************** Bit definition for DBGMCU_IDCODE register *************/
NYX 0:85b3fd62ea1a 13958 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
NYX 0:85b3fd62ea1a 13959 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 13960 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
NYX 0:85b3fd62ea1a 13961 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
NYX 0:85b3fd62ea1a 13962 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 13963 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
NYX 0:85b3fd62ea1a 13964
NYX 0:85b3fd62ea1a 13965 /******************** Bit definition for DBGMCU_CR register *****************/
NYX 0:85b3fd62ea1a 13966 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
NYX 0:85b3fd62ea1a 13967 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13968 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
NYX 0:85b3fd62ea1a 13969 #define DBGMCU_CR_DBG_STOP_Pos (1U)
NYX 0:85b3fd62ea1a 13970 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13971 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
NYX 0:85b3fd62ea1a 13972 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
NYX 0:85b3fd62ea1a 13973 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13974 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
NYX 0:85b3fd62ea1a 13975 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
NYX 0:85b3fd62ea1a 13976 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 13977 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
NYX 0:85b3fd62ea1a 13978
NYX 0:85b3fd62ea1a 13979 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
NYX 0:85b3fd62ea1a 13980 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
NYX 0:85b3fd62ea1a 13981 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
NYX 0:85b3fd62ea1a 13982 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 13983 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 13984
NYX 0:85b3fd62ea1a 13985 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
NYX 0:85b3fd62ea1a 13986 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
NYX 0:85b3fd62ea1a 13987 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 13988 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
NYX 0:85b3fd62ea1a 13989 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
NYX 0:85b3fd62ea1a 13990 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 13991 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
NYX 0:85b3fd62ea1a 13992 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
NYX 0:85b3fd62ea1a 13993 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 13994 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
NYX 0:85b3fd62ea1a 13995 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
NYX 0:85b3fd62ea1a 13996 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 13997 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
NYX 0:85b3fd62ea1a 13998 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
NYX 0:85b3fd62ea1a 13999 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14000 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
NYX 0:85b3fd62ea1a 14001 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
NYX 0:85b3fd62ea1a 14002 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14003 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
NYX 0:85b3fd62ea1a 14004 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
NYX 0:85b3fd62ea1a 14005 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14006 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
NYX 0:85b3fd62ea1a 14007 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
NYX 0:85b3fd62ea1a 14008 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14009 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
NYX 0:85b3fd62ea1a 14010 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
NYX 0:85b3fd62ea1a 14011 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14012 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
NYX 0:85b3fd62ea1a 14013 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
NYX 0:85b3fd62ea1a 14014 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 14015 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
NYX 0:85b3fd62ea1a 14016 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
NYX 0:85b3fd62ea1a 14017 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 14018 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
NYX 0:85b3fd62ea1a 14019 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
NYX 0:85b3fd62ea1a 14020 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 14021 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
NYX 0:85b3fd62ea1a 14022 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
NYX 0:85b3fd62ea1a 14023 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14024 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
NYX 0:85b3fd62ea1a 14025 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
NYX 0:85b3fd62ea1a 14026 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 14027 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
NYX 0:85b3fd62ea1a 14028 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
NYX 0:85b3fd62ea1a 14029 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 14030 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
NYX 0:85b3fd62ea1a 14031 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
NYX 0:85b3fd62ea1a 14032 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14033 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
NYX 0:85b3fd62ea1a 14034 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
NYX 0:85b3fd62ea1a 14035 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 14036 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
NYX 0:85b3fd62ea1a 14037 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
NYX 0:85b3fd62ea1a 14038 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 14039 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
NYX 0:85b3fd62ea1a 14040 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
NYX 0:85b3fd62ea1a 14041 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
NYX 0:85b3fd62ea1a 14042
NYX 0:85b3fd62ea1a 14043 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
NYX 0:85b3fd62ea1a 14044 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
NYX 0:85b3fd62ea1a 14045 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14046 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
NYX 0:85b3fd62ea1a 14047 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
NYX 0:85b3fd62ea1a 14048 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14049 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
NYX 0:85b3fd62ea1a 14050 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
NYX 0:85b3fd62ea1a 14051 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 14052 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
NYX 0:85b3fd62ea1a 14053 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
NYX 0:85b3fd62ea1a 14054 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14055 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
NYX 0:85b3fd62ea1a 14056 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
NYX 0:85b3fd62ea1a 14057 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14058 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
NYX 0:85b3fd62ea1a 14059
NYX 0:85b3fd62ea1a 14060 /******************************************************************************/
NYX 0:85b3fd62ea1a 14061 /* */
NYX 0:85b3fd62ea1a 14062 /* USB_OTG */
NYX 0:85b3fd62ea1a 14063 /* */
NYX 0:85b3fd62ea1a 14064 /******************************************************************************/
NYX 0:85b3fd62ea1a 14065 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
NYX 0:85b3fd62ea1a 14066 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
NYX 0:85b3fd62ea1a 14067 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14068 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
NYX 0:85b3fd62ea1a 14069 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
NYX 0:85b3fd62ea1a 14070 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14071 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
NYX 0:85b3fd62ea1a 14072 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
NYX 0:85b3fd62ea1a 14073 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14074 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
NYX 0:85b3fd62ea1a 14075 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
NYX 0:85b3fd62ea1a 14076 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14077 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
NYX 0:85b3fd62ea1a 14078 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
NYX 0:85b3fd62ea1a 14079 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14080 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
NYX 0:85b3fd62ea1a 14081 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
NYX 0:85b3fd62ea1a 14082 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14083 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
NYX 0:85b3fd62ea1a 14084 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
NYX 0:85b3fd62ea1a 14085 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14086 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
NYX 0:85b3fd62ea1a 14087 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
NYX 0:85b3fd62ea1a 14088 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14089 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
NYX 0:85b3fd62ea1a 14090 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
NYX 0:85b3fd62ea1a 14091 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14092 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
NYX 0:85b3fd62ea1a 14093 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
NYX 0:85b3fd62ea1a 14094 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14095 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
NYX 0:85b3fd62ea1a 14096 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
NYX 0:85b3fd62ea1a 14097 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 14098 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
NYX 0:85b3fd62ea1a 14099 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
NYX 0:85b3fd62ea1a 14100 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 14101 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
NYX 0:85b3fd62ea1a 14102 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
NYX 0:85b3fd62ea1a 14103 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 14104 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
NYX 0:85b3fd62ea1a 14105 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
NYX 0:85b3fd62ea1a 14106 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 14107 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
NYX 0:85b3fd62ea1a 14108 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
NYX 0:85b3fd62ea1a 14109 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14110 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
NYX 0:85b3fd62ea1a 14111 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
NYX 0:85b3fd62ea1a 14112 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14113 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
NYX 0:85b3fd62ea1a 14114 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
NYX 0:85b3fd62ea1a 14115 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14116 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
NYX 0:85b3fd62ea1a 14117 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
NYX 0:85b3fd62ea1a 14118 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14119 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
NYX 0:85b3fd62ea1a 14120
NYX 0:85b3fd62ea1a 14121 /******************** Bit definition forUSB_OTG_HCFG register ********************/
NYX 0:85b3fd62ea1a 14122
NYX 0:85b3fd62ea1a 14123 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
NYX 0:85b3fd62ea1a 14124 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 14125 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
NYX 0:85b3fd62ea1a 14126 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14127 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14128 #define USB_OTG_HCFG_FSLSS_Pos (2U)
NYX 0:85b3fd62ea1a 14129 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14130 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
NYX 0:85b3fd62ea1a 14131
NYX 0:85b3fd62ea1a 14132 /******************** Bit definition for USB_OTG_DCFG register ********************/
NYX 0:85b3fd62ea1a 14133
NYX 0:85b3fd62ea1a 14134 #define USB_OTG_DCFG_DSPD_Pos (0U)
NYX 0:85b3fd62ea1a 14135 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
NYX 0:85b3fd62ea1a 14136 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
NYX 0:85b3fd62ea1a 14137 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14138 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14139 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
NYX 0:85b3fd62ea1a 14140 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14141 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
NYX 0:85b3fd62ea1a 14142
NYX 0:85b3fd62ea1a 14143 #define USB_OTG_DCFG_DAD_Pos (4U)
NYX 0:85b3fd62ea1a 14144 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
NYX 0:85b3fd62ea1a 14145 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
NYX 0:85b3fd62ea1a 14146 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14147 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14148 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14149 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14150 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14151 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14152 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 14153
NYX 0:85b3fd62ea1a 14154 #define USB_OTG_DCFG_PFIVL_Pos (11U)
NYX 0:85b3fd62ea1a 14155 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
NYX 0:85b3fd62ea1a 14156 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
NYX 0:85b3fd62ea1a 14157 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 14158 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 14159
NYX 0:85b3fd62ea1a 14160 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
NYX 0:85b3fd62ea1a 14161 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
NYX 0:85b3fd62ea1a 14162 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
NYX 0:85b3fd62ea1a 14163 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14164 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 14165
NYX 0:85b3fd62ea1a 14166 /******************** Bit definition for USB_OTG_PCGCR register ********************/
NYX 0:85b3fd62ea1a 14167 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
NYX 0:85b3fd62ea1a 14168 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14169 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
NYX 0:85b3fd62ea1a 14170 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
NYX 0:85b3fd62ea1a 14171 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14172 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
NYX 0:85b3fd62ea1a 14173 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
NYX 0:85b3fd62ea1a 14174 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14175 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
NYX 0:85b3fd62ea1a 14176
NYX 0:85b3fd62ea1a 14177 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
NYX 0:85b3fd62ea1a 14178 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
NYX 0:85b3fd62ea1a 14179 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14180 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
NYX 0:85b3fd62ea1a 14181 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
NYX 0:85b3fd62ea1a 14182 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14183 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
NYX 0:85b3fd62ea1a 14184 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
NYX 0:85b3fd62ea1a 14185 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14186 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
NYX 0:85b3fd62ea1a 14187 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
NYX 0:85b3fd62ea1a 14188 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14189 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
NYX 0:85b3fd62ea1a 14190 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
NYX 0:85b3fd62ea1a 14191 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14192 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
NYX 0:85b3fd62ea1a 14193 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
NYX 0:85b3fd62ea1a 14194 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14195 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
NYX 0:85b3fd62ea1a 14196 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
NYX 0:85b3fd62ea1a 14197 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14198 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
NYX 0:85b3fd62ea1a 14199
NYX 0:85b3fd62ea1a 14200 /******************** Bit definition for USB_OTG_DCTL register ********************/
NYX 0:85b3fd62ea1a 14201 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
NYX 0:85b3fd62ea1a 14202 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14203 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
NYX 0:85b3fd62ea1a 14204 #define USB_OTG_DCTL_SDIS_Pos (1U)
NYX 0:85b3fd62ea1a 14205 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14206 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
NYX 0:85b3fd62ea1a 14207 #define USB_OTG_DCTL_GINSTS_Pos (2U)
NYX 0:85b3fd62ea1a 14208 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14209 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
NYX 0:85b3fd62ea1a 14210 #define USB_OTG_DCTL_GONSTS_Pos (3U)
NYX 0:85b3fd62ea1a 14211 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14212 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
NYX 0:85b3fd62ea1a 14213
NYX 0:85b3fd62ea1a 14214 #define USB_OTG_DCTL_TCTL_Pos (4U)
NYX 0:85b3fd62ea1a 14215 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
NYX 0:85b3fd62ea1a 14216 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
NYX 0:85b3fd62ea1a 14217 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14218 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14219 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14220 #define USB_OTG_DCTL_SGINAK_Pos (7U)
NYX 0:85b3fd62ea1a 14221 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14222 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
NYX 0:85b3fd62ea1a 14223 #define USB_OTG_DCTL_CGINAK_Pos (8U)
NYX 0:85b3fd62ea1a 14224 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14225 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
NYX 0:85b3fd62ea1a 14226 #define USB_OTG_DCTL_SGONAK_Pos (9U)
NYX 0:85b3fd62ea1a 14227 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14228 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
NYX 0:85b3fd62ea1a 14229 #define USB_OTG_DCTL_CGONAK_Pos (10U)
NYX 0:85b3fd62ea1a 14230 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 14231 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
NYX 0:85b3fd62ea1a 14232 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
NYX 0:85b3fd62ea1a 14233 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 14234 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
NYX 0:85b3fd62ea1a 14235
NYX 0:85b3fd62ea1a 14236 /******************** Bit definition for USB_OTG_HFIR register ********************/
NYX 0:85b3fd62ea1a 14237 #define USB_OTG_HFIR_FRIVL_Pos (0U)
NYX 0:85b3fd62ea1a 14238 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14239 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
NYX 0:85b3fd62ea1a 14240
NYX 0:85b3fd62ea1a 14241 /******************** Bit definition for USB_OTG_HFNUM register ********************/
NYX 0:85b3fd62ea1a 14242 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
NYX 0:85b3fd62ea1a 14243 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14244 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
NYX 0:85b3fd62ea1a 14245 #define USB_OTG_HFNUM_FTREM_Pos (16U)
NYX 0:85b3fd62ea1a 14246 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 14247 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
NYX 0:85b3fd62ea1a 14248
NYX 0:85b3fd62ea1a 14249 /******************** Bit definition for USB_OTG_DSTS register ********************/
NYX 0:85b3fd62ea1a 14250 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
NYX 0:85b3fd62ea1a 14251 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14252 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
NYX 0:85b3fd62ea1a 14253
NYX 0:85b3fd62ea1a 14254 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
NYX 0:85b3fd62ea1a 14255 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
NYX 0:85b3fd62ea1a 14256 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
NYX 0:85b3fd62ea1a 14257 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14258 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14259 #define USB_OTG_DSTS_EERR_Pos (3U)
NYX 0:85b3fd62ea1a 14260 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14261 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
NYX 0:85b3fd62ea1a 14262 #define USB_OTG_DSTS_FNSOF_Pos (8U)
NYX 0:85b3fd62ea1a 14263 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
NYX 0:85b3fd62ea1a 14264 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
NYX 0:85b3fd62ea1a 14265
NYX 0:85b3fd62ea1a 14266 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
NYX 0:85b3fd62ea1a 14267 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
NYX 0:85b3fd62ea1a 14268 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14269 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
NYX 0:85b3fd62ea1a 14270 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
NYX 0:85b3fd62ea1a 14271 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
NYX 0:85b3fd62ea1a 14272 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
NYX 0:85b3fd62ea1a 14273 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
NYX 0:85b3fd62ea1a 14274 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
NYX 0:85b3fd62ea1a 14275 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
NYX 0:85b3fd62ea1a 14276 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
NYX 0:85b3fd62ea1a 14277 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
NYX 0:85b3fd62ea1a 14278 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
NYX 0:85b3fd62ea1a 14279 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14280 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
NYX 0:85b3fd62ea1a 14281 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
NYX 0:85b3fd62ea1a 14282 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14283 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
NYX 0:85b3fd62ea1a 14284 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
NYX 0:85b3fd62ea1a 14285 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14286 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
NYX 0:85b3fd62ea1a 14287
NYX 0:85b3fd62ea1a 14288 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
NYX 0:85b3fd62ea1a 14289
NYX 0:85b3fd62ea1a 14290 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
NYX 0:85b3fd62ea1a 14291 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
NYX 0:85b3fd62ea1a 14292 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
NYX 0:85b3fd62ea1a 14293 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14294 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14295 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14296 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
NYX 0:85b3fd62ea1a 14297 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14298 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
NYX 0:85b3fd62ea1a 14299 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
NYX 0:85b3fd62ea1a 14300 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14301 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
NYX 0:85b3fd62ea1a 14302 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
NYX 0:85b3fd62ea1a 14303 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14304 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
NYX 0:85b3fd62ea1a 14305 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
NYX 0:85b3fd62ea1a 14306 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
NYX 0:85b3fd62ea1a 14307 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
NYX 0:85b3fd62ea1a 14308 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 14309 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 14310 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 14311 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 14312 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
NYX 0:85b3fd62ea1a 14313 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 14314 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
NYX 0:85b3fd62ea1a 14315 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
NYX 0:85b3fd62ea1a 14316 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14317 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
NYX 0:85b3fd62ea1a 14318 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
NYX 0:85b3fd62ea1a 14319 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14320 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
NYX 0:85b3fd62ea1a 14321 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
NYX 0:85b3fd62ea1a 14322 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14323 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
NYX 0:85b3fd62ea1a 14324 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
NYX 0:85b3fd62ea1a 14325 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14326 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
NYX 0:85b3fd62ea1a 14327 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
NYX 0:85b3fd62ea1a 14328 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14329 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
NYX 0:85b3fd62ea1a 14330 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
NYX 0:85b3fd62ea1a 14331 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 14332 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
NYX 0:85b3fd62ea1a 14333 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
NYX 0:85b3fd62ea1a 14334 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 14335 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
NYX 0:85b3fd62ea1a 14336 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
NYX 0:85b3fd62ea1a 14337 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14338 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
NYX 0:85b3fd62ea1a 14339 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
NYX 0:85b3fd62ea1a 14340 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 14341 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
NYX 0:85b3fd62ea1a 14342 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
NYX 0:85b3fd62ea1a 14343 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 14344 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
NYX 0:85b3fd62ea1a 14345 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
NYX 0:85b3fd62ea1a 14346 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 14347 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
NYX 0:85b3fd62ea1a 14348 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
NYX 0:85b3fd62ea1a 14349 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 14350 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
NYX 0:85b3fd62ea1a 14351
NYX 0:85b3fd62ea1a 14352 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
NYX 0:85b3fd62ea1a 14353 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
NYX 0:85b3fd62ea1a 14354 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14355 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
NYX 0:85b3fd62ea1a 14356 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
NYX 0:85b3fd62ea1a 14357 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14358 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
NYX 0:85b3fd62ea1a 14359 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
NYX 0:85b3fd62ea1a 14360 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14361 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
NYX 0:85b3fd62ea1a 14362 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
NYX 0:85b3fd62ea1a 14363 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14364 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
NYX 0:85b3fd62ea1a 14365 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
NYX 0:85b3fd62ea1a 14366 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14367 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
NYX 0:85b3fd62ea1a 14368
NYX 0:85b3fd62ea1a 14369
NYX 0:85b3fd62ea1a 14370 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
NYX 0:85b3fd62ea1a 14371 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
NYX 0:85b3fd62ea1a 14372 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
NYX 0:85b3fd62ea1a 14373 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14374 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14375 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14376 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14377 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 14378 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
NYX 0:85b3fd62ea1a 14379 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 14380 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
NYX 0:85b3fd62ea1a 14381 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
NYX 0:85b3fd62ea1a 14382 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 14383 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
NYX 0:85b3fd62ea1a 14384
NYX 0:85b3fd62ea1a 14385 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
NYX 0:85b3fd62ea1a 14386 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
NYX 0:85b3fd62ea1a 14387 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14388 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
NYX 0:85b3fd62ea1a 14389 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
NYX 0:85b3fd62ea1a 14390 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14391 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
NYX 0:85b3fd62ea1a 14392 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
NYX 0:85b3fd62ea1a 14393 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14394 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
NYX 0:85b3fd62ea1a 14395 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
NYX 0:85b3fd62ea1a 14396 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14397 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
NYX 0:85b3fd62ea1a 14398 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
NYX 0:85b3fd62ea1a 14399 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14400 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
NYX 0:85b3fd62ea1a 14401 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
NYX 0:85b3fd62ea1a 14402 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14403 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
NYX 0:85b3fd62ea1a 14404 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
NYX 0:85b3fd62ea1a 14405 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14406 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
NYX 0:85b3fd62ea1a 14407 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
NYX 0:85b3fd62ea1a 14408 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14409 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
NYX 0:85b3fd62ea1a 14410
NYX 0:85b3fd62ea1a 14411 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
NYX 0:85b3fd62ea1a 14412 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
NYX 0:85b3fd62ea1a 14413 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14414 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
NYX 0:85b3fd62ea1a 14415 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
NYX 0:85b3fd62ea1a 14416 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 14417 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
NYX 0:85b3fd62ea1a 14418 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 14419 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14420 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14421 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14422 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14423 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14424 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 14425 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 14426
NYX 0:85b3fd62ea1a 14427 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
NYX 0:85b3fd62ea1a 14428 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
NYX 0:85b3fd62ea1a 14429 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
NYX 0:85b3fd62ea1a 14430 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14431 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 14432 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 14433 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 14434 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 14435 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 14436 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 14437 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 14438
NYX 0:85b3fd62ea1a 14439 /******************** Bit definition for USB_OTG_HAINT register ********************/
NYX 0:85b3fd62ea1a 14440 #define USB_OTG_HAINT_HAINT_Pos (0U)
NYX 0:85b3fd62ea1a 14441 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14442 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
NYX 0:85b3fd62ea1a 14443
NYX 0:85b3fd62ea1a 14444 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
NYX 0:85b3fd62ea1a 14445 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
NYX 0:85b3fd62ea1a 14446 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14447 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
NYX 0:85b3fd62ea1a 14448 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
NYX 0:85b3fd62ea1a 14449 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14450 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
NYX 0:85b3fd62ea1a 14451 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
NYX 0:85b3fd62ea1a 14452 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14453 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
NYX 0:85b3fd62ea1a 14454 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
NYX 0:85b3fd62ea1a 14455 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14456 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
NYX 0:85b3fd62ea1a 14457 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
NYX 0:85b3fd62ea1a 14458 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14459 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
NYX 0:85b3fd62ea1a 14460 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
NYX 0:85b3fd62ea1a 14461 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14462 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
NYX 0:85b3fd62ea1a 14463 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
NYX 0:85b3fd62ea1a 14464 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14465 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
NYX 0:85b3fd62ea1a 14466 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
NYX 0:85b3fd62ea1a 14467 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14468 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
NYX 0:85b3fd62ea1a 14469
NYX 0:85b3fd62ea1a 14470 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
NYX 0:85b3fd62ea1a 14471 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
NYX 0:85b3fd62ea1a 14472 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14473 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
NYX 0:85b3fd62ea1a 14474 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
NYX 0:85b3fd62ea1a 14475 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14476 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
NYX 0:85b3fd62ea1a 14477 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
NYX 0:85b3fd62ea1a 14478 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14479 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
NYX 0:85b3fd62ea1a 14480 #define USB_OTG_GINTSTS_SOF_Pos (3U)
NYX 0:85b3fd62ea1a 14481 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14482 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
NYX 0:85b3fd62ea1a 14483 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
NYX 0:85b3fd62ea1a 14484 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14485 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
NYX 0:85b3fd62ea1a 14486 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
NYX 0:85b3fd62ea1a 14487 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14488 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
NYX 0:85b3fd62ea1a 14489 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
NYX 0:85b3fd62ea1a 14490 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14491 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
NYX 0:85b3fd62ea1a 14492 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
NYX 0:85b3fd62ea1a 14493 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14494 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
NYX 0:85b3fd62ea1a 14495 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
NYX 0:85b3fd62ea1a 14496 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 14497 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
NYX 0:85b3fd62ea1a 14498 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
NYX 0:85b3fd62ea1a 14499 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 14500 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
NYX 0:85b3fd62ea1a 14501 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
NYX 0:85b3fd62ea1a 14502 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 14503 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
NYX 0:85b3fd62ea1a 14504 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
NYX 0:85b3fd62ea1a 14505 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 14506 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
NYX 0:85b3fd62ea1a 14507 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
NYX 0:85b3fd62ea1a 14508 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 14509 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
NYX 0:85b3fd62ea1a 14510 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
NYX 0:85b3fd62ea1a 14511 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 14512 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
NYX 0:85b3fd62ea1a 14513 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
NYX 0:85b3fd62ea1a 14514 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14515 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
NYX 0:85b3fd62ea1a 14516 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
NYX 0:85b3fd62ea1a 14517 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14518 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
NYX 0:85b3fd62ea1a 14519 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
NYX 0:85b3fd62ea1a 14520 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14521 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
NYX 0:85b3fd62ea1a 14522 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
NYX 0:85b3fd62ea1a 14523 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14524 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
NYX 0:85b3fd62ea1a 14525 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
NYX 0:85b3fd62ea1a 14526 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 14527 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
NYX 0:85b3fd62ea1a 14528 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
NYX 0:85b3fd62ea1a 14529 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 14530 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
NYX 0:85b3fd62ea1a 14531 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
NYX 0:85b3fd62ea1a 14532 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14533 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
NYX 0:85b3fd62ea1a 14534 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
NYX 0:85b3fd62ea1a 14535 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 14536 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
NYX 0:85b3fd62ea1a 14537 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
NYX 0:85b3fd62ea1a 14538 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 14539 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
NYX 0:85b3fd62ea1a 14540 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
NYX 0:85b3fd62ea1a 14541 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 14542 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
NYX 0:85b3fd62ea1a 14543 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
NYX 0:85b3fd62ea1a 14544 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 14545 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
NYX 0:85b3fd62ea1a 14546 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
NYX 0:85b3fd62ea1a 14547 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 14548 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
NYX 0:85b3fd62ea1a 14549 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
NYX 0:85b3fd62ea1a 14550 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 14551 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
NYX 0:85b3fd62ea1a 14552 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
NYX 0:85b3fd62ea1a 14553 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 14554 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
NYX 0:85b3fd62ea1a 14555
NYX 0:85b3fd62ea1a 14556 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
NYX 0:85b3fd62ea1a 14557 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
NYX 0:85b3fd62ea1a 14558 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14559 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
NYX 0:85b3fd62ea1a 14560 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
NYX 0:85b3fd62ea1a 14561 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14562 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
NYX 0:85b3fd62ea1a 14563 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
NYX 0:85b3fd62ea1a 14564 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14565 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
NYX 0:85b3fd62ea1a 14566 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
NYX 0:85b3fd62ea1a 14567 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14568 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
NYX 0:85b3fd62ea1a 14569 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
NYX 0:85b3fd62ea1a 14570 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14571 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
NYX 0:85b3fd62ea1a 14572 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
NYX 0:85b3fd62ea1a 14573 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14574 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
NYX 0:85b3fd62ea1a 14575 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
NYX 0:85b3fd62ea1a 14576 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14577 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
NYX 0:85b3fd62ea1a 14578 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
NYX 0:85b3fd62ea1a 14579 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 14580 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
NYX 0:85b3fd62ea1a 14581 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
NYX 0:85b3fd62ea1a 14582 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 14583 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
NYX 0:85b3fd62ea1a 14584 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
NYX 0:85b3fd62ea1a 14585 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 14586 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
NYX 0:85b3fd62ea1a 14587 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
NYX 0:85b3fd62ea1a 14588 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 14589 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
NYX 0:85b3fd62ea1a 14590 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
NYX 0:85b3fd62ea1a 14591 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 14592 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
NYX 0:85b3fd62ea1a 14593 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
NYX 0:85b3fd62ea1a 14594 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 14595 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
NYX 0:85b3fd62ea1a 14596 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
NYX 0:85b3fd62ea1a 14597 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14598 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
NYX 0:85b3fd62ea1a 14599 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
NYX 0:85b3fd62ea1a 14600 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14601 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
NYX 0:85b3fd62ea1a 14602 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
NYX 0:85b3fd62ea1a 14603 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14604 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
NYX 0:85b3fd62ea1a 14605 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
NYX 0:85b3fd62ea1a 14606 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14607 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
NYX 0:85b3fd62ea1a 14608 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
NYX 0:85b3fd62ea1a 14609 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14610 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
NYX 0:85b3fd62ea1a 14611 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
NYX 0:85b3fd62ea1a 14612 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 14613 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
NYX 0:85b3fd62ea1a 14614 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
NYX 0:85b3fd62ea1a 14615 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 14616 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
NYX 0:85b3fd62ea1a 14617 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
NYX 0:85b3fd62ea1a 14618 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14619 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
NYX 0:85b3fd62ea1a 14620 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
NYX 0:85b3fd62ea1a 14621 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 14622 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
NYX 0:85b3fd62ea1a 14623 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
NYX 0:85b3fd62ea1a 14624 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 14625 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
NYX 0:85b3fd62ea1a 14626 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
NYX 0:85b3fd62ea1a 14627 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 14628 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
NYX 0:85b3fd62ea1a 14629 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
NYX 0:85b3fd62ea1a 14630 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 14631 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
NYX 0:85b3fd62ea1a 14632 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
NYX 0:85b3fd62ea1a 14633 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 14634 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
NYX 0:85b3fd62ea1a 14635 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
NYX 0:85b3fd62ea1a 14636 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 14637 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
NYX 0:85b3fd62ea1a 14638 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
NYX 0:85b3fd62ea1a 14639 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 14640 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
NYX 0:85b3fd62ea1a 14641
NYX 0:85b3fd62ea1a 14642 /******************** Bit definition for USB_OTG_DAINT register ********************/
NYX 0:85b3fd62ea1a 14643 #define USB_OTG_DAINT_IEPINT_Pos (0U)
NYX 0:85b3fd62ea1a 14644 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14645 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
NYX 0:85b3fd62ea1a 14646 #define USB_OTG_DAINT_OEPINT_Pos (16U)
NYX 0:85b3fd62ea1a 14647 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 14648 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
NYX 0:85b3fd62ea1a 14649
NYX 0:85b3fd62ea1a 14650 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
NYX 0:85b3fd62ea1a 14651 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
NYX 0:85b3fd62ea1a 14652 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14653 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
NYX 0:85b3fd62ea1a 14654
NYX 0:85b3fd62ea1a 14655 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
NYX 0:85b3fd62ea1a 14656 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
NYX 0:85b3fd62ea1a 14657 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 14658 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
NYX 0:85b3fd62ea1a 14659 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
NYX 0:85b3fd62ea1a 14660 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
NYX 0:85b3fd62ea1a 14661 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
NYX 0:85b3fd62ea1a 14662 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
NYX 0:85b3fd62ea1a 14663 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
NYX 0:85b3fd62ea1a 14664 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
NYX 0:85b3fd62ea1a 14665 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
NYX 0:85b3fd62ea1a 14666 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
NYX 0:85b3fd62ea1a 14667 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
NYX 0:85b3fd62ea1a 14668
NYX 0:85b3fd62ea1a 14669 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
NYX 0:85b3fd62ea1a 14670 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
NYX 0:85b3fd62ea1a 14671 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14672 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
NYX 0:85b3fd62ea1a 14673 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
NYX 0:85b3fd62ea1a 14674 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 14675 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
NYX 0:85b3fd62ea1a 14676
NYX 0:85b3fd62ea1a 14677 /******************** Bit definition for OTG register ********************/
NYX 0:85b3fd62ea1a 14678
NYX 0:85b3fd62ea1a 14679 #define USB_OTG_CHNUM_Pos (0U)
NYX 0:85b3fd62ea1a 14680 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 14681 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
NYX 0:85b3fd62ea1a 14682 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14683 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14684 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14685 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14686 #define USB_OTG_BCNT_Pos (4U)
NYX 0:85b3fd62ea1a 14687 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
NYX 0:85b3fd62ea1a 14688 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
NYX 0:85b3fd62ea1a 14689
NYX 0:85b3fd62ea1a 14690 #define USB_OTG_DPID_Pos (15U)
NYX 0:85b3fd62ea1a 14691 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
NYX 0:85b3fd62ea1a 14692 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
NYX 0:85b3fd62ea1a 14693 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 14694 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 14695
NYX 0:85b3fd62ea1a 14696 #define USB_OTG_PKTSTS_Pos (17U)
NYX 0:85b3fd62ea1a 14697 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
NYX 0:85b3fd62ea1a 14698 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
NYX 0:85b3fd62ea1a 14699 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14700 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14701 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14702 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14703
NYX 0:85b3fd62ea1a 14704 #define USB_OTG_EPNUM_Pos (0U)
NYX 0:85b3fd62ea1a 14705 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 14706 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
NYX 0:85b3fd62ea1a 14707 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14708 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14709 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14710 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14711
NYX 0:85b3fd62ea1a 14712 #define USB_OTG_FRMNUM_Pos (21U)
NYX 0:85b3fd62ea1a 14713 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
NYX 0:85b3fd62ea1a 14714 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
NYX 0:85b3fd62ea1a 14715 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14716 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 14717 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 14718 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14719
NYX 0:85b3fd62ea1a 14720 /******************** Bit definition for OTG register ********************/
NYX 0:85b3fd62ea1a 14721
NYX 0:85b3fd62ea1a 14722 #define USB_OTG_CHNUM_Pos (0U)
NYX 0:85b3fd62ea1a 14723 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 14724 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
NYX 0:85b3fd62ea1a 14725 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14726 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14727 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14728 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14729 #define USB_OTG_BCNT_Pos (4U)
NYX 0:85b3fd62ea1a 14730 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
NYX 0:85b3fd62ea1a 14731 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
NYX 0:85b3fd62ea1a 14732
NYX 0:85b3fd62ea1a 14733 #define USB_OTG_DPID_Pos (15U)
NYX 0:85b3fd62ea1a 14734 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
NYX 0:85b3fd62ea1a 14735 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
NYX 0:85b3fd62ea1a 14736 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 14737 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 14738
NYX 0:85b3fd62ea1a 14739 #define USB_OTG_PKTSTS_Pos (17U)
NYX 0:85b3fd62ea1a 14740 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
NYX 0:85b3fd62ea1a 14741 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
NYX 0:85b3fd62ea1a 14742 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14743 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14744 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14745 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14746
NYX 0:85b3fd62ea1a 14747 #define USB_OTG_EPNUM_Pos (0U)
NYX 0:85b3fd62ea1a 14748 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
NYX 0:85b3fd62ea1a 14749 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
NYX 0:85b3fd62ea1a 14750 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14751 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14752 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14753 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14754
NYX 0:85b3fd62ea1a 14755 #define USB_OTG_FRMNUM_Pos (21U)
NYX 0:85b3fd62ea1a 14756 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
NYX 0:85b3fd62ea1a 14757 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
NYX 0:85b3fd62ea1a 14758 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14759 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 14760 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 14761 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14762
NYX 0:85b3fd62ea1a 14763 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
NYX 0:85b3fd62ea1a 14764 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
NYX 0:85b3fd62ea1a 14765 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14766 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
NYX 0:85b3fd62ea1a 14767
NYX 0:85b3fd62ea1a 14768 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
NYX 0:85b3fd62ea1a 14769 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
NYX 0:85b3fd62ea1a 14770 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14771 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
NYX 0:85b3fd62ea1a 14772
NYX 0:85b3fd62ea1a 14773 /******************** Bit definition for OTG register ********************/
NYX 0:85b3fd62ea1a 14774 #define USB_OTG_NPTXFSA_Pos (0U)
NYX 0:85b3fd62ea1a 14775 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14776 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
NYX 0:85b3fd62ea1a 14777 #define USB_OTG_NPTXFD_Pos (16U)
NYX 0:85b3fd62ea1a 14778 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 14779 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
NYX 0:85b3fd62ea1a 14780 #define USB_OTG_TX0FSA_Pos (0U)
NYX 0:85b3fd62ea1a 14781 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14782 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
NYX 0:85b3fd62ea1a 14783 #define USB_OTG_TX0FD_Pos (16U)
NYX 0:85b3fd62ea1a 14784 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 14785 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
NYX 0:85b3fd62ea1a 14786
NYX 0:85b3fd62ea1a 14787 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
NYX 0:85b3fd62ea1a 14788 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
NYX 0:85b3fd62ea1a 14789 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
NYX 0:85b3fd62ea1a 14790 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
NYX 0:85b3fd62ea1a 14791
NYX 0:85b3fd62ea1a 14792 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
NYX 0:85b3fd62ea1a 14793 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
NYX 0:85b3fd62ea1a 14794 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14795 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
NYX 0:85b3fd62ea1a 14796
NYX 0:85b3fd62ea1a 14797 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
NYX 0:85b3fd62ea1a 14798 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
NYX 0:85b3fd62ea1a 14799 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
NYX 0:85b3fd62ea1a 14800 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 14801 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14802 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14803 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14804 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14805 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14806 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 14807 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 14808
NYX 0:85b3fd62ea1a 14809 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
NYX 0:85b3fd62ea1a 14810 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
NYX 0:85b3fd62ea1a 14811 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
NYX 0:85b3fd62ea1a 14812 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14813 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 14814 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 14815 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 14816 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 14817 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 14818 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 14819
NYX 0:85b3fd62ea1a 14820 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
NYX 0:85b3fd62ea1a 14821 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
NYX 0:85b3fd62ea1a 14822 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14823 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
NYX 0:85b3fd62ea1a 14824 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
NYX 0:85b3fd62ea1a 14825 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14826 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
NYX 0:85b3fd62ea1a 14827
NYX 0:85b3fd62ea1a 14828 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
NYX 0:85b3fd62ea1a 14829 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
NYX 0:85b3fd62ea1a 14830 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
NYX 0:85b3fd62ea1a 14831 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14832 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14833 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14834 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14835 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14836 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14837 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14838 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14839 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 14840 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
NYX 0:85b3fd62ea1a 14841 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 14842 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
NYX 0:85b3fd62ea1a 14843
NYX 0:85b3fd62ea1a 14844 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
NYX 0:85b3fd62ea1a 14845 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
NYX 0:85b3fd62ea1a 14846 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
NYX 0:85b3fd62ea1a 14847 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14848 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 14849 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 14850 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 14851 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14852 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 14853 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 14854 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14855 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 14856 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
NYX 0:85b3fd62ea1a 14857 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 14858 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
NYX 0:85b3fd62ea1a 14859
NYX 0:85b3fd62ea1a 14860 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
NYX 0:85b3fd62ea1a 14861 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
NYX 0:85b3fd62ea1a 14862 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 14863 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
NYX 0:85b3fd62ea1a 14864
NYX 0:85b3fd62ea1a 14865 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
NYX 0:85b3fd62ea1a 14866 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
NYX 0:85b3fd62ea1a 14867 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14868 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
NYX 0:85b3fd62ea1a 14869 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
NYX 0:85b3fd62ea1a 14870 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14871 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
NYX 0:85b3fd62ea1a 14872
NYX 0:85b3fd62ea1a 14873 /******************** Bit definition for USB_OTG_GCCFG register ********************/
NYX 0:85b3fd62ea1a 14874 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
NYX 0:85b3fd62ea1a 14875 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 14876 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
NYX 0:85b3fd62ea1a 14877 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
NYX 0:85b3fd62ea1a 14878 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 14879 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
NYX 0:85b3fd62ea1a 14880
NYX 0:85b3fd62ea1a 14881 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
NYX 0:85b3fd62ea1a 14882 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
NYX 0:85b3fd62ea1a 14883 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14884 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
NYX 0:85b3fd62ea1a 14885 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
NYX 0:85b3fd62ea1a 14886 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 14887 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
NYX 0:85b3fd62ea1a 14888
NYX 0:85b3fd62ea1a 14889 /******************** Bit definition for USB_OTG_CID register ********************/
NYX 0:85b3fd62ea1a 14890 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
NYX 0:85b3fd62ea1a 14891 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 14892 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
NYX 0:85b3fd62ea1a 14893
NYX 0:85b3fd62ea1a 14894 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
NYX 0:85b3fd62ea1a 14895 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
NYX 0:85b3fd62ea1a 14896 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14897 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
NYX 0:85b3fd62ea1a 14898 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
NYX 0:85b3fd62ea1a 14899 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14900 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
NYX 0:85b3fd62ea1a 14901 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
NYX 0:85b3fd62ea1a 14902 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
NYX 0:85b3fd62ea1a 14903 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
NYX 0:85b3fd62ea1a 14904 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
NYX 0:85b3fd62ea1a 14905 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14906 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
NYX 0:85b3fd62ea1a 14907 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
NYX 0:85b3fd62ea1a 14908 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14909 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
NYX 0:85b3fd62ea1a 14910 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
NYX 0:85b3fd62ea1a 14911 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
NYX 0:85b3fd62ea1a 14912 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
NYX 0:85b3fd62ea1a 14913 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
NYX 0:85b3fd62ea1a 14914 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 14915 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
NYX 0:85b3fd62ea1a 14916 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
NYX 0:85b3fd62ea1a 14917 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
NYX 0:85b3fd62ea1a 14918 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
NYX 0:85b3fd62ea1a 14919 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
NYX 0:85b3fd62ea1a 14920 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 14921 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
NYX 0:85b3fd62ea1a 14922 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
NYX 0:85b3fd62ea1a 14923 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 14924 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
NYX 0:85b3fd62ea1a 14925 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
NYX 0:85b3fd62ea1a 14926 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
NYX 0:85b3fd62ea1a 14927 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
NYX 0:85b3fd62ea1a 14928 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
NYX 0:85b3fd62ea1a 14929 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
NYX 0:85b3fd62ea1a 14930 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
NYX 0:85b3fd62ea1a 14931 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
NYX 0:85b3fd62ea1a 14932 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 14933 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
NYX 0:85b3fd62ea1a 14934 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
NYX 0:85b3fd62ea1a 14935 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
NYX 0:85b3fd62ea1a 14936 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
NYX 0:85b3fd62ea1a 14937 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
NYX 0:85b3fd62ea1a 14938 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 14939 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
NYX 0:85b3fd62ea1a 14940
NYX 0:85b3fd62ea1a 14941 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
NYX 0:85b3fd62ea1a 14942 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
NYX 0:85b3fd62ea1a 14943 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14944 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
NYX 0:85b3fd62ea1a 14945 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
NYX 0:85b3fd62ea1a 14946 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14947 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
NYX 0:85b3fd62ea1a 14948 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
NYX 0:85b3fd62ea1a 14949 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14950 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
NYX 0:85b3fd62ea1a 14951 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
NYX 0:85b3fd62ea1a 14952 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14953 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
NYX 0:85b3fd62ea1a 14954 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
NYX 0:85b3fd62ea1a 14955 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14956 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
NYX 0:85b3fd62ea1a 14957 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
NYX 0:85b3fd62ea1a 14958 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14959 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
NYX 0:85b3fd62ea1a 14960 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
NYX 0:85b3fd62ea1a 14961 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14962 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
NYX 0:85b3fd62ea1a 14963 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
NYX 0:85b3fd62ea1a 14964 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 14965 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
NYX 0:85b3fd62ea1a 14966 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
NYX 0:85b3fd62ea1a 14967 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 14968 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
NYX 0:85b3fd62ea1a 14969
NYX 0:85b3fd62ea1a 14970 /******************** Bit definition for USB_OTG_HPRT register ********************/
NYX 0:85b3fd62ea1a 14971 #define USB_OTG_HPRT_PCSTS_Pos (0U)
NYX 0:85b3fd62ea1a 14972 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 14973 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
NYX 0:85b3fd62ea1a 14974 #define USB_OTG_HPRT_PCDET_Pos (1U)
NYX 0:85b3fd62ea1a 14975 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 14976 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
NYX 0:85b3fd62ea1a 14977 #define USB_OTG_HPRT_PENA_Pos (2U)
NYX 0:85b3fd62ea1a 14978 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 14979 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
NYX 0:85b3fd62ea1a 14980 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
NYX 0:85b3fd62ea1a 14981 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 14982 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
NYX 0:85b3fd62ea1a 14983 #define USB_OTG_HPRT_POCA_Pos (4U)
NYX 0:85b3fd62ea1a 14984 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 14985 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
NYX 0:85b3fd62ea1a 14986 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
NYX 0:85b3fd62ea1a 14987 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 14988 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
NYX 0:85b3fd62ea1a 14989 #define USB_OTG_HPRT_PRES_Pos (6U)
NYX 0:85b3fd62ea1a 14990 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 14991 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
NYX 0:85b3fd62ea1a 14992 #define USB_OTG_HPRT_PSUSP_Pos (7U)
NYX 0:85b3fd62ea1a 14993 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 14994 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
NYX 0:85b3fd62ea1a 14995 #define USB_OTG_HPRT_PRST_Pos (8U)
NYX 0:85b3fd62ea1a 14996 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 14997 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
NYX 0:85b3fd62ea1a 14998
NYX 0:85b3fd62ea1a 14999 #define USB_OTG_HPRT_PLSTS_Pos (10U)
NYX 0:85b3fd62ea1a 15000 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
NYX 0:85b3fd62ea1a 15001 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
NYX 0:85b3fd62ea1a 15002 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 15003 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 15004 #define USB_OTG_HPRT_PPWR_Pos (12U)
NYX 0:85b3fd62ea1a 15005 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 15006 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
NYX 0:85b3fd62ea1a 15007
NYX 0:85b3fd62ea1a 15008 #define USB_OTG_HPRT_PTCTL_Pos (13U)
NYX 0:85b3fd62ea1a 15009 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
NYX 0:85b3fd62ea1a 15010 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
NYX 0:85b3fd62ea1a 15011 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 15012 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 15013 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 15014 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 15015
NYX 0:85b3fd62ea1a 15016 #define USB_OTG_HPRT_PSPD_Pos (17U)
NYX 0:85b3fd62ea1a 15017 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
NYX 0:85b3fd62ea1a 15018 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
NYX 0:85b3fd62ea1a 15019 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 15020 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 15021
NYX 0:85b3fd62ea1a 15022 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
NYX 0:85b3fd62ea1a 15023 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
NYX 0:85b3fd62ea1a 15024 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 15025 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
NYX 0:85b3fd62ea1a 15026 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
NYX 0:85b3fd62ea1a 15027 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 15028 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
NYX 0:85b3fd62ea1a 15029 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
NYX 0:85b3fd62ea1a 15030 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 15031 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
NYX 0:85b3fd62ea1a 15032 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
NYX 0:85b3fd62ea1a 15033 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 15034 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
NYX 0:85b3fd62ea1a 15035 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
NYX 0:85b3fd62ea1a 15036 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 15037 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
NYX 0:85b3fd62ea1a 15038 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
NYX 0:85b3fd62ea1a 15039 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 15040 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
NYX 0:85b3fd62ea1a 15041 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
NYX 0:85b3fd62ea1a 15042 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 15043 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
NYX 0:85b3fd62ea1a 15044 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
NYX 0:85b3fd62ea1a 15045 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 15046 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
NYX 0:85b3fd62ea1a 15047 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
NYX 0:85b3fd62ea1a 15048 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 15049 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
NYX 0:85b3fd62ea1a 15050 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
NYX 0:85b3fd62ea1a 15051 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 15052 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
NYX 0:85b3fd62ea1a 15053 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
NYX 0:85b3fd62ea1a 15054 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 15055 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
NYX 0:85b3fd62ea1a 15056
NYX 0:85b3fd62ea1a 15057 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
NYX 0:85b3fd62ea1a 15058 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
NYX 0:85b3fd62ea1a 15059 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 15060 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
NYX 0:85b3fd62ea1a 15061 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
NYX 0:85b3fd62ea1a 15062 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 15063 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
NYX 0:85b3fd62ea1a 15064
NYX 0:85b3fd62ea1a 15065 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
NYX 0:85b3fd62ea1a 15066 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
NYX 0:85b3fd62ea1a 15067 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
NYX 0:85b3fd62ea1a 15068 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
NYX 0:85b3fd62ea1a 15069 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
NYX 0:85b3fd62ea1a 15070 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 15071 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
NYX 0:85b3fd62ea1a 15072 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
NYX 0:85b3fd62ea1a 15073 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 15074 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
NYX 0:85b3fd62ea1a 15075 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
NYX 0:85b3fd62ea1a 15076 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 15077 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
NYX 0:85b3fd62ea1a 15078
NYX 0:85b3fd62ea1a 15079 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
NYX 0:85b3fd62ea1a 15080 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
NYX 0:85b3fd62ea1a 15081 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
NYX 0:85b3fd62ea1a 15082 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 15083 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 15084 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
NYX 0:85b3fd62ea1a 15085 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 15086 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
NYX 0:85b3fd62ea1a 15087
NYX 0:85b3fd62ea1a 15088 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
NYX 0:85b3fd62ea1a 15089 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
NYX 0:85b3fd62ea1a 15090 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
NYX 0:85b3fd62ea1a 15091 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 15092 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 15093 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 15094 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 15095 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
NYX 0:85b3fd62ea1a 15096 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 15097 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
NYX 0:85b3fd62ea1a 15098 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
NYX 0:85b3fd62ea1a 15099 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 15100 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
NYX 0:85b3fd62ea1a 15101 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
NYX 0:85b3fd62ea1a 15102 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 15103 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
NYX 0:85b3fd62ea1a 15104 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
NYX 0:85b3fd62ea1a 15105 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 15106 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
NYX 0:85b3fd62ea1a 15107 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
NYX 0:85b3fd62ea1a 15108 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 15109 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
NYX 0:85b3fd62ea1a 15110 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
NYX 0:85b3fd62ea1a 15111 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 15112 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
NYX 0:85b3fd62ea1a 15113
NYX 0:85b3fd62ea1a 15114 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
NYX 0:85b3fd62ea1a 15115 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
NYX 0:85b3fd62ea1a 15116 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
NYX 0:85b3fd62ea1a 15117 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
NYX 0:85b3fd62ea1a 15118
NYX 0:85b3fd62ea1a 15119 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
NYX 0:85b3fd62ea1a 15120 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
NYX 0:85b3fd62ea1a 15121 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
NYX 0:85b3fd62ea1a 15122 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 15123 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 15124 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 15125 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 15126 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
NYX 0:85b3fd62ea1a 15127 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 15128 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
NYX 0:85b3fd62ea1a 15129 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
NYX 0:85b3fd62ea1a 15130 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 15131 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
NYX 0:85b3fd62ea1a 15132
NYX 0:85b3fd62ea1a 15133 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
NYX 0:85b3fd62ea1a 15134 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
NYX 0:85b3fd62ea1a 15135 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
NYX 0:85b3fd62ea1a 15136 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 15137 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 15138
NYX 0:85b3fd62ea1a 15139 #define USB_OTG_HCCHAR_MC_Pos (20U)
NYX 0:85b3fd62ea1a 15140 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
NYX 0:85b3fd62ea1a 15141 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
NYX 0:85b3fd62ea1a 15142 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 15143 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 15144
NYX 0:85b3fd62ea1a 15145 #define USB_OTG_HCCHAR_DAD_Pos (22U)
NYX 0:85b3fd62ea1a 15146 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
NYX 0:85b3fd62ea1a 15147 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
NYX 0:85b3fd62ea1a 15148 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
NYX 0:85b3fd62ea1a 15149 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
NYX 0:85b3fd62ea1a 15150 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
NYX 0:85b3fd62ea1a 15151 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
NYX 0:85b3fd62ea1a 15152 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 15153 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 15154 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 15155 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
NYX 0:85b3fd62ea1a 15156 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 15157 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
NYX 0:85b3fd62ea1a 15158 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
NYX 0:85b3fd62ea1a 15159 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 15160 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
NYX 0:85b3fd62ea1a 15161 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
NYX 0:85b3fd62ea1a 15162 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 15163 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
NYX 0:85b3fd62ea1a 15164
NYX 0:85b3fd62ea1a 15165 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
NYX 0:85b3fd62ea1a 15166
NYX 0:85b3fd62ea1a 15167 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
NYX 0:85b3fd62ea1a 15168 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
NYX 0:85b3fd62ea1a 15169 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
NYX 0:85b3fd62ea1a 15170 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 15171 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 15172 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 15173 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 15174 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 15175 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 15176 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 15177
NYX 0:85b3fd62ea1a 15178 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
NYX 0:85b3fd62ea1a 15179 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
NYX 0:85b3fd62ea1a 15180 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
NYX 0:85b3fd62ea1a 15181 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 15182 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 15183 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 15184 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 15185 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 15186 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 15187 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 15188
NYX 0:85b3fd62ea1a 15189 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
NYX 0:85b3fd62ea1a 15190 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
NYX 0:85b3fd62ea1a 15191 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
NYX 0:85b3fd62ea1a 15192 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 15193 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 15194 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
NYX 0:85b3fd62ea1a 15195 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
NYX 0:85b3fd62ea1a 15196 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
NYX 0:85b3fd62ea1a 15197 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
NYX 0:85b3fd62ea1a 15198 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 15199 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
NYX 0:85b3fd62ea1a 15200
NYX 0:85b3fd62ea1a 15201 /******************** Bit definition for USB_OTG_HCINT register ********************/
NYX 0:85b3fd62ea1a 15202 #define USB_OTG_HCINT_XFRC_Pos (0U)
NYX 0:85b3fd62ea1a 15203 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 15204 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
NYX 0:85b3fd62ea1a 15205 #define USB_OTG_HCINT_CHH_Pos (1U)
NYX 0:85b3fd62ea1a 15206 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 15207 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
NYX 0:85b3fd62ea1a 15208 #define USB_OTG_HCINT_AHBERR_Pos (2U)
NYX 0:85b3fd62ea1a 15209 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 15210 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
NYX 0:85b3fd62ea1a 15211 #define USB_OTG_HCINT_STALL_Pos (3U)
NYX 0:85b3fd62ea1a 15212 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 15213 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
NYX 0:85b3fd62ea1a 15214 #define USB_OTG_HCINT_NAK_Pos (4U)
NYX 0:85b3fd62ea1a 15215 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 15216 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
NYX 0:85b3fd62ea1a 15217 #define USB_OTG_HCINT_ACK_Pos (5U)
NYX 0:85b3fd62ea1a 15218 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 15219 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
NYX 0:85b3fd62ea1a 15220 #define USB_OTG_HCINT_NYET_Pos (6U)
NYX 0:85b3fd62ea1a 15221 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 15222 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
NYX 0:85b3fd62ea1a 15223 #define USB_OTG_HCINT_TXERR_Pos (7U)
NYX 0:85b3fd62ea1a 15224 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 15225 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
NYX 0:85b3fd62ea1a 15226 #define USB_OTG_HCINT_BBERR_Pos (8U)
NYX 0:85b3fd62ea1a 15227 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 15228 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
NYX 0:85b3fd62ea1a 15229 #define USB_OTG_HCINT_FRMOR_Pos (9U)
NYX 0:85b3fd62ea1a 15230 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 15231 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
NYX 0:85b3fd62ea1a 15232 #define USB_OTG_HCINT_DTERR_Pos (10U)
NYX 0:85b3fd62ea1a 15233 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 15234 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
NYX 0:85b3fd62ea1a 15235
NYX 0:85b3fd62ea1a 15236 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
NYX 0:85b3fd62ea1a 15237 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
NYX 0:85b3fd62ea1a 15238 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 15239 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
NYX 0:85b3fd62ea1a 15240 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
NYX 0:85b3fd62ea1a 15241 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 15242 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
NYX 0:85b3fd62ea1a 15243 #define USB_OTG_DIEPINT_TOC_Pos (3U)
NYX 0:85b3fd62ea1a 15244 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 15245 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
NYX 0:85b3fd62ea1a 15246 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
NYX 0:85b3fd62ea1a 15247 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 15248 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
NYX 0:85b3fd62ea1a 15249 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
NYX 0:85b3fd62ea1a 15250 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 15251 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
NYX 0:85b3fd62ea1a 15252 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
NYX 0:85b3fd62ea1a 15253 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 15254 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
NYX 0:85b3fd62ea1a 15255 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
NYX 0:85b3fd62ea1a 15256 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 15257 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
NYX 0:85b3fd62ea1a 15258 #define USB_OTG_DIEPINT_BNA_Pos (9U)
NYX 0:85b3fd62ea1a 15259 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 15260 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
NYX 0:85b3fd62ea1a 15261 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
NYX 0:85b3fd62ea1a 15262 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
NYX 0:85b3fd62ea1a 15263 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
NYX 0:85b3fd62ea1a 15264 #define USB_OTG_DIEPINT_BERR_Pos (12U)
NYX 0:85b3fd62ea1a 15265 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
NYX 0:85b3fd62ea1a 15266 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
NYX 0:85b3fd62ea1a 15267 #define USB_OTG_DIEPINT_NAK_Pos (13U)
NYX 0:85b3fd62ea1a 15268 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
NYX 0:85b3fd62ea1a 15269 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
NYX 0:85b3fd62ea1a 15270
NYX 0:85b3fd62ea1a 15271 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
NYX 0:85b3fd62ea1a 15272 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
NYX 0:85b3fd62ea1a 15273 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 15274 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
NYX 0:85b3fd62ea1a 15275 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
NYX 0:85b3fd62ea1a 15276 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 15277 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
NYX 0:85b3fd62ea1a 15278 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
NYX 0:85b3fd62ea1a 15279 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
NYX 0:85b3fd62ea1a 15280 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
NYX 0:85b3fd62ea1a 15281 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
NYX 0:85b3fd62ea1a 15282 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 15283 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
NYX 0:85b3fd62ea1a 15284 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
NYX 0:85b3fd62ea1a 15285 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 15286 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
NYX 0:85b3fd62ea1a 15287 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
NYX 0:85b3fd62ea1a 15288 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 15289 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
NYX 0:85b3fd62ea1a 15290 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
NYX 0:85b3fd62ea1a 15291 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 15292 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
NYX 0:85b3fd62ea1a 15293 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
NYX 0:85b3fd62ea1a 15294 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
NYX 0:85b3fd62ea1a 15295 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
NYX 0:85b3fd62ea1a 15296 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
NYX 0:85b3fd62ea1a 15297 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
NYX 0:85b3fd62ea1a 15298 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
NYX 0:85b3fd62ea1a 15299 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
NYX 0:85b3fd62ea1a 15300 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
NYX 0:85b3fd62ea1a 15301 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
NYX 0:85b3fd62ea1a 15302 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
NYX 0:85b3fd62ea1a 15303 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
NYX 0:85b3fd62ea1a 15304 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
NYX 0:85b3fd62ea1a 15305
NYX 0:85b3fd62ea1a 15306 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
NYX 0:85b3fd62ea1a 15307
NYX 0:85b3fd62ea1a 15308 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
NYX 0:85b3fd62ea1a 15309 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
NYX 0:85b3fd62ea1a 15310 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
NYX 0:85b3fd62ea1a 15311 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
NYX 0:85b3fd62ea1a 15312 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
NYX 0:85b3fd62ea1a 15313 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
NYX 0:85b3fd62ea1a 15314 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
NYX 0:85b3fd62ea1a 15315 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
NYX 0:85b3fd62ea1a 15316 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
NYX 0:85b3fd62ea1a 15317 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
NYX 0:85b3fd62ea1a 15318 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
NYX 0:85b3fd62ea1a 15319 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
NYX 0:85b3fd62ea1a 15320 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
NYX 0:85b3fd62ea1a 15321 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
NYX 0:85b3fd62ea1a 15322 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
NYX 0:85b3fd62ea1a 15323 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
NYX 0:85b3fd62ea1a 15324 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
NYX 0:85b3fd62ea1a 15325 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 15326 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
NYX 0:85b3fd62ea1a 15327 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
NYX 0:85b3fd62ea1a 15328 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
NYX 0:85b3fd62ea1a 15329 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
NYX 0:85b3fd62ea1a 15330 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 15331 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 15332
NYX 0:85b3fd62ea1a 15333 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
NYX 0:85b3fd62ea1a 15334 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
NYX 0:85b3fd62ea1a 15335 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 15336 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
NYX 0:85b3fd62ea1a 15337
NYX 0:85b3fd62ea1a 15338 /******************** Bit definition for USB_OTG_HCDMA register ********************/
NYX 0:85b3fd62ea1a 15339 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
NYX 0:85b3fd62ea1a 15340 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
NYX 0:85b3fd62ea1a 15341 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
NYX 0:85b3fd62ea1a 15342
NYX 0:85b3fd62ea1a 15343 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
NYX 0:85b3fd62ea1a 15344 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
NYX 0:85b3fd62ea1a 15345 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 15346 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
NYX 0:85b3fd62ea1a 15347
NYX 0:85b3fd62ea1a 15348 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
NYX 0:85b3fd62ea1a 15349 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
NYX 0:85b3fd62ea1a 15350 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
NYX 0:85b3fd62ea1a 15351 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
NYX 0:85b3fd62ea1a 15352 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
NYX 0:85b3fd62ea1a 15353 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
NYX 0:85b3fd62ea1a 15354 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
NYX 0:85b3fd62ea1a 15355
NYX 0:85b3fd62ea1a 15356 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
NYX 0:85b3fd62ea1a 15357
NYX 0:85b3fd62ea1a 15358 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
NYX 0:85b3fd62ea1a 15359 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
NYX 0:85b3fd62ea1a 15360 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
NYX 0:85b3fd62ea1a 15361 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
NYX 0:85b3fd62ea1a 15362 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
NYX 0:85b3fd62ea1a 15363 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
NYX 0:85b3fd62ea1a 15364 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
NYX 0:85b3fd62ea1a 15365 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
NYX 0:85b3fd62ea1a 15366 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
NYX 0:85b3fd62ea1a 15367 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
NYX 0:85b3fd62ea1a 15368 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
NYX 0:85b3fd62ea1a 15369 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
NYX 0:85b3fd62ea1a 15370 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
NYX 0:85b3fd62ea1a 15371 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 15372 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
NYX 0:85b3fd62ea1a 15373 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
NYX 0:85b3fd62ea1a 15374 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
NYX 0:85b3fd62ea1a 15375 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
NYX 0:85b3fd62ea1a 15376 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
NYX 0:85b3fd62ea1a 15377 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
NYX 0:85b3fd62ea1a 15378 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
NYX 0:85b3fd62ea1a 15379 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
NYX 0:85b3fd62ea1a 15380 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
NYX 0:85b3fd62ea1a 15381 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
NYX 0:85b3fd62ea1a 15382 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
NYX 0:85b3fd62ea1a 15383 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
NYX 0:85b3fd62ea1a 15384 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
NYX 0:85b3fd62ea1a 15385 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
NYX 0:85b3fd62ea1a 15386 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
NYX 0:85b3fd62ea1a 15387 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
NYX 0:85b3fd62ea1a 15388 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
NYX 0:85b3fd62ea1a 15389 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
NYX 0:85b3fd62ea1a 15390 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
NYX 0:85b3fd62ea1a 15391 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 15392 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
NYX 0:85b3fd62ea1a 15393 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
NYX 0:85b3fd62ea1a 15394 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
NYX 0:85b3fd62ea1a 15395 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
NYX 0:85b3fd62ea1a 15396
NYX 0:85b3fd62ea1a 15397 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
NYX 0:85b3fd62ea1a 15398 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
NYX 0:85b3fd62ea1a 15399 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 15400 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
NYX 0:85b3fd62ea1a 15401 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
NYX 0:85b3fd62ea1a 15402 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 15403 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
NYX 0:85b3fd62ea1a 15404 #define USB_OTG_DOEPINT_STUP_Pos (3U)
NYX 0:85b3fd62ea1a 15405 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
NYX 0:85b3fd62ea1a 15406 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
NYX 0:85b3fd62ea1a 15407 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
NYX 0:85b3fd62ea1a 15408 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 15409 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
NYX 0:85b3fd62ea1a 15410 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
NYX 0:85b3fd62ea1a 15411 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
NYX 0:85b3fd62ea1a 15412 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
NYX 0:85b3fd62ea1a 15413 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
NYX 0:85b3fd62ea1a 15414 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
NYX 0:85b3fd62ea1a 15415 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
NYX 0:85b3fd62ea1a 15416 #define USB_OTG_DOEPINT_NYET_Pos (14U)
NYX 0:85b3fd62ea1a 15417 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
NYX 0:85b3fd62ea1a 15418 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
NYX 0:85b3fd62ea1a 15419
NYX 0:85b3fd62ea1a 15420 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
NYX 0:85b3fd62ea1a 15421
NYX 0:85b3fd62ea1a 15422 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
NYX 0:85b3fd62ea1a 15423 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
NYX 0:85b3fd62ea1a 15424 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
NYX 0:85b3fd62ea1a 15425 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
NYX 0:85b3fd62ea1a 15426 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
NYX 0:85b3fd62ea1a 15427 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
NYX 0:85b3fd62ea1a 15428
NYX 0:85b3fd62ea1a 15429 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
NYX 0:85b3fd62ea1a 15430 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
NYX 0:85b3fd62ea1a 15431 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
NYX 0:85b3fd62ea1a 15432 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
NYX 0:85b3fd62ea1a 15433 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
NYX 0:85b3fd62ea1a 15434
NYX 0:85b3fd62ea1a 15435 /******************** Bit definition for PCGCCTL register ********************/
NYX 0:85b3fd62ea1a 15436 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
NYX 0:85b3fd62ea1a 15437 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
NYX 0:85b3fd62ea1a 15438 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
NYX 0:85b3fd62ea1a 15439 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
NYX 0:85b3fd62ea1a 15440 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
NYX 0:85b3fd62ea1a 15441 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
NYX 0:85b3fd62ea1a 15442 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
NYX 0:85b3fd62ea1a 15443 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
NYX 0:85b3fd62ea1a 15444 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
NYX 0:85b3fd62ea1a 15445
NYX 0:85b3fd62ea1a 15446 /**
NYX 0:85b3fd62ea1a 15447 * @}
NYX 0:85b3fd62ea1a 15448 */
NYX 0:85b3fd62ea1a 15449
NYX 0:85b3fd62ea1a 15450 /**
NYX 0:85b3fd62ea1a 15451 * @}
NYX 0:85b3fd62ea1a 15452 */
NYX 0:85b3fd62ea1a 15453
NYX 0:85b3fd62ea1a 15454 /** @addtogroup Exported_macros
NYX 0:85b3fd62ea1a 15455 * @{
NYX 0:85b3fd62ea1a 15456 */
NYX 0:85b3fd62ea1a 15457
NYX 0:85b3fd62ea1a 15458 /******************************* ADC Instances ********************************/
NYX 0:85b3fd62ea1a 15459 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
NYX 0:85b3fd62ea1a 15460 ((INSTANCE) == ADC2) || \
NYX 0:85b3fd62ea1a 15461 ((INSTANCE) == ADC3))
NYX 0:85b3fd62ea1a 15462
NYX 0:85b3fd62ea1a 15463 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
NYX 0:85b3fd62ea1a 15464
NYX 0:85b3fd62ea1a 15465 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
NYX 0:85b3fd62ea1a 15466
NYX 0:85b3fd62ea1a 15467 /******************************* CAN Instances ********************************/
NYX 0:85b3fd62ea1a 15468 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
NYX 0:85b3fd62ea1a 15469 ((INSTANCE) == CAN2))
NYX 0:85b3fd62ea1a 15470 /******************************* CRC Instances ********************************/
NYX 0:85b3fd62ea1a 15471 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
NYX 0:85b3fd62ea1a 15472
NYX 0:85b3fd62ea1a 15473 /******************************* DAC Instances ********************************/
NYX 0:85b3fd62ea1a 15474 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
NYX 0:85b3fd62ea1a 15475
NYX 0:85b3fd62ea1a 15476 /******************************* DCMI Instances *******************************/
NYX 0:85b3fd62ea1a 15477 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
NYX 0:85b3fd62ea1a 15478
NYX 0:85b3fd62ea1a 15479 /******************************** DMA Instances *******************************/
NYX 0:85b3fd62ea1a 15480 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
NYX 0:85b3fd62ea1a 15481 ((INSTANCE) == DMA1_Stream1) || \
NYX 0:85b3fd62ea1a 15482 ((INSTANCE) == DMA1_Stream2) || \
NYX 0:85b3fd62ea1a 15483 ((INSTANCE) == DMA1_Stream3) || \
NYX 0:85b3fd62ea1a 15484 ((INSTANCE) == DMA1_Stream4) || \
NYX 0:85b3fd62ea1a 15485 ((INSTANCE) == DMA1_Stream5) || \
NYX 0:85b3fd62ea1a 15486 ((INSTANCE) == DMA1_Stream6) || \
NYX 0:85b3fd62ea1a 15487 ((INSTANCE) == DMA1_Stream7) || \
NYX 0:85b3fd62ea1a 15488 ((INSTANCE) == DMA2_Stream0) || \
NYX 0:85b3fd62ea1a 15489 ((INSTANCE) == DMA2_Stream1) || \
NYX 0:85b3fd62ea1a 15490 ((INSTANCE) == DMA2_Stream2) || \
NYX 0:85b3fd62ea1a 15491 ((INSTANCE) == DMA2_Stream3) || \
NYX 0:85b3fd62ea1a 15492 ((INSTANCE) == DMA2_Stream4) || \
NYX 0:85b3fd62ea1a 15493 ((INSTANCE) == DMA2_Stream5) || \
NYX 0:85b3fd62ea1a 15494 ((INSTANCE) == DMA2_Stream6) || \
NYX 0:85b3fd62ea1a 15495 ((INSTANCE) == DMA2_Stream7))
NYX 0:85b3fd62ea1a 15496
NYX 0:85b3fd62ea1a 15497 /******************************* GPIO Instances *******************************/
NYX 0:85b3fd62ea1a 15498 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
NYX 0:85b3fd62ea1a 15499 ((INSTANCE) == GPIOB) || \
NYX 0:85b3fd62ea1a 15500 ((INSTANCE) == GPIOC) || \
NYX 0:85b3fd62ea1a 15501 ((INSTANCE) == GPIOD) || \
NYX 0:85b3fd62ea1a 15502 ((INSTANCE) == GPIOE) || \
NYX 0:85b3fd62ea1a 15503 ((INSTANCE) == GPIOF) || \
NYX 0:85b3fd62ea1a 15504 ((INSTANCE) == GPIOG) || \
NYX 0:85b3fd62ea1a 15505 ((INSTANCE) == GPIOH))
NYX 0:85b3fd62ea1a 15506
NYX 0:85b3fd62ea1a 15507 /******************************** I2C Instances *******************************/
NYX 0:85b3fd62ea1a 15508 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
NYX 0:85b3fd62ea1a 15509 ((INSTANCE) == I2C2) || \
NYX 0:85b3fd62ea1a 15510 ((INSTANCE) == I2C3))
NYX 0:85b3fd62ea1a 15511
NYX 0:85b3fd62ea1a 15512 /******************************* SMBUS Instances ******************************/
NYX 0:85b3fd62ea1a 15513 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
NYX 0:85b3fd62ea1a 15514
NYX 0:85b3fd62ea1a 15515 /******************************** I2S Instances *******************************/
NYX 0:85b3fd62ea1a 15516 #define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
NYX 0:85b3fd62ea1a 15517 ((INSTANCE) == SPI3))
NYX 0:85b3fd62ea1a 15518
NYX 0:85b3fd62ea1a 15519 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
NYX 0:85b3fd62ea1a 15520 ((INSTANCE) == SPI2) || \
NYX 0:85b3fd62ea1a 15521 ((INSTANCE) == SPI3))
NYX 0:85b3fd62ea1a 15522
NYX 0:85b3fd62ea1a 15523
NYX 0:85b3fd62ea1a 15524
NYX 0:85b3fd62ea1a 15525 /****************************** RTC Instances *********************************/
NYX 0:85b3fd62ea1a 15526 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
NYX 0:85b3fd62ea1a 15527
NYX 0:85b3fd62ea1a 15528 /******************************* SAI Instances ********************************/
NYX 0:85b3fd62ea1a 15529 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
NYX 0:85b3fd62ea1a 15530 ((PERIPH) == SAI1_Block_B) || \
NYX 0:85b3fd62ea1a 15531 ((PERIPH) == SAI2_Block_A) || \
NYX 0:85b3fd62ea1a 15532 ((PERIPH) == SAI2_Block_B))
NYX 0:85b3fd62ea1a 15533 /* Legacy define */
NYX 0:85b3fd62ea1a 15534
NYX 0:85b3fd62ea1a 15535 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
NYX 0:85b3fd62ea1a 15536
NYX 0:85b3fd62ea1a 15537 /******************************** SPI Instances *******************************/
NYX 0:85b3fd62ea1a 15538 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
NYX 0:85b3fd62ea1a 15539 ((INSTANCE) == SPI2) || \
NYX 0:85b3fd62ea1a 15540 ((INSTANCE) == SPI3) || \
NYX 0:85b3fd62ea1a 15541 ((INSTANCE) == SPI4))
NYX 0:85b3fd62ea1a 15542
NYX 0:85b3fd62ea1a 15543
NYX 0:85b3fd62ea1a 15544 /****************** TIM Instances : All supported instances *******************/
NYX 0:85b3fd62ea1a 15545 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15546 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15547 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15548 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15549 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15550 ((INSTANCE) == TIM6) || \
NYX 0:85b3fd62ea1a 15551 ((INSTANCE) == TIM7) || \
NYX 0:85b3fd62ea1a 15552 ((INSTANCE) == TIM8) || \
NYX 0:85b3fd62ea1a 15553 ((INSTANCE) == TIM9) || \
NYX 0:85b3fd62ea1a 15554 ((INSTANCE) == TIM10)|| \
NYX 0:85b3fd62ea1a 15555 ((INSTANCE) == TIM11)|| \
NYX 0:85b3fd62ea1a 15556 ((INSTANCE) == TIM12)|| \
NYX 0:85b3fd62ea1a 15557 ((INSTANCE) == TIM13)|| \
NYX 0:85b3fd62ea1a 15558 ((INSTANCE) == TIM14))
NYX 0:85b3fd62ea1a 15559
NYX 0:85b3fd62ea1a 15560 /************* TIM Instances : at least 1 capture/compare channel *************/
NYX 0:85b3fd62ea1a 15561 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15562 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15563 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15564 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15565 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15566 ((INSTANCE) == TIM8) || \
NYX 0:85b3fd62ea1a 15567 ((INSTANCE) == TIM9) || \
NYX 0:85b3fd62ea1a 15568 ((INSTANCE) == TIM10) || \
NYX 0:85b3fd62ea1a 15569 ((INSTANCE) == TIM11) || \
NYX 0:85b3fd62ea1a 15570 ((INSTANCE) == TIM12) || \
NYX 0:85b3fd62ea1a 15571 ((INSTANCE) == TIM13) || \
NYX 0:85b3fd62ea1a 15572 ((INSTANCE) == TIM14))
NYX 0:85b3fd62ea1a 15573
NYX 0:85b3fd62ea1a 15574 /************ TIM Instances : at least 2 capture/compare channels *************/
NYX 0:85b3fd62ea1a 15575 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15576 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15577 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15578 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15579 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15580 ((INSTANCE) == TIM8) || \
NYX 0:85b3fd62ea1a 15581 ((INSTANCE) == TIM9) || \
NYX 0:85b3fd62ea1a 15582 ((INSTANCE) == TIM12))
NYX 0:85b3fd62ea1a 15583
NYX 0:85b3fd62ea1a 15584 /************ TIM Instances : at least 3 capture/compare channels *************/
NYX 0:85b3fd62ea1a 15585 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15586 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15587 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15588 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15589 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15590 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15591
NYX 0:85b3fd62ea1a 15592 /************ TIM Instances : at least 4 capture/compare channels *************/
NYX 0:85b3fd62ea1a 15593 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15594 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15595 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15596 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15597 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15598 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15599
NYX 0:85b3fd62ea1a 15600 /******************** TIM Instances : Advanced-control timers *****************/
NYX 0:85b3fd62ea1a 15601 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15602 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15603
NYX 0:85b3fd62ea1a 15604 /******************* TIM Instances : Timer input XOR function *****************/
NYX 0:85b3fd62ea1a 15605 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15606 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15607 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15608 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15609 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15610 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15611
NYX 0:85b3fd62ea1a 15612 /****************** TIM Instances : DMA requests generation (UDE) *************/
NYX 0:85b3fd62ea1a 15613 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15614 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15615 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15616 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15617 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15618 ((INSTANCE) == TIM6) || \
NYX 0:85b3fd62ea1a 15619 ((INSTANCE) == TIM7) || \
NYX 0:85b3fd62ea1a 15620 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15621
NYX 0:85b3fd62ea1a 15622 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
NYX 0:85b3fd62ea1a 15623 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15624 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15625 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15626 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15627 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15628 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15629
NYX 0:85b3fd62ea1a 15630 /************ TIM Instances : DMA requests generation (COMDE) *****************/
NYX 0:85b3fd62ea1a 15631 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15632 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15633 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15634 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15635 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15636 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15637
NYX 0:85b3fd62ea1a 15638 /******************** TIM Instances : DMA burst feature ***********************/
NYX 0:85b3fd62ea1a 15639 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15640 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15641 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15642 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15643 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15644 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15645
NYX 0:85b3fd62ea1a 15646 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
NYX 0:85b3fd62ea1a 15647 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15648 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15649 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15650 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15651 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15652 ((INSTANCE) == TIM6) || \
NYX 0:85b3fd62ea1a 15653 ((INSTANCE) == TIM7) || \
NYX 0:85b3fd62ea1a 15654 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15655
NYX 0:85b3fd62ea1a 15656 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
NYX 0:85b3fd62ea1a 15657 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15658 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15659 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15660 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15661 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15662 ((INSTANCE) == TIM8) || \
NYX 0:85b3fd62ea1a 15663 ((INSTANCE) == TIM9) || \
NYX 0:85b3fd62ea1a 15664 ((INSTANCE) == TIM12))
NYX 0:85b3fd62ea1a 15665
NYX 0:85b3fd62ea1a 15666 /********************** TIM Instances : 32 bit Counter ************************/
NYX 0:85b3fd62ea1a 15667 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15668 ((INSTANCE) == TIM5))
NYX 0:85b3fd62ea1a 15669
NYX 0:85b3fd62ea1a 15670 /***************** TIM Instances : external trigger input availabe ************/
NYX 0:85b3fd62ea1a 15671 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15672 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15673 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15674 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15675 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15676 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15677
NYX 0:85b3fd62ea1a 15678 /****************** TIM Instances : remapping capability **********************/
NYX 0:85b3fd62ea1a 15679 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15680 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15681 ((INSTANCE) == TIM11))
NYX 0:85b3fd62ea1a 15682
NYX 0:85b3fd62ea1a 15683 /******************* TIM Instances : output(s) available **********************/
NYX 0:85b3fd62ea1a 15684 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
NYX 0:85b3fd62ea1a 15685 ((((INSTANCE) == TIM1) && \
NYX 0:85b3fd62ea1a 15686 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15687 ((CHANNEL) == TIM_CHANNEL_2) || \
NYX 0:85b3fd62ea1a 15688 ((CHANNEL) == TIM_CHANNEL_3) || \
NYX 0:85b3fd62ea1a 15689 ((CHANNEL) == TIM_CHANNEL_4))) \
NYX 0:85b3fd62ea1a 15690 || \
NYX 0:85b3fd62ea1a 15691 (((INSTANCE) == TIM2) && \
NYX 0:85b3fd62ea1a 15692 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15693 ((CHANNEL) == TIM_CHANNEL_2) || \
NYX 0:85b3fd62ea1a 15694 ((CHANNEL) == TIM_CHANNEL_3) || \
NYX 0:85b3fd62ea1a 15695 ((CHANNEL) == TIM_CHANNEL_4))) \
NYX 0:85b3fd62ea1a 15696 || \
NYX 0:85b3fd62ea1a 15697 (((INSTANCE) == TIM3) && \
NYX 0:85b3fd62ea1a 15698 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15699 ((CHANNEL) == TIM_CHANNEL_2) || \
NYX 0:85b3fd62ea1a 15700 ((CHANNEL) == TIM_CHANNEL_3) || \
NYX 0:85b3fd62ea1a 15701 ((CHANNEL) == TIM_CHANNEL_4))) \
NYX 0:85b3fd62ea1a 15702 || \
NYX 0:85b3fd62ea1a 15703 (((INSTANCE) == TIM4) && \
NYX 0:85b3fd62ea1a 15704 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15705 ((CHANNEL) == TIM_CHANNEL_2) || \
NYX 0:85b3fd62ea1a 15706 ((CHANNEL) == TIM_CHANNEL_3) || \
NYX 0:85b3fd62ea1a 15707 ((CHANNEL) == TIM_CHANNEL_4))) \
NYX 0:85b3fd62ea1a 15708 || \
NYX 0:85b3fd62ea1a 15709 (((INSTANCE) == TIM5) && \
NYX 0:85b3fd62ea1a 15710 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15711 ((CHANNEL) == TIM_CHANNEL_2) || \
NYX 0:85b3fd62ea1a 15712 ((CHANNEL) == TIM_CHANNEL_3) || \
NYX 0:85b3fd62ea1a 15713 ((CHANNEL) == TIM_CHANNEL_4))) \
NYX 0:85b3fd62ea1a 15714 || \
NYX 0:85b3fd62ea1a 15715 (((INSTANCE) == TIM8) && \
NYX 0:85b3fd62ea1a 15716 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15717 ((CHANNEL) == TIM_CHANNEL_2) || \
NYX 0:85b3fd62ea1a 15718 ((CHANNEL) == TIM_CHANNEL_3) || \
NYX 0:85b3fd62ea1a 15719 ((CHANNEL) == TIM_CHANNEL_4))) \
NYX 0:85b3fd62ea1a 15720 || \
NYX 0:85b3fd62ea1a 15721 (((INSTANCE) == TIM9) && \
NYX 0:85b3fd62ea1a 15722 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15723 ((CHANNEL) == TIM_CHANNEL_2))) \
NYX 0:85b3fd62ea1a 15724 || \
NYX 0:85b3fd62ea1a 15725 (((INSTANCE) == TIM10) && \
NYX 0:85b3fd62ea1a 15726 (((CHANNEL) == TIM_CHANNEL_1))) \
NYX 0:85b3fd62ea1a 15727 || \
NYX 0:85b3fd62ea1a 15728 (((INSTANCE) == TIM11) && \
NYX 0:85b3fd62ea1a 15729 (((CHANNEL) == TIM_CHANNEL_1))) \
NYX 0:85b3fd62ea1a 15730 || \
NYX 0:85b3fd62ea1a 15731 (((INSTANCE) == TIM12) && \
NYX 0:85b3fd62ea1a 15732 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15733 ((CHANNEL) == TIM_CHANNEL_2))) \
NYX 0:85b3fd62ea1a 15734 || \
NYX 0:85b3fd62ea1a 15735 (((INSTANCE) == TIM13) && \
NYX 0:85b3fd62ea1a 15736 (((CHANNEL) == TIM_CHANNEL_1))) \
NYX 0:85b3fd62ea1a 15737 || \
NYX 0:85b3fd62ea1a 15738 (((INSTANCE) == TIM14) && \
NYX 0:85b3fd62ea1a 15739 (((CHANNEL) == TIM_CHANNEL_1))))
NYX 0:85b3fd62ea1a 15740
NYX 0:85b3fd62ea1a 15741 /************ TIM Instances : complementary output(s) available ***************/
NYX 0:85b3fd62ea1a 15742 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
NYX 0:85b3fd62ea1a 15743 ((((INSTANCE) == TIM1) && \
NYX 0:85b3fd62ea1a 15744 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15745 ((CHANNEL) == TIM_CHANNEL_2) || \
NYX 0:85b3fd62ea1a 15746 ((CHANNEL) == TIM_CHANNEL_3))) \
NYX 0:85b3fd62ea1a 15747 || \
NYX 0:85b3fd62ea1a 15748 (((INSTANCE) == TIM8) && \
NYX 0:85b3fd62ea1a 15749 (((CHANNEL) == TIM_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 15750 ((CHANNEL) == TIM_CHANNEL_2) || \
NYX 0:85b3fd62ea1a 15751 ((CHANNEL) == TIM_CHANNEL_3))))
NYX 0:85b3fd62ea1a 15752
NYX 0:85b3fd62ea1a 15753 /****************** TIM Instances : supporting counting mode selection ********/
NYX 0:85b3fd62ea1a 15754 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15755 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15756 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15757 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15758 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15759 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15760
NYX 0:85b3fd62ea1a 15761 /****************** TIM Instances : supporting clock division *****************/
NYX 0:85b3fd62ea1a 15762 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15763 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15764 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15765 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15766 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15767 ((INSTANCE) == TIM8) || \
NYX 0:85b3fd62ea1a 15768 ((INSTANCE) == TIM9) || \
NYX 0:85b3fd62ea1a 15769 ((INSTANCE) == TIM10)|| \
NYX 0:85b3fd62ea1a 15770 ((INSTANCE) == TIM11)|| \
NYX 0:85b3fd62ea1a 15771 ((INSTANCE) == TIM12)|| \
NYX 0:85b3fd62ea1a 15772 ((INSTANCE) == TIM13)|| \
NYX 0:85b3fd62ea1a 15773 ((INSTANCE) == TIM14))
NYX 0:85b3fd62ea1a 15774
NYX 0:85b3fd62ea1a 15775 /****************** TIM Instances : supporting commutation event generation ***/
NYX 0:85b3fd62ea1a 15776 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
NYX 0:85b3fd62ea1a 15777 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15778
NYX 0:85b3fd62ea1a 15779
NYX 0:85b3fd62ea1a 15780 /****************** TIM Instances : supporting OCxREF clear *******************/
NYX 0:85b3fd62ea1a 15781 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15782 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15783 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15784 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15785 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15786 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15787
NYX 0:85b3fd62ea1a 15788 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
NYX 0:85b3fd62ea1a 15789 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15790 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15791 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15792 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15793 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15794 ((INSTANCE) == TIM8) || \
NYX 0:85b3fd62ea1a 15795 ((INSTANCE) == TIM9) || \
NYX 0:85b3fd62ea1a 15796 ((INSTANCE) == TIM12))
NYX 0:85b3fd62ea1a 15797
NYX 0:85b3fd62ea1a 15798 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
NYX 0:85b3fd62ea1a 15799 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15800 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15801 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15802 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15803 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15804 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15805
NYX 0:85b3fd62ea1a 15806 /****************** TIM Instances : supporting repetition counter *************/
NYX 0:85b3fd62ea1a 15807 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15808 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15809
NYX 0:85b3fd62ea1a 15810 /****************** TIM Instances : supporting encoder interface **************/
NYX 0:85b3fd62ea1a 15811 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15812 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15813 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15814 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15815 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15816 ((INSTANCE) == TIM8) || \
NYX 0:85b3fd62ea1a 15817 ((INSTANCE) == TIM9) || \
NYX 0:85b3fd62ea1a 15818 ((INSTANCE) == TIM12))
NYX 0:85b3fd62ea1a 15819 /****************** TIM Instances : supporting Hall sensor interface **********/
NYX 0:85b3fd62ea1a 15820 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15821 ((INSTANCE) == TIM2) || \
NYX 0:85b3fd62ea1a 15822 ((INSTANCE) == TIM3) || \
NYX 0:85b3fd62ea1a 15823 ((INSTANCE) == TIM4) || \
NYX 0:85b3fd62ea1a 15824 ((INSTANCE) == TIM5) || \
NYX 0:85b3fd62ea1a 15825 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15826 /****************** TIM Instances : supporting the break function *************/
NYX 0:85b3fd62ea1a 15827 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
NYX 0:85b3fd62ea1a 15828 ((INSTANCE) == TIM8))
NYX 0:85b3fd62ea1a 15829
NYX 0:85b3fd62ea1a 15830 /******************** USART Instances : Synchronous mode **********************/
NYX 0:85b3fd62ea1a 15831 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
NYX 0:85b3fd62ea1a 15832 ((INSTANCE) == USART2) || \
NYX 0:85b3fd62ea1a 15833 ((INSTANCE) == USART3) || \
NYX 0:85b3fd62ea1a 15834 ((INSTANCE) == USART6))
NYX 0:85b3fd62ea1a 15835
NYX 0:85b3fd62ea1a 15836 /******************** UART Instances : Half-Duplex mode **********************/
NYX 0:85b3fd62ea1a 15837 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
NYX 0:85b3fd62ea1a 15838 ((INSTANCE) == USART2) || \
NYX 0:85b3fd62ea1a 15839 ((INSTANCE) == USART3) || \
NYX 0:85b3fd62ea1a 15840 ((INSTANCE) == UART4) || \
NYX 0:85b3fd62ea1a 15841 ((INSTANCE) == UART5) || \
NYX 0:85b3fd62ea1a 15842 ((INSTANCE) == USART6))
NYX 0:85b3fd62ea1a 15843
NYX 0:85b3fd62ea1a 15844 /* Legacy defines */
NYX 0:85b3fd62ea1a 15845 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
NYX 0:85b3fd62ea1a 15846
NYX 0:85b3fd62ea1a 15847 /****************** UART Instances : Hardware Flow control ********************/
NYX 0:85b3fd62ea1a 15848 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
NYX 0:85b3fd62ea1a 15849 ((INSTANCE) == USART2) || \
NYX 0:85b3fd62ea1a 15850 ((INSTANCE) == USART3) || \
NYX 0:85b3fd62ea1a 15851 ((INSTANCE) == USART6))
NYX 0:85b3fd62ea1a 15852 /******************** UART Instances : LIN mode **********************/
NYX 0:85b3fd62ea1a 15853 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
NYX 0:85b3fd62ea1a 15854
NYX 0:85b3fd62ea1a 15855 /********************* UART Instances : Smart card mode ***********************/
NYX 0:85b3fd62ea1a 15856 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
NYX 0:85b3fd62ea1a 15857 ((INSTANCE) == USART2) || \
NYX 0:85b3fd62ea1a 15858 ((INSTANCE) == USART3) || \
NYX 0:85b3fd62ea1a 15859 ((INSTANCE) == USART6))
NYX 0:85b3fd62ea1a 15860
NYX 0:85b3fd62ea1a 15861 /*********************** UART Instances : IRDA mode ***************************/
NYX 0:85b3fd62ea1a 15862 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
NYX 0:85b3fd62ea1a 15863 ((INSTANCE) == USART2) || \
NYX 0:85b3fd62ea1a 15864 ((INSTANCE) == USART3) || \
NYX 0:85b3fd62ea1a 15865 ((INSTANCE) == UART4) || \
NYX 0:85b3fd62ea1a 15866 ((INSTANCE) == UART5) || \
NYX 0:85b3fd62ea1a 15867 ((INSTANCE) == USART6))
NYX 0:85b3fd62ea1a 15868
NYX 0:85b3fd62ea1a 15869
NYX 0:85b3fd62ea1a 15870 /*********************** PCD Instances ****************************************/
NYX 0:85b3fd62ea1a 15871 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
NYX 0:85b3fd62ea1a 15872 ((INSTANCE) == USB_OTG_HS))
NYX 0:85b3fd62ea1a 15873
NYX 0:85b3fd62ea1a 15874 /*********************** HCD Instances ****************************************/
NYX 0:85b3fd62ea1a 15875 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
NYX 0:85b3fd62ea1a 15876 ((INSTANCE) == USB_OTG_HS))
NYX 0:85b3fd62ea1a 15877
NYX 0:85b3fd62ea1a 15878 /****************************** SDIO Instances ********************************/
NYX 0:85b3fd62ea1a 15879 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
NYX 0:85b3fd62ea1a 15880
NYX 0:85b3fd62ea1a 15881 /****************************** IWDG Instances ********************************/
NYX 0:85b3fd62ea1a 15882 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
NYX 0:85b3fd62ea1a 15883
NYX 0:85b3fd62ea1a 15884 /****************************** WWDG Instances ********************************/
NYX 0:85b3fd62ea1a 15885 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
NYX 0:85b3fd62ea1a 15886
NYX 0:85b3fd62ea1a 15887
NYX 0:85b3fd62ea1a 15888 /****************************** QSPI Instances ********************************/
NYX 0:85b3fd62ea1a 15889 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
NYX 0:85b3fd62ea1a 15890
NYX 0:85b3fd62ea1a 15891 /******************************* CEC Instances ********************************/
NYX 0:85b3fd62ea1a 15892 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
NYX 0:85b3fd62ea1a 15893
NYX 0:85b3fd62ea1a 15894 /***************************** FMPI2C Instances *******************************/
NYX 0:85b3fd62ea1a 15895 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
NYX 0:85b3fd62ea1a 15896
NYX 0:85b3fd62ea1a 15897 /******************************* SPDIFRX Instances ********************************/
NYX 0:85b3fd62ea1a 15898 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
NYX 0:85b3fd62ea1a 15899 /****************************** USB Exported Constants ************************/
NYX 0:85b3fd62ea1a 15900 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
NYX 0:85b3fd62ea1a 15901 #define USB_OTG_FS_MAX_IN_ENDPOINTS 5U /* Including EP0 */
NYX 0:85b3fd62ea1a 15902 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 5U /* Including EP0 */
NYX 0:85b3fd62ea1a 15903 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
NYX 0:85b3fd62ea1a 15904 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
NYX 0:85b3fd62ea1a 15905 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
NYX 0:85b3fd62ea1a 15906 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
NYX 0:85b3fd62ea1a 15907 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
NYX 0:85b3fd62ea1a 15908
NYX 0:85b3fd62ea1a 15909 /*
NYX 0:85b3fd62ea1a 15910 * @brief Specific devices reset values definitions
NYX 0:85b3fd62ea1a 15911 */
NYX 0:85b3fd62ea1a 15912 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
NYX 0:85b3fd62ea1a 15913 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
NYX 0:85b3fd62ea1a 15914 #define RCC_PLLSAICFGR_RST_VALUE 0x04003010U
NYX 0:85b3fd62ea1a 15915
NYX 0:85b3fd62ea1a 15916 #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
NYX 0:85b3fd62ea1a 15917 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
NYX 0:85b3fd62ea1a 15918 #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
NYX 0:85b3fd62ea1a 15919 #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
NYX 0:85b3fd62ea1a 15920 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
NYX 0:85b3fd62ea1a 15921 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
NYX 0:85b3fd62ea1a 15922 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
NYX 0:85b3fd62ea1a 15923 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
NYX 0:85b3fd62ea1a 15924
NYX 0:85b3fd62ea1a 15925 #define RCC_PLLN_MIN_VALUE 50U
NYX 0:85b3fd62ea1a 15926 #define RCC_PLLN_MAX_VALUE 432U
NYX 0:85b3fd62ea1a 15927
NYX 0:85b3fd62ea1a 15928 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
NYX 0:85b3fd62ea1a 15929 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
NYX 0:85b3fd62ea1a 15930 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
NYX 0:85b3fd62ea1a 15931 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
NYX 0:85b3fd62ea1a 15932 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
NYX 0:85b3fd62ea1a 15933
NYX 0:85b3fd62ea1a 15934 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
NYX 0:85b3fd62ea1a 15935 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
NYX 0:85b3fd62ea1a 15936 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
NYX 0:85b3fd62ea1a 15937 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
NYX 0:85b3fd62ea1a 15938 #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
NYX 0:85b3fd62ea1a 15939
NYX 0:85b3fd62ea1a 15940 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
NYX 0:85b3fd62ea1a 15941 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
NYX 0:85b3fd62ea1a 15942 #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
NYX 0:85b3fd62ea1a 15943
NYX 0:85b3fd62ea1a 15944 /******************************************************************************/
NYX 0:85b3fd62ea1a 15945 /* For a painless codes migration between the STM32F4xx device product */
NYX 0:85b3fd62ea1a 15946 /* lines, the aliases defined below are put in place to overcome the */
NYX 0:85b3fd62ea1a 15947 /* differences in the interrupt handlers and IRQn definitions. */
NYX 0:85b3fd62ea1a 15948 /* No need to update developed interrupt code when moving across */
NYX 0:85b3fd62ea1a 15949 /* product lines within the same STM32F4 Family */
NYX 0:85b3fd62ea1a 15950 /******************************************************************************/
NYX 0:85b3fd62ea1a 15951 /* Aliases for __IRQn */
NYX 0:85b3fd62ea1a 15952 #define FSMC_IRQn FMC_IRQn
NYX 0:85b3fd62ea1a 15953
NYX 0:85b3fd62ea1a 15954 /* Aliases for __IRQHandler */
NYX 0:85b3fd62ea1a 15955 #define FSMC_IRQHandler FMC_IRQHandler
NYX 0:85b3fd62ea1a 15956 #define QuadSPI_IRQHandler QUADSPI_IRQHandler
NYX 0:85b3fd62ea1a 15957
NYX 0:85b3fd62ea1a 15958 /**
NYX 0:85b3fd62ea1a 15959 * @}
NYX 0:85b3fd62ea1a 15960 */
NYX 0:85b3fd62ea1a 15961
NYX 0:85b3fd62ea1a 15962 /**
NYX 0:85b3fd62ea1a 15963 * @}
NYX 0:85b3fd62ea1a 15964 */
NYX 0:85b3fd62ea1a 15965
NYX 0:85b3fd62ea1a 15966 /**
NYX 0:85b3fd62ea1a 15967 * @}
NYX 0:85b3fd62ea1a 15968 */
NYX 0:85b3fd62ea1a 15969
NYX 0:85b3fd62ea1a 15970 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 15971 }
NYX 0:85b3fd62ea1a 15972 #endif /* __cplusplus */
NYX 0:85b3fd62ea1a 15973
NYX 0:85b3fd62ea1a 15974 #endif /* __STM32F446xx_H */
NYX 0:85b3fd62ea1a 15975
NYX 0:85b3fd62ea1a 15976
NYX 0:85b3fd62ea1a 15977
NYX 0:85b3fd62ea1a 15978 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/