Takaaki Numai / mbed-dev

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Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /* mbed Microcontroller Library
NYX 0:85b3fd62ea1a 2 * Copyright (c) 2006-2017 ARM Limited
NYX 0:85b3fd62ea1a 3 *
NYX 0:85b3fd62ea1a 4 * Licensed under the Apache License, Version 2.0 (the "License");
NYX 0:85b3fd62ea1a 5 * you may not use this file except in compliance with the License.
NYX 0:85b3fd62ea1a 6 * You may obtain a copy of the License at
NYX 0:85b3fd62ea1a 7 *
NYX 0:85b3fd62ea1a 8 * http://www.apache.org/licenses/LICENSE-2.0
NYX 0:85b3fd62ea1a 9 *
NYX 0:85b3fd62ea1a 10 * Unless required by applicable law or agreed to in writing, software
NYX 0:85b3fd62ea1a 11 * distributed under the License is distributed on an "AS IS" BASIS,
NYX 0:85b3fd62ea1a 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
NYX 0:85b3fd62ea1a 13 * See the License for the specific language governing permissions and
NYX 0:85b3fd62ea1a 14 * limitations under the License.
NYX 0:85b3fd62ea1a 15 */
NYX 0:85b3fd62ea1a 16
NYX 0:85b3fd62ea1a 17 /**
NYX 0:85b3fd62ea1a 18 * This file configures the system clock as follows:
NYX 0:85b3fd62ea1a 19 *-----------------------------------------------------------------------------
NYX 0:85b3fd62ea1a 20 * System clock source | 1- USE_PLL_HSE_EXTC | 3- USE_PLL_HSI
NYX 0:85b3fd62ea1a 21 * | (external 8 MHz clock) | (internal 16 MHz)
NYX 0:85b3fd62ea1a 22 * | 2- USE_PLL_HSE_XTAL |
NYX 0:85b3fd62ea1a 23 * | (external 8 MHz xtal) |
NYX 0:85b3fd62ea1a 24 *-----------------------------------------------------------------------------
NYX 0:85b3fd62ea1a 25 * SYSCLK(MHz) | 180 | 180
NYX 0:85b3fd62ea1a 26 *-----------------------------------------------------------------------------
NYX 0:85b3fd62ea1a 27 * AHBCLK (MHz) | 180 | 180
NYX 0:85b3fd62ea1a 28 *-----------------------------------------------------------------------------
NYX 0:85b3fd62ea1a 29 * APB1CLK (MHz) | 45 | 45
NYX 0:85b3fd62ea1a 30 *-----------------------------------------------------------------------------
NYX 0:85b3fd62ea1a 31 * APB2CLK (MHz) | 90 | 90
NYX 0:85b3fd62ea1a 32 *-----------------------------------------------------------------------------
NYX 0:85b3fd62ea1a 33 * USB capable (48 MHz precise clock) | YES | YES (HSI calibration needed)
NYX 0:85b3fd62ea1a 34 *-----------------------------------------------------------------------------
NYX 0:85b3fd62ea1a 35 **/
NYX 0:85b3fd62ea1a 36
NYX 0:85b3fd62ea1a 37 #include "stm32f4xx.h"
NYX 0:85b3fd62ea1a 38 #include "mbed_assert.h"
NYX 0:85b3fd62ea1a 39
NYX 0:85b3fd62ea1a 40 /*!< Uncomment the following line if you need to relocate your vector Table in
NYX 0:85b3fd62ea1a 41 Internal SRAM. */
NYX 0:85b3fd62ea1a 42 /* #define VECT_TAB_SRAM */
NYX 0:85b3fd62ea1a 43 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
NYX 0:85b3fd62ea1a 44 This value must be a multiple of 0x200. */
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46
NYX 0:85b3fd62ea1a 47 // clock source is selected with CLOCK_SOURCE in json config
NYX 0:85b3fd62ea1a 48 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
NYX 0:85b3fd62ea1a 49 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
NYX 0:85b3fd62ea1a 50 #define USE_PLL_HSI 0x2 // Use HSI internal clock
NYX 0:85b3fd62ea1a 51
NYX 0:85b3fd62ea1a 52 //#define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)
NYX 0:85b3fd62ea1a 53
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
NYX 0:85b3fd62ea1a 56 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
NYX 0:85b3fd62ea1a 57 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
NYX 0:85b3fd62ea1a 60 uint8_t SetSysClock_PLL_HSI(void);
NYX 0:85b3fd62ea1a 61 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
NYX 0:85b3fd62ea1a 62
NYX 0:85b3fd62ea1a 63
NYX 0:85b3fd62ea1a 64 /**
NYX 0:85b3fd62ea1a 65 * @brief Setup the microcontroller system
NYX 0:85b3fd62ea1a 66 * Initialize the FPU setting, vector table location and External memory
NYX 0:85b3fd62ea1a 67 * configuration.
NYX 0:85b3fd62ea1a 68 * @param None
NYX 0:85b3fd62ea1a 69 * @retval None
NYX 0:85b3fd62ea1a 70 */
NYX 0:85b3fd62ea1a 71 void SystemInit(void)
NYX 0:85b3fd62ea1a 72 {
NYX 0:85b3fd62ea1a 73 /* FPU settings ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 74 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
NYX 0:85b3fd62ea1a 75 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
NYX 0:85b3fd62ea1a 76 #endif
NYX 0:85b3fd62ea1a 77 /* Reset the RCC clock configuration to the default reset state ------------*/
NYX 0:85b3fd62ea1a 78 /* Set HSION bit */
NYX 0:85b3fd62ea1a 79 RCC->CR |= (uint32_t)0x00000001;
NYX 0:85b3fd62ea1a 80
NYX 0:85b3fd62ea1a 81 /* Reset CFGR register */
NYX 0:85b3fd62ea1a 82 RCC->CFGR = 0x00000000;
NYX 0:85b3fd62ea1a 83
NYX 0:85b3fd62ea1a 84 /* Reset HSEON, CSSON and PLLON bits */
NYX 0:85b3fd62ea1a 85 RCC->CR &= (uint32_t)0xFEF6FFFF;
NYX 0:85b3fd62ea1a 86
NYX 0:85b3fd62ea1a 87 /* Reset PLLCFGR register */
NYX 0:85b3fd62ea1a 88 RCC->PLLCFGR = 0x24003010;
NYX 0:85b3fd62ea1a 89
NYX 0:85b3fd62ea1a 90 /* Reset HSEBYP bit */
NYX 0:85b3fd62ea1a 91 RCC->CR &= (uint32_t)0xFFFBFFFF;
NYX 0:85b3fd62ea1a 92
NYX 0:85b3fd62ea1a 93 /* Disable all interrupts */
NYX 0:85b3fd62ea1a 94 RCC->CIR = 0x00000000;
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
NYX 0:85b3fd62ea1a 97 SystemInit_ExtMemCtl();
NYX 0:85b3fd62ea1a 98 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
NYX 0:85b3fd62ea1a 99
NYX 0:85b3fd62ea1a 100 /* Configure the Vector Table location add offset address ------------------*/
NYX 0:85b3fd62ea1a 101 #ifdef VECT_TAB_SRAM
NYX 0:85b3fd62ea1a 102 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
NYX 0:85b3fd62ea1a 103 #else
NYX 0:85b3fd62ea1a 104 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
NYX 0:85b3fd62ea1a 105 #endif
NYX 0:85b3fd62ea1a 106
NYX 0:85b3fd62ea1a 107 }
NYX 0:85b3fd62ea1a 108
NYX 0:85b3fd62ea1a 109
NYX 0:85b3fd62ea1a 110 /**
NYX 0:85b3fd62ea1a 111 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
NYX 0:85b3fd62ea1a 112 * AHB/APBx prescalers and Flash settings
NYX 0:85b3fd62ea1a 113 * @note This function should be called only once the RCC clock configuration
NYX 0:85b3fd62ea1a 114 * is reset to the default reset state (done in SystemInit() function).
NYX 0:85b3fd62ea1a 115 * @param None
NYX 0:85b3fd62ea1a 116 * @retval None
NYX 0:85b3fd62ea1a 117 */
NYX 0:85b3fd62ea1a 118
NYX 0:85b3fd62ea1a 119 void SetSysClock(void)
NYX 0:85b3fd62ea1a 120 {
NYX 0:85b3fd62ea1a 121 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
NYX 0:85b3fd62ea1a 122 /* 1- Try to start with HSE and external clock */
NYX 0:85b3fd62ea1a 123 if (SetSysClock_PLL_HSE(1) == 0)
NYX 0:85b3fd62ea1a 124 #endif
NYX 0:85b3fd62ea1a 125 {
NYX 0:85b3fd62ea1a 126 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
NYX 0:85b3fd62ea1a 127 /* 2- If fail try to start with HSE and external xtal */
NYX 0:85b3fd62ea1a 128 if (SetSysClock_PLL_HSE(0) == 0)
NYX 0:85b3fd62ea1a 129 #endif
NYX 0:85b3fd62ea1a 130 {
NYX 0:85b3fd62ea1a 131 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
NYX 0:85b3fd62ea1a 132 /* 3- If fail start with HSI clock */
NYX 0:85b3fd62ea1a 133 if (SetSysClock_PLL_HSI() == 0)
NYX 0:85b3fd62ea1a 134 #endif
NYX 0:85b3fd62ea1a 135 {
NYX 0:85b3fd62ea1a 136 while(1) {
NYX 0:85b3fd62ea1a 137 MBED_ASSERT(1);
NYX 0:85b3fd62ea1a 138 }
NYX 0:85b3fd62ea1a 139 }
NYX 0:85b3fd62ea1a 140 }
NYX 0:85b3fd62ea1a 141 }
NYX 0:85b3fd62ea1a 142
NYX 0:85b3fd62ea1a 143 // Output clock on MCO2 pin(PC9) for debugging purpose
NYX 0:85b3fd62ea1a 144 #if DEBUG_MCO == 1
NYX 0:85b3fd62ea1a 145 HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
NYX 0:85b3fd62ea1a 146 #endif
NYX 0:85b3fd62ea1a 147 }
NYX 0:85b3fd62ea1a 148
NYX 0:85b3fd62ea1a 149 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
NYX 0:85b3fd62ea1a 150 /******************************************************************************/
NYX 0:85b3fd62ea1a 151 /* PLL (clocked by HSE) used as System clock source */
NYX 0:85b3fd62ea1a 152 /******************************************************************************/
NYX 0:85b3fd62ea1a 153 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
NYX 0:85b3fd62ea1a 154 {
NYX 0:85b3fd62ea1a 155 RCC_OscInitTypeDef RCC_OscInitStruct;
NYX 0:85b3fd62ea1a 156 RCC_ClkInitTypeDef RCC_ClkInitStruct;
NYX 0:85b3fd62ea1a 157 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
NYX 0:85b3fd62ea1a 158
NYX 0:85b3fd62ea1a 159 /* The voltage scaling allows optimizing the power consumption when the device is
NYX 0:85b3fd62ea1a 160 clocked below the maximum system frequency, to update the voltage scaling value
NYX 0:85b3fd62ea1a 161 regarding system frequency refer to product datasheet. */
NYX 0:85b3fd62ea1a 162 __HAL_RCC_PWR_CLK_ENABLE();
NYX 0:85b3fd62ea1a 163 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
NYX 0:85b3fd62ea1a 164
NYX 0:85b3fd62ea1a 165 // Enable HSE oscillator and activate PLL with HSE as source
NYX 0:85b3fd62ea1a 166 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
NYX 0:85b3fd62ea1a 167 if (bypass == 0) {
NYX 0:85b3fd62ea1a 168 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
NYX 0:85b3fd62ea1a 169 } else {
NYX 0:85b3fd62ea1a 170 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
NYX 0:85b3fd62ea1a 171 }
NYX 0:85b3fd62ea1a 172
NYX 0:85b3fd62ea1a 173 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
NYX 0:85b3fd62ea1a 174 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
NYX 0:85b3fd62ea1a 175 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
NYX 0:85b3fd62ea1a 176 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
NYX 0:85b3fd62ea1a 177 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
NYX 0:85b3fd62ea1a 178 RCC_OscInitStruct.PLL.PLLQ = 7; //
NYX 0:85b3fd62ea1a 179 RCC_OscInitStruct.PLL.PLLR = 2; //
NYX 0:85b3fd62ea1a 180 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
NYX 0:85b3fd62ea1a 181 return 0; // FAIL
NYX 0:85b3fd62ea1a 182 }
NYX 0:85b3fd62ea1a 183
NYX 0:85b3fd62ea1a 184 // Activate the OverDrive to reach the 180 MHz Frequency
NYX 0:85b3fd62ea1a 185 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
NYX 0:85b3fd62ea1a 186 return 0; // FAIL
NYX 0:85b3fd62ea1a 187 }
NYX 0:85b3fd62ea1a 188
NYX 0:85b3fd62ea1a 189 // Select PLLSAI output as USB clock source
NYX 0:85b3fd62ea1a 190 PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
NYX 0:85b3fd62ea1a 191 PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
NYX 0:85b3fd62ea1a 192 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
NYX 0:85b3fd62ea1a 193 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
NYX 0:85b3fd62ea1a 194 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
NYX 0:85b3fd62ea1a 195 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
NYX 0:85b3fd62ea1a 196
NYX 0:85b3fd62ea1a 197 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
NYX 0:85b3fd62ea1a 198 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
NYX 0:85b3fd62ea1a 199 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
NYX 0:85b3fd62ea1a 200 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
NYX 0:85b3fd62ea1a 201 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
NYX 0:85b3fd62ea1a 202 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
NYX 0:85b3fd62ea1a 203 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
NYX 0:85b3fd62ea1a 204 return 0; // FAIL
NYX 0:85b3fd62ea1a 205 }
NYX 0:85b3fd62ea1a 206
NYX 0:85b3fd62ea1a 207 // Output clock on MCO1 pin(PA8) for debugging purpose
NYX 0:85b3fd62ea1a 208 #if DEBUG_MCO == 1
NYX 0:85b3fd62ea1a 209 if (bypass == 0)
NYX 0:85b3fd62ea1a 210 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
NYX 0:85b3fd62ea1a 211 else
NYX 0:85b3fd62ea1a 212 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
NYX 0:85b3fd62ea1a 213 #endif
NYX 0:85b3fd62ea1a 214
NYX 0:85b3fd62ea1a 215 return 1; // OK
NYX 0:85b3fd62ea1a 216 }
NYX 0:85b3fd62ea1a 217 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
NYX 0:85b3fd62ea1a 218
NYX 0:85b3fd62ea1a 219 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
NYX 0:85b3fd62ea1a 220 /******************************************************************************/
NYX 0:85b3fd62ea1a 221 /* PLL (clocked by HSI) used as System clock source */
NYX 0:85b3fd62ea1a 222 /******************************************************************************/
NYX 0:85b3fd62ea1a 223 uint8_t SetSysClock_PLL_HSI(void)
NYX 0:85b3fd62ea1a 224 {
NYX 0:85b3fd62ea1a 225 RCC_OscInitTypeDef RCC_OscInitStruct;
NYX 0:85b3fd62ea1a 226 RCC_ClkInitTypeDef RCC_ClkInitStruct;
NYX 0:85b3fd62ea1a 227 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
NYX 0:85b3fd62ea1a 228
NYX 0:85b3fd62ea1a 229 /* The voltage scaling allows optimizing the power consumption when the device is
NYX 0:85b3fd62ea1a 230 clocked below the maximum system frequency, to update the voltage scaling value
NYX 0:85b3fd62ea1a 231 regarding system frequency refer to product datasheet. */
NYX 0:85b3fd62ea1a 232 __HAL_RCC_PWR_CLK_ENABLE();
NYX 0:85b3fd62ea1a 233 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
NYX 0:85b3fd62ea1a 234
NYX 0:85b3fd62ea1a 235 // Enable HSI oscillator and activate PLL with HSI as source
NYX 0:85b3fd62ea1a 236 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
NYX 0:85b3fd62ea1a 237 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
NYX 0:85b3fd62ea1a 238 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
NYX 0:85b3fd62ea1a 239 RCC_OscInitStruct.HSICalibrationValue = 16;
NYX 0:85b3fd62ea1a 240 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
NYX 0:85b3fd62ea1a 241 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
NYX 0:85b3fd62ea1a 242 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
NYX 0:85b3fd62ea1a 243 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
NYX 0:85b3fd62ea1a 244 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
NYX 0:85b3fd62ea1a 245 RCC_OscInitStruct.PLL.PLLQ = 7; //
NYX 0:85b3fd62ea1a 246 RCC_OscInitStruct.PLL.PLLQ = 6; //
NYX 0:85b3fd62ea1a 247 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
NYX 0:85b3fd62ea1a 248 return 0; // FAIL
NYX 0:85b3fd62ea1a 249 }
NYX 0:85b3fd62ea1a 250
NYX 0:85b3fd62ea1a 251 // Activate the OverDrive to reach the 180 MHz Frequency
NYX 0:85b3fd62ea1a 252 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
NYX 0:85b3fd62ea1a 253 return 0; // FAIL
NYX 0:85b3fd62ea1a 254 }
NYX 0:85b3fd62ea1a 255
NYX 0:85b3fd62ea1a 256 // Select PLLSAI output as USB clock source
NYX 0:85b3fd62ea1a 257 PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
NYX 0:85b3fd62ea1a 258 PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
NYX 0:85b3fd62ea1a 259 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
NYX 0:85b3fd62ea1a 260 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
NYX 0:85b3fd62ea1a 261 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
NYX 0:85b3fd62ea1a 262 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
NYX 0:85b3fd62ea1a 263
NYX 0:85b3fd62ea1a 264 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
NYX 0:85b3fd62ea1a 265 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
NYX 0:85b3fd62ea1a 266 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
NYX 0:85b3fd62ea1a 267 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
NYX 0:85b3fd62ea1a 268 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
NYX 0:85b3fd62ea1a 269 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
NYX 0:85b3fd62ea1a 270 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
NYX 0:85b3fd62ea1a 271 return 0; // FAIL
NYX 0:85b3fd62ea1a 272 }
NYX 0:85b3fd62ea1a 273
NYX 0:85b3fd62ea1a 274 // Output clock on MCO1 pin(PA8) for debugging purpose
NYX 0:85b3fd62ea1a 275 #if DEBUG_MCO == 1
NYX 0:85b3fd62ea1a 276 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
NYX 0:85b3fd62ea1a 277 #endif
NYX 0:85b3fd62ea1a 278
NYX 0:85b3fd62ea1a 279 return 1; // OK
NYX 0:85b3fd62ea1a 280 }
NYX 0:85b3fd62ea1a 281 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */