Takaaki Numai / mbed-dev

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Dependents:   Hobbyking_Cheetah_0511

cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

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NYX 0:85b3fd62ea1a 1 /**************************************************************************//**
NYX 0:85b3fd62ea1a 2 * @file cmsis_armclang.h
NYX 0:85b3fd62ea1a 3 * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
NYX 0:85b3fd62ea1a 4 * @version V5.0.3
NYX 0:85b3fd62ea1a 5 * @date 27. March 2017
NYX 0:85b3fd62ea1a 6 ******************************************************************************/
NYX 0:85b3fd62ea1a 7 /*
NYX 0:85b3fd62ea1a 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
NYX 0:85b3fd62ea1a 9 *
NYX 0:85b3fd62ea1a 10 * SPDX-License-Identifier: Apache-2.0
NYX 0:85b3fd62ea1a 11 *
NYX 0:85b3fd62ea1a 12 * Licensed under the Apache License, Version 2.0 (the License); you may
NYX 0:85b3fd62ea1a 13 * not use this file except in compliance with the License.
NYX 0:85b3fd62ea1a 14 * You may obtain a copy of the License at
NYX 0:85b3fd62ea1a 15 *
NYX 0:85b3fd62ea1a 16 * www.apache.org/licenses/LICENSE-2.0
NYX 0:85b3fd62ea1a 17 *
NYX 0:85b3fd62ea1a 18 * Unless required by applicable law or agreed to in writing, software
NYX 0:85b3fd62ea1a 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
NYX 0:85b3fd62ea1a 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
NYX 0:85b3fd62ea1a 21 * See the License for the specific language governing permissions and
NYX 0:85b3fd62ea1a 22 * limitations under the License.
NYX 0:85b3fd62ea1a 23 */
NYX 0:85b3fd62ea1a 24
NYX 0:85b3fd62ea1a 25 //lint -esym(9058, IRQn) disable MISRA 2012 Rule 2.4 for IRQn
NYX 0:85b3fd62ea1a 26
NYX 0:85b3fd62ea1a 27 #ifndef __CMSIS_ARMCLANG_H
NYX 0:85b3fd62ea1a 28 #define __CMSIS_ARMCLANG_H
NYX 0:85b3fd62ea1a 29
NYX 0:85b3fd62ea1a 30 #ifndef __ARM_COMPAT_H
NYX 0:85b3fd62ea1a 31 #include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
NYX 0:85b3fd62ea1a 32 #endif
NYX 0:85b3fd62ea1a 33
NYX 0:85b3fd62ea1a 34 /* CMSIS compiler specific defines */
NYX 0:85b3fd62ea1a 35 #ifndef __ASM
NYX 0:85b3fd62ea1a 36 #define __ASM __asm
NYX 0:85b3fd62ea1a 37 #endif
NYX 0:85b3fd62ea1a 38 #ifndef __INLINE
NYX 0:85b3fd62ea1a 39 #define __INLINE __inline
NYX 0:85b3fd62ea1a 40 #endif
NYX 0:85b3fd62ea1a 41 #ifndef __STATIC_INLINE
NYX 0:85b3fd62ea1a 42 #define __STATIC_INLINE static __inline
NYX 0:85b3fd62ea1a 43 #endif
NYX 0:85b3fd62ea1a 44 #ifndef __NO_RETURN
NYX 0:85b3fd62ea1a 45 #define __NO_RETURN __attribute__((noreturn))
NYX 0:85b3fd62ea1a 46 #endif
NYX 0:85b3fd62ea1a 47 #ifndef __USED
NYX 0:85b3fd62ea1a 48 #define __USED __attribute__((used))
NYX 0:85b3fd62ea1a 49 #endif
NYX 0:85b3fd62ea1a 50 #ifndef __WEAK
NYX 0:85b3fd62ea1a 51 #define __WEAK __attribute__((weak))
NYX 0:85b3fd62ea1a 52 #endif
NYX 0:85b3fd62ea1a 53 #ifndef __PACKED
NYX 0:85b3fd62ea1a 54 #define __PACKED __attribute__((packed, aligned(1)))
NYX 0:85b3fd62ea1a 55 #endif
NYX 0:85b3fd62ea1a 56 #ifndef __PACKED_STRUCT
NYX 0:85b3fd62ea1a 57 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
NYX 0:85b3fd62ea1a 58 #endif
NYX 0:85b3fd62ea1a 59 #ifndef __UNALIGNED_UINT32 /* deprecated */
NYX 0:85b3fd62ea1a 60 #pragma clang diagnostic push
NYX 0:85b3fd62ea1a 61 #pragma clang diagnostic ignored "-Wpacked"
NYX 0:85b3fd62ea1a 62 //lint -esym(9058, T_UINT32) disable MISRA 2012 Rule 2.4 for T_UINT32
NYX 0:85b3fd62ea1a 63 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
NYX 0:85b3fd62ea1a 64 #pragma clang diagnostic pop
NYX 0:85b3fd62ea1a 65 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
NYX 0:85b3fd62ea1a 66 #endif
NYX 0:85b3fd62ea1a 67 #ifndef __UNALIGNED_UINT16_WRITE
NYX 0:85b3fd62ea1a 68 #pragma clang diagnostic push
NYX 0:85b3fd62ea1a 69 #pragma clang diagnostic ignored "-Wpacked"
NYX 0:85b3fd62ea1a 70 //lint -esym(9058, T_UINT16_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
NYX 0:85b3fd62ea1a 71 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
NYX 0:85b3fd62ea1a 72 #pragma clang diagnostic pop
NYX 0:85b3fd62ea1a 73 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
NYX 0:85b3fd62ea1a 74 #endif
NYX 0:85b3fd62ea1a 75 #ifndef __UNALIGNED_UINT16_READ
NYX 0:85b3fd62ea1a 76 #pragma clang diagnostic push
NYX 0:85b3fd62ea1a 77 #pragma clang diagnostic ignored "-Wpacked"
NYX 0:85b3fd62ea1a 78 //lint -esym(9058, T_UINT16_READ) disable MISRA 2012 Rule 2.4 for T_UINT16_READ
NYX 0:85b3fd62ea1a 79 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
NYX 0:85b3fd62ea1a 80 #pragma clang diagnostic pop
NYX 0:85b3fd62ea1a 81 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
NYX 0:85b3fd62ea1a 82 #endif
NYX 0:85b3fd62ea1a 83 #ifndef __UNALIGNED_UINT32_WRITE
NYX 0:85b3fd62ea1a 84 #pragma clang diagnostic push
NYX 0:85b3fd62ea1a 85 #pragma clang diagnostic ignored "-Wpacked"
NYX 0:85b3fd62ea1a 86 //lint -esym(9058, T_UINT32_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
NYX 0:85b3fd62ea1a 87 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
NYX 0:85b3fd62ea1a 88 #pragma clang diagnostic pop
NYX 0:85b3fd62ea1a 89 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
NYX 0:85b3fd62ea1a 90 #endif
NYX 0:85b3fd62ea1a 91 #ifndef __UNALIGNED_UINT32_READ
NYX 0:85b3fd62ea1a 92 #pragma clang diagnostic push
NYX 0:85b3fd62ea1a 93 #pragma clang diagnostic ignored "-Wpacked"
NYX 0:85b3fd62ea1a 94 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
NYX 0:85b3fd62ea1a 95 #pragma clang diagnostic pop
NYX 0:85b3fd62ea1a 96 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
NYX 0:85b3fd62ea1a 97 #endif
NYX 0:85b3fd62ea1a 98 #ifndef __ALIGNED
NYX 0:85b3fd62ea1a 99 #define __ALIGNED(x) __attribute__((aligned(x)))
NYX 0:85b3fd62ea1a 100 #endif
NYX 0:85b3fd62ea1a 101
NYX 0:85b3fd62ea1a 102
NYX 0:85b3fd62ea1a 103 /* ########################### Core Function Access ########################### */
NYX 0:85b3fd62ea1a 104 /** \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 105 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
NYX 0:85b3fd62ea1a 106 @{
NYX 0:85b3fd62ea1a 107 */
NYX 0:85b3fd62ea1a 108
NYX 0:85b3fd62ea1a 109 /**
NYX 0:85b3fd62ea1a 110 \brief Enable IRQ Interrupts
NYX 0:85b3fd62ea1a 111 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
NYX 0:85b3fd62ea1a 112 Can only be executed in Privileged modes.
NYX 0:85b3fd62ea1a 113 */
NYX 0:85b3fd62ea1a 114 /* intrinsic void __enable_irq(); see arm_compat.h */
NYX 0:85b3fd62ea1a 115
NYX 0:85b3fd62ea1a 116
NYX 0:85b3fd62ea1a 117 /**
NYX 0:85b3fd62ea1a 118 \brief Disable IRQ Interrupts
NYX 0:85b3fd62ea1a 119 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
NYX 0:85b3fd62ea1a 120 Can only be executed in Privileged modes.
NYX 0:85b3fd62ea1a 121 */
NYX 0:85b3fd62ea1a 122 /* intrinsic void __disable_irq(); see arm_compat.h */
NYX 0:85b3fd62ea1a 123
NYX 0:85b3fd62ea1a 124
NYX 0:85b3fd62ea1a 125 /**
NYX 0:85b3fd62ea1a 126 \brief Get Control Register
NYX 0:85b3fd62ea1a 127 \details Returns the content of the Control Register.
NYX 0:85b3fd62ea1a 128 \return Control Register value
NYX 0:85b3fd62ea1a 129 */
NYX 0:85b3fd62ea1a 130 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
NYX 0:85b3fd62ea1a 131 {
NYX 0:85b3fd62ea1a 132 uint32_t result;
NYX 0:85b3fd62ea1a 133
NYX 0:85b3fd62ea1a 134 __ASM volatile ("MRS %0, control" : "=r" (result) );
NYX 0:85b3fd62ea1a 135 return(result);
NYX 0:85b3fd62ea1a 136 }
NYX 0:85b3fd62ea1a 137
NYX 0:85b3fd62ea1a 138
NYX 0:85b3fd62ea1a 139 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 140 /**
NYX 0:85b3fd62ea1a 141 \brief Get Control Register (non-secure)
NYX 0:85b3fd62ea1a 142 \details Returns the content of the non-secure Control Register when in secure mode.
NYX 0:85b3fd62ea1a 143 \return non-secure Control Register value
NYX 0:85b3fd62ea1a 144 */
NYX 0:85b3fd62ea1a 145 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
NYX 0:85b3fd62ea1a 146 {
NYX 0:85b3fd62ea1a 147 uint32_t result;
NYX 0:85b3fd62ea1a 148
NYX 0:85b3fd62ea1a 149 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
NYX 0:85b3fd62ea1a 150 return(result);
NYX 0:85b3fd62ea1a 151 }
NYX 0:85b3fd62ea1a 152 #endif
NYX 0:85b3fd62ea1a 153
NYX 0:85b3fd62ea1a 154
NYX 0:85b3fd62ea1a 155 /**
NYX 0:85b3fd62ea1a 156 \brief Set Control Register
NYX 0:85b3fd62ea1a 157 \details Writes the given value to the Control Register.
NYX 0:85b3fd62ea1a 158 \param [in] control Control Register value to set
NYX 0:85b3fd62ea1a 159 */
NYX 0:85b3fd62ea1a 160 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
NYX 0:85b3fd62ea1a 161 {
NYX 0:85b3fd62ea1a 162 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
NYX 0:85b3fd62ea1a 163 }
NYX 0:85b3fd62ea1a 164
NYX 0:85b3fd62ea1a 165
NYX 0:85b3fd62ea1a 166 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 167 /**
NYX 0:85b3fd62ea1a 168 \brief Set Control Register (non-secure)
NYX 0:85b3fd62ea1a 169 \details Writes the given value to the non-secure Control Register when in secure state.
NYX 0:85b3fd62ea1a 170 \param [in] control Control Register value to set
NYX 0:85b3fd62ea1a 171 */
NYX 0:85b3fd62ea1a 172 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
NYX 0:85b3fd62ea1a 173 {
NYX 0:85b3fd62ea1a 174 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
NYX 0:85b3fd62ea1a 175 }
NYX 0:85b3fd62ea1a 176 #endif
NYX 0:85b3fd62ea1a 177
NYX 0:85b3fd62ea1a 178
NYX 0:85b3fd62ea1a 179 /**
NYX 0:85b3fd62ea1a 180 \brief Get IPSR Register
NYX 0:85b3fd62ea1a 181 \details Returns the content of the IPSR Register.
NYX 0:85b3fd62ea1a 182 \return IPSR Register value
NYX 0:85b3fd62ea1a 183 */
NYX 0:85b3fd62ea1a 184 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
NYX 0:85b3fd62ea1a 185 {
NYX 0:85b3fd62ea1a 186 uint32_t result;
NYX 0:85b3fd62ea1a 187
NYX 0:85b3fd62ea1a 188 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
NYX 0:85b3fd62ea1a 189 return(result);
NYX 0:85b3fd62ea1a 190 }
NYX 0:85b3fd62ea1a 191
NYX 0:85b3fd62ea1a 192
NYX 0:85b3fd62ea1a 193 /**
NYX 0:85b3fd62ea1a 194 \brief Get APSR Register
NYX 0:85b3fd62ea1a 195 \details Returns the content of the APSR Register.
NYX 0:85b3fd62ea1a 196 \return APSR Register value
NYX 0:85b3fd62ea1a 197 */
NYX 0:85b3fd62ea1a 198 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
NYX 0:85b3fd62ea1a 199 {
NYX 0:85b3fd62ea1a 200 uint32_t result;
NYX 0:85b3fd62ea1a 201
NYX 0:85b3fd62ea1a 202 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
NYX 0:85b3fd62ea1a 203 return(result);
NYX 0:85b3fd62ea1a 204 }
NYX 0:85b3fd62ea1a 205
NYX 0:85b3fd62ea1a 206
NYX 0:85b3fd62ea1a 207 /**
NYX 0:85b3fd62ea1a 208 \brief Get xPSR Register
NYX 0:85b3fd62ea1a 209 \details Returns the content of the xPSR Register.
NYX 0:85b3fd62ea1a 210 \return xPSR Register value
NYX 0:85b3fd62ea1a 211 */
NYX 0:85b3fd62ea1a 212 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
NYX 0:85b3fd62ea1a 213 {
NYX 0:85b3fd62ea1a 214 uint32_t result;
NYX 0:85b3fd62ea1a 215
NYX 0:85b3fd62ea1a 216 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
NYX 0:85b3fd62ea1a 217 return(result);
NYX 0:85b3fd62ea1a 218 }
NYX 0:85b3fd62ea1a 219
NYX 0:85b3fd62ea1a 220
NYX 0:85b3fd62ea1a 221 /**
NYX 0:85b3fd62ea1a 222 \brief Get Process Stack Pointer
NYX 0:85b3fd62ea1a 223 \details Returns the current value of the Process Stack Pointer (PSP).
NYX 0:85b3fd62ea1a 224 \return PSP Register value
NYX 0:85b3fd62ea1a 225 */
NYX 0:85b3fd62ea1a 226 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
NYX 0:85b3fd62ea1a 227 {
NYX 0:85b3fd62ea1a 228 register uint32_t result;
NYX 0:85b3fd62ea1a 229
NYX 0:85b3fd62ea1a 230 __ASM volatile ("MRS %0, psp" : "=r" (result) );
NYX 0:85b3fd62ea1a 231 return(result);
NYX 0:85b3fd62ea1a 232 }
NYX 0:85b3fd62ea1a 233
NYX 0:85b3fd62ea1a 234
NYX 0:85b3fd62ea1a 235 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 236 /**
NYX 0:85b3fd62ea1a 237 \brief Get Process Stack Pointer (non-secure)
NYX 0:85b3fd62ea1a 238 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
NYX 0:85b3fd62ea1a 239 \return PSP Register value
NYX 0:85b3fd62ea1a 240 */
NYX 0:85b3fd62ea1a 241 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
NYX 0:85b3fd62ea1a 242 {
NYX 0:85b3fd62ea1a 243 register uint32_t result;
NYX 0:85b3fd62ea1a 244
NYX 0:85b3fd62ea1a 245 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
NYX 0:85b3fd62ea1a 246 return(result);
NYX 0:85b3fd62ea1a 247 }
NYX 0:85b3fd62ea1a 248 #endif
NYX 0:85b3fd62ea1a 249
NYX 0:85b3fd62ea1a 250
NYX 0:85b3fd62ea1a 251 /**
NYX 0:85b3fd62ea1a 252 \brief Set Process Stack Pointer
NYX 0:85b3fd62ea1a 253 \details Assigns the given value to the Process Stack Pointer (PSP).
NYX 0:85b3fd62ea1a 254 \param [in] topOfProcStack Process Stack Pointer value to set
NYX 0:85b3fd62ea1a 255 */
NYX 0:85b3fd62ea1a 256 __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
NYX 0:85b3fd62ea1a 257 {
NYX 0:85b3fd62ea1a 258 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
NYX 0:85b3fd62ea1a 259 }
NYX 0:85b3fd62ea1a 260
NYX 0:85b3fd62ea1a 261
NYX 0:85b3fd62ea1a 262 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 263 /**
NYX 0:85b3fd62ea1a 264 \brief Set Process Stack Pointer (non-secure)
NYX 0:85b3fd62ea1a 265 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
NYX 0:85b3fd62ea1a 266 \param [in] topOfProcStack Process Stack Pointer value to set
NYX 0:85b3fd62ea1a 267 */
NYX 0:85b3fd62ea1a 268 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
NYX 0:85b3fd62ea1a 269 {
NYX 0:85b3fd62ea1a 270 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
NYX 0:85b3fd62ea1a 271 }
NYX 0:85b3fd62ea1a 272 #endif
NYX 0:85b3fd62ea1a 273
NYX 0:85b3fd62ea1a 274
NYX 0:85b3fd62ea1a 275 /**
NYX 0:85b3fd62ea1a 276 \brief Get Main Stack Pointer
NYX 0:85b3fd62ea1a 277 \details Returns the current value of the Main Stack Pointer (MSP).
NYX 0:85b3fd62ea1a 278 \return MSP Register value
NYX 0:85b3fd62ea1a 279 */
NYX 0:85b3fd62ea1a 280 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
NYX 0:85b3fd62ea1a 281 {
NYX 0:85b3fd62ea1a 282 register uint32_t result;
NYX 0:85b3fd62ea1a 283
NYX 0:85b3fd62ea1a 284 __ASM volatile ("MRS %0, msp" : "=r" (result) );
NYX 0:85b3fd62ea1a 285 return(result);
NYX 0:85b3fd62ea1a 286 }
NYX 0:85b3fd62ea1a 287
NYX 0:85b3fd62ea1a 288
NYX 0:85b3fd62ea1a 289 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 290 /**
NYX 0:85b3fd62ea1a 291 \brief Get Main Stack Pointer (non-secure)
NYX 0:85b3fd62ea1a 292 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
NYX 0:85b3fd62ea1a 293 \return MSP Register value
NYX 0:85b3fd62ea1a 294 */
NYX 0:85b3fd62ea1a 295 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
NYX 0:85b3fd62ea1a 296 {
NYX 0:85b3fd62ea1a 297 register uint32_t result;
NYX 0:85b3fd62ea1a 298
NYX 0:85b3fd62ea1a 299 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
NYX 0:85b3fd62ea1a 300 return(result);
NYX 0:85b3fd62ea1a 301 }
NYX 0:85b3fd62ea1a 302 #endif
NYX 0:85b3fd62ea1a 303
NYX 0:85b3fd62ea1a 304
NYX 0:85b3fd62ea1a 305 /**
NYX 0:85b3fd62ea1a 306 \brief Set Main Stack Pointer
NYX 0:85b3fd62ea1a 307 \details Assigns the given value to the Main Stack Pointer (MSP).
NYX 0:85b3fd62ea1a 308 \param [in] topOfMainStack Main Stack Pointer value to set
NYX 0:85b3fd62ea1a 309 */
NYX 0:85b3fd62ea1a 310 __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
NYX 0:85b3fd62ea1a 311 {
NYX 0:85b3fd62ea1a 312 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
NYX 0:85b3fd62ea1a 313 }
NYX 0:85b3fd62ea1a 314
NYX 0:85b3fd62ea1a 315
NYX 0:85b3fd62ea1a 316 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 317 /**
NYX 0:85b3fd62ea1a 318 \brief Set Main Stack Pointer (non-secure)
NYX 0:85b3fd62ea1a 319 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
NYX 0:85b3fd62ea1a 320 \param [in] topOfMainStack Main Stack Pointer value to set
NYX 0:85b3fd62ea1a 321 */
NYX 0:85b3fd62ea1a 322 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
NYX 0:85b3fd62ea1a 323 {
NYX 0:85b3fd62ea1a 324 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
NYX 0:85b3fd62ea1a 325 }
NYX 0:85b3fd62ea1a 326 #endif
NYX 0:85b3fd62ea1a 327
NYX 0:85b3fd62ea1a 328
NYX 0:85b3fd62ea1a 329 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 330 /**
NYX 0:85b3fd62ea1a 331 \brief Get Stack Pointer (non-secure)
NYX 0:85b3fd62ea1a 332 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
NYX 0:85b3fd62ea1a 333 \return SP Register value
NYX 0:85b3fd62ea1a 334 */
NYX 0:85b3fd62ea1a 335 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
NYX 0:85b3fd62ea1a 336 {
NYX 0:85b3fd62ea1a 337 register uint32_t result;
NYX 0:85b3fd62ea1a 338
NYX 0:85b3fd62ea1a 339 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
NYX 0:85b3fd62ea1a 340 return(result);
NYX 0:85b3fd62ea1a 341 }
NYX 0:85b3fd62ea1a 342
NYX 0:85b3fd62ea1a 343
NYX 0:85b3fd62ea1a 344 /**
NYX 0:85b3fd62ea1a 345 \brief Set Stack Pointer (non-secure)
NYX 0:85b3fd62ea1a 346 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
NYX 0:85b3fd62ea1a 347 \param [in] topOfStack Stack Pointer value to set
NYX 0:85b3fd62ea1a 348 */
NYX 0:85b3fd62ea1a 349 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
NYX 0:85b3fd62ea1a 350 {
NYX 0:85b3fd62ea1a 351 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
NYX 0:85b3fd62ea1a 352 }
NYX 0:85b3fd62ea1a 353 #endif
NYX 0:85b3fd62ea1a 354
NYX 0:85b3fd62ea1a 355
NYX 0:85b3fd62ea1a 356 /**
NYX 0:85b3fd62ea1a 357 \brief Get Priority Mask
NYX 0:85b3fd62ea1a 358 \details Returns the current state of the priority mask bit from the Priority Mask Register.
NYX 0:85b3fd62ea1a 359 \return Priority Mask value
NYX 0:85b3fd62ea1a 360 */
NYX 0:85b3fd62ea1a 361 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
NYX 0:85b3fd62ea1a 362 {
NYX 0:85b3fd62ea1a 363 uint32_t result;
NYX 0:85b3fd62ea1a 364
NYX 0:85b3fd62ea1a 365 __ASM volatile ("MRS %0, primask" : "=r" (result) );
NYX 0:85b3fd62ea1a 366 return(result);
NYX 0:85b3fd62ea1a 367 }
NYX 0:85b3fd62ea1a 368
NYX 0:85b3fd62ea1a 369
NYX 0:85b3fd62ea1a 370 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 371 /**
NYX 0:85b3fd62ea1a 372 \brief Get Priority Mask (non-secure)
NYX 0:85b3fd62ea1a 373 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
NYX 0:85b3fd62ea1a 374 \return Priority Mask value
NYX 0:85b3fd62ea1a 375 */
NYX 0:85b3fd62ea1a 376 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
NYX 0:85b3fd62ea1a 377 {
NYX 0:85b3fd62ea1a 378 uint32_t result;
NYX 0:85b3fd62ea1a 379
NYX 0:85b3fd62ea1a 380 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
NYX 0:85b3fd62ea1a 381 return(result);
NYX 0:85b3fd62ea1a 382 }
NYX 0:85b3fd62ea1a 383 #endif
NYX 0:85b3fd62ea1a 384
NYX 0:85b3fd62ea1a 385
NYX 0:85b3fd62ea1a 386 /**
NYX 0:85b3fd62ea1a 387 \brief Set Priority Mask
NYX 0:85b3fd62ea1a 388 \details Assigns the given value to the Priority Mask Register.
NYX 0:85b3fd62ea1a 389 \param [in] priMask Priority Mask
NYX 0:85b3fd62ea1a 390 */
NYX 0:85b3fd62ea1a 391 __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
NYX 0:85b3fd62ea1a 392 {
NYX 0:85b3fd62ea1a 393 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
NYX 0:85b3fd62ea1a 394 }
NYX 0:85b3fd62ea1a 395
NYX 0:85b3fd62ea1a 396
NYX 0:85b3fd62ea1a 397 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 398 /**
NYX 0:85b3fd62ea1a 399 \brief Set Priority Mask (non-secure)
NYX 0:85b3fd62ea1a 400 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
NYX 0:85b3fd62ea1a 401 \param [in] priMask Priority Mask
NYX 0:85b3fd62ea1a 402 */
NYX 0:85b3fd62ea1a 403 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
NYX 0:85b3fd62ea1a 404 {
NYX 0:85b3fd62ea1a 405 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
NYX 0:85b3fd62ea1a 406 }
NYX 0:85b3fd62ea1a 407 #endif
NYX 0:85b3fd62ea1a 408
NYX 0:85b3fd62ea1a 409
NYX 0:85b3fd62ea1a 410 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
NYX 0:85b3fd62ea1a 411 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
NYX 0:85b3fd62ea1a 412 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
NYX 0:85b3fd62ea1a 413 /**
NYX 0:85b3fd62ea1a 414 \brief Enable FIQ
NYX 0:85b3fd62ea1a 415 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
NYX 0:85b3fd62ea1a 416 Can only be executed in Privileged modes.
NYX 0:85b3fd62ea1a 417 */
NYX 0:85b3fd62ea1a 418 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
NYX 0:85b3fd62ea1a 419
NYX 0:85b3fd62ea1a 420
NYX 0:85b3fd62ea1a 421 /**
NYX 0:85b3fd62ea1a 422 \brief Disable FIQ
NYX 0:85b3fd62ea1a 423 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
NYX 0:85b3fd62ea1a 424 Can only be executed in Privileged modes.
NYX 0:85b3fd62ea1a 425 */
NYX 0:85b3fd62ea1a 426 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428
NYX 0:85b3fd62ea1a 429 /**
NYX 0:85b3fd62ea1a 430 \brief Get Base Priority
NYX 0:85b3fd62ea1a 431 \details Returns the current value of the Base Priority register.
NYX 0:85b3fd62ea1a 432 \return Base Priority register value
NYX 0:85b3fd62ea1a 433 */
NYX 0:85b3fd62ea1a 434 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
NYX 0:85b3fd62ea1a 435 {
NYX 0:85b3fd62ea1a 436 uint32_t result;
NYX 0:85b3fd62ea1a 437
NYX 0:85b3fd62ea1a 438 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
NYX 0:85b3fd62ea1a 439 return(result);
NYX 0:85b3fd62ea1a 440 }
NYX 0:85b3fd62ea1a 441
NYX 0:85b3fd62ea1a 442
NYX 0:85b3fd62ea1a 443 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 444 /**
NYX 0:85b3fd62ea1a 445 \brief Get Base Priority (non-secure)
NYX 0:85b3fd62ea1a 446 \details Returns the current value of the non-secure Base Priority register when in secure state.
NYX 0:85b3fd62ea1a 447 \return Base Priority register value
NYX 0:85b3fd62ea1a 448 */
NYX 0:85b3fd62ea1a 449 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
NYX 0:85b3fd62ea1a 450 {
NYX 0:85b3fd62ea1a 451 uint32_t result;
NYX 0:85b3fd62ea1a 452
NYX 0:85b3fd62ea1a 453 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
NYX 0:85b3fd62ea1a 454 return(result);
NYX 0:85b3fd62ea1a 455 }
NYX 0:85b3fd62ea1a 456 #endif
NYX 0:85b3fd62ea1a 457
NYX 0:85b3fd62ea1a 458
NYX 0:85b3fd62ea1a 459 /**
NYX 0:85b3fd62ea1a 460 \brief Set Base Priority
NYX 0:85b3fd62ea1a 461 \details Assigns the given value to the Base Priority register.
NYX 0:85b3fd62ea1a 462 \param [in] basePri Base Priority value to set
NYX 0:85b3fd62ea1a 463 */
NYX 0:85b3fd62ea1a 464 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
NYX 0:85b3fd62ea1a 465 {
NYX 0:85b3fd62ea1a 466 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
NYX 0:85b3fd62ea1a 467 }
NYX 0:85b3fd62ea1a 468
NYX 0:85b3fd62ea1a 469
NYX 0:85b3fd62ea1a 470 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 471 /**
NYX 0:85b3fd62ea1a 472 \brief Set Base Priority (non-secure)
NYX 0:85b3fd62ea1a 473 \details Assigns the given value to the non-secure Base Priority register when in secure state.
NYX 0:85b3fd62ea1a 474 \param [in] basePri Base Priority value to set
NYX 0:85b3fd62ea1a 475 */
NYX 0:85b3fd62ea1a 476 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
NYX 0:85b3fd62ea1a 477 {
NYX 0:85b3fd62ea1a 478 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
NYX 0:85b3fd62ea1a 479 }
NYX 0:85b3fd62ea1a 480 #endif
NYX 0:85b3fd62ea1a 481
NYX 0:85b3fd62ea1a 482
NYX 0:85b3fd62ea1a 483 /**
NYX 0:85b3fd62ea1a 484 \brief Set Base Priority with condition
NYX 0:85b3fd62ea1a 485 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
NYX 0:85b3fd62ea1a 486 or the new value increases the BASEPRI priority level.
NYX 0:85b3fd62ea1a 487 \param [in] basePri Base Priority value to set
NYX 0:85b3fd62ea1a 488 */
NYX 0:85b3fd62ea1a 489 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
NYX 0:85b3fd62ea1a 490 {
NYX 0:85b3fd62ea1a 491 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
NYX 0:85b3fd62ea1a 492 }
NYX 0:85b3fd62ea1a 493
NYX 0:85b3fd62ea1a 494
NYX 0:85b3fd62ea1a 495 /**
NYX 0:85b3fd62ea1a 496 \brief Get Fault Mask
NYX 0:85b3fd62ea1a 497 \details Returns the current value of the Fault Mask register.
NYX 0:85b3fd62ea1a 498 \return Fault Mask register value
NYX 0:85b3fd62ea1a 499 */
NYX 0:85b3fd62ea1a 500 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
NYX 0:85b3fd62ea1a 501 {
NYX 0:85b3fd62ea1a 502 uint32_t result;
NYX 0:85b3fd62ea1a 503
NYX 0:85b3fd62ea1a 504 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
NYX 0:85b3fd62ea1a 505 return(result);
NYX 0:85b3fd62ea1a 506 }
NYX 0:85b3fd62ea1a 507
NYX 0:85b3fd62ea1a 508
NYX 0:85b3fd62ea1a 509 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 510 /**
NYX 0:85b3fd62ea1a 511 \brief Get Fault Mask (non-secure)
NYX 0:85b3fd62ea1a 512 \details Returns the current value of the non-secure Fault Mask register when in secure state.
NYX 0:85b3fd62ea1a 513 \return Fault Mask register value
NYX 0:85b3fd62ea1a 514 */
NYX 0:85b3fd62ea1a 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
NYX 0:85b3fd62ea1a 516 {
NYX 0:85b3fd62ea1a 517 uint32_t result;
NYX 0:85b3fd62ea1a 518
NYX 0:85b3fd62ea1a 519 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
NYX 0:85b3fd62ea1a 520 return(result);
NYX 0:85b3fd62ea1a 521 }
NYX 0:85b3fd62ea1a 522 #endif
NYX 0:85b3fd62ea1a 523
NYX 0:85b3fd62ea1a 524
NYX 0:85b3fd62ea1a 525 /**
NYX 0:85b3fd62ea1a 526 \brief Set Fault Mask
NYX 0:85b3fd62ea1a 527 \details Assigns the given value to the Fault Mask register.
NYX 0:85b3fd62ea1a 528 \param [in] faultMask Fault Mask value to set
NYX 0:85b3fd62ea1a 529 */
NYX 0:85b3fd62ea1a 530 __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
NYX 0:85b3fd62ea1a 531 {
NYX 0:85b3fd62ea1a 532 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
NYX 0:85b3fd62ea1a 533 }
NYX 0:85b3fd62ea1a 534
NYX 0:85b3fd62ea1a 535
NYX 0:85b3fd62ea1a 536 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
NYX 0:85b3fd62ea1a 537 /**
NYX 0:85b3fd62ea1a 538 \brief Set Fault Mask (non-secure)
NYX 0:85b3fd62ea1a 539 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
NYX 0:85b3fd62ea1a 540 \param [in] faultMask Fault Mask value to set
NYX 0:85b3fd62ea1a 541 */
NYX 0:85b3fd62ea1a 542 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
NYX 0:85b3fd62ea1a 543 {
NYX 0:85b3fd62ea1a 544 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
NYX 0:85b3fd62ea1a 545 }
NYX 0:85b3fd62ea1a 546 #endif
NYX 0:85b3fd62ea1a 547
NYX 0:85b3fd62ea1a 548 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
NYX 0:85b3fd62ea1a 549 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
NYX 0:85b3fd62ea1a 550 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
NYX 0:85b3fd62ea1a 551
NYX 0:85b3fd62ea1a 552
NYX 0:85b3fd62ea1a 553 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
NYX 0:85b3fd62ea1a 554 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
NYX 0:85b3fd62ea1a 555
NYX 0:85b3fd62ea1a 556 /**
NYX 0:85b3fd62ea1a 557 \brief Get Process Stack Pointer Limit
NYX 0:85b3fd62ea1a 558 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
NYX 0:85b3fd62ea1a 559 \return PSPLIM Register value
NYX 0:85b3fd62ea1a 560 */
NYX 0:85b3fd62ea1a 561 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
NYX 0:85b3fd62ea1a 562 {
NYX 0:85b3fd62ea1a 563 register uint32_t result;
NYX 0:85b3fd62ea1a 564
NYX 0:85b3fd62ea1a 565 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
NYX 0:85b3fd62ea1a 566 return(result);
NYX 0:85b3fd62ea1a 567 }
NYX 0:85b3fd62ea1a 568
NYX 0:85b3fd62ea1a 569
NYX 0:85b3fd62ea1a 570 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
NYX 0:85b3fd62ea1a 571 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
NYX 0:85b3fd62ea1a 572 /**
NYX 0:85b3fd62ea1a 573 \brief Get Process Stack Pointer Limit (non-secure)
NYX 0:85b3fd62ea1a 574 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
NYX 0:85b3fd62ea1a 575 \return PSPLIM Register value
NYX 0:85b3fd62ea1a 576 */
NYX 0:85b3fd62ea1a 577 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
NYX 0:85b3fd62ea1a 578 {
NYX 0:85b3fd62ea1a 579 register uint32_t result;
NYX 0:85b3fd62ea1a 580
NYX 0:85b3fd62ea1a 581 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
NYX 0:85b3fd62ea1a 582 return(result);
NYX 0:85b3fd62ea1a 583 }
NYX 0:85b3fd62ea1a 584 #endif
NYX 0:85b3fd62ea1a 585
NYX 0:85b3fd62ea1a 586
NYX 0:85b3fd62ea1a 587 /**
NYX 0:85b3fd62ea1a 588 \brief Set Process Stack Pointer Limit
NYX 0:85b3fd62ea1a 589 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
NYX 0:85b3fd62ea1a 590 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
NYX 0:85b3fd62ea1a 591 */
NYX 0:85b3fd62ea1a 592 __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
NYX 0:85b3fd62ea1a 593 {
NYX 0:85b3fd62ea1a 594 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
NYX 0:85b3fd62ea1a 595 }
NYX 0:85b3fd62ea1a 596
NYX 0:85b3fd62ea1a 597
NYX 0:85b3fd62ea1a 598 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
NYX 0:85b3fd62ea1a 599 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
NYX 0:85b3fd62ea1a 600 /**
NYX 0:85b3fd62ea1a 601 \brief Set Process Stack Pointer (non-secure)
NYX 0:85b3fd62ea1a 602 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
NYX 0:85b3fd62ea1a 603 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
NYX 0:85b3fd62ea1a 604 */
NYX 0:85b3fd62ea1a 605 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
NYX 0:85b3fd62ea1a 606 {
NYX 0:85b3fd62ea1a 607 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
NYX 0:85b3fd62ea1a 608 }
NYX 0:85b3fd62ea1a 609 #endif
NYX 0:85b3fd62ea1a 610
NYX 0:85b3fd62ea1a 611
NYX 0:85b3fd62ea1a 612 /**
NYX 0:85b3fd62ea1a 613 \brief Get Main Stack Pointer Limit
NYX 0:85b3fd62ea1a 614 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
NYX 0:85b3fd62ea1a 615 \return MSPLIM Register value
NYX 0:85b3fd62ea1a 616 */
NYX 0:85b3fd62ea1a 617 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
NYX 0:85b3fd62ea1a 618 {
NYX 0:85b3fd62ea1a 619 register uint32_t result;
NYX 0:85b3fd62ea1a 620
NYX 0:85b3fd62ea1a 621 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
NYX 0:85b3fd62ea1a 622
NYX 0:85b3fd62ea1a 623 return(result);
NYX 0:85b3fd62ea1a 624 }
NYX 0:85b3fd62ea1a 625
NYX 0:85b3fd62ea1a 626
NYX 0:85b3fd62ea1a 627 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
NYX 0:85b3fd62ea1a 628 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
NYX 0:85b3fd62ea1a 629 /**
NYX 0:85b3fd62ea1a 630 \brief Get Main Stack Pointer Limit (non-secure)
NYX 0:85b3fd62ea1a 631 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
NYX 0:85b3fd62ea1a 632 \return MSPLIM Register value
NYX 0:85b3fd62ea1a 633 */
NYX 0:85b3fd62ea1a 634 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
NYX 0:85b3fd62ea1a 635 {
NYX 0:85b3fd62ea1a 636 register uint32_t result;
NYX 0:85b3fd62ea1a 637
NYX 0:85b3fd62ea1a 638 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
NYX 0:85b3fd62ea1a 639 return(result);
NYX 0:85b3fd62ea1a 640 }
NYX 0:85b3fd62ea1a 641 #endif
NYX 0:85b3fd62ea1a 642
NYX 0:85b3fd62ea1a 643
NYX 0:85b3fd62ea1a 644 /**
NYX 0:85b3fd62ea1a 645 \brief Set Main Stack Pointer Limit
NYX 0:85b3fd62ea1a 646 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
NYX 0:85b3fd62ea1a 647 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
NYX 0:85b3fd62ea1a 648 */
NYX 0:85b3fd62ea1a 649 __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
NYX 0:85b3fd62ea1a 650 {
NYX 0:85b3fd62ea1a 651 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
NYX 0:85b3fd62ea1a 652 }
NYX 0:85b3fd62ea1a 653
NYX 0:85b3fd62ea1a 654
NYX 0:85b3fd62ea1a 655 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
NYX 0:85b3fd62ea1a 656 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
NYX 0:85b3fd62ea1a 657 /**
NYX 0:85b3fd62ea1a 658 \brief Set Main Stack Pointer Limit (non-secure)
NYX 0:85b3fd62ea1a 659 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
NYX 0:85b3fd62ea1a 660 \param [in] MainStackPtrLimit Main Stack Pointer value to set
NYX 0:85b3fd62ea1a 661 */
NYX 0:85b3fd62ea1a 662 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
NYX 0:85b3fd62ea1a 663 {
NYX 0:85b3fd62ea1a 664 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
NYX 0:85b3fd62ea1a 665 }
NYX 0:85b3fd62ea1a 666 #endif
NYX 0:85b3fd62ea1a 667
NYX 0:85b3fd62ea1a 668 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
NYX 0:85b3fd62ea1a 669 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
NYX 0:85b3fd62ea1a 670
NYX 0:85b3fd62ea1a 671
NYX 0:85b3fd62ea1a 672 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
NYX 0:85b3fd62ea1a 673 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
NYX 0:85b3fd62ea1a 674
NYX 0:85b3fd62ea1a 675 /**
NYX 0:85b3fd62ea1a 676 \brief Get FPSCR
NYX 0:85b3fd62ea1a 677 \details Returns the current value of the Floating Point Status/Control register.
NYX 0:85b3fd62ea1a 678 \return Floating Point Status/Control register value
NYX 0:85b3fd62ea1a 679 */
NYX 0:85b3fd62ea1a 680 /* #define __get_FPSCR __builtin_arm_get_fpscr */
NYX 0:85b3fd62ea1a 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
NYX 0:85b3fd62ea1a 682 {
NYX 0:85b3fd62ea1a 683 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
NYX 0:85b3fd62ea1a 684 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
NYX 0:85b3fd62ea1a 685 uint32_t result;
NYX 0:85b3fd62ea1a 686
NYX 0:85b3fd62ea1a 687 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
NYX 0:85b3fd62ea1a 688 return(result);
NYX 0:85b3fd62ea1a 689 #else
NYX 0:85b3fd62ea1a 690 return(0U);
NYX 0:85b3fd62ea1a 691 #endif
NYX 0:85b3fd62ea1a 692 }
NYX 0:85b3fd62ea1a 693
NYX 0:85b3fd62ea1a 694
NYX 0:85b3fd62ea1a 695 /**
NYX 0:85b3fd62ea1a 696 \brief Set FPSCR
NYX 0:85b3fd62ea1a 697 \details Assigns the given value to the Floating Point Status/Control register.
NYX 0:85b3fd62ea1a 698 \param [in] fpscr Floating Point Status/Control value to set
NYX 0:85b3fd62ea1a 699 */
NYX 0:85b3fd62ea1a 700 /* #define __set_FPSCR __builtin_arm_set_fpscr */
NYX 0:85b3fd62ea1a 701 __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
NYX 0:85b3fd62ea1a 702 {
NYX 0:85b3fd62ea1a 703 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
NYX 0:85b3fd62ea1a 704 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
NYX 0:85b3fd62ea1a 705 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
NYX 0:85b3fd62ea1a 706 #else
NYX 0:85b3fd62ea1a 707 (void)fpscr;
NYX 0:85b3fd62ea1a 708 #endif
NYX 0:85b3fd62ea1a 709 }
NYX 0:85b3fd62ea1a 710
NYX 0:85b3fd62ea1a 711 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
NYX 0:85b3fd62ea1a 712 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
NYX 0:85b3fd62ea1a 713
NYX 0:85b3fd62ea1a 714
NYX 0:85b3fd62ea1a 715
NYX 0:85b3fd62ea1a 716 /*@} end of CMSIS_Core_RegAccFunctions */
NYX 0:85b3fd62ea1a 717
NYX 0:85b3fd62ea1a 718
NYX 0:85b3fd62ea1a 719 /* ########################## Core Instruction Access ######################### */
NYX 0:85b3fd62ea1a 720 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
NYX 0:85b3fd62ea1a 721 Access to dedicated instructions
NYX 0:85b3fd62ea1a 722 @{
NYX 0:85b3fd62ea1a 723 */
NYX 0:85b3fd62ea1a 724
NYX 0:85b3fd62ea1a 725 /* Define macros for porting to both thumb1 and thumb2.
NYX 0:85b3fd62ea1a 726 * For thumb1, use low register (r0-r7), specified by constraint "l"
NYX 0:85b3fd62ea1a 727 * Otherwise, use general registers, specified by constraint "r" */
NYX 0:85b3fd62ea1a 728 #if defined (__thumb__) && !defined (__thumb2__)
NYX 0:85b3fd62ea1a 729 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
NYX 0:85b3fd62ea1a 730 #define __CMSIS_GCC_USE_REG(r) "l" (r)
NYX 0:85b3fd62ea1a 731 #else
NYX 0:85b3fd62ea1a 732 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
NYX 0:85b3fd62ea1a 733 #define __CMSIS_GCC_USE_REG(r) "r" (r)
NYX 0:85b3fd62ea1a 734 #endif
NYX 0:85b3fd62ea1a 735
NYX 0:85b3fd62ea1a 736 /**
NYX 0:85b3fd62ea1a 737 \brief No Operation
NYX 0:85b3fd62ea1a 738 \details No Operation does nothing. This instruction can be used for code alignment purposes.
NYX 0:85b3fd62ea1a 739 */
NYX 0:85b3fd62ea1a 740 #define __NOP __builtin_arm_nop
NYX 0:85b3fd62ea1a 741
NYX 0:85b3fd62ea1a 742 /**
NYX 0:85b3fd62ea1a 743 \brief Wait For Interrupt
NYX 0:85b3fd62ea1a 744 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
NYX 0:85b3fd62ea1a 745 */
NYX 0:85b3fd62ea1a 746 #define __WFI __builtin_arm_wfi
NYX 0:85b3fd62ea1a 747
NYX 0:85b3fd62ea1a 748
NYX 0:85b3fd62ea1a 749 /**
NYX 0:85b3fd62ea1a 750 \brief Wait For Event
NYX 0:85b3fd62ea1a 751 \details Wait For Event is a hint instruction that permits the processor to enter
NYX 0:85b3fd62ea1a 752 a low-power state until one of a number of events occurs.
NYX 0:85b3fd62ea1a 753 */
NYX 0:85b3fd62ea1a 754 #define __WFE __builtin_arm_wfe
NYX 0:85b3fd62ea1a 755
NYX 0:85b3fd62ea1a 756
NYX 0:85b3fd62ea1a 757 /**
NYX 0:85b3fd62ea1a 758 \brief Send Event
NYX 0:85b3fd62ea1a 759 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
NYX 0:85b3fd62ea1a 760 */
NYX 0:85b3fd62ea1a 761 #define __SEV __builtin_arm_sev
NYX 0:85b3fd62ea1a 762
NYX 0:85b3fd62ea1a 763
NYX 0:85b3fd62ea1a 764 /**
NYX 0:85b3fd62ea1a 765 \brief Instruction Synchronization Barrier
NYX 0:85b3fd62ea1a 766 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
NYX 0:85b3fd62ea1a 767 so that all instructions following the ISB are fetched from cache or memory,
NYX 0:85b3fd62ea1a 768 after the instruction has been completed.
NYX 0:85b3fd62ea1a 769 */
NYX 0:85b3fd62ea1a 770 #define __ISB() __builtin_arm_isb(0xF);
NYX 0:85b3fd62ea1a 771
NYX 0:85b3fd62ea1a 772 /**
NYX 0:85b3fd62ea1a 773 \brief Data Synchronization Barrier
NYX 0:85b3fd62ea1a 774 \details Acts as a special kind of Data Memory Barrier.
NYX 0:85b3fd62ea1a 775 It completes when all explicit memory accesses before this instruction complete.
NYX 0:85b3fd62ea1a 776 */
NYX 0:85b3fd62ea1a 777 #define __DSB() __builtin_arm_dsb(0xF);
NYX 0:85b3fd62ea1a 778
NYX 0:85b3fd62ea1a 779
NYX 0:85b3fd62ea1a 780 /**
NYX 0:85b3fd62ea1a 781 \brief Data Memory Barrier
NYX 0:85b3fd62ea1a 782 \details Ensures the apparent order of the explicit memory operations before
NYX 0:85b3fd62ea1a 783 and after the instruction, without ensuring their completion.
NYX 0:85b3fd62ea1a 784 */
NYX 0:85b3fd62ea1a 785 #define __DMB() __builtin_arm_dmb(0xF);
NYX 0:85b3fd62ea1a 786
NYX 0:85b3fd62ea1a 787
NYX 0:85b3fd62ea1a 788 /**
NYX 0:85b3fd62ea1a 789 \brief Reverse byte order (32 bit)
NYX 0:85b3fd62ea1a 790 \details Reverses the byte order in integer value.
NYX 0:85b3fd62ea1a 791 \param [in] value Value to reverse
NYX 0:85b3fd62ea1a 792 \return Reversed value
NYX 0:85b3fd62ea1a 793 */
NYX 0:85b3fd62ea1a 794 #define __REV __builtin_bswap32
NYX 0:85b3fd62ea1a 795
NYX 0:85b3fd62ea1a 796
NYX 0:85b3fd62ea1a 797 /**
NYX 0:85b3fd62ea1a 798 \brief Reverse byte order (16 bit)
NYX 0:85b3fd62ea1a 799 \details Reverses the byte order in two unsigned short values.
NYX 0:85b3fd62ea1a 800 \param [in] value Value to reverse
NYX 0:85b3fd62ea1a 801 \return Reversed value
NYX 0:85b3fd62ea1a 802 */
NYX 0:85b3fd62ea1a 803 #define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
NYX 0:85b3fd62ea1a 804 #if 0
NYX 0:85b3fd62ea1a 805 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
NYX 0:85b3fd62ea1a 806 {
NYX 0:85b3fd62ea1a 807 uint32_t result;
NYX 0:85b3fd62ea1a 808
NYX 0:85b3fd62ea1a 809 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
NYX 0:85b3fd62ea1a 810 return(result);
NYX 0:85b3fd62ea1a 811 }
NYX 0:85b3fd62ea1a 812 #endif
NYX 0:85b3fd62ea1a 813
NYX 0:85b3fd62ea1a 814
NYX 0:85b3fd62ea1a 815 /**
NYX 0:85b3fd62ea1a 816 \brief Reverse byte order in signed short value
NYX 0:85b3fd62ea1a 817 \details Reverses the byte order in a signed short value with sign extension to integer.
NYX 0:85b3fd62ea1a 818 \param [in] value Value to reverse
NYX 0:85b3fd62ea1a 819 \return Reversed value
NYX 0:85b3fd62ea1a 820 */
NYX 0:85b3fd62ea1a 821 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
NYX 0:85b3fd62ea1a 822 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
NYX 0:85b3fd62ea1a 823 {
NYX 0:85b3fd62ea1a 824 int32_t result;
NYX 0:85b3fd62ea1a 825
NYX 0:85b3fd62ea1a 826 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
NYX 0:85b3fd62ea1a 827 return(result);
NYX 0:85b3fd62ea1a 828 }
NYX 0:85b3fd62ea1a 829
NYX 0:85b3fd62ea1a 830
NYX 0:85b3fd62ea1a 831 /**
NYX 0:85b3fd62ea1a 832 \brief Rotate Right in unsigned value (32 bit)
NYX 0:85b3fd62ea1a 833 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
NYX 0:85b3fd62ea1a 834 \param [in] op1 Value to rotate
NYX 0:85b3fd62ea1a 835 \param [in] op2 Number of Bits to rotate
NYX 0:85b3fd62ea1a 836 \return Rotated value
NYX 0:85b3fd62ea1a 837 */
NYX 0:85b3fd62ea1a 838 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 839 {
NYX 0:85b3fd62ea1a 840 return (op1 >> op2) | (op1 << (32U - op2));
NYX 0:85b3fd62ea1a 841 }
NYX 0:85b3fd62ea1a 842
NYX 0:85b3fd62ea1a 843
NYX 0:85b3fd62ea1a 844 /**
NYX 0:85b3fd62ea1a 845 \brief Breakpoint
NYX 0:85b3fd62ea1a 846 \details Causes the processor to enter Debug state.
NYX 0:85b3fd62ea1a 847 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
NYX 0:85b3fd62ea1a 848 \param [in] value is ignored by the processor.
NYX 0:85b3fd62ea1a 849 If required, a debugger can use it to store additional information about the breakpoint.
NYX 0:85b3fd62ea1a 850 */
NYX 0:85b3fd62ea1a 851 #define __BKPT(value) __ASM volatile ("bkpt "#value)
NYX 0:85b3fd62ea1a 852
NYX 0:85b3fd62ea1a 853
NYX 0:85b3fd62ea1a 854 /**
NYX 0:85b3fd62ea1a 855 \brief Reverse bit order of value
NYX 0:85b3fd62ea1a 856 \details Reverses the bit order of the given value.
NYX 0:85b3fd62ea1a 857 \param [in] value Value to reverse
NYX 0:85b3fd62ea1a 858 \return Reversed value
NYX 0:85b3fd62ea1a 859 */
NYX 0:85b3fd62ea1a 860 /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
NYX 0:85b3fd62ea1a 861 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
NYX 0:85b3fd62ea1a 862 {
NYX 0:85b3fd62ea1a 863 uint32_t result;
NYX 0:85b3fd62ea1a 864
NYX 0:85b3fd62ea1a 865 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
NYX 0:85b3fd62ea1a 866 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
NYX 0:85b3fd62ea1a 867 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
NYX 0:85b3fd62ea1a 868 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
NYX 0:85b3fd62ea1a 869 #else
NYX 0:85b3fd62ea1a 870 int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
NYX 0:85b3fd62ea1a 871
NYX 0:85b3fd62ea1a 872 result = value; /* r will be reversed bits of v; first get LSB of v */
NYX 0:85b3fd62ea1a 873 for (value >>= 1U; value; value >>= 1U)
NYX 0:85b3fd62ea1a 874 {
NYX 0:85b3fd62ea1a 875 result <<= 1U;
NYX 0:85b3fd62ea1a 876 result |= value & 1U;
NYX 0:85b3fd62ea1a 877 s--;
NYX 0:85b3fd62ea1a 878 }
NYX 0:85b3fd62ea1a 879 result <<= s; /* shift when v's highest bits are zero */
NYX 0:85b3fd62ea1a 880 #endif
NYX 0:85b3fd62ea1a 881 return(result);
NYX 0:85b3fd62ea1a 882 }
NYX 0:85b3fd62ea1a 883
NYX 0:85b3fd62ea1a 884
NYX 0:85b3fd62ea1a 885 /**
NYX 0:85b3fd62ea1a 886 \brief Count leading zeros
NYX 0:85b3fd62ea1a 887 \details Counts the number of leading zeros of a data value.
NYX 0:85b3fd62ea1a 888 \param [in] value Value to count the leading zeros
NYX 0:85b3fd62ea1a 889 \return number of leading zeros in value
NYX 0:85b3fd62ea1a 890 */
NYX 0:85b3fd62ea1a 891 #define __CLZ __builtin_clz
NYX 0:85b3fd62ea1a 892
NYX 0:85b3fd62ea1a 893
NYX 0:85b3fd62ea1a 894 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
NYX 0:85b3fd62ea1a 895 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
NYX 0:85b3fd62ea1a 896 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
NYX 0:85b3fd62ea1a 897 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
NYX 0:85b3fd62ea1a 898 /**
NYX 0:85b3fd62ea1a 899 \brief LDR Exclusive (8 bit)
NYX 0:85b3fd62ea1a 900 \details Executes a exclusive LDR instruction for 8 bit value.
NYX 0:85b3fd62ea1a 901 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 902 \return value of type uint8_t at (*ptr)
NYX 0:85b3fd62ea1a 903 */
NYX 0:85b3fd62ea1a 904 #define __LDREXB (uint8_t)__builtin_arm_ldrex
NYX 0:85b3fd62ea1a 905
NYX 0:85b3fd62ea1a 906
NYX 0:85b3fd62ea1a 907 /**
NYX 0:85b3fd62ea1a 908 \brief LDR Exclusive (16 bit)
NYX 0:85b3fd62ea1a 909 \details Executes a exclusive LDR instruction for 16 bit values.
NYX 0:85b3fd62ea1a 910 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 911 \return value of type uint16_t at (*ptr)
NYX 0:85b3fd62ea1a 912 */
NYX 0:85b3fd62ea1a 913 #define __LDREXH (uint16_t)__builtin_arm_ldrex
NYX 0:85b3fd62ea1a 914
NYX 0:85b3fd62ea1a 915
NYX 0:85b3fd62ea1a 916 /**
NYX 0:85b3fd62ea1a 917 \brief LDR Exclusive (32 bit)
NYX 0:85b3fd62ea1a 918 \details Executes a exclusive LDR instruction for 32 bit values.
NYX 0:85b3fd62ea1a 919 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 920 \return value of type uint32_t at (*ptr)
NYX 0:85b3fd62ea1a 921 */
NYX 0:85b3fd62ea1a 922 #define __LDREXW (uint32_t)__builtin_arm_ldrex
NYX 0:85b3fd62ea1a 923
NYX 0:85b3fd62ea1a 924
NYX 0:85b3fd62ea1a 925 /**
NYX 0:85b3fd62ea1a 926 \brief STR Exclusive (8 bit)
NYX 0:85b3fd62ea1a 927 \details Executes a exclusive STR instruction for 8 bit values.
NYX 0:85b3fd62ea1a 928 \param [in] value Value to store
NYX 0:85b3fd62ea1a 929 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 930 \return 0 Function succeeded
NYX 0:85b3fd62ea1a 931 \return 1 Function failed
NYX 0:85b3fd62ea1a 932 */
NYX 0:85b3fd62ea1a 933 #define __STREXB (uint32_t)__builtin_arm_strex
NYX 0:85b3fd62ea1a 934
NYX 0:85b3fd62ea1a 935
NYX 0:85b3fd62ea1a 936 /**
NYX 0:85b3fd62ea1a 937 \brief STR Exclusive (16 bit)
NYX 0:85b3fd62ea1a 938 \details Executes a exclusive STR instruction for 16 bit values.
NYX 0:85b3fd62ea1a 939 \param [in] value Value to store
NYX 0:85b3fd62ea1a 940 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 941 \return 0 Function succeeded
NYX 0:85b3fd62ea1a 942 \return 1 Function failed
NYX 0:85b3fd62ea1a 943 */
NYX 0:85b3fd62ea1a 944 #define __STREXH (uint32_t)__builtin_arm_strex
NYX 0:85b3fd62ea1a 945
NYX 0:85b3fd62ea1a 946
NYX 0:85b3fd62ea1a 947 /**
NYX 0:85b3fd62ea1a 948 \brief STR Exclusive (32 bit)
NYX 0:85b3fd62ea1a 949 \details Executes a exclusive STR instruction for 32 bit values.
NYX 0:85b3fd62ea1a 950 \param [in] value Value to store
NYX 0:85b3fd62ea1a 951 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 952 \return 0 Function succeeded
NYX 0:85b3fd62ea1a 953 \return 1 Function failed
NYX 0:85b3fd62ea1a 954 */
NYX 0:85b3fd62ea1a 955 #define __STREXW (uint32_t)__builtin_arm_strex
NYX 0:85b3fd62ea1a 956
NYX 0:85b3fd62ea1a 957
NYX 0:85b3fd62ea1a 958 /**
NYX 0:85b3fd62ea1a 959 \brief Remove the exclusive lock
NYX 0:85b3fd62ea1a 960 \details Removes the exclusive lock which is created by LDREX.
NYX 0:85b3fd62ea1a 961 */
NYX 0:85b3fd62ea1a 962 #define __CLREX __builtin_arm_clrex
NYX 0:85b3fd62ea1a 963
NYX 0:85b3fd62ea1a 964 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
NYX 0:85b3fd62ea1a 965 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
NYX 0:85b3fd62ea1a 966 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
NYX 0:85b3fd62ea1a 967 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
NYX 0:85b3fd62ea1a 968
NYX 0:85b3fd62ea1a 969
NYX 0:85b3fd62ea1a 970 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
NYX 0:85b3fd62ea1a 971 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
NYX 0:85b3fd62ea1a 972 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
NYX 0:85b3fd62ea1a 973 /**
NYX 0:85b3fd62ea1a 974 \brief Signed Saturate
NYX 0:85b3fd62ea1a 975 \details Saturates a signed value.
NYX 0:85b3fd62ea1a 976 \param [in] value Value to be saturated
NYX 0:85b3fd62ea1a 977 \param [in] sat Bit position to saturate to (1..32)
NYX 0:85b3fd62ea1a 978 \return Saturated value
NYX 0:85b3fd62ea1a 979 */
NYX 0:85b3fd62ea1a 980 #define __SSAT __builtin_arm_ssat
NYX 0:85b3fd62ea1a 981
NYX 0:85b3fd62ea1a 982
NYX 0:85b3fd62ea1a 983 /**
NYX 0:85b3fd62ea1a 984 \brief Unsigned Saturate
NYX 0:85b3fd62ea1a 985 \details Saturates an unsigned value.
NYX 0:85b3fd62ea1a 986 \param [in] value Value to be saturated
NYX 0:85b3fd62ea1a 987 \param [in] sat Bit position to saturate to (0..31)
NYX 0:85b3fd62ea1a 988 \return Saturated value
NYX 0:85b3fd62ea1a 989 */
NYX 0:85b3fd62ea1a 990 #define __USAT __builtin_arm_usat
NYX 0:85b3fd62ea1a 991
NYX 0:85b3fd62ea1a 992
NYX 0:85b3fd62ea1a 993 /**
NYX 0:85b3fd62ea1a 994 \brief Rotate Right with Extend (32 bit)
NYX 0:85b3fd62ea1a 995 \details Moves each bit of a bitstring right by one bit.
NYX 0:85b3fd62ea1a 996 The carry input is shifted in at the left end of the bitstring.
NYX 0:85b3fd62ea1a 997 \param [in] value Value to rotate
NYX 0:85b3fd62ea1a 998 \return Rotated value
NYX 0:85b3fd62ea1a 999 */
NYX 0:85b3fd62ea1a 1000 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
NYX 0:85b3fd62ea1a 1001 {
NYX 0:85b3fd62ea1a 1002 uint32_t result;
NYX 0:85b3fd62ea1a 1003
NYX 0:85b3fd62ea1a 1004 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
NYX 0:85b3fd62ea1a 1005 return(result);
NYX 0:85b3fd62ea1a 1006 }
NYX 0:85b3fd62ea1a 1007
NYX 0:85b3fd62ea1a 1008
NYX 0:85b3fd62ea1a 1009 /**
NYX 0:85b3fd62ea1a 1010 \brief LDRT Unprivileged (8 bit)
NYX 0:85b3fd62ea1a 1011 \details Executes a Unprivileged LDRT instruction for 8 bit value.
NYX 0:85b3fd62ea1a 1012 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 1013 \return value of type uint8_t at (*ptr)
NYX 0:85b3fd62ea1a 1014 */
NYX 0:85b3fd62ea1a 1015 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
NYX 0:85b3fd62ea1a 1016 {
NYX 0:85b3fd62ea1a 1017 uint32_t result;
NYX 0:85b3fd62ea1a 1018
NYX 0:85b3fd62ea1a 1019 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
NYX 0:85b3fd62ea1a 1020 return ((uint8_t) result); /* Add explicit type cast here */
NYX 0:85b3fd62ea1a 1021 }
NYX 0:85b3fd62ea1a 1022
NYX 0:85b3fd62ea1a 1023
NYX 0:85b3fd62ea1a 1024 /**
NYX 0:85b3fd62ea1a 1025 \brief LDRT Unprivileged (16 bit)
NYX 0:85b3fd62ea1a 1026 \details Executes a Unprivileged LDRT instruction for 16 bit values.
NYX 0:85b3fd62ea1a 1027 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 1028 \return value of type uint16_t at (*ptr)
NYX 0:85b3fd62ea1a 1029 */
NYX 0:85b3fd62ea1a 1030 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
NYX 0:85b3fd62ea1a 1031 {
NYX 0:85b3fd62ea1a 1032 uint32_t result;
NYX 0:85b3fd62ea1a 1033
NYX 0:85b3fd62ea1a 1034 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
NYX 0:85b3fd62ea1a 1035 return ((uint16_t) result); /* Add explicit type cast here */
NYX 0:85b3fd62ea1a 1036 }
NYX 0:85b3fd62ea1a 1037
NYX 0:85b3fd62ea1a 1038
NYX 0:85b3fd62ea1a 1039 /**
NYX 0:85b3fd62ea1a 1040 \brief LDRT Unprivileged (32 bit)
NYX 0:85b3fd62ea1a 1041 \details Executes a Unprivileged LDRT instruction for 32 bit values.
NYX 0:85b3fd62ea1a 1042 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 1043 \return value of type uint32_t at (*ptr)
NYX 0:85b3fd62ea1a 1044 */
NYX 0:85b3fd62ea1a 1045 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
NYX 0:85b3fd62ea1a 1046 {
NYX 0:85b3fd62ea1a 1047 uint32_t result;
NYX 0:85b3fd62ea1a 1048
NYX 0:85b3fd62ea1a 1049 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
NYX 0:85b3fd62ea1a 1050 return(result);
NYX 0:85b3fd62ea1a 1051 }
NYX 0:85b3fd62ea1a 1052
NYX 0:85b3fd62ea1a 1053
NYX 0:85b3fd62ea1a 1054 /**
NYX 0:85b3fd62ea1a 1055 \brief STRT Unprivileged (8 bit)
NYX 0:85b3fd62ea1a 1056 \details Executes a Unprivileged STRT instruction for 8 bit values.
NYX 0:85b3fd62ea1a 1057 \param [in] value Value to store
NYX 0:85b3fd62ea1a 1058 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 1059 */
NYX 0:85b3fd62ea1a 1060 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
NYX 0:85b3fd62ea1a 1061 {
NYX 0:85b3fd62ea1a 1062 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
NYX 0:85b3fd62ea1a 1063 }
NYX 0:85b3fd62ea1a 1064
NYX 0:85b3fd62ea1a 1065
NYX 0:85b3fd62ea1a 1066 /**
NYX 0:85b3fd62ea1a 1067 \brief STRT Unprivileged (16 bit)
NYX 0:85b3fd62ea1a 1068 \details Executes a Unprivileged STRT instruction for 16 bit values.
NYX 0:85b3fd62ea1a 1069 \param [in] value Value to store
NYX 0:85b3fd62ea1a 1070 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 1071 */
NYX 0:85b3fd62ea1a 1072 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
NYX 0:85b3fd62ea1a 1073 {
NYX 0:85b3fd62ea1a 1074 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
NYX 0:85b3fd62ea1a 1075 }
NYX 0:85b3fd62ea1a 1076
NYX 0:85b3fd62ea1a 1077
NYX 0:85b3fd62ea1a 1078 /**
NYX 0:85b3fd62ea1a 1079 \brief STRT Unprivileged (32 bit)
NYX 0:85b3fd62ea1a 1080 \details Executes a Unprivileged STRT instruction for 32 bit values.
NYX 0:85b3fd62ea1a 1081 \param [in] value Value to store
NYX 0:85b3fd62ea1a 1082 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 1083 */
NYX 0:85b3fd62ea1a 1084 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
NYX 0:85b3fd62ea1a 1085 {
NYX 0:85b3fd62ea1a 1086 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
NYX 0:85b3fd62ea1a 1087 }
NYX 0:85b3fd62ea1a 1088
NYX 0:85b3fd62ea1a 1089 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
NYX 0:85b3fd62ea1a 1090 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
NYX 0:85b3fd62ea1a 1091 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
NYX 0:85b3fd62ea1a 1092
NYX 0:85b3fd62ea1a 1093
NYX 0:85b3fd62ea1a 1094 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
NYX 0:85b3fd62ea1a 1095 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
NYX 0:85b3fd62ea1a 1096 /**
NYX 0:85b3fd62ea1a 1097 \brief Load-Acquire (8 bit)
NYX 0:85b3fd62ea1a 1098 \details Executes a LDAB instruction for 8 bit value.
NYX 0:85b3fd62ea1a 1099 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 1100 \return value of type uint8_t at (*ptr)
NYX 0:85b3fd62ea1a 1101 */
NYX 0:85b3fd62ea1a 1102 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
NYX 0:85b3fd62ea1a 1103 {
NYX 0:85b3fd62ea1a 1104 uint32_t result;
NYX 0:85b3fd62ea1a 1105
NYX 0:85b3fd62ea1a 1106 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
NYX 0:85b3fd62ea1a 1107 return ((uint8_t) result);
NYX 0:85b3fd62ea1a 1108 }
NYX 0:85b3fd62ea1a 1109
NYX 0:85b3fd62ea1a 1110
NYX 0:85b3fd62ea1a 1111 /**
NYX 0:85b3fd62ea1a 1112 \brief Load-Acquire (16 bit)
NYX 0:85b3fd62ea1a 1113 \details Executes a LDAH instruction for 16 bit values.
NYX 0:85b3fd62ea1a 1114 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 1115 \return value of type uint16_t at (*ptr)
NYX 0:85b3fd62ea1a 1116 */
NYX 0:85b3fd62ea1a 1117 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
NYX 0:85b3fd62ea1a 1118 {
NYX 0:85b3fd62ea1a 1119 uint32_t result;
NYX 0:85b3fd62ea1a 1120
NYX 0:85b3fd62ea1a 1121 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
NYX 0:85b3fd62ea1a 1122 return ((uint16_t) result);
NYX 0:85b3fd62ea1a 1123 }
NYX 0:85b3fd62ea1a 1124
NYX 0:85b3fd62ea1a 1125
NYX 0:85b3fd62ea1a 1126 /**
NYX 0:85b3fd62ea1a 1127 \brief Load-Acquire (32 bit)
NYX 0:85b3fd62ea1a 1128 \details Executes a LDA instruction for 32 bit values.
NYX 0:85b3fd62ea1a 1129 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 1130 \return value of type uint32_t at (*ptr)
NYX 0:85b3fd62ea1a 1131 */
NYX 0:85b3fd62ea1a 1132 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
NYX 0:85b3fd62ea1a 1133 {
NYX 0:85b3fd62ea1a 1134 uint32_t result;
NYX 0:85b3fd62ea1a 1135
NYX 0:85b3fd62ea1a 1136 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
NYX 0:85b3fd62ea1a 1137 return(result);
NYX 0:85b3fd62ea1a 1138 }
NYX 0:85b3fd62ea1a 1139
NYX 0:85b3fd62ea1a 1140
NYX 0:85b3fd62ea1a 1141 /**
NYX 0:85b3fd62ea1a 1142 \brief Store-Release (8 bit)
NYX 0:85b3fd62ea1a 1143 \details Executes a STLB instruction for 8 bit values.
NYX 0:85b3fd62ea1a 1144 \param [in] value Value to store
NYX 0:85b3fd62ea1a 1145 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 1146 */
NYX 0:85b3fd62ea1a 1147 __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
NYX 0:85b3fd62ea1a 1148 {
NYX 0:85b3fd62ea1a 1149 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
NYX 0:85b3fd62ea1a 1150 }
NYX 0:85b3fd62ea1a 1151
NYX 0:85b3fd62ea1a 1152
NYX 0:85b3fd62ea1a 1153 /**
NYX 0:85b3fd62ea1a 1154 \brief Store-Release (16 bit)
NYX 0:85b3fd62ea1a 1155 \details Executes a STLH instruction for 16 bit values.
NYX 0:85b3fd62ea1a 1156 \param [in] value Value to store
NYX 0:85b3fd62ea1a 1157 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 1158 */
NYX 0:85b3fd62ea1a 1159 __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
NYX 0:85b3fd62ea1a 1160 {
NYX 0:85b3fd62ea1a 1161 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
NYX 0:85b3fd62ea1a 1162 }
NYX 0:85b3fd62ea1a 1163
NYX 0:85b3fd62ea1a 1164
NYX 0:85b3fd62ea1a 1165 /**
NYX 0:85b3fd62ea1a 1166 \brief Store-Release (32 bit)
NYX 0:85b3fd62ea1a 1167 \details Executes a STL instruction for 32 bit values.
NYX 0:85b3fd62ea1a 1168 \param [in] value Value to store
NYX 0:85b3fd62ea1a 1169 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 1170 */
NYX 0:85b3fd62ea1a 1171 __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
NYX 0:85b3fd62ea1a 1172 {
NYX 0:85b3fd62ea1a 1173 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
NYX 0:85b3fd62ea1a 1174 }
NYX 0:85b3fd62ea1a 1175
NYX 0:85b3fd62ea1a 1176
NYX 0:85b3fd62ea1a 1177 /**
NYX 0:85b3fd62ea1a 1178 \brief Load-Acquire Exclusive (8 bit)
NYX 0:85b3fd62ea1a 1179 \details Executes a LDAB exclusive instruction for 8 bit value.
NYX 0:85b3fd62ea1a 1180 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 1181 \return value of type uint8_t at (*ptr)
NYX 0:85b3fd62ea1a 1182 */
NYX 0:85b3fd62ea1a 1183 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
NYX 0:85b3fd62ea1a 1184
NYX 0:85b3fd62ea1a 1185
NYX 0:85b3fd62ea1a 1186 /**
NYX 0:85b3fd62ea1a 1187 \brief Load-Acquire Exclusive (16 bit)
NYX 0:85b3fd62ea1a 1188 \details Executes a LDAH exclusive instruction for 16 bit values.
NYX 0:85b3fd62ea1a 1189 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 1190 \return value of type uint16_t at (*ptr)
NYX 0:85b3fd62ea1a 1191 */
NYX 0:85b3fd62ea1a 1192 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
NYX 0:85b3fd62ea1a 1193
NYX 0:85b3fd62ea1a 1194
NYX 0:85b3fd62ea1a 1195 /**
NYX 0:85b3fd62ea1a 1196 \brief Load-Acquire Exclusive (32 bit)
NYX 0:85b3fd62ea1a 1197 \details Executes a LDA exclusive instruction for 32 bit values.
NYX 0:85b3fd62ea1a 1198 \param [in] ptr Pointer to data
NYX 0:85b3fd62ea1a 1199 \return value of type uint32_t at (*ptr)
NYX 0:85b3fd62ea1a 1200 */
NYX 0:85b3fd62ea1a 1201 #define __LDAEX (uint32_t)__builtin_arm_ldaex
NYX 0:85b3fd62ea1a 1202
NYX 0:85b3fd62ea1a 1203
NYX 0:85b3fd62ea1a 1204 /**
NYX 0:85b3fd62ea1a 1205 \brief Store-Release Exclusive (8 bit)
NYX 0:85b3fd62ea1a 1206 \details Executes a STLB exclusive instruction for 8 bit values.
NYX 0:85b3fd62ea1a 1207 \param [in] value Value to store
NYX 0:85b3fd62ea1a 1208 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 1209 \return 0 Function succeeded
NYX 0:85b3fd62ea1a 1210 \return 1 Function failed
NYX 0:85b3fd62ea1a 1211 */
NYX 0:85b3fd62ea1a 1212 #define __STLEXB (uint32_t)__builtin_arm_stlex
NYX 0:85b3fd62ea1a 1213
NYX 0:85b3fd62ea1a 1214
NYX 0:85b3fd62ea1a 1215 /**
NYX 0:85b3fd62ea1a 1216 \brief Store-Release Exclusive (16 bit)
NYX 0:85b3fd62ea1a 1217 \details Executes a STLH exclusive instruction for 16 bit values.
NYX 0:85b3fd62ea1a 1218 \param [in] value Value to store
NYX 0:85b3fd62ea1a 1219 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 1220 \return 0 Function succeeded
NYX 0:85b3fd62ea1a 1221 \return 1 Function failed
NYX 0:85b3fd62ea1a 1222 */
NYX 0:85b3fd62ea1a 1223 #define __STLEXH (uint32_t)__builtin_arm_stlex
NYX 0:85b3fd62ea1a 1224
NYX 0:85b3fd62ea1a 1225
NYX 0:85b3fd62ea1a 1226 /**
NYX 0:85b3fd62ea1a 1227 \brief Store-Release Exclusive (32 bit)
NYX 0:85b3fd62ea1a 1228 \details Executes a STL exclusive instruction for 32 bit values.
NYX 0:85b3fd62ea1a 1229 \param [in] value Value to store
NYX 0:85b3fd62ea1a 1230 \param [in] ptr Pointer to location
NYX 0:85b3fd62ea1a 1231 \return 0 Function succeeded
NYX 0:85b3fd62ea1a 1232 \return 1 Function failed
NYX 0:85b3fd62ea1a 1233 */
NYX 0:85b3fd62ea1a 1234 #define __STLEX (uint32_t)__builtin_arm_stlex
NYX 0:85b3fd62ea1a 1235
NYX 0:85b3fd62ea1a 1236 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
NYX 0:85b3fd62ea1a 1237 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
NYX 0:85b3fd62ea1a 1238
NYX 0:85b3fd62ea1a 1239 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
NYX 0:85b3fd62ea1a 1240
NYX 0:85b3fd62ea1a 1241
NYX 0:85b3fd62ea1a 1242 /* ################### Compiler specific Intrinsics ########################### */
NYX 0:85b3fd62ea1a 1243 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
NYX 0:85b3fd62ea1a 1244 Access to dedicated SIMD instructions
NYX 0:85b3fd62ea1a 1245 @{
NYX 0:85b3fd62ea1a 1246 */
NYX 0:85b3fd62ea1a 1247
NYX 0:85b3fd62ea1a 1248 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
NYX 0:85b3fd62ea1a 1249
NYX 0:85b3fd62ea1a 1250 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1251 {
NYX 0:85b3fd62ea1a 1252 uint32_t result;
NYX 0:85b3fd62ea1a 1253
NYX 0:85b3fd62ea1a 1254 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1255 return(result);
NYX 0:85b3fd62ea1a 1256 }
NYX 0:85b3fd62ea1a 1257
NYX 0:85b3fd62ea1a 1258 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1259 {
NYX 0:85b3fd62ea1a 1260 uint32_t result;
NYX 0:85b3fd62ea1a 1261
NYX 0:85b3fd62ea1a 1262 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1263 return(result);
NYX 0:85b3fd62ea1a 1264 }
NYX 0:85b3fd62ea1a 1265
NYX 0:85b3fd62ea1a 1266 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1267 {
NYX 0:85b3fd62ea1a 1268 uint32_t result;
NYX 0:85b3fd62ea1a 1269
NYX 0:85b3fd62ea1a 1270 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1271 return(result);
NYX 0:85b3fd62ea1a 1272 }
NYX 0:85b3fd62ea1a 1273
NYX 0:85b3fd62ea1a 1274 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1275 {
NYX 0:85b3fd62ea1a 1276 uint32_t result;
NYX 0:85b3fd62ea1a 1277
NYX 0:85b3fd62ea1a 1278 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1279 return(result);
NYX 0:85b3fd62ea1a 1280 }
NYX 0:85b3fd62ea1a 1281
NYX 0:85b3fd62ea1a 1282 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1283 {
NYX 0:85b3fd62ea1a 1284 uint32_t result;
NYX 0:85b3fd62ea1a 1285
NYX 0:85b3fd62ea1a 1286 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1287 return(result);
NYX 0:85b3fd62ea1a 1288 }
NYX 0:85b3fd62ea1a 1289
NYX 0:85b3fd62ea1a 1290 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1291 {
NYX 0:85b3fd62ea1a 1292 uint32_t result;
NYX 0:85b3fd62ea1a 1293
NYX 0:85b3fd62ea1a 1294 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1295 return(result);
NYX 0:85b3fd62ea1a 1296 }
NYX 0:85b3fd62ea1a 1297
NYX 0:85b3fd62ea1a 1298
NYX 0:85b3fd62ea1a 1299 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1300 {
NYX 0:85b3fd62ea1a 1301 uint32_t result;
NYX 0:85b3fd62ea1a 1302
NYX 0:85b3fd62ea1a 1303 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1304 return(result);
NYX 0:85b3fd62ea1a 1305 }
NYX 0:85b3fd62ea1a 1306
NYX 0:85b3fd62ea1a 1307 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1308 {
NYX 0:85b3fd62ea1a 1309 uint32_t result;
NYX 0:85b3fd62ea1a 1310
NYX 0:85b3fd62ea1a 1311 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1312 return(result);
NYX 0:85b3fd62ea1a 1313 }
NYX 0:85b3fd62ea1a 1314
NYX 0:85b3fd62ea1a 1315 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1316 {
NYX 0:85b3fd62ea1a 1317 uint32_t result;
NYX 0:85b3fd62ea1a 1318
NYX 0:85b3fd62ea1a 1319 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1320 return(result);
NYX 0:85b3fd62ea1a 1321 }
NYX 0:85b3fd62ea1a 1322
NYX 0:85b3fd62ea1a 1323 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1324 {
NYX 0:85b3fd62ea1a 1325 uint32_t result;
NYX 0:85b3fd62ea1a 1326
NYX 0:85b3fd62ea1a 1327 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1328 return(result);
NYX 0:85b3fd62ea1a 1329 }
NYX 0:85b3fd62ea1a 1330
NYX 0:85b3fd62ea1a 1331 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1332 {
NYX 0:85b3fd62ea1a 1333 uint32_t result;
NYX 0:85b3fd62ea1a 1334
NYX 0:85b3fd62ea1a 1335 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1336 return(result);
NYX 0:85b3fd62ea1a 1337 }
NYX 0:85b3fd62ea1a 1338
NYX 0:85b3fd62ea1a 1339 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1340 {
NYX 0:85b3fd62ea1a 1341 uint32_t result;
NYX 0:85b3fd62ea1a 1342
NYX 0:85b3fd62ea1a 1343 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1344 return(result);
NYX 0:85b3fd62ea1a 1345 }
NYX 0:85b3fd62ea1a 1346
NYX 0:85b3fd62ea1a 1347
NYX 0:85b3fd62ea1a 1348 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1349 {
NYX 0:85b3fd62ea1a 1350 uint32_t result;
NYX 0:85b3fd62ea1a 1351
NYX 0:85b3fd62ea1a 1352 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1353 return(result);
NYX 0:85b3fd62ea1a 1354 }
NYX 0:85b3fd62ea1a 1355
NYX 0:85b3fd62ea1a 1356 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1357 {
NYX 0:85b3fd62ea1a 1358 uint32_t result;
NYX 0:85b3fd62ea1a 1359
NYX 0:85b3fd62ea1a 1360 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1361 return(result);
NYX 0:85b3fd62ea1a 1362 }
NYX 0:85b3fd62ea1a 1363
NYX 0:85b3fd62ea1a 1364 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1365 {
NYX 0:85b3fd62ea1a 1366 uint32_t result;
NYX 0:85b3fd62ea1a 1367
NYX 0:85b3fd62ea1a 1368 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1369 return(result);
NYX 0:85b3fd62ea1a 1370 }
NYX 0:85b3fd62ea1a 1371
NYX 0:85b3fd62ea1a 1372 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1373 {
NYX 0:85b3fd62ea1a 1374 uint32_t result;
NYX 0:85b3fd62ea1a 1375
NYX 0:85b3fd62ea1a 1376 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1377 return(result);
NYX 0:85b3fd62ea1a 1378 }
NYX 0:85b3fd62ea1a 1379
NYX 0:85b3fd62ea1a 1380 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1381 {
NYX 0:85b3fd62ea1a 1382 uint32_t result;
NYX 0:85b3fd62ea1a 1383
NYX 0:85b3fd62ea1a 1384 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1385 return(result);
NYX 0:85b3fd62ea1a 1386 }
NYX 0:85b3fd62ea1a 1387
NYX 0:85b3fd62ea1a 1388 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1389 {
NYX 0:85b3fd62ea1a 1390 uint32_t result;
NYX 0:85b3fd62ea1a 1391
NYX 0:85b3fd62ea1a 1392 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1393 return(result);
NYX 0:85b3fd62ea1a 1394 }
NYX 0:85b3fd62ea1a 1395
NYX 0:85b3fd62ea1a 1396 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1397 {
NYX 0:85b3fd62ea1a 1398 uint32_t result;
NYX 0:85b3fd62ea1a 1399
NYX 0:85b3fd62ea1a 1400 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1401 return(result);
NYX 0:85b3fd62ea1a 1402 }
NYX 0:85b3fd62ea1a 1403
NYX 0:85b3fd62ea1a 1404 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1405 {
NYX 0:85b3fd62ea1a 1406 uint32_t result;
NYX 0:85b3fd62ea1a 1407
NYX 0:85b3fd62ea1a 1408 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1409 return(result);
NYX 0:85b3fd62ea1a 1410 }
NYX 0:85b3fd62ea1a 1411
NYX 0:85b3fd62ea1a 1412 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1413 {
NYX 0:85b3fd62ea1a 1414 uint32_t result;
NYX 0:85b3fd62ea1a 1415
NYX 0:85b3fd62ea1a 1416 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1417 return(result);
NYX 0:85b3fd62ea1a 1418 }
NYX 0:85b3fd62ea1a 1419
NYX 0:85b3fd62ea1a 1420 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1421 {
NYX 0:85b3fd62ea1a 1422 uint32_t result;
NYX 0:85b3fd62ea1a 1423
NYX 0:85b3fd62ea1a 1424 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1425 return(result);
NYX 0:85b3fd62ea1a 1426 }
NYX 0:85b3fd62ea1a 1427
NYX 0:85b3fd62ea1a 1428 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1429 {
NYX 0:85b3fd62ea1a 1430 uint32_t result;
NYX 0:85b3fd62ea1a 1431
NYX 0:85b3fd62ea1a 1432 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1433 return(result);
NYX 0:85b3fd62ea1a 1434 }
NYX 0:85b3fd62ea1a 1435
NYX 0:85b3fd62ea1a 1436 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1437 {
NYX 0:85b3fd62ea1a 1438 uint32_t result;
NYX 0:85b3fd62ea1a 1439
NYX 0:85b3fd62ea1a 1440 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1441 return(result);
NYX 0:85b3fd62ea1a 1442 }
NYX 0:85b3fd62ea1a 1443
NYX 0:85b3fd62ea1a 1444 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1445 {
NYX 0:85b3fd62ea1a 1446 uint32_t result;
NYX 0:85b3fd62ea1a 1447
NYX 0:85b3fd62ea1a 1448 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1449 return(result);
NYX 0:85b3fd62ea1a 1450 }
NYX 0:85b3fd62ea1a 1451
NYX 0:85b3fd62ea1a 1452 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1453 {
NYX 0:85b3fd62ea1a 1454 uint32_t result;
NYX 0:85b3fd62ea1a 1455
NYX 0:85b3fd62ea1a 1456 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1457 return(result);
NYX 0:85b3fd62ea1a 1458 }
NYX 0:85b3fd62ea1a 1459
NYX 0:85b3fd62ea1a 1460 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1461 {
NYX 0:85b3fd62ea1a 1462 uint32_t result;
NYX 0:85b3fd62ea1a 1463
NYX 0:85b3fd62ea1a 1464 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1465 return(result);
NYX 0:85b3fd62ea1a 1466 }
NYX 0:85b3fd62ea1a 1467
NYX 0:85b3fd62ea1a 1468 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1469 {
NYX 0:85b3fd62ea1a 1470 uint32_t result;
NYX 0:85b3fd62ea1a 1471
NYX 0:85b3fd62ea1a 1472 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1473 return(result);
NYX 0:85b3fd62ea1a 1474 }
NYX 0:85b3fd62ea1a 1475
NYX 0:85b3fd62ea1a 1476 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1477 {
NYX 0:85b3fd62ea1a 1478 uint32_t result;
NYX 0:85b3fd62ea1a 1479
NYX 0:85b3fd62ea1a 1480 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1481 return(result);
NYX 0:85b3fd62ea1a 1482 }
NYX 0:85b3fd62ea1a 1483
NYX 0:85b3fd62ea1a 1484 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1485 {
NYX 0:85b3fd62ea1a 1486 uint32_t result;
NYX 0:85b3fd62ea1a 1487
NYX 0:85b3fd62ea1a 1488 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1489 return(result);
NYX 0:85b3fd62ea1a 1490 }
NYX 0:85b3fd62ea1a 1491
NYX 0:85b3fd62ea1a 1492 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1493 {
NYX 0:85b3fd62ea1a 1494 uint32_t result;
NYX 0:85b3fd62ea1a 1495
NYX 0:85b3fd62ea1a 1496 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1497 return(result);
NYX 0:85b3fd62ea1a 1498 }
NYX 0:85b3fd62ea1a 1499
NYX 0:85b3fd62ea1a 1500 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1501 {
NYX 0:85b3fd62ea1a 1502 uint32_t result;
NYX 0:85b3fd62ea1a 1503
NYX 0:85b3fd62ea1a 1504 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1505 return(result);
NYX 0:85b3fd62ea1a 1506 }
NYX 0:85b3fd62ea1a 1507
NYX 0:85b3fd62ea1a 1508 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1509 {
NYX 0:85b3fd62ea1a 1510 uint32_t result;
NYX 0:85b3fd62ea1a 1511
NYX 0:85b3fd62ea1a 1512 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1513 return(result);
NYX 0:85b3fd62ea1a 1514 }
NYX 0:85b3fd62ea1a 1515
NYX 0:85b3fd62ea1a 1516 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1517 {
NYX 0:85b3fd62ea1a 1518 uint32_t result;
NYX 0:85b3fd62ea1a 1519
NYX 0:85b3fd62ea1a 1520 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1521 return(result);
NYX 0:85b3fd62ea1a 1522 }
NYX 0:85b3fd62ea1a 1523
NYX 0:85b3fd62ea1a 1524 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1525 {
NYX 0:85b3fd62ea1a 1526 uint32_t result;
NYX 0:85b3fd62ea1a 1527
NYX 0:85b3fd62ea1a 1528 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1529 return(result);
NYX 0:85b3fd62ea1a 1530 }
NYX 0:85b3fd62ea1a 1531
NYX 0:85b3fd62ea1a 1532 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1533 {
NYX 0:85b3fd62ea1a 1534 uint32_t result;
NYX 0:85b3fd62ea1a 1535
NYX 0:85b3fd62ea1a 1536 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1537 return(result);
NYX 0:85b3fd62ea1a 1538 }
NYX 0:85b3fd62ea1a 1539
NYX 0:85b3fd62ea1a 1540 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1541 {
NYX 0:85b3fd62ea1a 1542 uint32_t result;
NYX 0:85b3fd62ea1a 1543
NYX 0:85b3fd62ea1a 1544 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1545 return(result);
NYX 0:85b3fd62ea1a 1546 }
NYX 0:85b3fd62ea1a 1547
NYX 0:85b3fd62ea1a 1548 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
NYX 0:85b3fd62ea1a 1549 {
NYX 0:85b3fd62ea1a 1550 uint32_t result;
NYX 0:85b3fd62ea1a 1551
NYX 0:85b3fd62ea1a 1552 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
NYX 0:85b3fd62ea1a 1553 return(result);
NYX 0:85b3fd62ea1a 1554 }
NYX 0:85b3fd62ea1a 1555
NYX 0:85b3fd62ea1a 1556 #define __SSAT16(ARG1,ARG2) \
NYX 0:85b3fd62ea1a 1557 ({ \
NYX 0:85b3fd62ea1a 1558 int32_t __RES, __ARG1 = (ARG1); \
NYX 0:85b3fd62ea1a 1559 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
NYX 0:85b3fd62ea1a 1560 __RES; \
NYX 0:85b3fd62ea1a 1561 })
NYX 0:85b3fd62ea1a 1562
NYX 0:85b3fd62ea1a 1563 #define __USAT16(ARG1,ARG2) \
NYX 0:85b3fd62ea1a 1564 ({ \
NYX 0:85b3fd62ea1a 1565 uint32_t __RES, __ARG1 = (ARG1); \
NYX 0:85b3fd62ea1a 1566 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
NYX 0:85b3fd62ea1a 1567 __RES; \
NYX 0:85b3fd62ea1a 1568 })
NYX 0:85b3fd62ea1a 1569
NYX 0:85b3fd62ea1a 1570 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
NYX 0:85b3fd62ea1a 1571 {
NYX 0:85b3fd62ea1a 1572 uint32_t result;
NYX 0:85b3fd62ea1a 1573
NYX 0:85b3fd62ea1a 1574 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
NYX 0:85b3fd62ea1a 1575 return(result);
NYX 0:85b3fd62ea1a 1576 }
NYX 0:85b3fd62ea1a 1577
NYX 0:85b3fd62ea1a 1578 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1579 {
NYX 0:85b3fd62ea1a 1580 uint32_t result;
NYX 0:85b3fd62ea1a 1581
NYX 0:85b3fd62ea1a 1582 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1583 return(result);
NYX 0:85b3fd62ea1a 1584 }
NYX 0:85b3fd62ea1a 1585
NYX 0:85b3fd62ea1a 1586 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
NYX 0:85b3fd62ea1a 1587 {
NYX 0:85b3fd62ea1a 1588 uint32_t result;
NYX 0:85b3fd62ea1a 1589
NYX 0:85b3fd62ea1a 1590 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
NYX 0:85b3fd62ea1a 1591 return(result);
NYX 0:85b3fd62ea1a 1592 }
NYX 0:85b3fd62ea1a 1593
NYX 0:85b3fd62ea1a 1594 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1595 {
NYX 0:85b3fd62ea1a 1596 uint32_t result;
NYX 0:85b3fd62ea1a 1597
NYX 0:85b3fd62ea1a 1598 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1599 return(result);
NYX 0:85b3fd62ea1a 1600 }
NYX 0:85b3fd62ea1a 1601
NYX 0:85b3fd62ea1a 1602 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1603 {
NYX 0:85b3fd62ea1a 1604 uint32_t result;
NYX 0:85b3fd62ea1a 1605
NYX 0:85b3fd62ea1a 1606 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1607 return(result);
NYX 0:85b3fd62ea1a 1608 }
NYX 0:85b3fd62ea1a 1609
NYX 0:85b3fd62ea1a 1610 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1611 {
NYX 0:85b3fd62ea1a 1612 uint32_t result;
NYX 0:85b3fd62ea1a 1613
NYX 0:85b3fd62ea1a 1614 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1615 return(result);
NYX 0:85b3fd62ea1a 1616 }
NYX 0:85b3fd62ea1a 1617
NYX 0:85b3fd62ea1a 1618 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
NYX 0:85b3fd62ea1a 1619 {
NYX 0:85b3fd62ea1a 1620 uint32_t result;
NYX 0:85b3fd62ea1a 1621
NYX 0:85b3fd62ea1a 1622 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
NYX 0:85b3fd62ea1a 1623 return(result);
NYX 0:85b3fd62ea1a 1624 }
NYX 0:85b3fd62ea1a 1625
NYX 0:85b3fd62ea1a 1626 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
NYX 0:85b3fd62ea1a 1627 {
NYX 0:85b3fd62ea1a 1628 uint32_t result;
NYX 0:85b3fd62ea1a 1629
NYX 0:85b3fd62ea1a 1630 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
NYX 0:85b3fd62ea1a 1631 return(result);
NYX 0:85b3fd62ea1a 1632 }
NYX 0:85b3fd62ea1a 1633
NYX 0:85b3fd62ea1a 1634 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
NYX 0:85b3fd62ea1a 1635 {
NYX 0:85b3fd62ea1a 1636 union llreg_u{
NYX 0:85b3fd62ea1a 1637 uint32_t w32[2];
NYX 0:85b3fd62ea1a 1638 uint64_t w64;
NYX 0:85b3fd62ea1a 1639 } llr;
NYX 0:85b3fd62ea1a 1640 llr.w64 = acc;
NYX 0:85b3fd62ea1a 1641
NYX 0:85b3fd62ea1a 1642 #ifndef __ARMEB__ /* Little endian */
NYX 0:85b3fd62ea1a 1643 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
NYX 0:85b3fd62ea1a 1644 #else /* Big endian */
NYX 0:85b3fd62ea1a 1645 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
NYX 0:85b3fd62ea1a 1646 #endif
NYX 0:85b3fd62ea1a 1647
NYX 0:85b3fd62ea1a 1648 return(llr.w64);
NYX 0:85b3fd62ea1a 1649 }
NYX 0:85b3fd62ea1a 1650
NYX 0:85b3fd62ea1a 1651 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
NYX 0:85b3fd62ea1a 1652 {
NYX 0:85b3fd62ea1a 1653 union llreg_u{
NYX 0:85b3fd62ea1a 1654 uint32_t w32[2];
NYX 0:85b3fd62ea1a 1655 uint64_t w64;
NYX 0:85b3fd62ea1a 1656 } llr;
NYX 0:85b3fd62ea1a 1657 llr.w64 = acc;
NYX 0:85b3fd62ea1a 1658
NYX 0:85b3fd62ea1a 1659 #ifndef __ARMEB__ /* Little endian */
NYX 0:85b3fd62ea1a 1660 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
NYX 0:85b3fd62ea1a 1661 #else /* Big endian */
NYX 0:85b3fd62ea1a 1662 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
NYX 0:85b3fd62ea1a 1663 #endif
NYX 0:85b3fd62ea1a 1664
NYX 0:85b3fd62ea1a 1665 return(llr.w64);
NYX 0:85b3fd62ea1a 1666 }
NYX 0:85b3fd62ea1a 1667
NYX 0:85b3fd62ea1a 1668 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1669 {
NYX 0:85b3fd62ea1a 1670 uint32_t result;
NYX 0:85b3fd62ea1a 1671
NYX 0:85b3fd62ea1a 1672 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1673 return(result);
NYX 0:85b3fd62ea1a 1674 }
NYX 0:85b3fd62ea1a 1675
NYX 0:85b3fd62ea1a 1676 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1677 {
NYX 0:85b3fd62ea1a 1678 uint32_t result;
NYX 0:85b3fd62ea1a 1679
NYX 0:85b3fd62ea1a 1680 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1681 return(result);
NYX 0:85b3fd62ea1a 1682 }
NYX 0:85b3fd62ea1a 1683
NYX 0:85b3fd62ea1a 1684 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
NYX 0:85b3fd62ea1a 1685 {
NYX 0:85b3fd62ea1a 1686 uint32_t result;
NYX 0:85b3fd62ea1a 1687
NYX 0:85b3fd62ea1a 1688 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
NYX 0:85b3fd62ea1a 1689 return(result);
NYX 0:85b3fd62ea1a 1690 }
NYX 0:85b3fd62ea1a 1691
NYX 0:85b3fd62ea1a 1692 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
NYX 0:85b3fd62ea1a 1693 {
NYX 0:85b3fd62ea1a 1694 uint32_t result;
NYX 0:85b3fd62ea1a 1695
NYX 0:85b3fd62ea1a 1696 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
NYX 0:85b3fd62ea1a 1697 return(result);
NYX 0:85b3fd62ea1a 1698 }
NYX 0:85b3fd62ea1a 1699
NYX 0:85b3fd62ea1a 1700 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
NYX 0:85b3fd62ea1a 1701 {
NYX 0:85b3fd62ea1a 1702 union llreg_u{
NYX 0:85b3fd62ea1a 1703 uint32_t w32[2];
NYX 0:85b3fd62ea1a 1704 uint64_t w64;
NYX 0:85b3fd62ea1a 1705 } llr;
NYX 0:85b3fd62ea1a 1706 llr.w64 = acc;
NYX 0:85b3fd62ea1a 1707
NYX 0:85b3fd62ea1a 1708 #ifndef __ARMEB__ /* Little endian */
NYX 0:85b3fd62ea1a 1709 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
NYX 0:85b3fd62ea1a 1710 #else /* Big endian */
NYX 0:85b3fd62ea1a 1711 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
NYX 0:85b3fd62ea1a 1712 #endif
NYX 0:85b3fd62ea1a 1713
NYX 0:85b3fd62ea1a 1714 return(llr.w64);
NYX 0:85b3fd62ea1a 1715 }
NYX 0:85b3fd62ea1a 1716
NYX 0:85b3fd62ea1a 1717 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
NYX 0:85b3fd62ea1a 1718 {
NYX 0:85b3fd62ea1a 1719 union llreg_u{
NYX 0:85b3fd62ea1a 1720 uint32_t w32[2];
NYX 0:85b3fd62ea1a 1721 uint64_t w64;
NYX 0:85b3fd62ea1a 1722 } llr;
NYX 0:85b3fd62ea1a 1723 llr.w64 = acc;
NYX 0:85b3fd62ea1a 1724
NYX 0:85b3fd62ea1a 1725 #ifndef __ARMEB__ /* Little endian */
NYX 0:85b3fd62ea1a 1726 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
NYX 0:85b3fd62ea1a 1727 #else /* Big endian */
NYX 0:85b3fd62ea1a 1728 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
NYX 0:85b3fd62ea1a 1729 #endif
NYX 0:85b3fd62ea1a 1730
NYX 0:85b3fd62ea1a 1731 return(llr.w64);
NYX 0:85b3fd62ea1a 1732 }
NYX 0:85b3fd62ea1a 1733
NYX 0:85b3fd62ea1a 1734 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
NYX 0:85b3fd62ea1a 1735 {
NYX 0:85b3fd62ea1a 1736 uint32_t result;
NYX 0:85b3fd62ea1a 1737
NYX 0:85b3fd62ea1a 1738 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1739 return(result);
NYX 0:85b3fd62ea1a 1740 }
NYX 0:85b3fd62ea1a 1741
NYX 0:85b3fd62ea1a 1742 __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
NYX 0:85b3fd62ea1a 1743 {
NYX 0:85b3fd62ea1a 1744 int32_t result;
NYX 0:85b3fd62ea1a 1745
NYX 0:85b3fd62ea1a 1746 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1747 return(result);
NYX 0:85b3fd62ea1a 1748 }
NYX 0:85b3fd62ea1a 1749
NYX 0:85b3fd62ea1a 1750 __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
NYX 0:85b3fd62ea1a 1751 {
NYX 0:85b3fd62ea1a 1752 int32_t result;
NYX 0:85b3fd62ea1a 1753
NYX 0:85b3fd62ea1a 1754 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
NYX 0:85b3fd62ea1a 1755 return(result);
NYX 0:85b3fd62ea1a 1756 }
NYX 0:85b3fd62ea1a 1757
NYX 0:85b3fd62ea1a 1758 #if 0
NYX 0:85b3fd62ea1a 1759 #define __PKHBT(ARG1,ARG2,ARG3) \
NYX 0:85b3fd62ea1a 1760 ({ \
NYX 0:85b3fd62ea1a 1761 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
NYX 0:85b3fd62ea1a 1762 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
NYX 0:85b3fd62ea1a 1763 __RES; \
NYX 0:85b3fd62ea1a 1764 })
NYX 0:85b3fd62ea1a 1765
NYX 0:85b3fd62ea1a 1766 #define __PKHTB(ARG1,ARG2,ARG3) \
NYX 0:85b3fd62ea1a 1767 ({ \
NYX 0:85b3fd62ea1a 1768 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
NYX 0:85b3fd62ea1a 1769 if (ARG3 == 0) \
NYX 0:85b3fd62ea1a 1770 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
NYX 0:85b3fd62ea1a 1771 else \
NYX 0:85b3fd62ea1a 1772 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
NYX 0:85b3fd62ea1a 1773 __RES; \
NYX 0:85b3fd62ea1a 1774 })
NYX 0:85b3fd62ea1a 1775 #endif
NYX 0:85b3fd62ea1a 1776
NYX 0:85b3fd62ea1a 1777 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
NYX 0:85b3fd62ea1a 1778 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
NYX 0:85b3fd62ea1a 1779
NYX 0:85b3fd62ea1a 1780 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
NYX 0:85b3fd62ea1a 1781 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
NYX 0:85b3fd62ea1a 1782
NYX 0:85b3fd62ea1a 1783 __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
NYX 0:85b3fd62ea1a 1784 {
NYX 0:85b3fd62ea1a 1785 int32_t result;
NYX 0:85b3fd62ea1a 1786
NYX 0:85b3fd62ea1a 1787 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
NYX 0:85b3fd62ea1a 1788 return(result);
NYX 0:85b3fd62ea1a 1789 }
NYX 0:85b3fd62ea1a 1790
NYX 0:85b3fd62ea1a 1791 #endif /* (__ARM_FEATURE_DSP == 1) */
NYX 0:85b3fd62ea1a 1792 /*@} end of group CMSIS_SIMD_intrinsics */
NYX 0:85b3fd62ea1a 1793
NYX 0:85b3fd62ea1a 1794
NYX 0:85b3fd62ea1a 1795 #endif /* __CMSIS_ARMCLANG_H */