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Dependents: WizFi250_AP_HelloWorld
Fork of
mbed-src
by 
DongEun Koak
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lptmr.h@324:406fd2029f23, 2014-09-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 18 14:00:17 2014 +0100
- Revision:
- 324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5
Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/
Extended #476, which does not break ethernet for K64F
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 324:406fd2029f23 | 1 | /* |
| mbed_official | 324:406fd2029f23 | 2 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 3 | ** Compilers: Keil ARM C/C++ Compiler |
| mbed_official | 324:406fd2029f23 | 4 | ** Freescale C/C++ for Embedded ARM |
| mbed_official | 324:406fd2029f23 | 5 | ** GNU C Compiler |
| mbed_official | 324:406fd2029f23 | 6 | ** IAR ANSI C/C++ Compiler for ARM |
| mbed_official | 324:406fd2029f23 | 7 | ** |
| mbed_official | 324:406fd2029f23 | 8 | ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 |
| mbed_official | 324:406fd2029f23 | 9 | ** Version: rev. 2.5, 2014-05-06 |
| mbed_official | 324:406fd2029f23 | 10 | ** Build: b140604 |
| mbed_official | 324:406fd2029f23 | 11 | ** |
| mbed_official | 324:406fd2029f23 | 12 | ** Abstract: |
| mbed_official | 324:406fd2029f23 | 13 | ** Extension to the CMSIS register access layer header. |
| mbed_official | 324:406fd2029f23 | 14 | ** |
| mbed_official | 324:406fd2029f23 | 15 | ** Copyright (c) 2014 Freescale Semiconductor, Inc. |
| mbed_official | 324:406fd2029f23 | 16 | ** All rights reserved. |
| mbed_official | 324:406fd2029f23 | 17 | ** |
| mbed_official | 324:406fd2029f23 | 18 | ** Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 324:406fd2029f23 | 19 | ** are permitted provided that the following conditions are met: |
| mbed_official | 324:406fd2029f23 | 20 | ** |
| mbed_official | 324:406fd2029f23 | 21 | ** o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 324:406fd2029f23 | 22 | ** of conditions and the following disclaimer. |
| mbed_official | 324:406fd2029f23 | 23 | ** |
| mbed_official | 324:406fd2029f23 | 24 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 324:406fd2029f23 | 25 | ** list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 324:406fd2029f23 | 26 | ** other materials provided with the distribution. |
| mbed_official | 324:406fd2029f23 | 27 | ** |
| mbed_official | 324:406fd2029f23 | 28 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 324:406fd2029f23 | 29 | ** contributors may be used to endorse or promote products derived from this |
| mbed_official | 324:406fd2029f23 | 30 | ** software without specific prior written permission. |
| mbed_official | 324:406fd2029f23 | 31 | ** |
| mbed_official | 324:406fd2029f23 | 32 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 324:406fd2029f23 | 33 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 324:406fd2029f23 | 34 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 324:406fd2029f23 | 35 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 324:406fd2029f23 | 36 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 324:406fd2029f23 | 37 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 324:406fd2029f23 | 38 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 324:406fd2029f23 | 39 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 324:406fd2029f23 | 40 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 324:406fd2029f23 | 41 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 324:406fd2029f23 | 42 | ** |
| mbed_official | 324:406fd2029f23 | 43 | ** http: www.freescale.com |
| mbed_official | 324:406fd2029f23 | 44 | ** mail: support@freescale.com |
| mbed_official | 324:406fd2029f23 | 45 | ** |
| mbed_official | 324:406fd2029f23 | 46 | ** Revisions: |
| mbed_official | 324:406fd2029f23 | 47 | ** - rev. 1.0 (2013-07-23) |
| mbed_official | 324:406fd2029f23 | 48 | ** Initial version. |
| mbed_official | 324:406fd2029f23 | 49 | ** - rev. 1.1 (2013-09-17) |
| mbed_official | 324:406fd2029f23 | 50 | ** RM rev. 0.4 update. |
| mbed_official | 324:406fd2029f23 | 51 | ** - rev. 2.0 (2013-10-29) |
| mbed_official | 324:406fd2029f23 | 52 | ** Register accessor macros added to the memory map. |
| mbed_official | 324:406fd2029f23 | 53 | ** Symbols for Processor Expert memory map compatibility added to the memory map. |
| mbed_official | 324:406fd2029f23 | 54 | ** Startup file for gcc has been updated according to CMSIS 3.2. |
| mbed_official | 324:406fd2029f23 | 55 | ** System initialization updated. |
| mbed_official | 324:406fd2029f23 | 56 | ** - rev. 2.1 (2013-10-30) |
| mbed_official | 324:406fd2029f23 | 57 | ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. |
| mbed_official | 324:406fd2029f23 | 58 | ** - rev. 2.2 (2013-12-20) |
| mbed_official | 324:406fd2029f23 | 59 | ** Update according to reference manual rev. 0.6, |
| mbed_official | 324:406fd2029f23 | 60 | ** - rev. 2.3 (2014-01-13) |
| mbed_official | 324:406fd2029f23 | 61 | ** Update according to reference manual rev. 0.61, |
| mbed_official | 324:406fd2029f23 | 62 | ** - rev. 2.4 (2014-02-10) |
| mbed_official | 324:406fd2029f23 | 63 | ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h |
| mbed_official | 324:406fd2029f23 | 64 | ** - rev. 2.5 (2014-05-06) |
| mbed_official | 324:406fd2029f23 | 65 | ** Update according to reference manual rev. 1.0, |
| mbed_official | 324:406fd2029f23 | 66 | ** Update of system and startup files. |
| mbed_official | 324:406fd2029f23 | 67 | ** Module access macro module_BASES replaced by module_BASE_PTRS. |
| mbed_official | 324:406fd2029f23 | 68 | ** |
| mbed_official | 324:406fd2029f23 | 69 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 70 | */ |
| mbed_official | 324:406fd2029f23 | 71 | |
| mbed_official | 324:406fd2029f23 | 72 | /* |
| mbed_official | 324:406fd2029f23 | 73 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
| mbed_official | 324:406fd2029f23 | 74 | * |
| mbed_official | 324:406fd2029f23 | 75 | * This file was generated automatically and any changes may be lost. |
| mbed_official | 324:406fd2029f23 | 76 | */ |
| mbed_official | 324:406fd2029f23 | 77 | #ifndef __HW_LPTMR_REGISTERS_H__ |
| mbed_official | 324:406fd2029f23 | 78 | #define __HW_LPTMR_REGISTERS_H__ |
| mbed_official | 324:406fd2029f23 | 79 | |
| mbed_official | 324:406fd2029f23 | 80 | #include "MK22F51212.h" |
| mbed_official | 324:406fd2029f23 | 81 | #include "fsl_bitaccess.h" |
| mbed_official | 324:406fd2029f23 | 82 | |
| mbed_official | 324:406fd2029f23 | 83 | /* |
| mbed_official | 324:406fd2029f23 | 84 | * MK22F51212 LPTMR |
| mbed_official | 324:406fd2029f23 | 85 | * |
| mbed_official | 324:406fd2029f23 | 86 | * Low Power Timer |
| mbed_official | 324:406fd2029f23 | 87 | * |
| mbed_official | 324:406fd2029f23 | 88 | * Registers defined in this header file: |
| mbed_official | 324:406fd2029f23 | 89 | * - HW_LPTMR_CSR - Low Power Timer Control Status Register |
| mbed_official | 324:406fd2029f23 | 90 | * - HW_LPTMR_PSR - Low Power Timer Prescale Register |
| mbed_official | 324:406fd2029f23 | 91 | * - HW_LPTMR_CMR - Low Power Timer Compare Register |
| mbed_official | 324:406fd2029f23 | 92 | * - HW_LPTMR_CNR - Low Power Timer Counter Register |
| mbed_official | 324:406fd2029f23 | 93 | * |
| mbed_official | 324:406fd2029f23 | 94 | * - hw_lptmr_t - Struct containing all module registers. |
| mbed_official | 324:406fd2029f23 | 95 | */ |
| mbed_official | 324:406fd2029f23 | 96 | |
| mbed_official | 324:406fd2029f23 | 97 | #define HW_LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */ |
| mbed_official | 324:406fd2029f23 | 98 | |
| mbed_official | 324:406fd2029f23 | 99 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 100 | * HW_LPTMR_CSR - Low Power Timer Control Status Register |
| mbed_official | 324:406fd2029f23 | 101 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 102 | |
| mbed_official | 324:406fd2029f23 | 103 | /*! |
| mbed_official | 324:406fd2029f23 | 104 | * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW) |
| mbed_official | 324:406fd2029f23 | 105 | * |
| mbed_official | 324:406fd2029f23 | 106 | * Reset value: 0x00000000U |
| mbed_official | 324:406fd2029f23 | 107 | */ |
| mbed_official | 324:406fd2029f23 | 108 | typedef union _hw_lptmr_csr |
| mbed_official | 324:406fd2029f23 | 109 | { |
| mbed_official | 324:406fd2029f23 | 110 | uint32_t U; |
| mbed_official | 324:406fd2029f23 | 111 | struct _hw_lptmr_csr_bitfields |
| mbed_official | 324:406fd2029f23 | 112 | { |
| mbed_official | 324:406fd2029f23 | 113 | uint32_t TEN : 1; /*!< [0] Timer Enable */ |
| mbed_official | 324:406fd2029f23 | 114 | uint32_t TMS : 1; /*!< [1] Timer Mode Select */ |
| mbed_official | 324:406fd2029f23 | 115 | uint32_t TFC : 1; /*!< [2] Timer Free-Running Counter */ |
| mbed_official | 324:406fd2029f23 | 116 | uint32_t TPP : 1; /*!< [3] Timer Pin Polarity */ |
| mbed_official | 324:406fd2029f23 | 117 | uint32_t TPS : 2; /*!< [5:4] Timer Pin Select */ |
| mbed_official | 324:406fd2029f23 | 118 | uint32_t TIE : 1; /*!< [6] Timer Interrupt Enable */ |
| mbed_official | 324:406fd2029f23 | 119 | uint32_t TCF : 1; /*!< [7] Timer Compare Flag */ |
| mbed_official | 324:406fd2029f23 | 120 | uint32_t RESERVED0 : 24; /*!< [31:8] */ |
| mbed_official | 324:406fd2029f23 | 121 | } B; |
| mbed_official | 324:406fd2029f23 | 122 | } hw_lptmr_csr_t; |
| mbed_official | 324:406fd2029f23 | 123 | |
| mbed_official | 324:406fd2029f23 | 124 | /*! |
| mbed_official | 324:406fd2029f23 | 125 | * @name Constants and macros for entire LPTMR_CSR register |
| mbed_official | 324:406fd2029f23 | 126 | */ |
| mbed_official | 324:406fd2029f23 | 127 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 128 | #define HW_LPTMR_CSR_ADDR(x) ((x) + 0x0U) |
| mbed_official | 324:406fd2029f23 | 129 | |
| mbed_official | 324:406fd2029f23 | 130 | #define HW_LPTMR_CSR(x) (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 131 | #define HW_LPTMR_CSR_RD(x) (HW_LPTMR_CSR(x).U) |
| mbed_official | 324:406fd2029f23 | 132 | #define HW_LPTMR_CSR_WR(x, v) (HW_LPTMR_CSR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 133 | #define HW_LPTMR_CSR_SET(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 134 | #define HW_LPTMR_CSR_CLR(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 135 | #define HW_LPTMR_CSR_TOG(x, v) (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 136 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 137 | |
| mbed_official | 324:406fd2029f23 | 138 | /* |
| mbed_official | 324:406fd2029f23 | 139 | * Constants & macros for individual LPTMR_CSR bitfields |
| mbed_official | 324:406fd2029f23 | 140 | */ |
| mbed_official | 324:406fd2029f23 | 141 | |
| mbed_official | 324:406fd2029f23 | 142 | /*! |
| mbed_official | 324:406fd2029f23 | 143 | * @name Register LPTMR_CSR, field TEN[0] (RW) |
| mbed_official | 324:406fd2029f23 | 144 | * |
| mbed_official | 324:406fd2029f23 | 145 | * When TEN is clear, it resets the LPTMR internal logic, including the CNR and |
| mbed_official | 324:406fd2029f23 | 146 | * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field, |
| mbed_official | 324:406fd2029f23 | 147 | * CSR[5:1] must not be altered. |
| mbed_official | 324:406fd2029f23 | 148 | * |
| mbed_official | 324:406fd2029f23 | 149 | * Values: |
| mbed_official | 324:406fd2029f23 | 150 | * - 0 - LPTMR is disabled and internal logic is reset. |
| mbed_official | 324:406fd2029f23 | 151 | * - 1 - LPTMR is enabled. |
| mbed_official | 324:406fd2029f23 | 152 | */ |
| mbed_official | 324:406fd2029f23 | 153 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 154 | #define BP_LPTMR_CSR_TEN (0U) /*!< Bit position for LPTMR_CSR_TEN. */ |
| mbed_official | 324:406fd2029f23 | 155 | #define BM_LPTMR_CSR_TEN (0x00000001U) /*!< Bit mask for LPTMR_CSR_TEN. */ |
| mbed_official | 324:406fd2029f23 | 156 | #define BS_LPTMR_CSR_TEN (1U) /*!< Bit field size in bits for LPTMR_CSR_TEN. */ |
| mbed_official | 324:406fd2029f23 | 157 | |
| mbed_official | 324:406fd2029f23 | 158 | /*! @brief Read current value of the LPTMR_CSR_TEN field. */ |
| mbed_official | 324:406fd2029f23 | 159 | #define BR_LPTMR_CSR_TEN(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN)) |
| mbed_official | 324:406fd2029f23 | 160 | |
| mbed_official | 324:406fd2029f23 | 161 | /*! @brief Format value for bitfield LPTMR_CSR_TEN. */ |
| mbed_official | 324:406fd2029f23 | 162 | #define BF_LPTMR_CSR_TEN(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TEN) & BM_LPTMR_CSR_TEN) |
| mbed_official | 324:406fd2029f23 | 163 | |
| mbed_official | 324:406fd2029f23 | 164 | /*! @brief Set the TEN field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 165 | #define BW_LPTMR_CSR_TEN(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN) = (v)) |
| mbed_official | 324:406fd2029f23 | 166 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 167 | |
| mbed_official | 324:406fd2029f23 | 168 | /*! |
| mbed_official | 324:406fd2029f23 | 169 | * @name Register LPTMR_CSR, field TMS[1] (RW) |
| mbed_official | 324:406fd2029f23 | 170 | * |
| mbed_official | 324:406fd2029f23 | 171 | * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is |
| mbed_official | 324:406fd2029f23 | 172 | * disabled. |
| mbed_official | 324:406fd2029f23 | 173 | * |
| mbed_official | 324:406fd2029f23 | 174 | * Values: |
| mbed_official | 324:406fd2029f23 | 175 | * - 0 - Time Counter mode. |
| mbed_official | 324:406fd2029f23 | 176 | * - 1 - Pulse Counter mode. |
| mbed_official | 324:406fd2029f23 | 177 | */ |
| mbed_official | 324:406fd2029f23 | 178 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 179 | #define BP_LPTMR_CSR_TMS (1U) /*!< Bit position for LPTMR_CSR_TMS. */ |
| mbed_official | 324:406fd2029f23 | 180 | #define BM_LPTMR_CSR_TMS (0x00000002U) /*!< Bit mask for LPTMR_CSR_TMS. */ |
| mbed_official | 324:406fd2029f23 | 181 | #define BS_LPTMR_CSR_TMS (1U) /*!< Bit field size in bits for LPTMR_CSR_TMS. */ |
| mbed_official | 324:406fd2029f23 | 182 | |
| mbed_official | 324:406fd2029f23 | 183 | /*! @brief Read current value of the LPTMR_CSR_TMS field. */ |
| mbed_official | 324:406fd2029f23 | 184 | #define BR_LPTMR_CSR_TMS(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS)) |
| mbed_official | 324:406fd2029f23 | 185 | |
| mbed_official | 324:406fd2029f23 | 186 | /*! @brief Format value for bitfield LPTMR_CSR_TMS. */ |
| mbed_official | 324:406fd2029f23 | 187 | #define BF_LPTMR_CSR_TMS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TMS) & BM_LPTMR_CSR_TMS) |
| mbed_official | 324:406fd2029f23 | 188 | |
| mbed_official | 324:406fd2029f23 | 189 | /*! @brief Set the TMS field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 190 | #define BW_LPTMR_CSR_TMS(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS) = (v)) |
| mbed_official | 324:406fd2029f23 | 191 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 192 | |
| mbed_official | 324:406fd2029f23 | 193 | /*! |
| mbed_official | 324:406fd2029f23 | 194 | * @name Register LPTMR_CSR, field TFC[2] (RW) |
| mbed_official | 324:406fd2029f23 | 195 | * |
| mbed_official | 324:406fd2029f23 | 196 | * When clear, TFC configures the CNR to reset whenever TCF is set. When set, |
| mbed_official | 324:406fd2029f23 | 197 | * TFC configures the CNR to reset on overflow. TFC must be altered only when the |
| mbed_official | 324:406fd2029f23 | 198 | * LPTMR is disabled. |
| mbed_official | 324:406fd2029f23 | 199 | * |
| mbed_official | 324:406fd2029f23 | 200 | * Values: |
| mbed_official | 324:406fd2029f23 | 201 | * - 0 - CNR is reset whenever TCF is set. |
| mbed_official | 324:406fd2029f23 | 202 | * - 1 - CNR is reset on overflow. |
| mbed_official | 324:406fd2029f23 | 203 | */ |
| mbed_official | 324:406fd2029f23 | 204 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 205 | #define BP_LPTMR_CSR_TFC (2U) /*!< Bit position for LPTMR_CSR_TFC. */ |
| mbed_official | 324:406fd2029f23 | 206 | #define BM_LPTMR_CSR_TFC (0x00000004U) /*!< Bit mask for LPTMR_CSR_TFC. */ |
| mbed_official | 324:406fd2029f23 | 207 | #define BS_LPTMR_CSR_TFC (1U) /*!< Bit field size in bits for LPTMR_CSR_TFC. */ |
| mbed_official | 324:406fd2029f23 | 208 | |
| mbed_official | 324:406fd2029f23 | 209 | /*! @brief Read current value of the LPTMR_CSR_TFC field. */ |
| mbed_official | 324:406fd2029f23 | 210 | #define BR_LPTMR_CSR_TFC(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC)) |
| mbed_official | 324:406fd2029f23 | 211 | |
| mbed_official | 324:406fd2029f23 | 212 | /*! @brief Format value for bitfield LPTMR_CSR_TFC. */ |
| mbed_official | 324:406fd2029f23 | 213 | #define BF_LPTMR_CSR_TFC(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TFC) & BM_LPTMR_CSR_TFC) |
| mbed_official | 324:406fd2029f23 | 214 | |
| mbed_official | 324:406fd2029f23 | 215 | /*! @brief Set the TFC field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 216 | #define BW_LPTMR_CSR_TFC(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC) = (v)) |
| mbed_official | 324:406fd2029f23 | 217 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 218 | |
| mbed_official | 324:406fd2029f23 | 219 | /*! |
| mbed_official | 324:406fd2029f23 | 220 | * @name Register LPTMR_CSR, field TPP[3] (RW) |
| mbed_official | 324:406fd2029f23 | 221 | * |
| mbed_official | 324:406fd2029f23 | 222 | * Configures the polarity of the input source in Pulse Counter mode. TPP must |
| mbed_official | 324:406fd2029f23 | 223 | * be changed only when the LPTMR is disabled. |
| mbed_official | 324:406fd2029f23 | 224 | * |
| mbed_official | 324:406fd2029f23 | 225 | * Values: |
| mbed_official | 324:406fd2029f23 | 226 | * - 0 - Pulse Counter input source is active-high, and the CNR will increment |
| mbed_official | 324:406fd2029f23 | 227 | * on the rising-edge. |
| mbed_official | 324:406fd2029f23 | 228 | * - 1 - Pulse Counter input source is active-low, and the CNR will increment on |
| mbed_official | 324:406fd2029f23 | 229 | * the falling-edge. |
| mbed_official | 324:406fd2029f23 | 230 | */ |
| mbed_official | 324:406fd2029f23 | 231 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 232 | #define BP_LPTMR_CSR_TPP (3U) /*!< Bit position for LPTMR_CSR_TPP. */ |
| mbed_official | 324:406fd2029f23 | 233 | #define BM_LPTMR_CSR_TPP (0x00000008U) /*!< Bit mask for LPTMR_CSR_TPP. */ |
| mbed_official | 324:406fd2029f23 | 234 | #define BS_LPTMR_CSR_TPP (1U) /*!< Bit field size in bits for LPTMR_CSR_TPP. */ |
| mbed_official | 324:406fd2029f23 | 235 | |
| mbed_official | 324:406fd2029f23 | 236 | /*! @brief Read current value of the LPTMR_CSR_TPP field. */ |
| mbed_official | 324:406fd2029f23 | 237 | #define BR_LPTMR_CSR_TPP(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP)) |
| mbed_official | 324:406fd2029f23 | 238 | |
| mbed_official | 324:406fd2029f23 | 239 | /*! @brief Format value for bitfield LPTMR_CSR_TPP. */ |
| mbed_official | 324:406fd2029f23 | 240 | #define BF_LPTMR_CSR_TPP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPP) & BM_LPTMR_CSR_TPP) |
| mbed_official | 324:406fd2029f23 | 241 | |
| mbed_official | 324:406fd2029f23 | 242 | /*! @brief Set the TPP field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 243 | #define BW_LPTMR_CSR_TPP(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP) = (v)) |
| mbed_official | 324:406fd2029f23 | 244 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 245 | |
| mbed_official | 324:406fd2029f23 | 246 | /*! |
| mbed_official | 324:406fd2029f23 | 247 | * @name Register LPTMR_CSR, field TPS[5:4] (RW) |
| mbed_official | 324:406fd2029f23 | 248 | * |
| mbed_official | 324:406fd2029f23 | 249 | * Configures the input source to be used in Pulse Counter mode. TPS must be |
| mbed_official | 324:406fd2029f23 | 250 | * altered only when the LPTMR is disabled. The input connections vary by device. |
| mbed_official | 324:406fd2029f23 | 251 | * See the chip configuration details for information on the connections to these |
| mbed_official | 324:406fd2029f23 | 252 | * inputs. |
| mbed_official | 324:406fd2029f23 | 253 | * |
| mbed_official | 324:406fd2029f23 | 254 | * Values: |
| mbed_official | 324:406fd2029f23 | 255 | * - 00 - Pulse counter input 0 is selected. |
| mbed_official | 324:406fd2029f23 | 256 | * - 01 - Pulse counter input 1 is selected. |
| mbed_official | 324:406fd2029f23 | 257 | * - 10 - Pulse counter input 2 is selected. |
| mbed_official | 324:406fd2029f23 | 258 | * - 11 - Pulse counter input 3 is selected. |
| mbed_official | 324:406fd2029f23 | 259 | */ |
| mbed_official | 324:406fd2029f23 | 260 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 261 | #define BP_LPTMR_CSR_TPS (4U) /*!< Bit position for LPTMR_CSR_TPS. */ |
| mbed_official | 324:406fd2029f23 | 262 | #define BM_LPTMR_CSR_TPS (0x00000030U) /*!< Bit mask for LPTMR_CSR_TPS. */ |
| mbed_official | 324:406fd2029f23 | 263 | #define BS_LPTMR_CSR_TPS (2U) /*!< Bit field size in bits for LPTMR_CSR_TPS. */ |
| mbed_official | 324:406fd2029f23 | 264 | |
| mbed_official | 324:406fd2029f23 | 265 | /*! @brief Read current value of the LPTMR_CSR_TPS field. */ |
| mbed_official | 324:406fd2029f23 | 266 | #define BR_LPTMR_CSR_TPS(x) (HW_LPTMR_CSR(x).B.TPS) |
| mbed_official | 324:406fd2029f23 | 267 | |
| mbed_official | 324:406fd2029f23 | 268 | /*! @brief Format value for bitfield LPTMR_CSR_TPS. */ |
| mbed_official | 324:406fd2029f23 | 269 | #define BF_LPTMR_CSR_TPS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPS) & BM_LPTMR_CSR_TPS) |
| mbed_official | 324:406fd2029f23 | 270 | |
| mbed_official | 324:406fd2029f23 | 271 | /*! @brief Set the TPS field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 272 | #define BW_LPTMR_CSR_TPS(x, v) (HW_LPTMR_CSR_WR(x, (HW_LPTMR_CSR_RD(x) & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v))) |
| mbed_official | 324:406fd2029f23 | 273 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 274 | |
| mbed_official | 324:406fd2029f23 | 275 | /*! |
| mbed_official | 324:406fd2029f23 | 276 | * @name Register LPTMR_CSR, field TIE[6] (RW) |
| mbed_official | 324:406fd2029f23 | 277 | * |
| mbed_official | 324:406fd2029f23 | 278 | * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set. |
| mbed_official | 324:406fd2029f23 | 279 | * |
| mbed_official | 324:406fd2029f23 | 280 | * Values: |
| mbed_official | 324:406fd2029f23 | 281 | * - 0 - Timer interrupt disabled. |
| mbed_official | 324:406fd2029f23 | 282 | * - 1 - Timer interrupt enabled. |
| mbed_official | 324:406fd2029f23 | 283 | */ |
| mbed_official | 324:406fd2029f23 | 284 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 285 | #define BP_LPTMR_CSR_TIE (6U) /*!< Bit position for LPTMR_CSR_TIE. */ |
| mbed_official | 324:406fd2029f23 | 286 | #define BM_LPTMR_CSR_TIE (0x00000040U) /*!< Bit mask for LPTMR_CSR_TIE. */ |
| mbed_official | 324:406fd2029f23 | 287 | #define BS_LPTMR_CSR_TIE (1U) /*!< Bit field size in bits for LPTMR_CSR_TIE. */ |
| mbed_official | 324:406fd2029f23 | 288 | |
| mbed_official | 324:406fd2029f23 | 289 | /*! @brief Read current value of the LPTMR_CSR_TIE field. */ |
| mbed_official | 324:406fd2029f23 | 290 | #define BR_LPTMR_CSR_TIE(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE)) |
| mbed_official | 324:406fd2029f23 | 291 | |
| mbed_official | 324:406fd2029f23 | 292 | /*! @brief Format value for bitfield LPTMR_CSR_TIE. */ |
| mbed_official | 324:406fd2029f23 | 293 | #define BF_LPTMR_CSR_TIE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TIE) & BM_LPTMR_CSR_TIE) |
| mbed_official | 324:406fd2029f23 | 294 | |
| mbed_official | 324:406fd2029f23 | 295 | /*! @brief Set the TIE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 296 | #define BW_LPTMR_CSR_TIE(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE) = (v)) |
| mbed_official | 324:406fd2029f23 | 297 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 298 | |
| mbed_official | 324:406fd2029f23 | 299 | /*! |
| mbed_official | 324:406fd2029f23 | 300 | * @name Register LPTMR_CSR, field TCF[7] (W1C) |
| mbed_official | 324:406fd2029f23 | 301 | * |
| mbed_official | 324:406fd2029f23 | 302 | * TCF is set when the LPTMR is enabled and the CNR equals the CMR and |
| mbed_official | 324:406fd2029f23 | 303 | * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it. |
| mbed_official | 324:406fd2029f23 | 304 | * |
| mbed_official | 324:406fd2029f23 | 305 | * Values: |
| mbed_official | 324:406fd2029f23 | 306 | * - 0 - The value of CNR is not equal to CMR and increments. |
| mbed_official | 324:406fd2029f23 | 307 | * - 1 - The value of CNR is equal to CMR and increments. |
| mbed_official | 324:406fd2029f23 | 308 | */ |
| mbed_official | 324:406fd2029f23 | 309 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 310 | #define BP_LPTMR_CSR_TCF (7U) /*!< Bit position for LPTMR_CSR_TCF. */ |
| mbed_official | 324:406fd2029f23 | 311 | #define BM_LPTMR_CSR_TCF (0x00000080U) /*!< Bit mask for LPTMR_CSR_TCF. */ |
| mbed_official | 324:406fd2029f23 | 312 | #define BS_LPTMR_CSR_TCF (1U) /*!< Bit field size in bits for LPTMR_CSR_TCF. */ |
| mbed_official | 324:406fd2029f23 | 313 | |
| mbed_official | 324:406fd2029f23 | 314 | /*! @brief Read current value of the LPTMR_CSR_TCF field. */ |
| mbed_official | 324:406fd2029f23 | 315 | #define BR_LPTMR_CSR_TCF(x) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF)) |
| mbed_official | 324:406fd2029f23 | 316 | |
| mbed_official | 324:406fd2029f23 | 317 | /*! @brief Format value for bitfield LPTMR_CSR_TCF. */ |
| mbed_official | 324:406fd2029f23 | 318 | #define BF_LPTMR_CSR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TCF) & BM_LPTMR_CSR_TCF) |
| mbed_official | 324:406fd2029f23 | 319 | |
| mbed_official | 324:406fd2029f23 | 320 | /*! @brief Set the TCF field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 321 | #define BW_LPTMR_CSR_TCF(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF) = (v)) |
| mbed_official | 324:406fd2029f23 | 322 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 323 | |
| mbed_official | 324:406fd2029f23 | 324 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 325 | * HW_LPTMR_PSR - Low Power Timer Prescale Register |
| mbed_official | 324:406fd2029f23 | 326 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 327 | |
| mbed_official | 324:406fd2029f23 | 328 | /*! |
| mbed_official | 324:406fd2029f23 | 329 | * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW) |
| mbed_official | 324:406fd2029f23 | 330 | * |
| mbed_official | 324:406fd2029f23 | 331 | * Reset value: 0x00000000U |
| mbed_official | 324:406fd2029f23 | 332 | */ |
| mbed_official | 324:406fd2029f23 | 333 | typedef union _hw_lptmr_psr |
| mbed_official | 324:406fd2029f23 | 334 | { |
| mbed_official | 324:406fd2029f23 | 335 | uint32_t U; |
| mbed_official | 324:406fd2029f23 | 336 | struct _hw_lptmr_psr_bitfields |
| mbed_official | 324:406fd2029f23 | 337 | { |
| mbed_official | 324:406fd2029f23 | 338 | uint32_t PCS : 2; /*!< [1:0] Prescaler Clock Select */ |
| mbed_official | 324:406fd2029f23 | 339 | uint32_t PBYP : 1; /*!< [2] Prescaler Bypass */ |
| mbed_official | 324:406fd2029f23 | 340 | uint32_t PRESCALE : 4; /*!< [6:3] Prescale Value */ |
| mbed_official | 324:406fd2029f23 | 341 | uint32_t RESERVED0 : 25; /*!< [31:7] */ |
| mbed_official | 324:406fd2029f23 | 342 | } B; |
| mbed_official | 324:406fd2029f23 | 343 | } hw_lptmr_psr_t; |
| mbed_official | 324:406fd2029f23 | 344 | |
| mbed_official | 324:406fd2029f23 | 345 | /*! |
| mbed_official | 324:406fd2029f23 | 346 | * @name Constants and macros for entire LPTMR_PSR register |
| mbed_official | 324:406fd2029f23 | 347 | */ |
| mbed_official | 324:406fd2029f23 | 348 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 349 | #define HW_LPTMR_PSR_ADDR(x) ((x) + 0x4U) |
| mbed_official | 324:406fd2029f23 | 350 | |
| mbed_official | 324:406fd2029f23 | 351 | #define HW_LPTMR_PSR(x) (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 352 | #define HW_LPTMR_PSR_RD(x) (HW_LPTMR_PSR(x).U) |
| mbed_official | 324:406fd2029f23 | 353 | #define HW_LPTMR_PSR_WR(x, v) (HW_LPTMR_PSR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 354 | #define HW_LPTMR_PSR_SET(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 355 | #define HW_LPTMR_PSR_CLR(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 356 | #define HW_LPTMR_PSR_TOG(x, v) (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 357 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 358 | |
| mbed_official | 324:406fd2029f23 | 359 | /* |
| mbed_official | 324:406fd2029f23 | 360 | * Constants & macros for individual LPTMR_PSR bitfields |
| mbed_official | 324:406fd2029f23 | 361 | */ |
| mbed_official | 324:406fd2029f23 | 362 | |
| mbed_official | 324:406fd2029f23 | 363 | /*! |
| mbed_official | 324:406fd2029f23 | 364 | * @name Register LPTMR_PSR, field PCS[1:0] (RW) |
| mbed_official | 324:406fd2029f23 | 365 | * |
| mbed_official | 324:406fd2029f23 | 366 | * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must |
| mbed_official | 324:406fd2029f23 | 367 | * be altered only when the LPTMR is disabled. The clock connections vary by |
| mbed_official | 324:406fd2029f23 | 368 | * device. See the chip configuration details for information on the connections to |
| mbed_official | 324:406fd2029f23 | 369 | * these inputs. |
| mbed_official | 324:406fd2029f23 | 370 | * |
| mbed_official | 324:406fd2029f23 | 371 | * Values: |
| mbed_official | 324:406fd2029f23 | 372 | * - 00 - Prescaler/glitch filter clock 0 selected. |
| mbed_official | 324:406fd2029f23 | 373 | * - 01 - Prescaler/glitch filter clock 1 selected. |
| mbed_official | 324:406fd2029f23 | 374 | * - 10 - Prescaler/glitch filter clock 2 selected. |
| mbed_official | 324:406fd2029f23 | 375 | * - 11 - Prescaler/glitch filter clock 3 selected. |
| mbed_official | 324:406fd2029f23 | 376 | */ |
| mbed_official | 324:406fd2029f23 | 377 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 378 | #define BP_LPTMR_PSR_PCS (0U) /*!< Bit position for LPTMR_PSR_PCS. */ |
| mbed_official | 324:406fd2029f23 | 379 | #define BM_LPTMR_PSR_PCS (0x00000003U) /*!< Bit mask for LPTMR_PSR_PCS. */ |
| mbed_official | 324:406fd2029f23 | 380 | #define BS_LPTMR_PSR_PCS (2U) /*!< Bit field size in bits for LPTMR_PSR_PCS. */ |
| mbed_official | 324:406fd2029f23 | 381 | |
| mbed_official | 324:406fd2029f23 | 382 | /*! @brief Read current value of the LPTMR_PSR_PCS field. */ |
| mbed_official | 324:406fd2029f23 | 383 | #define BR_LPTMR_PSR_PCS(x) (HW_LPTMR_PSR(x).B.PCS) |
| mbed_official | 324:406fd2029f23 | 384 | |
| mbed_official | 324:406fd2029f23 | 385 | /*! @brief Format value for bitfield LPTMR_PSR_PCS. */ |
| mbed_official | 324:406fd2029f23 | 386 | #define BF_LPTMR_PSR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PCS) & BM_LPTMR_PSR_PCS) |
| mbed_official | 324:406fd2029f23 | 387 | |
| mbed_official | 324:406fd2029f23 | 388 | /*! @brief Set the PCS field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 389 | #define BW_LPTMR_PSR_PCS(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v))) |
| mbed_official | 324:406fd2029f23 | 390 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 391 | |
| mbed_official | 324:406fd2029f23 | 392 | /*! |
| mbed_official | 324:406fd2029f23 | 393 | * @name Register LPTMR_PSR, field PBYP[2] (RW) |
| mbed_official | 324:406fd2029f23 | 394 | * |
| mbed_official | 324:406fd2029f23 | 395 | * When PBYP is set, the selected prescaler clock in Time Counter mode or |
| mbed_official | 324:406fd2029f23 | 396 | * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is |
| mbed_official | 324:406fd2029f23 | 397 | * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP |
| mbed_official | 324:406fd2029f23 | 398 | * must be altered only when the LPTMR is disabled. |
| mbed_official | 324:406fd2029f23 | 399 | * |
| mbed_official | 324:406fd2029f23 | 400 | * Values: |
| mbed_official | 324:406fd2029f23 | 401 | * - 0 - Prescaler/glitch filter is enabled. |
| mbed_official | 324:406fd2029f23 | 402 | * - 1 - Prescaler/glitch filter is bypassed. |
| mbed_official | 324:406fd2029f23 | 403 | */ |
| mbed_official | 324:406fd2029f23 | 404 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 405 | #define BP_LPTMR_PSR_PBYP (2U) /*!< Bit position for LPTMR_PSR_PBYP. */ |
| mbed_official | 324:406fd2029f23 | 406 | #define BM_LPTMR_PSR_PBYP (0x00000004U) /*!< Bit mask for LPTMR_PSR_PBYP. */ |
| mbed_official | 324:406fd2029f23 | 407 | #define BS_LPTMR_PSR_PBYP (1U) /*!< Bit field size in bits for LPTMR_PSR_PBYP. */ |
| mbed_official | 324:406fd2029f23 | 408 | |
| mbed_official | 324:406fd2029f23 | 409 | /*! @brief Read current value of the LPTMR_PSR_PBYP field. */ |
| mbed_official | 324:406fd2029f23 | 410 | #define BR_LPTMR_PSR_PBYP(x) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP)) |
| mbed_official | 324:406fd2029f23 | 411 | |
| mbed_official | 324:406fd2029f23 | 412 | /*! @brief Format value for bitfield LPTMR_PSR_PBYP. */ |
| mbed_official | 324:406fd2029f23 | 413 | #define BF_LPTMR_PSR_PBYP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PBYP) & BM_LPTMR_PSR_PBYP) |
| mbed_official | 324:406fd2029f23 | 414 | |
| mbed_official | 324:406fd2029f23 | 415 | /*! @brief Set the PBYP field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 416 | #define BW_LPTMR_PSR_PBYP(x, v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP) = (v)) |
| mbed_official | 324:406fd2029f23 | 417 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 418 | |
| mbed_official | 324:406fd2029f23 | 419 | /*! |
| mbed_official | 324:406fd2029f23 | 420 | * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW) |
| mbed_official | 324:406fd2029f23 | 421 | * |
| mbed_official | 324:406fd2029f23 | 422 | * Configures the size of the Prescaler in Time Counter mode or width of the |
| mbed_official | 324:406fd2029f23 | 423 | * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR |
| mbed_official | 324:406fd2029f23 | 424 | * is disabled. |
| mbed_official | 324:406fd2029f23 | 425 | * |
| mbed_official | 324:406fd2029f23 | 426 | * Values: |
| mbed_official | 324:406fd2029f23 | 427 | * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not |
| mbed_official | 324:406fd2029f23 | 428 | * support this configuration. |
| mbed_official | 324:406fd2029f23 | 429 | * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes |
| mbed_official | 324:406fd2029f23 | 430 | * change on input pin after 2 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 431 | * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes |
| mbed_official | 324:406fd2029f23 | 432 | * change on input pin after 4 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 433 | * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter |
| mbed_official | 324:406fd2029f23 | 434 | * recognizes change on input pin after 8 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 435 | * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter |
| mbed_official | 324:406fd2029f23 | 436 | * recognizes change on input pin after 16 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 437 | * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter |
| mbed_official | 324:406fd2029f23 | 438 | * recognizes change on input pin after 32 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 439 | * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter |
| mbed_official | 324:406fd2029f23 | 440 | * recognizes change on input pin after 64 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 441 | * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter |
| mbed_official | 324:406fd2029f23 | 442 | * recognizes change on input pin after 128 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 443 | * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter |
| mbed_official | 324:406fd2029f23 | 444 | * recognizes change on input pin after 256 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 445 | * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter |
| mbed_official | 324:406fd2029f23 | 446 | * recognizes change on input pin after 512 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 447 | * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter |
| mbed_official | 324:406fd2029f23 | 448 | * recognizes change on input pin after 1024 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 449 | * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter |
| mbed_official | 324:406fd2029f23 | 450 | * recognizes change on input pin after 2048 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 451 | * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter |
| mbed_official | 324:406fd2029f23 | 452 | * recognizes change on input pin after 4096 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 453 | * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter |
| mbed_official | 324:406fd2029f23 | 454 | * recognizes change on input pin after 8192 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 455 | * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter |
| mbed_official | 324:406fd2029f23 | 456 | * recognizes change on input pin after 16,384 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 457 | * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter |
| mbed_official | 324:406fd2029f23 | 458 | * recognizes change on input pin after 32,768 rising clock edges. |
| mbed_official | 324:406fd2029f23 | 459 | */ |
| mbed_official | 324:406fd2029f23 | 460 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 461 | #define BP_LPTMR_PSR_PRESCALE (3U) /*!< Bit position for LPTMR_PSR_PRESCALE. */ |
| mbed_official | 324:406fd2029f23 | 462 | #define BM_LPTMR_PSR_PRESCALE (0x00000078U) /*!< Bit mask for LPTMR_PSR_PRESCALE. */ |
| mbed_official | 324:406fd2029f23 | 463 | #define BS_LPTMR_PSR_PRESCALE (4U) /*!< Bit field size in bits for LPTMR_PSR_PRESCALE. */ |
| mbed_official | 324:406fd2029f23 | 464 | |
| mbed_official | 324:406fd2029f23 | 465 | /*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */ |
| mbed_official | 324:406fd2029f23 | 466 | #define BR_LPTMR_PSR_PRESCALE(x) (HW_LPTMR_PSR(x).B.PRESCALE) |
| mbed_official | 324:406fd2029f23 | 467 | |
| mbed_official | 324:406fd2029f23 | 468 | /*! @brief Format value for bitfield LPTMR_PSR_PRESCALE. */ |
| mbed_official | 324:406fd2029f23 | 469 | #define BF_LPTMR_PSR_PRESCALE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PRESCALE) & BM_LPTMR_PSR_PRESCALE) |
| mbed_official | 324:406fd2029f23 | 470 | |
| mbed_official | 324:406fd2029f23 | 471 | /*! @brief Set the PRESCALE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 472 | #define BW_LPTMR_PSR_PRESCALE(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v))) |
| mbed_official | 324:406fd2029f23 | 473 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 474 | |
| mbed_official | 324:406fd2029f23 | 475 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 476 | * HW_LPTMR_CMR - Low Power Timer Compare Register |
| mbed_official | 324:406fd2029f23 | 477 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 478 | |
| mbed_official | 324:406fd2029f23 | 479 | /*! |
| mbed_official | 324:406fd2029f23 | 480 | * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW) |
| mbed_official | 324:406fd2029f23 | 481 | * |
| mbed_official | 324:406fd2029f23 | 482 | * Reset value: 0x00000000U |
| mbed_official | 324:406fd2029f23 | 483 | */ |
| mbed_official | 324:406fd2029f23 | 484 | typedef union _hw_lptmr_cmr |
| mbed_official | 324:406fd2029f23 | 485 | { |
| mbed_official | 324:406fd2029f23 | 486 | uint32_t U; |
| mbed_official | 324:406fd2029f23 | 487 | struct _hw_lptmr_cmr_bitfields |
| mbed_official | 324:406fd2029f23 | 488 | { |
| mbed_official | 324:406fd2029f23 | 489 | uint32_t COMPARE : 16; /*!< [15:0] Compare Value */ |
| mbed_official | 324:406fd2029f23 | 490 | uint32_t RESERVED0 : 16; /*!< [31:16] */ |
| mbed_official | 324:406fd2029f23 | 491 | } B; |
| mbed_official | 324:406fd2029f23 | 492 | } hw_lptmr_cmr_t; |
| mbed_official | 324:406fd2029f23 | 493 | |
| mbed_official | 324:406fd2029f23 | 494 | /*! |
| mbed_official | 324:406fd2029f23 | 495 | * @name Constants and macros for entire LPTMR_CMR register |
| mbed_official | 324:406fd2029f23 | 496 | */ |
| mbed_official | 324:406fd2029f23 | 497 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 498 | #define HW_LPTMR_CMR_ADDR(x) ((x) + 0x8U) |
| mbed_official | 324:406fd2029f23 | 499 | |
| mbed_official | 324:406fd2029f23 | 500 | #define HW_LPTMR_CMR(x) (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 501 | #define HW_LPTMR_CMR_RD(x) (HW_LPTMR_CMR(x).U) |
| mbed_official | 324:406fd2029f23 | 502 | #define HW_LPTMR_CMR_WR(x, v) (HW_LPTMR_CMR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 503 | #define HW_LPTMR_CMR_SET(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 504 | #define HW_LPTMR_CMR_CLR(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 505 | #define HW_LPTMR_CMR_TOG(x, v) (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 506 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 507 | |
| mbed_official | 324:406fd2029f23 | 508 | /* |
| mbed_official | 324:406fd2029f23 | 509 | * Constants & macros for individual LPTMR_CMR bitfields |
| mbed_official | 324:406fd2029f23 | 510 | */ |
| mbed_official | 324:406fd2029f23 | 511 | |
| mbed_official | 324:406fd2029f23 | 512 | /*! |
| mbed_official | 324:406fd2029f23 | 513 | * @name Register LPTMR_CMR, field COMPARE[15:0] (RW) |
| mbed_official | 324:406fd2029f23 | 514 | * |
| mbed_official | 324:406fd2029f23 | 515 | * When the LPTMR is enabled and the CNR equals the value in the CMR and |
| mbed_official | 324:406fd2029f23 | 516 | * increments, TCF is set and the hardware trigger asserts until the next time the CNR |
| mbed_official | 324:406fd2029f23 | 517 | * increments. If the CMR is 0, the hardware trigger will remain asserted until |
| mbed_official | 324:406fd2029f23 | 518 | * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only |
| mbed_official | 324:406fd2029f23 | 519 | * when TCF is set. |
| mbed_official | 324:406fd2029f23 | 520 | */ |
| mbed_official | 324:406fd2029f23 | 521 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 522 | #define BP_LPTMR_CMR_COMPARE (0U) /*!< Bit position for LPTMR_CMR_COMPARE. */ |
| mbed_official | 324:406fd2029f23 | 523 | #define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) /*!< Bit mask for LPTMR_CMR_COMPARE. */ |
| mbed_official | 324:406fd2029f23 | 524 | #define BS_LPTMR_CMR_COMPARE (16U) /*!< Bit field size in bits for LPTMR_CMR_COMPARE. */ |
| mbed_official | 324:406fd2029f23 | 525 | |
| mbed_official | 324:406fd2029f23 | 526 | /*! @brief Read current value of the LPTMR_CMR_COMPARE field. */ |
| mbed_official | 324:406fd2029f23 | 527 | #define BR_LPTMR_CMR_COMPARE(x) (HW_LPTMR_CMR(x).B.COMPARE) |
| mbed_official | 324:406fd2029f23 | 528 | |
| mbed_official | 324:406fd2029f23 | 529 | /*! @brief Format value for bitfield LPTMR_CMR_COMPARE. */ |
| mbed_official | 324:406fd2029f23 | 530 | #define BF_LPTMR_CMR_COMPARE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CMR_COMPARE) & BM_LPTMR_CMR_COMPARE) |
| mbed_official | 324:406fd2029f23 | 531 | |
| mbed_official | 324:406fd2029f23 | 532 | /*! @brief Set the COMPARE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 533 | #define BW_LPTMR_CMR_COMPARE(x, v) (HW_LPTMR_CMR_WR(x, (HW_LPTMR_CMR_RD(x) & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v))) |
| mbed_official | 324:406fd2029f23 | 534 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 535 | |
| mbed_official | 324:406fd2029f23 | 536 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 537 | * HW_LPTMR_CNR - Low Power Timer Counter Register |
| mbed_official | 324:406fd2029f23 | 538 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 539 | |
| mbed_official | 324:406fd2029f23 | 540 | /*! |
| mbed_official | 324:406fd2029f23 | 541 | * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW) |
| mbed_official | 324:406fd2029f23 | 542 | * |
| mbed_official | 324:406fd2029f23 | 543 | * Reset value: 0x00000000U |
| mbed_official | 324:406fd2029f23 | 544 | */ |
| mbed_official | 324:406fd2029f23 | 545 | typedef union _hw_lptmr_cnr |
| mbed_official | 324:406fd2029f23 | 546 | { |
| mbed_official | 324:406fd2029f23 | 547 | uint32_t U; |
| mbed_official | 324:406fd2029f23 | 548 | struct _hw_lptmr_cnr_bitfields |
| mbed_official | 324:406fd2029f23 | 549 | { |
| mbed_official | 324:406fd2029f23 | 550 | uint32_t COUNTER : 16; /*!< [15:0] Counter Value */ |
| mbed_official | 324:406fd2029f23 | 551 | uint32_t RESERVED0 : 16; /*!< [31:16] */ |
| mbed_official | 324:406fd2029f23 | 552 | } B; |
| mbed_official | 324:406fd2029f23 | 553 | } hw_lptmr_cnr_t; |
| mbed_official | 324:406fd2029f23 | 554 | |
| mbed_official | 324:406fd2029f23 | 555 | /*! |
| mbed_official | 324:406fd2029f23 | 556 | * @name Constants and macros for entire LPTMR_CNR register |
| mbed_official | 324:406fd2029f23 | 557 | */ |
| mbed_official | 324:406fd2029f23 | 558 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 559 | #define HW_LPTMR_CNR_ADDR(x) ((x) + 0xCU) |
| mbed_official | 324:406fd2029f23 | 560 | |
| mbed_official | 324:406fd2029f23 | 561 | #define HW_LPTMR_CNR(x) (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 562 | #define HW_LPTMR_CNR_RD(x) (HW_LPTMR_CNR(x).U) |
| mbed_official | 324:406fd2029f23 | 563 | #define HW_LPTMR_CNR_WR(x, v) (HW_LPTMR_CNR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 564 | #define HW_LPTMR_CNR_SET(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 565 | #define HW_LPTMR_CNR_CLR(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 566 | #define HW_LPTMR_CNR_TOG(x, v) (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 567 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 568 | |
| mbed_official | 324:406fd2029f23 | 569 | /* |
| mbed_official | 324:406fd2029f23 | 570 | * Constants & macros for individual LPTMR_CNR bitfields |
| mbed_official | 324:406fd2029f23 | 571 | */ |
| mbed_official | 324:406fd2029f23 | 572 | |
| mbed_official | 324:406fd2029f23 | 573 | /*! |
| mbed_official | 324:406fd2029f23 | 574 | * @name Register LPTMR_CNR, field COUNTER[15:0] (RW) |
| mbed_official | 324:406fd2029f23 | 575 | */ |
| mbed_official | 324:406fd2029f23 | 576 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 577 | #define BP_LPTMR_CNR_COUNTER (0U) /*!< Bit position for LPTMR_CNR_COUNTER. */ |
| mbed_official | 324:406fd2029f23 | 578 | #define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) /*!< Bit mask for LPTMR_CNR_COUNTER. */ |
| mbed_official | 324:406fd2029f23 | 579 | #define BS_LPTMR_CNR_COUNTER (16U) /*!< Bit field size in bits for LPTMR_CNR_COUNTER. */ |
| mbed_official | 324:406fd2029f23 | 580 | |
| mbed_official | 324:406fd2029f23 | 581 | /*! @brief Read current value of the LPTMR_CNR_COUNTER field. */ |
| mbed_official | 324:406fd2029f23 | 582 | #define BR_LPTMR_CNR_COUNTER(x) (HW_LPTMR_CNR(x).B.COUNTER) |
| mbed_official | 324:406fd2029f23 | 583 | |
| mbed_official | 324:406fd2029f23 | 584 | /*! @brief Format value for bitfield LPTMR_CNR_COUNTER. */ |
| mbed_official | 324:406fd2029f23 | 585 | #define BF_LPTMR_CNR_COUNTER(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CNR_COUNTER) & BM_LPTMR_CNR_COUNTER) |
| mbed_official | 324:406fd2029f23 | 586 | |
| mbed_official | 324:406fd2029f23 | 587 | /*! @brief Set the COUNTER field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 588 | #define BW_LPTMR_CNR_COUNTER(x, v) (HW_LPTMR_CNR_WR(x, (HW_LPTMR_CNR_RD(x) & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v))) |
| mbed_official | 324:406fd2029f23 | 589 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 590 | |
| mbed_official | 324:406fd2029f23 | 591 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 592 | * hw_lptmr_t - module struct |
| mbed_official | 324:406fd2029f23 | 593 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 594 | /*! |
| mbed_official | 324:406fd2029f23 | 595 | * @brief All LPTMR module registers. |
| mbed_official | 324:406fd2029f23 | 596 | */ |
| mbed_official | 324:406fd2029f23 | 597 | #pragma pack(1) |
| mbed_official | 324:406fd2029f23 | 598 | typedef struct _hw_lptmr |
| mbed_official | 324:406fd2029f23 | 599 | { |
| mbed_official | 324:406fd2029f23 | 600 | __IO hw_lptmr_csr_t CSR; /*!< [0x0] Low Power Timer Control Status Register */ |
| mbed_official | 324:406fd2029f23 | 601 | __IO hw_lptmr_psr_t PSR; /*!< [0x4] Low Power Timer Prescale Register */ |
| mbed_official | 324:406fd2029f23 | 602 | __IO hw_lptmr_cmr_t CMR; /*!< [0x8] Low Power Timer Compare Register */ |
| mbed_official | 324:406fd2029f23 | 603 | __IO hw_lptmr_cnr_t CNR; /*!< [0xC] Low Power Timer Counter Register */ |
| mbed_official | 324:406fd2029f23 | 604 | } hw_lptmr_t; |
| mbed_official | 324:406fd2029f23 | 605 | #pragma pack() |
| mbed_official | 324:406fd2029f23 | 606 | |
| mbed_official | 324:406fd2029f23 | 607 | /*! @brief Macro to access all LPTMR registers. */ |
| mbed_official | 324:406fd2029f23 | 608 | /*! @param x LPTMR module instance base address. */ |
| mbed_official | 324:406fd2029f23 | 609 | /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
| mbed_official | 324:406fd2029f23 | 610 | * use the '&' operator, like <code>&HW_LPTMR(LPTMR0_BASE)</code>. */ |
| mbed_official | 324:406fd2029f23 | 611 | #define HW_LPTMR(x) (*(hw_lptmr_t *)(x)) |
| mbed_official | 324:406fd2029f23 | 612 | |
| mbed_official | 324:406fd2029f23 | 613 | #endif /* __HW_LPTMR_REGISTERS_H__ */ |
| mbed_official | 324:406fd2029f23 | 614 | /* EOF */ |