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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Parent:
82:6473597d706e 
Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Version: rev. 1.0, 2014-05-14
Kojto 90:cb3d968589d8 4 ** Build: b140515
Kojto 90:cb3d968589d8 5 **
Kojto 90:cb3d968589d8 6 ** Abstract:
Kojto 90:cb3d968589d8 7 ** Chip specific module features.
Kojto 90:cb3d968589d8 8 **
Kojto 90:cb3d968589d8 9 ** Copyright: 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 10 ** All rights reserved.
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 13 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 16 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 19 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 20 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 21 **
Kojto 90:cb3d968589d8 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 23 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 24 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 25 **
Kojto 90:cb3d968589d8 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 36 **
Kojto 90:cb3d968589d8 37 ** http: www.freescale.com
Kojto 90:cb3d968589d8 38 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 39 **
Kojto 90:cb3d968589d8 40 ** Revisions:
Kojto 90:cb3d968589d8 41 ** - rev. 1.0 (2014-05-14)
Kojto 90:cb3d968589d8 42 ** Customer release.
Kojto 90:cb3d968589d8 43 **
Kojto 90:cb3d968589d8 44 ** ###################################################################
Kojto 90:cb3d968589d8 45 */
Kojto 90:cb3d968589d8 46
bogdanm 82:6473597d706e 47 #if !defined(__FSL_PORT_FEATURES_H__)
bogdanm 82:6473597d706e 48 #define __FSL_PORT_FEATURES_H__
bogdanm 82:6473597d706e 49
Kojto 90:cb3d968589d8 50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
Kojto 90:cb3d968589d8 51 defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \
Kojto 90:cb3d968589d8 52 defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
Kojto 90:cb3d968589d8 53 defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \
Kojto 90:cb3d968589d8 54 defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
Kojto 90:cb3d968589d8 55 defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
Kojto 90:cb3d968589d8 56 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
Kojto 90:cb3d968589d8 57 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
Kojto 90:cb3d968589d8 58 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
Kojto 90:cb3d968589d8 59 defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
Kojto 90:cb3d968589d8 60 defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
Kojto 90:cb3d968589d8 61 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
Kojto 90:cb3d968589d8 62 defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
Kojto 90:cb3d968589d8 63 defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
Kojto 90:cb3d968589d8 64 defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \
Kojto 90:cb3d968589d8 65 defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
bogdanm 82:6473597d706e 66 defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
Kojto 90:cb3d968589d8 67 defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
Kojto 90:cb3d968589d8 68 defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \
Kojto 90:cb3d968589d8 69 defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
Kojto 90:cb3d968589d8 70 defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
Kojto 90:cb3d968589d8 71 defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \
Kojto 90:cb3d968589d8 72 defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \
Kojto 90:cb3d968589d8 73 defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \
Kojto 90:cb3d968589d8 74 defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
Kojto 90:cb3d968589d8 75 /* @brief Has control lock (register bit PCR[LK]). */
bogdanm 82:6473597d706e 76 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
Kojto 90:cb3d968589d8 77 /* @brief Has open drain control (register bit PCR[ODE]). */
bogdanm 82:6473597d706e 78 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
Kojto 90:cb3d968589d8 79 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
bogdanm 82:6473597d706e 80 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
bogdanm 82:6473597d706e 81 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 82 ((x) == 0 ? (0) : \
bogdanm 82:6473597d706e 83 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 84 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 85 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 86 ((x) == 4 ? (0) : (-1))))))
Kojto 90:cb3d968589d8 87 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
bogdanm 82:6473597d706e 88 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
Kojto 90:cb3d968589d8 89 /* @brief Has pull resistor selection (register bit PCR[PS]). */
bogdanm 82:6473597d706e 90 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
Kojto 90:cb3d968589d8 91 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
bogdanm 82:6473597d706e 92 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
Kojto 90:cb3d968589d8 93 /* @brief Has slew rate control (register bit PCR[SRE]). */
bogdanm 82:6473597d706e 94 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
Kojto 90:cb3d968589d8 95 /* @brief Has passive filter (register bit field PCR[PFE]). */
bogdanm 82:6473597d706e 96 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 97 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 98 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 99 ((x) == 1 ? (1) : \
bogdanm 82:6473597d706e 100 ((x) == 2 ? (1) : \
bogdanm 82:6473597d706e 101 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 102 ((x) == 4 ? (1) : (-1))))))
Kojto 90:cb3d968589d8 103 /* @brief Has drive strength control (register bit PCR[DSE]). */
bogdanm 82:6473597d706e 104 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
Kojto 90:cb3d968589d8 105 /* @brief Has separate drive strength register (HDRVE). */
bogdanm 82:6473597d706e 106 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
Kojto 90:cb3d968589d8 107 /* @brief Has glitch filter (register IOFLT). */
bogdanm 82:6473597d706e 108 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
bogdanm 82:6473597d706e 109 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
bogdanm 82:6473597d706e 110 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
Kojto 90:cb3d968589d8 111 /* @brief Has control lock (register bit PCR[LK]). */
bogdanm 82:6473597d706e 112 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
Kojto 90:cb3d968589d8 113 /* @brief Has open drain control (register bit PCR[ODE]). */
bogdanm 82:6473597d706e 114 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
Kojto 90:cb3d968589d8 115 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
bogdanm 82:6473597d706e 116 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
bogdanm 82:6473597d706e 117 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 118 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 119 ((x) == 1 ? (1) : \
bogdanm 82:6473597d706e 120 ((x) == 2 ? (1) : \
bogdanm 82:6473597d706e 121 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 122 ((x) == 4 ? (1) : \
bogdanm 82:6473597d706e 123 ((x) == 5 ? (1) : (-1)))))))
Kojto 90:cb3d968589d8 124 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
bogdanm 82:6473597d706e 125 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
Kojto 90:cb3d968589d8 126 /* @brief Has pull resistor selection (register bit PCR[PS]). */
bogdanm 82:6473597d706e 127 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
Kojto 90:cb3d968589d8 128 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
bogdanm 82:6473597d706e 129 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
Kojto 90:cb3d968589d8 130 /* @brief Has slew rate control (register bit PCR[SRE]). */
bogdanm 82:6473597d706e 131 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
Kojto 90:cb3d968589d8 132 /* @brief Has passive filter (register bit field PCR[PFE]). */
bogdanm 82:6473597d706e 133 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 134 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 135 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 136 ((x) == 1 ? (1) : \
bogdanm 82:6473597d706e 137 ((x) == 2 ? (1) : \
bogdanm 82:6473597d706e 138 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 139 ((x) == 4 ? (1) : \
bogdanm 82:6473597d706e 140 ((x) == 5 ? (1) : (-1)))))))
Kojto 90:cb3d968589d8 141 /* @brief Has drive strength control (register bit PCR[DSE]). */
bogdanm 82:6473597d706e 142 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
Kojto 90:cb3d968589d8 143 /* @brief Has separate drive strength register (HDRVE). */
bogdanm 82:6473597d706e 144 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
Kojto 90:cb3d968589d8 145 /* @brief Has glitch filter (register IOFLT). */
bogdanm 82:6473597d706e 146 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
Kojto 90:cb3d968589d8 147 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
Kojto 90:cb3d968589d8 148 defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
Kojto 90:cb3d968589d8 149 /* @brief Has control lock (register bit PCR[LK]). */
bogdanm 82:6473597d706e 150 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
Kojto 90:cb3d968589d8 151 /* @brief Has open drain control (register bit PCR[ODE]). */
bogdanm 82:6473597d706e 152 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
Kojto 90:cb3d968589d8 153 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
bogdanm 82:6473597d706e 154 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
bogdanm 82:6473597d706e 155 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 156 ((x) == 0 ? (0) : \
bogdanm 82:6473597d706e 157 ((x) == 1 ? (0) : (-1)))
Kojto 90:cb3d968589d8 158 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
Kojto 90:cb3d968589d8 159 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0)
Kojto 90:cb3d968589d8 160 /* @brief Has pull resistor selection (register bit PCR[PS]). */
bogdanm 82:6473597d706e 161 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
Kojto 90:cb3d968589d8 162 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
bogdanm 82:6473597d706e 163 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
Kojto 90:cb3d968589d8 164 /* @brief Has slew rate control (register bit PCR[SRE]). */
bogdanm 82:6473597d706e 165 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
Kojto 90:cb3d968589d8 166 /* @brief Has passive filter (register bit field PCR[PFE]). */
bogdanm 82:6473597d706e 167 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 168 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 169 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 170 ((x) == 1 ? (1) : (-1)))
Kojto 90:cb3d968589d8 171 /* @brief Has drive strength control (register bit PCR[DSE]). */
bogdanm 82:6473597d706e 172 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
Kojto 90:cb3d968589d8 173 /* @brief Has separate drive strength register (HDRVE). */
bogdanm 82:6473597d706e 174 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
Kojto 90:cb3d968589d8 175 /* @brief Has glitch filter (register IOFLT). */
bogdanm 82:6473597d706e 176 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
Kojto 90:cb3d968589d8 177 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
Kojto 90:cb3d968589d8 178 defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
Kojto 90:cb3d968589d8 179 defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
Kojto 90:cb3d968589d8 180 /* @brief Has control lock (register bit PCR[LK]). */
bogdanm 82:6473597d706e 181 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
Kojto 90:cb3d968589d8 182 /* @brief Has open drain control (register bit PCR[ODE]). */
bogdanm 82:6473597d706e 183 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
Kojto 90:cb3d968589d8 184 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
Kojto 90:cb3d968589d8 185 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
Kojto 90:cb3d968589d8 186 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
Kojto 90:cb3d968589d8 187 ((x) == 0 ? (0) : \
Kojto 90:cb3d968589d8 188 ((x) == 1 ? (0) : (-1)))
Kojto 90:cb3d968589d8 189 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
Kojto 90:cb3d968589d8 190 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
Kojto 90:cb3d968589d8 191 /* @brief Has pull resistor selection (register bit PCR[PS]). */
Kojto 90:cb3d968589d8 192 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
Kojto 90:cb3d968589d8 193 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
Kojto 90:cb3d968589d8 194 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
Kojto 90:cb3d968589d8 195 /* @brief Has slew rate control (register bit PCR[SRE]). */
Kojto 90:cb3d968589d8 196 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
Kojto 90:cb3d968589d8 197 /* @brief Has passive filter (register bit field PCR[PFE]). */
Kojto 90:cb3d968589d8 198 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
Kojto 90:cb3d968589d8 199 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
Kojto 90:cb3d968589d8 200 ((x) == 0 ? (1) : \
Kojto 90:cb3d968589d8 201 ((x) == 1 ? (1) : (-1)))
Kojto 90:cb3d968589d8 202 /* @brief Has drive strength control (register bit PCR[DSE]). */
Kojto 90:cb3d968589d8 203 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
Kojto 90:cb3d968589d8 204 /* @brief Has separate drive strength register (HDRVE). */
Kojto 90:cb3d968589d8 205 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
Kojto 90:cb3d968589d8 206 /* @brief Has glitch filter (register IOFLT). */
Kojto 90:cb3d968589d8 207 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
Kojto 90:cb3d968589d8 208 #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
Kojto 90:cb3d968589d8 209 defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
Kojto 90:cb3d968589d8 210 defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
Kojto 90:cb3d968589d8 211 defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
Kojto 90:cb3d968589d8 212 defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
Kojto 90:cb3d968589d8 213 defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
Kojto 90:cb3d968589d8 214 defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
Kojto 90:cb3d968589d8 215 defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
Kojto 90:cb3d968589d8 216 defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
Kojto 90:cb3d968589d8 217 /* @brief Has control lock (register bit PCR[LK]). */
Kojto 90:cb3d968589d8 218 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
Kojto 90:cb3d968589d8 219 /* @brief Has open drain control (register bit PCR[ODE]). */
Kojto 90:cb3d968589d8 220 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
Kojto 90:cb3d968589d8 221 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
bogdanm 82:6473597d706e 222 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
bogdanm 82:6473597d706e 223 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 224 ((x) == 0 ? (0) : \
bogdanm 82:6473597d706e 225 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 226 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 227 ((x) == 3 ? (0) : \
bogdanm 82:6473597d706e 228 ((x) == 4 ? (0) : (-1))))))
Kojto 90:cb3d968589d8 229 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
bogdanm 82:6473597d706e 230 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
Kojto 90:cb3d968589d8 231 /* @brief Has pull resistor selection (register bit PCR[PS]). */
Kojto 90:cb3d968589d8 232 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
Kojto 90:cb3d968589d8 233 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
Kojto 90:cb3d968589d8 234 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
Kojto 90:cb3d968589d8 235 /* @brief Has slew rate control (register bit PCR[SRE]). */
Kojto 90:cb3d968589d8 236 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
Kojto 90:cb3d968589d8 237 /* @brief Has passive filter (register bit field PCR[PFE]). */
Kojto 90:cb3d968589d8 238 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
Kojto 90:cb3d968589d8 239 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
Kojto 90:cb3d968589d8 240 ((x) == 0 ? (1) : \
Kojto 90:cb3d968589d8 241 ((x) == 1 ? (1) : \
Kojto 90:cb3d968589d8 242 ((x) == 2 ? (1) : \
Kojto 90:cb3d968589d8 243 ((x) == 3 ? (1) : \
Kojto 90:cb3d968589d8 244 ((x) == 4 ? (1) : (-1))))))
Kojto 90:cb3d968589d8 245 /* @brief Has drive strength control (register bit PCR[DSE]). */
Kojto 90:cb3d968589d8 246 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
Kojto 90:cb3d968589d8 247 /* @brief Has separate drive strength register (HDRVE). */
Kojto 90:cb3d968589d8 248 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
Kojto 90:cb3d968589d8 249 /* @brief Has glitch filter (register IOFLT). */
Kojto 90:cb3d968589d8 250 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
Kojto 90:cb3d968589d8 251 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
Kojto 90:cb3d968589d8 252 defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
Kojto 90:cb3d968589d8 253 defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
Kojto 90:cb3d968589d8 254 /* @brief Has control lock (register bit PCR[LK]). */
Kojto 90:cb3d968589d8 255 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
Kojto 90:cb3d968589d8 256 /* @brief Has open drain control (register bit PCR[ODE]). */
Kojto 90:cb3d968589d8 257 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
Kojto 90:cb3d968589d8 258 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
Kojto 90:cb3d968589d8 259 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
Kojto 90:cb3d968589d8 260 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
Kojto 90:cb3d968589d8 261 ((x) == 0 ? (0) : \
Kojto 90:cb3d968589d8 262 ((x) == 1 ? (0) : \
Kojto 90:cb3d968589d8 263 ((x) == 2 ? (0) : \
Kojto 90:cb3d968589d8 264 ((x) == 3 ? (0) : \
Kojto 90:cb3d968589d8 265 ((x) == 4 ? (0) : (-1))))))
Kojto 90:cb3d968589d8 266 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
Kojto 90:cb3d968589d8 267 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
Kojto 90:cb3d968589d8 268 /* @brief Has pull resistor selection (register bit PCR[PS]). */
bogdanm 82:6473597d706e 269 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0)
Kojto 90:cb3d968589d8 270 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
bogdanm 82:6473597d706e 271 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
Kojto 90:cb3d968589d8 272 /* @brief Has slew rate control (register bit PCR[SRE]). */
bogdanm 82:6473597d706e 273 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
Kojto 90:cb3d968589d8 274 /* @brief Has passive filter (register bit field PCR[PFE]). */
bogdanm 82:6473597d706e 275 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 276 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 277 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 278 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 279 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 280 ((x) == 3 ? (0) : \
bogdanm 82:6473597d706e 281 ((x) == 4 ? (0) : (-1))))))
Kojto 90:cb3d968589d8 282 /* @brief Has drive strength control (register bit PCR[DSE]). */
bogdanm 82:6473597d706e 283 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
Kojto 90:cb3d968589d8 284 /* @brief Has separate drive strength register (HDRVE). */
bogdanm 82:6473597d706e 285 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
Kojto 90:cb3d968589d8 286 /* @brief Has glitch filter (register IOFLT). */
bogdanm 82:6473597d706e 287 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
Kojto 90:cb3d968589d8 288 #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \
Kojto 90:cb3d968589d8 289 defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
Kojto 90:cb3d968589d8 290 defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
Kojto 90:cb3d968589d8 291 /* @brief Has control lock (register bit PCR[LK]). */
bogdanm 82:6473597d706e 292 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
Kojto 90:cb3d968589d8 293 /* @brief Has open drain control (register bit PCR[ODE]). */
bogdanm 82:6473597d706e 294 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
Kojto 90:cb3d968589d8 295 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
bogdanm 82:6473597d706e 296 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
bogdanm 82:6473597d706e 297 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 298 ((x) == 0 ? (0) : \
bogdanm 82:6473597d706e 299 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 300 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 301 ((x) == 3 ? (0) : \
bogdanm 82:6473597d706e 302 ((x) == 4 ? (0) : (-1))))))
Kojto 90:cb3d968589d8 303 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
bogdanm 82:6473597d706e 304 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
Kojto 90:cb3d968589d8 305 /* @brief Has pull resistor selection (register bit PCR[PS]). */
bogdanm 82:6473597d706e 306 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
Kojto 90:cb3d968589d8 307 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
bogdanm 82:6473597d706e 308 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
Kojto 90:cb3d968589d8 309 /* @brief Has slew rate control (register bit PCR[SRE]). */
bogdanm 82:6473597d706e 310 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
Kojto 90:cb3d968589d8 311 /* @brief Has passive filter (register bit field PCR[PFE]). */
bogdanm 82:6473597d706e 312 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 313 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 314 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 315 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 316 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 317 ((x) == 3 ? (0) : \
bogdanm 82:6473597d706e 318 ((x) == 4 ? (0) : (-1))))))
Kojto 90:cb3d968589d8 319 /* @brief Has drive strength control (register bit PCR[DSE]). */
bogdanm 82:6473597d706e 320 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
Kojto 90:cb3d968589d8 321 /* @brief Has separate drive strength register (HDRVE). */
bogdanm 82:6473597d706e 322 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
Kojto 90:cb3d968589d8 323 /* @brief Has glitch filter (register IOFLT). */
bogdanm 82:6473597d706e 324 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
bogdanm 82:6473597d706e 325 #else
bogdanm 82:6473597d706e 326 #error "No valid CPU defined!"
bogdanm 82:6473597d706e 327 #endif
bogdanm 82:6473597d706e 328
Kojto 90:cb3d968589d8 329 #endif /* __FSL_PORT_FEATURES_H__ */
Kojto 90:cb3d968589d8 330
bogdanm 82:6473597d706e 331 /*******************************************************************************
bogdanm 82:6473597d706e 332 * EOF
bogdanm 82:6473597d706e 333 ******************************************************************************/