Egor Rumjantsev / mbed

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TARGET_LPC4088/TOOLCHAIN_GCC_CR/LPC407x_8x.ld@76:824293ae5e43, 2014-01-13 (annotated)

Committer:
bogdanm
Date:
Mon Jan 13 15:31:11 2014 +0200
Revision:
76:824293ae5e43
Parent:
69:4a7918f48478 
Release 76 of the mbed library



Main changes:



- enabled SPI slave on LPC812

- the RTOS should now work with GCC_CR  (LPC1768 and LPC4088)

- GCC now uses 'hard' as the floating point ABI (arguments in floating point registers)

- Bug fixes on various platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 69:4a7918f48478 1 /*
emilmont 69:4a7918f48478 2 * GENERATED FILE - DO NOT EDIT
emilmont 69:4a7918f48478 3 * (C) Code Red Technologies Ltd, 2008-2013
emilmont 69:4a7918f48478 4 * Generated linker script file for LPC4088
emilmont 69:4a7918f48478 5 * Created from generic_c.ld (vLPCXpresso v5.1 (2 [Build 2065] [2013-02-20] ))
emilmont 69:4a7918f48478 6 * By LPCXpresso v5.1.2 [Build 2065] [2013-02-20] on Wed Apr 17 14:50:07 CEST 2013
emilmont 69:4a7918f48478 7 */
emilmont 69:4a7918f48478 8
emilmont 69:4a7918f48478 9
emilmont 69:4a7918f48478 10 GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
emilmont 69:4a7918f48478 11
emilmont 69:4a7918f48478 12 MEMORY
emilmont 69:4a7918f48478 13 {
emilmont 69:4a7918f48478 14 /* Define each memory region */
emilmont 69:4a7918f48478 15 MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
emilmont 69:4a7918f48478 16 RamLoc64 (rwx) : ORIGIN = 0x100000E8, LENGTH = 0xFF18 /* 64k */
emilmont 69:4a7918f48478 17 RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */
emilmont 69:4a7918f48478 18
emilmont 69:4a7918f48478 19 }
emilmont 69:4a7918f48478 20 /* Define a symbol for the top of each memory region */
emilmont 69:4a7918f48478 21 __top_MFlash512 = 0x0 + 0x80000;
emilmont 69:4a7918f48478 22 __top_RamLoc64 = 0x10000000 + 0x10000;
emilmont 69:4a7918f48478 23 __top_RamPeriph32 = 0x20000000 + 0x8000;
emilmont 69:4a7918f48478 24
emilmont 69:4a7918f48478 25 ENTRY(ResetISR)
emilmont 69:4a7918f48478 26
emilmont 69:4a7918f48478 27 SECTIONS
emilmont 69:4a7918f48478 28 {
emilmont 69:4a7918f48478 29
emilmont 69:4a7918f48478 30 /* MAIN TEXT SECTION */
emilmont 69:4a7918f48478 31 .text : ALIGN(4)
emilmont 69:4a7918f48478 32 {
emilmont 69:4a7918f48478 33 FILL(0xff)
emilmont 69:4a7918f48478 34 KEEP(*(.isr_vector))
emilmont 69:4a7918f48478 35
emilmont 69:4a7918f48478 36 /* Global Section Table */
emilmont 69:4a7918f48478 37 . = ALIGN(4) ;
emilmont 69:4a7918f48478 38 __section_table_start = .;
emilmont 69:4a7918f48478 39 __data_section_table = .;
emilmont 69:4a7918f48478 40 LONG(LOADADDR(.data));
emilmont 69:4a7918f48478 41 LONG( ADDR(.data)) ;
emilmont 69:4a7918f48478 42 LONG( SIZEOF(.data));
emilmont 69:4a7918f48478 43 LONG(LOADADDR(.data_RAM2));
emilmont 69:4a7918f48478 44 LONG( ADDR(.data_RAM2)) ;
emilmont 69:4a7918f48478 45 LONG( SIZEOF(.data_RAM2));
emilmont 69:4a7918f48478 46 __data_section_table_end = .;
emilmont 69:4a7918f48478 47 __bss_section_table = .;
emilmont 69:4a7918f48478 48 LONG( ADDR(.bss));
emilmont 69:4a7918f48478 49 LONG( SIZEOF(.bss));
emilmont 69:4a7918f48478 50 LONG( ADDR(.bss_RAM2));
emilmont 69:4a7918f48478 51 LONG( SIZEOF(.bss_RAM2));
emilmont 69:4a7918f48478 52 __bss_section_table_end = .;
emilmont 69:4a7918f48478 53 __section_table_end = . ;
emilmont 69:4a7918f48478 54 /* End of Global Section Table */
emilmont 69:4a7918f48478 55
emilmont 69:4a7918f48478 56
emilmont 69:4a7918f48478 57 *(.after_vectors*)
emilmont 69:4a7918f48478 58
emilmont 69:4a7918f48478 59 *(.text*)
emilmont 69:4a7918f48478 60 *(.rodata .rodata.*)
emilmont 69:4a7918f48478 61 . = ALIGN(4);
emilmont 69:4a7918f48478 62
emilmont 69:4a7918f48478 63 /* C++ constructors etc */
emilmont 69:4a7918f48478 64 . = ALIGN(4);
emilmont 69:4a7918f48478 65 KEEP(*(.init))
emilmont 69:4a7918f48478 66
emilmont 69:4a7918f48478 67 . = ALIGN(4);
emilmont 69:4a7918f48478 68 __preinit_array_start = .;
emilmont 69:4a7918f48478 69 KEEP (*(.preinit_array))
emilmont 69:4a7918f48478 70 __preinit_array_end = .;
emilmont 69:4a7918f48478 71
emilmont 69:4a7918f48478 72 . = ALIGN(4);
emilmont 69:4a7918f48478 73 __init_array_start = .;
emilmont 69:4a7918f48478 74 KEEP (*(SORT(.init_array.*)))
emilmont 69:4a7918f48478 75 KEEP (*(.init_array))
emilmont 69:4a7918f48478 76 __init_array_end = .;
emilmont 69:4a7918f48478 77
emilmont 69:4a7918f48478 78 KEEP(*(.fini));
emilmont 69:4a7918f48478 79
emilmont 69:4a7918f48478 80 . = ALIGN(4);
emilmont 69:4a7918f48478 81 KEEP (*crtbegin.o(.ctors))
emilmont 69:4a7918f48478 82 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
emilmont 69:4a7918f48478 83 KEEP (*(SORT(.ctors.*)))
emilmont 69:4a7918f48478 84 KEEP (*crtend.o(.ctors))
emilmont 69:4a7918f48478 85
emilmont 69:4a7918f48478 86 . = ALIGN(4);
emilmont 69:4a7918f48478 87 KEEP (*crtbegin.o(.dtors))
emilmont 69:4a7918f48478 88 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
emilmont 69:4a7918f48478 89 KEEP (*(SORT(.dtors.*)))
emilmont 69:4a7918f48478 90 KEEP (*crtend.o(.dtors))
emilmont 69:4a7918f48478 91 /* End C++ */
emilmont 69:4a7918f48478 92 } > MFlash512
emilmont 69:4a7918f48478 93
emilmont 69:4a7918f48478 94 /*
emilmont 69:4a7918f48478 95 * for exception handling/unwind - some Newlib functions (in common
emilmont 69:4a7918f48478 96 * with C++ and STDC++) use this.
emilmont 69:4a7918f48478 97 */
emilmont 69:4a7918f48478 98 .ARM.extab : ALIGN(4)
emilmont 69:4a7918f48478 99 {
emilmont 69:4a7918f48478 100 *(.ARM.extab* .gnu.linkonce.armextab.*)
emilmont 69:4a7918f48478 101 } > MFlash512
emilmont 69:4a7918f48478 102 __exidx_start = .;
emilmont 69:4a7918f48478 103
emilmont 69:4a7918f48478 104 .ARM.exidx : ALIGN(4)
emilmont 69:4a7918f48478 105 {
emilmont 69:4a7918f48478 106 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
emilmont 69:4a7918f48478 107 } > MFlash512
emilmont 69:4a7918f48478 108 __exidx_end = .;
emilmont 69:4a7918f48478 109
emilmont 69:4a7918f48478 110 _etext = .;
emilmont 69:4a7918f48478 111
emilmont 69:4a7918f48478 112
emilmont 69:4a7918f48478 113 /* DATA section for RamPeriph32 */
emilmont 69:4a7918f48478 114 .data_RAM2 : ALIGN(4)
emilmont 69:4a7918f48478 115 {
emilmont 69:4a7918f48478 116 FILL(0xff)
emilmont 69:4a7918f48478 117 *(.data.$RAM2*)
emilmont 69:4a7918f48478 118 *(.data.$RamPeriph32*)
emilmont 69:4a7918f48478 119 . = ALIGN(4) ;
emilmont 69:4a7918f48478 120 } > RamPeriph32 AT>MFlash512
emilmont 69:4a7918f48478 121
emilmont 69:4a7918f48478 122 /* MAIN DATA SECTION */
emilmont 69:4a7918f48478 123
emilmont 69:4a7918f48478 124
emilmont 69:4a7918f48478 125 .uninit_RESERVED : ALIGN(4)
emilmont 69:4a7918f48478 126 {
emilmont 69:4a7918f48478 127 KEEP(*(.bss.$RESERVED*))
emilmont 69:4a7918f48478 128 . = ALIGN(4) ;
emilmont 69:4a7918f48478 129 _end_uninit_RESERVED = .;
emilmont 69:4a7918f48478 130 } > RamLoc64
emilmont 69:4a7918f48478 131
emilmont 69:4a7918f48478 132 .data : ALIGN(4)
emilmont 69:4a7918f48478 133 {
emilmont 69:4a7918f48478 134 FILL(0xff)
emilmont 69:4a7918f48478 135 _data = .;
emilmont 69:4a7918f48478 136 *(vtable)
emilmont 69:4a7918f48478 137 *(.data*)
emilmont 69:4a7918f48478 138 . = ALIGN(4) ;
emilmont 69:4a7918f48478 139 _edata = .;
emilmont 69:4a7918f48478 140 } > RamLoc64 AT>MFlash512
emilmont 69:4a7918f48478 141
emilmont 69:4a7918f48478 142 /* BSS section for RamPeriph32 */
emilmont 69:4a7918f48478 143 .bss_RAM2 : ALIGN(4)
emilmont 69:4a7918f48478 144 {
emilmont 69:4a7918f48478 145 *(.bss.$RAM2*)
emilmont 69:4a7918f48478 146 *(.bss.$RamPeriph32*)
emilmont 69:4a7918f48478 147 . = ALIGN(4) ;
emilmont 69:4a7918f48478 148 } > RamPeriph32
emilmont 69:4a7918f48478 149
emilmont 69:4a7918f48478 150 /* MAIN BSS SECTION */
emilmont 69:4a7918f48478 151 .bss : ALIGN(4)
emilmont 69:4a7918f48478 152 {
emilmont 69:4a7918f48478 153 _bss = .;
emilmont 69:4a7918f48478 154 *(.bss*)
emilmont 69:4a7918f48478 155 *(COMMON)
emilmont 69:4a7918f48478 156 . = ALIGN(4) ;
emilmont 69:4a7918f48478 157 _ebss = .;
emilmont 69:4a7918f48478 158 PROVIDE(end = .);
bogdanm 76:824293ae5e43 159 __end__ = .;
emilmont 69:4a7918f48478 160 } > RamLoc64
emilmont 69:4a7918f48478 161
emilmont 69:4a7918f48478 162 /* NOINIT section for RamPeriph32 */
emilmont 69:4a7918f48478 163 .noinit_RAM2 (NOLOAD) : ALIGN(4)
emilmont 69:4a7918f48478 164 {
emilmont 69:4a7918f48478 165 *(.noinit.$RAM2*)
emilmont 69:4a7918f48478 166 *(.noinit.$RamPeriph32*)
emilmont 69:4a7918f48478 167 . = ALIGN(4) ;
emilmont 69:4a7918f48478 168 } > RamPeriph32
emilmont 69:4a7918f48478 169
emilmont 69:4a7918f48478 170 /* DEFAULT NOINIT SECTION */
emilmont 69:4a7918f48478 171 .noinit (NOLOAD): ALIGN(4)
emilmont 69:4a7918f48478 172 {
emilmont 69:4a7918f48478 173 _noinit = .;
emilmont 69:4a7918f48478 174 *(.noinit*)
emilmont 69:4a7918f48478 175 . = ALIGN(4) ;
emilmont 69:4a7918f48478 176 _end_noinit = .;
emilmont 69:4a7918f48478 177 } > RamLoc64
emilmont 69:4a7918f48478 178
emilmont 69:4a7918f48478 179 PROVIDE(_pvHeapStart = .);
emilmont 69:4a7918f48478 180 PROVIDE(_vStackTop = __top_RamLoc64 - 0);
emilmont 69:4a7918f48478 181 }