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TARGET_EFM32LG_STK3600/efm32lg_dmareq.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
98:8ab26030e058 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 98:8ab26030e058 1 /**************************************************************************//**
Kojto 98:8ab26030e058 2 * @file efm32lg_dmareq.h
Kojto 98:8ab26030e058 3 * @brief EFM32LG_DMAREQ register and bit field definitions
Kojto 98:8ab26030e058 4 * @version 3.20.6
Kojto 98:8ab26030e058 5 ******************************************************************************
Kojto 98:8ab26030e058 6 * @section License
Kojto 98:8ab26030e058 7 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
Kojto 98:8ab26030e058 8 ******************************************************************************
Kojto 98:8ab26030e058 9 *
Kojto 98:8ab26030e058 10 * Permission is granted to anyone to use this software for any purpose,
Kojto 98:8ab26030e058 11 * including commercial applications, and to alter it and redistribute it
Kojto 98:8ab26030e058 12 * freely, subject to the following restrictions:
Kojto 98:8ab26030e058 13 *
Kojto 98:8ab26030e058 14 * 1. The origin of this software must not be misrepresented; you must not
Kojto 98:8ab26030e058 15 * claim that you wrote the original software.@n
Kojto 98:8ab26030e058 16 * 2. Altered source versions must be plainly marked as such, and must not be
Kojto 98:8ab26030e058 17 * misrepresented as being the original software.@n
Kojto 98:8ab26030e058 18 * 3. This notice may not be removed or altered from any source distribution.
Kojto 98:8ab26030e058 19 *
Kojto 98:8ab26030e058 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
Kojto 98:8ab26030e058 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
Kojto 98:8ab26030e058 22 * providing the Software "AS IS", with no express or implied warranties of any
Kojto 98:8ab26030e058 23 * kind, including, but not limited to, any implied warranties of
Kojto 98:8ab26030e058 24 * merchantability or fitness for any particular purpose or warranties against
Kojto 98:8ab26030e058 25 * infringement of any proprietary rights of a third party.
Kojto 98:8ab26030e058 26 *
Kojto 98:8ab26030e058 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
Kojto 98:8ab26030e058 28 * incidental, or special damages, or any other relief, or for any claim by
Kojto 98:8ab26030e058 29 * any third party, arising from your use of this Software.
Kojto 98:8ab26030e058 30 *
Kojto 98:8ab26030e058 31 *****************************************************************************/
Kojto 98:8ab26030e058 32
Kojto 98:8ab26030e058 33 /**************************************************************************//**
Kojto 98:8ab26030e058 34 * @defgroup EFM32LG_DMAREQ_BitFields
Kojto 98:8ab26030e058 35 * @{
Kojto 98:8ab26030e058 36 *****************************************************************************/
Kojto 98:8ab26030e058 37 #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
Kojto 98:8ab26030e058 38 #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
Kojto 98:8ab26030e058 39 #define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */
Kojto 98:8ab26030e058 40 #define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */
Kojto 98:8ab26030e058 41 #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
Kojto 98:8ab26030e058 42 #define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
Kojto 98:8ab26030e058 43 #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
Kojto 98:8ab26030e058 44 #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
Kojto 98:8ab26030e058 45 #define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
Kojto 98:8ab26030e058 46 #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
Kojto 98:8ab26030e058 47 #define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
Kojto 98:8ab26030e058 48 #define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
Kojto 98:8ab26030e058 49 #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
Kojto 98:8ab26030e058 50 #define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
Kojto 98:8ab26030e058 51 #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
Kojto 98:8ab26030e058 52 #define DMAREQ_USART2_RXDATAVRIGHT ((14 << 16) + 3) /**< DMA channel select for USART2_RXDATAVRIGHT */
Kojto 98:8ab26030e058 53 #define DMAREQ_USART2_TXBLRIGHT ((14 << 16) + 4) /**< DMA channel select for USART2_TXBLRIGHT */
Kojto 98:8ab26030e058 54 #define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
Kojto 98:8ab26030e058 55 #define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
Kojto 98:8ab26030e058 56 #define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
Kojto 98:8ab26030e058 57 #define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
Kojto 98:8ab26030e058 58 #define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
Kojto 98:8ab26030e058 59 #define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
Kojto 98:8ab26030e058 60 #define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
Kojto 98:8ab26030e058 61 #define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
Kojto 98:8ab26030e058 62 #define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
Kojto 98:8ab26030e058 63 #define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
Kojto 98:8ab26030e058 64 #define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
Kojto 98:8ab26030e058 65 #define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
Kojto 98:8ab26030e058 66 #define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
Kojto 98:8ab26030e058 67 #define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
Kojto 98:8ab26030e058 68 #define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
Kojto 98:8ab26030e058 69 #define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
Kojto 98:8ab26030e058 70 #define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
Kojto 98:8ab26030e058 71 #define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
Kojto 98:8ab26030e058 72 #define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
Kojto 98:8ab26030e058 73 #define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
Kojto 98:8ab26030e058 74 #define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
Kojto 98:8ab26030e058 75 #define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
Kojto 98:8ab26030e058 76 #define DMAREQ_TIMER3_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */
Kojto 98:8ab26030e058 77 #define DMAREQ_TIMER3_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */
Kojto 98:8ab26030e058 78 #define DMAREQ_TIMER3_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */
Kojto 98:8ab26030e058 79 #define DMAREQ_TIMER3_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */
Kojto 98:8ab26030e058 80 #define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
Kojto 98:8ab26030e058 81 #define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */
Kojto 98:8ab26030e058 82 #define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
Kojto 98:8ab26030e058 83 #define DMAREQ_UART1_RXDATAV ((45 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */
Kojto 98:8ab26030e058 84 #define DMAREQ_UART1_TXBL ((45 << 16) + 1) /**< DMA channel select for UART1_TXBL */
Kojto 98:8ab26030e058 85 #define DMAREQ_UART1_TXEMPTY ((45 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */
Kojto 98:8ab26030e058 86 #define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
Kojto 98:8ab26030e058 87 #define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */
Kojto 98:8ab26030e058 88 #define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */
Kojto 98:8ab26030e058 89 #define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */
Kojto 98:8ab26030e058 90 #define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
Kojto 98:8ab26030e058 91 #define DMAREQ_LESENSE_BUFDATAV ((50 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
Kojto 98:8ab26030e058 92 #define DMAREQ_EBI_PXL0EMPTY ((51 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */
Kojto 98:8ab26030e058 93 #define DMAREQ_EBI_PXL1EMPTY ((51 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */
Kojto 98:8ab26030e058 94 #define DMAREQ_EBI_PXLFULL ((51 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */
Kojto 98:8ab26030e058 95 #define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
Kojto 98:8ab26030e058 96
Kojto 98:8ab26030e058 97 /** @} End of group EFM32LG_DMAREQ */
Kojto 98:8ab26030e058 98
Kojto 98:8ab26030e058 99