Egor Rumjantsev
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TARGET_RZ_A1H/cpg_iobitmask.h@99:7f6c6de930c0, 2015-05-03 (annotated)
- Committer:
- Mikchel
- Date:
- Sun May 03 16:04:42 2015 +0000
- Revision:
- 99:7f6c6de930c0
- Parent:
- 92:4fc01daae5a5
12
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 92:4fc01daae5a5 | 1 | /******************************************************************************* |
| bogdanm | 92:4fc01daae5a5 | 2 | * DISCLAIMER |
| bogdanm | 92:4fc01daae5a5 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| bogdanm | 92:4fc01daae5a5 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| bogdanm | 92:4fc01daae5a5 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| bogdanm | 92:4fc01daae5a5 | 6 | * all applicable laws, including copyright laws. |
| bogdanm | 92:4fc01daae5a5 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| bogdanm | 92:4fc01daae5a5 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| bogdanm | 92:4fc01daae5a5 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| bogdanm | 92:4fc01daae5a5 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| bogdanm | 92:4fc01daae5a5 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| bogdanm | 92:4fc01daae5a5 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| bogdanm | 92:4fc01daae5a5 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| bogdanm | 92:4fc01daae5a5 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| bogdanm | 92:4fc01daae5a5 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| bogdanm | 92:4fc01daae5a5 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| bogdanm | 92:4fc01daae5a5 | 17 | * and to discontinue the availability of this software. By using this software, |
| bogdanm | 92:4fc01daae5a5 | 18 | * you agree to the additional terms and conditions found by accessing the |
| bogdanm | 92:4fc01daae5a5 | 19 | * following link: |
| bogdanm | 92:4fc01daae5a5 | 20 | * http://www.renesas.com/disclaimer |
| bogdanm | 92:4fc01daae5a5 | 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. |
| bogdanm | 92:4fc01daae5a5 | 22 | *******************************************************************************/ |
| bogdanm | 92:4fc01daae5a5 | 23 | /******************************************************************************* |
| bogdanm | 92:4fc01daae5a5 | 24 | * File Name : cpg_iobitmask.h |
| bogdanm | 92:4fc01daae5a5 | 25 | * $Rev: 1115 $ |
| bogdanm | 92:4fc01daae5a5 | 26 | * $Date:: 2014-07-09 15:35:02 +0900#$ |
| bogdanm | 92:4fc01daae5a5 | 27 | * Description : CPG register define header |
| bogdanm | 92:4fc01daae5a5 | 28 | *******************************************************************************/ |
| bogdanm | 92:4fc01daae5a5 | 29 | #ifndef CPG_IOBITMASK_H |
| bogdanm | 92:4fc01daae5a5 | 30 | #define CPG_IOBITMASK_H |
| bogdanm | 92:4fc01daae5a5 | 31 | |
| bogdanm | 92:4fc01daae5a5 | 32 | |
| bogdanm | 92:4fc01daae5a5 | 33 | /* ==== Mask values for IO registers ==== */ |
| bogdanm | 92:4fc01daae5a5 | 34 | #define CPG_FRQCR_IFC (0x0300u) |
| bogdanm | 92:4fc01daae5a5 | 35 | #define CPG_FRQCR_CKOEN (0x3000u) |
| bogdanm | 92:4fc01daae5a5 | 36 | #define CPG_FRQCR_CKOEN2 (0x4000u) |
| bogdanm | 92:4fc01daae5a5 | 37 | |
| bogdanm | 92:4fc01daae5a5 | 38 | #define CPG_FRQCR2_GFC (0x0003u) |
| bogdanm | 92:4fc01daae5a5 | 39 | |
| bogdanm | 92:4fc01daae5a5 | 40 | #define CPG_CPUSTS_ISBUSY (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 41 | |
| bogdanm | 92:4fc01daae5a5 | 42 | #define CPG_STBCR1_DEEP (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 43 | #define CPG_STBCR1_STBY (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 44 | |
| bogdanm | 92:4fc01daae5a5 | 45 | #define CPG_STBCR2_MSTP20 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 46 | #define CPG_STBCR2_HIZ (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 47 | |
| bogdanm | 92:4fc01daae5a5 | 48 | #define CPG_STBREQ1_STBRQ10 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 49 | #define CPG_STBREQ1_STBRQ12 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 50 | #define CPG_STBREQ1_STBRQ13 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 51 | #define CPG_STBREQ1_STBRQ15 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 52 | |
| bogdanm | 92:4fc01daae5a5 | 53 | #define CPG_STBREQ2_STBRQ20 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 54 | #define CPG_STBREQ2_STBRQ21 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 55 | #define CPG_STBREQ2_STBRQ22 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 56 | #define CPG_STBREQ2_STBRQ23 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 57 | #define CPG_STBREQ2_STBRQ24 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 58 | #define CPG_STBREQ2_STBRQ25 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 59 | #define CPG_STBREQ2_STBRQ26 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 60 | #define CPG_STBREQ2_STBRQ27 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 61 | |
| bogdanm | 92:4fc01daae5a5 | 62 | #define CPG_STBACK1_STBAK10 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 63 | #define CPG_STBACK1_STBAK12 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 64 | #define CPG_STBACK1_STBAK13 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 65 | #define CPG_STBACK1_STBAK15 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 66 | |
| bogdanm | 92:4fc01daae5a5 | 67 | #define CPG_STBACK2_STBAK20 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 68 | #define CPG_STBACK2_STBAK21 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 69 | #define CPG_STBACK2_STBAK22 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 70 | #define CPG_STBACK2_STBAK23 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 71 | #define CPG_STBACK2_STBAK24 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 72 | #define CPG_STBACK2_STBAK25 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 73 | #define CPG_STBACK2_STBAK26 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 74 | #define CPG_STBACK2_STBAK27 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 75 | |
| bogdanm | 92:4fc01daae5a5 | 76 | #define CPG_SYSCR1_VRAME0 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 77 | #define CPG_SYSCR1_VRAME1 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 78 | #define CPG_SYSCR1_VRAME2 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 79 | #define CPG_SYSCR1_VRAME3 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 80 | #define CPG_SYSCR1_VRAME4 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 81 | |
| bogdanm | 92:4fc01daae5a5 | 82 | #define CPG_SYSCR2_VRAMWE0 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 83 | #define CPG_SYSCR2_VRAMWE1 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 84 | #define CPG_SYSCR2_VRAMWE2 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 85 | #define CPG_SYSCR2_VRAMWE3 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 86 | #define CPG_SYSCR2_VRAMWE4 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 87 | |
| bogdanm | 92:4fc01daae5a5 | 88 | #define CPG_SYSCR3_RRAMWE0 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 89 | #define CPG_SYSCR3_RRAMWE1 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 90 | #define CPG_SYSCR3_RRAMWE2 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 91 | #define CPG_SYSCR3_RRAMWE3 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 92 | |
| bogdanm | 92:4fc01daae5a5 | 93 | #define CPG_STBCR3_MSTP30 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 94 | #define CPG_STBCR3_MSTP31 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 95 | #define CPG_STBCR3_MSTP32 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 96 | #define CPG_STBCR3_MSTP33 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 97 | #define CPG_STBCR3_MSTP34 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 98 | #define CPG_STBCR3_MSTP35 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 99 | #define CPG_STBCR3_MSTP36 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 100 | #define CPG_STBCR3_MSTP37 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 101 | |
| bogdanm | 92:4fc01daae5a5 | 102 | #define CPG_STBCR4_MSTP40 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 103 | #define CPG_STBCR4_MSTP41 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 104 | #define CPG_STBCR4_MSTP42 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 105 | #define CPG_STBCR4_MSTP43 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 106 | #define CPG_STBCR4_MSTP44 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 107 | #define CPG_STBCR4_MSTP45 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 108 | #define CPG_STBCR4_MSTP46 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 109 | #define CPG_STBCR4_MSTP47 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 110 | |
| bogdanm | 92:4fc01daae5a5 | 111 | #define CPG_STBCR5_MSTP50 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 112 | #define CPG_STBCR5_MSTP51 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 113 | #define CPG_STBCR5_MSTP52 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 114 | #define CPG_STBCR5_MSTP53 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 115 | #define CPG_STBCR5_MSTP54 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 116 | #define CPG_STBCR5_MSTP55 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 117 | #define CPG_STBCR5_MSTP56 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 118 | #define CPG_STBCR5_MSTP57 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 119 | |
| bogdanm | 92:4fc01daae5a5 | 120 | #define CPG_STBCR6_MSTP60 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 121 | #define CPG_STBCR6_MSTP61 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 122 | #define CPG_STBCR6_MSTP62 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 123 | #define CPG_STBCR6_MSTP63 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 124 | #define CPG_STBCR6_MSTP64 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 125 | #define CPG_STBCR6_MSTP65 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 126 | #define CPG_STBCR6_MSTP66 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 127 | #define CPG_STBCR6_MSTP67 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 128 | |
| bogdanm | 92:4fc01daae5a5 | 129 | #define CPG_STBCR7_MSTP70 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 130 | #define CPG_STBCR7_MSTP71 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 131 | #define CPG_STBCR7_MSTP73 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 132 | #define CPG_STBCR7_MSTP74 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 133 | #define CPG_STBCR7_MSTP76 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 134 | #define CPG_STBCR7_MSTP77 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 135 | |
| bogdanm | 92:4fc01daae5a5 | 136 | #define CPG_STBCR8_MSTP81 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 137 | #define CPG_STBCR8_MSTP82 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 138 | #define CPG_STBCR8_MSTP83 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 139 | #define CPG_STBCR8_MSTP84 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 140 | #define CPG_STBCR8_MSTP85 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 141 | #define CPG_STBCR8_MSTP86 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 142 | #define CPG_STBCR8_MSTP87 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 143 | |
| bogdanm | 92:4fc01daae5a5 | 144 | #define CPG_STBCR9_MSTP90 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 145 | #define CPG_STBCR9_MSTP91 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 146 | #define CPG_STBCR9_MSTP92 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 147 | #define CPG_STBCR9_MSTP93 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 148 | #define CPG_STBCR9_MSTP94 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 149 | #define CPG_STBCR9_MSTP95 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 150 | #define CPG_STBCR9_MSTP96 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 151 | #define CPG_STBCR9_MSTP97 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 152 | |
| bogdanm | 92:4fc01daae5a5 | 153 | #define CPG_STBCR10_MSTP100 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 154 | #define CPG_STBCR10_MSTP101 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 155 | #define CPG_STBCR10_MSTP102 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 156 | #define CPG_STBCR10_MSTP103 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 157 | #define CPG_STBCR10_MSTP104 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 158 | #define CPG_STBCR10_MSTP105 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 159 | #define CPG_STBCR10_MSTP106 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 160 | #define CPG_STBCR10_MSTP107 (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 161 | |
| bogdanm | 92:4fc01daae5a5 | 162 | #define CPG_STBCR11_MSTP110 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 163 | #define CPG_STBCR11_MSTP111 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 164 | #define CPG_STBCR11_MSTP112 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 165 | #define CPG_STBCR11_MSTP113 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 166 | #define CPG_STBCR11_MSTP114 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 167 | #define CPG_STBCR11_MSTP115 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 168 | |
| bogdanm | 92:4fc01daae5a5 | 169 | #define CPG_STBCR12_MSTP120 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 170 | #define CPG_STBCR12_MSTP121 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 171 | #define CPG_STBCR12_MSTP122 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 172 | #define CPG_STBCR12_MSTP123 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 173 | |
| bogdanm | 92:4fc01daae5a5 | 174 | #define CPG_STBCR13_MSTP131 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 175 | #define CPG_STBCR13_MSTP132 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 176 | |
| bogdanm | 92:4fc01daae5a5 | 177 | #define CPG_SWRSTCR1_SRST11 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 178 | #define CPG_SWRSTCR1_SRST12 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 179 | #define CPG_SWRSTCR1_SRST13 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 180 | #define CPG_SWRSTCR1_SRST14 (0x10u) |
| bogdanm | 92:4fc01daae5a5 | 181 | #define CPG_SWRSTCR1_SRST15 (0x20u) |
| bogdanm | 92:4fc01daae5a5 | 182 | #define CPG_SWRSTCR1_SRST16 (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 183 | #define CPG_SWRSTCR1_AXTALE (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 184 | |
| bogdanm | 92:4fc01daae5a5 | 185 | #define CPG_SWRSTCR2_SRST21 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 186 | |
| bogdanm | 92:4fc01daae5a5 | 187 | #define CPG_SWRSTCR3_SRST32 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 188 | |
| bogdanm | 92:4fc01daae5a5 | 189 | #define CPG_RRAMKP_RRAMKP0 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 190 | #define CPG_RRAMKP_RRAMKP1 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 191 | #define CPG_RRAMKP_RRAMKP2 (0x04u) |
| bogdanm | 92:4fc01daae5a5 | 192 | #define CPG_RRAMKP_RRAMKP3 (0x08u) |
| bogdanm | 92:4fc01daae5a5 | 193 | |
| bogdanm | 92:4fc01daae5a5 | 194 | #define CPG_DSCTR_RAMBOOT (0x40u) |
| bogdanm | 92:4fc01daae5a5 | 195 | #define CPG_DSCTR_EBUSKEEPE (0x80u) |
| bogdanm | 92:4fc01daae5a5 | 196 | |
| bogdanm | 92:4fc01daae5a5 | 197 | #define CPG_DSSSR_P8_2 (0x0001u) |
| bogdanm | 92:4fc01daae5a5 | 198 | #define CPG_DSSSR_P9_1 (0x0002u) |
| bogdanm | 92:4fc01daae5a5 | 199 | #define CPG_DSSSR_P2_15 (0x0004u) |
| bogdanm | 92:4fc01daae5a5 | 200 | #define CPG_DSSSR_P7_8 (0x0008u) |
| bogdanm | 92:4fc01daae5a5 | 201 | #define CPG_DSSSR_P5_9 (0x0010u) |
| bogdanm | 92:4fc01daae5a5 | 202 | #define CPG_DSSSR_P6_4 (0x0020u) |
| bogdanm | 92:4fc01daae5a5 | 203 | #define CPG_DSSSR_RTCAR (0x0040u) |
| bogdanm | 92:4fc01daae5a5 | 204 | #define CPG_DSSSR_NMI (0x0100u) |
| bogdanm | 92:4fc01daae5a5 | 205 | #define CPG_DSSSR_P3_3 (0x0200u) |
| bogdanm | 92:4fc01daae5a5 | 206 | #define CPG_DSSSR_P8_7 (0x0400u) |
| bogdanm | 92:4fc01daae5a5 | 207 | #define CPG_DSSSR_P2_12 (0x0800u) |
| bogdanm | 92:4fc01daae5a5 | 208 | #define CPG_DSSSR_P3_1 (0x1000u) |
| bogdanm | 92:4fc01daae5a5 | 209 | #define CPG_DSSSR_P3_9 (0x2000u) |
| bogdanm | 92:4fc01daae5a5 | 210 | #define CPG_DSSSR_P6_2 (0x4000u) |
| bogdanm | 92:4fc01daae5a5 | 211 | |
| bogdanm | 92:4fc01daae5a5 | 212 | #define CPG_DSESR_P8_2E (0x0001u) |
| bogdanm | 92:4fc01daae5a5 | 213 | #define CPG_DSESR_P9_1E (0x0002u) |
| bogdanm | 92:4fc01daae5a5 | 214 | #define CPG_DSESR_P2_15E (0x0004u) |
| bogdanm | 92:4fc01daae5a5 | 215 | #define CPG_DSESR_P7_8E (0x0008u) |
| bogdanm | 92:4fc01daae5a5 | 216 | #define CPG_DSESR_P5_9E (0x0010u) |
| bogdanm | 92:4fc01daae5a5 | 217 | #define CPG_DSESR_P6_4E (0x0020u) |
| bogdanm | 92:4fc01daae5a5 | 218 | #define CPG_DSESR_NMIE (0x0100u) |
| bogdanm | 92:4fc01daae5a5 | 219 | #define CPG_DSESR_P3_3E (0x0200u) |
| bogdanm | 92:4fc01daae5a5 | 220 | #define CPG_DSESR_P8_7E (0x0400u) |
| bogdanm | 92:4fc01daae5a5 | 221 | #define CPG_DSESR_P2_12E (0x0800u) |
| bogdanm | 92:4fc01daae5a5 | 222 | #define CPG_DSESR_P3_1E (0x1000u) |
| bogdanm | 92:4fc01daae5a5 | 223 | #define CPG_DSESR_P3_9E (0x2000u) |
| bogdanm | 92:4fc01daae5a5 | 224 | #define CPG_DSESR_P6_2E (0x4000u) |
| bogdanm | 92:4fc01daae5a5 | 225 | |
| bogdanm | 92:4fc01daae5a5 | 226 | #define CPG_DSFR_P8_2F (0x0001u) |
| bogdanm | 92:4fc01daae5a5 | 227 | #define CPG_DSFR_P9_1F (0x0002u) |
| bogdanm | 92:4fc01daae5a5 | 228 | #define CPG_DSFR_P2_15F (0x0004u) |
| bogdanm | 92:4fc01daae5a5 | 229 | #define CPG_DSFR_P7_8F (0x0008u) |
| bogdanm | 92:4fc01daae5a5 | 230 | #define CPG_DSFR_P5_9F (0x0010u) |
| bogdanm | 92:4fc01daae5a5 | 231 | #define CPG_DSFR_P6_4F (0x0020u) |
| bogdanm | 92:4fc01daae5a5 | 232 | #define CPG_DSFR_RTCARF (0x0040u) |
| bogdanm | 92:4fc01daae5a5 | 233 | #define CPG_DSFR_NMIF (0x0100u) |
| bogdanm | 92:4fc01daae5a5 | 234 | #define CPG_DSFR_P3_3F (0x0200u) |
| bogdanm | 92:4fc01daae5a5 | 235 | #define CPG_DSFR_P8_7F (0x0400u) |
| bogdanm | 92:4fc01daae5a5 | 236 | #define CPG_DSFR_P2_12F (0x0800u) |
| bogdanm | 92:4fc01daae5a5 | 237 | #define CPG_DSFR_P3_1F (0x1000u) |
| bogdanm | 92:4fc01daae5a5 | 238 | #define CPG_DSFR_P3_9F (0x2000u) |
| bogdanm | 92:4fc01daae5a5 | 239 | #define CPG_DSFR_P6_2F (0x4000u) |
| bogdanm | 92:4fc01daae5a5 | 240 | #define CPG_DSFR_IOKEEP (0x8000u) |
| bogdanm | 92:4fc01daae5a5 | 241 | |
| bogdanm | 92:4fc01daae5a5 | 242 | #define CPG_XTALCTR_GAIN0 (0x01u) |
| bogdanm | 92:4fc01daae5a5 | 243 | #define CPG_XTALCTR_GAIN1 (0x02u) |
| bogdanm | 92:4fc01daae5a5 | 244 | |
| bogdanm | 92:4fc01daae5a5 | 245 | |
| bogdanm | 92:4fc01daae5a5 | 246 | /* ==== Shift values for IO registers ==== */ |
| bogdanm | 92:4fc01daae5a5 | 247 | #define CPG_FRQCR_IFC_SHIFT (8u) |
| bogdanm | 92:4fc01daae5a5 | 248 | #define CPG_FRQCR_CKOEN_SHIFT (12u) |
| bogdanm | 92:4fc01daae5a5 | 249 | #define CPG_FRQCR_CKOEN2_SHIFT (14u) |
| bogdanm | 92:4fc01daae5a5 | 250 | |
| bogdanm | 92:4fc01daae5a5 | 251 | #define CPG_FRQCR2_GFC_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 252 | |
| bogdanm | 92:4fc01daae5a5 | 253 | #define CPG_CPUSTS_ISBUSY_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 254 | |
| bogdanm | 92:4fc01daae5a5 | 255 | #define CPG_STBCR1_DEEP_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 256 | #define CPG_STBCR1_STBY_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 257 | |
| bogdanm | 92:4fc01daae5a5 | 258 | #define CPG_STBCR2_MSTP20_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 259 | #define CPG_STBCR2_HIZ_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 260 | |
| bogdanm | 92:4fc01daae5a5 | 261 | #define CPG_STBREQ1_STBRQ10_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 262 | #define CPG_STBREQ1_STBRQ12_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 263 | #define CPG_STBREQ1_STBRQ13_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 264 | #define CPG_STBREQ1_STBRQ15_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 265 | |
| bogdanm | 92:4fc01daae5a5 | 266 | #define CPG_STBREQ2_STBRQ20_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 267 | #define CPG_STBREQ2_STBRQ21_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 268 | #define CPG_STBREQ2_STBRQ22_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 269 | #define CPG_STBREQ2_STBRQ23_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 270 | #define CPG_STBREQ2_STBRQ24_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 271 | #define CPG_STBREQ2_STBRQ25_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 272 | #define CPG_STBREQ2_STBRQ26_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 273 | #define CPG_STBREQ2_STBRQ27_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 274 | |
| bogdanm | 92:4fc01daae5a5 | 275 | #define CPG_STBACK1_STBAK10_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 276 | #define CPG_STBACK1_STBAK12_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 277 | #define CPG_STBACK1_STBAK13_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 278 | #define CPG_STBACK1_STBAK15_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 279 | |
| bogdanm | 92:4fc01daae5a5 | 280 | #define CPG_STBACK2_STBAK20_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 281 | #define CPG_STBACK2_STBAK21_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 282 | #define CPG_STBACK2_STBAK22_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 283 | #define CPG_STBACK2_STBAK23_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 284 | #define CPG_STBACK2_STBAK24_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 285 | #define CPG_STBACK2_STBAK25_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 286 | #define CPG_STBACK2_STBAK26_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 287 | #define CPG_STBACK2_STBAK27_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 288 | |
| bogdanm | 92:4fc01daae5a5 | 289 | #define CPG_SYSCR1_VRAME0_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 290 | #define CPG_SYSCR1_VRAME1_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 291 | #define CPG_SYSCR1_VRAME2_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 292 | #define CPG_SYSCR1_VRAME3_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 293 | #define CPG_SYSCR1_VRAME4_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 294 | |
| bogdanm | 92:4fc01daae5a5 | 295 | #define CPG_SYSCR2_VRAMWE0_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 296 | #define CPG_SYSCR2_VRAMWE1_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 297 | #define CPG_SYSCR2_VRAMWE2_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 298 | #define CPG_SYSCR2_VRAMWE3_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 299 | #define CPG_SYSCR2_VRAMWE4_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 300 | |
| bogdanm | 92:4fc01daae5a5 | 301 | #define CPG_SYSCR3_RRAMWE0_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 302 | #define CPG_SYSCR3_RRAMWE1_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 303 | #define CPG_SYSCR3_RRAMWE2_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 304 | #define CPG_SYSCR3_RRAMWE3_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 305 | |
| bogdanm | 92:4fc01daae5a5 | 306 | #define CPG_STBCR3_MSTP30_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 307 | #define CPG_STBCR3_MSTP31_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 308 | #define CPG_STBCR3_MSTP32_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 309 | #define CPG_STBCR3_MSTP33_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 310 | #define CPG_STBCR3_MSTP34_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 311 | #define CPG_STBCR3_MSTP35_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 312 | #define CPG_STBCR3_MSTP36_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 313 | #define CPG_STBCR3_MSTP37_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 314 | |
| bogdanm | 92:4fc01daae5a5 | 315 | #define CPG_STBCR4_MSTP40_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 316 | #define CPG_STBCR4_MSTP41_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 317 | #define CPG_STBCR4_MSTP42_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 318 | #define CPG_STBCR4_MSTP43_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 319 | #define CPG_STBCR4_MSTP44_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 320 | #define CPG_STBCR4_MSTP45_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 321 | #define CPG_STBCR4_MSTP46_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 322 | #define CPG_STBCR4_MSTP47_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 323 | |
| bogdanm | 92:4fc01daae5a5 | 324 | #define CPG_STBCR5_MSTP50_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 325 | #define CPG_STBCR5_MSTP51_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 326 | #define CPG_STBCR5_MSTP52_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 327 | #define CPG_STBCR5_MSTP53_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 328 | #define CPG_STBCR5_MSTP54_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 329 | #define CPG_STBCR5_MSTP55_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 330 | #define CPG_STBCR5_MSTP56_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 331 | #define CPG_STBCR5_MSTP57_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 332 | |
| bogdanm | 92:4fc01daae5a5 | 333 | #define CPG_STBCR6_MSTP60_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 334 | #define CPG_STBCR6_MSTP61_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 335 | #define CPG_STBCR6_MSTP62_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 336 | #define CPG_STBCR6_MSTP63_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 337 | #define CPG_STBCR6_MSTP64_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 338 | #define CPG_STBCR6_MSTP65_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 339 | #define CPG_STBCR6_MSTP66_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 340 | #define CPG_STBCR6_MSTP67_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 341 | |
| bogdanm | 92:4fc01daae5a5 | 342 | #define CPG_STBCR7_MSTP70_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 343 | #define CPG_STBCR7_MSTP71_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 344 | #define CPG_STBCR7_MSTP73_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 345 | #define CPG_STBCR7_MSTP74_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 346 | #define CPG_STBCR7_MSTP76_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 347 | #define CPG_STBCR7_MSTP77_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 348 | |
| bogdanm | 92:4fc01daae5a5 | 349 | #define CPG_STBCR8_MSTP81_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 350 | #define CPG_STBCR8_MSTP82_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 351 | #define CPG_STBCR8_MSTP83_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 352 | #define CPG_STBCR8_MSTP84_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 353 | #define CPG_STBCR8_MSTP85_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 354 | #define CPG_STBCR8_MSTP86_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 355 | #define CPG_STBCR8_MSTP87_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 356 | |
| bogdanm | 92:4fc01daae5a5 | 357 | #define CPG_STBCR9_MSTP90_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 358 | #define CPG_STBCR9_MSTP91_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 359 | #define CPG_STBCR9_MSTP92_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 360 | #define CPG_STBCR9_MSTP93_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 361 | #define CPG_STBCR9_MSTP94_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 362 | #define CPG_STBCR9_MSTP95_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 363 | #define CPG_STBCR9_MSTP96_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 364 | #define CPG_STBCR9_MSTP97_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 365 | |
| bogdanm | 92:4fc01daae5a5 | 366 | #define CPG_STBCR10_MSTP100_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 367 | #define CPG_STBCR10_MSTP101_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 368 | #define CPG_STBCR10_MSTP102_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 369 | #define CPG_STBCR10_MSTP103_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 370 | #define CPG_STBCR10_MSTP104_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 371 | #define CPG_STBCR10_MSTP105_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 372 | #define CPG_STBCR10_MSTP106_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 373 | #define CPG_STBCR10_MSTP107_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 374 | |
| bogdanm | 92:4fc01daae5a5 | 375 | #define CPG_STBCR11_MSTP110_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 376 | #define CPG_STBCR11_MSTP111_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 377 | #define CPG_STBCR11_MSTP112_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 378 | #define CPG_STBCR11_MSTP113_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 379 | #define CPG_STBCR11_MSTP114_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 380 | #define CPG_STBCR11_MSTP115_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 381 | |
| bogdanm | 92:4fc01daae5a5 | 382 | #define CPG_STBCR12_MSTP120_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 383 | #define CPG_STBCR12_MSTP121_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 384 | #define CPG_STBCR12_MSTP122_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 385 | #define CPG_STBCR12_MSTP123_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 386 | |
| bogdanm | 92:4fc01daae5a5 | 387 | #define CPG_STBCR13_MSTP131_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 388 | #define CPG_STBCR13_MSTP132_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 389 | |
| bogdanm | 92:4fc01daae5a5 | 390 | #define CPG_SWRSTCR1_SRST11_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 391 | #define CPG_SWRSTCR1_SRST12_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 392 | #define CPG_SWRSTCR1_SRST13_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 393 | #define CPG_SWRSTCR1_SRST14_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 394 | #define CPG_SWRSTCR1_SRST15_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 395 | #define CPG_SWRSTCR1_SRST16_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 396 | #define CPG_SWRSTCR1_AXTALE_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 397 | |
| bogdanm | 92:4fc01daae5a5 | 398 | #define CPG_SWRSTCR2_SRST21_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 399 | |
| bogdanm | 92:4fc01daae5a5 | 400 | #define CPG_SWRSTCR3_SRST32_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 401 | |
| bogdanm | 92:4fc01daae5a5 | 402 | #define CPG_RRAMKP_RRAMKP0_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 403 | #define CPG_RRAMKP_RRAMKP1_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 404 | #define CPG_RRAMKP_RRAMKP2_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 405 | #define CPG_RRAMKP_RRAMKP3_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 406 | |
| bogdanm | 92:4fc01daae5a5 | 407 | #define CPG_DSCTR_RAMBOOT_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 408 | #define CPG_DSCTR_EBUSKEEPE_SHIFT (7u) |
| bogdanm | 92:4fc01daae5a5 | 409 | |
| bogdanm | 92:4fc01daae5a5 | 410 | #define CPG_DSSSR_P8_2_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 411 | #define CPG_DSSSR_P9_1_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 412 | #define CPG_DSSSR_P2_15_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 413 | #define CPG_DSSSR_P7_8_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 414 | #define CPG_DSSSR_P5_9_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 415 | #define CPG_DSSSR_P6_4_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 416 | #define CPG_DSSSR_RTCAR_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 417 | #define CPG_DSSSR_NMI_SHIFT (8u) |
| bogdanm | 92:4fc01daae5a5 | 418 | #define CPG_DSSSR_P3_3_SHIFT (9u) |
| bogdanm | 92:4fc01daae5a5 | 419 | #define CPG_DSSSR_P8_7_SHIFT (10u) |
| bogdanm | 92:4fc01daae5a5 | 420 | #define CPG_DSSSR_P2_12_SHIFT (11u) |
| bogdanm | 92:4fc01daae5a5 | 421 | #define CPG_DSSSR_P3_1_SHIFT (12u) |
| bogdanm | 92:4fc01daae5a5 | 422 | #define CPG_DSSSR_P3_9_SHIFT (13u) |
| bogdanm | 92:4fc01daae5a5 | 423 | #define CPG_DSSSR_P6_2_SHIFT (14u) |
| bogdanm | 92:4fc01daae5a5 | 424 | |
| bogdanm | 92:4fc01daae5a5 | 425 | #define CPG_DSESR_P8_2E_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 426 | #define CPG_DSESR_P9_1E_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 427 | #define CPG_DSESR_P2_15E_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 428 | #define CPG_DSESR_P7_8E_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 429 | #define CPG_DSESR_P5_9E_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 430 | #define CPG_DSESR_P6_4E_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 431 | #define CPG_DSESR_NMIE_SHIFT (8u) |
| bogdanm | 92:4fc01daae5a5 | 432 | #define CPG_DSESR_P3_3E_SHIFT (9u) |
| bogdanm | 92:4fc01daae5a5 | 433 | #define CPG_DSESR_P8_7E_SHIFT (10u) |
| bogdanm | 92:4fc01daae5a5 | 434 | #define CPG_DSESR_P2_12E_SHIFT (11u) |
| bogdanm | 92:4fc01daae5a5 | 435 | #define CPG_DSESR_P3_1E_SHIFT (12u) |
| bogdanm | 92:4fc01daae5a5 | 436 | #define CPG_DSESR_P3_9E_SHIFT (13u) |
| bogdanm | 92:4fc01daae5a5 | 437 | #define CPG_DSESR_P6_2E_SHIFT (14u) |
| bogdanm | 92:4fc01daae5a5 | 438 | |
| bogdanm | 92:4fc01daae5a5 | 439 | #define CPG_DSFR_P8_2F_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 440 | #define CPG_DSFR_P9_1F_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 441 | #define CPG_DSFR_P2_15F_SHIFT (2u) |
| bogdanm | 92:4fc01daae5a5 | 442 | #define CPG_DSFR_P7_8F_SHIFT (3u) |
| bogdanm | 92:4fc01daae5a5 | 443 | #define CPG_DSFR_P5_9F_SHIFT (4u) |
| bogdanm | 92:4fc01daae5a5 | 444 | #define CPG_DSFR_P6_4F_SHIFT (5u) |
| bogdanm | 92:4fc01daae5a5 | 445 | #define CPG_DSFR_RTCARF_SHIFT (6u) |
| bogdanm | 92:4fc01daae5a5 | 446 | #define CPG_DSFR_NMIF_SHIFT (8u) |
| bogdanm | 92:4fc01daae5a5 | 447 | #define CPG_DSFR_P3_3F_SHIFT (9u) |
| bogdanm | 92:4fc01daae5a5 | 448 | #define CPG_DSFR_P8_7F_SHIFT (10u) |
| bogdanm | 92:4fc01daae5a5 | 449 | #define CPG_DSFR_P2_12F_SHIFT (11u) |
| bogdanm | 92:4fc01daae5a5 | 450 | #define CPG_DSFR_P3_1F_SHIFT (12u) |
| bogdanm | 92:4fc01daae5a5 | 451 | #define CPG_DSFR_P3_9F_SHIFT (13u) |
| bogdanm | 92:4fc01daae5a5 | 452 | #define CPG_DSFR_P6_2F_SHIFT (14u) |
| bogdanm | 92:4fc01daae5a5 | 453 | #define CPG_DSFR_IOKEEP_SHIFT (15u) |
| bogdanm | 92:4fc01daae5a5 | 454 | |
| bogdanm | 92:4fc01daae5a5 | 455 | #define CPG_XTALCTR_GAIN0_SHIFT (0u) |
| bogdanm | 92:4fc01daae5a5 | 456 | #define CPG_XTALCTR_GAIN1_SHIFT (1u) |
| bogdanm | 92:4fc01daae5a5 | 457 | |
| bogdanm | 92:4fc01daae5a5 | 458 | |
| bogdanm | 92:4fc01daae5a5 | 459 | #endif /* CPG_IOBITMASK_H */ |
| bogdanm | 92:4fc01daae5a5 | 460 | |
| bogdanm | 92:4fc01daae5a5 | 461 | /* End of File */ |