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TARGET_NUCLEO_F091RC/stm32f091xc.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
93:e188a91d3eaa 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**
Kojto 90:cb3d968589d8 2 ******************************************************************************
Kojto 90:cb3d968589d8 3 * @file stm32f091xc.h
Kojto 90:cb3d968589d8 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V2.2.0
Kojto 93:e188a91d3eaa 6 * @date 05-December-2014
Kojto 90:cb3d968589d8 7 * @brief CMSIS STM32F091xC devices Peripheral Access Layer Header File.
Kojto 90:cb3d968589d8 8 *
Kojto 90:cb3d968589d8 9 * This file contains:
Kojto 90:cb3d968589d8 10 * - Data structures and the address mapping for all peripherals
Kojto 90:cb3d968589d8 11 * - Peripheral's registers declarations and bits definition
Kojto 90:cb3d968589d8 12 * - Macros to access peripheral’s registers hardware
Kojto 90:cb3d968589d8 13 *
Kojto 90:cb3d968589d8 14 ******************************************************************************
Kojto 90:cb3d968589d8 15 * @attention
Kojto 90:cb3d968589d8 16 *
Kojto 90:cb3d968589d8 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 90:cb3d968589d8 18 *
Kojto 90:cb3d968589d8 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 20 * are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 90:cb3d968589d8 22 * this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 90:cb3d968589d8 24 * this list of conditions and the following disclaimer in the documentation
Kojto 90:cb3d968589d8 25 * and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 90:cb3d968589d8 27 * may be used to endorse or promote products derived from this software
Kojto 90:cb3d968589d8 28 * without specific prior written permission.
Kojto 90:cb3d968589d8 29 *
Kojto 90:cb3d968589d8 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 90:cb3d968589d8 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 90:cb3d968589d8 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 90:cb3d968589d8 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 90:cb3d968589d8 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 90:cb3d968589d8 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 90:cb3d968589d8 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 40 *
Kojto 90:cb3d968589d8 41 ******************************************************************************
Kojto 90:cb3d968589d8 42 */
Kojto 90:cb3d968589d8 43
Kojto 90:cb3d968589d8 44 /** @addtogroup CMSIS_Device
Kojto 90:cb3d968589d8 45 * @{
Kojto 90:cb3d968589d8 46 */
Kojto 90:cb3d968589d8 47
Kojto 90:cb3d968589d8 48 /** @addtogroup stm32f091xc
Kojto 90:cb3d968589d8 49 * @{
Kojto 90:cb3d968589d8 50 */
Kojto 90:cb3d968589d8 51
Kojto 90:cb3d968589d8 52 #ifndef __STM32F091xC_H
Kojto 90:cb3d968589d8 53 #define __STM32F091xC_H
Kojto 90:cb3d968589d8 54
Kojto 90:cb3d968589d8 55 #ifdef __cplusplus
Kojto 90:cb3d968589d8 56 extern "C" {
Kojto 90:cb3d968589d8 57 #endif /* __cplusplus */
Kojto 90:cb3d968589d8 58
Kojto 90:cb3d968589d8 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 90:cb3d968589d8 60 * @{
Kojto 90:cb3d968589d8 61 */
Kojto 90:cb3d968589d8 62
Kojto 90:cb3d968589d8 63 /**
Kojto 90:cb3d968589d8 64 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
Kojto 90:cb3d968589d8 65 */
Kojto 90:cb3d968589d8 66 #define __CM0_REV 0 /*!< Core Revision r0p0 */
Kojto 90:cb3d968589d8 67 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
Kojto 90:cb3d968589d8 68 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
Kojto 90:cb3d968589d8 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 90:cb3d968589d8 70
Kojto 90:cb3d968589d8 71 /**
Kojto 90:cb3d968589d8 72 * @}
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 90:cb3d968589d8 76 * @{
Kojto 90:cb3d968589d8 77 */
Kojto 90:cb3d968589d8 78
Kojto 90:cb3d968589d8 79 /**
Kojto 90:cb3d968589d8 80 * @brief STM32F091xC device Interrupt Number Definition
Kojto 90:cb3d968589d8 81 */
Kojto 90:cb3d968589d8 82 typedef enum
Kojto 90:cb3d968589d8 83 {
Kojto 90:cb3d968589d8 84 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
Kojto 90:cb3d968589d8 85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 90:cb3d968589d8 86 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
Kojto 90:cb3d968589d8 87 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
Kojto 90:cb3d968589d8 88 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
Kojto 90:cb3d968589d8 89 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
Kojto 90:cb3d968589d8 90
Kojto 90:cb3d968589d8 91 /****** STM32F091xC specific Interrupt Numbers **************************************************/
Kojto 90:cb3d968589d8 92 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 90:cb3d968589d8 93 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
Kojto 90:cb3d968589d8 94 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
Kojto 90:cb3d968589d8 95 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
Kojto 90:cb3d968589d8 96 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */
Kojto 90:cb3d968589d8 97 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
Kojto 90:cb3d968589d8 98 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
Kojto 90:cb3d968589d8 99 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
Kojto 90:cb3d968589d8 100 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
Kojto 90:cb3d968589d8 101 DMA1_Ch1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
Kojto 90:cb3d968589d8 102 DMA1_Ch2_3_DMA2_Ch1_2_IRQn = 10, /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */
Kojto 90:cb3d968589d8 103 DMA1_Ch4_7_DMA2_Ch3_5_IRQn = 11, /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts */
Kojto 90:cb3d968589d8 104 ADC1_COMP_IRQn = 12, /*!< ADC, COMP1 and COMP2 Interrupts (EXTI Lines 21 and 22) */
Kojto 90:cb3d968589d8 105 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
Kojto 90:cb3d968589d8 106 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
Kojto 90:cb3d968589d8 107 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
Kojto 90:cb3d968589d8 108 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
Kojto 90:cb3d968589d8 109 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
Kojto 90:cb3d968589d8 110 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
Kojto 90:cb3d968589d8 111 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
Kojto 90:cb3d968589d8 112 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
Kojto 90:cb3d968589d8 113 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
Kojto 90:cb3d968589d8 114 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
Kojto 90:cb3d968589d8 115 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
Kojto 90:cb3d968589d8 116 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
Kojto 90:cb3d968589d8 117 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
Kojto 90:cb3d968589d8 118 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
Kojto 90:cb3d968589d8 119 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
Kojto 90:cb3d968589d8 120 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
Kojto 90:cb3d968589d8 121 USART3_8_IRQn = 29, /*!< USART3 to USART8 global Interrupts */
Kojto 90:cb3d968589d8 122 CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
Kojto 90:cb3d968589d8 123 } IRQn_Type;
Kojto 90:cb3d968589d8 124
Kojto 90:cb3d968589d8 125 /**
Kojto 90:cb3d968589d8 126 * @}
Kojto 90:cb3d968589d8 127 */
Kojto 90:cb3d968589d8 128
Kojto 90:cb3d968589d8 129 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Kojto 90:cb3d968589d8 130 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
Kojto 90:cb3d968589d8 131 #include <stdint.h>
Kojto 90:cb3d968589d8 132
Kojto 90:cb3d968589d8 133 /** @addtogroup Peripheral_registers_structures
Kojto 90:cb3d968589d8 134 * @{
Kojto 90:cb3d968589d8 135 */
Kojto 90:cb3d968589d8 136
Kojto 90:cb3d968589d8 137 /**
Kojto 90:cb3d968589d8 138 * @brief Analog to Digital Converter
Kojto 90:cb3d968589d8 139 */
Kojto 90:cb3d968589d8 140
Kojto 90:cb3d968589d8 141 typedef struct
Kojto 90:cb3d968589d8 142 {
Kojto 90:cb3d968589d8 143 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
Kojto 90:cb3d968589d8 144 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
Kojto 90:cb3d968589d8 145 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
Kojto 90:cb3d968589d8 146 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
Kojto 90:cb3d968589d8 147 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
Kojto 90:cb3d968589d8 148 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
Kojto 90:cb3d968589d8 149 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 90:cb3d968589d8 150 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 90:cb3d968589d8 151 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
Kojto 90:cb3d968589d8 152 uint32_t RESERVED3; /*!< Reserved, 0x24 */
Kojto 90:cb3d968589d8 153 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
Kojto 90:cb3d968589d8 154 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
Kojto 90:cb3d968589d8 155 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
Kojto 90:cb3d968589d8 156 }ADC_TypeDef;
Kojto 90:cb3d968589d8 157
Kojto 90:cb3d968589d8 158 typedef struct
Kojto 90:cb3d968589d8 159 {
Kojto 90:cb3d968589d8 160 __IO uint32_t CCR;
Kojto 90:cb3d968589d8 161 }ADC_Common_TypeDef;
Kojto 90:cb3d968589d8 162
Kojto 90:cb3d968589d8 163 /**
Kojto 90:cb3d968589d8 164 * @brief Controller Area Network TxMailBox
Kojto 90:cb3d968589d8 165 */
Kojto 90:cb3d968589d8 166 typedef struct
Kojto 90:cb3d968589d8 167 {
Kojto 90:cb3d968589d8 168 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 90:cb3d968589d8 169 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 90:cb3d968589d8 170 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 90:cb3d968589d8 171 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 90:cb3d968589d8 172 }CAN_TxMailBox_TypeDef;
Kojto 90:cb3d968589d8 173
Kojto 90:cb3d968589d8 174 /**
Kojto 90:cb3d968589d8 175 * @brief Controller Area Network FIFOMailBox
Kojto 90:cb3d968589d8 176 */
Kojto 90:cb3d968589d8 177 typedef struct
Kojto 90:cb3d968589d8 178 {
Kojto 90:cb3d968589d8 179 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 90:cb3d968589d8 180 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 90:cb3d968589d8 181 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 90:cb3d968589d8 182 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 90:cb3d968589d8 183 }CAN_FIFOMailBox_TypeDef;
Kojto 90:cb3d968589d8 184
Kojto 90:cb3d968589d8 185 /**
Kojto 90:cb3d968589d8 186 * @brief Controller Area Network FilterRegister
Kojto 90:cb3d968589d8 187 */
Kojto 90:cb3d968589d8 188 typedef struct
Kojto 90:cb3d968589d8 189 {
Kojto 90:cb3d968589d8 190 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 90:cb3d968589d8 191 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 90:cb3d968589d8 192 }CAN_FilterRegister_TypeDef;
Kojto 90:cb3d968589d8 193
Kojto 90:cb3d968589d8 194 /**
Kojto 90:cb3d968589d8 195 * @brief Controller Area Network
Kojto 90:cb3d968589d8 196 */
Kojto 90:cb3d968589d8 197 typedef struct
Kojto 90:cb3d968589d8 198 {
Kojto 90:cb3d968589d8 199 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 200 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 201 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 202 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 203 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 204 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 205 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 206 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 207 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 90:cb3d968589d8 208 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 90:cb3d968589d8 209 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 90:cb3d968589d8 210 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 90:cb3d968589d8 211 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 90:cb3d968589d8 212 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 90:cb3d968589d8 213 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 90:cb3d968589d8 214 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 90:cb3d968589d8 215 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 90:cb3d968589d8 216 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 90:cb3d968589d8 217 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 90:cb3d968589d8 218 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 90:cb3d968589d8 219 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 90:cb3d968589d8 220 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 90:cb3d968589d8 221 }CAN_TypeDef;
Kojto 90:cb3d968589d8 222
Kojto 90:cb3d968589d8 223 /**
Kojto 90:cb3d968589d8 224 * @brief HDMI-CEC
Kojto 90:cb3d968589d8 225 */
Kojto 90:cb3d968589d8 226
Kojto 90:cb3d968589d8 227 typedef struct
Kojto 90:cb3d968589d8 228 {
Kojto 90:cb3d968589d8 229 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
Kojto 90:cb3d968589d8 230 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
Kojto 90:cb3d968589d8 231 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
Kojto 90:cb3d968589d8 232 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
Kojto 90:cb3d968589d8 233 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
Kojto 90:cb3d968589d8 234 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
Kojto 90:cb3d968589d8 235 }CEC_TypeDef;
Kojto 90:cb3d968589d8 236
Kojto 90:cb3d968589d8 237 /**
Kojto 90:cb3d968589d8 238 * @brief Comparator
Kojto 90:cb3d968589d8 239 */
Kojto 90:cb3d968589d8 240
Kojto 90:cb3d968589d8 241 typedef struct
Kojto 90:cb3d968589d8 242 {
Kojto 90:cb3d968589d8 243 __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 244 }COMP1_2_TypeDef;
Kojto 90:cb3d968589d8 245
Kojto 90:cb3d968589d8 246 typedef struct
Kojto 90:cb3d968589d8 247 {
Kojto 90:cb3d968589d8 248 __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 249 }COMP_TypeDef;
Kojto 90:cb3d968589d8 250
Kojto 90:cb3d968589d8 251 /**
Kojto 90:cb3d968589d8 252 * @brief CRC calculation unit
Kojto 90:cb3d968589d8 253 */
Kojto 90:cb3d968589d8 254
Kojto 90:cb3d968589d8 255 typedef struct
Kojto 90:cb3d968589d8 256 {
Kojto 90:cb3d968589d8 257 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 258 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 259 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 90:cb3d968589d8 260 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 90:cb3d968589d8 261 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 262 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 90:cb3d968589d8 263 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 264 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 265 }CRC_TypeDef;
Kojto 90:cb3d968589d8 266
Kojto 90:cb3d968589d8 267 /**
Kojto 90:cb3d968589d8 268 * @brief Clock Recovery System
Kojto 90:cb3d968589d8 269 */
Kojto 90:cb3d968589d8 270 typedef struct
Kojto 90:cb3d968589d8 271 {
Kojto 90:cb3d968589d8 272 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 273 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 274 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 275 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 276 }CRS_TypeDef;
Kojto 90:cb3d968589d8 277
Kojto 90:cb3d968589d8 278 /**
Kojto 90:cb3d968589d8 279 * @brief Digital to Analog Converter
Kojto 90:cb3d968589d8 280 */
Kojto 90:cb3d968589d8 281
Kojto 90:cb3d968589d8 282 typedef struct
Kojto 90:cb3d968589d8 283 {
Kojto 90:cb3d968589d8 284 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 285 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 286 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 287 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 288 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 289 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 290 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 291 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 292 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 293 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 294 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 295 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 296 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 90:cb3d968589d8 297 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 90:cb3d968589d8 298 }DAC_TypeDef;
Kojto 90:cb3d968589d8 299
Kojto 90:cb3d968589d8 300 /**
Kojto 90:cb3d968589d8 301 * @brief Debug MCU
Kojto 90:cb3d968589d8 302 */
Kojto 90:cb3d968589d8 303
Kojto 90:cb3d968589d8 304 typedef struct
Kojto 90:cb3d968589d8 305 {
Kojto 90:cb3d968589d8 306 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 90:cb3d968589d8 307 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 308 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 309 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 310 }DBGMCU_TypeDef;
Kojto 90:cb3d968589d8 311
Kojto 90:cb3d968589d8 312 /**
Kojto 90:cb3d968589d8 313 * @brief DMA Controller
Kojto 90:cb3d968589d8 314 */
Kojto 90:cb3d968589d8 315
Kojto 90:cb3d968589d8 316 typedef struct
Kojto 90:cb3d968589d8 317 {
Kojto 90:cb3d968589d8 318 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 90:cb3d968589d8 319 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 90:cb3d968589d8 320 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 90:cb3d968589d8 321 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 90:cb3d968589d8 322 }DMA_Channel_TypeDef;
Kojto 90:cb3d968589d8 323
Kojto 90:cb3d968589d8 324 typedef struct
Kojto 90:cb3d968589d8 325 {
Kojto 90:cb3d968589d8 326 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 327 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 328 uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4 */
Kojto 93:e188a91d3eaa 329 __IO uint32_t CSELR; /*!< Channel selection register, Address offset: 0xA8 */
Kojto 90:cb3d968589d8 330 }DMA_TypeDef;
Kojto 90:cb3d968589d8 331
Kojto 90:cb3d968589d8 332 /**
Kojto 90:cb3d968589d8 333 * @brief External Interrupt/Event Controller
Kojto 90:cb3d968589d8 334 */
Kojto 90:cb3d968589d8 335
Kojto 90:cb3d968589d8 336 typedef struct
Kojto 90:cb3d968589d8 337 {
Kojto 90:cb3d968589d8 338 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 339 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 340 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Kojto 90:cb3d968589d8 341 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 342 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 343 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 344 }EXTI_TypeDef;
Kojto 90:cb3d968589d8 345
Kojto 90:cb3d968589d8 346 /**
Kojto 90:cb3d968589d8 347 * @brief FLASH Registers
Kojto 90:cb3d968589d8 348 */
Kojto 90:cb3d968589d8 349 typedef struct
Kojto 90:cb3d968589d8 350 {
Kojto 90:cb3d968589d8 351 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 352 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 353 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 354 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 355 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 356 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 357 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
Kojto 90:cb3d968589d8 358 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 359 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 360 }FLASH_TypeDef;
Kojto 90:cb3d968589d8 361
Kojto 90:cb3d968589d8 362
Kojto 90:cb3d968589d8 363 /**
Kojto 90:cb3d968589d8 364 * @brief Option Bytes Registers
Kojto 90:cb3d968589d8 365 */
Kojto 90:cb3d968589d8 366 typedef struct
Kojto 90:cb3d968589d8 367 {
Kojto 90:cb3d968589d8 368 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
Kojto 90:cb3d968589d8 369 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
Kojto 90:cb3d968589d8 370 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
Kojto 90:cb3d968589d8 371 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
Kojto 90:cb3d968589d8 372 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
Kojto 90:cb3d968589d8 373 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
Kojto 90:cb3d968589d8 374 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
Kojto 90:cb3d968589d8 375 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
Kojto 90:cb3d968589d8 376 }OB_TypeDef;
Kojto 90:cb3d968589d8 377
Kojto 90:cb3d968589d8 378 /**
Kojto 90:cb3d968589d8 379 * @brief General Purpose I/O
Kojto 90:cb3d968589d8 380 */
Kojto 90:cb3d968589d8 381
Kojto 90:cb3d968589d8 382 typedef struct
Kojto 90:cb3d968589d8 383 {
Kojto 90:cb3d968589d8 384 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 385 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 386 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 387 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 388 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 389 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 390 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
Kojto 90:cb3d968589d8 391 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 392 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
Kojto 90:cb3d968589d8 393 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 394 }GPIO_TypeDef;
Kojto 90:cb3d968589d8 395
Kojto 90:cb3d968589d8 396 /**
Kojto 90:cb3d968589d8 397 * @brief SysTem Configuration
Kojto 90:cb3d968589d8 398 */
Kojto 90:cb3d968589d8 399
Kojto 90:cb3d968589d8 400 typedef struct
Kojto 90:cb3d968589d8 401 {
Kojto 90:cb3d968589d8 402 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 403 uint32_t RESERVED; /*!< Reserved, 0x04 */
Kojto 90:cb3d968589d8 404 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
Kojto 90:cb3d968589d8 405 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
Kojto 90:cb3d968589d8 406 uint32_t RESERVED1[25]; /*!< Reserved + COMP, 0x1C */
Kojto 90:cb3d968589d8 407 __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
Kojto 90:cb3d968589d8 408
Kojto 90:cb3d968589d8 409 }SYSCFG_TypeDef;
Kojto 90:cb3d968589d8 410
Kojto 90:cb3d968589d8 411 /**
Kojto 90:cb3d968589d8 412 * @brief Inter-integrated Circuit Interface
Kojto 90:cb3d968589d8 413 */
Kojto 90:cb3d968589d8 414
Kojto 90:cb3d968589d8 415 typedef struct
Kojto 90:cb3d968589d8 416 {
Kojto 90:cb3d968589d8 417 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 418 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 419 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 420 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 421 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 422 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 423 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 424 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 425 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 426 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 427 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 428 }I2C_TypeDef;
Kojto 90:cb3d968589d8 429
Kojto 90:cb3d968589d8 430 /**
Kojto 90:cb3d968589d8 431 * @brief Independent WATCHDOG
Kojto 90:cb3d968589d8 432 */
Kojto 90:cb3d968589d8 433
Kojto 90:cb3d968589d8 434 typedef struct
Kojto 90:cb3d968589d8 435 {
Kojto 90:cb3d968589d8 436 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 437 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 438 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 439 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 440 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 441 }IWDG_TypeDef;
Kojto 90:cb3d968589d8 442
Kojto 90:cb3d968589d8 443 /**
Kojto 90:cb3d968589d8 444 * @brief Power Control
Kojto 90:cb3d968589d8 445 */
Kojto 90:cb3d968589d8 446
Kojto 90:cb3d968589d8 447 typedef struct
Kojto 90:cb3d968589d8 448 {
Kojto 90:cb3d968589d8 449 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 450 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 451 }PWR_TypeDef;
Kojto 90:cb3d968589d8 452
Kojto 90:cb3d968589d8 453 /**
Kojto 90:cb3d968589d8 454 * @brief Reset and Clock Control
Kojto 90:cb3d968589d8 455 */
Kojto 90:cb3d968589d8 456 typedef struct
Kojto 90:cb3d968589d8 457 {
Kojto 90:cb3d968589d8 458 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 459 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 460 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 461 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 462 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 463 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 464 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 465 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 466 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 467 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 468 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 469 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
Kojto 90:cb3d968589d8 470 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
Kojto 90:cb3d968589d8 471 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
Kojto 90:cb3d968589d8 472 }RCC_TypeDef;
Kojto 90:cb3d968589d8 473
Kojto 90:cb3d968589d8 474 /**
Kojto 90:cb3d968589d8 475 * @brief Real-Time Clock
Kojto 90:cb3d968589d8 476 */
Kojto 90:cb3d968589d8 477
Kojto 90:cb3d968589d8 478 typedef struct
Kojto 90:cb3d968589d8 479 {
Kojto 90:cb3d968589d8 480 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 481 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 482 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 483 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 484 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 485 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 486 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
Kojto 90:cb3d968589d8 487 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 488 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
Kojto 90:cb3d968589d8 489 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 490 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 491 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 492 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 90:cb3d968589d8 493 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 90:cb3d968589d8 494 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 90:cb3d968589d8 495 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 90:cb3d968589d8 496 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 90:cb3d968589d8 497 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 90:cb3d968589d8 498 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
Kojto 90:cb3d968589d8 499 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
Kojto 90:cb3d968589d8 500 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 90:cb3d968589d8 501 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 90:cb3d968589d8 502 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 90:cb3d968589d8 503 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 90:cb3d968589d8 504 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 90:cb3d968589d8 505 }RTC_TypeDef;
Kojto 90:cb3d968589d8 506
Kojto 90:cb3d968589d8 507 /**
Kojto 90:cb3d968589d8 508 * @brief Serial Peripheral Interface
Kojto 90:cb3d968589d8 509 */
Kojto 90:cb3d968589d8 510
Kojto 90:cb3d968589d8 511 typedef struct
Kojto 90:cb3d968589d8 512 {
Kojto 93:e188a91d3eaa 513 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 93:e188a91d3eaa 514 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 93:e188a91d3eaa 515 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 93:e188a91d3eaa 516 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 93:e188a91d3eaa 517 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 93:e188a91d3eaa 518 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 93:e188a91d3eaa 519 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 93:e188a91d3eaa 520 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 93:e188a91d3eaa 521 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 522 }SPI_TypeDef;
Kojto 90:cb3d968589d8 523
Kojto 90:cb3d968589d8 524 /**
Kojto 90:cb3d968589d8 525 * @brief TIM
Kojto 90:cb3d968589d8 526 */
Kojto 90:cb3d968589d8 527 typedef struct
Kojto 90:cb3d968589d8 528 {
Kojto 90:cb3d968589d8 529 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 530 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 531 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 532 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 533 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 534 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 535 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 90:cb3d968589d8 536 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 90:cb3d968589d8 537 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 538 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 539 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 540 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 541 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 90:cb3d968589d8 542 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 90:cb3d968589d8 543 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 90:cb3d968589d8 544 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 90:cb3d968589d8 545 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 90:cb3d968589d8 546 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 90:cb3d968589d8 547 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 90:cb3d968589d8 548 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Kojto 90:cb3d968589d8 549 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 90:cb3d968589d8 550 }TIM_TypeDef;
Kojto 90:cb3d968589d8 551
Kojto 90:cb3d968589d8 552 /**
Kojto 90:cb3d968589d8 553 * @brief Touch Sensing Controller (TSC)
Kojto 90:cb3d968589d8 554 */
Kojto 90:cb3d968589d8 555 typedef struct
Kojto 90:cb3d968589d8 556 {
Kojto 90:cb3d968589d8 557 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 558 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 559 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 560 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 561 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 562 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Kojto 90:cb3d968589d8 563 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 564 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
Kojto 90:cb3d968589d8 565 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 566 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
Kojto 90:cb3d968589d8 567 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 568 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
Kojto 90:cb3d968589d8 569 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
Kojto 90:cb3d968589d8 570 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
Kojto 90:cb3d968589d8 571 }TSC_TypeDef;
Kojto 90:cb3d968589d8 572
Kojto 90:cb3d968589d8 573 /**
Kojto 90:cb3d968589d8 574 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 90:cb3d968589d8 575 */
Kojto 90:cb3d968589d8 576
Kojto 90:cb3d968589d8 577 typedef struct
Kojto 90:cb3d968589d8 578 {
Kojto 90:cb3d968589d8 579 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 580 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 581 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 90:cb3d968589d8 582 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 583 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 584 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 585 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 586 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 587 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 588 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 589 uint16_t RESERVED1; /*!< Reserved, 0x26 */
Kojto 90:cb3d968589d8 590 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 591 uint16_t RESERVED2; /*!< Reserved, 0x2A */
Kojto 90:cb3d968589d8 592 }USART_TypeDef;
Kojto 90:cb3d968589d8 593
Kojto 90:cb3d968589d8 594 /**
Kojto 90:cb3d968589d8 595 * @brief Window WATCHDOG
Kojto 90:cb3d968589d8 596 */
Kojto 90:cb3d968589d8 597 typedef struct
Kojto 90:cb3d968589d8 598 {
Kojto 90:cb3d968589d8 599 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 600 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 601 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 602 }WWDG_TypeDef;
Kojto 90:cb3d968589d8 603
Kojto 90:cb3d968589d8 604 /**
Kojto 90:cb3d968589d8 605 * @}
Kojto 90:cb3d968589d8 606 */
Kojto 90:cb3d968589d8 607
Kojto 90:cb3d968589d8 608 /** @addtogroup Peripheral_memory_map
Kojto 90:cb3d968589d8 609 * @{
Kojto 90:cb3d968589d8 610 */
Kojto 90:cb3d968589d8 611
Kojto 90:cb3d968589d8 612 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
Kojto 90:cb3d968589d8 613 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
Kojto 90:cb3d968589d8 614 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 90:cb3d968589d8 615
Kojto 90:cb3d968589d8 616 /*!< Peripheral memory map */
Kojto 90:cb3d968589d8 617 #define APBPERIPH_BASE PERIPH_BASE
Kojto 90:cb3d968589d8 618 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 90:cb3d968589d8 619 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Kojto 90:cb3d968589d8 620
Kojto 90:cb3d968589d8 621 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
Kojto 90:cb3d968589d8 622 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
Kojto 90:cb3d968589d8 623 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
Kojto 90:cb3d968589d8 624 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
Kojto 90:cb3d968589d8 625 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
Kojto 90:cb3d968589d8 626 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Kojto 90:cb3d968589d8 627 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Kojto 90:cb3d968589d8 628 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Kojto 90:cb3d968589d8 629 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
Kojto 90:cb3d968589d8 630 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
Kojto 90:cb3d968589d8 631 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
Kojto 90:cb3d968589d8 632 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
Kojto 90:cb3d968589d8 633 #define USART5_BASE (APBPERIPH_BASE + 0x00005000)
Kojto 90:cb3d968589d8 634 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Kojto 90:cb3d968589d8 635 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
Kojto 90:cb3d968589d8 636 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
Kojto 90:cb3d968589d8 637 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
Kojto 90:cb3d968589d8 638 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Kojto 90:cb3d968589d8 639 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
Kojto 90:cb3d968589d8 640 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
Kojto 90:cb3d968589d8 641
Kojto 90:cb3d968589d8 642 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Kojto 90:cb3d968589d8 643 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
Kojto 90:cb3d968589d8 644 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Kojto 90:cb3d968589d8 645 #define USART6_BASE (APBPERIPH_BASE + 0x00011400)
Kojto 90:cb3d968589d8 646 #define USART7_BASE (APBPERIPH_BASE + 0x00011800)
Kojto 90:cb3d968589d8 647 #define USART8_BASE (APBPERIPH_BASE + 0x00011C00)
Kojto 90:cb3d968589d8 648 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Kojto 90:cb3d968589d8 649 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Kojto 90:cb3d968589d8 650 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
Kojto 90:cb3d968589d8 651 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Kojto 90:cb3d968589d8 652 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Kojto 90:cb3d968589d8 653 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
Kojto 90:cb3d968589d8 654 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
Kojto 90:cb3d968589d8 655 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
Kojto 90:cb3d968589d8 656 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Kojto 90:cb3d968589d8 657
Kojto 90:cb3d968589d8 658 /*!< AHB1 peripherals */
Kojto 90:cb3d968589d8 659 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Kojto 90:cb3d968589d8 660 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Kojto 90:cb3d968589d8 661 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Kojto 90:cb3d968589d8 662 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Kojto 90:cb3d968589d8 663 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Kojto 90:cb3d968589d8 664 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Kojto 90:cb3d968589d8 665 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
Kojto 90:cb3d968589d8 666 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
Kojto 90:cb3d968589d8 667 #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400)
Kojto 90:cb3d968589d8 668 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
Kojto 90:cb3d968589d8 669 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
Kojto 90:cb3d968589d8 670 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
Kojto 90:cb3d968589d8 671 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
Kojto 90:cb3d968589d8 672 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
Kojto 90:cb3d968589d8 673
Kojto 90:cb3d968589d8 674 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Kojto 90:cb3d968589d8 675 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
Kojto 90:cb3d968589d8 676 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
Kojto 90:cb3d968589d8 677 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Kojto 90:cb3d968589d8 678 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
Kojto 90:cb3d968589d8 679
Kojto 90:cb3d968589d8 680 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Kojto 90:cb3d968589d8 681 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Kojto 90:cb3d968589d8 682 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Kojto 90:cb3d968589d8 683 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
Kojto 90:cb3d968589d8 684 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
Kojto 90:cb3d968589d8 685 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Kojto 90:cb3d968589d8 686
Kojto 90:cb3d968589d8 687 /**
Kojto 90:cb3d968589d8 688 * @}
Kojto 90:cb3d968589d8 689 */
Kojto 90:cb3d968589d8 690
Kojto 90:cb3d968589d8 691 /** @addtogroup Peripheral_declaration
Kojto 90:cb3d968589d8 692 * @{
Kojto 90:cb3d968589d8 693 */
Kojto 90:cb3d968589d8 694
Kojto 90:cb3d968589d8 695 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 90:cb3d968589d8 696 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 90:cb3d968589d8 697 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 90:cb3d968589d8 698 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 90:cb3d968589d8 699 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 90:cb3d968589d8 700 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 90:cb3d968589d8 701 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 90:cb3d968589d8 702 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 90:cb3d968589d8 703 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 90:cb3d968589d8 704 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 90:cb3d968589d8 705 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 90:cb3d968589d8 706 #define USART4 ((USART_TypeDef *) USART4_BASE)
Kojto 90:cb3d968589d8 707 #define USART5 ((USART_TypeDef *) USART5_BASE)
Kojto 90:cb3d968589d8 708 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 90:cb3d968589d8 709 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 90:cb3d968589d8 710 #define CAN ((CAN_TypeDef *) CAN_BASE)
Kojto 90:cb3d968589d8 711 #define CRS ((CRS_TypeDef *) CRS_BASE)
Kojto 90:cb3d968589d8 712 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 90:cb3d968589d8 713 #define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto 90:cb3d968589d8 714 #define CEC ((CEC_TypeDef *) CEC_BASE)
Kojto 90:cb3d968589d8 715 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 90:cb3d968589d8 716 #define COMP ((COMP1_2_TypeDef *) COMP_BASE)
Kojto 90:cb3d968589d8 717 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
Kojto 90:cb3d968589d8 718 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
Kojto 90:cb3d968589d8 719 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 90:cb3d968589d8 720 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 90:cb3d968589d8 721 #define USART7 ((USART_TypeDef *) USART7_BASE)
Kojto 90:cb3d968589d8 722 #define USART8 ((USART_TypeDef *) USART8_BASE)
Kojto 90:cb3d968589d8 723 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 90:cb3d968589d8 724 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 90:cb3d968589d8 725 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 90:cb3d968589d8 726 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 90:cb3d968589d8 727 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 90:cb3d968589d8 728 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Kojto 90:cb3d968589d8 729 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Kojto 90:cb3d968589d8 730 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Kojto 90:cb3d968589d8 731 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 90:cb3d968589d8 732 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 90:cb3d968589d8 733 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 90:cb3d968589d8 734 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 90:cb3d968589d8 735 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 90:cb3d968589d8 736 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 90:cb3d968589d8 737 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 90:cb3d968589d8 738 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Kojto 90:cb3d968589d8 739 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Kojto 90:cb3d968589d8 740 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 90:cb3d968589d8 741 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
Kojto 90:cb3d968589d8 742 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
Kojto 90:cb3d968589d8 743 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
Kojto 90:cb3d968589d8 744 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
Kojto 90:cb3d968589d8 745 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
Kojto 90:cb3d968589d8 746 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 90:cb3d968589d8 747 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 90:cb3d968589d8 748 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 90:cb3d968589d8 749 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 90:cb3d968589d8 750 #define TSC ((TSC_TypeDef *) TSC_BASE)
Kojto 90:cb3d968589d8 751 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 90:cb3d968589d8 752 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 90:cb3d968589d8 753 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 90:cb3d968589d8 754 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 90:cb3d968589d8 755 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 90:cb3d968589d8 756 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 90:cb3d968589d8 757
Kojto 90:cb3d968589d8 758 /**
Kojto 90:cb3d968589d8 759 * @}
Kojto 90:cb3d968589d8 760 */
Kojto 90:cb3d968589d8 761
Kojto 90:cb3d968589d8 762 /** @addtogroup Exported_constants
Kojto 90:cb3d968589d8 763 * @{
Kojto 90:cb3d968589d8 764 */
Kojto 90:cb3d968589d8 765
Kojto 90:cb3d968589d8 766 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 90:cb3d968589d8 767 * @{
Kojto 90:cb3d968589d8 768 */
Kojto 90:cb3d968589d8 769
Kojto 90:cb3d968589d8 770 /******************************************************************************/
Kojto 90:cb3d968589d8 771 /* Peripheral Registers Bits Definition */
Kojto 90:cb3d968589d8 772 /******************************************************************************/
Kojto 90:cb3d968589d8 773 /******************************************************************************/
Kojto 90:cb3d968589d8 774 /* */
Kojto 90:cb3d968589d8 775 /* Analog to Digital Converter (ADC) */
Kojto 90:cb3d968589d8 776 /* */
Kojto 90:cb3d968589d8 777 /******************************************************************************/
Kojto 90:cb3d968589d8 778 /******************** Bits definition for ADC_ISR register ******************/
Kojto 90:cb3d968589d8 779 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
Kojto 90:cb3d968589d8 780 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
Kojto 90:cb3d968589d8 781 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
Kojto 90:cb3d968589d8 782 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
Kojto 90:cb3d968589d8 783 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
Kojto 90:cb3d968589d8 784 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
Kojto 90:cb3d968589d8 785
Kojto 90:cb3d968589d8 786 /* Old EOSEQ bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 787 #define ADC_ISR_EOS ADC_ISR_EOSEQ
Kojto 90:cb3d968589d8 788
Kojto 90:cb3d968589d8 789 /******************** Bits definition for ADC_IER register ******************/
Kojto 90:cb3d968589d8 790 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
Kojto 90:cb3d968589d8 791 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
Kojto 90:cb3d968589d8 792 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
Kojto 90:cb3d968589d8 793 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
Kojto 90:cb3d968589d8 794 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
Kojto 90:cb3d968589d8 795 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
Kojto 90:cb3d968589d8 796
Kojto 90:cb3d968589d8 797 /* Old EOSEQIE bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 798 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
Kojto 90:cb3d968589d8 799
Kojto 90:cb3d968589d8 800 /******************** Bits definition for ADC_CR register *******************/
Kojto 90:cb3d968589d8 801 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
Kojto 90:cb3d968589d8 802 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
Kojto 90:cb3d968589d8 803 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
Kojto 90:cb3d968589d8 804 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
Kojto 90:cb3d968589d8 805 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
Kojto 90:cb3d968589d8 806
Kojto 90:cb3d968589d8 807 /******************* Bits definition for ADC_CFGR1 register *****************/
Kojto 90:cb3d968589d8 808 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 90:cb3d968589d8 809 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 810 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 811 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 90:cb3d968589d8 812 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 90:cb3d968589d8 813 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 90:cb3d968589d8 814 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
Kojto 90:cb3d968589d8 815 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
Kojto 90:cb3d968589d8 816 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
Kojto 90:cb3d968589d8 817 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
Kojto 90:cb3d968589d8 818 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
Kojto 90:cb3d968589d8 819 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
Kojto 90:cb3d968589d8 820 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
Kojto 90:cb3d968589d8 821 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
Kojto 90:cb3d968589d8 822 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 90:cb3d968589d8 823 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 90:cb3d968589d8 824 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
Kojto 90:cb3d968589d8 825 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 90:cb3d968589d8 826 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 90:cb3d968589d8 827 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
Kojto 90:cb3d968589d8 828 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
Kojto 90:cb3d968589d8 829 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
Kojto 90:cb3d968589d8 830 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 90:cb3d968589d8 831 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 90:cb3d968589d8 832 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
Kojto 90:cb3d968589d8 833 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
Kojto 90:cb3d968589d8 834 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
Kojto 90:cb3d968589d8 835
Kojto 90:cb3d968589d8 836 /* Old WAIT bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 837 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
Kojto 90:cb3d968589d8 838
Kojto 90:cb3d968589d8 839 /******************* Bits definition for ADC_CFGR2 register *****************/
Kojto 90:cb3d968589d8 840 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
Kojto 90:cb3d968589d8 841 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
Kojto 90:cb3d968589d8 842 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
Kojto 90:cb3d968589d8 843
Kojto 90:cb3d968589d8 844 /* Old bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 845 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
Kojto 90:cb3d968589d8 846 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
Kojto 90:cb3d968589d8 847
Kojto 90:cb3d968589d8 848 /****************** Bit definition for ADC_SMPR register ********************/
Kojto 90:cb3d968589d8 849 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 90:cb3d968589d8 850 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 90:cb3d968589d8 851 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 90:cb3d968589d8 852 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 90:cb3d968589d8 853
Kojto 90:cb3d968589d8 854 /* Old bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 855 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 90:cb3d968589d8 856 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
Kojto 90:cb3d968589d8 857 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
Kojto 90:cb3d968589d8 858 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
Kojto 90:cb3d968589d8 859
Kojto 90:cb3d968589d8 860 /******************* Bit definition for ADC_TR register ********************/
Kojto 90:cb3d968589d8 861 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
Kojto 90:cb3d968589d8 862 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
Kojto 90:cb3d968589d8 863
Kojto 90:cb3d968589d8 864 /* Old bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 865 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
Kojto 90:cb3d968589d8 866 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
Kojto 90:cb3d968589d8 867
Kojto 90:cb3d968589d8 868 /****************** Bit definition for ADC_CHSELR register ******************/
Kojto 90:cb3d968589d8 869 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
Kojto 90:cb3d968589d8 870 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
Kojto 90:cb3d968589d8 871 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
Kojto 90:cb3d968589d8 872 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
Kojto 90:cb3d968589d8 873 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
Kojto 90:cb3d968589d8 874 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
Kojto 90:cb3d968589d8 875 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
Kojto 90:cb3d968589d8 876 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
Kojto 90:cb3d968589d8 877 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
Kojto 90:cb3d968589d8 878 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
Kojto 90:cb3d968589d8 879 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
Kojto 90:cb3d968589d8 880 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
Kojto 90:cb3d968589d8 881 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
Kojto 90:cb3d968589d8 882 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
Kojto 90:cb3d968589d8 883 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
Kojto 90:cb3d968589d8 884 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
Kojto 90:cb3d968589d8 885 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
Kojto 90:cb3d968589d8 886 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
Kojto 90:cb3d968589d8 887 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
Kojto 90:cb3d968589d8 888
Kojto 90:cb3d968589d8 889 /******************** Bit definition for ADC_DR register ********************/
Kojto 90:cb3d968589d8 890 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
Kojto 90:cb3d968589d8 891
Kojto 90:cb3d968589d8 892 /******************* Bit definition for ADC_CCR register ********************/
Kojto 90:cb3d968589d8 893 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
Kojto 90:cb3d968589d8 894 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
Kojto 90:cb3d968589d8 895 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
Kojto 90:cb3d968589d8 896
Kojto 90:cb3d968589d8 897 /******************************************************************************/
Kojto 90:cb3d968589d8 898 /* */
Kojto 90:cb3d968589d8 899 /* Controller Area Network (CAN ) */
Kojto 90:cb3d968589d8 900 /* */
Kojto 90:cb3d968589d8 901 /******************************************************************************/
Kojto 90:cb3d968589d8 902 /*!<CAN control and status registers */
Kojto 90:cb3d968589d8 903 /******************* Bit definition for CAN_MCR register ********************/
Kojto 90:cb3d968589d8 904 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
Kojto 90:cb3d968589d8 905 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
Kojto 90:cb3d968589d8 906 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
Kojto 90:cb3d968589d8 907 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
Kojto 90:cb3d968589d8 908 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
Kojto 90:cb3d968589d8 909 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
Kojto 90:cb3d968589d8 910 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
Kojto 90:cb3d968589d8 911 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
Kojto 90:cb3d968589d8 912 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
Kojto 90:cb3d968589d8 913
Kojto 90:cb3d968589d8 914 /******************* Bit definition for CAN_MSR register ********************/
Kojto 90:cb3d968589d8 915 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
Kojto 90:cb3d968589d8 916 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
Kojto 90:cb3d968589d8 917 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
Kojto 90:cb3d968589d8 918 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
Kojto 90:cb3d968589d8 919 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
Kojto 90:cb3d968589d8 920 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
Kojto 90:cb3d968589d8 921 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
Kojto 90:cb3d968589d8 922 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
Kojto 90:cb3d968589d8 923 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
Kojto 90:cb3d968589d8 924
Kojto 90:cb3d968589d8 925 /******************* Bit definition for CAN_TSR register ********************/
Kojto 90:cb3d968589d8 926 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
Kojto 90:cb3d968589d8 927 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
Kojto 90:cb3d968589d8 928 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
Kojto 90:cb3d968589d8 929 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
Kojto 90:cb3d968589d8 930 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
Kojto 90:cb3d968589d8 931 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
Kojto 90:cb3d968589d8 932 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
Kojto 90:cb3d968589d8 933 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
Kojto 90:cb3d968589d8 934 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
Kojto 90:cb3d968589d8 935 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
Kojto 90:cb3d968589d8 936 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
Kojto 90:cb3d968589d8 937 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
Kojto 90:cb3d968589d8 938 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
Kojto 90:cb3d968589d8 939 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
Kojto 90:cb3d968589d8 940 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
Kojto 90:cb3d968589d8 941 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
Kojto 90:cb3d968589d8 942
Kojto 90:cb3d968589d8 943 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
Kojto 90:cb3d968589d8 944 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
Kojto 90:cb3d968589d8 945 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
Kojto 90:cb3d968589d8 946 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
Kojto 90:cb3d968589d8 947
Kojto 90:cb3d968589d8 948 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
Kojto 90:cb3d968589d8 949 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 90:cb3d968589d8 950 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 90:cb3d968589d8 951 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 90:cb3d968589d8 952
Kojto 90:cb3d968589d8 953 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 90:cb3d968589d8 954 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
Kojto 90:cb3d968589d8 955 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
Kojto 90:cb3d968589d8 956 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
Kojto 90:cb3d968589d8 957 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
Kojto 90:cb3d968589d8 958
Kojto 90:cb3d968589d8 959 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 90:cb3d968589d8 960 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
Kojto 90:cb3d968589d8 961 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
Kojto 90:cb3d968589d8 962 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
Kojto 90:cb3d968589d8 963 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
Kojto 90:cb3d968589d8 964
Kojto 90:cb3d968589d8 965 /******************** Bit definition for CAN_IER register *******************/
Kojto 90:cb3d968589d8 966 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 90:cb3d968589d8 967 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
Kojto 90:cb3d968589d8 968 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
Kojto 90:cb3d968589d8 969 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
Kojto 90:cb3d968589d8 970 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
Kojto 90:cb3d968589d8 971 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
Kojto 90:cb3d968589d8 972 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
Kojto 90:cb3d968589d8 973 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
Kojto 90:cb3d968589d8 974 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
Kojto 90:cb3d968589d8 975 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
Kojto 90:cb3d968589d8 976 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
Kojto 90:cb3d968589d8 977 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
Kojto 90:cb3d968589d8 978 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
Kojto 90:cb3d968589d8 979 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
Kojto 90:cb3d968589d8 980
Kojto 90:cb3d968589d8 981 /******************** Bit definition for CAN_ESR register *******************/
Kojto 90:cb3d968589d8 982 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
Kojto 90:cb3d968589d8 983 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
Kojto 90:cb3d968589d8 984 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
Kojto 90:cb3d968589d8 985
Kojto 90:cb3d968589d8 986 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
Kojto 90:cb3d968589d8 987 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 90:cb3d968589d8 988 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 90:cb3d968589d8 989 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 90:cb3d968589d8 990
Kojto 90:cb3d968589d8 991 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 90:cb3d968589d8 992 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
Kojto 90:cb3d968589d8 993
Kojto 90:cb3d968589d8 994 /******************* Bit definition for CAN_BTR register ********************/
Kojto 90:cb3d968589d8 995 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
Kojto 90:cb3d968589d8 996 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
Kojto 90:cb3d968589d8 997 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
Kojto 90:cb3d968589d8 998 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
Kojto 90:cb3d968589d8 999 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
Kojto 90:cb3d968589d8 1000 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
Kojto 90:cb3d968589d8 1001 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
Kojto 90:cb3d968589d8 1002 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
Kojto 90:cb3d968589d8 1003 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
Kojto 90:cb3d968589d8 1004 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
Kojto 90:cb3d968589d8 1005 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
Kojto 90:cb3d968589d8 1006 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
Kojto 90:cb3d968589d8 1007 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
Kojto 90:cb3d968589d8 1008 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
Kojto 90:cb3d968589d8 1009 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
Kojto 90:cb3d968589d8 1010
Kojto 90:cb3d968589d8 1011 /*!<Mailbox registers */
Kojto 90:cb3d968589d8 1012 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 90:cb3d968589d8 1013 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 90:cb3d968589d8 1014 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 90:cb3d968589d8 1015 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 90:cb3d968589d8 1016 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 90:cb3d968589d8 1017 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1018
Kojto 90:cb3d968589d8 1019 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 90:cb3d968589d8 1020 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 90:cb3d968589d8 1021 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 90:cb3d968589d8 1022 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1023
Kojto 90:cb3d968589d8 1024 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 90:cb3d968589d8 1025 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 90:cb3d968589d8 1026 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 90:cb3d968589d8 1027 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 90:cb3d968589d8 1028 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1029
Kojto 90:cb3d968589d8 1030 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 90:cb3d968589d8 1031 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 90:cb3d968589d8 1032 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 90:cb3d968589d8 1033 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 90:cb3d968589d8 1034 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1035
Kojto 90:cb3d968589d8 1036 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 90:cb3d968589d8 1037 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 90:cb3d968589d8 1038 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 90:cb3d968589d8 1039 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 90:cb3d968589d8 1040 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 90:cb3d968589d8 1041 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1042
Kojto 90:cb3d968589d8 1043 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 90:cb3d968589d8 1044 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 90:cb3d968589d8 1045 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 90:cb3d968589d8 1046 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1047
Kojto 90:cb3d968589d8 1048 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 90:cb3d968589d8 1049 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 90:cb3d968589d8 1050 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 90:cb3d968589d8 1051 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 90:cb3d968589d8 1052 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1053
Kojto 90:cb3d968589d8 1054 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 90:cb3d968589d8 1055 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 90:cb3d968589d8 1056 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 90:cb3d968589d8 1057 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 90:cb3d968589d8 1058 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1059
Kojto 90:cb3d968589d8 1060 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 90:cb3d968589d8 1061 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 90:cb3d968589d8 1062 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 90:cb3d968589d8 1063 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 90:cb3d968589d8 1064 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 90:cb3d968589d8 1065 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1066
Kojto 90:cb3d968589d8 1067 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 90:cb3d968589d8 1068 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 90:cb3d968589d8 1069 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 90:cb3d968589d8 1070 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1071
Kojto 90:cb3d968589d8 1072 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 90:cb3d968589d8 1073 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 90:cb3d968589d8 1074 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 90:cb3d968589d8 1075 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 90:cb3d968589d8 1076 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1077
Kojto 90:cb3d968589d8 1078 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 90:cb3d968589d8 1079 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 90:cb3d968589d8 1080 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 90:cb3d968589d8 1081 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 90:cb3d968589d8 1082 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1083
Kojto 90:cb3d968589d8 1084 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 90:cb3d968589d8 1085 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 90:cb3d968589d8 1086 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 90:cb3d968589d8 1087 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 90:cb3d968589d8 1088 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1089
Kojto 90:cb3d968589d8 1090 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 90:cb3d968589d8 1091 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 90:cb3d968589d8 1092 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 90:cb3d968589d8 1093 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1094
Kojto 90:cb3d968589d8 1095 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 90:cb3d968589d8 1096 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 90:cb3d968589d8 1097 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 90:cb3d968589d8 1098 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 90:cb3d968589d8 1099 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1100
Kojto 90:cb3d968589d8 1101 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 90:cb3d968589d8 1102 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 90:cb3d968589d8 1103 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 90:cb3d968589d8 1104 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 90:cb3d968589d8 1105 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1106
Kojto 90:cb3d968589d8 1107 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 90:cb3d968589d8 1108 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 90:cb3d968589d8 1109 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 90:cb3d968589d8 1110 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 90:cb3d968589d8 1111 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 90:cb3d968589d8 1112
Kojto 90:cb3d968589d8 1113 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 90:cb3d968589d8 1114 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 90:cb3d968589d8 1115 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 90:cb3d968589d8 1116 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 90:cb3d968589d8 1117
Kojto 90:cb3d968589d8 1118 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 90:cb3d968589d8 1119 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 90:cb3d968589d8 1120 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 90:cb3d968589d8 1121 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 90:cb3d968589d8 1122 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 90:cb3d968589d8 1123
Kojto 90:cb3d968589d8 1124 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 90:cb3d968589d8 1125 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 90:cb3d968589d8 1126 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 90:cb3d968589d8 1127 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 90:cb3d968589d8 1128 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 90:cb3d968589d8 1129
Kojto 90:cb3d968589d8 1130 /*!<CAN filter registers */
Kojto 90:cb3d968589d8 1131 /******************* Bit definition for CAN_FMR register ********************/
Kojto 90:cb3d968589d8 1132 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
Kojto 90:cb3d968589d8 1133
Kojto 90:cb3d968589d8 1134 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 90:cb3d968589d8 1135 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
Kojto 90:cb3d968589d8 1136 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
Kojto 90:cb3d968589d8 1137 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
Kojto 90:cb3d968589d8 1138 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
Kojto 90:cb3d968589d8 1139 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
Kojto 90:cb3d968589d8 1140 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
Kojto 90:cb3d968589d8 1141 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
Kojto 90:cb3d968589d8 1142 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
Kojto 90:cb3d968589d8 1143 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
Kojto 90:cb3d968589d8 1144 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
Kojto 90:cb3d968589d8 1145 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
Kojto 90:cb3d968589d8 1146 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
Kojto 90:cb3d968589d8 1147 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
Kojto 90:cb3d968589d8 1148 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
Kojto 90:cb3d968589d8 1149 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
Kojto 90:cb3d968589d8 1150
Kojto 90:cb3d968589d8 1151 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 90:cb3d968589d8 1152 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
Kojto 90:cb3d968589d8 1153 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
Kojto 90:cb3d968589d8 1154 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
Kojto 90:cb3d968589d8 1155 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
Kojto 90:cb3d968589d8 1156 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
Kojto 90:cb3d968589d8 1157 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
Kojto 90:cb3d968589d8 1158 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
Kojto 90:cb3d968589d8 1159 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
Kojto 90:cb3d968589d8 1160 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
Kojto 90:cb3d968589d8 1161 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
Kojto 90:cb3d968589d8 1162 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
Kojto 90:cb3d968589d8 1163 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
Kojto 90:cb3d968589d8 1164 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
Kojto 90:cb3d968589d8 1165 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
Kojto 90:cb3d968589d8 1166 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
Kojto 90:cb3d968589d8 1167
Kojto 90:cb3d968589d8 1168 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 90:cb3d968589d8 1169 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
Kojto 90:cb3d968589d8 1170 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
Kojto 90:cb3d968589d8 1171 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
Kojto 90:cb3d968589d8 1172 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
Kojto 90:cb3d968589d8 1173 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
Kojto 90:cb3d968589d8 1174 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
Kojto 90:cb3d968589d8 1175 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
Kojto 90:cb3d968589d8 1176 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
Kojto 90:cb3d968589d8 1177 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
Kojto 90:cb3d968589d8 1178 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
Kojto 90:cb3d968589d8 1179 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
Kojto 90:cb3d968589d8 1180 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
Kojto 90:cb3d968589d8 1181 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
Kojto 90:cb3d968589d8 1182 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
Kojto 90:cb3d968589d8 1183 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
Kojto 90:cb3d968589d8 1184
Kojto 90:cb3d968589d8 1185 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 90:cb3d968589d8 1186 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
Kojto 90:cb3d968589d8 1187 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
Kojto 90:cb3d968589d8 1188 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
Kojto 90:cb3d968589d8 1189 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
Kojto 90:cb3d968589d8 1190 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
Kojto 90:cb3d968589d8 1191 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
Kojto 90:cb3d968589d8 1192 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
Kojto 90:cb3d968589d8 1193 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
Kojto 90:cb3d968589d8 1194 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
Kojto 90:cb3d968589d8 1195 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
Kojto 90:cb3d968589d8 1196 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
Kojto 90:cb3d968589d8 1197 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
Kojto 90:cb3d968589d8 1198 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
Kojto 90:cb3d968589d8 1199 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
Kojto 90:cb3d968589d8 1200 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
Kojto 90:cb3d968589d8 1201
Kojto 90:cb3d968589d8 1202 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 90:cb3d968589d8 1203 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1204 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1205 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1206 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1207 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1208 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1209 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1210 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1211 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1212 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1213 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1214 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1215 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1216 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1217 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1218 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1219 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1220 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1221 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1222 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1223 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1224 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1225 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1226 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1227 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1228 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1229 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1230 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1231 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1232 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1233 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1234 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1235
Kojto 90:cb3d968589d8 1236 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 90:cb3d968589d8 1237 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1238 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1239 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1240 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1241 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1242 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1243 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1244 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1245 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1246 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1247 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1248 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1249 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1250 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1251 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1252 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1253 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1254 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1255 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1256 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1257 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1258 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1259 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1260 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1261 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1262 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1263 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1264 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1265 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1266 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1267 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1268 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1269
Kojto 90:cb3d968589d8 1270 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 90:cb3d968589d8 1271 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1272 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1273 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1274 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1275 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1276 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1277 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1278 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1279 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1280 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1281 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1282 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1283 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1284 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1285 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1286 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1287 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1288 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1289 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1290 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1291 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1292 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1293 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1294 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1295 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1296 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1297 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1298 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1299 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1300 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1301 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1302 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1303
Kojto 90:cb3d968589d8 1304 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 90:cb3d968589d8 1305 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1306 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1307 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1308 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1309 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1310 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1311 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1312 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1313 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1314 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1315 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1316 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1317 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1318 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1319 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1320 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1321 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1322 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1323 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1324 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1325 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1326 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1327 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1328 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1329 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1330 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1331 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1332 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1333 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1334 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1335 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1336 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1337
Kojto 90:cb3d968589d8 1338 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 90:cb3d968589d8 1339 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1340 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1341 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1342 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1343 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1344 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1345 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1346 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1347 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1348 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1349 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1350 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1351 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1352 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1353 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1354 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1355 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1356 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1357 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1358 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1359 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1360 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1361 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1362 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1363 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1364 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1365 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1366 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1367 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1368 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1369 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1370 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1371
Kojto 90:cb3d968589d8 1372 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 90:cb3d968589d8 1373 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1374 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1375 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1376 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1377 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1378 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1379 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1380 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1381 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1382 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1383 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1384 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1385 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1386 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1387 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1388 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1389 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1390 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1391 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1392 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1393 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1394 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1395 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1396 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1397 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1398 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1399 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1400 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1401 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1402 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1403 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1404 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1405
Kojto 90:cb3d968589d8 1406 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 90:cb3d968589d8 1407 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1408 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1409 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1410 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1411 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1412 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1413 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1414 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1415 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1416 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1417 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1418 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1419 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1420 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1421 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1422 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1423 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1424 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1425 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1426 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1427 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1428 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1429 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1430 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1431 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1432 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1433 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1434 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1435 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1436 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1437 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1438 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1439
Kojto 90:cb3d968589d8 1440 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 90:cb3d968589d8 1441 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1442 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1443 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1444 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1445 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1446 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1447 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1448 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1449 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1450 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1451 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1452 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1453 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1454 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1455 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1456 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1457 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1458 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1459 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1460 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1461 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1462 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1463 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1464 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1465 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1466 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1467 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1468 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1469 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1470 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1471 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1472 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1473
Kojto 90:cb3d968589d8 1474 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 90:cb3d968589d8 1475 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1476 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1477 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1478 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1479 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1480 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1481 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1482 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1483 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1484 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1485 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1486 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1487 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1488 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1489 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1490 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1491 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1492 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1493 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1494 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1495 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1496 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1497 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1498 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1499 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1500 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1501 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1502 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1503 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1504 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1505 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1506 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1507
Kojto 90:cb3d968589d8 1508 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 90:cb3d968589d8 1509 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1510 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1511 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1512 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1513 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1514 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1515 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1516 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1517 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1518 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1519 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1520 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1521 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1522 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1523 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1524 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1525 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1526 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1527 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1528 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1529 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1530 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1531 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1532 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1533 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1534 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1535 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1536 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1537 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1538 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1539 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1540 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1541
Kojto 90:cb3d968589d8 1542 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 90:cb3d968589d8 1543 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1544 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1545 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1546 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1547 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1548 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1549 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1550 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1551 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1552 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1553 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1554 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1555 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1556 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1557 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1558 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1559 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1560 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1561 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1562 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1563 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1564 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1565 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1566 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1567 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1568 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1569 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1570 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1571 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1572 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1573 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1574 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1575
Kojto 90:cb3d968589d8 1576 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 90:cb3d968589d8 1577 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1578 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1579 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1580 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1581 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1582 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1583 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1584 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1585 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1586 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1587 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1588 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1589 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1590 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1591 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1592 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1593 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1594 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1595 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1596 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1597 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1598 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1599 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1600 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1601 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1602 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1603 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1604 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1605 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1606 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1607 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1608 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1609
Kojto 90:cb3d968589d8 1610 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 90:cb3d968589d8 1611 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1612 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1613 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1614 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1615 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1616 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1617 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1618 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1619 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1620 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1621 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1622 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1623 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1624 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1625 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1626 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1627 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1628 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1629 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1630 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1631 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1632 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1633 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1634 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1635 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1636 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1637 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1638 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1639 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1640 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1641 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1642 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1643
Kojto 90:cb3d968589d8 1644 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 90:cb3d968589d8 1645 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1646 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1647 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1648 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1649 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1650 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1651 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1652 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1653 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1654 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1655 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1656 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1657 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1658 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1659 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1660 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1661 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1662 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1663 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1664 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1665 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1666 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1667 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1668 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1669 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1670 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1671 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1672 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1673 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1674 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1675 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1676 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1677
Kojto 90:cb3d968589d8 1678 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 90:cb3d968589d8 1679 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1680 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1681 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1682 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1683 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1684 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1685 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1686 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1687 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1688 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1689 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1690 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1691 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1692 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1693 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1694 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1695 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1696 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1697 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1698 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1699 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1700 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1701 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1702 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1703 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1704 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1705 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1706 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1707 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1708 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1709 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1710 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1711
Kojto 90:cb3d968589d8 1712 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 90:cb3d968589d8 1713 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1714 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1715 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1716 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1717 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1718 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1719 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1720 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1721 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1722 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1723 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1724 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1725 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1726 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1727 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1728 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1729 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1730 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1731 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1732 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1733 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1734 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1735 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1736 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1737 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1738 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1739 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1740 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1741 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1742 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1743 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1744 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1745
Kojto 90:cb3d968589d8 1746 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 90:cb3d968589d8 1747 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1748 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1749 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1750 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1751 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1752 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1753 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1754 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1755 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1756 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1757 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1758 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1759 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1760 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1761 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1762 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1763 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1764 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1765 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1766 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1767 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1768 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1769 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1770 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1771 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1772 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1773 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1774 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1775 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1776 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1777 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1778 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1779
Kojto 90:cb3d968589d8 1780 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 90:cb3d968589d8 1781 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1782 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1783 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1784 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1785 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1786 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1787 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1788 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1789 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1790 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1791 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1792 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1793 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1794 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1795 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1796 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1797 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1798 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1799 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1800 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1801 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1802 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1803 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1804 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1805 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1806 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1807 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1808 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1809 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1810 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1811 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1812 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1813
Kojto 90:cb3d968589d8 1814 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 90:cb3d968589d8 1815 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1816 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1817 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1818 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1819 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1820 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1821 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1822 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1823 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1824 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1825 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1826 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1827 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1828 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1829 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1830 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1831 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1832 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1833 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1834 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1835 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1836 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1837 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1838 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1839 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1840 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1841 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1842 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1843 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1844 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1845 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1846 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1847
Kojto 90:cb3d968589d8 1848 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 90:cb3d968589d8 1849 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1850 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1851 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1852 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1853 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1854 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1855 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1856 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1857 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1858 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1859 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1860 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1861 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1862 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1863 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1864 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1865 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1866 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1867 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1868 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1869 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1870 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1871 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1872 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1873 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1874 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1875 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1876 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1877 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1878 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1879 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1880 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1881
Kojto 90:cb3d968589d8 1882 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 90:cb3d968589d8 1883 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1884 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1885 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1886 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1887 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1888 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1889 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1890 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1891 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1892 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1893 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1894 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1895 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1896 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1897 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1898 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1899 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1900 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1901 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1902 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1903 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1904 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1905 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1906 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1907 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1908 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1909 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1910 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1911 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1912 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1913 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1914 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1915
Kojto 90:cb3d968589d8 1916 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 90:cb3d968589d8 1917 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1918 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1919 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1920 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1921 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1922 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1923 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1924 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1925 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1926 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1927 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1928 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1929 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1930 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1931 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1932 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1933 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1934 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1935 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1936 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1937 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1938 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1939 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1940 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1941 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1942 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1943 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1944 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1945 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1946 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1947 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1948 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1949
Kojto 90:cb3d968589d8 1950 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 90:cb3d968589d8 1951 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1952 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1953 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1954 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1955 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1956 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1957 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1958 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1959 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1960 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1961 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1962 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1963 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1964 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1965 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 1966 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 1967 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 1968 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 1969 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 1970 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 1971 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 1972 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 1973 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 1974 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 1975 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 1976 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 1977 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 1978 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 1979 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 1980 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 1981 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 1982 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 1983
Kojto 90:cb3d968589d8 1984 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 90:cb3d968589d8 1985 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 1986 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 1987 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 1988 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 1989 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 1990 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 1991 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 1992 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 1993 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 1994 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 1995 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 1996 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 1997 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 1998 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 1999 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 2000 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 2001 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 2002 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 2003 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 2004 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 2005 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 2006 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 2007 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 2008 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 2009 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 2010 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 2011 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 2012 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 2013 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 2014 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 2015 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 2016 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2017
Kojto 90:cb3d968589d8 2018 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 90:cb3d968589d8 2019 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 2020 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 2021 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 2022 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 2023 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 2024 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 2025 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 2026 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 2027 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 2028 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 2029 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 2030 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 2031 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 2032 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 2033 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 2034 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 2035 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 2036 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 2037 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 2038 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 2039 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 2040 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 2041 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 2042 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 2043 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 2044 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 2045 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 2046 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 2047 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 2048 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 2049 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 2050 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2051
Kojto 90:cb3d968589d8 2052 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 90:cb3d968589d8 2053 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 2054 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 2055 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 2056 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 2057 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 2058 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 2059 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 2060 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 2061 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 2062 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 2063 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 2064 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 2065 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 2066 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 2067 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 2068 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 2069 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 2070 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 2071 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 2072 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 2073 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 2074 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 2075 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 2076 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 2077 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 2078 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 2079 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 2080 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 2081 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 2082 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 2083 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 2084 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2085
Kojto 90:cb3d968589d8 2086 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 90:cb3d968589d8 2087 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 2088 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 2089 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 2090 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 2091 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 2092 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 2093 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 2094 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 2095 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 2096 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 2097 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 2098 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 2099 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 2100 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 2101 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 2102 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 2103 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 2104 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 2105 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 2106 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 2107 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 2108 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 2109 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 2110 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 2111 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 2112 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 2113 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 2114 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 2115 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 2116 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 2117 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 2118 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2119
Kojto 90:cb3d968589d8 2120 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 90:cb3d968589d8 2121 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 90:cb3d968589d8 2122 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 90:cb3d968589d8 2123 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 90:cb3d968589d8 2124 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 90:cb3d968589d8 2125 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 90:cb3d968589d8 2126 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 90:cb3d968589d8 2127 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 90:cb3d968589d8 2128 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 90:cb3d968589d8 2129 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 90:cb3d968589d8 2130 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 90:cb3d968589d8 2131 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 90:cb3d968589d8 2132 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 90:cb3d968589d8 2133 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 90:cb3d968589d8 2134 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 90:cb3d968589d8 2135 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 90:cb3d968589d8 2136 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 90:cb3d968589d8 2137 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 90:cb3d968589d8 2138 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 90:cb3d968589d8 2139 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 90:cb3d968589d8 2140 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 90:cb3d968589d8 2141 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 90:cb3d968589d8 2142 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 90:cb3d968589d8 2143 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 90:cb3d968589d8 2144 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 90:cb3d968589d8 2145 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 90:cb3d968589d8 2146 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 90:cb3d968589d8 2147 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 90:cb3d968589d8 2148 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 90:cb3d968589d8 2149 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 90:cb3d968589d8 2150 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 90:cb3d968589d8 2151 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 90:cb3d968589d8 2152 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 90:cb3d968589d8 2153
Kojto 90:cb3d968589d8 2154 /******************************************************************************/
Kojto 90:cb3d968589d8 2155 /* */
Kojto 90:cb3d968589d8 2156 /* HDMI-CEC (CEC) */
Kojto 90:cb3d968589d8 2157 /* */
Kojto 90:cb3d968589d8 2158 /******************************************************************************/
Kojto 90:cb3d968589d8 2159
Kojto 90:cb3d968589d8 2160 /******************* Bit definition for CEC_CR register *********************/
Kojto 90:cb3d968589d8 2161 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
Kojto 90:cb3d968589d8 2162 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
Kojto 90:cb3d968589d8 2163 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
Kojto 90:cb3d968589d8 2164
Kojto 90:cb3d968589d8 2165 /******************* Bit definition for CEC_CFGR register *******************/
Kojto 90:cb3d968589d8 2166 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
Kojto 90:cb3d968589d8 2167 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
Kojto 90:cb3d968589d8 2168 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
Kojto 90:cb3d968589d8 2169 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
Kojto 90:cb3d968589d8 2170 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
Kojto 90:cb3d968589d8 2171 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
Kojto 90:cb3d968589d8 2172 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
Kojto 90:cb3d968589d8 2173 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
Kojto 90:cb3d968589d8 2174 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
Kojto 90:cb3d968589d8 2175
Kojto 90:cb3d968589d8 2176 /******************* Bit definition for CEC_TXDR register *******************/
Kojto 90:cb3d968589d8 2177 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
Kojto 90:cb3d968589d8 2178
Kojto 90:cb3d968589d8 2179 /******************* Bit definition for CEC_RXDR register *******************/
Kojto 90:cb3d968589d8 2180 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
Kojto 90:cb3d968589d8 2181
Kojto 90:cb3d968589d8 2182 /******************* Bit definition for CEC_ISR register ********************/
Kojto 90:cb3d968589d8 2183 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
Kojto 90:cb3d968589d8 2184 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
Kojto 90:cb3d968589d8 2185 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
Kojto 90:cb3d968589d8 2186 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
Kojto 90:cb3d968589d8 2187 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
Kojto 90:cb3d968589d8 2188 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
Kojto 90:cb3d968589d8 2189 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
Kojto 90:cb3d968589d8 2190 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
Kojto 90:cb3d968589d8 2191 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
Kojto 90:cb3d968589d8 2192 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
Kojto 90:cb3d968589d8 2193 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
Kojto 90:cb3d968589d8 2194 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
Kojto 90:cb3d968589d8 2195 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
Kojto 90:cb3d968589d8 2196
Kojto 90:cb3d968589d8 2197 /******************* Bit definition for CEC_IER register ********************/
Kojto 90:cb3d968589d8 2198 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
Kojto 90:cb3d968589d8 2199 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
Kojto 90:cb3d968589d8 2200 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
Kojto 90:cb3d968589d8 2201 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
Kojto 90:cb3d968589d8 2202 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
Kojto 90:cb3d968589d8 2203 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
Kojto 90:cb3d968589d8 2204 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
Kojto 90:cb3d968589d8 2205 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
Kojto 90:cb3d968589d8 2206 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
Kojto 90:cb3d968589d8 2207 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
Kojto 90:cb3d968589d8 2208 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
Kojto 90:cb3d968589d8 2209 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
Kojto 90:cb3d968589d8 2210 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
Kojto 90:cb3d968589d8 2211
Kojto 90:cb3d968589d8 2212
Kojto 90:cb3d968589d8 2213 /******************************************************************************/
Kojto 90:cb3d968589d8 2214 /* */
Kojto 90:cb3d968589d8 2215 /* Analog Comparators (COMP) */
Kojto 90:cb3d968589d8 2216 /* */
Kojto 90:cb3d968589d8 2217 /******************************************************************************/
Kojto 90:cb3d968589d8 2218 /*********************** Bit definition for COMP_CSR register ***************/
Kojto 90:cb3d968589d8 2219 /* COMP1 bits definition */
Kojto 90:cb3d968589d8 2220 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
Kojto 90:cb3d968589d8 2221 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
Kojto 90:cb3d968589d8 2222 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
Kojto 90:cb3d968589d8 2223 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
Kojto 90:cb3d968589d8 2224 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
Kojto 90:cb3d968589d8 2225 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
Kojto 90:cb3d968589d8 2226 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
Kojto 90:cb3d968589d8 2227 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
Kojto 90:cb3d968589d8 2228 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
Kojto 90:cb3d968589d8 2229 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
Kojto 90:cb3d968589d8 2230 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
Kojto 90:cb3d968589d8 2231 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
Kojto 90:cb3d968589d8 2232 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
Kojto 90:cb3d968589d8 2233 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
Kojto 90:cb3d968589d8 2234 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
Kojto 90:cb3d968589d8 2235 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
Kojto 90:cb3d968589d8 2236 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
Kojto 90:cb3d968589d8 2237 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
Kojto 90:cb3d968589d8 2238 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
Kojto 90:cb3d968589d8 2239 /* COMP2 bits definition */
Kojto 90:cb3d968589d8 2240 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
Kojto 90:cb3d968589d8 2241 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
Kojto 90:cb3d968589d8 2242 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
Kojto 90:cb3d968589d8 2243 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
Kojto 90:cb3d968589d8 2244 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
Kojto 90:cb3d968589d8 2245 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
Kojto 90:cb3d968589d8 2246 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
Kojto 90:cb3d968589d8 2247 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
Kojto 90:cb3d968589d8 2248 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
Kojto 90:cb3d968589d8 2249 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
Kojto 90:cb3d968589d8 2250 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
Kojto 90:cb3d968589d8 2251 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
Kojto 90:cb3d968589d8 2252 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
Kojto 90:cb3d968589d8 2253 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
Kojto 90:cb3d968589d8 2254 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
Kojto 90:cb3d968589d8 2255 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
Kojto 90:cb3d968589d8 2256 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
Kojto 90:cb3d968589d8 2257 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
Kojto 90:cb3d968589d8 2258 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
Kojto 90:cb3d968589d8 2259 /* COMPx bits definition */
Kojto 90:cb3d968589d8 2260 #define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
Kojto 90:cb3d968589d8 2261 #define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
Kojto 90:cb3d968589d8 2262 #define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
Kojto 90:cb3d968589d8 2263 #define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
Kojto 90:cb3d968589d8 2264 #define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
Kojto 90:cb3d968589d8 2265 #define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
Kojto 90:cb3d968589d8 2266 #define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
Kojto 90:cb3d968589d8 2267 #define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
Kojto 90:cb3d968589d8 2268 #define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
Kojto 90:cb3d968589d8 2269 #define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
Kojto 90:cb3d968589d8 2270 #define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
Kojto 90:cb3d968589d8 2271 #define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
Kojto 90:cb3d968589d8 2272 #define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
Kojto 90:cb3d968589d8 2273 #define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
Kojto 90:cb3d968589d8 2274 #define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
Kojto 90:cb3d968589d8 2275 #define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
Kojto 90:cb3d968589d8 2276 #define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
Kojto 90:cb3d968589d8 2277 #define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
Kojto 90:cb3d968589d8 2278
Kojto 90:cb3d968589d8 2279 /******************************************************************************/
Kojto 90:cb3d968589d8 2280 /* */
Kojto 90:cb3d968589d8 2281 /* CRC calculation unit (CRC) */
Kojto 90:cb3d968589d8 2282 /* */
Kojto 90:cb3d968589d8 2283 /******************************************************************************/
Kojto 90:cb3d968589d8 2284 /******************* Bit definition for CRC_DR register *********************/
Kojto 90:cb3d968589d8 2285 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 90:cb3d968589d8 2286
Kojto 90:cb3d968589d8 2287 /******************* Bit definition for CRC_IDR register ********************/
Kojto 90:cb3d968589d8 2288 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 90:cb3d968589d8 2289
Kojto 90:cb3d968589d8 2290 /******************** Bit definition for CRC_CR register ********************/
Kojto 90:cb3d968589d8 2291 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
Kojto 90:cb3d968589d8 2292 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
Kojto 90:cb3d968589d8 2293 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
Kojto 90:cb3d968589d8 2294 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
Kojto 90:cb3d968589d8 2295 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
Kojto 90:cb3d968589d8 2296 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
Kojto 90:cb3d968589d8 2297 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
Kojto 90:cb3d968589d8 2298 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
Kojto 90:cb3d968589d8 2299
Kojto 90:cb3d968589d8 2300 /******************* Bit definition for CRC_INIT register *******************/
Kojto 90:cb3d968589d8 2301 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
Kojto 90:cb3d968589d8 2302
Kojto 90:cb3d968589d8 2303 /******************* Bit definition for CRC_POL register ********************/
Kojto 90:cb3d968589d8 2304 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
Kojto 90:cb3d968589d8 2305
Kojto 90:cb3d968589d8 2306 /******************************************************************************/
Kojto 90:cb3d968589d8 2307 /* */
Kojto 90:cb3d968589d8 2308 /* CRS Clock Recovery System */
Kojto 90:cb3d968589d8 2309 /******************************************************************************/
Kojto 90:cb3d968589d8 2310
Kojto 90:cb3d968589d8 2311 /******************* Bit definition for CRS_CR register *********************/
Kojto 90:cb3d968589d8 2312 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
Kojto 90:cb3d968589d8 2313 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
Kojto 90:cb3d968589d8 2314 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
Kojto 90:cb3d968589d8 2315 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
Kojto 90:cb3d968589d8 2316 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
Kojto 90:cb3d968589d8 2317 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
Kojto 90:cb3d968589d8 2318 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
Kojto 90:cb3d968589d8 2319 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
Kojto 90:cb3d968589d8 2320
Kojto 90:cb3d968589d8 2321 /******************* Bit definition for CRS_CFGR register *********************/
Kojto 90:cb3d968589d8 2322 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
Kojto 90:cb3d968589d8 2323 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
Kojto 90:cb3d968589d8 2324
Kojto 90:cb3d968589d8 2325 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
Kojto 90:cb3d968589d8 2326 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
Kojto 90:cb3d968589d8 2327 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
Kojto 90:cb3d968589d8 2328 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
Kojto 90:cb3d968589d8 2329
Kojto 90:cb3d968589d8 2330 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
Kojto 90:cb3d968589d8 2331 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
Kojto 90:cb3d968589d8 2332 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
Kojto 90:cb3d968589d8 2333
Kojto 90:cb3d968589d8 2334 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
Kojto 90:cb3d968589d8 2335
Kojto 90:cb3d968589d8 2336 /******************* Bit definition for CRS_ISR register *********************/
Kojto 90:cb3d968589d8 2337 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
Kojto 90:cb3d968589d8 2338 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
Kojto 90:cb3d968589d8 2339 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
Kojto 90:cb3d968589d8 2340 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
Kojto 90:cb3d968589d8 2341 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
Kojto 90:cb3d968589d8 2342 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
Kojto 90:cb3d968589d8 2343 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
Kojto 90:cb3d968589d8 2344 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
Kojto 90:cb3d968589d8 2345 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
Kojto 90:cb3d968589d8 2346
Kojto 90:cb3d968589d8 2347 /******************* Bit definition for CRS_ICR register *********************/
Kojto 90:cb3d968589d8 2348 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
Kojto 90:cb3d968589d8 2349 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
Kojto 90:cb3d968589d8 2350 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
Kojto 90:cb3d968589d8 2351 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
Kojto 90:cb3d968589d8 2352
Kojto 90:cb3d968589d8 2353 /******************************************************************************/
Kojto 90:cb3d968589d8 2354 /* */
Kojto 90:cb3d968589d8 2355 /* Digital to Analog Converter (DAC) */
Kojto 90:cb3d968589d8 2356 /* */
Kojto 90:cb3d968589d8 2357 /******************************************************************************/
Kojto 90:cb3d968589d8 2358 /******************** Bit definition for DAC_CR register ********************/
Kojto 90:cb3d968589d8 2359 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
Kojto 90:cb3d968589d8 2360 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
Kojto 90:cb3d968589d8 2361 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
Kojto 90:cb3d968589d8 2362
Kojto 90:cb3d968589d8 2363 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 90:cb3d968589d8 2364 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2365 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2366 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2367
Kojto 90:cb3d968589d8 2368 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 90:cb3d968589d8 2369 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2370 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2371
Kojto 90:cb3d968589d8 2372 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 90:cb3d968589d8 2373 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2374 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2375 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2376 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 90:cb3d968589d8 2377
Kojto 90:cb3d968589d8 2378 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
Kojto 90:cb3d968589d8 2379 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
Kojto 90:cb3d968589d8 2380
Kojto 90:cb3d968589d8 2381 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
Kojto 90:cb3d968589d8 2382 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
Kojto 90:cb3d968589d8 2383 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
Kojto 90:cb3d968589d8 2384
Kojto 90:cb3d968589d8 2385 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 90:cb3d968589d8 2386 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2387 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2388 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2389
Kojto 90:cb3d968589d8 2390 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 90:cb3d968589d8 2391 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2392 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2393
Kojto 90:cb3d968589d8 2394 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 90:cb3d968589d8 2395 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2396 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2397 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2398 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Kojto 90:cb3d968589d8 2399
Kojto 90:cb3d968589d8 2400 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
Kojto 90:cb3d968589d8 2401 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */
Kojto 90:cb3d968589d8 2402
Kojto 90:cb3d968589d8 2403 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 90:cb3d968589d8 2404 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
Kojto 90:cb3d968589d8 2405 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
Kojto 90:cb3d968589d8 2406
Kojto 90:cb3d968589d8 2407 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 90:cb3d968589d8 2408 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
Kojto 90:cb3d968589d8 2409
Kojto 90:cb3d968589d8 2410 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 90:cb3d968589d8 2411 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
Kojto 90:cb3d968589d8 2412
Kojto 90:cb3d968589d8 2413 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 90:cb3d968589d8 2414 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
Kojto 90:cb3d968589d8 2415
Kojto 90:cb3d968589d8 2416 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 90:cb3d968589d8 2417 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
Kojto 90:cb3d968589d8 2418
Kojto 90:cb3d968589d8 2419 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 90:cb3d968589d8 2420 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
Kojto 90:cb3d968589d8 2421
Kojto 90:cb3d968589d8 2422 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 90:cb3d968589d8 2423 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
Kojto 90:cb3d968589d8 2424
Kojto 90:cb3d968589d8 2425 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 90:cb3d968589d8 2426 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
Kojto 90:cb3d968589d8 2427 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
Kojto 90:cb3d968589d8 2428
Kojto 90:cb3d968589d8 2429 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 90:cb3d968589d8 2430 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
Kojto 90:cb3d968589d8 2431 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
Kojto 90:cb3d968589d8 2432
Kojto 90:cb3d968589d8 2433 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 90:cb3d968589d8 2434 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
Kojto 90:cb3d968589d8 2435 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
Kojto 90:cb3d968589d8 2436
Kojto 90:cb3d968589d8 2437 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 90:cb3d968589d8 2438 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
Kojto 90:cb3d968589d8 2439
Kojto 90:cb3d968589d8 2440 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 90:cb3d968589d8 2441 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
Kojto 90:cb3d968589d8 2442
Kojto 90:cb3d968589d8 2443 /******************** Bit definition for DAC_SR register ********************/
Kojto 90:cb3d968589d8 2444 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
Kojto 90:cb3d968589d8 2445 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
Kojto 90:cb3d968589d8 2446
Kojto 90:cb3d968589d8 2447 /******************************************************************************/
Kojto 90:cb3d968589d8 2448 /* */
Kojto 90:cb3d968589d8 2449 /* Debug MCU (DBGMCU) */
Kojto 90:cb3d968589d8 2450 /* */
Kojto 90:cb3d968589d8 2451 /******************************************************************************/
Kojto 90:cb3d968589d8 2452
Kojto 90:cb3d968589d8 2453 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Kojto 90:cb3d968589d8 2454 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
Kojto 90:cb3d968589d8 2455
Kojto 90:cb3d968589d8 2456 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
Kojto 90:cb3d968589d8 2457 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2458 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2459 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2460 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 90:cb3d968589d8 2461 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 90:cb3d968589d8 2462 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
Kojto 90:cb3d968589d8 2463 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
Kojto 90:cb3d968589d8 2464 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
Kojto 90:cb3d968589d8 2465 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
Kojto 90:cb3d968589d8 2466 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
Kojto 90:cb3d968589d8 2467 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
Kojto 90:cb3d968589d8 2468 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
Kojto 90:cb3d968589d8 2469 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
Kojto 90:cb3d968589d8 2470 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
Kojto 90:cb3d968589d8 2471 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
Kojto 90:cb3d968589d8 2472 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
Kojto 90:cb3d968589d8 2473
Kojto 90:cb3d968589d8 2474 /****************** Bit definition for DBGMCU_CR register *******************/
Kojto 90:cb3d968589d8 2475 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
Kojto 90:cb3d968589d8 2476 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
Kojto 90:cb3d968589d8 2477
Kojto 90:cb3d968589d8 2478 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
Kojto 90:cb3d968589d8 2479 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
Kojto 90:cb3d968589d8 2480 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
Kojto 90:cb3d968589d8 2481 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
Kojto 90:cb3d968589d8 2482 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
Kojto 90:cb3d968589d8 2483 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
Kojto 90:cb3d968589d8 2484 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
Kojto 90:cb3d968589d8 2485 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
Kojto 90:cb3d968589d8 2486 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
Kojto 90:cb3d968589d8 2487 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
Kojto 90:cb3d968589d8 2488 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
Kojto 90:cb3d968589d8 2489
Kojto 90:cb3d968589d8 2490 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
Kojto 90:cb3d968589d8 2491 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
Kojto 90:cb3d968589d8 2492 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
Kojto 90:cb3d968589d8 2493 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
Kojto 90:cb3d968589d8 2494 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
Kojto 90:cb3d968589d8 2495
Kojto 90:cb3d968589d8 2496 /******************************************************************************/
Kojto 90:cb3d968589d8 2497 /* */
Kojto 90:cb3d968589d8 2498 /* DMA Controller (DMA) */
Kojto 90:cb3d968589d8 2499 /* */
Kojto 90:cb3d968589d8 2500 /******************************************************************************/
Kojto 90:cb3d968589d8 2501 /******************* Bit definition for DMA_ISR register ********************/
Kojto 90:cb3d968589d8 2502 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
Kojto 90:cb3d968589d8 2503 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
Kojto 90:cb3d968589d8 2504 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
Kojto 90:cb3d968589d8 2505 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
Kojto 90:cb3d968589d8 2506 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
Kojto 90:cb3d968589d8 2507 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
Kojto 90:cb3d968589d8 2508 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
Kojto 90:cb3d968589d8 2509 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
Kojto 90:cb3d968589d8 2510 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
Kojto 90:cb3d968589d8 2511 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
Kojto 90:cb3d968589d8 2512 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
Kojto 90:cb3d968589d8 2513 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
Kojto 90:cb3d968589d8 2514 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
Kojto 90:cb3d968589d8 2515 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
Kojto 90:cb3d968589d8 2516 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
Kojto 90:cb3d968589d8 2517 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
Kojto 90:cb3d968589d8 2518 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
Kojto 90:cb3d968589d8 2519 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
Kojto 90:cb3d968589d8 2520 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
Kojto 90:cb3d968589d8 2521 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
Kojto 90:cb3d968589d8 2522 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
Kojto 90:cb3d968589d8 2523 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
Kojto 90:cb3d968589d8 2524 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
Kojto 90:cb3d968589d8 2525 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
Kojto 90:cb3d968589d8 2526 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
Kojto 90:cb3d968589d8 2527 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
Kojto 90:cb3d968589d8 2528 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
Kojto 90:cb3d968589d8 2529 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
Kojto 90:cb3d968589d8 2530
Kojto 90:cb3d968589d8 2531 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 90:cb3d968589d8 2532 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
Kojto 90:cb3d968589d8 2533 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
Kojto 90:cb3d968589d8 2534 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
Kojto 90:cb3d968589d8 2535 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
Kojto 90:cb3d968589d8 2536 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
Kojto 90:cb3d968589d8 2537 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
Kojto 90:cb3d968589d8 2538 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
Kojto 90:cb3d968589d8 2539 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
Kojto 90:cb3d968589d8 2540 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
Kojto 90:cb3d968589d8 2541 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
Kojto 90:cb3d968589d8 2542 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
Kojto 90:cb3d968589d8 2543 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
Kojto 90:cb3d968589d8 2544 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
Kojto 90:cb3d968589d8 2545 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
Kojto 90:cb3d968589d8 2546 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
Kojto 90:cb3d968589d8 2547 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
Kojto 90:cb3d968589d8 2548 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
Kojto 90:cb3d968589d8 2549 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
Kojto 90:cb3d968589d8 2550 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
Kojto 90:cb3d968589d8 2551 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
Kojto 90:cb3d968589d8 2552 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
Kojto 90:cb3d968589d8 2553 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
Kojto 90:cb3d968589d8 2554 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
Kojto 90:cb3d968589d8 2555 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
Kojto 90:cb3d968589d8 2556 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
Kojto 90:cb3d968589d8 2557 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
Kojto 90:cb3d968589d8 2558 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
Kojto 90:cb3d968589d8 2559 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
Kojto 90:cb3d968589d8 2560
Kojto 90:cb3d968589d8 2561 /******************* Bit definition for DMA_CCR register ********************/
Kojto 90:cb3d968589d8 2562 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
Kojto 90:cb3d968589d8 2563 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
Kojto 90:cb3d968589d8 2564 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
Kojto 90:cb3d968589d8 2565 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
Kojto 90:cb3d968589d8 2566 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
Kojto 90:cb3d968589d8 2567 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
Kojto 90:cb3d968589d8 2568 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
Kojto 90:cb3d968589d8 2569 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
Kojto 90:cb3d968589d8 2570
Kojto 90:cb3d968589d8 2571 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 90:cb3d968589d8 2572 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2573 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2574
Kojto 90:cb3d968589d8 2575 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
Kojto 90:cb3d968589d8 2576 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2577 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2578
Kojto 90:cb3d968589d8 2579 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 90:cb3d968589d8 2580 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 2581 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2582
Kojto 90:cb3d968589d8 2583 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
Kojto 90:cb3d968589d8 2584
Kojto 90:cb3d968589d8 2585 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 90:cb3d968589d8 2586 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 2587
Kojto 90:cb3d968589d8 2588 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 90:cb3d968589d8 2589 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
Kojto 90:cb3d968589d8 2590
Kojto 90:cb3d968589d8 2591 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 90:cb3d968589d8 2592 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 90:cb3d968589d8 2593
Kojto 93:e188a91d3eaa 2594 /****************** Bit definition for DMA1_CSELR register ********************/
Kojto 93:e188a91d3eaa 2595 #define DMA1_CSELR_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA1 */
Kojto 93:e188a91d3eaa 2596 #define DMA1_CSELR_CH1_ADC ((uint32_t)0x00000001) /*!< Remap ADC on DMA1 Channel 1*/
Kojto 93:e188a91d3eaa 2597 #define DMA1_CSELR_CH1_TIM17_CH1 ((uint32_t)0x00000007) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2598 #define DMA1_CSELR_CH1_TIM17_UP ((uint32_t)0x00000007) /*!< Remap TIM17 up on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2599 #define DMA1_CSELR_CH1_USART1_RX ((uint32_t)0x00000008) /*!< Remap USART1 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2600 #define DMA1_CSELR_CH1_USART2_RX ((uint32_t)0x00000009) /*!< Remap USART2 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2601 #define DMA1_CSELR_CH1_USART3_RX ((uint32_t)0x0000000A) /*!< Remap USART3 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2602 #define DMA1_CSELR_CH1_USART4_RX ((uint32_t)0x0000000B) /*!< Remap USART4 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2603 #define DMA1_CSELR_CH1_USART5_RX ((uint32_t)0x0000000C) /*!< Remap USART5 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2604 #define DMA1_CSELR_CH1_USART6_RX ((uint32_t)0x0000000D) /*!< Remap USART6 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2605 #define DMA1_CSELR_CH1_USART7_RX ((uint32_t)0x0000000E) /*!< Remap USART7 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2606 #define DMA1_CSELR_CH1_USART8_RX ((uint32_t)0x0000000F) /*!< Remap USART8 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 2607 #define DMA1_CSELR_CH2_ADC ((uint32_t)0x00000010) /*!< Remap ADC on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2608 #define DMA1_CSELR_CH2_I2C1_TX ((uint32_t)0x00000020) /*!< Remap I2C1 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2609 #define DMA1_CSELR_CH2_SPI1_RX ((uint32_t)0x00000030) /*!< Remap SPI1 Rx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2610 #define DMA1_CSELR_CH2_TIM1_CH1 ((uint32_t)0x00000040) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2611 #define DMA1_CSELR_CH2_TIM17_CH1 ((uint32_t)0x00000070) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2612 #define DMA1_CSELR_CH2_TIM17_UP ((uint32_t)0x00000070) /*!< Remap TIM17 up on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2613 #define DMA1_CSELR_CH2_USART1_TX ((uint32_t)0x00000080) /*!< Remap USART1 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2614 #define DMA1_CSELR_CH2_USART2_TX ((uint32_t)0x00000090) /*!< Remap USART2 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2615 #define DMA1_CSELR_CH2_USART3_TX ((uint32_t)0x000000A0) /*!< Remap USART3 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2616 #define DMA1_CSELR_CH2_USART4_TX ((uint32_t)0x000000B0) /*!< Remap USART4 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2617 #define DMA1_CSELR_CH2_USART5_TX ((uint32_t)0x000000C0) /*!< Remap USART5 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2618 #define DMA1_CSELR_CH2_USART6_TX ((uint32_t)0x000000D0) /*!< Remap USART6 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2619 #define DMA1_CSELR_CH2_USART7_TX ((uint32_t)0x000000E0) /*!< Remap USART7 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2620 #define DMA1_CSELR_CH2_USART8_TX ((uint32_t)0x000000F0) /*!< Remap USART8 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 2621 #define DMA1_CSELR_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2622 #define DMA1_CSELR_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC Channel 1on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2623 #define DMA1_CSELR_CH3_I2C1_RX ((uint32_t)0x00000200) /*!< Remap I2C1 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2624 #define DMA1_CSELR_CH3_SPI1_TX ((uint32_t)0x00000300) /*!< Remap SPI1 Tx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2625 #define DMA1_CSELR_CH3_TIM1_CH2 ((uint32_t)0x00000400) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2626 #define DMA1_CSELR_CH3_TIM2_CH2 ((uint32_t)0x00000500) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2627 #define DMA1_CSELR_CH3_TIM16_CH1 ((uint32_t)0x00000700) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2628 #define DMA1_CSELR_CH3_TIM16_UP ((uint32_t)0x00000700) /*!< Remap TIM16 up on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2629 #define DMA1_CSELR_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2630 #define DMA1_CSELR_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2631 #define DMA1_CSELR_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2632 #define DMA1_CSELR_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2633 #define DMA1_CSELR_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2634 #define DMA1_CSELR_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2635 #define DMA1_CSELR_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2636 #define DMA1_CSELR_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 2637 #define DMA1_CSELR_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2638 #define DMA1_CSELR_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2639 #define DMA1_CSELR_CH4_I2C2_TX ((uint32_t)0x00002000) /*!< Remap I2C2 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2640 #define DMA1_CSELR_CH4_SPI2_RX ((uint32_t)0x00003000) /*!< Remap SPI2 Rx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2641 #define DMA1_CSELR_CH4_TIM2_CH4 ((uint32_t)0x00005000) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2642 #define DMA1_CSELR_CH4_TIM3_CH1 ((uint32_t)0x00006000) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2643 #define DMA1_CSELR_CH4_TIM3_TRIG ((uint32_t)0x00006000) /*!< Remap TIM3 Trig on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2644 #define DMA1_CSELR_CH4_TIM16_CH1 ((uint32_t)0x00007000) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2645 #define DMA1_CSELR_CH4_TIM16_UP ((uint32_t)0x00007000) /*!< Remap TIM16 up on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2646 #define DMA1_CSELR_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2647 #define DMA1_CSELR_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2648 #define DMA1_CSELR_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2649 #define DMA1_CSELR_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2650 #define DMA1_CSELR_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2651 #define DMA1_CSELR_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2652 #define DMA1_CSELR_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2653 #define DMA1_CSELR_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 2654 #define DMA1_CSELR_CH5_I2C2_RX ((uint32_t)0x00020000) /*!< Remap I2C2 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2655 #define DMA1_CSELR_CH5_SPI2_TX ((uint32_t)0x00030000) /*!< Remap SPI1 Tx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2656 #define DMA1_CSELR_CH5_TIM1_CH3 ((uint32_t)0x00040000) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2657 #define DMA1_CSELR_CH5_USART1_RX ((uint32_t)0x00080000) /*!< Remap USART1 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2658 #define DMA1_CSELR_CH5_USART2_RX ((uint32_t)0x00090000) /*!< Remap USART2 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2659 #define DMA1_CSELR_CH5_USART3_RX ((uint32_t)0x000A0000) /*!< Remap USART3 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2660 #define DMA1_CSELR_CH5_USART4_RX ((uint32_t)0x000B0000) /*!< Remap USART4 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2661 #define DMA1_CSELR_CH5_USART5_RX ((uint32_t)0x000C0000) /*!< Remap USART5 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2662 #define DMA1_CSELR_CH5_USART6_RX ((uint32_t)0x000D0000) /*!< Remap USART6 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2663 #define DMA1_CSELR_CH5_USART7_RX ((uint32_t)0x000E0000) /*!< Remap USART7 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2664 #define DMA1_CSELR_CH5_USART8_RX ((uint32_t)0x000F0000) /*!< Remap USART8 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 2665 #define DMA1_CSELR_CH6_I2C1_TX ((uint32_t)0x00200000) /*!< Remap I2C1 Tx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2666 #define DMA1_CSELR_CH6_SPI2_RX ((uint32_t)0x00300000) /*!< Remap SPI2 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2667 #define DMA1_CSELR_CH6_TIM1_CH1 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2668 #define DMA1_CSELR_CH6_TIM1_CH2 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2669 #define DMA1_CSELR_CH6_TIM1_CH3 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2670 #define DMA1_CSELR_CH6_TIM3_CH1 ((uint32_t)0x00600000) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2671 #define DMA1_CSELR_CH6_TIM3_TRIG ((uint32_t)0x00600000) /*!< Remap TIM3 Trig on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2672 #define DMA1_CSELR_CH6_TIM16_CH1 ((uint32_t)0x00700000) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2673 #define DMA1_CSELR_CH6_TIM16_UP ((uint32_t)0x00700000) /*!< Remap TIM16 up on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2674 #define DMA1_CSELR_CH6_USART1_RX ((uint32_t)0x00800000) /*!< Remap USART1 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2675 #define DMA1_CSELR_CH6_USART2_RX ((uint32_t)0x00900000) /*!< Remap USART2 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2676 #define DMA1_CSELR_CH6_USART3_RX ((uint32_t)0x00A00000) /*!< Remap USART3 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2677 #define DMA1_CSELR_CH6_USART4_RX ((uint32_t)0x00B00000) /*!< Remap USART4 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2678 #define DMA1_CSELR_CH6_USART5_RX ((uint32_t)0x00C00000) /*!< Remap USART5 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2679 #define DMA1_CSELR_CH6_USART6_RX ((uint32_t)0x00D00000) /*!< Remap USART6 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2680 #define DMA1_CSELR_CH6_USART7_RX ((uint32_t)0x00E00000) /*!< Remap USART7 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2681 #define DMA1_CSELR_CH6_USART8_RX ((uint32_t)0x00F00000) /*!< Remap USART8 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 2682 #define DMA1_CSELR_CH7_I2C1_RX ((uint32_t)0x02000000) /*!< Remap I2C1 Rx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2683 #define DMA1_CSELR_CH7_SPI2_TX ((uint32_t)0x03000000) /*!< Remap SPI2 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2684 #define DMA1_CSELR_CH7_TIM2_CH2 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2685 #define DMA1_CSELR_CH7_TIM2_CH4 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2686 #define DMA1_CSELR_CH7_TIM17_CH1 ((uint32_t)0x07000000) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2687 #define DMA1_CSELR_CH7_TIM17_UP ((uint32_t)0x07000000) /*!< Remap TIM17 up on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2688 #define DMA1_CSELR_CH7_USART1_TX ((uint32_t)0x08000000) /*!< Remap USART1 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2689 #define DMA1_CSELR_CH7_USART2_TX ((uint32_t)0x09000000) /*!< Remap USART2 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2690 #define DMA1_CSELR_CH7_USART3_TX ((uint32_t)0x0A000000) /*!< Remap USART3 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2691 #define DMA1_CSELR_CH7_USART4_TX ((uint32_t)0x0B000000) /*!< Remap USART4 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2692 #define DMA1_CSELR_CH7_USART5_TX ((uint32_t)0x0C000000) /*!< Remap USART5 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2693 #define DMA1_CSELR_CH7_USART6_TX ((uint32_t)0x0D000000) /*!< Remap USART6 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2694 #define DMA1_CSELR_CH7_USART7_TX ((uint32_t)0x0E000000) /*!< Remap USART7 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2695 #define DMA1_CSELR_CH7_USART8_TX ((uint32_t)0x0F000000) /*!< Remap USART8 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 2696
Kojto 93:e188a91d3eaa 2697 /****************** Bit definition for DMA2_CSELR register ********************/
Kojto 93:e188a91d3eaa 2698 #define DMA2_CSELR_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA2 */
Kojto 93:e188a91d3eaa 2699 #define DMA2_CSELR_CH1_I2C2_TX ((uint32_t)0x00000002) /*!< Remap I2C2 TX on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 2700 #define DMA2_CSELR_CH1_USART1_TX ((uint32_t)0x00000008) /*!< Remap USART1 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 2701 #define DMA2_CSELR_CH1_USART2_TX ((uint32_t)0x00000009) /*!< Remap USART2 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 2702 #define DMA2_CSELR_CH1_USART3_TX ((uint32_t)0x0000000A) /*!< Remap USART3 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 2703 #define DMA2_CSELR_CH1_USART4_TX ((uint32_t)0x0000000B) /*!< Remap USART4 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 2704 #define DMA2_CSELR_CH1_USART5_TX ((uint32_t)0x0000000C) /*!< Remap USART5 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 2705 #define DMA2_CSELR_CH1_USART6_TX ((uint32_t)0x0000000D) /*!< Remap USART6 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 2706 #define DMA2_CSELR_CH1_USART7_TX ((uint32_t)0x0000000E) /*!< Remap USART7 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 2707 #define DMA2_CSELR_CH1_USART8_TX ((uint32_t)0x0000000F) /*!< Remap USART8 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 2708 #define DMA2_CSELR_CH2_I2C2_RX ((uint32_t)0x00000020) /*!< Remap I2C2 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 2709 #define DMA2_CSELR_CH2_USART1_RX ((uint32_t)0x00000080) /*!< Remap USART1 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 2710 #define DMA2_CSELR_CH2_USART2_RX ((uint32_t)0x00000090) /*!< Remap USART2 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 2711 #define DMA2_CSELR_CH2_USART3_RX ((uint32_t)0x000000A0) /*!< Remap USART3 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 2712 #define DMA2_CSELR_CH2_USART4_RX ((uint32_t)0x000000B0) /*!< Remap USART4 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 2713 #define DMA2_CSELR_CH2_USART5_RX ((uint32_t)0x000000C0) /*!< Remap USART5 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 2714 #define DMA2_CSELR_CH2_USART6_RX ((uint32_t)0x000000D0) /*!< Remap USART6 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 2715 #define DMA2_CSELR_CH2_USART7_RX ((uint32_t)0x000000E0) /*!< Remap USART7 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 2716 #define DMA2_CSELR_CH2_USART8_RX ((uint32_t)0x000000F0) /*!< Remap USART8 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 2717 #define DMA2_CSELR_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2718 #define DMA2_CSELR_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC channel 1 on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2719 #define DMA2_CSELR_CH3_SPI1_RX ((uint32_t)0x00000300) /*!< Remap SPI1 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2720 #define DMA2_CSELR_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2721 #define DMA2_CSELR_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2722 #define DMA2_CSELR_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2723 #define DMA2_CSELR_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2724 #define DMA2_CSELR_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2725 #define DMA2_CSELR_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2726 #define DMA2_CSELR_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2727 #define DMA2_CSELR_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 2728 #define DMA2_CSELR_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2729 #define DMA2_CSELR_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC channel 2 on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2730 #define DMA2_CSELR_CH4_SPI1_TX ((uint32_t)0x00003000) /*!< Remap SPI1 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2731 #define DMA2_CSELR_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2732 #define DMA2_CSELR_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2733 #define DMA2_CSELR_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2734 #define DMA2_CSELR_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2735 #define DMA2_CSELR_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2736 #define DMA2_CSELR_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2737 #define DMA2_CSELR_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2738 #define DMA2_CSELR_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 2739 #define DMA2_CSELR_CH5_ADC ((uint32_t)0x00010000) /*!< Remap ADC on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 2740 #define DMA2_CSELR_CH5_USART1_TX ((uint32_t)0x00080000) /*!< Remap USART1 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 2741 #define DMA2_CSELR_CH5_USART2_TX ((uint32_t)0x00090000) /*!< Remap USART2 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 2742 #define DMA2_CSELR_CH5_USART3_TX ((uint32_t)0x000A0000) /*!< Remap USART3 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 2743 #define DMA2_CSELR_CH5_USART4_TX ((uint32_t)0x000B0000) /*!< Remap USART4 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 2744 #define DMA2_CSELR_CH5_USART5_TX ((uint32_t)0x000C0000) /*!< Remap USART5 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 2745 #define DMA2_CSELR_CH5_USART6_TX ((uint32_t)0x000D0000) /*!< Remap USART6 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 2746 #define DMA2_CSELR_CH5_USART7_TX ((uint32_t)0x000E0000) /*!< Remap USART7 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 2747 #define DMA2_CSELR_CH5_USART8_TX ((uint32_t)0x000F0000) /*!< Remap USART8 Tx on DMA2 channel 5 */
Kojto 90:cb3d968589d8 2748
Kojto 90:cb3d968589d8 2749 /******************************************************************************/
Kojto 90:cb3d968589d8 2750 /* */
Kojto 90:cb3d968589d8 2751 /* External Interrupt/Event Controller (EXTI) */
Kojto 90:cb3d968589d8 2752 /* */
Kojto 90:cb3d968589d8 2753 /******************************************************************************/
Kojto 90:cb3d968589d8 2754 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 90:cb3d968589d8 2755 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 90:cb3d968589d8 2756 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 90:cb3d968589d8 2757 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 90:cb3d968589d8 2758 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 90:cb3d968589d8 2759 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 90:cb3d968589d8 2760 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 90:cb3d968589d8 2761 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 90:cb3d968589d8 2762 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 90:cb3d968589d8 2763 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 90:cb3d968589d8 2764 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 90:cb3d968589d8 2765 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 90:cb3d968589d8 2766 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 90:cb3d968589d8 2767 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 90:cb3d968589d8 2768 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 90:cb3d968589d8 2769 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 90:cb3d968589d8 2770 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 90:cb3d968589d8 2771 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 90:cb3d968589d8 2772 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 90:cb3d968589d8 2773 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 93:e188a91d3eaa 2774 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
Kojto 90:cb3d968589d8 2775 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Kojto 90:cb3d968589d8 2776 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Kojto 90:cb3d968589d8 2777 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
Kojto 90:cb3d968589d8 2778 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
Kojto 93:e188a91d3eaa 2779 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
Kojto 90:cb3d968589d8 2780 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
Kojto 93:e188a91d3eaa 2781 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
Kojto 93:e188a91d3eaa 2782 #define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
Kojto 90:cb3d968589d8 2783
Kojto 90:cb3d968589d8 2784 /****************** Bit definition for EXTI_EMR register ********************/
Kojto 90:cb3d968589d8 2785 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 90:cb3d968589d8 2786 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 90:cb3d968589d8 2787 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 90:cb3d968589d8 2788 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 90:cb3d968589d8 2789 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 90:cb3d968589d8 2790 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 90:cb3d968589d8 2791 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 90:cb3d968589d8 2792 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 90:cb3d968589d8 2793 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 90:cb3d968589d8 2794 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 90:cb3d968589d8 2795 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 90:cb3d968589d8 2796 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 90:cb3d968589d8 2797 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 90:cb3d968589d8 2798 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 90:cb3d968589d8 2799 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 90:cb3d968589d8 2800 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 90:cb3d968589d8 2801 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 90:cb3d968589d8 2802 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 90:cb3d968589d8 2803 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 93:e188a91d3eaa 2804 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
Kojto 90:cb3d968589d8 2805 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Kojto 90:cb3d968589d8 2806 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Kojto 90:cb3d968589d8 2807 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
Kojto 90:cb3d968589d8 2808 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
Kojto 93:e188a91d3eaa 2809 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
Kojto 90:cb3d968589d8 2810 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
Kojto 93:e188a91d3eaa 2811 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
Kojto 93:e188a91d3eaa 2812 #define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
Kojto 90:cb3d968589d8 2813
Kojto 90:cb3d968589d8 2814 /******************* Bit definition for EXTI_RTSR register ******************/
Kojto 90:cb3d968589d8 2815 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 90:cb3d968589d8 2816 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 90:cb3d968589d8 2817 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 90:cb3d968589d8 2818 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 90:cb3d968589d8 2819 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 90:cb3d968589d8 2820 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 90:cb3d968589d8 2821 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 90:cb3d968589d8 2822 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 90:cb3d968589d8 2823 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 90:cb3d968589d8 2824 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 90:cb3d968589d8 2825 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 90:cb3d968589d8 2826 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 90:cb3d968589d8 2827 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 90:cb3d968589d8 2828 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 90:cb3d968589d8 2829 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 90:cb3d968589d8 2830 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 90:cb3d968589d8 2831 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 90:cb3d968589d8 2832 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 90:cb3d968589d8 2833 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 93:e188a91d3eaa 2834 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
Kojto 93:e188a91d3eaa 2835 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
Kojto 93:e188a91d3eaa 2836 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
Kojto 90:cb3d968589d8 2837
Kojto 90:cb3d968589d8 2838 /******************* Bit definition for EXTI_FTSR register *******************/
Kojto 90:cb3d968589d8 2839 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 90:cb3d968589d8 2840 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 90:cb3d968589d8 2841 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 90:cb3d968589d8 2842 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 90:cb3d968589d8 2843 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 90:cb3d968589d8 2844 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 90:cb3d968589d8 2845 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 90:cb3d968589d8 2846 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 90:cb3d968589d8 2847 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 90:cb3d968589d8 2848 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 90:cb3d968589d8 2849 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 90:cb3d968589d8 2850 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 90:cb3d968589d8 2851 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 90:cb3d968589d8 2852 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 90:cb3d968589d8 2853 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 90:cb3d968589d8 2854 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 90:cb3d968589d8 2855 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 90:cb3d968589d8 2856 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 90:cb3d968589d8 2857 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 93:e188a91d3eaa 2858 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
Kojto 93:e188a91d3eaa 2859 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
Kojto 93:e188a91d3eaa 2860 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
Kojto 90:cb3d968589d8 2861
Kojto 90:cb3d968589d8 2862 /******************* Bit definition for EXTI_SWIER register *******************/
Kojto 90:cb3d968589d8 2863 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 90:cb3d968589d8 2864 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 90:cb3d968589d8 2865 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 90:cb3d968589d8 2866 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 90:cb3d968589d8 2867 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 90:cb3d968589d8 2868 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 90:cb3d968589d8 2869 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 90:cb3d968589d8 2870 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 90:cb3d968589d8 2871 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 90:cb3d968589d8 2872 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 90:cb3d968589d8 2873 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 90:cb3d968589d8 2874 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 90:cb3d968589d8 2875 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 90:cb3d968589d8 2876 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 90:cb3d968589d8 2877 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 90:cb3d968589d8 2878 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 90:cb3d968589d8 2879 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 90:cb3d968589d8 2880 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 90:cb3d968589d8 2881 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 93:e188a91d3eaa 2882 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
Kojto 93:e188a91d3eaa 2883 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
Kojto 93:e188a91d3eaa 2884 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
Kojto 90:cb3d968589d8 2885
Kojto 90:cb3d968589d8 2886 /****************** Bit definition for EXTI_PR register *********************/
Kojto 90:cb3d968589d8 2887 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
Kojto 90:cb3d968589d8 2888 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
Kojto 90:cb3d968589d8 2889 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
Kojto 90:cb3d968589d8 2890 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
Kojto 90:cb3d968589d8 2891 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
Kojto 90:cb3d968589d8 2892 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
Kojto 90:cb3d968589d8 2893 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
Kojto 90:cb3d968589d8 2894 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
Kojto 90:cb3d968589d8 2895 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
Kojto 90:cb3d968589d8 2896 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
Kojto 90:cb3d968589d8 2897 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
Kojto 90:cb3d968589d8 2898 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
Kojto 90:cb3d968589d8 2899 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
Kojto 90:cb3d968589d8 2900 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
Kojto 90:cb3d968589d8 2901 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
Kojto 90:cb3d968589d8 2902 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
Kojto 90:cb3d968589d8 2903 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
Kojto 90:cb3d968589d8 2904 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
Kojto 90:cb3d968589d8 2905 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
Kojto 93:e188a91d3eaa 2906 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
Kojto 93:e188a91d3eaa 2907 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
Kojto 93:e188a91d3eaa 2908 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
Kojto 90:cb3d968589d8 2909
Kojto 90:cb3d968589d8 2910 /******************************************************************************/
Kojto 90:cb3d968589d8 2911 /* */
Kojto 90:cb3d968589d8 2912 /* FLASH and Option Bytes Registers */
Kojto 90:cb3d968589d8 2913 /* */
Kojto 90:cb3d968589d8 2914 /******************************************************************************/
Kojto 90:cb3d968589d8 2915
Kojto 90:cb3d968589d8 2916 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 90:cb3d968589d8 2917 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
Kojto 90:cb3d968589d8 2918
Kojto 90:cb3d968589d8 2919 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
Kojto 90:cb3d968589d8 2920 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
Kojto 90:cb3d968589d8 2921
Kojto 90:cb3d968589d8 2922 /****************** Bit definition for FLASH_KEYR register ******************/
Kojto 90:cb3d968589d8 2923 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
Kojto 90:cb3d968589d8 2924
Kojto 90:cb3d968589d8 2925 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto 90:cb3d968589d8 2926 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
Kojto 90:cb3d968589d8 2927
Kojto 90:cb3d968589d8 2928 /****************** FLASH Keys **********************************************/
Kojto 90:cb3d968589d8 2929 #define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
Kojto 90:cb3d968589d8 2930 #define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
Kojto 90:cb3d968589d8 2931 to unlock the write access to the FPEC. */
Kojto 90:cb3d968589d8 2932
Kojto 90:cb3d968589d8 2933 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
Kojto 90:cb3d968589d8 2934 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
Kojto 90:cb3d968589d8 2935 unlock the write access to the option byte block */
Kojto 90:cb3d968589d8 2936
Kojto 90:cb3d968589d8 2937 /****************** Bit definition for FLASH_SR register *******************/
Kojto 90:cb3d968589d8 2938 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
Kojto 90:cb3d968589d8 2939 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
Kojto 90:cb3d968589d8 2940 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
Kojto 90:cb3d968589d8 2941 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
Kojto 90:cb3d968589d8 2942 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
Kojto 90:cb3d968589d8 2943
Kojto 90:cb3d968589d8 2944 /******************* Bit definition for FLASH_CR register *******************/
Kojto 90:cb3d968589d8 2945 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
Kojto 90:cb3d968589d8 2946 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
Kojto 90:cb3d968589d8 2947 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
Kojto 90:cb3d968589d8 2948 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
Kojto 90:cb3d968589d8 2949 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
Kojto 90:cb3d968589d8 2950 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
Kojto 90:cb3d968589d8 2951 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
Kojto 90:cb3d968589d8 2952 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
Kojto 90:cb3d968589d8 2953 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
Kojto 90:cb3d968589d8 2954 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
Kojto 90:cb3d968589d8 2955 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
Kojto 90:cb3d968589d8 2956
Kojto 90:cb3d968589d8 2957 /******************* Bit definition for FLASH_AR register *******************/
Kojto 90:cb3d968589d8 2958 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
Kojto 90:cb3d968589d8 2959
Kojto 90:cb3d968589d8 2960 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 90:cb3d968589d8 2961 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
Kojto 90:cb3d968589d8 2962 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
Kojto 90:cb3d968589d8 2963 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
Kojto 90:cb3d968589d8 2964
Kojto 90:cb3d968589d8 2965 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
Kojto 90:cb3d968589d8 2966 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
Kojto 90:cb3d968589d8 2967 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
Kojto 90:cb3d968589d8 2968 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
Kojto 90:cb3d968589d8 2969 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
Kojto 90:cb3d968589d8 2970 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
Kojto 90:cb3d968589d8 2971
Kojto 90:cb3d968589d8 2972 /* Old BOOT1 bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 2973 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
Kojto 90:cb3d968589d8 2974
Kojto 90:cb3d968589d8 2975 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 2976 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
Kojto 90:cb3d968589d8 2977
Kojto 90:cb3d968589d8 2978 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 90:cb3d968589d8 2979 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
Kojto 90:cb3d968589d8 2980
Kojto 90:cb3d968589d8 2981 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 2982
Kojto 90:cb3d968589d8 2983 /****************** Bit definition for OB_RDP register **********************/
Kojto 90:cb3d968589d8 2984 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
Kojto 90:cb3d968589d8 2985 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
Kojto 90:cb3d968589d8 2986
Kojto 90:cb3d968589d8 2987 /****************** Bit definition for OB_USER register *********************/
Kojto 90:cb3d968589d8 2988 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
Kojto 90:cb3d968589d8 2989 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
Kojto 90:cb3d968589d8 2990
Kojto 90:cb3d968589d8 2991 /****************** Bit definition for OB_WRP0 register *********************/
Kojto 90:cb3d968589d8 2992 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 90:cb3d968589d8 2993 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 2994
Kojto 90:cb3d968589d8 2995 /****************** Bit definition for OB_WRP1 register *********************/
Kojto 90:cb3d968589d8 2996 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Kojto 90:cb3d968589d8 2997 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 2998
Kojto 90:cb3d968589d8 2999 /****************** Bit definition for OB_WRP2 register *********************/
Kojto 90:cb3d968589d8 3000 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 90:cb3d968589d8 3001 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 3002
Kojto 90:cb3d968589d8 3003 /****************** Bit definition for OB_WRP3 register *********************/
Kojto 90:cb3d968589d8 3004 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Kojto 90:cb3d968589d8 3005 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 3006
Kojto 90:cb3d968589d8 3007 /******************************************************************************/
Kojto 90:cb3d968589d8 3008 /* */
Kojto 90:cb3d968589d8 3009 /* General Purpose IOs (GPIO) */
Kojto 90:cb3d968589d8 3010 /* */
Kojto 90:cb3d968589d8 3011 /******************************************************************************/
Kojto 90:cb3d968589d8 3012 /******************* Bit definition for GPIO_MODER register *****************/
Kojto 90:cb3d968589d8 3013 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 90:cb3d968589d8 3014 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3015 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3016 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 90:cb3d968589d8 3017 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3018 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3019 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 90:cb3d968589d8 3020 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3021 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3022 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 90:cb3d968589d8 3023 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3024 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 3025 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 90:cb3d968589d8 3026 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3027 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3028 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 90:cb3d968589d8 3029 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3030 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3031 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 90:cb3d968589d8 3032 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3033 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3034 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 90:cb3d968589d8 3035 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3036 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3037 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 90:cb3d968589d8 3038 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 3039 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 3040 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 90:cb3d968589d8 3041 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 3042 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 90:cb3d968589d8 3043 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 90:cb3d968589d8 3044 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 90:cb3d968589d8 3045 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 90:cb3d968589d8 3046 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 90:cb3d968589d8 3047 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 90:cb3d968589d8 3048 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 90:cb3d968589d8 3049 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 90:cb3d968589d8 3050 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 90:cb3d968589d8 3051 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 90:cb3d968589d8 3052 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 90:cb3d968589d8 3053 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 90:cb3d968589d8 3054 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 90:cb3d968589d8 3055 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 90:cb3d968589d8 3056 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 90:cb3d968589d8 3057 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 90:cb3d968589d8 3058 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 90:cb3d968589d8 3059 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 90:cb3d968589d8 3060 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 90:cb3d968589d8 3061
Kojto 90:cb3d968589d8 3062 /****************** Bit definition for GPIO_OTYPER register *****************/
Kojto 90:cb3d968589d8 3063 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3064 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3065 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3066 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3067 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3068 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3069 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3070 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 3071 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3072 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3073 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3074 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3075 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3076 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3077 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3078 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3079
Kojto 90:cb3d968589d8 3080 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Kojto 90:cb3d968589d8 3081 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 90:cb3d968589d8 3082 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3083 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3084 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 90:cb3d968589d8 3085 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3086 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3087 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 90:cb3d968589d8 3088 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3089 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3090 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 90:cb3d968589d8 3091 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3092 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 3093 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 90:cb3d968589d8 3094 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3095 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3096 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 90:cb3d968589d8 3097 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3098 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3099 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 90:cb3d968589d8 3100 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3101 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3102 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 90:cb3d968589d8 3103 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3104 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3105 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 90:cb3d968589d8 3106 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 3107 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 3108 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 90:cb3d968589d8 3109 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 3110 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 90:cb3d968589d8 3111 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 90:cb3d968589d8 3112 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 90:cb3d968589d8 3113 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 90:cb3d968589d8 3114 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 90:cb3d968589d8 3115 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 90:cb3d968589d8 3116 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 90:cb3d968589d8 3117 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 90:cb3d968589d8 3118 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 90:cb3d968589d8 3119 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 90:cb3d968589d8 3120 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 90:cb3d968589d8 3121 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 90:cb3d968589d8 3122 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 90:cb3d968589d8 3123 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 90:cb3d968589d8 3124 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 90:cb3d968589d8 3125 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 90:cb3d968589d8 3126 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 90:cb3d968589d8 3127 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 90:cb3d968589d8 3128 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 90:cb3d968589d8 3129
Kojto 90:cb3d968589d8 3130 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
Kojto 90:cb3d968589d8 3131 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
Kojto 90:cb3d968589d8 3132 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
Kojto 90:cb3d968589d8 3133 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
Kojto 90:cb3d968589d8 3134 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
Kojto 90:cb3d968589d8 3135 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
Kojto 90:cb3d968589d8 3136 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
Kojto 90:cb3d968589d8 3137 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
Kojto 90:cb3d968589d8 3138 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
Kojto 90:cb3d968589d8 3139 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
Kojto 90:cb3d968589d8 3140 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
Kojto 90:cb3d968589d8 3141 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
Kojto 90:cb3d968589d8 3142 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
Kojto 90:cb3d968589d8 3143 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
Kojto 90:cb3d968589d8 3144 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
Kojto 90:cb3d968589d8 3145 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
Kojto 90:cb3d968589d8 3146 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
Kojto 90:cb3d968589d8 3147 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
Kojto 90:cb3d968589d8 3148 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
Kojto 90:cb3d968589d8 3149 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
Kojto 90:cb3d968589d8 3150 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
Kojto 90:cb3d968589d8 3151 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
Kojto 90:cb3d968589d8 3152 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
Kojto 90:cb3d968589d8 3153 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
Kojto 90:cb3d968589d8 3154 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
Kojto 90:cb3d968589d8 3155 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
Kojto 90:cb3d968589d8 3156 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
Kojto 90:cb3d968589d8 3157 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
Kojto 90:cb3d968589d8 3158 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
Kojto 90:cb3d968589d8 3159 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
Kojto 90:cb3d968589d8 3160 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
Kojto 90:cb3d968589d8 3161 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
Kojto 90:cb3d968589d8 3162 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
Kojto 90:cb3d968589d8 3163 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
Kojto 90:cb3d968589d8 3164 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
Kojto 90:cb3d968589d8 3165 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
Kojto 90:cb3d968589d8 3166 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
Kojto 90:cb3d968589d8 3167 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
Kojto 90:cb3d968589d8 3168 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
Kojto 90:cb3d968589d8 3169 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
Kojto 90:cb3d968589d8 3170 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
Kojto 90:cb3d968589d8 3171 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
Kojto 90:cb3d968589d8 3172 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
Kojto 90:cb3d968589d8 3173 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
Kojto 90:cb3d968589d8 3174 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
Kojto 90:cb3d968589d8 3175 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
Kojto 90:cb3d968589d8 3176 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
Kojto 90:cb3d968589d8 3177 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
Kojto 90:cb3d968589d8 3178 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
Kojto 90:cb3d968589d8 3179
Kojto 90:cb3d968589d8 3180 /******************* Bit definition for GPIO_PUPDR register ******************/
Kojto 90:cb3d968589d8 3181 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 90:cb3d968589d8 3182 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3183 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3184 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 90:cb3d968589d8 3185 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3186 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3187 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 90:cb3d968589d8 3188 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3189 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3190 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 90:cb3d968589d8 3191 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3192 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 3193 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 90:cb3d968589d8 3194 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3195 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3196 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 90:cb3d968589d8 3197 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3198 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3199 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 90:cb3d968589d8 3200 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3201 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3202 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 90:cb3d968589d8 3203 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3204 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3205 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 90:cb3d968589d8 3206 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 3207 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 3208 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 90:cb3d968589d8 3209 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 3210 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 90:cb3d968589d8 3211 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 90:cb3d968589d8 3212 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 90:cb3d968589d8 3213 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 90:cb3d968589d8 3214 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 90:cb3d968589d8 3215 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 90:cb3d968589d8 3216 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 90:cb3d968589d8 3217 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 90:cb3d968589d8 3218 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 90:cb3d968589d8 3219 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 90:cb3d968589d8 3220 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 90:cb3d968589d8 3221 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 90:cb3d968589d8 3222 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 90:cb3d968589d8 3223 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 90:cb3d968589d8 3224 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 90:cb3d968589d8 3225 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 90:cb3d968589d8 3226 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 90:cb3d968589d8 3227 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 90:cb3d968589d8 3228 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 90:cb3d968589d8 3229
Kojto 90:cb3d968589d8 3230 /******************* Bit definition for GPIO_IDR register *******************/
Kojto 90:cb3d968589d8 3231 #define GPIO_IDR_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3232 #define GPIO_IDR_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3233 #define GPIO_IDR_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3234 #define GPIO_IDR_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3235 #define GPIO_IDR_4 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3236 #define GPIO_IDR_5 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3237 #define GPIO_IDR_6 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3238 #define GPIO_IDR_7 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 3239 #define GPIO_IDR_8 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3240 #define GPIO_IDR_9 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3241 #define GPIO_IDR_10 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3242 #define GPIO_IDR_11 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3243 #define GPIO_IDR_12 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3244 #define GPIO_IDR_13 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3245 #define GPIO_IDR_14 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3246 #define GPIO_IDR_15 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3247
Kojto 90:cb3d968589d8 3248 /****************** Bit definition for GPIO_ODR register ********************/
Kojto 90:cb3d968589d8 3249 #define GPIO_ODR_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3250 #define GPIO_ODR_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3251 #define GPIO_ODR_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3252 #define GPIO_ODR_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3253 #define GPIO_ODR_4 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3254 #define GPIO_ODR_5 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3255 #define GPIO_ODR_6 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3256 #define GPIO_ODR_7 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 3257 #define GPIO_ODR_8 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3258 #define GPIO_ODR_9 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3259 #define GPIO_ODR_10 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3260 #define GPIO_ODR_11 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3261 #define GPIO_ODR_12 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3262 #define GPIO_ODR_13 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3263 #define GPIO_ODR_14 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3264 #define GPIO_ODR_15 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3265
Kojto 90:cb3d968589d8 3266 /****************** Bit definition for GPIO_BSRR register ********************/
Kojto 90:cb3d968589d8 3267 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3268 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3269 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3270 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3271 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3272 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3273 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3274 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 3275 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3276 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3277 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3278 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3279 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3280 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3281 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3282 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3283 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 3284 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 3285 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 3286 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 90:cb3d968589d8 3287 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 90:cb3d968589d8 3288 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 90:cb3d968589d8 3289 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 90:cb3d968589d8 3290 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 90:cb3d968589d8 3291 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 90:cb3d968589d8 3292 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 90:cb3d968589d8 3293 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 90:cb3d968589d8 3294 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 90:cb3d968589d8 3295 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 90:cb3d968589d8 3296 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 90:cb3d968589d8 3297 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 90:cb3d968589d8 3298 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 90:cb3d968589d8 3299
Kojto 90:cb3d968589d8 3300 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 90:cb3d968589d8 3301 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3302 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3303 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3304 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3305 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3306 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3307 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3308 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 3309 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3310 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3311 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3312 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3313 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3314 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3315 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3316 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3317 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 3318
Kojto 90:cb3d968589d8 3319 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 90:cb3d968589d8 3320 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
Kojto 90:cb3d968589d8 3321 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
Kojto 90:cb3d968589d8 3322 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
Kojto 90:cb3d968589d8 3323 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
Kojto 90:cb3d968589d8 3324 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
Kojto 90:cb3d968589d8 3325 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
Kojto 90:cb3d968589d8 3326 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
Kojto 90:cb3d968589d8 3327 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
Kojto 90:cb3d968589d8 3328
Kojto 90:cb3d968589d8 3329 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 90:cb3d968589d8 3330 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
Kojto 90:cb3d968589d8 3331 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
Kojto 90:cb3d968589d8 3332 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
Kojto 90:cb3d968589d8 3333 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
Kojto 90:cb3d968589d8 3334 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
Kojto 90:cb3d968589d8 3335 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
Kojto 90:cb3d968589d8 3336 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
Kojto 90:cb3d968589d8 3337 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
Kojto 90:cb3d968589d8 3338
Kojto 90:cb3d968589d8 3339 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 90:cb3d968589d8 3340 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3341 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3342 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3343 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3344 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3345 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3346 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3347 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 3348 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3349 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3350 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3351 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3352 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3353 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3354 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3355 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3356
Kojto 90:cb3d968589d8 3357 /******************************************************************************/
Kojto 90:cb3d968589d8 3358 /* */
Kojto 90:cb3d968589d8 3359 /* Inter-integrated Circuit Interface (I2C) */
Kojto 90:cb3d968589d8 3360 /* */
Kojto 90:cb3d968589d8 3361 /******************************************************************************/
Kojto 90:cb3d968589d8 3362
Kojto 90:cb3d968589d8 3363 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 90:cb3d968589d8 3364 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
Kojto 90:cb3d968589d8 3365 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
Kojto 90:cb3d968589d8 3366 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
Kojto 90:cb3d968589d8 3367 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
Kojto 90:cb3d968589d8 3368 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
Kojto 90:cb3d968589d8 3369 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
Kojto 90:cb3d968589d8 3370 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
Kojto 90:cb3d968589d8 3371 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
Kojto 90:cb3d968589d8 3372 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
Kojto 90:cb3d968589d8 3373 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
Kojto 90:cb3d968589d8 3374 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
Kojto 90:cb3d968589d8 3375 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
Kojto 90:cb3d968589d8 3376 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
Kojto 90:cb3d968589d8 3377 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
Kojto 90:cb3d968589d8 3378 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
Kojto 90:cb3d968589d8 3379 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
Kojto 90:cb3d968589d8 3380 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
Kojto 90:cb3d968589d8 3381 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
Kojto 90:cb3d968589d8 3382 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
Kojto 90:cb3d968589d8 3383 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
Kojto 90:cb3d968589d8 3384 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
Kojto 90:cb3d968589d8 3385
Kojto 90:cb3d968589d8 3386 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 90:cb3d968589d8 3387 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
Kojto 90:cb3d968589d8 3388 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
Kojto 90:cb3d968589d8 3389 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
Kojto 90:cb3d968589d8 3390 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
Kojto 90:cb3d968589d8 3391 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
Kojto 90:cb3d968589d8 3392 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
Kojto 90:cb3d968589d8 3393 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
Kojto 90:cb3d968589d8 3394 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
Kojto 90:cb3d968589d8 3395 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
Kojto 90:cb3d968589d8 3396 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
Kojto 90:cb3d968589d8 3397 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
Kojto 90:cb3d968589d8 3398
Kojto 90:cb3d968589d8 3399 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 90:cb3d968589d8 3400 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
Kojto 90:cb3d968589d8 3401 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
Kojto 90:cb3d968589d8 3402 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
Kojto 90:cb3d968589d8 3403
Kojto 90:cb3d968589d8 3404 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 90:cb3d968589d8 3405 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
Kojto 90:cb3d968589d8 3406 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
Kojto 90:cb3d968589d8 3407 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
Kojto 90:cb3d968589d8 3408
Kojto 90:cb3d968589d8 3409 /******************* Bit definition for I2C_TIMINGR register ****************/
Kojto 90:cb3d968589d8 3410 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
Kojto 90:cb3d968589d8 3411 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
Kojto 90:cb3d968589d8 3412 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
Kojto 90:cb3d968589d8 3413 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
Kojto 90:cb3d968589d8 3414 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
Kojto 90:cb3d968589d8 3415
Kojto 90:cb3d968589d8 3416 /******************* Bit definition for I2C_TIMEOUTR register ****************/
Kojto 90:cb3d968589d8 3417 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
Kojto 90:cb3d968589d8 3418 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
Kojto 90:cb3d968589d8 3419 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
Kojto 90:cb3d968589d8 3420 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
Kojto 90:cb3d968589d8 3421 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
Kojto 90:cb3d968589d8 3422
Kojto 90:cb3d968589d8 3423 /****************** Bit definition for I2C_ISR register ********************/
Kojto 90:cb3d968589d8 3424 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
Kojto 90:cb3d968589d8 3425 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
Kojto 90:cb3d968589d8 3426 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
Kojto 90:cb3d968589d8 3427 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
Kojto 90:cb3d968589d8 3428 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
Kojto 90:cb3d968589d8 3429 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
Kojto 90:cb3d968589d8 3430 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
Kojto 90:cb3d968589d8 3431 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
Kojto 90:cb3d968589d8 3432 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
Kojto 90:cb3d968589d8 3433 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
Kojto 90:cb3d968589d8 3434 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
Kojto 90:cb3d968589d8 3435 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
Kojto 90:cb3d968589d8 3436 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
Kojto 90:cb3d968589d8 3437 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
Kojto 90:cb3d968589d8 3438 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
Kojto 90:cb3d968589d8 3439 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
Kojto 90:cb3d968589d8 3440 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
Kojto 90:cb3d968589d8 3441
Kojto 90:cb3d968589d8 3442 /****************** Bit definition for I2C_ICR register ********************/
Kojto 90:cb3d968589d8 3443 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
Kojto 90:cb3d968589d8 3444 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
Kojto 90:cb3d968589d8 3445 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
Kojto 90:cb3d968589d8 3446 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
Kojto 90:cb3d968589d8 3447 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
Kojto 90:cb3d968589d8 3448 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
Kojto 90:cb3d968589d8 3449 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
Kojto 90:cb3d968589d8 3450 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
Kojto 90:cb3d968589d8 3451 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
Kojto 90:cb3d968589d8 3452
Kojto 90:cb3d968589d8 3453 /****************** Bit definition for I2C_PECR register *******************/
Kojto 90:cb3d968589d8 3454 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
Kojto 90:cb3d968589d8 3455
Kojto 90:cb3d968589d8 3456 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 90:cb3d968589d8 3457 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
Kojto 90:cb3d968589d8 3458
Kojto 90:cb3d968589d8 3459 /****************** Bit definition for I2C_TXDR register *******************/
Kojto 90:cb3d968589d8 3460 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
Kojto 90:cb3d968589d8 3461
Kojto 90:cb3d968589d8 3462 /*****************************************************************************/
Kojto 90:cb3d968589d8 3463 /* */
Kojto 90:cb3d968589d8 3464 /* Independent WATCHDOG (IWDG) */
Kojto 90:cb3d968589d8 3465 /* */
Kojto 90:cb3d968589d8 3466 /*****************************************************************************/
Kojto 90:cb3d968589d8 3467 /******************* Bit definition for IWDG_KR register *******************/
Kojto 90:cb3d968589d8 3468 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
Kojto 90:cb3d968589d8 3469
Kojto 90:cb3d968589d8 3470 /******************* Bit definition for IWDG_PR register *******************/
Kojto 90:cb3d968589d8 3471 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
Kojto 90:cb3d968589d8 3472 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3473 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3474 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
Kojto 90:cb3d968589d8 3475
Kojto 90:cb3d968589d8 3476 /******************* Bit definition for IWDG_RLR register ******************/
Kojto 90:cb3d968589d8 3477 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
Kojto 90:cb3d968589d8 3478
Kojto 90:cb3d968589d8 3479 /******************* Bit definition for IWDG_SR register *******************/
Kojto 90:cb3d968589d8 3480 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
Kojto 90:cb3d968589d8 3481 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
Kojto 90:cb3d968589d8 3482 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
Kojto 90:cb3d968589d8 3483
Kojto 90:cb3d968589d8 3484 /******************* Bit definition for IWDG_KR register *******************/
Kojto 90:cb3d968589d8 3485 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
Kojto 90:cb3d968589d8 3486
Kojto 90:cb3d968589d8 3487 /*****************************************************************************/
Kojto 90:cb3d968589d8 3488 /* */
Kojto 90:cb3d968589d8 3489 /* Power Control (PWR) */
Kojto 90:cb3d968589d8 3490 /* */
Kojto 90:cb3d968589d8 3491 /*****************************************************************************/
Kojto 90:cb3d968589d8 3492
Kojto 90:cb3d968589d8 3493 /******************** Bit definition for PWR_CR register *******************/
Kojto 90:cb3d968589d8 3494 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
Kojto 90:cb3d968589d8 3495 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 90:cb3d968589d8 3496 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 90:cb3d968589d8 3497 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 90:cb3d968589d8 3498 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 90:cb3d968589d8 3499
Kojto 90:cb3d968589d8 3500 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 90:cb3d968589d8 3501 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3502 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3503 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 90:cb3d968589d8 3504
Kojto 90:cb3d968589d8 3505 /*!< PVD level configuration */
Kojto 90:cb3d968589d8 3506 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Kojto 90:cb3d968589d8 3507 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Kojto 90:cb3d968589d8 3508 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Kojto 90:cb3d968589d8 3509 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Kojto 90:cb3d968589d8 3510 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Kojto 90:cb3d968589d8 3511 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Kojto 90:cb3d968589d8 3512 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Kojto 90:cb3d968589d8 3513 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Kojto 90:cb3d968589d8 3514
Kojto 90:cb3d968589d8 3515 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 90:cb3d968589d8 3516
Kojto 90:cb3d968589d8 3517 /******************* Bit definition for PWR_CSR register *******************/
Kojto 90:cb3d968589d8 3518 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 90:cb3d968589d8 3519 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 90:cb3d968589d8 3520 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 90:cb3d968589d8 3521 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
Kojto 90:cb3d968589d8 3522
Kojto 90:cb3d968589d8 3523 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
Kojto 90:cb3d968589d8 3524 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
Kojto 90:cb3d968589d8 3525 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
Kojto 90:cb3d968589d8 3526 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
Kojto 90:cb3d968589d8 3527 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
Kojto 90:cb3d968589d8 3528 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
Kojto 90:cb3d968589d8 3529 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
Kojto 90:cb3d968589d8 3530 #define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
Kojto 90:cb3d968589d8 3531
Kojto 90:cb3d968589d8 3532 /*****************************************************************************/
Kojto 90:cb3d968589d8 3533 /* */
Kojto 90:cb3d968589d8 3534 /* Reset and Clock Control */
Kojto 90:cb3d968589d8 3535 /* */
Kojto 90:cb3d968589d8 3536 /*****************************************************************************/
Kojto 90:cb3d968589d8 3537
Kojto 90:cb3d968589d8 3538 /******************** Bit definition for RCC_CR register *******************/
Kojto 90:cb3d968589d8 3539 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
Kojto 90:cb3d968589d8 3540 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
Kojto 90:cb3d968589d8 3541
Kojto 90:cb3d968589d8 3542 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
Kojto 90:cb3d968589d8 3543 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 90:cb3d968589d8 3544 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 90:cb3d968589d8 3545 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 90:cb3d968589d8 3546 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
Kojto 90:cb3d968589d8 3547 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
Kojto 90:cb3d968589d8 3548
Kojto 90:cb3d968589d8 3549 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
Kojto 90:cb3d968589d8 3550 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 90:cb3d968589d8 3551 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 90:cb3d968589d8 3552 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 90:cb3d968589d8 3553 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 90:cb3d968589d8 3554 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 90:cb3d968589d8 3555 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 90:cb3d968589d8 3556 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 90:cb3d968589d8 3557 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 90:cb3d968589d8 3558
Kojto 90:cb3d968589d8 3559 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
Kojto 90:cb3d968589d8 3560 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
Kojto 90:cb3d968589d8 3561 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
Kojto 90:cb3d968589d8 3562 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
Kojto 90:cb3d968589d8 3563 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
Kojto 90:cb3d968589d8 3564 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
Kojto 90:cb3d968589d8 3565
Kojto 90:cb3d968589d8 3566 /******************** Bit definition for RCC_CFGR register *****************/
Kojto 90:cb3d968589d8 3567 /*!< SW configuration */
Kojto 90:cb3d968589d8 3568 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 90:cb3d968589d8 3569 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3570 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3571
Kojto 90:cb3d968589d8 3572 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 90:cb3d968589d8 3573 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 90:cb3d968589d8 3574 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 90:cb3d968589d8 3575 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
Kojto 90:cb3d968589d8 3576
Kojto 90:cb3d968589d8 3577 /*!< SWS configuration */
Kojto 90:cb3d968589d8 3578 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 90:cb3d968589d8 3579 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3580 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3581
Kojto 90:cb3d968589d8 3582 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 90:cb3d968589d8 3583 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 90:cb3d968589d8 3584 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 90:cb3d968589d8 3585 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
Kojto 90:cb3d968589d8 3586
Kojto 90:cb3d968589d8 3587 /*!< HPRE configuration */
Kojto 90:cb3d968589d8 3588 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 90:cb3d968589d8 3589 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3590 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3591 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 90:cb3d968589d8 3592 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 90:cb3d968589d8 3593
Kojto 90:cb3d968589d8 3594 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 90:cb3d968589d8 3595 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 90:cb3d968589d8 3596 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 90:cb3d968589d8 3597 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 90:cb3d968589d8 3598 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 90:cb3d968589d8 3599 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 90:cb3d968589d8 3600 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 90:cb3d968589d8 3601 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 90:cb3d968589d8 3602 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 90:cb3d968589d8 3603
Kojto 90:cb3d968589d8 3604 /*!< PPRE configuration */
Kojto 90:cb3d968589d8 3605 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
Kojto 90:cb3d968589d8 3606 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3607 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3608 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 90:cb3d968589d8 3609
Kojto 90:cb3d968589d8 3610 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 90:cb3d968589d8 3611 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
Kojto 90:cb3d968589d8 3612 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
Kojto 90:cb3d968589d8 3613 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
Kojto 90:cb3d968589d8 3614 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
Kojto 90:cb3d968589d8 3615
Kojto 90:cb3d968589d8 3616 /*!< ADCPPRE configuration: obsolete setting for STM32F091xC */
Kojto 90:cb3d968589d8 3617 /*#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000)*/ /*!< ADCPRE bit (ADC prescaler) */
Kojto 90:cb3d968589d8 3618
Kojto 90:cb3d968589d8 3619 /*#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000)*/ /*!< PCLK divided by 2 */
Kojto 90:cb3d968589d8 3620 /*#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000)*/ /*!< PCLK divided by 4 */
Kojto 90:cb3d968589d8 3621
Kojto 90:cb3d968589d8 3622 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
Kojto 90:cb3d968589d8 3623 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
Kojto 90:cb3d968589d8 3624 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
Kojto 90:cb3d968589d8 3625 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
Kojto 90:cb3d968589d8 3626 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
Kojto 90:cb3d968589d8 3627
Kojto 90:cb3d968589d8 3628 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
Kojto 90:cb3d968589d8 3629 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
Kojto 90:cb3d968589d8 3630 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
Kojto 90:cb3d968589d8 3631
Kojto 90:cb3d968589d8 3632 /*!< PLLMUL configuration */
Kojto 90:cb3d968589d8 3633 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 90:cb3d968589d8 3634 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3635 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3636 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 90:cb3d968589d8 3637 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Kojto 90:cb3d968589d8 3638
Kojto 90:cb3d968589d8 3639 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
Kojto 90:cb3d968589d8 3640 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
Kojto 90:cb3d968589d8 3641 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
Kojto 90:cb3d968589d8 3642 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
Kojto 90:cb3d968589d8 3643 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
Kojto 90:cb3d968589d8 3644 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
Kojto 90:cb3d968589d8 3645 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
Kojto 90:cb3d968589d8 3646 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
Kojto 90:cb3d968589d8 3647 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
Kojto 90:cb3d968589d8 3648 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
Kojto 90:cb3d968589d8 3649 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
Kojto 90:cb3d968589d8 3650 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
Kojto 90:cb3d968589d8 3651 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
Kojto 90:cb3d968589d8 3652 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
Kojto 90:cb3d968589d8 3653 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
Kojto 90:cb3d968589d8 3654
Kojto 90:cb3d968589d8 3655 /*!< MCO configuration */
Kojto 90:cb3d968589d8 3656 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
Kojto 90:cb3d968589d8 3657 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3658 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3659 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 90:cb3d968589d8 3660 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Kojto 90:cb3d968589d8 3661
Kojto 90:cb3d968589d8 3662 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 90:cb3d968589d8 3663 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
Kojto 90:cb3d968589d8 3664 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
Kojto 90:cb3d968589d8 3665 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
Kojto 90:cb3d968589d8 3666 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
Kojto 90:cb3d968589d8 3667 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
Kojto 90:cb3d968589d8 3668 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
Kojto 90:cb3d968589d8 3669 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
Kojto 90:cb3d968589d8 3670 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
Kojto 90:cb3d968589d8 3671
Kojto 90:cb3d968589d8 3672 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
Kojto 90:cb3d968589d8 3673 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
Kojto 90:cb3d968589d8 3674 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
Kojto 90:cb3d968589d8 3675 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
Kojto 90:cb3d968589d8 3676 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
Kojto 90:cb3d968589d8 3677 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
Kojto 90:cb3d968589d8 3678 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
Kojto 90:cb3d968589d8 3679 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
Kojto 90:cb3d968589d8 3680 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
Kojto 90:cb3d968589d8 3681
Kojto 90:cb3d968589d8 3682 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
Kojto 90:cb3d968589d8 3683
Kojto 90:cb3d968589d8 3684 /*!<****************** Bit definition for RCC_CIR register *****************/
Kojto 90:cb3d968589d8 3685 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
Kojto 90:cb3d968589d8 3686 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
Kojto 90:cb3d968589d8 3687 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
Kojto 90:cb3d968589d8 3688 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
Kojto 90:cb3d968589d8 3689 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
Kojto 90:cb3d968589d8 3690 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
Kojto 90:cb3d968589d8 3691 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
Kojto 90:cb3d968589d8 3692 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
Kojto 90:cb3d968589d8 3693 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
Kojto 90:cb3d968589d8 3694 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
Kojto 90:cb3d968589d8 3695 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
Kojto 90:cb3d968589d8 3696 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
Kojto 90:cb3d968589d8 3697 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
Kojto 90:cb3d968589d8 3698 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
Kojto 90:cb3d968589d8 3699 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
Kojto 90:cb3d968589d8 3700 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
Kojto 90:cb3d968589d8 3701 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
Kojto 90:cb3d968589d8 3702 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
Kojto 90:cb3d968589d8 3703 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
Kojto 90:cb3d968589d8 3704 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
Kojto 90:cb3d968589d8 3705 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
Kojto 90:cb3d968589d8 3706 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
Kojto 90:cb3d968589d8 3707 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
Kojto 90:cb3d968589d8 3708
Kojto 90:cb3d968589d8 3709 /***************** Bit definition for RCC_APB2RSTR register ****************/
Kojto 90:cb3d968589d8 3710 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
Kojto 90:cb3d968589d8 3711 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
Kojto 90:cb3d968589d8 3712 #define RCC_APB2RSTR_USART8RST ((uint32_t)0x00000080) /*!< USART8 clock reset */
Kojto 90:cb3d968589d8 3713 #define RCC_APB2RSTR_USART7RST ((uint32_t)0x00000040) /*!< USART7 clock reset */
Kojto 90:cb3d968589d8 3714 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) /*!< USART6 clock reset */
Kojto 90:cb3d968589d8 3715 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
Kojto 90:cb3d968589d8 3716 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
Kojto 90:cb3d968589d8 3717 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
Kojto 90:cb3d968589d8 3718 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
Kojto 90:cb3d968589d8 3719 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
Kojto 90:cb3d968589d8 3720 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
Kojto 90:cb3d968589d8 3721 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
Kojto 90:cb3d968589d8 3722
Kojto 90:cb3d968589d8 3723 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 3724 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
Kojto 90:cb3d968589d8 3725
Kojto 90:cb3d968589d8 3726 /***************** Bit definition for RCC_APB1RSTR register ****************/
Kojto 90:cb3d968589d8 3727 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
Kojto 90:cb3d968589d8 3728 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
Kojto 90:cb3d968589d8 3729 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
Kojto 90:cb3d968589d8 3730 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
Kojto 90:cb3d968589d8 3731 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
Kojto 90:cb3d968589d8 3732 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
Kojto 90:cb3d968589d8 3733 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
Kojto 90:cb3d968589d8 3734 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
Kojto 90:cb3d968589d8 3735 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
Kojto 90:cb3d968589d8 3736 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
Kojto 90:cb3d968589d8 3737 #define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000) /*!< USART 5 clock reset */
Kojto 90:cb3d968589d8 3738 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
Kojto 90:cb3d968589d8 3739 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
Kojto 90:cb3d968589d8 3740 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
Kojto 90:cb3d968589d8 3741 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
Kojto 90:cb3d968589d8 3742 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
Kojto 90:cb3d968589d8 3743 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
Kojto 90:cb3d968589d8 3744 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
Kojto 90:cb3d968589d8 3745
Kojto 90:cb3d968589d8 3746 /****************** Bit definition for RCC_AHBENR register *****************/
Kojto 90:cb3d968589d8 3747 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
Kojto 90:cb3d968589d8 3748 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
Kojto 90:cb3d968589d8 3749 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
Kojto 90:cb3d968589d8 3750 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
Kojto 90:cb3d968589d8 3751 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
Kojto 90:cb3d968589d8 3752 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
Kojto 90:cb3d968589d8 3753 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
Kojto 90:cb3d968589d8 3754 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
Kojto 90:cb3d968589d8 3755 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
Kojto 90:cb3d968589d8 3756 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
Kojto 90:cb3d968589d8 3757 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
Kojto 90:cb3d968589d8 3758 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
Kojto 90:cb3d968589d8 3759
Kojto 90:cb3d968589d8 3760 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 3761 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
Kojto 90:cb3d968589d8 3762 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Kojto 90:cb3d968589d8 3763
Kojto 90:cb3d968589d8 3764 /***************** Bit definition for RCC_APB2ENR register *****************/
Kojto 90:cb3d968589d8 3765 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
Kojto 90:cb3d968589d8 3766 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
Kojto 90:cb3d968589d8 3767 #define RCC_APB2ENR_USART8EN ((uint32_t)0x00000080) /*!< USART8 clock enable */
Kojto 90:cb3d968589d8 3768 #define RCC_APB2ENR_USART7EN ((uint32_t)0x00000040) /*!< USART7 clock enable */
Kojto 90:cb3d968589d8 3769 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) /*!< USART6 clock enable */
Kojto 90:cb3d968589d8 3770 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
Kojto 90:cb3d968589d8 3771 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
Kojto 90:cb3d968589d8 3772 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
Kojto 90:cb3d968589d8 3773 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
Kojto 90:cb3d968589d8 3774 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
Kojto 90:cb3d968589d8 3775 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
Kojto 90:cb3d968589d8 3776 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
Kojto 90:cb3d968589d8 3777
Kojto 90:cb3d968589d8 3778 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 3779 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
Kojto 90:cb3d968589d8 3780 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
Kojto 90:cb3d968589d8 3781
Kojto 90:cb3d968589d8 3782 /***************** Bit definition for RCC_APB1ENR register *****************/
Kojto 90:cb3d968589d8 3783 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
Kojto 90:cb3d968589d8 3784 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
Kojto 90:cb3d968589d8 3785 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
Kojto 90:cb3d968589d8 3786 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
Kojto 90:cb3d968589d8 3787 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
Kojto 90:cb3d968589d8 3788 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
Kojto 90:cb3d968589d8 3789 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
Kojto 90:cb3d968589d8 3790 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
Kojto 90:cb3d968589d8 3791 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
Kojto 90:cb3d968589d8 3792 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
Kojto 90:cb3d968589d8 3793 #define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000) /*!< USART5 clock enable */
Kojto 90:cb3d968589d8 3794 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
Kojto 90:cb3d968589d8 3795 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
Kojto 90:cb3d968589d8 3796 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
Kojto 90:cb3d968589d8 3797 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
Kojto 90:cb3d968589d8 3798 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
Kojto 90:cb3d968589d8 3799 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
Kojto 90:cb3d968589d8 3800 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
Kojto 90:cb3d968589d8 3801
Kojto 90:cb3d968589d8 3802 /******************* Bit definition for RCC_BDCR register ******************/
Kojto 90:cb3d968589d8 3803 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
Kojto 90:cb3d968589d8 3804 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
Kojto 90:cb3d968589d8 3805 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
Kojto 90:cb3d968589d8 3806
Kojto 90:cb3d968589d8 3807 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Kojto 90:cb3d968589d8 3808 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3809 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3810
Kojto 90:cb3d968589d8 3811 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 90:cb3d968589d8 3812 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3813 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3814
Kojto 90:cb3d968589d8 3815 /*!< RTC configuration */
Kojto 90:cb3d968589d8 3816 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 90:cb3d968589d8 3817 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
Kojto 90:cb3d968589d8 3818 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
Kojto 90:cb3d968589d8 3819 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
Kojto 90:cb3d968589d8 3820
Kojto 90:cb3d968589d8 3821 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
Kojto 90:cb3d968589d8 3822 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
Kojto 90:cb3d968589d8 3823
Kojto 90:cb3d968589d8 3824 /******************* Bit definition for RCC_CSR register *******************/
Kojto 90:cb3d968589d8 3825 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
Kojto 90:cb3d968589d8 3826 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
Kojto 90:cb3d968589d8 3827 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
Kojto 90:cb3d968589d8 3828 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
Kojto 90:cb3d968589d8 3829 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
Kojto 90:cb3d968589d8 3830 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
Kojto 90:cb3d968589d8 3831 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
Kojto 90:cb3d968589d8 3832 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
Kojto 90:cb3d968589d8 3833 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
Kojto 90:cb3d968589d8 3834 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
Kojto 90:cb3d968589d8 3835 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
Kojto 90:cb3d968589d8 3836
Kojto 90:cb3d968589d8 3837 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 3838 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
Kojto 90:cb3d968589d8 3839
Kojto 90:cb3d968589d8 3840 /******************* Bit definition for RCC_AHBRSTR register ***************/
Kojto 90:cb3d968589d8 3841 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
Kojto 90:cb3d968589d8 3842 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
Kojto 90:cb3d968589d8 3843 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
Kojto 90:cb3d968589d8 3844 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
Kojto 90:cb3d968589d8 3845 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE clock reset */
Kojto 90:cb3d968589d8 3846 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
Kojto 90:cb3d968589d8 3847 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
Kojto 90:cb3d968589d8 3848
Kojto 90:cb3d968589d8 3849 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 3850 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
Kojto 90:cb3d968589d8 3851
Kojto 90:cb3d968589d8 3852 /******************* Bit definition for RCC_CFGR2 register *****************/
Kojto 90:cb3d968589d8 3853 /*!< PREDIV configuration */
Kojto 90:cb3d968589d8 3854 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
Kojto 90:cb3d968589d8 3855 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3856 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3857 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 90:cb3d968589d8 3858 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 90:cb3d968589d8 3859
Kojto 90:cb3d968589d8 3860 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
Kojto 90:cb3d968589d8 3861 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
Kojto 90:cb3d968589d8 3862 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
Kojto 90:cb3d968589d8 3863 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
Kojto 90:cb3d968589d8 3864 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
Kojto 90:cb3d968589d8 3865 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
Kojto 90:cb3d968589d8 3866 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
Kojto 90:cb3d968589d8 3867 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
Kojto 90:cb3d968589d8 3868 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
Kojto 90:cb3d968589d8 3869 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
Kojto 90:cb3d968589d8 3870 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
Kojto 90:cb3d968589d8 3871 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
Kojto 90:cb3d968589d8 3872 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
Kojto 90:cb3d968589d8 3873 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
Kojto 90:cb3d968589d8 3874 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
Kojto 90:cb3d968589d8 3875 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
Kojto 90:cb3d968589d8 3876
Kojto 90:cb3d968589d8 3877 /******************* Bit definition for RCC_CFGR3 register *****************/
Kojto 90:cb3d968589d8 3878 /*!< USART1 Clock source selection */
Kojto 90:cb3d968589d8 3879 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
Kojto 90:cb3d968589d8 3880 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3881 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3882
Kojto 90:cb3d968589d8 3883 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
Kojto 90:cb3d968589d8 3884 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
Kojto 90:cb3d968589d8 3885 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
Kojto 90:cb3d968589d8 3886 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
Kojto 90:cb3d968589d8 3887
Kojto 90:cb3d968589d8 3888 /*!< I2C1 Clock source selection */
Kojto 90:cb3d968589d8 3889 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
Kojto 90:cb3d968589d8 3890
Kojto 90:cb3d968589d8 3891 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
Kojto 90:cb3d968589d8 3892 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
Kojto 90:cb3d968589d8 3893
Kojto 90:cb3d968589d8 3894 /*!< CEC Clock source selection */
Kojto 90:cb3d968589d8 3895 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
Kojto 90:cb3d968589d8 3896
Kojto 90:cb3d968589d8 3897 #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
Kojto 90:cb3d968589d8 3898 #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
Kojto 90:cb3d968589d8 3899
Kojto 90:cb3d968589d8 3900 /*!< USART2 Clock source selection */
Kojto 90:cb3d968589d8 3901 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
Kojto 90:cb3d968589d8 3902 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3903 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3904
Kojto 90:cb3d968589d8 3905 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
Kojto 90:cb3d968589d8 3906 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
Kojto 90:cb3d968589d8 3907 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
Kojto 90:cb3d968589d8 3908 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
Kojto 90:cb3d968589d8 3909
Kojto 90:cb3d968589d8 3910 /*!< USART3 Clock source selection */
Kojto 90:cb3d968589d8 3911 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
Kojto 90:cb3d968589d8 3912 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 3913 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3914
Kojto 90:cb3d968589d8 3915 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART3 clock source */
Kojto 90:cb3d968589d8 3916 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
Kojto 90:cb3d968589d8 3917 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
Kojto 90:cb3d968589d8 3918 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
Kojto 90:cb3d968589d8 3919
Kojto 90:cb3d968589d8 3920 /******************* Bit definition for RCC_CR2 register *******************/
Kojto 90:cb3d968589d8 3921 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
Kojto 90:cb3d968589d8 3922 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
Kojto 90:cb3d968589d8 3923 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
Kojto 90:cb3d968589d8 3924 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
Kojto 90:cb3d968589d8 3925 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
Kojto 90:cb3d968589d8 3926 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
Kojto 90:cb3d968589d8 3927 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
Kojto 90:cb3d968589d8 3928 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
Kojto 90:cb3d968589d8 3929
Kojto 90:cb3d968589d8 3930 /*****************************************************************************/
Kojto 90:cb3d968589d8 3931 /* */
Kojto 90:cb3d968589d8 3932 /* Real-Time Clock (RTC) */
Kojto 90:cb3d968589d8 3933 /* */
Kojto 90:cb3d968589d8 3934 /*****************************************************************************/
Kojto 90:cb3d968589d8 3935 /******************** Bits definition for RTC_TR register ******************/
Kojto 90:cb3d968589d8 3936 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 90:cb3d968589d8 3937 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 90:cb3d968589d8 3938 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 90:cb3d968589d8 3939 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 90:cb3d968589d8 3940 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 90:cb3d968589d8 3941 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 3942 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 3943 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 3944 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 90:cb3d968589d8 3945 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 90:cb3d968589d8 3946 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3947 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3948 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3949 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 90:cb3d968589d8 3950 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3951 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3952 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3953 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3954 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 90:cb3d968589d8 3955 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3956 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3957 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 3958 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 90:cb3d968589d8 3959 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3960 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3961 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3962 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3963
Kojto 90:cb3d968589d8 3964 /******************** Bits definition for RTC_DR register ******************/
Kojto 90:cb3d968589d8 3965 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 90:cb3d968589d8 3966 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 90:cb3d968589d8 3967 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 90:cb3d968589d8 3968 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 90:cb3d968589d8 3969 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 90:cb3d968589d8 3970 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 90:cb3d968589d8 3971 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 3972 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 3973 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 3974 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 90:cb3d968589d8 3975 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 90:cb3d968589d8 3976 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 3977 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 3978 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 3979 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 3980 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 90:cb3d968589d8 3981 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 3982 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 3983 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 3984 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 3985 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 90:cb3d968589d8 3986 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 3987 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 3988 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 90:cb3d968589d8 3989 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 3990 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 3991 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 3992 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 3993
Kojto 90:cb3d968589d8 3994 /******************** Bits definition for RTC_CR register ******************/
Kojto 90:cb3d968589d8 3995 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 90:cb3d968589d8 3996 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 90:cb3d968589d8 3997 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 90:cb3d968589d8 3998 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 90:cb3d968589d8 3999 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 90:cb3d968589d8 4000 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 90:cb3d968589d8 4001 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 4002 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 4003 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 4004 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 4005 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 4006 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 4007 #define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 4008 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 4009 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 4010 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 4011 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 4012 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 4013 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto 90:cb3d968589d8 4014 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 4015 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 4016 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 4017
Kojto 90:cb3d968589d8 4018 /******************** Bits definition for RTC_ISR register *****************/
Kojto 90:cb3d968589d8 4019 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 4020 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 4021 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 4022 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 4023 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 4024 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 4025 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 4026 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 4027 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 4028 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 4029 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 4030 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 4031 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 4032 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 4033 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 4034
Kojto 90:cb3d968589d8 4035 /******************** Bits definition for RTC_PRER register ****************/
Kojto 90:cb3d968589d8 4036 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 90:cb3d968589d8 4037 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto 90:cb3d968589d8 4038
Kojto 90:cb3d968589d8 4039 /******************** Bits definition for RTC_WUTR register ****************/
Kojto 90:cb3d968589d8 4040 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto 90:cb3d968589d8 4041
Kojto 90:cb3d968589d8 4042 /******************** Bits definition for RTC_ALRMAR register **************/
Kojto 90:cb3d968589d8 4043 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 90:cb3d968589d8 4044 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 90:cb3d968589d8 4045 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 90:cb3d968589d8 4046 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 90:cb3d968589d8 4047 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 90:cb3d968589d8 4048 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 90:cb3d968589d8 4049 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 90:cb3d968589d8 4050 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 90:cb3d968589d8 4051 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 90:cb3d968589d8 4052 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 90:cb3d968589d8 4053 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 90:cb3d968589d8 4054 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 90:cb3d968589d8 4055 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 90:cb3d968589d8 4056 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 90:cb3d968589d8 4057 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 90:cb3d968589d8 4058 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 90:cb3d968589d8 4059 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 4060 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 4061 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 4062 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 90:cb3d968589d8 4063 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 4064 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 90:cb3d968589d8 4065 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 4066 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 4067 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 4068 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 90:cb3d968589d8 4069 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 4070 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 4071 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 4072 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 4073 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 4074 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 90:cb3d968589d8 4075 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 4076 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 4077 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 4078 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 90:cb3d968589d8 4079 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 4080 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 4081 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 4082 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 4083
Kojto 90:cb3d968589d8 4084 /******************** Bits definition for RTC_WPR register *****************/
Kojto 90:cb3d968589d8 4085 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 90:cb3d968589d8 4086
Kojto 90:cb3d968589d8 4087 /******************** Bits definition for RTC_SSR register *****************/
Kojto 90:cb3d968589d8 4088 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 90:cb3d968589d8 4089
Kojto 90:cb3d968589d8 4090 /******************** Bits definition for RTC_SHIFTR register **************/
Kojto 90:cb3d968589d8 4091 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 90:cb3d968589d8 4092 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 90:cb3d968589d8 4093
Kojto 90:cb3d968589d8 4094 /******************** Bits definition for RTC_TSTR register ****************/
Kojto 90:cb3d968589d8 4095 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 90:cb3d968589d8 4096 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 90:cb3d968589d8 4097 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 90:cb3d968589d8 4098 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 90:cb3d968589d8 4099 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 90:cb3d968589d8 4100 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 4101 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 4102 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 4103 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 90:cb3d968589d8 4104 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 90:cb3d968589d8 4105 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 4106 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 4107 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 4108 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 90:cb3d968589d8 4109 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 4110 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 4111 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 4112 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 4113 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 90:cb3d968589d8 4114 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 4115 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 4116 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 4117 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 90:cb3d968589d8 4118 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 4119 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 4120 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 4121 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 4122
Kojto 90:cb3d968589d8 4123 /******************** Bits definition for RTC_TSDR register ****************/
Kojto 90:cb3d968589d8 4124 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 90:cb3d968589d8 4125 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 4126 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 4127 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 4128 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 4129 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 90:cb3d968589d8 4130 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 4131 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 4132 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 4133 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 4134 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 90:cb3d968589d8 4135 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 4136 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 4137 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 90:cb3d968589d8 4138 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 4139 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 4140 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 4141 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 4142
Kojto 90:cb3d968589d8 4143 /******************** Bits definition for RTC_TSSSR register ***************/
Kojto 90:cb3d968589d8 4144 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 90:cb3d968589d8 4145
Kojto 90:cb3d968589d8 4146 /******************** Bits definition for RTC_CALR register ****************/
Kojto 90:cb3d968589d8 4147 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 4148 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 4149 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 4150 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 90:cb3d968589d8 4151 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 4152 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 4153 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 4154 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 4155 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 4156 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 4157 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 4158 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 4159 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 4160
Kojto 90:cb3d968589d8 4161 /******************** Bits definition for RTC_TAFCR register ***************/
Kojto 90:cb3d968589d8 4162 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 4163 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 90:cb3d968589d8 4164 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 90:cb3d968589d8 4165 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 90:cb3d968589d8 4166 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 90:cb3d968589d8 4167 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 90:cb3d968589d8 4168 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 90:cb3d968589d8 4169 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 90:cb3d968589d8 4170 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 90:cb3d968589d8 4171 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 90:cb3d968589d8 4172 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 90:cb3d968589d8 4173 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 4174 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto 90:cb3d968589d8 4175 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
Kojto 90:cb3d968589d8 4176 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 4177 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto 90:cb3d968589d8 4178 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto 90:cb3d968589d8 4179 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto 90:cb3d968589d8 4180 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 4181 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 4182
Kojto 90:cb3d968589d8 4183 /******************** Bits definition for RTC_ALRMASSR register ************/
Kojto 90:cb3d968589d8 4184 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 90:cb3d968589d8 4185 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 90:cb3d968589d8 4186 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 90:cb3d968589d8 4187 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 90:cb3d968589d8 4188 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 90:cb3d968589d8 4189 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 90:cb3d968589d8 4190
Kojto 90:cb3d968589d8 4191 /******************** Bits definition for RTC_BKP0R register ***************/
Kojto 90:cb3d968589d8 4192 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto 90:cb3d968589d8 4193
Kojto 90:cb3d968589d8 4194 /******************** Bits definition for RTC_BKP1R register ***************/
Kojto 90:cb3d968589d8 4195 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto 90:cb3d968589d8 4196
Kojto 90:cb3d968589d8 4197 /******************** Bits definition for RTC_BKP2R register ***************/
Kojto 90:cb3d968589d8 4198 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto 90:cb3d968589d8 4199
Kojto 90:cb3d968589d8 4200 /******************** Bits definition for RTC_BKP3R register ***************/
Kojto 90:cb3d968589d8 4201 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto 90:cb3d968589d8 4202
Kojto 90:cb3d968589d8 4203 /******************** Bits definition for RTC_BKP4R register ***************/
Kojto 90:cb3d968589d8 4204 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto 90:cb3d968589d8 4205
Kojto 90:cb3d968589d8 4206 /******************** Number of backup registers ******************************/
Kojto 90:cb3d968589d8 4207 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
Kojto 90:cb3d968589d8 4208
Kojto 90:cb3d968589d8 4209 /*****************************************************************************/
Kojto 90:cb3d968589d8 4210 /* */
Kojto 90:cb3d968589d8 4211 /* Serial Peripheral Interface (SPI) */
Kojto 90:cb3d968589d8 4212 /* */
Kojto 90:cb3d968589d8 4213 /*****************************************************************************/
Kojto 90:cb3d968589d8 4214 /******************* Bit definition for SPI_CR1 register *******************/
Kojto 90:cb3d968589d8 4215 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
Kojto 90:cb3d968589d8 4216 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
Kojto 90:cb3d968589d8 4217 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
Kojto 90:cb3d968589d8 4218 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 90:cb3d968589d8 4219 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 90:cb3d968589d8 4220 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 90:cb3d968589d8 4221 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 90:cb3d968589d8 4222 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
Kojto 90:cb3d968589d8 4223 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
Kojto 90:cb3d968589d8 4224 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
Kojto 90:cb3d968589d8 4225 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
Kojto 90:cb3d968589d8 4226 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
Kojto 90:cb3d968589d8 4227 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
Kojto 90:cb3d968589d8 4228 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
Kojto 90:cb3d968589d8 4229 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
Kojto 90:cb3d968589d8 4230 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
Kojto 90:cb3d968589d8 4231 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
Kojto 90:cb3d968589d8 4232
Kojto 90:cb3d968589d8 4233 /******************* Bit definition for SPI_CR2 register *******************/
Kojto 90:cb3d968589d8 4234 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
Kojto 90:cb3d968589d8 4235 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
Kojto 90:cb3d968589d8 4236 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
Kojto 90:cb3d968589d8 4237 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
Kojto 90:cb3d968589d8 4238 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
Kojto 90:cb3d968589d8 4239 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
Kojto 90:cb3d968589d8 4240 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
Kojto 90:cb3d968589d8 4241 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
Kojto 90:cb3d968589d8 4242 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
Kojto 90:cb3d968589d8 4243 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 90:cb3d968589d8 4244 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 90:cb3d968589d8 4245 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 90:cb3d968589d8 4246 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 90:cb3d968589d8 4247 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
Kojto 90:cb3d968589d8 4248 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
Kojto 90:cb3d968589d8 4249 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
Kojto 90:cb3d968589d8 4250
Kojto 90:cb3d968589d8 4251 /******************** Bit definition for SPI_SR register *******************/
Kojto 90:cb3d968589d8 4252 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
Kojto 90:cb3d968589d8 4253 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
Kojto 90:cb3d968589d8 4254 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
Kojto 90:cb3d968589d8 4255 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
Kojto 90:cb3d968589d8 4256 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
Kojto 90:cb3d968589d8 4257 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
Kojto 90:cb3d968589d8 4258 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
Kojto 90:cb3d968589d8 4259 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
Kojto 90:cb3d968589d8 4260 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
Kojto 90:cb3d968589d8 4261 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
Kojto 90:cb3d968589d8 4262 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 90:cb3d968589d8 4263 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 90:cb3d968589d8 4264 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
Kojto 90:cb3d968589d8 4265 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
Kojto 90:cb3d968589d8 4266 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 4267
Kojto 90:cb3d968589d8 4268 /******************** Bit definition for SPI_DR register *******************/
Kojto 90:cb3d968589d8 4269 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
Kojto 90:cb3d968589d8 4270
Kojto 90:cb3d968589d8 4271 /******************* Bit definition for SPI_CRCPR register *****************/
Kojto 90:cb3d968589d8 4272 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
Kojto 90:cb3d968589d8 4273
Kojto 90:cb3d968589d8 4274 /****************** Bit definition for SPI_RXCRCR register *****************/
Kojto 90:cb3d968589d8 4275 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
Kojto 90:cb3d968589d8 4276
Kojto 90:cb3d968589d8 4277 /****************** Bit definition for SPI_TXCRCR register *****************/
Kojto 90:cb3d968589d8 4278 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
Kojto 90:cb3d968589d8 4279
Kojto 90:cb3d968589d8 4280 /****************** Bit definition for SPI_I2SCFGR register ****************/
Kojto 90:cb3d968589d8 4281 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
Kojto 90:cb3d968589d8 4282 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 90:cb3d968589d8 4283 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4284 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4285 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
Kojto 90:cb3d968589d8 4286 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 90:cb3d968589d8 4287 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4288 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4289 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
Kojto 90:cb3d968589d8 4290 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 90:cb3d968589d8 4291 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4292 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4293 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
Kojto 90:cb3d968589d8 4294 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
Kojto 90:cb3d968589d8 4295
Kojto 90:cb3d968589d8 4296 /****************** Bit definition for SPI_I2SPR register ******************/
Kojto 90:cb3d968589d8 4297 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
Kojto 90:cb3d968589d8 4298 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
Kojto 90:cb3d968589d8 4299 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
Kojto 90:cb3d968589d8 4300
Kojto 90:cb3d968589d8 4301 /*****************************************************************************/
Kojto 90:cb3d968589d8 4302 /* */
Kojto 90:cb3d968589d8 4303 /* System Configuration (SYSCFG) */
Kojto 90:cb3d968589d8 4304 /* */
Kojto 90:cb3d968589d8 4305 /*****************************************************************************/
Kojto 90:cb3d968589d8 4306 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
Kojto 90:cb3d968589d8 4307 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
Kojto 90:cb3d968589d8 4308 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
Kojto 90:cb3d968589d8 4309 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
Kojto 90:cb3d968589d8 4310 #define SYSCFG_CFGR1_IRDA_ENV_SEL ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
Kojto 90:cb3d968589d8 4311 #define SYSCFG_CFGR1_IRDA_ENV_SEL_0 ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
Kojto 90:cb3d968589d8 4312 #define SYSCFG_CFGR1_IRDA_ENV_SEL_1 ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
Kojto 90:cb3d968589d8 4313 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
Kojto 90:cb3d968589d8 4314 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
Kojto 90:cb3d968589d8 4315 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
Kojto 90:cb3d968589d8 4316 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
Kojto 90:cb3d968589d8 4317 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
Kojto 90:cb3d968589d8 4318 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
Kojto 90:cb3d968589d8 4319 #define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 */
Kojto 90:cb3d968589d8 4320 #define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
Kojto 90:cb3d968589d8 4321
Kojto 90:cb3d968589d8 4322 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
Kojto 90:cb3d968589d8 4323 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
Kojto 90:cb3d968589d8 4324 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
Kojto 90:cb3d968589d8 4325 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
Kojto 90:cb3d968589d8 4326 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
Kojto 90:cb3d968589d8 4327
Kojto 90:cb3d968589d8 4328 /**
Kojto 90:cb3d968589d8 4329 * @brief EXTI0 configuration
Kojto 90:cb3d968589d8 4330 */
Kojto 90:cb3d968589d8 4331 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
Kojto 90:cb3d968589d8 4332 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
Kojto 90:cb3d968589d8 4333 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
Kojto 90:cb3d968589d8 4334 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
Kojto 90:cb3d968589d8 4335 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
Kojto 90:cb3d968589d8 4336 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
Kojto 90:cb3d968589d8 4337
Kojto 90:cb3d968589d8 4338 /**
Kojto 90:cb3d968589d8 4339 * @brief EXTI1 configuration
Kojto 90:cb3d968589d8 4340 */
Kojto 90:cb3d968589d8 4341 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
Kojto 90:cb3d968589d8 4342 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
Kojto 90:cb3d968589d8 4343 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
Kojto 90:cb3d968589d8 4344 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
Kojto 90:cb3d968589d8 4345 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
Kojto 90:cb3d968589d8 4346 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
Kojto 90:cb3d968589d8 4347
Kojto 90:cb3d968589d8 4348 /**
Kojto 90:cb3d968589d8 4349 * @brief EXTI2 configuration
Kojto 90:cb3d968589d8 4350 */
Kojto 90:cb3d968589d8 4351 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
Kojto 90:cb3d968589d8 4352 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
Kojto 90:cb3d968589d8 4353 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
Kojto 90:cb3d968589d8 4354 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
Kojto 90:cb3d968589d8 4355 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
Kojto 90:cb3d968589d8 4356 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
Kojto 90:cb3d968589d8 4357
Kojto 90:cb3d968589d8 4358 /**
Kojto 90:cb3d968589d8 4359 * @brief EXTI3 configuration
Kojto 90:cb3d968589d8 4360 */
Kojto 90:cb3d968589d8 4361 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
Kojto 90:cb3d968589d8 4362 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
Kojto 90:cb3d968589d8 4363 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
Kojto 90:cb3d968589d8 4364 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
Kojto 90:cb3d968589d8 4365 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
Kojto 90:cb3d968589d8 4366 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
Kojto 90:cb3d968589d8 4367
Kojto 90:cb3d968589d8 4368 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
Kojto 90:cb3d968589d8 4369 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
Kojto 90:cb3d968589d8 4370 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
Kojto 90:cb3d968589d8 4371 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
Kojto 90:cb3d968589d8 4372 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
Kojto 90:cb3d968589d8 4373
Kojto 90:cb3d968589d8 4374 /**
Kojto 90:cb3d968589d8 4375 * @brief EXTI4 configuration
Kojto 90:cb3d968589d8 4376 */
Kojto 90:cb3d968589d8 4377 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
Kojto 90:cb3d968589d8 4378 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
Kojto 90:cb3d968589d8 4379 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
Kojto 90:cb3d968589d8 4380 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
Kojto 90:cb3d968589d8 4381 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
Kojto 90:cb3d968589d8 4382 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
Kojto 90:cb3d968589d8 4383
Kojto 90:cb3d968589d8 4384 /**
Kojto 90:cb3d968589d8 4385 * @brief EXTI5 configuration
Kojto 90:cb3d968589d8 4386 */
Kojto 90:cb3d968589d8 4387 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
Kojto 90:cb3d968589d8 4388 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
Kojto 90:cb3d968589d8 4389 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
Kojto 90:cb3d968589d8 4390 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
Kojto 90:cb3d968589d8 4391 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
Kojto 90:cb3d968589d8 4392 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
Kojto 90:cb3d968589d8 4393
Kojto 90:cb3d968589d8 4394 /**
Kojto 90:cb3d968589d8 4395 * @brief EXTI6 configuration
Kojto 90:cb3d968589d8 4396 */
Kojto 90:cb3d968589d8 4397 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
Kojto 90:cb3d968589d8 4398 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
Kojto 90:cb3d968589d8 4399 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
Kojto 90:cb3d968589d8 4400 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
Kojto 90:cb3d968589d8 4401 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
Kojto 90:cb3d968589d8 4402 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
Kojto 90:cb3d968589d8 4403
Kojto 90:cb3d968589d8 4404 /**
Kojto 90:cb3d968589d8 4405 * @brief EXTI7 configuration
Kojto 90:cb3d968589d8 4406 */
Kojto 90:cb3d968589d8 4407 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
Kojto 90:cb3d968589d8 4408 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
Kojto 90:cb3d968589d8 4409 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
Kojto 90:cb3d968589d8 4410 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
Kojto 90:cb3d968589d8 4411 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
Kojto 90:cb3d968589d8 4412 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
Kojto 90:cb3d968589d8 4413
Kojto 90:cb3d968589d8 4414 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
Kojto 90:cb3d968589d8 4415 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
Kojto 90:cb3d968589d8 4416 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
Kojto 90:cb3d968589d8 4417 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
Kojto 90:cb3d968589d8 4418 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
Kojto 90:cb3d968589d8 4419
Kojto 90:cb3d968589d8 4420 /**
Kojto 90:cb3d968589d8 4421 * @brief EXTI8 configuration
Kojto 90:cb3d968589d8 4422 */
Kojto 90:cb3d968589d8 4423 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
Kojto 90:cb3d968589d8 4424 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
Kojto 90:cb3d968589d8 4425 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
Kojto 90:cb3d968589d8 4426 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
Kojto 90:cb3d968589d8 4427 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
Kojto 90:cb3d968589d8 4428
Kojto 90:cb3d968589d8 4429 /**
Kojto 90:cb3d968589d8 4430 * @brief EXTI9 configuration
Kojto 90:cb3d968589d8 4431 */
Kojto 90:cb3d968589d8 4432 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
Kojto 90:cb3d968589d8 4433 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
Kojto 90:cb3d968589d8 4434 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
Kojto 90:cb3d968589d8 4435 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
Kojto 90:cb3d968589d8 4436 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
Kojto 90:cb3d968589d8 4437 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
Kojto 90:cb3d968589d8 4438
Kojto 90:cb3d968589d8 4439 /**
Kojto 90:cb3d968589d8 4440 * @brief EXTI10 configuration
Kojto 90:cb3d968589d8 4441 */
Kojto 90:cb3d968589d8 4442 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
Kojto 90:cb3d968589d8 4443 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
Kojto 90:cb3d968589d8 4444 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
Kojto 90:cb3d968589d8 4445 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
Kojto 90:cb3d968589d8 4446 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
Kojto 90:cb3d968589d8 4447 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
Kojto 90:cb3d968589d8 4448
Kojto 90:cb3d968589d8 4449 /**
Kojto 90:cb3d968589d8 4450 * @brief EXTI11 configuration
Kojto 90:cb3d968589d8 4451 */
Kojto 90:cb3d968589d8 4452 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
Kojto 90:cb3d968589d8 4453 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
Kojto 90:cb3d968589d8 4454 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
Kojto 90:cb3d968589d8 4455 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
Kojto 90:cb3d968589d8 4456 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
Kojto 90:cb3d968589d8 4457
Kojto 90:cb3d968589d8 4458 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
Kojto 90:cb3d968589d8 4459 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
Kojto 90:cb3d968589d8 4460 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
Kojto 90:cb3d968589d8 4461 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
Kojto 90:cb3d968589d8 4462 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
Kojto 90:cb3d968589d8 4463
Kojto 90:cb3d968589d8 4464 /**
Kojto 90:cb3d968589d8 4465 * @brief EXTI12 configuration
Kojto 90:cb3d968589d8 4466 */
Kojto 90:cb3d968589d8 4467 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
Kojto 90:cb3d968589d8 4468 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
Kojto 90:cb3d968589d8 4469 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
Kojto 90:cb3d968589d8 4470 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
Kojto 90:cb3d968589d8 4471 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
Kojto 90:cb3d968589d8 4472
Kojto 90:cb3d968589d8 4473 /**
Kojto 90:cb3d968589d8 4474 * @brief EXTI13 configuration
Kojto 90:cb3d968589d8 4475 */
Kojto 90:cb3d968589d8 4476 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
Kojto 90:cb3d968589d8 4477 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
Kojto 90:cb3d968589d8 4478 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
Kojto 90:cb3d968589d8 4479 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
Kojto 90:cb3d968589d8 4480 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
Kojto 90:cb3d968589d8 4481
Kojto 90:cb3d968589d8 4482 /**
Kojto 90:cb3d968589d8 4483 * @brief EXTI14 configuration
Kojto 90:cb3d968589d8 4484 */
Kojto 90:cb3d968589d8 4485 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
Kojto 90:cb3d968589d8 4486 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
Kojto 90:cb3d968589d8 4487 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
Kojto 90:cb3d968589d8 4488 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
Kojto 90:cb3d968589d8 4489 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
Kojto 90:cb3d968589d8 4490
Kojto 90:cb3d968589d8 4491 /**
Kojto 90:cb3d968589d8 4492 * @brief EXTI15 configuration
Kojto 90:cb3d968589d8 4493 */
Kojto 90:cb3d968589d8 4494 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
Kojto 90:cb3d968589d8 4495 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
Kojto 90:cb3d968589d8 4496 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
Kojto 90:cb3d968589d8 4497 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
Kojto 90:cb3d968589d8 4498 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
Kojto 90:cb3d968589d8 4499
Kojto 90:cb3d968589d8 4500 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
Kojto 90:cb3d968589d8 4501 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
Kojto 90:cb3d968589d8 4502 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
Kojto 90:cb3d968589d8 4503 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
Kojto 90:cb3d968589d8 4504 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
Kojto 90:cb3d968589d8 4505 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
Kojto 90:cb3d968589d8 4506
Kojto 90:cb3d968589d8 4507 /***************** Bit definition for SYSCFG_xxx ISR Wrapper register ****************/
Kojto 90:cb3d968589d8 4508 #define SYSCFG_ITLINE0_SR_EWDG ((uint32_t)0x00000001) /*!< EWDG interrupt */
Kojto 90:cb3d968589d8 4509 #define SYSCFG_ITLINE1_SR_PVDOUT ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
Kojto 90:cb3d968589d8 4510 #define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
Kojto 90:cb3d968589d8 4511 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
Kojto 90:cb3d968589d8 4512 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
Kojto 90:cb3d968589d8 4513 #define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
Kojto 90:cb3d968589d8 4514 #define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
Kojto 90:cb3d968589d8 4515 #define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */
Kojto 90:cb3d968589d8 4516 #define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
Kojto 90:cb3d968589d8 4517 #define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */
Kojto 90:cb3d968589d8 4518 #define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */
Kojto 90:cb3d968589d8 4519 #define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */
Kojto 90:cb3d968589d8 4520 #define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */
Kojto 90:cb3d968589d8 4521 #define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4522 #define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4523 #define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4524 #define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4525 #define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4526 #define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4527 #define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4528 #define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4529 #define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4530 #define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4531 #define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4532 #define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
Kojto 90:cb3d968589d8 4533 #define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
Kojto 90:cb3d968589d8 4534 #define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
Kojto 90:cb3d968589d8 4535 #define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
Kojto 90:cb3d968589d8 4536 #define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
Kojto 90:cb3d968589d8 4537 #define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
Kojto 90:cb3d968589d8 4538 #define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
Kojto 90:cb3d968589d8 4539 #define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
Kojto 90:cb3d968589d8 4540 #define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
Kojto 90:cb3d968589d8 4541 #define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
Kojto 90:cb3d968589d8 4542 #define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
Kojto 90:cb3d968589d8 4543 #define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
Kojto 90:cb3d968589d8 4544 #define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
Kojto 90:cb3d968589d8 4545 #define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
Kojto 90:cb3d968589d8 4546 #define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
Kojto 90:cb3d968589d8 4547 #define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */
Kojto 90:cb3d968589d8 4548 #define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
Kojto 90:cb3d968589d8 4549 #define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
Kojto 90:cb3d968589d8 4550 #define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
Kojto 90:cb3d968589d8 4551 #define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
Kojto 90:cb3d968589d8 4552 #define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
Kojto 90:cb3d968589d8 4553 #define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
Kojto 90:cb3d968589d8 4554 #define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
Kojto 90:cb3d968589d8 4555 #define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
Kojto 90:cb3d968589d8 4556 #define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
Kojto 90:cb3d968589d8 4557 #define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */
Kojto 90:cb3d968589d8 4558 #define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
Kojto 90:cb3d968589d8 4559 #define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
Kojto 90:cb3d968589d8 4560 #define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
Kojto 90:cb3d968589d8 4561 #define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
Kojto 90:cb3d968589d8 4562 #define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
Kojto 90:cb3d968589d8 4563 #define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
Kojto 90:cb3d968589d8 4564 #define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
Kojto 90:cb3d968589d8 4565 #define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
Kojto 90:cb3d968589d8 4566 #define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
Kojto 90:cb3d968589d8 4567 #define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */
Kojto 90:cb3d968589d8 4568 #define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
Kojto 90:cb3d968589d8 4569 #define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
Kojto 90:cb3d968589d8 4570 #define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
Kojto 90:cb3d968589d8 4571 #define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
Kojto 90:cb3d968589d8 4572 #define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
Kojto 90:cb3d968589d8 4573 #define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
Kojto 90:cb3d968589d8 4574 #define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
Kojto 90:cb3d968589d8 4575 #define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
Kojto 90:cb3d968589d8 4576 #define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */
Kojto 90:cb3d968589d8 4577 #define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */
Kojto 90:cb3d968589d8 4578
Kojto 90:cb3d968589d8 4579 /*****************************************************************************/
Kojto 90:cb3d968589d8 4580 /* */
Kojto 90:cb3d968589d8 4581 /* Timers (TIM) */
Kojto 90:cb3d968589d8 4582 /* */
Kojto 90:cb3d968589d8 4583 /*****************************************************************************/
Kojto 90:cb3d968589d8 4584 /******************* Bit definition for TIM_CR1 register *******************/
Kojto 90:cb3d968589d8 4585 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
Kojto 90:cb3d968589d8 4586 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
Kojto 90:cb3d968589d8 4587 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
Kojto 90:cb3d968589d8 4588 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
Kojto 90:cb3d968589d8 4589 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
Kojto 90:cb3d968589d8 4590
Kojto 90:cb3d968589d8 4591 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 90:cb3d968589d8 4592 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4593 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4594
Kojto 90:cb3d968589d8 4595 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
Kojto 90:cb3d968589d8 4596
Kojto 90:cb3d968589d8 4597 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
Kojto 90:cb3d968589d8 4598 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4599 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4600
Kojto 90:cb3d968589d8 4601 /******************* Bit definition for TIM_CR2 register *******************/
Kojto 90:cb3d968589d8 4602 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
Kojto 90:cb3d968589d8 4603 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
Kojto 90:cb3d968589d8 4604 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
Kojto 90:cb3d968589d8 4605
Kojto 90:cb3d968589d8 4606 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 90:cb3d968589d8 4607 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4608 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4609 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4610
Kojto 90:cb3d968589d8 4611 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
Kojto 90:cb3d968589d8 4612 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
Kojto 90:cb3d968589d8 4613 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
Kojto 90:cb3d968589d8 4614 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
Kojto 90:cb3d968589d8 4615 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
Kojto 90:cb3d968589d8 4616 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
Kojto 90:cb3d968589d8 4617 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
Kojto 90:cb3d968589d8 4618 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
Kojto 90:cb3d968589d8 4619
Kojto 90:cb3d968589d8 4620 /******************* Bit definition for TIM_SMCR register ******************/
Kojto 90:cb3d968589d8 4621 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 90:cb3d968589d8 4622 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4623 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4624 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4625
Kojto 90:cb3d968589d8 4626 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
Kojto 90:cb3d968589d8 4627
Kojto 90:cb3d968589d8 4628 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 90:cb3d968589d8 4629 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4630 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4631 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4632
Kojto 90:cb3d968589d8 4633 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
Kojto 90:cb3d968589d8 4634
Kojto 90:cb3d968589d8 4635 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 90:cb3d968589d8 4636 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4637 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4638 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4639 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4640
Kojto 90:cb3d968589d8 4641 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 90:cb3d968589d8 4642 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4643 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4644
Kojto 90:cb3d968589d8 4645 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
Kojto 90:cb3d968589d8 4646 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
Kojto 90:cb3d968589d8 4647
Kojto 90:cb3d968589d8 4648 /******************* Bit definition for TIM_DIER register ******************/
Kojto 90:cb3d968589d8 4649 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
Kojto 90:cb3d968589d8 4650 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
Kojto 90:cb3d968589d8 4651 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
Kojto 90:cb3d968589d8 4652 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
Kojto 90:cb3d968589d8 4653 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
Kojto 90:cb3d968589d8 4654 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
Kojto 90:cb3d968589d8 4655 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
Kojto 90:cb3d968589d8 4656 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
Kojto 90:cb3d968589d8 4657 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
Kojto 90:cb3d968589d8 4658 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
Kojto 90:cb3d968589d8 4659 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
Kojto 90:cb3d968589d8 4660 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
Kojto 90:cb3d968589d8 4661 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
Kojto 90:cb3d968589d8 4662 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
Kojto 90:cb3d968589d8 4663 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
Kojto 90:cb3d968589d8 4664
Kojto 90:cb3d968589d8 4665 /******************** Bit definition for TIM_SR register *******************/
Kojto 90:cb3d968589d8 4666 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
Kojto 90:cb3d968589d8 4667 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 90:cb3d968589d8 4668 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 90:cb3d968589d8 4669 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 90:cb3d968589d8 4670 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 90:cb3d968589d8 4671 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
Kojto 90:cb3d968589d8 4672 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
Kojto 90:cb3d968589d8 4673 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
Kojto 90:cb3d968589d8 4674 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 90:cb3d968589d8 4675 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 90:cb3d968589d8 4676 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 90:cb3d968589d8 4677 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 90:cb3d968589d8 4678
Kojto 90:cb3d968589d8 4679 /******************* Bit definition for TIM_EGR register *******************/
Kojto 90:cb3d968589d8 4680 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
Kojto 90:cb3d968589d8 4681 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
Kojto 90:cb3d968589d8 4682 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
Kojto 90:cb3d968589d8 4683 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
Kojto 90:cb3d968589d8 4684 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
Kojto 90:cb3d968589d8 4685 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
Kojto 90:cb3d968589d8 4686 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
Kojto 90:cb3d968589d8 4687 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
Kojto 90:cb3d968589d8 4688
Kojto 90:cb3d968589d8 4689 /****************** Bit definition for TIM_CCMR1 register ******************/
Kojto 90:cb3d968589d8 4690 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 90:cb3d968589d8 4691 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4692 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4693
Kojto 90:cb3d968589d8 4694 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
Kojto 90:cb3d968589d8 4695 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
Kojto 90:cb3d968589d8 4696
Kojto 90:cb3d968589d8 4697 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 90:cb3d968589d8 4698 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4699 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4700 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4701
Kojto 90:cb3d968589d8 4702 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
Kojto 90:cb3d968589d8 4703
Kojto 90:cb3d968589d8 4704 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 90:cb3d968589d8 4705 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4706 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4707
Kojto 90:cb3d968589d8 4708 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
Kojto 90:cb3d968589d8 4709 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
Kojto 90:cb3d968589d8 4710
Kojto 90:cb3d968589d8 4711 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 90:cb3d968589d8 4712 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4713 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4714 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4715
Kojto 90:cb3d968589d8 4716 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
Kojto 90:cb3d968589d8 4717
Kojto 90:cb3d968589d8 4718 /*---------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 4719
Kojto 90:cb3d968589d8 4720 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 90:cb3d968589d8 4721 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4722 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4723
Kojto 90:cb3d968589d8 4724 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 90:cb3d968589d8 4725 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4726 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4727 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4728 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4729
Kojto 90:cb3d968589d8 4730 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 90:cb3d968589d8 4731 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4732 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4733
Kojto 90:cb3d968589d8 4734 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 90:cb3d968589d8 4735 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4736 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4737 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4738 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4739
Kojto 90:cb3d968589d8 4740 /****************** Bit definition for TIM_CCMR2 register ******************/
Kojto 90:cb3d968589d8 4741 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 90:cb3d968589d8 4742 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4743 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4744
Kojto 90:cb3d968589d8 4745 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
Kojto 90:cb3d968589d8 4746 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
Kojto 90:cb3d968589d8 4747
Kojto 90:cb3d968589d8 4748 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 90:cb3d968589d8 4749 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4750 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4751 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4752
Kojto 90:cb3d968589d8 4753 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
Kojto 90:cb3d968589d8 4754
Kojto 90:cb3d968589d8 4755 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 90:cb3d968589d8 4756 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4757 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4758
Kojto 90:cb3d968589d8 4759 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
Kojto 90:cb3d968589d8 4760 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
Kojto 90:cb3d968589d8 4761
Kojto 90:cb3d968589d8 4762 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 90:cb3d968589d8 4763 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4764 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4765 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4766
Kojto 90:cb3d968589d8 4767 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
Kojto 90:cb3d968589d8 4768
Kojto 90:cb3d968589d8 4769 /*---------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 4770
Kojto 90:cb3d968589d8 4771 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 90:cb3d968589d8 4772 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4773 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4774
Kojto 90:cb3d968589d8 4775 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 90:cb3d968589d8 4776 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4777 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4778 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4779 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4780
Kojto 90:cb3d968589d8 4781 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 90:cb3d968589d8 4782 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4783 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4784
Kojto 90:cb3d968589d8 4785 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 90:cb3d968589d8 4786 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4787 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4788 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4789 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4790
Kojto 90:cb3d968589d8 4791 /******************* Bit definition for TIM_CCER register ******************/
Kojto 90:cb3d968589d8 4792 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
Kojto 90:cb3d968589d8 4793 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
Kojto 90:cb3d968589d8 4794 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 90:cb3d968589d8 4795 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 90:cb3d968589d8 4796 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
Kojto 90:cb3d968589d8 4797 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
Kojto 90:cb3d968589d8 4798 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 90:cb3d968589d8 4799 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 90:cb3d968589d8 4800 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
Kojto 90:cb3d968589d8 4801 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
Kojto 90:cb3d968589d8 4802 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 90:cb3d968589d8 4803 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 90:cb3d968589d8 4804 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
Kojto 90:cb3d968589d8 4805 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
Kojto 90:cb3d968589d8 4806 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 90:cb3d968589d8 4807
Kojto 90:cb3d968589d8 4808 /******************* Bit definition for TIM_CNT register *******************/
Kojto 90:cb3d968589d8 4809 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
Kojto 90:cb3d968589d8 4810
Kojto 90:cb3d968589d8 4811 /******************* Bit definition for TIM_PSC register *******************/
Kojto 90:cb3d968589d8 4812 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
Kojto 90:cb3d968589d8 4813
Kojto 90:cb3d968589d8 4814 /******************* Bit definition for TIM_ARR register *******************/
Kojto 90:cb3d968589d8 4815 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
Kojto 90:cb3d968589d8 4816
Kojto 90:cb3d968589d8 4817 /******************* Bit definition for TIM_RCR register *******************/
Kojto 90:cb3d968589d8 4818 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
Kojto 90:cb3d968589d8 4819
Kojto 90:cb3d968589d8 4820 /******************* Bit definition for TIM_CCR1 register ******************/
Kojto 90:cb3d968589d8 4821 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
Kojto 90:cb3d968589d8 4822
Kojto 90:cb3d968589d8 4823 /******************* Bit definition for TIM_CCR2 register ******************/
Kojto 90:cb3d968589d8 4824 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
Kojto 90:cb3d968589d8 4825
Kojto 90:cb3d968589d8 4826 /******************* Bit definition for TIM_CCR3 register ******************/
Kojto 90:cb3d968589d8 4827 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
Kojto 90:cb3d968589d8 4828
Kojto 90:cb3d968589d8 4829 /******************* Bit definition for TIM_CCR4 register ******************/
Kojto 90:cb3d968589d8 4830 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
Kojto 90:cb3d968589d8 4831
Kojto 90:cb3d968589d8 4832 /******************* Bit definition for TIM_BDTR register ******************/
Kojto 90:cb3d968589d8 4833 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 90:cb3d968589d8 4834 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4835 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4836 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4837 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4838 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 90:cb3d968589d8 4839 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 90:cb3d968589d8 4840 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 90:cb3d968589d8 4841 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 90:cb3d968589d8 4842
Kojto 90:cb3d968589d8 4843 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 90:cb3d968589d8 4844 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4845 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4846
Kojto 90:cb3d968589d8 4847 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
Kojto 90:cb3d968589d8 4848 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
Kojto 90:cb3d968589d8 4849 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
Kojto 90:cb3d968589d8 4850 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
Kojto 90:cb3d968589d8 4851 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
Kojto 90:cb3d968589d8 4852 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
Kojto 90:cb3d968589d8 4853
Kojto 90:cb3d968589d8 4854 /******************* Bit definition for TIM_DCR register *******************/
Kojto 90:cb3d968589d8 4855 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 90:cb3d968589d8 4856 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4857 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4858 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4859 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4860 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 90:cb3d968589d8 4861
Kojto 90:cb3d968589d8 4862 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 90:cb3d968589d8 4863 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4864 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4865 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4866 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4867 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 90:cb3d968589d8 4868
Kojto 90:cb3d968589d8 4869 /******************* Bit definition for TIM_DMAR register ******************/
Kojto 90:cb3d968589d8 4870 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
Kojto 90:cb3d968589d8 4871
Kojto 90:cb3d968589d8 4872 /******************* Bit definition for TIM14_OR register ********************/
Kojto 90:cb3d968589d8 4873 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
Kojto 90:cb3d968589d8 4874 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4875 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4876
Kojto 90:cb3d968589d8 4877 /******************************************************************************/
Kojto 90:cb3d968589d8 4878 /* */
Kojto 90:cb3d968589d8 4879 /* Touch Sensing Controller (TSC) */
Kojto 90:cb3d968589d8 4880 /* */
Kojto 90:cb3d968589d8 4881 /******************************************************************************/
Kojto 90:cb3d968589d8 4882 /******************* Bit definition for TSC_CR register *********************/
Kojto 90:cb3d968589d8 4883 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
Kojto 90:cb3d968589d8 4884 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
Kojto 90:cb3d968589d8 4885 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
Kojto 90:cb3d968589d8 4886 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
Kojto 90:cb3d968589d8 4887 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
Kojto 90:cb3d968589d8 4888
Kojto 90:cb3d968589d8 4889 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
Kojto 90:cb3d968589d8 4890 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4891 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4892 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4893
Kojto 90:cb3d968589d8 4894 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
Kojto 90:cb3d968589d8 4895 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4896 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4897 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4898
Kojto 90:cb3d968589d8 4899 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
Kojto 90:cb3d968589d8 4900 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
Kojto 90:cb3d968589d8 4901
Kojto 90:cb3d968589d8 4902 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
Kojto 90:cb3d968589d8 4903 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4904 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4905 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4906 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4907 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
Kojto 90:cb3d968589d8 4908 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
Kojto 90:cb3d968589d8 4909 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
Kojto 90:cb3d968589d8 4910
Kojto 90:cb3d968589d8 4911 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
Kojto 90:cb3d968589d8 4912 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4913 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4914 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4915 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4916
Kojto 90:cb3d968589d8 4917 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
Kojto 90:cb3d968589d8 4918 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 90:cb3d968589d8 4919 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4920 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
Kojto 90:cb3d968589d8 4921 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4922
Kojto 90:cb3d968589d8 4923 /******************* Bit definition for TSC_IER register ********************/
Kojto 90:cb3d968589d8 4924 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
Kojto 90:cb3d968589d8 4925 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
Kojto 90:cb3d968589d8 4926
Kojto 90:cb3d968589d8 4927 /******************* Bit definition for TSC_ICR register ********************/
Kojto 90:cb3d968589d8 4928 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
Kojto 90:cb3d968589d8 4929 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
Kojto 90:cb3d968589d8 4930
Kojto 90:cb3d968589d8 4931 /******************* Bit definition for TSC_ISR register ********************/
Kojto 90:cb3d968589d8 4932 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
Kojto 90:cb3d968589d8 4933 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
Kojto 90:cb3d968589d8 4934
Kojto 90:cb3d968589d8 4935 /******************* Bit definition for TSC_IOHCR register ******************/
Kojto 90:cb3d968589d8 4936 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4937 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4938 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4939 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4940 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4941 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4942 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4943 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4944 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4945 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4946 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4947 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4948 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4949 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4950 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4951 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4952 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4953 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4954 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4955 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4956 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4957 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4958 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4959 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4960 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4961 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4962 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4963 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4964 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4965 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4966 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4967 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
Kojto 90:cb3d968589d8 4968
Kojto 90:cb3d968589d8 4969 /******************* Bit definition for TSC_IOASCR register *****************/
Kojto 90:cb3d968589d8 4970 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
Kojto 90:cb3d968589d8 4971 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
Kojto 90:cb3d968589d8 4972 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
Kojto 90:cb3d968589d8 4973 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
Kojto 90:cb3d968589d8 4974 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
Kojto 90:cb3d968589d8 4975 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
Kojto 90:cb3d968589d8 4976 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
Kojto 90:cb3d968589d8 4977 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
Kojto 90:cb3d968589d8 4978 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
Kojto 90:cb3d968589d8 4979 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
Kojto 90:cb3d968589d8 4980 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
Kojto 90:cb3d968589d8 4981 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
Kojto 90:cb3d968589d8 4982 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
Kojto 90:cb3d968589d8 4983 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
Kojto 90:cb3d968589d8 4984 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
Kojto 90:cb3d968589d8 4985 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
Kojto 90:cb3d968589d8 4986 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
Kojto 90:cb3d968589d8 4987 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
Kojto 90:cb3d968589d8 4988 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
Kojto 90:cb3d968589d8 4989 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
Kojto 90:cb3d968589d8 4990 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
Kojto 90:cb3d968589d8 4991 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
Kojto 90:cb3d968589d8 4992 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
Kojto 90:cb3d968589d8 4993 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
Kojto 90:cb3d968589d8 4994 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
Kojto 90:cb3d968589d8 4995 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
Kojto 90:cb3d968589d8 4996 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
Kojto 90:cb3d968589d8 4997 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
Kojto 90:cb3d968589d8 4998 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
Kojto 90:cb3d968589d8 4999 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
Kojto 90:cb3d968589d8 5000 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
Kojto 90:cb3d968589d8 5001 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
Kojto 90:cb3d968589d8 5002
Kojto 90:cb3d968589d8 5003 /******************* Bit definition for TSC_IOSCR register ******************/
Kojto 90:cb3d968589d8 5004 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
Kojto 90:cb3d968589d8 5005 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
Kojto 90:cb3d968589d8 5006 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
Kojto 90:cb3d968589d8 5007 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
Kojto 90:cb3d968589d8 5008 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
Kojto 90:cb3d968589d8 5009 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
Kojto 90:cb3d968589d8 5010 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
Kojto 90:cb3d968589d8 5011 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
Kojto 90:cb3d968589d8 5012 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
Kojto 90:cb3d968589d8 5013 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
Kojto 90:cb3d968589d8 5014 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
Kojto 90:cb3d968589d8 5015 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
Kojto 90:cb3d968589d8 5016 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
Kojto 90:cb3d968589d8 5017 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
Kojto 90:cb3d968589d8 5018 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
Kojto 90:cb3d968589d8 5019 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
Kojto 90:cb3d968589d8 5020 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
Kojto 90:cb3d968589d8 5021 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
Kojto 90:cb3d968589d8 5022 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
Kojto 90:cb3d968589d8 5023 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
Kojto 90:cb3d968589d8 5024 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
Kojto 90:cb3d968589d8 5025 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
Kojto 90:cb3d968589d8 5026 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
Kojto 90:cb3d968589d8 5027 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
Kojto 90:cb3d968589d8 5028 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
Kojto 90:cb3d968589d8 5029 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
Kojto 90:cb3d968589d8 5030 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
Kojto 90:cb3d968589d8 5031 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
Kojto 90:cb3d968589d8 5032 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
Kojto 90:cb3d968589d8 5033 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
Kojto 90:cb3d968589d8 5034 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
Kojto 90:cb3d968589d8 5035 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
Kojto 90:cb3d968589d8 5036
Kojto 90:cb3d968589d8 5037 /******************* Bit definition for TSC_IOCCR register ******************/
Kojto 90:cb3d968589d8 5038 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
Kojto 90:cb3d968589d8 5039 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
Kojto 90:cb3d968589d8 5040 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
Kojto 90:cb3d968589d8 5041 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
Kojto 90:cb3d968589d8 5042 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
Kojto 90:cb3d968589d8 5043 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
Kojto 90:cb3d968589d8 5044 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
Kojto 90:cb3d968589d8 5045 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
Kojto 90:cb3d968589d8 5046 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
Kojto 90:cb3d968589d8 5047 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
Kojto 90:cb3d968589d8 5048 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
Kojto 90:cb3d968589d8 5049 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
Kojto 90:cb3d968589d8 5050 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
Kojto 90:cb3d968589d8 5051 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
Kojto 90:cb3d968589d8 5052 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
Kojto 90:cb3d968589d8 5053 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
Kojto 90:cb3d968589d8 5054 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
Kojto 90:cb3d968589d8 5055 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
Kojto 90:cb3d968589d8 5056 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
Kojto 90:cb3d968589d8 5057 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
Kojto 90:cb3d968589d8 5058 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
Kojto 90:cb3d968589d8 5059 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
Kojto 90:cb3d968589d8 5060 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
Kojto 90:cb3d968589d8 5061 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
Kojto 90:cb3d968589d8 5062 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
Kojto 90:cb3d968589d8 5063 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
Kojto 90:cb3d968589d8 5064 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
Kojto 90:cb3d968589d8 5065 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
Kojto 90:cb3d968589d8 5066 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
Kojto 90:cb3d968589d8 5067 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
Kojto 90:cb3d968589d8 5068 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
Kojto 90:cb3d968589d8 5069 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
Kojto 90:cb3d968589d8 5070
Kojto 90:cb3d968589d8 5071 /******************* Bit definition for TSC_IOGCSR register *****************/
Kojto 90:cb3d968589d8 5072 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
Kojto 90:cb3d968589d8 5073 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
Kojto 90:cb3d968589d8 5074 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
Kojto 90:cb3d968589d8 5075 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
Kojto 90:cb3d968589d8 5076 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
Kojto 90:cb3d968589d8 5077 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
Kojto 90:cb3d968589d8 5078 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
Kojto 90:cb3d968589d8 5079 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
Kojto 90:cb3d968589d8 5080 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
Kojto 90:cb3d968589d8 5081 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
Kojto 90:cb3d968589d8 5082 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
Kojto 90:cb3d968589d8 5083 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
Kojto 90:cb3d968589d8 5084 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
Kojto 90:cb3d968589d8 5085 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
Kojto 90:cb3d968589d8 5086 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
Kojto 90:cb3d968589d8 5087 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
Kojto 90:cb3d968589d8 5088
Kojto 90:cb3d968589d8 5089 /******************* Bit definition for TSC_IOGXCR register *****************/
Kojto 90:cb3d968589d8 5090 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
Kojto 90:cb3d968589d8 5091
Kojto 90:cb3d968589d8 5092 /******************************************************************************/
Kojto 90:cb3d968589d8 5093 /* */
Kojto 90:cb3d968589d8 5094 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 90:cb3d968589d8 5095 /* */
Kojto 90:cb3d968589d8 5096 /******************************************************************************/
Kojto 90:cb3d968589d8 5097 /****************** Bit definition for USART_CR1 register *******************/
Kojto 90:cb3d968589d8 5098 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
Kojto 90:cb3d968589d8 5099 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
Kojto 90:cb3d968589d8 5100 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
Kojto 90:cb3d968589d8 5101 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
Kojto 90:cb3d968589d8 5102 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
Kojto 90:cb3d968589d8 5103 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
Kojto 90:cb3d968589d8 5104 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
Kojto 90:cb3d968589d8 5105 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
Kojto 90:cb3d968589d8 5106 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
Kojto 90:cb3d968589d8 5107 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
Kojto 90:cb3d968589d8 5108 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
Kojto 90:cb3d968589d8 5109 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
Kojto 90:cb3d968589d8 5110 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
Kojto 90:cb3d968589d8 5111 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
Kojto 90:cb3d968589d8 5112 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
Kojto 90:cb3d968589d8 5113 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 90:cb3d968589d8 5114 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 90:cb3d968589d8 5115 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 5116 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 5117 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 90:cb3d968589d8 5118 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 90:cb3d968589d8 5119 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 90:cb3d968589d8 5120 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 90:cb3d968589d8 5121 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 5122 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 5123 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
Kojto 90:cb3d968589d8 5124 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
Kojto 90:cb3d968589d8 5125 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
Kojto 90:cb3d968589d8 5126 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
Kojto 90:cb3d968589d8 5127 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
Kojto 90:cb3d968589d8 5128 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
Kojto 90:cb3d968589d8 5129 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
Kojto 90:cb3d968589d8 5130
Kojto 90:cb3d968589d8 5131 /****************** Bit definition for USART_CR2 register *******************/
Kojto 90:cb3d968589d8 5132 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
Kojto 90:cb3d968589d8 5133 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
Kojto 90:cb3d968589d8 5134 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
Kojto 90:cb3d968589d8 5135 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
Kojto 90:cb3d968589d8 5136 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
Kojto 90:cb3d968589d8 5137 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
Kojto 90:cb3d968589d8 5138 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
Kojto 90:cb3d968589d8 5139 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
Kojto 90:cb3d968589d8 5140 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 5141 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 5142 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
Kojto 90:cb3d968589d8 5143 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
Kojto 90:cb3d968589d8 5144 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
Kojto 90:cb3d968589d8 5145 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
Kojto 90:cb3d968589d8 5146 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
Kojto 90:cb3d968589d8 5147 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
Kojto 90:cb3d968589d8 5148 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
Kojto 90:cb3d968589d8 5149 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 90:cb3d968589d8 5150 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 5151 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 5152 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
Kojto 90:cb3d968589d8 5153 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
Kojto 90:cb3d968589d8 5154
Kojto 90:cb3d968589d8 5155 /****************** Bit definition for USART_CR3 register *******************/
Kojto 90:cb3d968589d8 5156 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
Kojto 90:cb3d968589d8 5157 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
Kojto 90:cb3d968589d8 5158 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
Kojto 90:cb3d968589d8 5159 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
Kojto 90:cb3d968589d8 5160 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
Kojto 90:cb3d968589d8 5161 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
Kojto 90:cb3d968589d8 5162 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
Kojto 90:cb3d968589d8 5163 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
Kojto 90:cb3d968589d8 5164 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
Kojto 90:cb3d968589d8 5165 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
Kojto 90:cb3d968589d8 5166 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
Kojto 90:cb3d968589d8 5167 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
Kojto 90:cb3d968589d8 5168 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
Kojto 90:cb3d968589d8 5169 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
Kojto 90:cb3d968589d8 5170 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
Kojto 90:cb3d968589d8 5171 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
Kojto 90:cb3d968589d8 5172 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 90:cb3d968589d8 5173 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 5174 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 5175 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
Kojto 90:cb3d968589d8 5176 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
Kojto 90:cb3d968589d8 5177 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 90:cb3d968589d8 5178 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 90:cb3d968589d8 5179 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
Kojto 90:cb3d968589d8 5180
Kojto 90:cb3d968589d8 5181 /****************** Bit definition for USART_BRR register *******************/
Kojto 90:cb3d968589d8 5182 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
Kojto 90:cb3d968589d8 5183 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
Kojto 90:cb3d968589d8 5184
Kojto 90:cb3d968589d8 5185 /****************** Bit definition for USART_GTPR register ******************/
Kojto 90:cb3d968589d8 5186 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
Kojto 90:cb3d968589d8 5187 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
Kojto 90:cb3d968589d8 5188
Kojto 90:cb3d968589d8 5189
Kojto 90:cb3d968589d8 5190 /******************* Bit definition for USART_RTOR register *****************/
Kojto 90:cb3d968589d8 5191 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
Kojto 90:cb3d968589d8 5192 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
Kojto 90:cb3d968589d8 5193
Kojto 90:cb3d968589d8 5194 /******************* Bit definition for USART_RQR register ******************/
Kojto 90:cb3d968589d8 5195 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
Kojto 90:cb3d968589d8 5196 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
Kojto 90:cb3d968589d8 5197 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
Kojto 90:cb3d968589d8 5198 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
Kojto 90:cb3d968589d8 5199 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
Kojto 90:cb3d968589d8 5200
Kojto 90:cb3d968589d8 5201 /******************* Bit definition for USART_ISR register ******************/
Kojto 90:cb3d968589d8 5202 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
Kojto 90:cb3d968589d8 5203 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
Kojto 90:cb3d968589d8 5204 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
Kojto 90:cb3d968589d8 5205 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
Kojto 90:cb3d968589d8 5206 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
Kojto 90:cb3d968589d8 5207 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
Kojto 90:cb3d968589d8 5208 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
Kojto 90:cb3d968589d8 5209 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
Kojto 90:cb3d968589d8 5210 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
Kojto 90:cb3d968589d8 5211 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
Kojto 90:cb3d968589d8 5212 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
Kojto 90:cb3d968589d8 5213 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
Kojto 90:cb3d968589d8 5214 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
Kojto 90:cb3d968589d8 5215 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
Kojto 90:cb3d968589d8 5216 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
Kojto 90:cb3d968589d8 5217 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
Kojto 90:cb3d968589d8 5218 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
Kojto 90:cb3d968589d8 5219 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
Kojto 90:cb3d968589d8 5220 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
Kojto 90:cb3d968589d8 5221 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
Kojto 90:cb3d968589d8 5222 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
Kojto 90:cb3d968589d8 5223 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
Kojto 90:cb3d968589d8 5224
Kojto 90:cb3d968589d8 5225 /******************* Bit definition for USART_ICR register ******************/
Kojto 90:cb3d968589d8 5226 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
Kojto 90:cb3d968589d8 5227 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
Kojto 90:cb3d968589d8 5228 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
Kojto 90:cb3d968589d8 5229 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
Kojto 90:cb3d968589d8 5230 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
Kojto 90:cb3d968589d8 5231 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
Kojto 90:cb3d968589d8 5232 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
Kojto 90:cb3d968589d8 5233 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
Kojto 90:cb3d968589d8 5234 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
Kojto 90:cb3d968589d8 5235 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
Kojto 90:cb3d968589d8 5236 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
Kojto 90:cb3d968589d8 5237 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
Kojto 90:cb3d968589d8 5238
Kojto 90:cb3d968589d8 5239 /******************* Bit definition for USART_RDR register ******************/
Kojto 90:cb3d968589d8 5240 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
Kojto 90:cb3d968589d8 5241
Kojto 90:cb3d968589d8 5242 /******************* Bit definition for USART_TDR register ******************/
Kojto 90:cb3d968589d8 5243 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 90:cb3d968589d8 5244
Kojto 90:cb3d968589d8 5245 /******************************************************************************/
Kojto 90:cb3d968589d8 5246 /* */
Kojto 90:cb3d968589d8 5247 /* Window WATCHDOG (WWDG) */
Kojto 90:cb3d968589d8 5248 /* */
Kojto 90:cb3d968589d8 5249 /******************************************************************************/
Kojto 90:cb3d968589d8 5250 /******************* Bit definition for WWDG_CR register ********************/
Kojto 90:cb3d968589d8 5251 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 90:cb3d968589d8 5252 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 90:cb3d968589d8 5253 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 90:cb3d968589d8 5254 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 90:cb3d968589d8 5255 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
Kojto 90:cb3d968589d8 5256 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
Kojto 90:cb3d968589d8 5257 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
Kojto 90:cb3d968589d8 5258 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
Kojto 90:cb3d968589d8 5259
Kojto 90:cb3d968589d8 5260 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Kojto 90:cb3d968589d8 5261
Kojto 90:cb3d968589d8 5262 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 90:cb3d968589d8 5263 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 90:cb3d968589d8 5264 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 90:cb3d968589d8 5265 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 90:cb3d968589d8 5266 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 90:cb3d968589d8 5267 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 90:cb3d968589d8 5268 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 90:cb3d968589d8 5269 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 90:cb3d968589d8 5270 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 90:cb3d968589d8 5271
Kojto 90:cb3d968589d8 5272 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 90:cb3d968589d8 5273 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
Kojto 90:cb3d968589d8 5274 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
Kojto 90:cb3d968589d8 5275
Kojto 90:cb3d968589d8 5276 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Kojto 90:cb3d968589d8 5277
Kojto 90:cb3d968589d8 5278 /******************* Bit definition for WWDG_SR register ********************/
Kojto 90:cb3d968589d8 5279 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Kojto 90:cb3d968589d8 5280
Kojto 90:cb3d968589d8 5281 /**
Kojto 90:cb3d968589d8 5282 * @}
Kojto 90:cb3d968589d8 5283 */
Kojto 90:cb3d968589d8 5284
Kojto 90:cb3d968589d8 5285 /**
Kojto 90:cb3d968589d8 5286 * @}
Kojto 90:cb3d968589d8 5287 */
Kojto 90:cb3d968589d8 5288
Kojto 90:cb3d968589d8 5289
Kojto 90:cb3d968589d8 5290 /** @addtogroup Exported_macro
Kojto 90:cb3d968589d8 5291 * @{
Kojto 90:cb3d968589d8 5292 */
Kojto 90:cb3d968589d8 5293
Kojto 90:cb3d968589d8 5294 /****************************** ADC Instances *********************************/
Kojto 90:cb3d968589d8 5295 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 90:cb3d968589d8 5296
Kojto 90:cb3d968589d8 5297 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
Kojto 90:cb3d968589d8 5298
Kojto 90:cb3d968589d8 5299 /******************************* CAN Instances ********************************/
Kojto 90:cb3d968589d8 5300 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
Kojto 90:cb3d968589d8 5301
Kojto 90:cb3d968589d8 5302 /****************************** COMP Instances *********************************/
Kojto 90:cb3d968589d8 5303 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
Kojto 90:cb3d968589d8 5304 ((INSTANCE) == COMP2))
Kojto 90:cb3d968589d8 5305
Kojto 90:cb3d968589d8 5306 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
Kojto 90:cb3d968589d8 5307
Kojto 90:cb3d968589d8 5308 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
Kojto 90:cb3d968589d8 5309
Kojto 90:cb3d968589d8 5310 /****************************** CEC Instances *********************************/
Kojto 90:cb3d968589d8 5311 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
Kojto 90:cb3d968589d8 5312
Kojto 90:cb3d968589d8 5313 /****************************** CRC Instances *********************************/
Kojto 90:cb3d968589d8 5314 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 90:cb3d968589d8 5315
Kojto 90:cb3d968589d8 5316 /******************************* DAC Instances ********************************/
Kojto 90:cb3d968589d8 5317 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
Kojto 90:cb3d968589d8 5318
Kojto 90:cb3d968589d8 5319 /******************************* DMA Instances ******************************/
Kojto 90:cb3d968589d8 5320 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 90:cb3d968589d8 5321 ((INSTANCE) == DMA1_Channel2) || \
Kojto 90:cb3d968589d8 5322 ((INSTANCE) == DMA1_Channel3) || \
Kojto 90:cb3d968589d8 5323 ((INSTANCE) == DMA1_Channel4) || \
Kojto 90:cb3d968589d8 5324 ((INSTANCE) == DMA1_Channel5) || \
Kojto 90:cb3d968589d8 5325 ((INSTANCE) == DMA1_Channel6) || \
Kojto 90:cb3d968589d8 5326 ((INSTANCE) == DMA1_Channel7) || \
Kojto 90:cb3d968589d8 5327 ((INSTANCE) == DMA2_Channel1) || \
Kojto 90:cb3d968589d8 5328 ((INSTANCE) == DMA2_Channel2) || \
Kojto 90:cb3d968589d8 5329 ((INSTANCE) == DMA2_Channel3) || \
Kojto 90:cb3d968589d8 5330 ((INSTANCE) == DMA2_Channel4) || \
Kojto 90:cb3d968589d8 5331 ((INSTANCE) == DMA2_Channel5))
Kojto 90:cb3d968589d8 5332
Kojto 90:cb3d968589d8 5333 /****************************** GPIO Instances ********************************/
Kojto 93:e188a91d3eaa 5334 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 5335 ((INSTANCE) == GPIOB) || \
Kojto 93:e188a91d3eaa 5336 ((INSTANCE) == GPIOC) || \
Kojto 93:e188a91d3eaa 5337 ((INSTANCE) == GPIOD) || \
Kojto 93:e188a91d3eaa 5338 ((INSTANCE) == GPIOE) || \
Kojto 93:e188a91d3eaa 5339 ((INSTANCE) == GPIOF))
Kojto 93:e188a91d3eaa 5340
Kojto 93:e188a91d3eaa 5341 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 5342 ((INSTANCE) == GPIOB) || \
Kojto 93:e188a91d3eaa 5343 ((INSTANCE) == GPIOC) || \
Kojto 93:e188a91d3eaa 5344 ((INSTANCE) == GPIOD) || \
Kojto 93:e188a91d3eaa 5345 ((INSTANCE) == GPIOE) || \
Kojto 93:e188a91d3eaa 5346 ((INSTANCE) == GPIOF))
Kojto 93:e188a91d3eaa 5347
Kojto 90:cb3d968589d8 5348 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 90:cb3d968589d8 5349 ((INSTANCE) == GPIOB))
Kojto 90:cb3d968589d8 5350
Kojto 90:cb3d968589d8 5351 /****************************** I2C Instances *********************************/
Kojto 90:cb3d968589d8 5352 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 90:cb3d968589d8 5353 ((INSTANCE) == I2C2))
Kojto 90:cb3d968589d8 5354
Kojto 90:cb3d968589d8 5355 /****************************** I2S Instances *********************************/
Kojto 90:cb3d968589d8 5356 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 90:cb3d968589d8 5357 ((INSTANCE) == SPI2))
Kojto 90:cb3d968589d8 5358
Kojto 90:cb3d968589d8 5359 /****************************** IWDG Instances ********************************/
Kojto 90:cb3d968589d8 5360 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 90:cb3d968589d8 5361
Kojto 90:cb3d968589d8 5362 /****************************** RTC Instances *********************************/
Kojto 90:cb3d968589d8 5363 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 90:cb3d968589d8 5364
Kojto 90:cb3d968589d8 5365 /****************************** SMBUS Instances *********************************/
Kojto 90:cb3d968589d8 5366 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 90:cb3d968589d8 5367
Kojto 90:cb3d968589d8 5368 /****************************** SPI Instances *********************************/
Kojto 90:cb3d968589d8 5369 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 90:cb3d968589d8 5370 ((INSTANCE) == SPI2))
Kojto 90:cb3d968589d8 5371
Kojto 90:cb3d968589d8 5372 /****************************** TIM Instances *********************************/
Kojto 90:cb3d968589d8 5373 #define IS_TIM_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5374 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5375 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5376 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5377 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 5378 ((INSTANCE) == TIM7) || \
Kojto 90:cb3d968589d8 5379 ((INSTANCE) == TIM14) || \
Kojto 90:cb3d968589d8 5380 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5381 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5382 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5383
Kojto 90:cb3d968589d8 5384 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5385 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5386 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5387 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5388 ((INSTANCE) == TIM14) || \
Kojto 90:cb3d968589d8 5389 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5390 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5391 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5392
Kojto 90:cb3d968589d8 5393 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5394 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5395 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5396 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5397 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5398
Kojto 90:cb3d968589d8 5399 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5400 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5401 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5402 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5403
Kojto 90:cb3d968589d8 5404 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5405 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5406 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5407 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5408
Kojto 90:cb3d968589d8 5409 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5410 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5411 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5412 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5413
Kojto 90:cb3d968589d8 5414 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5415 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5416 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5417 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5418
Kojto 90:cb3d968589d8 5419 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5420 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5421 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5422 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5423 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5424
Kojto 90:cb3d968589d8 5425 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5426 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5427 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5428 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5429 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5430
Kojto 90:cb3d968589d8 5431 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5432 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5433 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5434 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5435
Kojto 90:cb3d968589d8 5436 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5437 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5438 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5439 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5440
Kojto 90:cb3d968589d8 5441 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5442 (((INSTANCE) == TIM1))
Kojto 90:cb3d968589d8 5443
Kojto 90:cb3d968589d8 5444 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5445 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5446 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5447 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5448
Kojto 90:cb3d968589d8 5449 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5450 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5451 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5452 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5453 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 5454 ((INSTANCE) == TIM7) || \
Kojto 90:cb3d968589d8 5455 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5456
Kojto 90:cb3d968589d8 5457 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5458 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5459 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5460 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5461 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5462
Kojto 90:cb3d968589d8 5463 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5464 ((INSTANCE) == TIM2)
Kojto 90:cb3d968589d8 5465
Kojto 90:cb3d968589d8 5466 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5467 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5468 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5469 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5470 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5471 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5472 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5473
Kojto 90:cb3d968589d8 5474 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5475 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5476 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5477 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5478 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5479
Kojto 90:cb3d968589d8 5480 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 90:cb3d968589d8 5481 ((((INSTANCE) == TIM1) && \
Kojto 90:cb3d968589d8 5482 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 5483 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 5484 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 5485 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 5486 || \
Kojto 90:cb3d968589d8 5487 (((INSTANCE) == TIM2) && \
Kojto 90:cb3d968589d8 5488 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 5489 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 5490 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 5491 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 5492 || \
Kojto 90:cb3d968589d8 5493 (((INSTANCE) == TIM3) && \
Kojto 90:cb3d968589d8 5494 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 5495 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 5496 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 5497 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 5498 || \
Kojto 90:cb3d968589d8 5499 (((INSTANCE) == TIM14) && \
Kojto 90:cb3d968589d8 5500 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 90:cb3d968589d8 5501 || \
Kojto 90:cb3d968589d8 5502 (((INSTANCE) == TIM15) && \
Kojto 90:cb3d968589d8 5503 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 5504 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 90:cb3d968589d8 5505 || \
Kojto 90:cb3d968589d8 5506 (((INSTANCE) == TIM16) && \
Kojto 90:cb3d968589d8 5507 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 90:cb3d968589d8 5508 || \
Kojto 90:cb3d968589d8 5509 (((INSTANCE) == TIM17) && \
Kojto 90:cb3d968589d8 5510 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 90:cb3d968589d8 5511
Kojto 90:cb3d968589d8 5512 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 90:cb3d968589d8 5513 ((((INSTANCE) == TIM1) && \
Kojto 90:cb3d968589d8 5514 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 5515 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 5516 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 90:cb3d968589d8 5517 || \
Kojto 90:cb3d968589d8 5518 (((INSTANCE) == TIM15) && \
Kojto 90:cb3d968589d8 5519 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 90:cb3d968589d8 5520 || \
Kojto 90:cb3d968589d8 5521 (((INSTANCE) == TIM16) && \
Kojto 90:cb3d968589d8 5522 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 90:cb3d968589d8 5523 || \
Kojto 90:cb3d968589d8 5524 (((INSTANCE) == TIM17) && \
Kojto 90:cb3d968589d8 5525 ((CHANNEL) == TIM_CHANNEL_1)))
Kojto 90:cb3d968589d8 5526
Kojto 90:cb3d968589d8 5527 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5528 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5529 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5530 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5531
Kojto 90:cb3d968589d8 5532 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5533 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5534 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5535 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5536 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5537
Kojto 90:cb3d968589d8 5538 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5539 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5540 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5541 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5542 ((INSTANCE) == TIM14) || \
Kojto 90:cb3d968589d8 5543 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5544 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5545 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5546
Kojto 90:cb3d968589d8 5547 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5548 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5549 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5550 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5551 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 5552 ((INSTANCE) == TIM7) || \
Kojto 90:cb3d968589d8 5553 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5554 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5555 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5556
Kojto 90:cb3d968589d8 5557 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5558 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5559 ((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 5560 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5561 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5562 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5563 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5564
Kojto 90:cb3d968589d8 5565 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5566 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5567 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5568 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5569 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5570
Kojto 90:cb3d968589d8 5571 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5572 ((INSTANCE) == TIM14)
Kojto 90:cb3d968589d8 5573
Kojto 90:cb3d968589d8 5574 /****************************** TSC Instances *********************************/
Kojto 90:cb3d968589d8 5575 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
Kojto 90:cb3d968589d8 5576
Kojto 90:cb3d968589d8 5577 /*********************** UART Instances : IRDA mode ***************************/
Kojto 90:cb3d968589d8 5578 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5579 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5580 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 5581
Kojto 90:cb3d968589d8 5582 /********************* UART Instances : Smard card mode ***********************/
Kojto 90:cb3d968589d8 5583 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5584 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5585 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 5586
Kojto 90:cb3d968589d8 5587 /******************** USART Instances : Synchronous mode **********************/
Kojto 90:cb3d968589d8 5588 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5589 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5590 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 5591 ((INSTANCE) == USART4) || \
Kojto 90:cb3d968589d8 5592 ((INSTANCE) == USART5) || \
Kojto 90:cb3d968589d8 5593 ((INSTANCE) == USART6) || \
Kojto 90:cb3d968589d8 5594 ((INSTANCE) == USART7) || \
Kojto 90:cb3d968589d8 5595 ((INSTANCE) == USART8))
Kojto 90:cb3d968589d8 5596
Kojto 90:cb3d968589d8 5597 /******************** USART Instances : auto Baud rate detection **************/
Kojto 90:cb3d968589d8 5598 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5599 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5600 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 5601
Kojto 90:cb3d968589d8 5602 /******************** UART Instances : Asynchronous mode **********************/
Kojto 90:cb3d968589d8 5603 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5604 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5605 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 5606 ((INSTANCE) == USART4) || \
Kojto 90:cb3d968589d8 5607 ((INSTANCE) == USART5) || \
Kojto 90:cb3d968589d8 5608 ((INSTANCE) == USART6) || \
Kojto 90:cb3d968589d8 5609 ((INSTANCE) == USART7) || \
Kojto 90:cb3d968589d8 5610 ((INSTANCE) == USART8))
Kojto 90:cb3d968589d8 5611
Kojto 90:cb3d968589d8 5612 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 90:cb3d968589d8 5613 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5614 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5615 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 5616 ((INSTANCE) == USART4) || \
Kojto 90:cb3d968589d8 5617 ((INSTANCE) == USART5) || \
Kojto 90:cb3d968589d8 5618 ((INSTANCE) == USART6) || \
Kojto 90:cb3d968589d8 5619 ((INSTANCE) == USART7) || \
Kojto 90:cb3d968589d8 5620 ((INSTANCE) == USART8))
Kojto 90:cb3d968589d8 5621
Kojto 90:cb3d968589d8 5622 /****************** UART Instances : Hardware Flow control ********************/
Kojto 90:cb3d968589d8 5623 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5624 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5625 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 5626 ((INSTANCE) == USART4) || \
Kojto 90:cb3d968589d8 5627 ((INSTANCE) == USART5) || \
Kojto 90:cb3d968589d8 5628 ((INSTANCE) == USART6) || \
Kojto 90:cb3d968589d8 5629 ((INSTANCE) == USART7) || \
Kojto 90:cb3d968589d8 5630 ((INSTANCE) == USART8))
Kojto 90:cb3d968589d8 5631
Kojto 90:cb3d968589d8 5632 /****************** UART Instances : LIN mode ********************/
Kojto 90:cb3d968589d8 5633 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5634 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5635 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 5636
Kojto 90:cb3d968589d8 5637 /****************** UART Instances : wakeup from stop mode ********************/
Kojto 90:cb3d968589d8 5638 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5639 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5640 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 5641
Kojto 90:cb3d968589d8 5642 /****************** UART Instances : Auto Baud Rate detection ********************/
Kojto 90:cb3d968589d8 5643 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5644 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5645 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 5646
Kojto 90:cb3d968589d8 5647 /****************** UART Instances : Driver enable detection ********************/
Kojto 90:cb3d968589d8 5648 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5649 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 5650 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 5651 ((INSTANCE) == USART4) || \
Kojto 90:cb3d968589d8 5652 ((INSTANCE) == USART5) || \
Kojto 90:cb3d968589d8 5653 ((INSTANCE) == USART6) || \
Kojto 90:cb3d968589d8 5654 ((INSTANCE) == USART7) || \
Kojto 90:cb3d968589d8 5655 ((INSTANCE) == USART8))
Kojto 90:cb3d968589d8 5656
Kojto 90:cb3d968589d8 5657 /****************************** WWDG Instances ********************************/
Kojto 90:cb3d968589d8 5658 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 90:cb3d968589d8 5659
Kojto 90:cb3d968589d8 5660 /**
Kojto 90:cb3d968589d8 5661 * @}
Kojto 90:cb3d968589d8 5662 */
Kojto 90:cb3d968589d8 5663
Kojto 90:cb3d968589d8 5664 /******************************************************************************/
Kojto 90:cb3d968589d8 5665 /* For a painless codes migration between the STM32F3xx device product */
Kojto 90:cb3d968589d8 5666 /* lines, the aliases defined below are put in place to overcome the */
Kojto 90:cb3d968589d8 5667 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 90:cb3d968589d8 5668 /* No need to update developed interrupt code when moving across */
Kojto 90:cb3d968589d8 5669 /* product lines within the same STM32L0 Family */
Kojto 90:cb3d968589d8 5670 /******************************************************************************/
Kojto 90:cb3d968589d8 5671
Kojto 90:cb3d968589d8 5672 /* Aliases for __IRQn */
Kojto 90:cb3d968589d8 5673 #define PVD_IRQn PVD_VDDIO2_IRQn
Kojto 90:cb3d968589d8 5674 #define VDDIO2_IRQn PVD_VDDIO2_IRQn
Kojto 90:cb3d968589d8 5675 #define RCC_IRQn RCC_CRS_IRQn
Kojto 90:cb3d968589d8 5676 #define DMA1_Channel1_IRQn DMA1_Ch1_IRQn
Kojto 90:cb3d968589d8 5677 #define DMA1_Channel2_3_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn
Kojto 90:cb3d968589d8 5678 #define DMA1_Channel4_5_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn
Kojto 90:cb3d968589d8 5679 #define DMA1_Channel4_5_6_7_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn
Kojto 90:cb3d968589d8 5680 #define ADC1_IRQn ADC1_COMP_IRQn
Kojto 90:cb3d968589d8 5681 #define TIM6_IRQn TIM6_DAC_IRQn
Kojto 90:cb3d968589d8 5682 #define USART3_4_IRQn USART3_8_IRQn
Kojto 90:cb3d968589d8 5683
Kojto 90:cb3d968589d8 5684 /* Aliases for __IRQHandler */
Kojto 90:cb3d968589d8 5685 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
Kojto 90:cb3d968589d8 5686 #define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
Kojto 90:cb3d968589d8 5687 #define RCC_IRQHandler RCC_CRS_IRQHandler
Kojto 90:cb3d968589d8 5688 #define DMA1_Channel1_IRQHandler DMA1_Ch1_IRQHandler
Kojto 90:cb3d968589d8 5689 #define DMA1_Channel2_3_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
Kojto 90:cb3d968589d8 5690 #define DMA1_Channel4_5_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
Kojto 90:cb3d968589d8 5691 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
Kojto 90:cb3d968589d8 5692 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
Kojto 90:cb3d968589d8 5693 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
Kojto 90:cb3d968589d8 5694 #define USART3_4_IRQHandler USART3_8_IRQHandler
Kojto 90:cb3d968589d8 5695
Kojto 90:cb3d968589d8 5696 #ifdef __cplusplus
Kojto 90:cb3d968589d8 5697 }
Kojto 90:cb3d968589d8 5698 #endif /* __cplusplus */
Kojto 90:cb3d968589d8 5699
Kojto 90:cb3d968589d8 5700 #endif /* __STM32F091xC_H */
Kojto 90:cb3d968589d8 5701
Kojto 90:cb3d968589d8 5702 /**
Kojto 90:cb3d968589d8 5703 * @}
Kojto 90:cb3d968589d8 5704 */
Kojto 90:cb3d968589d8 5705
Kojto 90:cb3d968589d8 5706 /**
Kojto 90:cb3d968589d8 5707 * @}
Kojto 90:cb3d968589d8 5708 */
Kojto 90:cb3d968589d8 5709
Kojto 90:cb3d968589d8 5710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/