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TARGET_NUCLEO_F070RB/stm32f0xx_hal_rcc_ex.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
93:e188a91d3eaa 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 93:e188a91d3eaa 1 /**
Kojto 93:e188a91d3eaa 2 ******************************************************************************
Kojto 93:e188a91d3eaa 3 * @file stm32f0xx_hal_rcc_ex.h
Kojto 93:e188a91d3eaa 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V1.2.0
Kojto 93:e188a91d3eaa 6 * @date 11-December-2014
Kojto 93:e188a91d3eaa 7 * @brief Header file of RCC HAL Extension module.
Kojto 93:e188a91d3eaa 8 ******************************************************************************
Kojto 93:e188a91d3eaa 9 * @attention
Kojto 93:e188a91d3eaa 10 *
Kojto 93:e188a91d3eaa 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 93:e188a91d3eaa 12 *
Kojto 93:e188a91d3eaa 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 93:e188a91d3eaa 14 * are permitted provided that the following conditions are met:
Kojto 93:e188a91d3eaa 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 93:e188a91d3eaa 16 * this list of conditions and the following disclaimer.
Kojto 93:e188a91d3eaa 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 93:e188a91d3eaa 18 * this list of conditions and the following disclaimer in the documentation
Kojto 93:e188a91d3eaa 19 * and/or other materials provided with the distribution.
Kojto 93:e188a91d3eaa 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 93:e188a91d3eaa 21 * may be used to endorse or promote products derived from this software
Kojto 93:e188a91d3eaa 22 * without specific prior written permission.
Kojto 93:e188a91d3eaa 23 *
Kojto 93:e188a91d3eaa 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 93:e188a91d3eaa 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 93:e188a91d3eaa 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 93:e188a91d3eaa 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 93:e188a91d3eaa 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 93:e188a91d3eaa 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 93:e188a91d3eaa 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 93:e188a91d3eaa 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 93:e188a91d3eaa 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 93:e188a91d3eaa 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 93:e188a91d3eaa 34 *
Kojto 93:e188a91d3eaa 35 ******************************************************************************
Kojto 93:e188a91d3eaa 36 */
Kojto 93:e188a91d3eaa 37
Kojto 93:e188a91d3eaa 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 93:e188a91d3eaa 39 #ifndef __STM32F0xx_HAL_RCC_EX_H
Kojto 93:e188a91d3eaa 40 #define __STM32F0xx_HAL_RCC_EX_H
Kojto 93:e188a91d3eaa 41
Kojto 93:e188a91d3eaa 42 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 43 extern "C" {
Kojto 93:e188a91d3eaa 44 #endif
Kojto 93:e188a91d3eaa 45
Kojto 93:e188a91d3eaa 46 /* Includes ------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 47 #include "stm32f0xx_hal_def.h"
Kojto 93:e188a91d3eaa 48
Kojto 93:e188a91d3eaa 49 /** @addtogroup STM32F0xx_HAL_Driver
Kojto 93:e188a91d3eaa 50 * @{
Kojto 93:e188a91d3eaa 51 */
Kojto 93:e188a91d3eaa 52
Kojto 93:e188a91d3eaa 53 /** @addtogroup RCCEx
Kojto 93:e188a91d3eaa 54 * @{
Kojto 93:e188a91d3eaa 55 */
Kojto 93:e188a91d3eaa 56
Kojto 93:e188a91d3eaa 57 /* Exported types ------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 58
Kojto 93:e188a91d3eaa 59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 93:e188a91d3eaa 60 * @{
Kojto 93:e188a91d3eaa 61 */
Kojto 93:e188a91d3eaa 62
Kojto 93:e188a91d3eaa 63 /**
Kojto 93:e188a91d3eaa 64 * @brief RCC extended clocks structure definition
Kojto 93:e188a91d3eaa 65 */
Kojto 93:e188a91d3eaa 66 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 93:e188a91d3eaa 67 defined(STM32F030xC)
Kojto 93:e188a91d3eaa 68 typedef struct
Kojto 93:e188a91d3eaa 69 {
Kojto 93:e188a91d3eaa 70 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 71 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 72
Kojto 93:e188a91d3eaa 73 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 93:e188a91d3eaa 74 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 75
Kojto 93:e188a91d3eaa 76 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 93:e188a91d3eaa 77 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 93:e188a91d3eaa 78
Kojto 93:e188a91d3eaa 79 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 93:e188a91d3eaa 80 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 93:e188a91d3eaa 81
Kojto 93:e188a91d3eaa 82 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 83 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
Kojto 93:e188a91d3eaa 84 STM32F030xC */
Kojto 93:e188a91d3eaa 85
Kojto 93:e188a91d3eaa 86 #if defined(STM32F070x6) || defined(STM32F070xB)
Kojto 93:e188a91d3eaa 87 typedef struct
Kojto 93:e188a91d3eaa 88 {
Kojto 93:e188a91d3eaa 89 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 90 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 91
Kojto 93:e188a91d3eaa 92 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 93:e188a91d3eaa 93 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 94
Kojto 93:e188a91d3eaa 95 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 93:e188a91d3eaa 96 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 93:e188a91d3eaa 97
Kojto 93:e188a91d3eaa 98 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 93:e188a91d3eaa 99 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 93:e188a91d3eaa 100
Kojto 93:e188a91d3eaa 101 uint32_t UsbClockSelection; /*!< USB clock source
Kojto 93:e188a91d3eaa 102 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 93:e188a91d3eaa 103
Kojto 93:e188a91d3eaa 104 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 105 #endif /* STM32F070x6 || STM32F070xB */
Kojto 93:e188a91d3eaa 106
Kojto 93:e188a91d3eaa 107 #if defined(STM32F042x6) || defined(STM32F048xx)
Kojto 93:e188a91d3eaa 108 typedef struct
Kojto 93:e188a91d3eaa 109 {
Kojto 93:e188a91d3eaa 110 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 111 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 112
Kojto 93:e188a91d3eaa 113 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 93:e188a91d3eaa 114 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 115
Kojto 93:e188a91d3eaa 116 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 93:e188a91d3eaa 117 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 93:e188a91d3eaa 118
Kojto 93:e188a91d3eaa 119 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 93:e188a91d3eaa 120 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 93:e188a91d3eaa 121
Kojto 93:e188a91d3eaa 122 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 93:e188a91d3eaa 123 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 93:e188a91d3eaa 124
Kojto 93:e188a91d3eaa 125 uint32_t UsbClockSelection; /*!< USB clock source
Kojto 93:e188a91d3eaa 126 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 93:e188a91d3eaa 127
Kojto 93:e188a91d3eaa 128 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 129 #endif /* STM32F042x6 || STM32F048xx */
Kojto 93:e188a91d3eaa 130
Kojto 93:e188a91d3eaa 131 #if defined(STM32F051x8) || defined(STM32F058xx)
Kojto 93:e188a91d3eaa 132 typedef struct
Kojto 93:e188a91d3eaa 133 {
Kojto 93:e188a91d3eaa 134 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 135 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 136
Kojto 93:e188a91d3eaa 137 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 93:e188a91d3eaa 138 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 139
Kojto 93:e188a91d3eaa 140 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 93:e188a91d3eaa 141 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 93:e188a91d3eaa 142
Kojto 93:e188a91d3eaa 143 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 93:e188a91d3eaa 144 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 93:e188a91d3eaa 145
Kojto 93:e188a91d3eaa 146 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 93:e188a91d3eaa 147 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 93:e188a91d3eaa 148
Kojto 93:e188a91d3eaa 149 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 150 #endif /* STM32F051x8 || STM32F058xx */
Kojto 93:e188a91d3eaa 151
Kojto 93:e188a91d3eaa 152 #if defined(STM32F071xB)
Kojto 93:e188a91d3eaa 153 typedef struct
Kojto 93:e188a91d3eaa 154 {
Kojto 93:e188a91d3eaa 155 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 156 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 157
Kojto 93:e188a91d3eaa 158 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 93:e188a91d3eaa 159 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 160
Kojto 93:e188a91d3eaa 161 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 93:e188a91d3eaa 162 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 93:e188a91d3eaa 163
Kojto 93:e188a91d3eaa 164 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 93:e188a91d3eaa 165 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 93:e188a91d3eaa 166
Kojto 93:e188a91d3eaa 167 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 93:e188a91d3eaa 168 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 93:e188a91d3eaa 169
Kojto 93:e188a91d3eaa 170 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 93:e188a91d3eaa 171 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 93:e188a91d3eaa 172
Kojto 93:e188a91d3eaa 173 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 174 #endif /* STM32F071xB */
Kojto 93:e188a91d3eaa 175
Kojto 93:e188a91d3eaa 176 #if defined(STM32F072xB) || defined(STM32F078xx)
Kojto 93:e188a91d3eaa 177 typedef struct
Kojto 93:e188a91d3eaa 178 {
Kojto 93:e188a91d3eaa 179 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 180 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 181
Kojto 93:e188a91d3eaa 182 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 93:e188a91d3eaa 183 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 184
Kojto 93:e188a91d3eaa 185 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 93:e188a91d3eaa 186 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 93:e188a91d3eaa 187
Kojto 93:e188a91d3eaa 188 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 93:e188a91d3eaa 189 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 93:e188a91d3eaa 190
Kojto 93:e188a91d3eaa 191 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 93:e188a91d3eaa 192 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 93:e188a91d3eaa 193
Kojto 93:e188a91d3eaa 194 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 93:e188a91d3eaa 195 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 93:e188a91d3eaa 196
Kojto 93:e188a91d3eaa 197 uint32_t UsbClockSelection; /*!< USB clock source
Kojto 93:e188a91d3eaa 198 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 93:e188a91d3eaa 199
Kojto 93:e188a91d3eaa 200 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 201 #endif /* STM32F072xB || STM32F078xx */
Kojto 93:e188a91d3eaa 202
Kojto 93:e188a91d3eaa 203
Kojto 93:e188a91d3eaa 204 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 205 typedef struct
Kojto 93:e188a91d3eaa 206 {
Kojto 93:e188a91d3eaa 207 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 208 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 209
Kojto 93:e188a91d3eaa 210 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 93:e188a91d3eaa 211 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 212
Kojto 93:e188a91d3eaa 213 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 93:e188a91d3eaa 214 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 93:e188a91d3eaa 215
Kojto 93:e188a91d3eaa 216 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 93:e188a91d3eaa 217 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 93:e188a91d3eaa 218
Kojto 93:e188a91d3eaa 219 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 93:e188a91d3eaa 220 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto 93:e188a91d3eaa 221
Kojto 93:e188a91d3eaa 222 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 93:e188a91d3eaa 223 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 93:e188a91d3eaa 224
Kojto 93:e188a91d3eaa 225 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 93:e188a91d3eaa 226 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 93:e188a91d3eaa 227
Kojto 93:e188a91d3eaa 228 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 229 #endif /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 230
Kojto 93:e188a91d3eaa 231 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 232 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 233 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 234
Kojto 93:e188a91d3eaa 235 /**
Kojto 93:e188a91d3eaa 236 * @brief RCC_CRS Init structure definition
Kojto 93:e188a91d3eaa 237 */
Kojto 93:e188a91d3eaa 238 typedef struct
Kojto 93:e188a91d3eaa 239 {
Kojto 93:e188a91d3eaa 240 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
Kojto 93:e188a91d3eaa 241 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
Kojto 93:e188a91d3eaa 242
Kojto 93:e188a91d3eaa 243 uint32_t Source; /*!< Specifies the SYNC signal source.
Kojto 93:e188a91d3eaa 244 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
Kojto 93:e188a91d3eaa 245
Kojto 93:e188a91d3eaa 246 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
Kojto 93:e188a91d3eaa 247 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
Kojto 93:e188a91d3eaa 248
Kojto 93:e188a91d3eaa 249 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
Kojto 93:e188a91d3eaa 250 It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
Kojto 93:e188a91d3eaa 251 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
Kojto 93:e188a91d3eaa 252
Kojto 93:e188a91d3eaa 253 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
Kojto 93:e188a91d3eaa 254 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
Kojto 93:e188a91d3eaa 255
Kojto 93:e188a91d3eaa 256 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
Kojto 93:e188a91d3eaa 257 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
Kojto 93:e188a91d3eaa 258
Kojto 93:e188a91d3eaa 259 }RCC_CRSInitTypeDef;
Kojto 93:e188a91d3eaa 260
Kojto 93:e188a91d3eaa 261 /**
Kojto 93:e188a91d3eaa 262 * @brief RCC_CRS Synchronization structure definition
Kojto 93:e188a91d3eaa 263 */
Kojto 93:e188a91d3eaa 264 typedef struct
Kojto 93:e188a91d3eaa 265 {
Kojto 93:e188a91d3eaa 266 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Kojto 93:e188a91d3eaa 267 This parameter must be a number between 0 and 0xFFFF*/
Kojto 93:e188a91d3eaa 268
Kojto 93:e188a91d3eaa 269 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
Kojto 93:e188a91d3eaa 270 This parameter must be a number between 0 and 0x3F */
Kojto 93:e188a91d3eaa 271
Kojto 93:e188a91d3eaa 272 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
Kojto 93:e188a91d3eaa 273 value latched in the time of the last SYNC event.
Kojto 93:e188a91d3eaa 274 This parameter must be a number between 0 and 0xFFFF */
Kojto 93:e188a91d3eaa 275
Kojto 93:e188a91d3eaa 276 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
Kojto 93:e188a91d3eaa 277 frequency error counter latched in the time of the last SYNC event.
Kojto 93:e188a91d3eaa 278 It shows whether the actual frequency is below or above the target.
Kojto 93:e188a91d3eaa 279 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
Kojto 93:e188a91d3eaa 280
Kojto 93:e188a91d3eaa 281 }RCC_CRSSynchroInfoTypeDef;
Kojto 93:e188a91d3eaa 282
Kojto 93:e188a91d3eaa 283 #endif /* STM32F042x6 || STM32F048xx */
Kojto 93:e188a91d3eaa 284 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 285 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 286
Kojto 93:e188a91d3eaa 287 /**
Kojto 93:e188a91d3eaa 288 * @}
Kojto 93:e188a91d3eaa 289 */
Kojto 93:e188a91d3eaa 290
Kojto 93:e188a91d3eaa 291 /* Exported constants --------------------------------------------------------*/
Kojto 93:e188a91d3eaa 292
Kojto 93:e188a91d3eaa 293 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 93:e188a91d3eaa 294 * @{
Kojto 93:e188a91d3eaa 295 */
Kojto 93:e188a91d3eaa 296
Kojto 93:e188a91d3eaa 297 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
Kojto 93:e188a91d3eaa 298 * @{
Kojto 93:e188a91d3eaa 299 */
Kojto 93:e188a91d3eaa 300 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 301 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 302 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 303
Kojto 93:e188a91d3eaa 304 #define RCC_CRS_NONE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 305 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 306 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 307 #define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 308 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 309 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 310 #define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 311
Kojto 93:e188a91d3eaa 312 #endif /* STM32F042x6 || STM32F048xx */
Kojto 93:e188a91d3eaa 313 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 314 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 315 /**
Kojto 93:e188a91d3eaa 316 * @}
Kojto 93:e188a91d3eaa 317 */
Kojto 93:e188a91d3eaa 318
Kojto 93:e188a91d3eaa 319 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
Kojto 93:e188a91d3eaa 320 * @{
Kojto 93:e188a91d3eaa 321 */
Kojto 93:e188a91d3eaa 322 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 93:e188a91d3eaa 323 defined(STM32F030xC)
Kojto 93:e188a91d3eaa 324 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 325 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 326 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 327
Kojto 93:e188a91d3eaa 328 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
Kojto 93:e188a91d3eaa 329 RCC_PERIPHCLK_RTC))
Kojto 93:e188a91d3eaa 330 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
Kojto 93:e188a91d3eaa 331 STM32F030xC */
Kojto 93:e188a91d3eaa 332
Kojto 93:e188a91d3eaa 333 #if defined(STM32F070x6) || defined(STM32F070xB)
Kojto 93:e188a91d3eaa 334 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 335 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 336 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 337 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 338
Kojto 93:e188a91d3eaa 339 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
Kojto 93:e188a91d3eaa 340 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
Kojto 93:e188a91d3eaa 341 #endif /* STM32F070x6 || STM32F070xB */
Kojto 93:e188a91d3eaa 342
Kojto 93:e188a91d3eaa 343 #if defined(STM32F042x6) || defined(STM32F048xx)
Kojto 93:e188a91d3eaa 344 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 345 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 346 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 347 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 348 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 349
Kojto 93:e188a91d3eaa 350 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
Kojto 93:e188a91d3eaa 351 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
Kojto 93:e188a91d3eaa 352 RCC_PERIPHCLK_USB))
Kojto 93:e188a91d3eaa 353 #endif /* STM32F042x6 || STM32F048xx */
Kojto 93:e188a91d3eaa 354
Kojto 93:e188a91d3eaa 355 #if defined(STM32F051x8) || defined(STM32F058xx)
Kojto 93:e188a91d3eaa 356 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 357 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 358 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 359 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 360
Kojto 93:e188a91d3eaa 361 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
Kojto 93:e188a91d3eaa 362 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
Kojto 93:e188a91d3eaa 363 #endif /* STM32F051x8 || STM32F058xx */
Kojto 93:e188a91d3eaa 364
Kojto 93:e188a91d3eaa 365 #if defined(STM32F071xB)
Kojto 93:e188a91d3eaa 366 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 367 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 368 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 369 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 370 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 371
Kojto 93:e188a91d3eaa 372 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
Kojto 93:e188a91d3eaa 373 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
Kojto 93:e188a91d3eaa 374 RCC_PERIPHCLK_RTC))
Kojto 93:e188a91d3eaa 375 #endif /* STM32F071xB */
Kojto 93:e188a91d3eaa 376
Kojto 93:e188a91d3eaa 377 #if defined(STM32F072xB) || defined(STM32F078xx)
Kojto 93:e188a91d3eaa 378 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 379 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 380 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 381 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 382 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 383 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 384
Kojto 93:e188a91d3eaa 385 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
Kojto 93:e188a91d3eaa 386 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
Kojto 93:e188a91d3eaa 387 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
Kojto 93:e188a91d3eaa 388 #endif /* STM32F072xB || STM32F078xx */
Kojto 93:e188a91d3eaa 389
Kojto 93:e188a91d3eaa 390 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 391 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 392 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 393 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 394 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 395 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 396 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 397
Kojto 93:e188a91d3eaa 398 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
Kojto 93:e188a91d3eaa 399 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
Kojto 93:e188a91d3eaa 400 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
Kojto 93:e188a91d3eaa 401 #endif /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 402
Kojto 93:e188a91d3eaa 403 /**
Kojto 93:e188a91d3eaa 404 * @}
Kojto 93:e188a91d3eaa 405 */
Kojto 93:e188a91d3eaa 406
Kojto 93:e188a91d3eaa 407 /** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
Kojto 93:e188a91d3eaa 408 * @{
Kojto 93:e188a91d3eaa 409 */
Kojto 93:e188a91d3eaa 410
Kojto 93:e188a91d3eaa 411 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 412
Kojto 93:e188a91d3eaa 413 #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
Kojto 93:e188a91d3eaa 414
Kojto 93:e188a91d3eaa 415 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
Kojto 93:e188a91d3eaa 416 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
Kojto 93:e188a91d3eaa 417 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
Kojto 93:e188a91d3eaa 418 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
Kojto 93:e188a91d3eaa 419 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 420 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
Kojto 93:e188a91d3eaa 421 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
Kojto 93:e188a91d3eaa 422 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
Kojto 93:e188a91d3eaa 423 ((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto 93:e188a91d3eaa 424
Kojto 93:e188a91d3eaa 425 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
Kojto 93:e188a91d3eaa 426
Kojto 93:e188a91d3eaa 427 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
Kojto 93:e188a91d3eaa 428
Kojto 93:e188a91d3eaa 429 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
Kojto 93:e188a91d3eaa 430 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
Kojto 93:e188a91d3eaa 431 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
Kojto 93:e188a91d3eaa 432 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
Kojto 93:e188a91d3eaa 433 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 434 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
Kojto 93:e188a91d3eaa 435 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
Kojto 93:e188a91d3eaa 436 ((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto 93:e188a91d3eaa 437
Kojto 93:e188a91d3eaa 438 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
Kojto 93:e188a91d3eaa 439
Kojto 93:e188a91d3eaa 440 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 441 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 442 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 443
Kojto 93:e188a91d3eaa 444 #define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
Kojto 93:e188a91d3eaa 445 #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
Kojto 93:e188a91d3eaa 446
Kojto 93:e188a91d3eaa 447 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
Kojto 93:e188a91d3eaa 448 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
Kojto 93:e188a91d3eaa 449 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
Kojto 93:e188a91d3eaa 450 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
Kojto 93:e188a91d3eaa 451 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 452 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
Kojto 93:e188a91d3eaa 453 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
Kojto 93:e188a91d3eaa 454 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
Kojto 93:e188a91d3eaa 455 ((SOURCE) == RCC_MCOSOURCE_HSI14) || \
Kojto 93:e188a91d3eaa 456 ((SOURCE) == RCC_MCOSOURCE_HSI48))
Kojto 93:e188a91d3eaa 457
Kojto 93:e188a91d3eaa 458 #define RCC_IT_HSI48 ((uint8_t)0x40)
Kojto 93:e188a91d3eaa 459
Kojto 93:e188a91d3eaa 460 /* Flags in the CR2 register */
Kojto 93:e188a91d3eaa 461 #define RCC_CR2_HSI48RDY_BitNumber 16
Kojto 93:e188a91d3eaa 462
Kojto 93:e188a91d3eaa 463 #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
Kojto 93:e188a91d3eaa 464
Kojto 93:e188a91d3eaa 465 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 466 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 467 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 468 /**
Kojto 93:e188a91d3eaa 469 * @}
Kojto 93:e188a91d3eaa 470 */
Kojto 93:e188a91d3eaa 471
Kojto 93:e188a91d3eaa 472 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
Kojto 93:e188a91d3eaa 473
Kojto 93:e188a91d3eaa 474 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto 93:e188a91d3eaa 475 * @{
Kojto 93:e188a91d3eaa 476 */
Kojto 93:e188a91d3eaa 477 #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
Kojto 93:e188a91d3eaa 478 #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
Kojto 93:e188a91d3eaa 479
Kojto 93:e188a91d3eaa 480 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
Kojto 93:e188a91d3eaa 481 ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto 93:e188a91d3eaa 482 /**
Kojto 93:e188a91d3eaa 483 * @}
Kojto 93:e188a91d3eaa 484 */
Kojto 93:e188a91d3eaa 485
Kojto 93:e188a91d3eaa 486 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
Kojto 93:e188a91d3eaa 487
Kojto 93:e188a91d3eaa 488 #if defined(STM32F070x6) || defined(STM32F070xB)
Kojto 93:e188a91d3eaa 489
Kojto 93:e188a91d3eaa 490 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto 93:e188a91d3eaa 491 * @{
Kojto 93:e188a91d3eaa 492 */
Kojto 93:e188a91d3eaa 493 #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
Kojto 93:e188a91d3eaa 494
Kojto 93:e188a91d3eaa 495 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto 93:e188a91d3eaa 496 /**
Kojto 93:e188a91d3eaa 497 * @}
Kojto 93:e188a91d3eaa 498 */
Kojto 93:e188a91d3eaa 499
Kojto 93:e188a91d3eaa 500 #endif /* STM32F070x6 || STM32F070xB */
Kojto 93:e188a91d3eaa 501
Kojto 93:e188a91d3eaa 502 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 503 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 504
Kojto 93:e188a91d3eaa 505 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
Kojto 93:e188a91d3eaa 506 * @{
Kojto 93:e188a91d3eaa 507 */
Kojto 93:e188a91d3eaa 508 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
Kojto 93:e188a91d3eaa 509 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
Kojto 93:e188a91d3eaa 510 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
Kojto 93:e188a91d3eaa 511 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
Kojto 93:e188a91d3eaa 512
Kojto 93:e188a91d3eaa 513 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
Kojto 93:e188a91d3eaa 514 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
Kojto 93:e188a91d3eaa 515 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
Kojto 93:e188a91d3eaa 516 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto 93:e188a91d3eaa 517 /**
Kojto 93:e188a91d3eaa 518 * @}
Kojto 93:e188a91d3eaa 519 */
Kojto 93:e188a91d3eaa 520
Kojto 93:e188a91d3eaa 521 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 522 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 523
Kojto 93:e188a91d3eaa 524 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 525
Kojto 93:e188a91d3eaa 526 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
Kojto 93:e188a91d3eaa 527 * @{
Kojto 93:e188a91d3eaa 528 */
Kojto 93:e188a91d3eaa 529 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
Kojto 93:e188a91d3eaa 530 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
Kojto 93:e188a91d3eaa 531 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
Kojto 93:e188a91d3eaa 532 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
Kojto 93:e188a91d3eaa 533
Kojto 93:e188a91d3eaa 534 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
Kojto 93:e188a91d3eaa 535 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
Kojto 93:e188a91d3eaa 536 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
Kojto 93:e188a91d3eaa 537 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto 93:e188a91d3eaa 538 /**
Kojto 93:e188a91d3eaa 539 * @}
Kojto 93:e188a91d3eaa 540 */
Kojto 93:e188a91d3eaa 541
Kojto 93:e188a91d3eaa 542 #endif /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 543
Kojto 93:e188a91d3eaa 544
Kojto 93:e188a91d3eaa 545 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 546 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 547 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 548 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 549
Kojto 93:e188a91d3eaa 550 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
Kojto 93:e188a91d3eaa 551 * @{
Kojto 93:e188a91d3eaa 552 */
Kojto 93:e188a91d3eaa 553 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
Kojto 93:e188a91d3eaa 554 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
Kojto 93:e188a91d3eaa 555
Kojto 93:e188a91d3eaa 556 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 557 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto 93:e188a91d3eaa 558 /**
Kojto 93:e188a91d3eaa 559 * @}
Kojto 93:e188a91d3eaa 560 */
Kojto 93:e188a91d3eaa 561
Kojto 93:e188a91d3eaa 562 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 563 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 564 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 565 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 566
Kojto 93:e188a91d3eaa 567 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 568 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 569 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 570
Kojto 93:e188a91d3eaa 571 /** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
Kojto 93:e188a91d3eaa 572 * @{
Kojto 93:e188a91d3eaa 573 */
Kojto 93:e188a91d3eaa 574 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto 93:e188a91d3eaa 575 #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
Kojto 93:e188a91d3eaa 576
Kojto 93:e188a91d3eaa 577 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 578 ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
Kojto 93:e188a91d3eaa 579 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 93:e188a91d3eaa 580 /**
Kojto 93:e188a91d3eaa 581 * @}
Kojto 93:e188a91d3eaa 582 */
Kojto 93:e188a91d3eaa 583
Kojto 93:e188a91d3eaa 584 /** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
Kojto 93:e188a91d3eaa 585 * @{
Kojto 93:e188a91d3eaa 586 */
Kojto 93:e188a91d3eaa 587 #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
Kojto 93:e188a91d3eaa 588
Kojto 93:e188a91d3eaa 589 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 590 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 93:e188a91d3eaa 591 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Kojto 93:e188a91d3eaa 592 ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
Kojto 93:e188a91d3eaa 593
Kojto 93:e188a91d3eaa 594 #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
Kojto 93:e188a91d3eaa 595
Kojto 93:e188a91d3eaa 596 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
Kojto 93:e188a91d3eaa 597 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
Kojto 93:e188a91d3eaa 598 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
Kojto 93:e188a91d3eaa 599 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
Kojto 93:e188a91d3eaa 600 /**
Kojto 93:e188a91d3eaa 601 * @}
Kojto 93:e188a91d3eaa 602 */
Kojto 93:e188a91d3eaa 603
Kojto 93:e188a91d3eaa 604 /** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto 93:e188a91d3eaa 605 * @{
Kojto 93:e188a91d3eaa 606 */
Kojto 93:e188a91d3eaa 607 #define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 608 #define RCC_HSI48_ON ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 609
Kojto 93:e188a91d3eaa 610 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
Kojto 93:e188a91d3eaa 611 /**
Kojto 93:e188a91d3eaa 612 * @}
Kojto 93:e188a91d3eaa 613 */
Kojto 93:e188a91d3eaa 614 #else
Kojto 93:e188a91d3eaa 615 /** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
Kojto 93:e188a91d3eaa 616 * @{
Kojto 93:e188a91d3eaa 617 */
Kojto 93:e188a91d3eaa 618
Kojto 93:e188a91d3eaa 619 #if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 620 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto 93:e188a91d3eaa 621 #else
Kojto 93:e188a91d3eaa 622 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto 93:e188a91d3eaa 623 #endif
Kojto 93:e188a91d3eaa 624
Kojto 93:e188a91d3eaa 625 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 626 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 93:e188a91d3eaa 627 /**
Kojto 93:e188a91d3eaa 628 * @}
Kojto 93:e188a91d3eaa 629 */
Kojto 93:e188a91d3eaa 630
Kojto 93:e188a91d3eaa 631 /** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
Kojto 93:e188a91d3eaa 632 * @{
Kojto 93:e188a91d3eaa 633 */
Kojto 93:e188a91d3eaa 634 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 635 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 93:e188a91d3eaa 636 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto 93:e188a91d3eaa 637
Kojto 93:e188a91d3eaa 638 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
Kojto 93:e188a91d3eaa 639 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
Kojto 93:e188a91d3eaa 640 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
Kojto 93:e188a91d3eaa 641 /**
Kojto 93:e188a91d3eaa 642 * @}
Kojto 93:e188a91d3eaa 643 */
Kojto 93:e188a91d3eaa 644
Kojto 93:e188a91d3eaa 645 /** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto 93:e188a91d3eaa 646 * @{
Kojto 93:e188a91d3eaa 647 */
Kojto 93:e188a91d3eaa 648 #define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 649
Kojto 93:e188a91d3eaa 650 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
Kojto 93:e188a91d3eaa 651 /**
Kojto 93:e188a91d3eaa 652 * @}
Kojto 93:e188a91d3eaa 653 */
Kojto 93:e188a91d3eaa 654
Kojto 93:e188a91d3eaa 655 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 656 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 657 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 658
Kojto 93:e188a91d3eaa 659
Kojto 93:e188a91d3eaa 660 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
Kojto 93:e188a91d3eaa 661 * @{
Kojto 93:e188a91d3eaa 662 */
Kojto 93:e188a91d3eaa 663
Kojto 93:e188a91d3eaa 664 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
Kojto 93:e188a91d3eaa 665
Kojto 93:e188a91d3eaa 666 #define RCC_MCO_NODIV ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 667
Kojto 93:e188a91d3eaa 668 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
Kojto 93:e188a91d3eaa 669
Kojto 93:e188a91d3eaa 670 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
Kojto 93:e188a91d3eaa 671
Kojto 93:e188a91d3eaa 672 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 673 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 674 defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 675 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 676
Kojto 93:e188a91d3eaa 677 #define RCC_MCO_DIV1 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 678 #define RCC_MCO_DIV2 ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 679 #define RCC_MCO_DIV4 ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 680 #define RCC_MCO_DIV8 ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 681 #define RCC_MCO_DIV16 ((uint32_t)0x40000000)
Kojto 93:e188a91d3eaa 682 #define RCC_MCO_DIV32 ((uint32_t)0x50000000)
Kojto 93:e188a91d3eaa 683 #define RCC_MCO_DIV64 ((uint32_t)0x60000000)
Kojto 93:e188a91d3eaa 684 #define RCC_MCO_DIV128 ((uint32_t)0x70000000)
Kojto 93:e188a91d3eaa 685
Kojto 93:e188a91d3eaa 686 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
Kojto 93:e188a91d3eaa 687 ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
Kojto 93:e188a91d3eaa 688 ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
Kojto 93:e188a91d3eaa 689 ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
Kojto 93:e188a91d3eaa 690
Kojto 93:e188a91d3eaa 691 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 692 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */
Kojto 93:e188a91d3eaa 693 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 694
Kojto 93:e188a91d3eaa 695 /**
Kojto 93:e188a91d3eaa 696 * @}
Kojto 93:e188a91d3eaa 697 */
Kojto 93:e188a91d3eaa 698
Kojto 93:e188a91d3eaa 699 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 700 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 701 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 702
Kojto 93:e188a91d3eaa 703 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
Kojto 93:e188a91d3eaa 704 * @{
Kojto 93:e188a91d3eaa 705 */
Kojto 93:e188a91d3eaa 706 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
Kojto 93:e188a91d3eaa 707 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
Kojto 93:e188a91d3eaa 708 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
Kojto 93:e188a91d3eaa 709
Kojto 93:e188a91d3eaa 710 #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
Kojto 93:e188a91d3eaa 711 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
Kojto 93:e188a91d3eaa 712 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
Kojto 93:e188a91d3eaa 713 /**
Kojto 93:e188a91d3eaa 714 * @}
Kojto 93:e188a91d3eaa 715 */
Kojto 93:e188a91d3eaa 716
Kojto 93:e188a91d3eaa 717 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
Kojto 93:e188a91d3eaa 718 * @{
Kojto 93:e188a91d3eaa 719 */
Kojto 93:e188a91d3eaa 720 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
Kojto 93:e188a91d3eaa 721 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
Kojto 93:e188a91d3eaa 722 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
Kojto 93:e188a91d3eaa 723 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
Kojto 93:e188a91d3eaa 724 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
Kojto 93:e188a91d3eaa 725 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
Kojto 93:e188a91d3eaa 726 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
Kojto 93:e188a91d3eaa 727 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
Kojto 93:e188a91d3eaa 728
Kojto 93:e188a91d3eaa 729 #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
Kojto 93:e188a91d3eaa 730 ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
Kojto 93:e188a91d3eaa 731 ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
Kojto 93:e188a91d3eaa 732 ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
Kojto 93:e188a91d3eaa 733 /**
Kojto 93:e188a91d3eaa 734 * @}
Kojto 93:e188a91d3eaa 735 */
Kojto 93:e188a91d3eaa 736
Kojto 93:e188a91d3eaa 737 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
Kojto 93:e188a91d3eaa 738 * @{
Kojto 93:e188a91d3eaa 739 */
Kojto 93:e188a91d3eaa 740 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
Kojto 93:e188a91d3eaa 741 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
Kojto 93:e188a91d3eaa 742
Kojto 93:e188a91d3eaa 743 #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
Kojto 93:e188a91d3eaa 744 ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
Kojto 93:e188a91d3eaa 745 /**
Kojto 93:e188a91d3eaa 746 * @}
Kojto 93:e188a91d3eaa 747 */
Kojto 93:e188a91d3eaa 748
Kojto 93:e188a91d3eaa 749 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
Kojto 93:e188a91d3eaa 750 * @{
Kojto 93:e188a91d3eaa 751 */
Kojto 93:e188a91d3eaa 752 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
Kojto 93:e188a91d3eaa 753 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
Kojto 93:e188a91d3eaa 754
Kojto 93:e188a91d3eaa 755 #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
Kojto 93:e188a91d3eaa 756 /**
Kojto 93:e188a91d3eaa 757 * @}
Kojto 93:e188a91d3eaa 758 */
Kojto 93:e188a91d3eaa 759
Kojto 93:e188a91d3eaa 760 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
Kojto 93:e188a91d3eaa 761 * @{
Kojto 93:e188a91d3eaa 762 */
Kojto 93:e188a91d3eaa 763 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
Kojto 93:e188a91d3eaa 764
Kojto 93:e188a91d3eaa 765 #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
Kojto 93:e188a91d3eaa 766 /**
Kojto 93:e188a91d3eaa 767 * @}
Kojto 93:e188a91d3eaa 768 */
Kojto 93:e188a91d3eaa 769
Kojto 93:e188a91d3eaa 770 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
Kojto 93:e188a91d3eaa 771 * @{
Kojto 93:e188a91d3eaa 772 */
Kojto 93:e188a91d3eaa 773 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
Kojto 93:e188a91d3eaa 774 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
Kojto 93:e188a91d3eaa 775 corresponds to a higher output frequency */
Kojto 93:e188a91d3eaa 776
Kojto 93:e188a91d3eaa 777 #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
Kojto 93:e188a91d3eaa 778 /**
Kojto 93:e188a91d3eaa 779 * @}
Kojto 93:e188a91d3eaa 780 */
Kojto 93:e188a91d3eaa 781
Kojto 93:e188a91d3eaa 782 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
Kojto 93:e188a91d3eaa 783 * @{
Kojto 93:e188a91d3eaa 784 */
Kojto 93:e188a91d3eaa 785 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
Kojto 93:e188a91d3eaa 786 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
Kojto 93:e188a91d3eaa 787
Kojto 93:e188a91d3eaa 788 #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
Kojto 93:e188a91d3eaa 789 ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
Kojto 93:e188a91d3eaa 790 /**
Kojto 93:e188a91d3eaa 791 * @}
Kojto 93:e188a91d3eaa 792 */
Kojto 93:e188a91d3eaa 793
Kojto 93:e188a91d3eaa 794 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
Kojto 93:e188a91d3eaa 795 * @{
Kojto 93:e188a91d3eaa 796 */
Kojto 93:e188a91d3eaa 797 #define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
Kojto 93:e188a91d3eaa 798 #define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
Kojto 93:e188a91d3eaa 799 #define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */
Kojto 93:e188a91d3eaa 800 #define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
Kojto 93:e188a91d3eaa 801 #define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
Kojto 93:e188a91d3eaa 802 #define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
Kojto 93:e188a91d3eaa 803 #define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
Kojto 93:e188a91d3eaa 804
Kojto 93:e188a91d3eaa 805 /**
Kojto 93:e188a91d3eaa 806 * @}
Kojto 93:e188a91d3eaa 807 */
Kojto 93:e188a91d3eaa 808
Kojto 93:e188a91d3eaa 809 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
Kojto 93:e188a91d3eaa 810 * @{
Kojto 93:e188a91d3eaa 811 */
Kojto 93:e188a91d3eaa 812 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
Kojto 93:e188a91d3eaa 813 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
Kojto 93:e188a91d3eaa 814 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
Kojto 93:e188a91d3eaa 815 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
Kojto 93:e188a91d3eaa 816 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
Kojto 93:e188a91d3eaa 817 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
Kojto 93:e188a91d3eaa 818 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
Kojto 93:e188a91d3eaa 819
Kojto 93:e188a91d3eaa 820 /**
Kojto 93:e188a91d3eaa 821 * @}
Kojto 93:e188a91d3eaa 822 */
Kojto 93:e188a91d3eaa 823
Kojto 93:e188a91d3eaa 824 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 825 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 826 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 827
Kojto 93:e188a91d3eaa 828 /**
Kojto 93:e188a91d3eaa 829 * @}
Kojto 93:e188a91d3eaa 830 */
Kojto 93:e188a91d3eaa 831
Kojto 93:e188a91d3eaa 832 /* Exported macros ------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 833 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 93:e188a91d3eaa 834 * @{
Kojto 93:e188a91d3eaa 835 */
Kojto 93:e188a91d3eaa 836
Kojto 93:e188a91d3eaa 837 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
Kojto 93:e188a91d3eaa 838 * @brief Enables or disables the AHB1 peripheral clock.
Kojto 93:e188a91d3eaa 839 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 840 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 841 * using it.
Kojto 93:e188a91d3eaa 842 * @{
Kojto 93:e188a91d3eaa 843 */
Kojto 93:e188a91d3eaa 844 #if defined(STM32F030x6) || defined(STM32F030x8) || \
Kojto 93:e188a91d3eaa 845 defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 846 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 847 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 848
Kojto 93:e188a91d3eaa 849 #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
Kojto 93:e188a91d3eaa 850
Kojto 93:e188a91d3eaa 851 #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
Kojto 93:e188a91d3eaa 852
Kojto 93:e188a91d3eaa 853 #endif /* STM32F030x6 || STM32F030x8 || */
Kojto 93:e188a91d3eaa 854 /* STM32F051x8 || STM32F058xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 855 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 856 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 857
Kojto 93:e188a91d3eaa 858 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 859 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 860
Kojto 93:e188a91d3eaa 861 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
Kojto 93:e188a91d3eaa 862
Kojto 93:e188a91d3eaa 863 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto 93:e188a91d3eaa 864
Kojto 93:e188a91d3eaa 865 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 866 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 867
Kojto 93:e188a91d3eaa 868 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 869 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 870 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 871 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 872
Kojto 93:e188a91d3eaa 873 #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
Kojto 93:e188a91d3eaa 874
Kojto 93:e188a91d3eaa 875 #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
Kojto 93:e188a91d3eaa 876
Kojto 93:e188a91d3eaa 877 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 878 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 879 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 880 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 881
Kojto 93:e188a91d3eaa 882 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 883
Kojto 93:e188a91d3eaa 884 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
Kojto 93:e188a91d3eaa 885
Kojto 93:e188a91d3eaa 886 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto 93:e188a91d3eaa 887
Kojto 93:e188a91d3eaa 888 #endif /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 889
Kojto 93:e188a91d3eaa 890 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 93:e188a91d3eaa 891 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 892 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 893 * using it.
Kojto 93:e188a91d3eaa 894 */
Kojto 93:e188a91d3eaa 895 #if defined(STM32F030x8) || \
Kojto 93:e188a91d3eaa 896 defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 897 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 898 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 899 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 900
Kojto 93:e188a91d3eaa 901 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
Kojto 93:e188a91d3eaa 902 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
Kojto 93:e188a91d3eaa 903
Kojto 93:e188a91d3eaa 904 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 93:e188a91d3eaa 905 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 93:e188a91d3eaa 906
Kojto 93:e188a91d3eaa 907 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 908 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 909 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 910 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 911
Kojto 93:e188a91d3eaa 912 #if defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 93:e188a91d3eaa 913 defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 914 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 915 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 916 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 917
Kojto 93:e188a91d3eaa 918 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
Kojto 93:e188a91d3eaa 919
Kojto 93:e188a91d3eaa 920 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto 93:e188a91d3eaa 921
Kojto 93:e188a91d3eaa 922 #endif /* STM32F031x6 || STM32F038xx || */
Kojto 93:e188a91d3eaa 923 /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 924 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 925 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 926 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 927
Kojto 93:e188a91d3eaa 928 #if defined(STM32F030x8) || \
Kojto 93:e188a91d3eaa 929 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 930 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 931 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 932
Kojto 93:e188a91d3eaa 933 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
Kojto 93:e188a91d3eaa 934 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
Kojto 93:e188a91d3eaa 935
Kojto 93:e188a91d3eaa 936 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 93:e188a91d3eaa 937 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 93:e188a91d3eaa 938
Kojto 93:e188a91d3eaa 939 #endif /* STM32F030x8 || */
Kojto 93:e188a91d3eaa 940 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 941 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 942 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 943
Kojto 93:e188a91d3eaa 944 #if defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 945 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 946 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 947
Kojto 93:e188a91d3eaa 948 #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
Kojto 93:e188a91d3eaa 949
Kojto 93:e188a91d3eaa 950 #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 93:e188a91d3eaa 951
Kojto 93:e188a91d3eaa 952 #endif /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 953 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 954 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 955
Kojto 93:e188a91d3eaa 956 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 957 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 958 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 959 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 960
Kojto 93:e188a91d3eaa 961 #define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
Kojto 93:e188a91d3eaa 962
Kojto 93:e188a91d3eaa 963 #define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto 93:e188a91d3eaa 964
Kojto 93:e188a91d3eaa 965 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 966 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 967 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 968 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 969
Kojto 93:e188a91d3eaa 970 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 971 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 972
Kojto 93:e188a91d3eaa 973 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
Kojto 93:e188a91d3eaa 974 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
Kojto 93:e188a91d3eaa 975 #define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
Kojto 93:e188a91d3eaa 976
Kojto 93:e188a91d3eaa 977 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 93:e188a91d3eaa 978 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 93:e188a91d3eaa 979 #define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
Kojto 93:e188a91d3eaa 980
Kojto 93:e188a91d3eaa 981 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 982 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 983
Kojto 93:e188a91d3eaa 984 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 985 defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
Kojto 93:e188a91d3eaa 986
Kojto 93:e188a91d3eaa 987 #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
Kojto 93:e188a91d3eaa 988
Kojto 93:e188a91d3eaa 989 #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto 93:e188a91d3eaa 990
Kojto 93:e188a91d3eaa 991 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 93:e188a91d3eaa 992 /* STM32F072xB || STM32F078xx || STM32F070xB */
Kojto 93:e188a91d3eaa 993
Kojto 93:e188a91d3eaa 994 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
Kojto 93:e188a91d3eaa 995 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 996
Kojto 93:e188a91d3eaa 997 #define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
Kojto 93:e188a91d3eaa 998 #define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
Kojto 93:e188a91d3eaa 999
Kojto 93:e188a91d3eaa 1000 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
Kojto 93:e188a91d3eaa 1001 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1002
Kojto 93:e188a91d3eaa 1003 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1004 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1005 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1006
Kojto 93:e188a91d3eaa 1007 #define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
Kojto 93:e188a91d3eaa 1008
Kojto 93:e188a91d3eaa 1009 #define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
Kojto 93:e188a91d3eaa 1010
Kojto 93:e188a91d3eaa 1011 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1012 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1013 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1014
Kojto 93:e188a91d3eaa 1015 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1016
Kojto 93:e188a91d3eaa 1017 #define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
Kojto 93:e188a91d3eaa 1018
Kojto 93:e188a91d3eaa 1019 #define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
Kojto 93:e188a91d3eaa 1020
Kojto 93:e188a91d3eaa 1021 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1022
Kojto 93:e188a91d3eaa 1023 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 93:e188a91d3eaa 1024 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 1025 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 1026 * using it.
Kojto 93:e188a91d3eaa 1027 */
Kojto 93:e188a91d3eaa 1028 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 1029 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1030 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1031 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1032
Kojto 93:e188a91d3eaa 1033 #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
Kojto 93:e188a91d3eaa 1034
Kojto 93:e188a91d3eaa 1035 #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
Kojto 93:e188a91d3eaa 1036
Kojto 93:e188a91d3eaa 1037 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 93:e188a91d3eaa 1038 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1039 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1040 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1041
Kojto 93:e188a91d3eaa 1042 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1043
Kojto 93:e188a91d3eaa 1044 #define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
Kojto 93:e188a91d3eaa 1045
Kojto 93:e188a91d3eaa 1046 #define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 93:e188a91d3eaa 1047
Kojto 93:e188a91d3eaa 1048 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1049
Kojto 93:e188a91d3eaa 1050 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1051
Kojto 93:e188a91d3eaa 1052 #define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN))
Kojto 93:e188a91d3eaa 1053 #define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN))
Kojto 93:e188a91d3eaa 1054
Kojto 93:e188a91d3eaa 1055 #define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
Kojto 93:e188a91d3eaa 1056 #define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
Kojto 93:e188a91d3eaa 1057
Kojto 93:e188a91d3eaa 1058 #endif /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1059
Kojto 93:e188a91d3eaa 1060 /**
Kojto 93:e188a91d3eaa 1061 * @}
Kojto 93:e188a91d3eaa 1062 */
Kojto 93:e188a91d3eaa 1063
Kojto 93:e188a91d3eaa 1064
Kojto 93:e188a91d3eaa 1065 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
Kojto 93:e188a91d3eaa 1066 * @brief Forces or releases peripheral reset.
Kojto 93:e188a91d3eaa 1067 * @{
Kojto 93:e188a91d3eaa 1068 */
Kojto 93:e188a91d3eaa 1069
Kojto 93:e188a91d3eaa 1070 /** @brief Force or release AHB peripheral reset.
Kojto 93:e188a91d3eaa 1071 */
Kojto 93:e188a91d3eaa 1072 #if defined(STM32F030x6) || defined(STM32F030x8) || \
Kojto 93:e188a91d3eaa 1073 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1074 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1075 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1076
Kojto 93:e188a91d3eaa 1077 #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
Kojto 93:e188a91d3eaa 1078
Kojto 93:e188a91d3eaa 1079 #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
Kojto 93:e188a91d3eaa 1080
Kojto 93:e188a91d3eaa 1081 #endif /* STM32F030x6 || STM32F030x8 || */
Kojto 93:e188a91d3eaa 1082 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1083 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1084 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1085
Kojto 93:e188a91d3eaa 1086 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1087 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1088
Kojto 93:e188a91d3eaa 1089 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
Kojto 93:e188a91d3eaa 1090
Kojto 93:e188a91d3eaa 1091 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto 93:e188a91d3eaa 1092
Kojto 93:e188a91d3eaa 1093 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1094 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1095
Kojto 93:e188a91d3eaa 1096 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1097 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1098 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1099 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1100
Kojto 93:e188a91d3eaa 1101 #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
Kojto 93:e188a91d3eaa 1102
Kojto 93:e188a91d3eaa 1103 #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
Kojto 93:e188a91d3eaa 1104
Kojto 93:e188a91d3eaa 1105 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1106 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1107 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1108 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1109
Kojto 93:e188a91d3eaa 1110 /** @brief Force or release APB1 peripheral reset.
Kojto 93:e188a91d3eaa 1111 */
Kojto 93:e188a91d3eaa 1112 #if defined(STM32F030x8) || \
Kojto 93:e188a91d3eaa 1113 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 1114 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1115 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1116 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1117
Kojto 93:e188a91d3eaa 1118 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 93:e188a91d3eaa 1119 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 93:e188a91d3eaa 1120
Kojto 93:e188a91d3eaa 1121 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 93:e188a91d3eaa 1122 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 93:e188a91d3eaa 1123
Kojto 93:e188a91d3eaa 1124 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 93:e188a91d3eaa 1125 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1126 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1127 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1128
Kojto 93:e188a91d3eaa 1129 #if defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 93:e188a91d3eaa 1130 defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1131 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1132 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1133 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1134
Kojto 93:e188a91d3eaa 1135 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 93:e188a91d3eaa 1136
Kojto 93:e188a91d3eaa 1137 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto 93:e188a91d3eaa 1138
Kojto 93:e188a91d3eaa 1139 #endif /* STM32F031x6 || STM32F038xx || */
Kojto 93:e188a91d3eaa 1140 /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1141 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1142 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1143 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1144
Kojto 93:e188a91d3eaa 1145 #if defined(STM32F030x8) || \
Kojto 93:e188a91d3eaa 1146 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1147 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) ||\
Kojto 93:e188a91d3eaa 1148 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1149
Kojto 93:e188a91d3eaa 1150 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 93:e188a91d3eaa 1151 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 93:e188a91d3eaa 1152
Kojto 93:e188a91d3eaa 1153 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 93:e188a91d3eaa 1154 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 93:e188a91d3eaa 1155
Kojto 93:e188a91d3eaa 1156 #endif /* STM32F030x8 || */
Kojto 93:e188a91d3eaa 1157 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1158 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1159 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1160
Kojto 93:e188a91d3eaa 1161 #if defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1162 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1163 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1164
Kojto 93:e188a91d3eaa 1165 #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 93:e188a91d3eaa 1166
Kojto 93:e188a91d3eaa 1167 #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 93:e188a91d3eaa 1168
Kojto 93:e188a91d3eaa 1169 #endif /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1170 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1171 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1172
Kojto 93:e188a91d3eaa 1173 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1174 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1175 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1176 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1177
Kojto 93:e188a91d3eaa 1178 #define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
Kojto 93:e188a91d3eaa 1179
Kojto 93:e188a91d3eaa 1180 #define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto 93:e188a91d3eaa 1181
Kojto 93:e188a91d3eaa 1182 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1183 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1184 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1185 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1186
Kojto 93:e188a91d3eaa 1187 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1188 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1189
Kojto 93:e188a91d3eaa 1190 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 93:e188a91d3eaa 1191 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 93:e188a91d3eaa 1192 #define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
Kojto 93:e188a91d3eaa 1193
Kojto 93:e188a91d3eaa 1194 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 93:e188a91d3eaa 1195 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 93:e188a91d3eaa 1196 #define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
Kojto 93:e188a91d3eaa 1197
Kojto 93:e188a91d3eaa 1198 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1199 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1200
Kojto 93:e188a91d3eaa 1201 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 1202 defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
Kojto 93:e188a91d3eaa 1203
Kojto 93:e188a91d3eaa 1204 #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
Kojto 93:e188a91d3eaa 1205
Kojto 93:e188a91d3eaa 1206 #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto 93:e188a91d3eaa 1207
Kojto 93:e188a91d3eaa 1208 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 93:e188a91d3eaa 1209 /* STM32F072xB || STM32F078xx || STM32F070xB */
Kojto 93:e188a91d3eaa 1210
Kojto 93:e188a91d3eaa 1211 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
Kojto 93:e188a91d3eaa 1212 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1213
Kojto 93:e188a91d3eaa 1214 #define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
Kojto 93:e188a91d3eaa 1215
Kojto 93:e188a91d3eaa 1216 #define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
Kojto 93:e188a91d3eaa 1217
Kojto 93:e188a91d3eaa 1218 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
Kojto 93:e188a91d3eaa 1219 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1220
Kojto 93:e188a91d3eaa 1221 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1222 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1223 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1224
Kojto 93:e188a91d3eaa 1225 #define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
Kojto 93:e188a91d3eaa 1226
Kojto 93:e188a91d3eaa 1227 #define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
Kojto 93:e188a91d3eaa 1228
Kojto 93:e188a91d3eaa 1229 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1230 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1231 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1232
Kojto 93:e188a91d3eaa 1233 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1234
Kojto 93:e188a91d3eaa 1235 #define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
Kojto 93:e188a91d3eaa 1236
Kojto 93:e188a91d3eaa 1237 #define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
Kojto 93:e188a91d3eaa 1238
Kojto 93:e188a91d3eaa 1239 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1240
Kojto 93:e188a91d3eaa 1241
Kojto 93:e188a91d3eaa 1242 /** @brief Force or release APB2 peripheral reset.
Kojto 93:e188a91d3eaa 1243 */
Kojto 93:e188a91d3eaa 1244 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 1245 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1246 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1247 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1248
Kojto 93:e188a91d3eaa 1249 #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
Kojto 93:e188a91d3eaa 1250
Kojto 93:e188a91d3eaa 1251 #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
Kojto 93:e188a91d3eaa 1252
Kojto 93:e188a91d3eaa 1253 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 93:e188a91d3eaa 1254 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1255 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1256 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1257
Kojto 93:e188a91d3eaa 1258 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1259
Kojto 93:e188a91d3eaa 1260 #define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 93:e188a91d3eaa 1261
Kojto 93:e188a91d3eaa 1262 #define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 93:e188a91d3eaa 1263
Kojto 93:e188a91d3eaa 1264 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1265
Kojto 93:e188a91d3eaa 1266 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1267
Kojto 93:e188a91d3eaa 1268 #define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
Kojto 93:e188a91d3eaa 1269 #define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
Kojto 93:e188a91d3eaa 1270
Kojto 93:e188a91d3eaa 1271 #define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
Kojto 93:e188a91d3eaa 1272 #define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
Kojto 93:e188a91d3eaa 1273
Kojto 93:e188a91d3eaa 1274 #endif /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1275
Kojto 93:e188a91d3eaa 1276 /**
Kojto 93:e188a91d3eaa 1277 * @}
Kojto 93:e188a91d3eaa 1278 */
Kojto 93:e188a91d3eaa 1279
Kojto 93:e188a91d3eaa 1280 /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
Kojto 93:e188a91d3eaa 1281 * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
Kojto 93:e188a91d3eaa 1282 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 1283 * @note HSI48 can not be stopped if it is used as system clock source. In this case,
Kojto 93:e188a91d3eaa 1284 * you have to select another source of the system clock then stop the HSI14.
Kojto 93:e188a91d3eaa 1285 * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
Kojto 93:e188a91d3eaa 1286 * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
Kojto 93:e188a91d3eaa 1287 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
Kojto 93:e188a91d3eaa 1288 * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
Kojto 93:e188a91d3eaa 1289 * clock cycles.
Kojto 93:e188a91d3eaa 1290 * @{
Kojto 93:e188a91d3eaa 1291 */
Kojto 93:e188a91d3eaa 1292 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1293 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1294 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1295
Kojto 93:e188a91d3eaa 1296 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
Kojto 93:e188a91d3eaa 1297 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
Kojto 93:e188a91d3eaa 1298
Kojto 93:e188a91d3eaa 1299 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
Kojto 93:e188a91d3eaa 1300 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 1301 * @arg RCC_HSI48_ON: HSI48 enabled
Kojto 93:e188a91d3eaa 1302 * @arg RCC_HSI48_OFF: HSI48 disabled
Kojto 93:e188a91d3eaa 1303 */
Kojto 93:e188a91d3eaa 1304 #define __HAL_RCC_GET_HSI48_STATE() \
Kojto 93:e188a91d3eaa 1305 (((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
Kojto 93:e188a91d3eaa 1306
Kojto 93:e188a91d3eaa 1307 #else
Kojto 93:e188a91d3eaa 1308
Kojto 93:e188a91d3eaa 1309 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
Kojto 93:e188a91d3eaa 1310 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 1311 * @arg RCC_HSI_OFF: HSI48 disabled
Kojto 93:e188a91d3eaa 1312 */
Kojto 93:e188a91d3eaa 1313 #define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
Kojto 93:e188a91d3eaa 1314
Kojto 93:e188a91d3eaa 1315 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1316 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1317 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1318
Kojto 93:e188a91d3eaa 1319 /**
Kojto 93:e188a91d3eaa 1320 * @}
Kojto 93:e188a91d3eaa 1321 */
Kojto 93:e188a91d3eaa 1322
Kojto 93:e188a91d3eaa 1323 /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
Kojto 93:e188a91d3eaa 1324 * @{
Kojto 93:e188a91d3eaa 1325 */
Kojto 93:e188a91d3eaa 1326 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1327 defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1328 defined(STM32F070x6) || defined(STM32F070xB)
Kojto 93:e188a91d3eaa 1329
Kojto 93:e188a91d3eaa 1330 /** @brief Macro to configure the USB clock (USBCLK).
Kojto 93:e188a91d3eaa 1331 * @param __USBCLKSource__: specifies the USB clock source.
Kojto 93:e188a91d3eaa 1332 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1333 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
Kojto 93:e188a91d3eaa 1334 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto 93:e188a91d3eaa 1335 */
Kojto 93:e188a91d3eaa 1336 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
Kojto 93:e188a91d3eaa 1337 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
Kojto 93:e188a91d3eaa 1338
Kojto 93:e188a91d3eaa 1339 /** @brief Macro to get the USB clock source.
Kojto 93:e188a91d3eaa 1340 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 1341 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
Kojto 93:e188a91d3eaa 1342 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto 93:e188a91d3eaa 1343 */
Kojto 93:e188a91d3eaa 1344 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
Kojto 93:e188a91d3eaa 1345
Kojto 93:e188a91d3eaa 1346 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1347 /* STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1348 /* STM32F070x6 || STM32F070xB */
Kojto 93:e188a91d3eaa 1349
Kojto 93:e188a91d3eaa 1350 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1351 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1352 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1353 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1354
Kojto 93:e188a91d3eaa 1355 /** @brief Macro to configure the CEC clock.
Kojto 93:e188a91d3eaa 1356 * @param __CECCLKSource__: specifies the CEC clock source.
Kojto 93:e188a91d3eaa 1357 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1358 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 93:e188a91d3eaa 1359 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 93:e188a91d3eaa 1360 */
Kojto 93:e188a91d3eaa 1361 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
Kojto 93:e188a91d3eaa 1362 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
Kojto 93:e188a91d3eaa 1363
Kojto 93:e188a91d3eaa 1364 /** @brief Macro to get the HDMI CEC clock source.
Kojto 93:e188a91d3eaa 1365 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 1366 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 93:e188a91d3eaa 1367 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 93:e188a91d3eaa 1368 */
Kojto 93:e188a91d3eaa 1369 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
Kojto 93:e188a91d3eaa 1370
Kojto 93:e188a91d3eaa 1371 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1372 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1373 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1374 /* STM32F091xC || defined(STM32F098xx) */
Kojto 93:e188a91d3eaa 1375
Kojto 93:e188a91d3eaa 1376 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 93:e188a91d3eaa 1377 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 1378 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1379 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1380
Kojto 93:e188a91d3eaa 1381 /** @brief Macro to configure the MCO clock.
Kojto 93:e188a91d3eaa 1382 * @param __MCOCLKSource__: specifies the MCO clock source.
Kojto 93:e188a91d3eaa 1383 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1384 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto 93:e188a91d3eaa 1385 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto 93:e188a91d3eaa 1386 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto 93:e188a91d3eaa 1387 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto 93:e188a91d3eaa 1388 * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
Kojto 93:e188a91d3eaa 1389 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto 93:e188a91d3eaa 1390 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto 93:e188a91d3eaa 1391 * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
Kojto 93:e188a91d3eaa 1392 * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
Kojto 93:e188a91d3eaa 1393 * @param __MCODiv__: specifies the MCO clock prescaler.
Kojto 93:e188a91d3eaa 1394 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1395 * @arg RCC_MCO_DIV1: MCO clock source is divided by 1
Kojto 93:e188a91d3eaa 1396 * @arg RCC_MCO_DIV2: MCO clock source is divided by 2
Kojto 93:e188a91d3eaa 1397 * @arg RCC_MCO_DIV4: MCO clock source is divided by 4
Kojto 93:e188a91d3eaa 1398 * @arg RCC_MCO_DIV8: MCO clock source is divided by 8
Kojto 93:e188a91d3eaa 1399 * @arg RCC_MCO_DIV16: MCO clock source is divided by 16
Kojto 93:e188a91d3eaa 1400 * @arg RCC_MCO_DIV32: MCO clock source is divided by 32
Kojto 93:e188a91d3eaa 1401 * @arg RCC_MCO_DIV64: MCO clock source is divided by 64
Kojto 93:e188a91d3eaa 1402 * @arg RCC_MCO_DIV128: MCO clock source is divided by 128
Kojto 93:e188a91d3eaa 1403 */
Kojto 93:e188a91d3eaa 1404 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto 93:e188a91d3eaa 1405 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__)))
Kojto 93:e188a91d3eaa 1406 #else
Kojto 93:e188a91d3eaa 1407
Kojto 93:e188a91d3eaa 1408 /** @brief Macro to configure the MCO clock.
Kojto 93:e188a91d3eaa 1409 * @param __MCOCLKSource__: specifies the MCO clock source.
Kojto 93:e188a91d3eaa 1410 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1411 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto 93:e188a91d3eaa 1412 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto 93:e188a91d3eaa 1413 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto 93:e188a91d3eaa 1414 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto 93:e188a91d3eaa 1415 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto 93:e188a91d3eaa 1416 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto 93:e188a91d3eaa 1417 * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
Kojto 93:e188a91d3eaa 1418 * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
Kojto 93:e188a91d3eaa 1419 * @param __MCODiv__: specifies the MCO clock prescaler.
Kojto 93:e188a91d3eaa 1420 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1421 * @arg RCC_MCO_NODIV: No division applied on MCO clock source
Kojto 93:e188a91d3eaa 1422 */
Kojto 93:e188a91d3eaa 1423 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto 93:e188a91d3eaa 1424 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
Kojto 93:e188a91d3eaa 1425
Kojto 93:e188a91d3eaa 1426 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || */
Kojto 93:e188a91d3eaa 1427 /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1428 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1429 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1430
Kojto 93:e188a91d3eaa 1431 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1432 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1433 /** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto 93:e188a91d3eaa 1434 * @param __USART2CLKSource__: specifies the USART2 clock source.
Kojto 93:e188a91d3eaa 1435 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1436 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 93:e188a91d3eaa 1437 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 93:e188a91d3eaa 1438 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 93:e188a91d3eaa 1439 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 93:e188a91d3eaa 1440 */
Kojto 93:e188a91d3eaa 1441 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
Kojto 93:e188a91d3eaa 1442 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
Kojto 93:e188a91d3eaa 1443
Kojto 93:e188a91d3eaa 1444 /** @brief Macro to get the USART2 clock source.
Kojto 93:e188a91d3eaa 1445 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 1446 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 93:e188a91d3eaa 1447 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 93:e188a91d3eaa 1448 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 93:e188a91d3eaa 1449 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 93:e188a91d3eaa 1450 */
Kojto 93:e188a91d3eaa 1451 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Kojto 93:e188a91d3eaa 1452 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/
Kojto 93:e188a91d3eaa 1453
Kojto 93:e188a91d3eaa 1454 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1455 /** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto 93:e188a91d3eaa 1456 * @param __USART3CLKSource__: specifies the USART3 clock source.
Kojto 93:e188a91d3eaa 1457 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1458 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 93:e188a91d3eaa 1459 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 93:e188a91d3eaa 1460 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 93:e188a91d3eaa 1461 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 93:e188a91d3eaa 1462 */
Kojto 93:e188a91d3eaa 1463 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
Kojto 93:e188a91d3eaa 1464 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
Kojto 93:e188a91d3eaa 1465
Kojto 93:e188a91d3eaa 1466 /** @brief Macro to get the USART3 clock source.
Kojto 93:e188a91d3eaa 1467 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 1468 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 93:e188a91d3eaa 1469 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 93:e188a91d3eaa 1470 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 93:e188a91d3eaa 1471 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 93:e188a91d3eaa 1472 */
Kojto 93:e188a91d3eaa 1473 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
Kojto 93:e188a91d3eaa 1474
Kojto 93:e188a91d3eaa 1475 #endif /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1476 /**
Kojto 93:e188a91d3eaa 1477 * @}
Kojto 93:e188a91d3eaa 1478 */
Kojto 93:e188a91d3eaa 1479
Kojto 93:e188a91d3eaa 1480 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1481 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1482 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1483
Kojto 93:e188a91d3eaa 1484 /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
Kojto 93:e188a91d3eaa 1485 * @{
Kojto 93:e188a91d3eaa 1486 */
Kojto 93:e188a91d3eaa 1487 /* Interrupt & Flag management */
Kojto 93:e188a91d3eaa 1488
Kojto 93:e188a91d3eaa 1489 /**
Kojto 93:e188a91d3eaa 1490 * @brief Enables the specified CRS interrupts.
Kojto 93:e188a91d3eaa 1491 * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
Kojto 93:e188a91d3eaa 1492 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1493 * @arg RCC_CRS_IT_SYNCOK
Kojto 93:e188a91d3eaa 1494 * @arg RCC_CRS_IT_SYNCWARN
Kojto 93:e188a91d3eaa 1495 * @arg RCC_CRS_IT_ERR
Kojto 93:e188a91d3eaa 1496 * @arg RCC_CRS_IT_ESYNC
Kojto 93:e188a91d3eaa 1497 * @retval None
Kojto 93:e188a91d3eaa 1498 */
Kojto 93:e188a91d3eaa 1499 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__))
Kojto 93:e188a91d3eaa 1500
Kojto 93:e188a91d3eaa 1501 /**
Kojto 93:e188a91d3eaa 1502 * @brief Disables the specified CRS interrupts.
Kojto 93:e188a91d3eaa 1503 * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
Kojto 93:e188a91d3eaa 1504 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1505 * @arg RCC_CRS_IT_SYNCOK
Kojto 93:e188a91d3eaa 1506 * @arg RCC_CRS_IT_SYNCWARN
Kojto 93:e188a91d3eaa 1507 * @arg RCC_CRS_IT_ERR
Kojto 93:e188a91d3eaa 1508 * @arg RCC_CRS_IT_ESYNC
Kojto 93:e188a91d3eaa 1509 * @retval None
Kojto 93:e188a91d3eaa 1510 */
Kojto 93:e188a91d3eaa 1511 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
Kojto 93:e188a91d3eaa 1512
Kojto 93:e188a91d3eaa 1513 /** @brief Check the CRS's interrupt has occurred or not.
Kojto 93:e188a91d3eaa 1514 * @param __INTERRUPT__: specifies the CRS interrupt source to check.
Kojto 93:e188a91d3eaa 1515 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1516 * @arg RCC_CRS_IT_SYNCOK
Kojto 93:e188a91d3eaa 1517 * @arg RCC_CRS_IT_SYNCWARN
Kojto 93:e188a91d3eaa 1518 * @arg RCC_CRS_IT_ERR
Kojto 93:e188a91d3eaa 1519 * @arg RCC_CRS_IT_ESYNC
Kojto 93:e188a91d3eaa 1520 * @retval The new state of __INTERRUPT__ (SET or RESET).
Kojto 93:e188a91d3eaa 1521 */
Kojto 93:e188a91d3eaa 1522 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
Kojto 93:e188a91d3eaa 1523
Kojto 93:e188a91d3eaa 1524 /** @brief Clear the CRS's interrupt pending bits
Kojto 93:e188a91d3eaa 1525 * bits to clear the selected interrupt pending bits.
Kojto 93:e188a91d3eaa 1526 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 93:e188a91d3eaa 1527 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1528 * @arg RCC_CRS_IT_SYNCOK
Kojto 93:e188a91d3eaa 1529 * @arg RCC_CRS_IT_SYNCWARN
Kojto 93:e188a91d3eaa 1530 * @arg RCC_CRS_IT_ERR
Kojto 93:e188a91d3eaa 1531 * @arg RCC_CRS_IT_ESYNC
Kojto 93:e188a91d3eaa 1532 * @arg RCC_CRS_IT_TRIMOVF
Kojto 93:e188a91d3eaa 1533 * @arg RCC_CRS_IT_SYNCERR
Kojto 93:e188a91d3eaa 1534 * @arg RCC_CRS_IT_SYNCMISS
Kojto 93:e188a91d3eaa 1535 */
Kojto 93:e188a91d3eaa 1536 /* CRS IT Error Mask */
Kojto 93:e188a91d3eaa 1537 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
Kojto 93:e188a91d3eaa 1538
Kojto 93:e188a91d3eaa 1539 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
Kojto 93:e188a91d3eaa 1540 (CRS->ICR |= (__INTERRUPT__)))
Kojto 93:e188a91d3eaa 1541
Kojto 93:e188a91d3eaa 1542 /**
Kojto 93:e188a91d3eaa 1543 * @brief Checks whether the specified CRS flag is set or not.
Kojto 93:e188a91d3eaa 1544 * @param _FLAG_: specifies the flag to check.
Kojto 93:e188a91d3eaa 1545 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1546 * @arg RCC_CRS_FLAG_SYNCOK
Kojto 93:e188a91d3eaa 1547 * @arg RCC_CRS_FLAG_SYNCWARN
Kojto 93:e188a91d3eaa 1548 * @arg RCC_CRS_FLAG_ERR
Kojto 93:e188a91d3eaa 1549 * @arg RCC_CRS_FLAG_ESYNC
Kojto 93:e188a91d3eaa 1550 * @arg RCC_CRS_FLAG_TRIMOVF
Kojto 93:e188a91d3eaa 1551 * @arg RCC_CRS_FLAG_SYNCERR
Kojto 93:e188a91d3eaa 1552 * @arg RCC_CRS_FLAG_SYNCMISS
Kojto 93:e188a91d3eaa 1553 * @retval The new state of _FLAG_ (TRUE or FALSE).
Kojto 93:e188a91d3eaa 1554 */
Kojto 93:e188a91d3eaa 1555 #define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
Kojto 93:e188a91d3eaa 1556
Kojto 93:e188a91d3eaa 1557 /**
Kojto 93:e188a91d3eaa 1558 * @brief Clears the CRS specified FLAG.
Kojto 93:e188a91d3eaa 1559 * @param _FLAG_: specifies the flag to clear.
Kojto 93:e188a91d3eaa 1560 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1561 * @arg RCC_CRS_FLAG_SYNCOK
Kojto 93:e188a91d3eaa 1562 * @arg RCC_CRS_FLAG_SYNCWARN
Kojto 93:e188a91d3eaa 1563 * @arg RCC_CRS_FLAG_ERR
Kojto 93:e188a91d3eaa 1564 * @arg RCC_CRS_FLAG_ESYNC
Kojto 93:e188a91d3eaa 1565 * @arg RCC_CRS_FLAG_TRIMOVF
Kojto 93:e188a91d3eaa 1566 * @arg RCC_CRS_FLAG_SYNCERR
Kojto 93:e188a91d3eaa 1567 * @arg RCC_CRS_FLAG_SYNCMISS
Kojto 93:e188a91d3eaa 1568 * @retval None
Kojto 93:e188a91d3eaa 1569 */
Kojto 93:e188a91d3eaa 1570
Kojto 93:e188a91d3eaa 1571 /* CRS Flag Error Mask */
Kojto 93:e188a91d3eaa 1572 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
Kojto 93:e188a91d3eaa 1573
Kojto 93:e188a91d3eaa 1574 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
Kojto 93:e188a91d3eaa 1575 (CRS->ICR |= (__FLAG__)))
Kojto 93:e188a91d3eaa 1576
Kojto 93:e188a91d3eaa 1577 /**
Kojto 93:e188a91d3eaa 1578 * @}
Kojto 93:e188a91d3eaa 1579 */
Kojto 93:e188a91d3eaa 1580
Kojto 93:e188a91d3eaa 1581 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
Kojto 93:e188a91d3eaa 1582 * @{
Kojto 93:e188a91d3eaa 1583 */
Kojto 93:e188a91d3eaa 1584 /**
Kojto 93:e188a91d3eaa 1585 * @brief Enables the oscillator clock for frequency error counter.
Kojto 93:e188a91d3eaa 1586 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 93:e188a91d3eaa 1587 * @retval None
Kojto 93:e188a91d3eaa 1588 */
Kojto 93:e188a91d3eaa 1589 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
Kojto 93:e188a91d3eaa 1590
Kojto 93:e188a91d3eaa 1591 /**
Kojto 93:e188a91d3eaa 1592 * @brief Disables the oscillator clock for frequency error counter.
Kojto 93:e188a91d3eaa 1593 * @retval None
Kojto 93:e188a91d3eaa 1594 */
Kojto 93:e188a91d3eaa 1595 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
Kojto 93:e188a91d3eaa 1596
Kojto 93:e188a91d3eaa 1597 /**
Kojto 93:e188a91d3eaa 1598 * @brief Enables the automatic hardware adjustement of TRIM bits.
Kojto 93:e188a91d3eaa 1599 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 93:e188a91d3eaa 1600 * @retval None
Kojto 93:e188a91d3eaa 1601 */
Kojto 93:e188a91d3eaa 1602 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN)
Kojto 93:e188a91d3eaa 1603
Kojto 93:e188a91d3eaa 1604 /**
Kojto 93:e188a91d3eaa 1605 * @brief Enables or disables the automatic hardware adjustement of TRIM bits.
Kojto 93:e188a91d3eaa 1606 * @retval None
Kojto 93:e188a91d3eaa 1607 */
Kojto 93:e188a91d3eaa 1608 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
Kojto 93:e188a91d3eaa 1609
Kojto 93:e188a91d3eaa 1610 /**
Kojto 93:e188a91d3eaa 1611 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
Kojto 93:e188a91d3eaa 1612 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
Kojto 93:e188a91d3eaa 1613 * of the synchronization source after prescaling. It is then decreased by one in order to
Kojto 93:e188a91d3eaa 1614 * reach the expected synchronization on the zero value. The formula is the following:
Kojto 93:e188a91d3eaa 1615 * RELOAD = (fTARGET / fSYNC) -1
Kojto 93:e188a91d3eaa 1616 * @param _FTARGET_ Target frequency (value in Hz)
Kojto 93:e188a91d3eaa 1617 * @param _FSYNC_ Synchronization signal frequency (value in Hz)
Kojto 93:e188a91d3eaa 1618 * @retval None
Kojto 93:e188a91d3eaa 1619 */
Kojto 93:e188a91d3eaa 1620 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
Kojto 93:e188a91d3eaa 1621
Kojto 93:e188a91d3eaa 1622 /**
Kojto 93:e188a91d3eaa 1623 * @}
Kojto 93:e188a91d3eaa 1624 */
Kojto 93:e188a91d3eaa 1625
Kojto 93:e188a91d3eaa 1626 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1627 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1628 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1629
Kojto 93:e188a91d3eaa 1630 /**
Kojto 93:e188a91d3eaa 1631 * @}
Kojto 93:e188a91d3eaa 1632 */
Kojto 93:e188a91d3eaa 1633
Kojto 93:e188a91d3eaa 1634 /* Exported functions --------------------------------------------------------*/
Kojto 93:e188a91d3eaa 1635 /** @addtogroup RCCEx_Exported_Functions
Kojto 93:e188a91d3eaa 1636 * @{
Kojto 93:e188a91d3eaa 1637 */
Kojto 93:e188a91d3eaa 1638
Kojto 93:e188a91d3eaa 1639 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 93:e188a91d3eaa 1640 * @{
Kojto 93:e188a91d3eaa 1641 */
Kojto 93:e188a91d3eaa 1642
Kojto 93:e188a91d3eaa 1643 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 93:e188a91d3eaa 1644 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 93:e188a91d3eaa 1645
Kojto 93:e188a91d3eaa 1646 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1647 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1648 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1649 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
Kojto 93:e188a91d3eaa 1650 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
Kojto 93:e188a91d3eaa 1651 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto 93:e188a91d3eaa 1652 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Kojto 93:e188a91d3eaa 1653 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1654 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1655 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 1656
Kojto 93:e188a91d3eaa 1657
Kojto 93:e188a91d3eaa 1658 /**
Kojto 93:e188a91d3eaa 1659 * @}
Kojto 93:e188a91d3eaa 1660 */
Kojto 93:e188a91d3eaa 1661
Kojto 93:e188a91d3eaa 1662 /**
Kojto 93:e188a91d3eaa 1663 * @}
Kojto 93:e188a91d3eaa 1664 */
Kojto 93:e188a91d3eaa 1665
Kojto 93:e188a91d3eaa 1666 /**
Kojto 93:e188a91d3eaa 1667 * @}
Kojto 93:e188a91d3eaa 1668 */
Kojto 93:e188a91d3eaa 1669
Kojto 93:e188a91d3eaa 1670 /**
Kojto 93:e188a91d3eaa 1671 * @}
Kojto 93:e188a91d3eaa 1672 */
Kojto 93:e188a91d3eaa 1673
Kojto 93:e188a91d3eaa 1674 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 1675 }
Kojto 93:e188a91d3eaa 1676 #endif
Kojto 93:e188a91d3eaa 1677
Kojto 93:e188a91d3eaa 1678 #endif /* __STM32F0xx_HAL_RCC_EX_H */
Kojto 93:e188a91d3eaa 1679
Kojto 93:e188a91d3eaa 1680 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/