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TARGET_NUCLEO_F070RB/stm32f0xx_hal_rcc.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
93:e188a91d3eaa 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 93:e188a91d3eaa 1 /**
Kojto 93:e188a91d3eaa 2 ******************************************************************************
Kojto 93:e188a91d3eaa 3 * @file stm32f0xx_hal_rcc.h
Kojto 93:e188a91d3eaa 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V1.2.0
Kojto 93:e188a91d3eaa 6 * @date 11-December-2014
Kojto 93:e188a91d3eaa 7 * @brief Header file of RCC HAL module.
Kojto 93:e188a91d3eaa 8 ******************************************************************************
Kojto 93:e188a91d3eaa 9 * @attention
Kojto 93:e188a91d3eaa 10 *
Kojto 93:e188a91d3eaa 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 93:e188a91d3eaa 12 *
Kojto 93:e188a91d3eaa 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 93:e188a91d3eaa 14 * are permitted provided that the following conditions are met:
Kojto 93:e188a91d3eaa 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 93:e188a91d3eaa 16 * this list of conditions and the following disclaimer.
Kojto 93:e188a91d3eaa 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 93:e188a91d3eaa 18 * this list of conditions and the following disclaimer in the documentation
Kojto 93:e188a91d3eaa 19 * and/or other materials provided with the distribution.
Kojto 93:e188a91d3eaa 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 93:e188a91d3eaa 21 * may be used to endorse or promote products derived from this software
Kojto 93:e188a91d3eaa 22 * without specific prior written permission.
Kojto 93:e188a91d3eaa 23 *
Kojto 93:e188a91d3eaa 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 93:e188a91d3eaa 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 93:e188a91d3eaa 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 93:e188a91d3eaa 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 93:e188a91d3eaa 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 93:e188a91d3eaa 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 93:e188a91d3eaa 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 93:e188a91d3eaa 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 93:e188a91d3eaa 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 93:e188a91d3eaa 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 93:e188a91d3eaa 34 *
Kojto 93:e188a91d3eaa 35 ******************************************************************************
Kojto 93:e188a91d3eaa 36 */
Kojto 93:e188a91d3eaa 37
Kojto 93:e188a91d3eaa 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 93:e188a91d3eaa 39 #ifndef __STM32F0xx_HAL_RCC_H
Kojto 93:e188a91d3eaa 40 #define __STM32F0xx_HAL_RCC_H
Kojto 93:e188a91d3eaa 41
Kojto 93:e188a91d3eaa 42 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 43 extern "C" {
Kojto 93:e188a91d3eaa 44 #endif
Kojto 93:e188a91d3eaa 45
Kojto 93:e188a91d3eaa 46 /* Includes ------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 47 #include "stm32f0xx_hal_def.h"
Kojto 93:e188a91d3eaa 48
Kojto 93:e188a91d3eaa 49 /** @addtogroup STM32F0xx_HAL_Driver
Kojto 93:e188a91d3eaa 50 * @{
Kojto 93:e188a91d3eaa 51 */
Kojto 93:e188a91d3eaa 52
Kojto 93:e188a91d3eaa 53 /** @addtogroup RCC
Kojto 93:e188a91d3eaa 54 * @{
Kojto 93:e188a91d3eaa 55 */
Kojto 93:e188a91d3eaa 56
Kojto 93:e188a91d3eaa 57 /* Exported types ------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 58
Kojto 93:e188a91d3eaa 59 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 93:e188a91d3eaa 60 * @{
Kojto 93:e188a91d3eaa 61 */
Kojto 93:e188a91d3eaa 62
Kojto 93:e188a91d3eaa 63 /**
Kojto 93:e188a91d3eaa 64 * @brief RCC PLL configuration structure definition
Kojto 93:e188a91d3eaa 65 */
Kojto 93:e188a91d3eaa 66 typedef struct
Kojto 93:e188a91d3eaa 67 {
Kojto 93:e188a91d3eaa 68 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto 93:e188a91d3eaa 69 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 93:e188a91d3eaa 70
Kojto 93:e188a91d3eaa 71 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto 93:e188a91d3eaa 72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 93:e188a91d3eaa 73
Kojto 93:e188a91d3eaa 74 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
Kojto 93:e188a91d3eaa 75 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
Kojto 93:e188a91d3eaa 76
Kojto 93:e188a91d3eaa 77 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto 93:e188a91d3eaa 78 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
Kojto 93:e188a91d3eaa 79
Kojto 93:e188a91d3eaa 80 }RCC_PLLInitTypeDef;
Kojto 93:e188a91d3eaa 81
Kojto 93:e188a91d3eaa 82 /**
Kojto 93:e188a91d3eaa 83 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 93:e188a91d3eaa 84 */
Kojto 93:e188a91d3eaa 85 typedef struct
Kojto 93:e188a91d3eaa 86 {
Kojto 93:e188a91d3eaa 87 uint32_t OscillatorType; /*!< The Oscillators to be configured.
Kojto 93:e188a91d3eaa 88 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 93:e188a91d3eaa 89
Kojto 93:e188a91d3eaa 90 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 93:e188a91d3eaa 91 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 93:e188a91d3eaa 92
Kojto 93:e188a91d3eaa 93 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 93:e188a91d3eaa 94 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 93:e188a91d3eaa 95
Kojto 93:e188a91d3eaa 96 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 93:e188a91d3eaa 97 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 93:e188a91d3eaa 98
Kojto 93:e188a91d3eaa 99 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 93:e188a91d3eaa 100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 93:e188a91d3eaa 101
Kojto 93:e188a91d3eaa 102 uint32_t HSI14State; /*!< The new state of the HSI14.
Kojto 93:e188a91d3eaa 103 This parameter can be a value of @ref RCC_HSI14_Config */
Kojto 93:e188a91d3eaa 104
Kojto 93:e188a91d3eaa 105 uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
Kojto 93:e188a91d3eaa 106 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 93:e188a91d3eaa 107
Kojto 93:e188a91d3eaa 108 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
Kojto 93:e188a91d3eaa 109 This parameter can be a value of @ref RCCEx_HSI48_Config */
Kojto 93:e188a91d3eaa 110
Kojto 93:e188a91d3eaa 111 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 93:e188a91d3eaa 112 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 93:e188a91d3eaa 113
Kojto 93:e188a91d3eaa 114 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 93:e188a91d3eaa 115
Kojto 93:e188a91d3eaa 116 }RCC_OscInitTypeDef;
Kojto 93:e188a91d3eaa 117
Kojto 93:e188a91d3eaa 118 /**
Kojto 93:e188a91d3eaa 119 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 93:e188a91d3eaa 120 */
Kojto 93:e188a91d3eaa 121 typedef struct
Kojto 93:e188a91d3eaa 122 {
Kojto 93:e188a91d3eaa 123 uint32_t ClockType; /*!< The clock to be configured.
Kojto 93:e188a91d3eaa 124 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 93:e188a91d3eaa 125
Kojto 93:e188a91d3eaa 126 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto 93:e188a91d3eaa 127 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 93:e188a91d3eaa 128
Kojto 93:e188a91d3eaa 129 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 93:e188a91d3eaa 130 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 93:e188a91d3eaa 131
Kojto 93:e188a91d3eaa 132 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 93:e188a91d3eaa 133 This parameter can be a value of @ref RCC_APB1_Clock_Source */
Kojto 93:e188a91d3eaa 134
Kojto 93:e188a91d3eaa 135 }RCC_ClkInitTypeDef;
Kojto 93:e188a91d3eaa 136
Kojto 93:e188a91d3eaa 137 /**
Kojto 93:e188a91d3eaa 138 * @}
Kojto 93:e188a91d3eaa 139 */
Kojto 93:e188a91d3eaa 140
Kojto 93:e188a91d3eaa 141 /* Exported constants --------------------------------------------------------*/
Kojto 93:e188a91d3eaa 142 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 93:e188a91d3eaa 143 * @{
Kojto 93:e188a91d3eaa 144 */
Kojto 93:e188a91d3eaa 145
Kojto 93:e188a91d3eaa 146 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 93:e188a91d3eaa 147 * @brief RCC registers bit address in the alias region
Kojto 93:e188a91d3eaa 148 * @{
Kojto 93:e188a91d3eaa 149 */
Kojto 93:e188a91d3eaa 150 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 93:e188a91d3eaa 151 /* --- CR Register ---*/
Kojto 93:e188a91d3eaa 152 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto 93:e188a91d3eaa 153 /* --- CFGR Register ---*/
Kojto 93:e188a91d3eaa 154 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
Kojto 93:e188a91d3eaa 155 /* --- CIR Register ---*/
Kojto 93:e188a91d3eaa 156 #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
Kojto 93:e188a91d3eaa 157 /* --- BDCR Register ---*/
Kojto 93:e188a91d3eaa 158 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
Kojto 93:e188a91d3eaa 159 /* --- CSR Register ---*/
Kojto 93:e188a91d3eaa 160 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
Kojto 93:e188a91d3eaa 161 /* --- CR2 Register ---*/
Kojto 93:e188a91d3eaa 162 #define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
Kojto 93:e188a91d3eaa 163
Kojto 93:e188a91d3eaa 164 /* CR register byte 2 (Bits[23:16]) base address */
Kojto 93:e188a91d3eaa 165 #define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
Kojto 93:e188a91d3eaa 166
Kojto 93:e188a91d3eaa 167 /* CIR register byte 1 (Bits[15:8]) base address */
Kojto 93:e188a91d3eaa 168 #define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
Kojto 93:e188a91d3eaa 169
Kojto 93:e188a91d3eaa 170 /* CIR register byte 2 (Bits[23:16]) base address */
Kojto 93:e188a91d3eaa 171 #define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
Kojto 93:e188a91d3eaa 172
Kojto 93:e188a91d3eaa 173 /* CSR register byte 1 (Bits[15:8]) base address */
Kojto 93:e188a91d3eaa 174 #define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
Kojto 93:e188a91d3eaa 175
Kojto 93:e188a91d3eaa 176 /* BDCR register byte 0 (Bits[7:0] base address */
Kojto 93:e188a91d3eaa 177 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 93:e188a91d3eaa 178
Kojto 93:e188a91d3eaa 179 #define RCC_CFGR_PLLMUL_BITNUMBER 18
Kojto 93:e188a91d3eaa 180 #define RCC_CFGR2_PREDIV_BITNUMBER 0
Kojto 93:e188a91d3eaa 181
Kojto 93:e188a91d3eaa 182 /**
Kojto 93:e188a91d3eaa 183 * @}
Kojto 93:e188a91d3eaa 184 */
Kojto 93:e188a91d3eaa 185
Kojto 93:e188a91d3eaa 186 /** @defgroup RCC_Timeout RCC Timeout
Kojto 93:e188a91d3eaa 187 * @{
Kojto 93:e188a91d3eaa 188 */
Kojto 93:e188a91d3eaa 189 /* LSE state change timeout */
Kojto 93:e188a91d3eaa 190 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto 93:e188a91d3eaa 191
Kojto 93:e188a91d3eaa 192 /* Disable Backup domain write protection state change timeout */
Kojto 93:e188a91d3eaa 193 #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 93:e188a91d3eaa 194 /**
Kojto 93:e188a91d3eaa 195 * @}
Kojto 93:e188a91d3eaa 196 */
Kojto 93:e188a91d3eaa 197
Kojto 93:e188a91d3eaa 198 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
Kojto 93:e188a91d3eaa 199 * @{
Kojto 93:e188a91d3eaa 200 */
Kojto 93:e188a91d3eaa 201 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 202 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 203 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 204 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 205 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 206 #define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 207 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 208
Kojto 93:e188a91d3eaa 209 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
Kojto 93:e188a91d3eaa 210 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
Kojto 93:e188a91d3eaa 211 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
Kojto 93:e188a91d3eaa 212 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
Kojto 93:e188a91d3eaa 213 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
Kojto 93:e188a91d3eaa 214 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
Kojto 93:e188a91d3eaa 215 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
Kojto 93:e188a91d3eaa 216 /**
Kojto 93:e188a91d3eaa 217 * @}
Kojto 93:e188a91d3eaa 218 */
Kojto 93:e188a91d3eaa 219
Kojto 93:e188a91d3eaa 220 /** @defgroup RCC_HSE_Config RCC HSE Config
Kojto 93:e188a91d3eaa 221 * @{
Kojto 93:e188a91d3eaa 222 */
Kojto 93:e188a91d3eaa 223 #define RCC_HSE_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 224 #define RCC_HSE_ON ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 225 #define RCC_HSE_BYPASS ((uint8_t)0x05)
Kojto 93:e188a91d3eaa 226
Kojto 93:e188a91d3eaa 227 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 93:e188a91d3eaa 228 ((HSE) == RCC_HSE_BYPASS))
Kojto 93:e188a91d3eaa 229 /**
Kojto 93:e188a91d3eaa 230 * @}
Kojto 93:e188a91d3eaa 231 */
Kojto 93:e188a91d3eaa 232
Kojto 93:e188a91d3eaa 233 /** @defgroup RCC_LSE_Config RCC_LSE_Config
Kojto 93:e188a91d3eaa 234 * @{
Kojto 93:e188a91d3eaa 235 */
Kojto 93:e188a91d3eaa 236 #define RCC_LSE_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 237 #define RCC_LSE_ON ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 238 #define RCC_LSE_BYPASS ((uint8_t)0x05)
Kojto 93:e188a91d3eaa 239
Kojto 93:e188a91d3eaa 240 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 93:e188a91d3eaa 241 ((LSE) == RCC_LSE_BYPASS))
Kojto 93:e188a91d3eaa 242 /**
Kojto 93:e188a91d3eaa 243 * @}
Kojto 93:e188a91d3eaa 244 */
Kojto 93:e188a91d3eaa 245
Kojto 93:e188a91d3eaa 246 /** @defgroup RCC_HSI_Config RCC HSI Config
Kojto 93:e188a91d3eaa 247 * @{
Kojto 93:e188a91d3eaa 248 */
Kojto 93:e188a91d3eaa 249 #define RCC_HSI_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 250 #define RCC_HSI_ON ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 251
Kojto 93:e188a91d3eaa 252 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 93:e188a91d3eaa 253
Kojto 93:e188a91d3eaa 254 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto 93:e188a91d3eaa 255 /**
Kojto 93:e188a91d3eaa 256 * @}
Kojto 93:e188a91d3eaa 257 */
Kojto 93:e188a91d3eaa 258
Kojto 93:e188a91d3eaa 259 /** @defgroup RCC_HSI14_Config RCC HSI14 Config
Kojto 93:e188a91d3eaa 260 * @{
Kojto 93:e188a91d3eaa 261 */
Kojto 93:e188a91d3eaa 262 #define RCC_HSI14_OFF ((uint32_t)0x00)
Kojto 93:e188a91d3eaa 263 #define RCC_HSI14_ON RCC_CR2_HSI14ON
Kojto 93:e188a91d3eaa 264 #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
Kojto 93:e188a91d3eaa 265
Kojto 93:e188a91d3eaa 266 #define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL))
Kojto 93:e188a91d3eaa 267
Kojto 93:e188a91d3eaa 268 #define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
Kojto 93:e188a91d3eaa 269 /**
Kojto 93:e188a91d3eaa 270 * @}
Kojto 93:e188a91d3eaa 271 */
Kojto 93:e188a91d3eaa 272
Kojto 93:e188a91d3eaa 273 /** @defgroup RCC_LSI_Config RCC LSI Config
Kojto 93:e188a91d3eaa 274 * @{
Kojto 93:e188a91d3eaa 275 */
Kojto 93:e188a91d3eaa 276 #define RCC_LSI_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 277 #define RCC_LSI_ON ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 278
Kojto 93:e188a91d3eaa 279 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 93:e188a91d3eaa 280 /**
Kojto 93:e188a91d3eaa 281 * @}
Kojto 93:e188a91d3eaa 282 */
Kojto 93:e188a91d3eaa 283
Kojto 93:e188a91d3eaa 284 /** @defgroup RCC_PLL_Config RCC PLL Config
Kojto 93:e188a91d3eaa 285 * @{
Kojto 93:e188a91d3eaa 286 */
Kojto 93:e188a91d3eaa 287 #define RCC_PLL_NONE ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 288 #define RCC_PLL_OFF ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 289 #define RCC_PLL_ON ((uint8_t)0x02)
Kojto 93:e188a91d3eaa 290
Kojto 93:e188a91d3eaa 291 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 93:e188a91d3eaa 292 /**
Kojto 93:e188a91d3eaa 293 * @}
Kojto 93:e188a91d3eaa 294 */
Kojto 93:e188a91d3eaa 295
Kojto 93:e188a91d3eaa 296 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
Kojto 93:e188a91d3eaa 297 * @{
Kojto 93:e188a91d3eaa 298 */
Kojto 93:e188a91d3eaa 299 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto 93:e188a91d3eaa 300 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto 93:e188a91d3eaa 301 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto 93:e188a91d3eaa 302 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto 93:e188a91d3eaa 303 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto 93:e188a91d3eaa 304 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto 93:e188a91d3eaa 305 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto 93:e188a91d3eaa 306 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto 93:e188a91d3eaa 307 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto 93:e188a91d3eaa 308 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto 93:e188a91d3eaa 309 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto 93:e188a91d3eaa 310 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto 93:e188a91d3eaa 311 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto 93:e188a91d3eaa 312 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto 93:e188a91d3eaa 313 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto 93:e188a91d3eaa 314 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto 93:e188a91d3eaa 315
Kojto 93:e188a91d3eaa 316 #define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
Kojto 93:e188a91d3eaa 317 ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
Kojto 93:e188a91d3eaa 318 ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
Kojto 93:e188a91d3eaa 319 ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
Kojto 93:e188a91d3eaa 320 ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
Kojto 93:e188a91d3eaa 321 ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
Kojto 93:e188a91d3eaa 322 ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
Kojto 93:e188a91d3eaa 323 ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
Kojto 93:e188a91d3eaa 324 /**
Kojto 93:e188a91d3eaa 325 * @}
Kojto 93:e188a91d3eaa 326 */
Kojto 93:e188a91d3eaa 327
Kojto 93:e188a91d3eaa 328 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
Kojto 93:e188a91d3eaa 329 * @{
Kojto 93:e188a91d3eaa 330 */
Kojto 93:e188a91d3eaa 331 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
Kojto 93:e188a91d3eaa 332 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
Kojto 93:e188a91d3eaa 333 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
Kojto 93:e188a91d3eaa 334 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
Kojto 93:e188a91d3eaa 335 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
Kojto 93:e188a91d3eaa 336 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
Kojto 93:e188a91d3eaa 337 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
Kojto 93:e188a91d3eaa 338 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
Kojto 93:e188a91d3eaa 339 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
Kojto 93:e188a91d3eaa 340 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
Kojto 93:e188a91d3eaa 341 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
Kojto 93:e188a91d3eaa 342 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
Kojto 93:e188a91d3eaa 343 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
Kojto 93:e188a91d3eaa 344 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
Kojto 93:e188a91d3eaa 345 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
Kojto 93:e188a91d3eaa 346
Kojto 93:e188a91d3eaa 347 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
Kojto 93:e188a91d3eaa 348 ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
Kojto 93:e188a91d3eaa 349 ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
Kojto 93:e188a91d3eaa 350 ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
Kojto 93:e188a91d3eaa 351 ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
Kojto 93:e188a91d3eaa 352 ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
Kojto 93:e188a91d3eaa 353 ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
Kojto 93:e188a91d3eaa 354 ((MUL) == RCC_PLL_MUL16))
Kojto 93:e188a91d3eaa 355 /**
Kojto 93:e188a91d3eaa 356 * @}
Kojto 93:e188a91d3eaa 357 */
Kojto 93:e188a91d3eaa 358
Kojto 93:e188a91d3eaa 359 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
Kojto 93:e188a91d3eaa 360 * @{
Kojto 93:e188a91d3eaa 361 */
Kojto 93:e188a91d3eaa 362 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
Kojto 93:e188a91d3eaa 363 /**
Kojto 93:e188a91d3eaa 364 * @}
Kojto 93:e188a91d3eaa 365 */
Kojto 93:e188a91d3eaa 366
Kojto 93:e188a91d3eaa 367 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto 93:e188a91d3eaa 368 * @{
Kojto 93:e188a91d3eaa 369 */
Kojto 93:e188a91d3eaa 370 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 371 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 372 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 373
Kojto 93:e188a91d3eaa 374 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
Kojto 93:e188a91d3eaa 375 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
Kojto 93:e188a91d3eaa 376 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
Kojto 93:e188a91d3eaa 377 /**
Kojto 93:e188a91d3eaa 378 * @}
Kojto 93:e188a91d3eaa 379 */
Kojto 93:e188a91d3eaa 380
Kojto 93:e188a91d3eaa 381 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto 93:e188a91d3eaa 382 * @{
Kojto 93:e188a91d3eaa 383 */
Kojto 93:e188a91d3eaa 384 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto 93:e188a91d3eaa 385 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto 93:e188a91d3eaa 386 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 93:e188a91d3eaa 387 /**
Kojto 93:e188a91d3eaa 388 * @}
Kojto 93:e188a91d3eaa 389 */
Kojto 93:e188a91d3eaa 390
Kojto 93:e188a91d3eaa 391 /** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
Kojto 93:e188a91d3eaa 392 * @{
Kojto 93:e188a91d3eaa 393 */
Kojto 93:e188a91d3eaa 394 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
Kojto 93:e188a91d3eaa 395 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
Kojto 93:e188a91d3eaa 396 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
Kojto 93:e188a91d3eaa 397 /**
Kojto 93:e188a91d3eaa 398 * @}
Kojto 93:e188a91d3eaa 399 */
Kojto 93:e188a91d3eaa 400
Kojto 93:e188a91d3eaa 401 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
Kojto 93:e188a91d3eaa 402 * @{
Kojto 93:e188a91d3eaa 403 */
Kojto 93:e188a91d3eaa 404 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto 93:e188a91d3eaa 405 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto 93:e188a91d3eaa 406 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto 93:e188a91d3eaa 407 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto 93:e188a91d3eaa 408 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto 93:e188a91d3eaa 409 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto 93:e188a91d3eaa 410 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto 93:e188a91d3eaa 411 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto 93:e188a91d3eaa 412 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto 93:e188a91d3eaa 413
Kojto 93:e188a91d3eaa 414 #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
Kojto 93:e188a91d3eaa 415 ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
Kojto 93:e188a91d3eaa 416 ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
Kojto 93:e188a91d3eaa 417 ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
Kojto 93:e188a91d3eaa 418 ((DIV) == RCC_SYSCLK_DIV512))
Kojto 93:e188a91d3eaa 419 /**
Kojto 93:e188a91d3eaa 420 * @}
Kojto 93:e188a91d3eaa 421 */
Kojto 93:e188a91d3eaa 422
Kojto 93:e188a91d3eaa 423 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
Kojto 93:e188a91d3eaa 424 * @{
Kojto 93:e188a91d3eaa 425 */
Kojto 93:e188a91d3eaa 426 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
Kojto 93:e188a91d3eaa 427 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
Kojto 93:e188a91d3eaa 428 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
Kojto 93:e188a91d3eaa 429 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
Kojto 93:e188a91d3eaa 430 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
Kojto 93:e188a91d3eaa 431
Kojto 93:e188a91d3eaa 432 #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
Kojto 93:e188a91d3eaa 433 ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
Kojto 93:e188a91d3eaa 434 ((DIV) == RCC_HCLK_DIV16))
Kojto 93:e188a91d3eaa 435 /**
Kojto 93:e188a91d3eaa 436 * @}
Kojto 93:e188a91d3eaa 437 */
Kojto 93:e188a91d3eaa 438
Kojto 93:e188a91d3eaa 439 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
Kojto 93:e188a91d3eaa 440 * @{
Kojto 93:e188a91d3eaa 441 */
Kojto 93:e188a91d3eaa 442 #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
Kojto 93:e188a91d3eaa 443 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
Kojto 93:e188a91d3eaa 444 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
Kojto 93:e188a91d3eaa 445 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
Kojto 93:e188a91d3eaa 446
Kojto 93:e188a91d3eaa 447 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
Kojto 93:e188a91d3eaa 448 ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 93:e188a91d3eaa 449 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 93:e188a91d3eaa 450 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto 93:e188a91d3eaa 451 /**
Kojto 93:e188a91d3eaa 452 * @}
Kojto 93:e188a91d3eaa 453 */
Kojto 93:e188a91d3eaa 454
Kojto 93:e188a91d3eaa 455 /** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
Kojto 93:e188a91d3eaa 456 * @{
Kojto 93:e188a91d3eaa 457 */
Kojto 93:e188a91d3eaa 458 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
Kojto 93:e188a91d3eaa 459 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto 93:e188a91d3eaa 460 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto 93:e188a91d3eaa 461 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto 93:e188a91d3eaa 462
Kojto 93:e188a91d3eaa 463 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
Kojto 93:e188a91d3eaa 464 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 93:e188a91d3eaa 465 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 93:e188a91d3eaa 466 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 93:e188a91d3eaa 467 /**
Kojto 93:e188a91d3eaa 468 * @}
Kojto 93:e188a91d3eaa 469 */
Kojto 93:e188a91d3eaa 470
Kojto 93:e188a91d3eaa 471 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
Kojto 93:e188a91d3eaa 472 * @{
Kojto 93:e188a91d3eaa 473 */
Kojto 93:e188a91d3eaa 474 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
Kojto 93:e188a91d3eaa 475 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
Kojto 93:e188a91d3eaa 476
Kojto 93:e188a91d3eaa 477 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 478 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
Kojto 93:e188a91d3eaa 479 /**
Kojto 93:e188a91d3eaa 480 * @}
Kojto 93:e188a91d3eaa 481 */
Kojto 93:e188a91d3eaa 482
Kojto 93:e188a91d3eaa 483 /** @defgroup RCC_MCOx_Index RCC MCOx Index
Kojto 93:e188a91d3eaa 484 * @{
Kojto 93:e188a91d3eaa 485 */
Kojto 93:e188a91d3eaa 486 #define RCC_MCO ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 487
Kojto 93:e188a91d3eaa 488 #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
Kojto 93:e188a91d3eaa 489 /**
Kojto 93:e188a91d3eaa 490 * @}
Kojto 93:e188a91d3eaa 491 */
Kojto 93:e188a91d3eaa 492
Kojto 93:e188a91d3eaa 493 /** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
Kojto 93:e188a91d3eaa 494 * @{
Kojto 93:e188a91d3eaa 495 */
Kojto 93:e188a91d3eaa 496 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
Kojto 93:e188a91d3eaa 497 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
Kojto 93:e188a91d3eaa 498 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
Kojto 93:e188a91d3eaa 499 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 93:e188a91d3eaa 500 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
Kojto 93:e188a91d3eaa 501 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
Kojto 93:e188a91d3eaa 502 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto 93:e188a91d3eaa 503 #define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
Kojto 93:e188a91d3eaa 504 /**
Kojto 93:e188a91d3eaa 505 * @}
Kojto 93:e188a91d3eaa 506 */
Kojto 93:e188a91d3eaa 507
Kojto 93:e188a91d3eaa 508 /** @defgroup RCC_Interrupt RCC Interrupt
Kojto 93:e188a91d3eaa 509 * @{
Kojto 93:e188a91d3eaa 510 */
Kojto 93:e188a91d3eaa 511 #define RCC_IT_LSIRDY ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 512 #define RCC_IT_LSERDY ((uint8_t)0x02)
Kojto 93:e188a91d3eaa 513 #define RCC_IT_HSIRDY ((uint8_t)0x04)
Kojto 93:e188a91d3eaa 514 #define RCC_IT_HSERDY ((uint8_t)0x08)
Kojto 93:e188a91d3eaa 515 #define RCC_IT_PLLRDY ((uint8_t)0x10)
Kojto 93:e188a91d3eaa 516 #define RCC_IT_HSI14 ((uint8_t)0x20)
Kojto 93:e188a91d3eaa 517 #define RCC_IT_CSS ((uint8_t)0x80)
Kojto 93:e188a91d3eaa 518 /**
Kojto 93:e188a91d3eaa 519 * @}
Kojto 93:e188a91d3eaa 520 */
Kojto 93:e188a91d3eaa 521
Kojto 93:e188a91d3eaa 522 /** @defgroup RCC_Flag RCC Flag
Kojto 93:e188a91d3eaa 523 * Elements values convention: 0XXYYYYYb
Kojto 93:e188a91d3eaa 524 * - YYYYY : Flag position in the register
Kojto 93:e188a91d3eaa 525 * - XX : Register index
Kojto 93:e188a91d3eaa 526 * - 00: CR register
Kojto 93:e188a91d3eaa 527 * - 01: CR2 register
Kojto 93:e188a91d3eaa 528 * - 10: BDCR register
Kojto 93:e188a91d3eaa 529 * - 11: CSR register
Kojto 93:e188a91d3eaa 530 * @{
Kojto 93:e188a91d3eaa 531 */
Kojto 93:e188a91d3eaa 532 #define CR_REG_INDEX 0
Kojto 93:e188a91d3eaa 533 #define CR2_REG_INDEX 1
Kojto 93:e188a91d3eaa 534 #define BDCR_REG_INDEX 2
Kojto 93:e188a91d3eaa 535 #define CSR_REG_INDEX 3
Kojto 93:e188a91d3eaa 536
Kojto 93:e188a91d3eaa 537 /* Flags in the CR register */
Kojto 93:e188a91d3eaa 538 #define RCC_CR_HSIRDY_BitNumber 1
Kojto 93:e188a91d3eaa 539 #define RCC_CR_HSERDY_BitNumber 17
Kojto 93:e188a91d3eaa 540 #define RCC_CR_PLLRDY_BitNumber 25
Kojto 93:e188a91d3eaa 541
Kojto 93:e188a91d3eaa 542 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber))
Kojto 93:e188a91d3eaa 543 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber))
Kojto 93:e188a91d3eaa 544 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber))
Kojto 93:e188a91d3eaa 545
Kojto 93:e188a91d3eaa 546 /* Flags in the CR2 register */
Kojto 93:e188a91d3eaa 547 #define RCC_CR2_HSI14RDY_BitNumber 1
Kojto 93:e188a91d3eaa 548
Kojto 93:e188a91d3eaa 549 #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber))
Kojto 93:e188a91d3eaa 550
Kojto 93:e188a91d3eaa 551 /* Flags in the BDCR register */
Kojto 93:e188a91d3eaa 552 #define RCC_BDCR_LSERDY_BitNumber 1
Kojto 93:e188a91d3eaa 553
Kojto 93:e188a91d3eaa 554 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
Kojto 93:e188a91d3eaa 555
Kojto 93:e188a91d3eaa 556 /* Flags in the CSR register */
Kojto 93:e188a91d3eaa 557 #define RCC_CSR_LSIRDY_BitNumber 1
Kojto 93:e188a91d3eaa 558 #define RCC_CSR_V18PWRRSTF_BitNumber 23
Kojto 93:e188a91d3eaa 559 #define RCC_CSR_RMVF_BitNumber 24
Kojto 93:e188a91d3eaa 560 #define RCC_CSR_OBLRSTF_BitNumber 25
Kojto 93:e188a91d3eaa 561 #define RCC_CSR_PINRSTF_BitNumber 26
Kojto 93:e188a91d3eaa 562 #define RCC_CSR_PORRSTF_BitNumber 27
Kojto 93:e188a91d3eaa 563 #define RCC_CSR_SFTRSTF_BitNumber 28
Kojto 93:e188a91d3eaa 564 #define RCC_CSR_IWDGRSTF_BitNumber 29
Kojto 93:e188a91d3eaa 565 #define RCC_CSR_WWDGRSTF_BitNumber 30
Kojto 93:e188a91d3eaa 566 #define RCC_CSR_LPWRRSTF_BitNumber 31
Kojto 93:e188a91d3eaa 567
Kojto 93:e188a91d3eaa 568 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
Kojto 93:e188a91d3eaa 569 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
Kojto 93:e188a91d3eaa 570 #define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber))
Kojto 93:e188a91d3eaa 571 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber))
Kojto 93:e188a91d3eaa 572 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber))
Kojto 93:e188a91d3eaa 573 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber))
Kojto 93:e188a91d3eaa 574 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_BitNumber))
Kojto 93:e188a91d3eaa 575 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber))
Kojto 93:e188a91d3eaa 576 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber))
Kojto 93:e188a91d3eaa 577 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber))
Kojto 93:e188a91d3eaa 578 /**
Kojto 93:e188a91d3eaa 579 * @}
Kojto 93:e188a91d3eaa 580 */
Kojto 93:e188a91d3eaa 581
Kojto 93:e188a91d3eaa 582 /** @defgroup RCC_Calibration_values RCC Calibration values
Kojto 93:e188a91d3eaa 583 * @{
Kojto 93:e188a91d3eaa 584 */
Kojto 93:e188a91d3eaa 585 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto 93:e188a91d3eaa 586
Kojto 93:e188a91d3eaa 587 /**
Kojto 93:e188a91d3eaa 588 * @}
Kojto 93:e188a91d3eaa 589 */
Kojto 93:e188a91d3eaa 590
Kojto 93:e188a91d3eaa 591 /** @addtogroup RCC_Timeout
Kojto 93:e188a91d3eaa 592 * @{
Kojto 93:e188a91d3eaa 593 */
Kojto 93:e188a91d3eaa 594
Kojto 93:e188a91d3eaa 595 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 93:e188a91d3eaa 596 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 93:e188a91d3eaa 597 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 93:e188a91d3eaa 598 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto 93:e188a91d3eaa 599 #define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 93:e188a91d3eaa 600 #define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 93:e188a91d3eaa 601 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 93:e188a91d3eaa 602 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto 93:e188a91d3eaa 603
Kojto 93:e188a91d3eaa 604 /**
Kojto 93:e188a91d3eaa 605 * @}
Kojto 93:e188a91d3eaa 606 */
Kojto 93:e188a91d3eaa 607
Kojto 93:e188a91d3eaa 608 /**
Kojto 93:e188a91d3eaa 609 * @}
Kojto 93:e188a91d3eaa 610 */
Kojto 93:e188a91d3eaa 611
Kojto 93:e188a91d3eaa 612 /* Exported macro ------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 613
Kojto 93:e188a91d3eaa 614 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 93:e188a91d3eaa 615 * @{
Kojto 93:e188a91d3eaa 616 */
Kojto 93:e188a91d3eaa 617
Kojto 93:e188a91d3eaa 618 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
Kojto 93:e188a91d3eaa 619 * @brief Enable or disable the AHB peripheral clock.
Kojto 93:e188a91d3eaa 620 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 621 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 622 * using it.
Kojto 93:e188a91d3eaa 623 * @{
Kojto 93:e188a91d3eaa 624 */
Kojto 93:e188a91d3eaa 625 #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
Kojto 93:e188a91d3eaa 626 #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
Kojto 93:e188a91d3eaa 627 #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
Kojto 93:e188a91d3eaa 628 #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
Kojto 93:e188a91d3eaa 629 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
Kojto 93:e188a91d3eaa 630 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
Kojto 93:e188a91d3eaa 631 #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
Kojto 93:e188a91d3eaa 632 #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
Kojto 93:e188a91d3eaa 633
Kojto 93:e188a91d3eaa 634 #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto 93:e188a91d3eaa 635 #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto 93:e188a91d3eaa 636 #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto 93:e188a91d3eaa 637 #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
Kojto 93:e188a91d3eaa 638 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto 93:e188a91d3eaa 639 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto 93:e188a91d3eaa 640 #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
Kojto 93:e188a91d3eaa 641 #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
Kojto 93:e188a91d3eaa 642 /**
Kojto 93:e188a91d3eaa 643 * @}
Kojto 93:e188a91d3eaa 644 */
Kojto 93:e188a91d3eaa 645
Kojto 93:e188a91d3eaa 646 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
Kojto 93:e188a91d3eaa 647 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 93:e188a91d3eaa 648 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 649 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 650 * using it.
Kojto 93:e188a91d3eaa 651 * @{
Kojto 93:e188a91d3eaa 652 */
Kojto 93:e188a91d3eaa 653 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
Kojto 93:e188a91d3eaa 654 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
Kojto 93:e188a91d3eaa 655 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
Kojto 93:e188a91d3eaa 656 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
Kojto 93:e188a91d3eaa 657 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
Kojto 93:e188a91d3eaa 658
Kojto 93:e188a91d3eaa 659 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 93:e188a91d3eaa 660 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 93:e188a91d3eaa 661 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 93:e188a91d3eaa 662 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 93:e188a91d3eaa 663 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 93:e188a91d3eaa 664 /**
Kojto 93:e188a91d3eaa 665 * @}
Kojto 93:e188a91d3eaa 666 */
Kojto 93:e188a91d3eaa 667
Kojto 93:e188a91d3eaa 668 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
Kojto 93:e188a91d3eaa 669 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 93:e188a91d3eaa 670 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 671 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 672 * using it.
Kojto 93:e188a91d3eaa 673 * @{
Kojto 93:e188a91d3eaa 674 */
Kojto 93:e188a91d3eaa 675 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
Kojto 93:e188a91d3eaa 676 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
Kojto 93:e188a91d3eaa 677 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
Kojto 93:e188a91d3eaa 678 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
Kojto 93:e188a91d3eaa 679 #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
Kojto 93:e188a91d3eaa 680 #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
Kojto 93:e188a91d3eaa 681 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
Kojto 93:e188a91d3eaa 682 #define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
Kojto 93:e188a91d3eaa 683
Kojto 93:e188a91d3eaa 684 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 93:e188a91d3eaa 685 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 93:e188a91d3eaa 686 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 93:e188a91d3eaa 687 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 93:e188a91d3eaa 688 #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
Kojto 93:e188a91d3eaa 689 #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
Kojto 93:e188a91d3eaa 690 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 93:e188a91d3eaa 691 #define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
Kojto 93:e188a91d3eaa 692 /**
Kojto 93:e188a91d3eaa 693 * @}
Kojto 93:e188a91d3eaa 694 */
Kojto 93:e188a91d3eaa 695
Kojto 93:e188a91d3eaa 696 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
Kojto 93:e188a91d3eaa 697 * @brief Force or release AHB peripheral reset.
Kojto 93:e188a91d3eaa 698 * @{
Kojto 93:e188a91d3eaa 699 */
Kojto 93:e188a91d3eaa 700 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto 93:e188a91d3eaa 701 #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
Kojto 93:e188a91d3eaa 702 #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
Kojto 93:e188a91d3eaa 703 #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
Kojto 93:e188a91d3eaa 704 #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
Kojto 93:e188a91d3eaa 705
Kojto 93:e188a91d3eaa 706 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto 93:e188a91d3eaa 707 #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto 93:e188a91d3eaa 708 #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto 93:e188a91d3eaa 709 #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto 93:e188a91d3eaa 710 #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
Kojto 93:e188a91d3eaa 711 /**
Kojto 93:e188a91d3eaa 712 * @}
Kojto 93:e188a91d3eaa 713 */
Kojto 93:e188a91d3eaa 714
Kojto 93:e188a91d3eaa 715 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
Kojto 93:e188a91d3eaa 716 * @brief Force or release APB1 peripheral reset.
Kojto 93:e188a91d3eaa 717 * @{
Kojto 93:e188a91d3eaa 718 */
Kojto 93:e188a91d3eaa 719 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 93:e188a91d3eaa 720 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 93:e188a91d3eaa 721 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 93:e188a91d3eaa 722 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 93:e188a91d3eaa 723 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 93:e188a91d3eaa 724 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
Kojto 93:e188a91d3eaa 725
Kojto 93:e188a91d3eaa 726 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 93:e188a91d3eaa 727 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 93:e188a91d3eaa 728 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 93:e188a91d3eaa 729 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 93:e188a91d3eaa 730 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 93:e188a91d3eaa 731 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 93:e188a91d3eaa 732 /**
Kojto 93:e188a91d3eaa 733 * @}
Kojto 93:e188a91d3eaa 734 */
Kojto 93:e188a91d3eaa 735
Kojto 93:e188a91d3eaa 736 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
Kojto 93:e188a91d3eaa 737 * @brief Force or release APB2 peripheral reset.
Kojto 93:e188a91d3eaa 738 * @{
Kojto 93:e188a91d3eaa 739 */
Kojto 93:e188a91d3eaa 740 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 93:e188a91d3eaa 741 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 93:e188a91d3eaa 742 #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
Kojto 93:e188a91d3eaa 743 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 93:e188a91d3eaa 744 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 93:e188a91d3eaa 745 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 93:e188a91d3eaa 746 #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
Kojto 93:e188a91d3eaa 747 #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
Kojto 93:e188a91d3eaa 748 #define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
Kojto 93:e188a91d3eaa 749
Kojto 93:e188a91d3eaa 750 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 93:e188a91d3eaa 751 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 93:e188a91d3eaa 752 #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto 93:e188a91d3eaa 753 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 93:e188a91d3eaa 754 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 93:e188a91d3eaa 755 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 93:e188a91d3eaa 756 #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
Kojto 93:e188a91d3eaa 757 #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
Kojto 93:e188a91d3eaa 758 #define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
Kojto 93:e188a91d3eaa 759 /**
Kojto 93:e188a91d3eaa 760 * @}
Kojto 93:e188a91d3eaa 761 */
Kojto 93:e188a91d3eaa 762
Kojto 93:e188a91d3eaa 763 /** @defgroup RCC_HSI_Configuration RCC HSI Configuration
Kojto 93:e188a91d3eaa 764 * @{
Kojto 93:e188a91d3eaa 765 */
Kojto 93:e188a91d3eaa 766
Kojto 93:e188a91d3eaa 767 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 93:e188a91d3eaa 768 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 769 * It is used (enabled by hardware) as system clock source after startup
Kojto 93:e188a91d3eaa 770 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto 93:e188a91d3eaa 771 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 93:e188a91d3eaa 772 * Security System CSS is enabled).
Kojto 93:e188a91d3eaa 773 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 93:e188a91d3eaa 774 * you have to select another source of the system clock then stop the HSI.
Kojto 93:e188a91d3eaa 775 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 93:e188a91d3eaa 776 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 93:e188a91d3eaa 777 * system clock source.
Kojto 93:e188a91d3eaa 778 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 93:e188a91d3eaa 779 * clock cycles.
Kojto 93:e188a91d3eaa 780 */
Kojto 93:e188a91d3eaa 781 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto 93:e188a91d3eaa 782 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto 93:e188a91d3eaa 783
Kojto 93:e188a91d3eaa 784 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 93:e188a91d3eaa 785 * @note The calibration is used to compensate for the variations in voltage
Kojto 93:e188a91d3eaa 786 * and temperature that influence the frequency of the internal HSI RC.
Kojto 93:e188a91d3eaa 787 * @param __HSICalibrationValue__: specifies the calibration trimming value
Kojto 93:e188a91d3eaa 788 * (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 93:e188a91d3eaa 789 * This parameter must be a number between 0 and 0x1F.
Kojto 93:e188a91d3eaa 790 */
Kojto 93:e188a91d3eaa 791 #define RCC_CR_HSITRIM_BitNumber 3
Kojto 93:e188a91d3eaa 792 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
Kojto 93:e188a91d3eaa 793 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
Kojto 93:e188a91d3eaa 794 /**
Kojto 93:e188a91d3eaa 795 * @}
Kojto 93:e188a91d3eaa 796 */
Kojto 93:e188a91d3eaa 797
Kojto 93:e188a91d3eaa 798 /** @defgroup RCC_LSI_Configuration RCC LSI Configuration
Kojto 93:e188a91d3eaa 799 * @{
Kojto 93:e188a91d3eaa 800 */
Kojto 93:e188a91d3eaa 801
Kojto 93:e188a91d3eaa 802 /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 93:e188a91d3eaa 803 * @note After enabling the LSI, the application software should wait on
Kojto 93:e188a91d3eaa 804 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 93:e188a91d3eaa 805 * be used to clock the IWDG and/or the RTC.
Kojto 93:e188a91d3eaa 806 * @note LSI can not be disabled if the IWDG is running.
Kojto 93:e188a91d3eaa 807 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 93:e188a91d3eaa 808 * clock cycles.
Kojto 93:e188a91d3eaa 809 */
Kojto 93:e188a91d3eaa 810 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 93:e188a91d3eaa 811 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 93:e188a91d3eaa 812 /**
Kojto 93:e188a91d3eaa 813 * @}
Kojto 93:e188a91d3eaa 814 */
Kojto 93:e188a91d3eaa 815
Kojto 93:e188a91d3eaa 816 /** @defgroup RCC_HSE_Configuration RCC HSE Configuration
Kojto 93:e188a91d3eaa 817 * @{
Kojto 93:e188a91d3eaa 818 */
Kojto 93:e188a91d3eaa 819
Kojto 93:e188a91d3eaa 820 /**
Kojto 93:e188a91d3eaa 821 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 93:e188a91d3eaa 822 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 93:e188a91d3eaa 823 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 93:e188a91d3eaa 824 * is stable and can be used to clock the PLL and/or system clock.
Kojto 93:e188a91d3eaa 825 * @note HSE state can not be changed if it is used directly or through the
Kojto 93:e188a91d3eaa 826 * PLL as system clock. In this case, you have to select another source
Kojto 93:e188a91d3eaa 827 * of the system clock then change the HSE state (ex. disable it).
Kojto 93:e188a91d3eaa 828 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 829 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
Kojto 93:e188a91d3eaa 830 * was previously enabled you have to enable it again after calling this
Kojto 93:e188a91d3eaa 831 * function.
Kojto 93:e188a91d3eaa 832 * @param __STATE__: specifies the new state of the HSE.
Kojto 93:e188a91d3eaa 833 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 834 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 93:e188a91d3eaa 835 * 6 HSE oscillator clock cycles.
Kojto 93:e188a91d3eaa 836 * @arg RCC_HSE_ON: turn ON the HSE oscillator
Kojto 93:e188a91d3eaa 837 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
Kojto 93:e188a91d3eaa 838 */
Kojto 93:e188a91d3eaa 839 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto 93:e188a91d3eaa 840
Kojto 93:e188a91d3eaa 841 /**
Kojto 93:e188a91d3eaa 842 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
Kojto 93:e188a91d3eaa 843 * @note Predivision factor can not be changed if PLL is used as system clock
Kojto 93:e188a91d3eaa 844 * In this case, you have to select another source of the system clock, disable the PLL and
Kojto 93:e188a91d3eaa 845 * then change the HSE predivision factor.
Kojto 93:e188a91d3eaa 846 * @param __HSEPredivValue__: specifies the division value applied to HSE.
Kojto 93:e188a91d3eaa 847 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
Kojto 93:e188a91d3eaa 848 */
Kojto 93:e188a91d3eaa 849 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
Kojto 93:e188a91d3eaa 850 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
Kojto 93:e188a91d3eaa 851 /**
Kojto 93:e188a91d3eaa 852 * @}
Kojto 93:e188a91d3eaa 853 */
Kojto 93:e188a91d3eaa 854
Kojto 93:e188a91d3eaa 855 /** @defgroup RCC_LSE_Configuration RCC LSE Configuration
Kojto 93:e188a91d3eaa 856 * @{
Kojto 93:e188a91d3eaa 857 */
Kojto 93:e188a91d3eaa 858 /**
Kojto 93:e188a91d3eaa 859 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 93:e188a91d3eaa 860 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 93:e188a91d3eaa 861 * this domain after reset, you have to enable write access using
Kojto 93:e188a91d3eaa 862 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 93:e188a91d3eaa 863 * (to be done once after reset).
Kojto 93:e188a91d3eaa 864 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 93:e188a91d3eaa 865 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 93:e188a91d3eaa 866 * is stable and can be used to clock the RTC.
Kojto 93:e188a91d3eaa 867 * @param __STATE__: specifies the new state of the LSE.
Kojto 93:e188a91d3eaa 868 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 869 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 93:e188a91d3eaa 870 * 6 LSE oscillator clock cycles.
Kojto 93:e188a91d3eaa 871 * @arg RCC_LSE_ON: turn ON the LSE oscillator
Kojto 93:e188a91d3eaa 872 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
Kojto 93:e188a91d3eaa 873 */
Kojto 93:e188a91d3eaa 874 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto 93:e188a91d3eaa 875 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
Kojto 93:e188a91d3eaa 876 /**
Kojto 93:e188a91d3eaa 877 * @}
Kojto 93:e188a91d3eaa 878 */
Kojto 93:e188a91d3eaa 879
Kojto 93:e188a91d3eaa 880 /** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
Kojto 93:e188a91d3eaa 881 * @{
Kojto 93:e188a91d3eaa 882 */
Kojto 93:e188a91d3eaa 883
Kojto 93:e188a91d3eaa 884 /** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
Kojto 93:e188a91d3eaa 885 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 886 * @note HSI14 can not be stopped if it is used as system clock source. In this case,
Kojto 93:e188a91d3eaa 887 * you have to select another source of the system clock then stop the HSI14.
Kojto 93:e188a91d3eaa 888 * @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
Kojto 93:e188a91d3eaa 889 * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
Kojto 93:e188a91d3eaa 890 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
Kojto 93:e188a91d3eaa 891 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
Kojto 93:e188a91d3eaa 892 * clock cycles.
Kojto 93:e188a91d3eaa 893 */
Kojto 93:e188a91d3eaa 894 #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
Kojto 93:e188a91d3eaa 895 #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
Kojto 93:e188a91d3eaa 896
Kojto 93:e188a91d3eaa 897 /** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
Kojto 93:e188a91d3eaa 898 */
Kojto 93:e188a91d3eaa 899 #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
Kojto 93:e188a91d3eaa 900 #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
Kojto 93:e188a91d3eaa 901
Kojto 93:e188a91d3eaa 902 /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
Kojto 93:e188a91d3eaa 903 * @note The calibration is used to compensate for the variations in voltage
Kojto 93:e188a91d3eaa 904 * and temperature that influence the frequency of the internal HSI14 RC.
Kojto 93:e188a91d3eaa 905 * @param __HSI14CalibrationValue__: specifies the calibration trimming value
Kojto 93:e188a91d3eaa 906 * (default is RCC_HSI14CALIBRATION_DEFAULT).
Kojto 93:e188a91d3eaa 907 * This parameter must be a number between 0 and 0x1F.
Kojto 93:e188a91d3eaa 908 */
Kojto 93:e188a91d3eaa 909 #define RCC_CR2_HSI14TRIM_BitNumber 3
Kojto 93:e188a91d3eaa 910 #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
Kojto 93:e188a91d3eaa 911 MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
Kojto 93:e188a91d3eaa 912 /**
Kojto 93:e188a91d3eaa 913 * @}
Kojto 93:e188a91d3eaa 914 */
Kojto 93:e188a91d3eaa 915
Kojto 93:e188a91d3eaa 916 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
Kojto 93:e188a91d3eaa 917 * @{
Kojto 93:e188a91d3eaa 918 */
Kojto 93:e188a91d3eaa 919
Kojto 93:e188a91d3eaa 920 /** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto 93:e188a91d3eaa 921 * @param __USART1CLKSource__: specifies the USART1 clock source.
Kojto 93:e188a91d3eaa 922 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 923 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
Kojto 93:e188a91d3eaa 924 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 93:e188a91d3eaa 925 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 93:e188a91d3eaa 926 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 93:e188a91d3eaa 927 */
Kojto 93:e188a91d3eaa 928 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
Kojto 93:e188a91d3eaa 929 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
Kojto 93:e188a91d3eaa 930
Kojto 93:e188a91d3eaa 931 /** @brief Macro to get the USART1 clock source.
Kojto 93:e188a91d3eaa 932 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 933 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
Kojto 93:e188a91d3eaa 934 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 93:e188a91d3eaa 935 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 93:e188a91d3eaa 936 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 93:e188a91d3eaa 937 */
Kojto 93:e188a91d3eaa 938 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
Kojto 93:e188a91d3eaa 939 /**
Kojto 93:e188a91d3eaa 940 * @}
Kojto 93:e188a91d3eaa 941 */
Kojto 93:e188a91d3eaa 942
Kojto 93:e188a91d3eaa 943 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
Kojto 93:e188a91d3eaa 944 * @{
Kojto 93:e188a91d3eaa 945 */
Kojto 93:e188a91d3eaa 946
Kojto 93:e188a91d3eaa 947 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto 93:e188a91d3eaa 948 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
Kojto 93:e188a91d3eaa 949 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 950 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 93:e188a91d3eaa 951 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 93:e188a91d3eaa 952 */
Kojto 93:e188a91d3eaa 953 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
Kojto 93:e188a91d3eaa 954 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
Kojto 93:e188a91d3eaa 955
Kojto 93:e188a91d3eaa 956 /** @brief Macro to get the I2C1 clock source.
Kojto 93:e188a91d3eaa 957 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 958 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 93:e188a91d3eaa 959 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 93:e188a91d3eaa 960 */
Kojto 93:e188a91d3eaa 961 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
Kojto 93:e188a91d3eaa 962 /**
Kojto 93:e188a91d3eaa 963 * @}
Kojto 93:e188a91d3eaa 964 */
Kojto 93:e188a91d3eaa 965
Kojto 93:e188a91d3eaa 966 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto 93:e188a91d3eaa 967 * @{
Kojto 93:e188a91d3eaa 968 */
Kojto 93:e188a91d3eaa 969 /** @brief Macros to enable or disable the the RTC clock.
Kojto 93:e188a91d3eaa 970 * @note These macros must be used only after the RTC clock source was selected.
Kojto 93:e188a91d3eaa 971 */
Kojto 93:e188a91d3eaa 972 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto 93:e188a91d3eaa 973 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto 93:e188a91d3eaa 974
Kojto 93:e188a91d3eaa 975 /** @brief Macro to configure the RTC clock (RTCCLK).
Kojto 93:e188a91d3eaa 976 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 93:e188a91d3eaa 977 * access is denied to this domain after reset, you have to enable write
Kojto 93:e188a91d3eaa 978 * access using the Power Backup Access macro before to configure
Kojto 93:e188a91d3eaa 979 * the RTC clock source (to be done once after reset).
Kojto 93:e188a91d3eaa 980 * @note Once the RTC clock is configured it can't be changed unless the
Kojto 93:e188a91d3eaa 981 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto 93:e188a91d3eaa 982 * a Power On Reset (POR).
Kojto 93:e188a91d3eaa 983 * @param __RTCCLKSource__: specifies the RTC clock source.
Kojto 93:e188a91d3eaa 984 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 985 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
Kojto 93:e188a91d3eaa 986 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto 93:e188a91d3eaa 987 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto 93:e188a91d3eaa 988 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
Kojto 93:e188a91d3eaa 989 *
Kojto 93:e188a91d3eaa 990 * @note If the LSE is used as RTC clock source, the RTC continues to
Kojto 93:e188a91d3eaa 991 * work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto 93:e188a91d3eaa 992 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
Kojto 93:e188a91d3eaa 993 * the RTC cannot be used in STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 994 * @note The system must always be configured so as to get a PCLK frequency greater than or
Kojto 93:e188a91d3eaa 995 * equal to the RTCCLK frequency for a proper operation of the RTC.
Kojto 93:e188a91d3eaa 996 */
Kojto 93:e188a91d3eaa 997 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
Kojto 93:e188a91d3eaa 998 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
Kojto 93:e188a91d3eaa 999
Kojto 93:e188a91d3eaa 1000 /** @brief Macro to get the RTC clock source.
Kojto 93:e188a91d3eaa 1001 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 1002 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
Kojto 93:e188a91d3eaa 1003 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto 93:e188a91d3eaa 1004 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto 93:e188a91d3eaa 1005 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
Kojto 93:e188a91d3eaa 1006 */
Kojto 93:e188a91d3eaa 1007 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Kojto 93:e188a91d3eaa 1008 /**
Kojto 93:e188a91d3eaa 1009 * @}
Kojto 93:e188a91d3eaa 1010 */
Kojto 93:e188a91d3eaa 1011
Kojto 93:e188a91d3eaa 1012 /** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
Kojto 93:e188a91d3eaa 1013 * @{
Kojto 93:e188a91d3eaa 1014 */
Kojto 93:e188a91d3eaa 1015
Kojto 93:e188a91d3eaa 1016 /** @brief Macro to force or release the Backup domain reset.
Kojto 93:e188a91d3eaa 1017 * @note These macros reset the RTC peripheral (including the backup registers)
Kojto 93:e188a91d3eaa 1018 * and the RTC clock source selection in RCC_CSR register.
Kojto 93:e188a91d3eaa 1019 * @note The BKPSRAM is not affected by this reset.
Kojto 93:e188a91d3eaa 1020 */
Kojto 93:e188a91d3eaa 1021 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 93:e188a91d3eaa 1022 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 93:e188a91d3eaa 1023 /**
Kojto 93:e188a91d3eaa 1024 * @}
Kojto 93:e188a91d3eaa 1025 */
Kojto 93:e188a91d3eaa 1026
Kojto 93:e188a91d3eaa 1027 /** @defgroup RCC_PLL_Configuration RCC PLL Configuration
Kojto 93:e188a91d3eaa 1028 * @{
Kojto 93:e188a91d3eaa 1029 */
Kojto 93:e188a91d3eaa 1030
Kojto 93:e188a91d3eaa 1031 /** @brief Macro to enable or disable the PLL.
Kojto 93:e188a91d3eaa 1032 * @note After enabling the PLL, the application software should wait on
Kojto 93:e188a91d3eaa 1033 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 93:e188a91d3eaa 1034 * be used as system clock source.
Kojto 93:e188a91d3eaa 1035 * @note The PLL can not be disabled if it is used as system clock source
Kojto 93:e188a91d3eaa 1036 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 1037 */
Kojto 93:e188a91d3eaa 1038 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 93:e188a91d3eaa 1039 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 93:e188a91d3eaa 1040
Kojto 93:e188a91d3eaa 1041 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
Kojto 93:e188a91d3eaa 1042 * @note This macro must be used only when the PLL is disabled.
Kojto 93:e188a91d3eaa 1043 *
Kojto 93:e188a91d3eaa 1044 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto 93:e188a91d3eaa 1045 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1046 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 93:e188a91d3eaa 1047 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 93:e188a91d3eaa 1048 * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
Kojto 93:e188a91d3eaa 1049 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
Kojto 93:e188a91d3eaa 1050 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
Kojto 93:e188a91d3eaa 1051 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto 93:e188a91d3eaa 1052 *
Kojto 93:e188a91d3eaa 1053 */
Kojto 93:e188a91d3eaa 1054 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
Kojto 93:e188a91d3eaa 1055 do { \
Kojto 93:e188a91d3eaa 1056 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
Kojto 93:e188a91d3eaa 1057 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
Kojto 93:e188a91d3eaa 1058 } while(0)
Kojto 93:e188a91d3eaa 1059 /**
Kojto 93:e188a91d3eaa 1060 * @}
Kojto 93:e188a91d3eaa 1061 */
Kojto 93:e188a91d3eaa 1062
Kojto 93:e188a91d3eaa 1063 /** @defgroup RCC_Get_Clock_source RCC Get Clock source
Kojto 93:e188a91d3eaa 1064 * @{
Kojto 93:e188a91d3eaa 1065 */
Kojto 93:e188a91d3eaa 1066
Kojto 93:e188a91d3eaa 1067 /** @brief Macro to get the clock source used as system clock.
Kojto 93:e188a91d3eaa 1068 * @retval The clock source used as system clock.
Kojto 93:e188a91d3eaa 1069 * The returned value can be one of the following value:
Kojto 93:e188a91d3eaa 1070 * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
Kojto 93:e188a91d3eaa 1071 * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
Kojto 93:e188a91d3eaa 1072 * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
Kojto 93:e188a91d3eaa 1073 */
Kojto 93:e188a91d3eaa 1074 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
Kojto 93:e188a91d3eaa 1075
Kojto 93:e188a91d3eaa 1076 /** @brief Macro to get the oscillator used as PLL clock source.
Kojto 93:e188a91d3eaa 1077 * @retval The oscillator used as PLL clock source. The returned value can be one
Kojto 93:e188a91d3eaa 1078 * of the following:
Kojto 93:e188a91d3eaa 1079 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto 93:e188a91d3eaa 1080 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto 93:e188a91d3eaa 1081 */
Kojto 93:e188a91d3eaa 1082 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Kojto 93:e188a91d3eaa 1083 /**
Kojto 93:e188a91d3eaa 1084 * @}
Kojto 93:e188a91d3eaa 1085 */
Kojto 93:e188a91d3eaa 1086
Kojto 93:e188a91d3eaa 1087 /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
Kojto 93:e188a91d3eaa 1088 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 93:e188a91d3eaa 1089 * @{
Kojto 93:e188a91d3eaa 1090 */
Kojto 93:e188a91d3eaa 1091
Kojto 93:e188a91d3eaa 1092 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
Kojto 93:e188a91d3eaa 1093 * the selected interrupts.).
Kojto 93:e188a91d3eaa 1094 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 93:e188a91d3eaa 1095 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1096 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
Kojto 93:e188a91d3eaa 1097 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
Kojto 93:e188a91d3eaa 1098 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
Kojto 93:e188a91d3eaa 1099 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
Kojto 93:e188a91d3eaa 1100 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
Kojto 93:e188a91d3eaa 1101 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto 93:e188a91d3eaa 1102 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto 93:e188a91d3eaa 1103 */
Kojto 93:e188a91d3eaa 1104 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Kojto 93:e188a91d3eaa 1105
Kojto 93:e188a91d3eaa 1106 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
Kojto 93:e188a91d3eaa 1107 * the selected interrupts.).
Kojto 93:e188a91d3eaa 1108 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 93:e188a91d3eaa 1109 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1110 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
Kojto 93:e188a91d3eaa 1111 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
Kojto 93:e188a91d3eaa 1112 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
Kojto 93:e188a91d3eaa 1113 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
Kojto 93:e188a91d3eaa 1114 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
Kojto 93:e188a91d3eaa 1115 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto 93:e188a91d3eaa 1116 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto 93:e188a91d3eaa 1117 */
Kojto 93:e188a91d3eaa 1118 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto 93:e188a91d3eaa 1119
Kojto 93:e188a91d3eaa 1120 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
Kojto 93:e188a91d3eaa 1121 * bits to clear the selected interrupt pending bits.
Kojto 93:e188a91d3eaa 1122 * @param __IT__: specifies the interrupt pending bit to clear.
Kojto 93:e188a91d3eaa 1123 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1124 * @arg RCC_IT_LSIRDY: LSI ready interrupt clear
Kojto 93:e188a91d3eaa 1125 * @arg RCC_IT_LSERDY: LSE ready interrupt clear
Kojto 93:e188a91d3eaa 1126 * @arg RCC_IT_HSIRDY: HSI ready interrupt clear
Kojto 93:e188a91d3eaa 1127 * @arg RCC_IT_HSERDY: HSE ready interrupt clear
Kojto 93:e188a91d3eaa 1128 * @arg RCC_IT_PLLRDY: PLL ready interrupt clear
Kojto 93:e188a91d3eaa 1129 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
Kojto 93:e188a91d3eaa 1130 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
Kojto 93:e188a91d3eaa 1131 * @arg RCC_IT_CSS: Clock Security System interrupt clear
Kojto 93:e188a91d3eaa 1132 */
Kojto 93:e188a91d3eaa 1133 #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__))
Kojto 93:e188a91d3eaa 1134
Kojto 93:e188a91d3eaa 1135 /** @brief Check the RCC's interrupt has occurred or not.
Kojto 93:e188a91d3eaa 1136 * @param __IT__: specifies the RCC interrupt source to check.
Kojto 93:e188a91d3eaa 1137 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1138 * @arg RCC_IT_LSIRDY: LSI ready interrupt flag
Kojto 93:e188a91d3eaa 1139 * @arg RCC_IT_LSERDY: LSE ready interrupt flag
Kojto 93:e188a91d3eaa 1140 * @arg RCC_IT_HSIRDY: HSI ready interrupt flag
Kojto 93:e188a91d3eaa 1141 * @arg RCC_IT_HSERDY: HSE ready interrupt flag
Kojto 93:e188a91d3eaa 1142 * @arg RCC_IT_PLLRDY: PLL ready interrupt flag
Kojto 93:e188a91d3eaa 1143 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
Kojto 93:e188a91d3eaa 1144 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
Kojto 93:e188a91d3eaa 1145 * @arg RCC_IT_CSS: Clock Security System interrupt flag
Kojto 93:e188a91d3eaa 1146 * @retval The new state of __IT__ (TRUE or FALSE).
Kojto 93:e188a91d3eaa 1147 */
Kojto 93:e188a91d3eaa 1148 #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
Kojto 93:e188a91d3eaa 1149
Kojto 93:e188a91d3eaa 1150 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto 93:e188a91d3eaa 1151 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Kojto 93:e188a91d3eaa 1152 */
Kojto 93:e188a91d3eaa 1153 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
Kojto 93:e188a91d3eaa 1154
Kojto 93:e188a91d3eaa 1155 /** @brief Check RCC flag is set or not.
Kojto 93:e188a91d3eaa 1156 * @param __FLAG__: specifies the flag to check.
Kojto 93:e188a91d3eaa 1157 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1158 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Kojto 93:e188a91d3eaa 1159 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
Kojto 93:e188a91d3eaa 1160 * @arg RCC_FLAG_PLLRDY: PLL clock ready
Kojto 93:e188a91d3eaa 1161 * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
Kojto 93:e188a91d3eaa 1162 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
Kojto 93:e188a91d3eaa 1163 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
Kojto 93:e188a91d3eaa 1164 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Kojto 93:e188a91d3eaa 1165 * @arg RCC_FLAG_OBLRST: Option Byte Load reset
Kojto 93:e188a91d3eaa 1166 * @arg RCC_FLAG_PINRST: Pin reset
Kojto 93:e188a91d3eaa 1167 * @arg RCC_FLAG_PORRST: POR/PDR reset
Kojto 93:e188a91d3eaa 1168 * @arg RCC_FLAG_SFTRST: Software reset
Kojto 93:e188a91d3eaa 1169 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
Kojto 93:e188a91d3eaa 1170 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
Kojto 93:e188a91d3eaa 1171 * @arg RCC_FLAG_LPWRRST: Low Power reset
Kojto 93:e188a91d3eaa 1172 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 93:e188a91d3eaa 1173 */
Kojto 93:e188a91d3eaa 1174 #define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto 93:e188a91d3eaa 1175 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
Kojto 93:e188a91d3eaa 1176 (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
Kojto 93:e188a91d3eaa 1177 (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
Kojto 93:e188a91d3eaa 1178 RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
Kojto 93:e188a91d3eaa 1179
Kojto 93:e188a91d3eaa 1180
Kojto 93:e188a91d3eaa 1181
Kojto 93:e188a91d3eaa 1182 /**
Kojto 93:e188a91d3eaa 1183 * @}
Kojto 93:e188a91d3eaa 1184 */
Kojto 93:e188a91d3eaa 1185
Kojto 93:e188a91d3eaa 1186 /**
Kojto 93:e188a91d3eaa 1187 * @}
Kojto 93:e188a91d3eaa 1188 */
Kojto 93:e188a91d3eaa 1189
Kojto 93:e188a91d3eaa 1190 /* Include RCC HAL Extension module */
Kojto 93:e188a91d3eaa 1191 #include "stm32f0xx_hal_rcc_ex.h"
Kojto 93:e188a91d3eaa 1192
Kojto 93:e188a91d3eaa 1193 /* Exported functions --------------------------------------------------------*/
Kojto 93:e188a91d3eaa 1194
Kojto 93:e188a91d3eaa 1195 /** @addtogroup RCC_Exported_Functions
Kojto 93:e188a91d3eaa 1196 * @{
Kojto 93:e188a91d3eaa 1197 */
Kojto 93:e188a91d3eaa 1198
Kojto 93:e188a91d3eaa 1199 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 93:e188a91d3eaa 1200 * @{
Kojto 93:e188a91d3eaa 1201 */
Kojto 93:e188a91d3eaa 1202
Kojto 93:e188a91d3eaa 1203 /* Initialization and de-initialization functions ***************************/
Kojto 93:e188a91d3eaa 1204 void HAL_RCC_DeInit(void);
Kojto 93:e188a91d3eaa 1205 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 93:e188a91d3eaa 1206 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 93:e188a91d3eaa 1207
Kojto 93:e188a91d3eaa 1208 /**
Kojto 93:e188a91d3eaa 1209 * @}
Kojto 93:e188a91d3eaa 1210 */
Kojto 93:e188a91d3eaa 1211
Kojto 93:e188a91d3eaa 1212 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 93:e188a91d3eaa 1213 * @{
Kojto 93:e188a91d3eaa 1214 */
Kojto 93:e188a91d3eaa 1215
Kojto 93:e188a91d3eaa 1216 /* Peripheral Control functions *********************************************/
Kojto 93:e188a91d3eaa 1217 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 93:e188a91d3eaa 1218 void HAL_RCC_EnableCSS(void);
Kojto 93:e188a91d3eaa 1219 void HAL_RCC_DisableCSS(void);
Kojto 93:e188a91d3eaa 1220 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 93:e188a91d3eaa 1221 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 93:e188a91d3eaa 1222 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 93:e188a91d3eaa 1223 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 93:e188a91d3eaa 1224 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 93:e188a91d3eaa 1225
Kojto 93:e188a91d3eaa 1226 /* CSS NMI IRQ handler */
Kojto 93:e188a91d3eaa 1227 void HAL_RCC_NMI_IRQHandler(void);
Kojto 93:e188a91d3eaa 1228
Kojto 93:e188a91d3eaa 1229 /* User Callbacks in non blocking mode (IT mode) */
Kojto 93:e188a91d3eaa 1230 void HAL_RCC_CCSCallback(void);
Kojto 93:e188a91d3eaa 1231
Kojto 93:e188a91d3eaa 1232 /**
Kojto 93:e188a91d3eaa 1233 * @}
Kojto 93:e188a91d3eaa 1234 */
Kojto 93:e188a91d3eaa 1235
Kojto 93:e188a91d3eaa 1236 /**
Kojto 93:e188a91d3eaa 1237 * @}
Kojto 93:e188a91d3eaa 1238 */
Kojto 93:e188a91d3eaa 1239
Kojto 93:e188a91d3eaa 1240 /**
Kojto 93:e188a91d3eaa 1241 * @}
Kojto 93:e188a91d3eaa 1242 */
Kojto 93:e188a91d3eaa 1243
Kojto 93:e188a91d3eaa 1244 /**
Kojto 93:e188a91d3eaa 1245 * @}
Kojto 93:e188a91d3eaa 1246 */
Kojto 93:e188a91d3eaa 1247
Kojto 93:e188a91d3eaa 1248 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 1249 }
Kojto 93:e188a91d3eaa 1250 #endif
Kojto 93:e188a91d3eaa 1251
Kojto 93:e188a91d3eaa 1252 #endif /* __STM32F0xx_HAL_RCC_H */
Kojto 93:e188a91d3eaa 1253
Kojto 93:e188a91d3eaa 1254 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 93:e188a91d3eaa 1255