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TARGET_NUCLEO_F070RB/stm32f0xx_hal_dma.h@99:7f6c6de930c0, 2015-05-03 (annotated)
- Committer:
- Mikchel
- Date:
- Sun May 03 16:04:42 2015 +0000
- Revision:
- 99:7f6c6de930c0
- Parent:
- 93:e188a91d3eaa
12
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 93:e188a91d3eaa | 1 | /** |
| Kojto | 93:e188a91d3eaa | 2 | ****************************************************************************** |
| Kojto | 93:e188a91d3eaa | 3 | * @file stm32f0xx_hal_dma.h |
| Kojto | 93:e188a91d3eaa | 4 | * @author MCD Application Team |
| Kojto | 93:e188a91d3eaa | 5 | * @version V1.2.0 |
| Kojto | 93:e188a91d3eaa | 6 | * @date 11-December-2014 |
| Kojto | 93:e188a91d3eaa | 7 | * @brief Header file of DMA HAL module. |
| Kojto | 93:e188a91d3eaa | 8 | ****************************************************************************** |
| Kojto | 93:e188a91d3eaa | 9 | * @attention |
| Kojto | 93:e188a91d3eaa | 10 | * |
| Kojto | 93:e188a91d3eaa | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| Kojto | 93:e188a91d3eaa | 12 | * |
| Kojto | 93:e188a91d3eaa | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 93:e188a91d3eaa | 14 | * are permitted provided that the following conditions are met: |
| Kojto | 93:e188a91d3eaa | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 93:e188a91d3eaa | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 93:e188a91d3eaa | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 93:e188a91d3eaa | 18 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 93:e188a91d3eaa | 19 | * and/or other materials provided with the distribution. |
| Kojto | 93:e188a91d3eaa | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 93:e188a91d3eaa | 21 | * may be used to endorse or promote products derived from this software |
| Kojto | 93:e188a91d3eaa | 22 | * without specific prior written permission. |
| Kojto | 93:e188a91d3eaa | 23 | * |
| Kojto | 93:e188a91d3eaa | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 93:e188a91d3eaa | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 93:e188a91d3eaa | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 93:e188a91d3eaa | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 93:e188a91d3eaa | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 93:e188a91d3eaa | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 93:e188a91d3eaa | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 93:e188a91d3eaa | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 93:e188a91d3eaa | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 93:e188a91d3eaa | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 93:e188a91d3eaa | 34 | * |
| Kojto | 93:e188a91d3eaa | 35 | ****************************************************************************** |
| Kojto | 93:e188a91d3eaa | 36 | */ |
| Kojto | 93:e188a91d3eaa | 37 | |
| Kojto | 93:e188a91d3eaa | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 39 | #ifndef __STM32F0xx_HAL_DMA_H |
| Kojto | 93:e188a91d3eaa | 40 | #define __STM32F0xx_HAL_DMA_H |
| Kojto | 93:e188a91d3eaa | 41 | |
| Kojto | 93:e188a91d3eaa | 42 | #ifdef __cplusplus |
| Kojto | 93:e188a91d3eaa | 43 | extern "C" { |
| Kojto | 93:e188a91d3eaa | 44 | #endif |
| Kojto | 93:e188a91d3eaa | 45 | |
| Kojto | 93:e188a91d3eaa | 46 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 47 | #include "stm32f0xx_hal_def.h" |
| Kojto | 93:e188a91d3eaa | 48 | |
| Kojto | 93:e188a91d3eaa | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
| Kojto | 93:e188a91d3eaa | 50 | * @{ |
| Kojto | 93:e188a91d3eaa | 51 | */ |
| Kojto | 93:e188a91d3eaa | 52 | |
| Kojto | 93:e188a91d3eaa | 53 | /** @addtogroup DMA |
| Kojto | 93:e188a91d3eaa | 54 | * @{ |
| Kojto | 93:e188a91d3eaa | 55 | */ |
| Kojto | 93:e188a91d3eaa | 56 | |
| Kojto | 93:e188a91d3eaa | 57 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 58 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| Kojto | 93:e188a91d3eaa | 59 | * @{ |
| Kojto | 93:e188a91d3eaa | 60 | */ |
| Kojto | 93:e188a91d3eaa | 61 | |
| Kojto | 93:e188a91d3eaa | 62 | /** |
| Kojto | 93:e188a91d3eaa | 63 | * @brief DMA Configuration Structure definition |
| Kojto | 93:e188a91d3eaa | 64 | */ |
| Kojto | 93:e188a91d3eaa | 65 | typedef struct |
| Kojto | 93:e188a91d3eaa | 66 | { |
| Kojto | 93:e188a91d3eaa | 67 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| Kojto | 93:e188a91d3eaa | 68 | from memory to memory or from peripheral to memory. |
| Kojto | 93:e188a91d3eaa | 69 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| Kojto | 93:e188a91d3eaa | 70 | |
| Kojto | 93:e188a91d3eaa | 71 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| Kojto | 93:e188a91d3eaa | 72 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| Kojto | 93:e188a91d3eaa | 73 | |
| Kojto | 93:e188a91d3eaa | 74 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| Kojto | 93:e188a91d3eaa | 75 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| Kojto | 93:e188a91d3eaa | 76 | |
| Kojto | 93:e188a91d3eaa | 77 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| Kojto | 93:e188a91d3eaa | 78 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| Kojto | 93:e188a91d3eaa | 79 | |
| Kojto | 93:e188a91d3eaa | 80 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| Kojto | 93:e188a91d3eaa | 81 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| Kojto | 93:e188a91d3eaa | 82 | |
| Kojto | 93:e188a91d3eaa | 83 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
| Kojto | 93:e188a91d3eaa | 84 | This parameter can be a value of @ref DMA_mode |
| Kojto | 93:e188a91d3eaa | 85 | @note The circular buffer mode cannot be used if the memory-to-memory |
| Kojto | 93:e188a91d3eaa | 86 | data transfer is configured on the selected Channel */ |
| Kojto | 93:e188a91d3eaa | 87 | |
| Kojto | 93:e188a91d3eaa | 88 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| Kojto | 93:e188a91d3eaa | 89 | This parameter can be a value of @ref DMA_Priority_level */ |
| Kojto | 93:e188a91d3eaa | 90 | |
| Kojto | 93:e188a91d3eaa | 91 | } DMA_InitTypeDef; |
| Kojto | 93:e188a91d3eaa | 92 | |
| Kojto | 93:e188a91d3eaa | 93 | /** |
| Kojto | 93:e188a91d3eaa | 94 | * @brief DMA Configuration enumeration values definition |
| Kojto | 93:e188a91d3eaa | 95 | */ |
| Kojto | 93:e188a91d3eaa | 96 | typedef enum |
| Kojto | 93:e188a91d3eaa | 97 | { |
| Kojto | 93:e188a91d3eaa | 98 | DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ |
| Kojto | 93:e188a91d3eaa | 99 | DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ |
| Kojto | 93:e188a91d3eaa | 100 | |
| Kojto | 93:e188a91d3eaa | 101 | } DMA_ControlTypeDef; |
| Kojto | 93:e188a91d3eaa | 102 | |
| Kojto | 93:e188a91d3eaa | 103 | /** |
| Kojto | 93:e188a91d3eaa | 104 | * @brief HAL DMA State structures definition |
| Kojto | 93:e188a91d3eaa | 105 | */ |
| Kojto | 93:e188a91d3eaa | 106 | typedef enum |
| Kojto | 93:e188a91d3eaa | 107 | { |
| Kojto | 93:e188a91d3eaa | 108 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| Kojto | 93:e188a91d3eaa | 109 | HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ |
| Kojto | 93:e188a91d3eaa | 110 | HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ |
| Kojto | 93:e188a91d3eaa | 111 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| Kojto | 93:e188a91d3eaa | 112 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| Kojto | 93:e188a91d3eaa | 113 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
| Kojto | 93:e188a91d3eaa | 114 | |
| Kojto | 93:e188a91d3eaa | 115 | }HAL_DMA_StateTypeDef; |
| Kojto | 93:e188a91d3eaa | 116 | |
| Kojto | 93:e188a91d3eaa | 117 | /** |
| Kojto | 93:e188a91d3eaa | 118 | * @brief HAL DMA Error Code structure definition |
| Kojto | 93:e188a91d3eaa | 119 | */ |
| Kojto | 93:e188a91d3eaa | 120 | typedef enum |
| Kojto | 93:e188a91d3eaa | 121 | { |
| Kojto | 93:e188a91d3eaa | 122 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| Kojto | 93:e188a91d3eaa | 123 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
| Kojto | 93:e188a91d3eaa | 124 | |
| Kojto | 93:e188a91d3eaa | 125 | }HAL_DMA_LevelCompleteTypeDef; |
| Kojto | 93:e188a91d3eaa | 126 | |
| Kojto | 93:e188a91d3eaa | 127 | |
| Kojto | 93:e188a91d3eaa | 128 | /** |
| Kojto | 93:e188a91d3eaa | 129 | * @brief DMA handle Structure definition |
| Kojto | 93:e188a91d3eaa | 130 | */ |
| Kojto | 93:e188a91d3eaa | 131 | typedef struct __DMA_HandleTypeDef |
| Kojto | 93:e188a91d3eaa | 132 | { |
| Kojto | 93:e188a91d3eaa | 133 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
| Kojto | 93:e188a91d3eaa | 134 | |
| Kojto | 93:e188a91d3eaa | 135 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| Kojto | 93:e188a91d3eaa | 136 | |
| Kojto | 93:e188a91d3eaa | 137 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| Kojto | 93:e188a91d3eaa | 138 | |
| Kojto | 93:e188a91d3eaa | 139 | HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| Kojto | 93:e188a91d3eaa | 140 | |
| Kojto | 93:e188a91d3eaa | 141 | void *Parent; /*!< Parent object state */ |
| Kojto | 93:e188a91d3eaa | 142 | |
| Kojto | 93:e188a91d3eaa | 143 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| Kojto | 93:e188a91d3eaa | 144 | |
| Kojto | 93:e188a91d3eaa | 145 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| Kojto | 93:e188a91d3eaa | 146 | |
| Kojto | 93:e188a91d3eaa | 147 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| Kojto | 93:e188a91d3eaa | 148 | |
| Kojto | 93:e188a91d3eaa | 149 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| Kojto | 93:e188a91d3eaa | 150 | |
| Kojto | 93:e188a91d3eaa | 151 | } DMA_HandleTypeDef; |
| Kojto | 93:e188a91d3eaa | 152 | /** |
| Kojto | 93:e188a91d3eaa | 153 | * @} |
| Kojto | 93:e188a91d3eaa | 154 | */ |
| Kojto | 93:e188a91d3eaa | 155 | |
| Kojto | 93:e188a91d3eaa | 156 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 157 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| Kojto | 93:e188a91d3eaa | 158 | * @{ |
| Kojto | 93:e188a91d3eaa | 159 | */ |
| Kojto | 93:e188a91d3eaa | 160 | |
| Kojto | 93:e188a91d3eaa | 161 | /** @defgroup DMA_Error_Code DMA Error Code |
| Kojto | 93:e188a91d3eaa | 162 | * @{ |
| Kojto | 93:e188a91d3eaa | 163 | */ |
| Kojto | 93:e188a91d3eaa | 164 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| Kojto | 93:e188a91d3eaa | 165 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
| Kojto | 93:e188a91d3eaa | 166 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| Kojto | 93:e188a91d3eaa | 167 | /** |
| Kojto | 93:e188a91d3eaa | 168 | * @} |
| Kojto | 93:e188a91d3eaa | 169 | */ |
| Kojto | 93:e188a91d3eaa | 170 | |
| Kojto | 93:e188a91d3eaa | 171 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| Kojto | 93:e188a91d3eaa | 172 | * @{ |
| Kojto | 93:e188a91d3eaa | 173 | */ |
| Kojto | 93:e188a91d3eaa | 174 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| Kojto | 93:e188a91d3eaa | 175 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
| Kojto | 93:e188a91d3eaa | 176 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ |
| Kojto | 93:e188a91d3eaa | 177 | |
| Kojto | 93:e188a91d3eaa | 178 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| Kojto | 93:e188a91d3eaa | 179 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| Kojto | 93:e188a91d3eaa | 180 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| Kojto | 93:e188a91d3eaa | 181 | /** |
| Kojto | 93:e188a91d3eaa | 182 | * @} |
| Kojto | 93:e188a91d3eaa | 183 | */ |
| Kojto | 93:e188a91d3eaa | 184 | |
| Kojto | 93:e188a91d3eaa | 185 | /** @defgroup DMA_Data_buffer_size DMA Data buffer size |
| Kojto | 93:e188a91d3eaa | 186 | * @{ |
| Kojto | 93:e188a91d3eaa | 187 | */ |
| Kojto | 93:e188a91d3eaa | 188 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| Kojto | 93:e188a91d3eaa | 189 | /** |
| Kojto | 93:e188a91d3eaa | 190 | * @} |
| Kojto | 93:e188a91d3eaa | 191 | */ |
| Kojto | 93:e188a91d3eaa | 192 | |
| Kojto | 93:e188a91d3eaa | 193 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| Kojto | 93:e188a91d3eaa | 194 | * @{ |
| Kojto | 93:e188a91d3eaa | 195 | */ |
| Kojto | 93:e188a91d3eaa | 196 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
| Kojto | 93:e188a91d3eaa | 197 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ |
| Kojto | 93:e188a91d3eaa | 198 | |
| Kojto | 93:e188a91d3eaa | 199 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| Kojto | 93:e188a91d3eaa | 200 | ((STATE) == DMA_PINC_DISABLE)) |
| Kojto | 93:e188a91d3eaa | 201 | /** |
| Kojto | 93:e188a91d3eaa | 202 | * @} |
| Kojto | 93:e188a91d3eaa | 203 | */ |
| Kojto | 93:e188a91d3eaa | 204 | |
| Kojto | 93:e188a91d3eaa | 205 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| Kojto | 93:e188a91d3eaa | 206 | * @{ |
| Kojto | 93:e188a91d3eaa | 207 | */ |
| Kojto | 93:e188a91d3eaa | 208 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
| Kojto | 93:e188a91d3eaa | 209 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ |
| Kojto | 93:e188a91d3eaa | 210 | |
| Kojto | 93:e188a91d3eaa | 211 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| Kojto | 93:e188a91d3eaa | 212 | ((STATE) == DMA_MINC_DISABLE)) |
| Kojto | 93:e188a91d3eaa | 213 | /** |
| Kojto | 93:e188a91d3eaa | 214 | * @} |
| Kojto | 93:e188a91d3eaa | 215 | */ |
| Kojto | 93:e188a91d3eaa | 216 | |
| Kojto | 93:e188a91d3eaa | 217 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| Kojto | 93:e188a91d3eaa | 218 | * @{ |
| Kojto | 93:e188a91d3eaa | 219 | */ |
| Kojto | 93:e188a91d3eaa | 220 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ |
| Kojto | 93:e188a91d3eaa | 221 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
| Kojto | 93:e188a91d3eaa | 222 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
| Kojto | 93:e188a91d3eaa | 223 | |
| Kojto | 93:e188a91d3eaa | 224 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| Kojto | 93:e188a91d3eaa | 225 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| Kojto | 93:e188a91d3eaa | 226 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| Kojto | 93:e188a91d3eaa | 227 | /** |
| Kojto | 93:e188a91d3eaa | 228 | * @} |
| Kojto | 93:e188a91d3eaa | 229 | */ |
| Kojto | 93:e188a91d3eaa | 230 | |
| Kojto | 93:e188a91d3eaa | 231 | |
| Kojto | 93:e188a91d3eaa | 232 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| Kojto | 93:e188a91d3eaa | 233 | * @{ |
| Kojto | 93:e188a91d3eaa | 234 | */ |
| Kojto | 93:e188a91d3eaa | 235 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ |
| Kojto | 93:e188a91d3eaa | 236 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
| Kojto | 93:e188a91d3eaa | 237 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
| Kojto | 93:e188a91d3eaa | 238 | |
| Kojto | 93:e188a91d3eaa | 239 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| Kojto | 93:e188a91d3eaa | 240 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| Kojto | 93:e188a91d3eaa | 241 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| Kojto | 93:e188a91d3eaa | 242 | /** |
| Kojto | 93:e188a91d3eaa | 243 | * @} |
| Kojto | 93:e188a91d3eaa | 244 | */ |
| Kojto | 93:e188a91d3eaa | 245 | |
| Kojto | 93:e188a91d3eaa | 246 | /** @defgroup DMA_mode DMA mode |
| Kojto | 93:e188a91d3eaa | 247 | * @{ |
| Kojto | 93:e188a91d3eaa | 248 | */ |
| Kojto | 93:e188a91d3eaa | 249 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ |
| Kojto | 93:e188a91d3eaa | 250 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
| Kojto | 93:e188a91d3eaa | 251 | |
| Kojto | 93:e188a91d3eaa | 252 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| Kojto | 93:e188a91d3eaa | 253 | ((MODE) == DMA_CIRCULAR)) |
| Kojto | 93:e188a91d3eaa | 254 | /** |
| Kojto | 93:e188a91d3eaa | 255 | * @} |
| Kojto | 93:e188a91d3eaa | 256 | */ |
| Kojto | 93:e188a91d3eaa | 257 | |
| Kojto | 93:e188a91d3eaa | 258 | /** @defgroup DMA_Priority_level DMA Priority level |
| Kojto | 93:e188a91d3eaa | 259 | * @{ |
| Kojto | 93:e188a91d3eaa | 260 | */ |
| Kojto | 93:e188a91d3eaa | 261 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ |
| Kojto | 93:e188a91d3eaa | 262 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
| Kojto | 93:e188a91d3eaa | 263 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
| Kojto | 93:e188a91d3eaa | 264 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
| Kojto | 93:e188a91d3eaa | 265 | |
| Kojto | 93:e188a91d3eaa | 266 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| Kojto | 93:e188a91d3eaa | 267 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| Kojto | 93:e188a91d3eaa | 268 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| Kojto | 93:e188a91d3eaa | 269 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| Kojto | 93:e188a91d3eaa | 270 | /** |
| Kojto | 93:e188a91d3eaa | 271 | * @} |
| Kojto | 93:e188a91d3eaa | 272 | */ |
| Kojto | 93:e188a91d3eaa | 273 | |
| Kojto | 93:e188a91d3eaa | 274 | |
| Kojto | 93:e188a91d3eaa | 275 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| Kojto | 93:e188a91d3eaa | 276 | * @{ |
| Kojto | 93:e188a91d3eaa | 277 | */ |
| Kojto | 93:e188a91d3eaa | 278 | |
| Kojto | 93:e188a91d3eaa | 279 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| Kojto | 93:e188a91d3eaa | 280 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| Kojto | 93:e188a91d3eaa | 281 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| Kojto | 93:e188a91d3eaa | 282 | |
| Kojto | 93:e188a91d3eaa | 283 | /** |
| Kojto | 93:e188a91d3eaa | 284 | * @} |
| Kojto | 93:e188a91d3eaa | 285 | */ |
| Kojto | 93:e188a91d3eaa | 286 | |
| Kojto | 93:e188a91d3eaa | 287 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| Kojto | 93:e188a91d3eaa | 288 | * @{ |
| Kojto | 93:e188a91d3eaa | 289 | */ |
| Kojto | 93:e188a91d3eaa | 290 | |
| Kojto | 93:e188a91d3eaa | 291 | #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */ |
| Kojto | 93:e188a91d3eaa | 292 | #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */ |
| Kojto | 93:e188a91d3eaa | 293 | #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */ |
| Kojto | 93:e188a91d3eaa | 294 | #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */ |
| Kojto | 93:e188a91d3eaa | 295 | #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */ |
| Kojto | 93:e188a91d3eaa | 296 | #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */ |
| Kojto | 93:e188a91d3eaa | 297 | #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */ |
| Kojto | 93:e188a91d3eaa | 298 | #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */ |
| Kojto | 93:e188a91d3eaa | 299 | #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */ |
| Kojto | 93:e188a91d3eaa | 300 | #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */ |
| Kojto | 93:e188a91d3eaa | 301 | #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */ |
| Kojto | 93:e188a91d3eaa | 302 | #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */ |
| Kojto | 93:e188a91d3eaa | 303 | #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */ |
| Kojto | 93:e188a91d3eaa | 304 | #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */ |
| Kojto | 93:e188a91d3eaa | 305 | #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */ |
| Kojto | 93:e188a91d3eaa | 306 | #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */ |
| Kojto | 93:e188a91d3eaa | 307 | #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */ |
| Kojto | 93:e188a91d3eaa | 308 | #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */ |
| Kojto | 93:e188a91d3eaa | 309 | #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */ |
| Kojto | 93:e188a91d3eaa | 310 | #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */ |
| Kojto | 93:e188a91d3eaa | 311 | #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */ |
| Kojto | 93:e188a91d3eaa | 312 | #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */ |
| Kojto | 93:e188a91d3eaa | 313 | #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */ |
| Kojto | 93:e188a91d3eaa | 314 | #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */ |
| Kojto | 93:e188a91d3eaa | 315 | #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */ |
| Kojto | 93:e188a91d3eaa | 316 | #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */ |
| Kojto | 93:e188a91d3eaa | 317 | #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */ |
| Kojto | 93:e188a91d3eaa | 318 | #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */ |
| Kojto | 93:e188a91d3eaa | 319 | |
| Kojto | 93:e188a91d3eaa | 320 | |
| Kojto | 93:e188a91d3eaa | 321 | /** |
| Kojto | 93:e188a91d3eaa | 322 | * @} |
| Kojto | 93:e188a91d3eaa | 323 | */ |
| Kojto | 93:e188a91d3eaa | 324 | |
| Kojto | 93:e188a91d3eaa | 325 | /** |
| Kojto | 93:e188a91d3eaa | 326 | * @} |
| Kojto | 93:e188a91d3eaa | 327 | */ |
| Kojto | 93:e188a91d3eaa | 328 | |
| Kojto | 93:e188a91d3eaa | 329 | /* Exported macros -----------------------------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 330 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
| Kojto | 93:e188a91d3eaa | 331 | * @{ |
| Kojto | 93:e188a91d3eaa | 332 | */ |
| Kojto | 93:e188a91d3eaa | 333 | |
| Kojto | 93:e188a91d3eaa | 334 | /** @brief Reset DMA handle state |
| Kojto | 93:e188a91d3eaa | 335 | * @param __HANDLE__: DMA handle. |
| Kojto | 93:e188a91d3eaa | 336 | * @retval None |
| Kojto | 93:e188a91d3eaa | 337 | */ |
| Kojto | 93:e188a91d3eaa | 338 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| Kojto | 93:e188a91d3eaa | 339 | |
| Kojto | 93:e188a91d3eaa | 340 | /** |
| Kojto | 93:e188a91d3eaa | 341 | * @brief Enable the specified DMA Channel. |
| Kojto | 93:e188a91d3eaa | 342 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 343 | * @retval None. |
| Kojto | 93:e188a91d3eaa | 344 | */ |
| Kojto | 93:e188a91d3eaa | 345 | #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
| Kojto | 93:e188a91d3eaa | 346 | |
| Kojto | 93:e188a91d3eaa | 347 | /** |
| Kojto | 93:e188a91d3eaa | 348 | * @brief Disable the specified DMA Channel. |
| Kojto | 93:e188a91d3eaa | 349 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 350 | * @retval None. |
| Kojto | 93:e188a91d3eaa | 351 | */ |
| Kojto | 93:e188a91d3eaa | 352 | #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
| Kojto | 93:e188a91d3eaa | 353 | |
| Kojto | 93:e188a91d3eaa | 354 | |
| Kojto | 93:e188a91d3eaa | 355 | /* Interrupt & Flag management */ |
| Kojto | 93:e188a91d3eaa | 356 | |
| Kojto | 93:e188a91d3eaa | 357 | /** |
| Kojto | 93:e188a91d3eaa | 358 | * @brief Enables the specified DMA Channel interrupts. |
| Kojto | 93:e188a91d3eaa | 359 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 360 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| Kojto | 93:e188a91d3eaa | 361 | * This parameter can be any combination of the following values: |
| Kojto | 93:e188a91d3eaa | 362 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| Kojto | 93:e188a91d3eaa | 363 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| Kojto | 93:e188a91d3eaa | 364 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| Kojto | 93:e188a91d3eaa | 365 | * @retval None |
| Kojto | 93:e188a91d3eaa | 366 | */ |
| Kojto | 93:e188a91d3eaa | 367 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) |
| Kojto | 93:e188a91d3eaa | 368 | |
| Kojto | 93:e188a91d3eaa | 369 | /** |
| Kojto | 93:e188a91d3eaa | 370 | * @brief Disables the specified DMA Channel interrupts. |
| Kojto | 93:e188a91d3eaa | 371 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 372 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| Kojto | 93:e188a91d3eaa | 373 | * This parameter can be any combination of the following values: |
| Kojto | 93:e188a91d3eaa | 374 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| Kojto | 93:e188a91d3eaa | 375 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| Kojto | 93:e188a91d3eaa | 376 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| Kojto | 93:e188a91d3eaa | 377 | * @retval None |
| Kojto | 93:e188a91d3eaa | 378 | */ |
| Kojto | 93:e188a91d3eaa | 379 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) |
| Kojto | 93:e188a91d3eaa | 380 | |
| Kojto | 93:e188a91d3eaa | 381 | /** |
| Kojto | 93:e188a91d3eaa | 382 | * @brief Checks whether the specified DMA Channel interrupt has occurred or not. |
| Kojto | 93:e188a91d3eaa | 383 | * @param __HANDLE__: DMA handle |
| Kojto | 93:e188a91d3eaa | 384 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| Kojto | 93:e188a91d3eaa | 385 | * This parameter can be one of the following values: |
| Kojto | 93:e188a91d3eaa | 386 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| Kojto | 93:e188a91d3eaa | 387 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| Kojto | 93:e188a91d3eaa | 388 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| Kojto | 93:e188a91d3eaa | 389 | * @retval The state of DMA_IT (SET or RESET). |
| Kojto | 93:e188a91d3eaa | 390 | */ |
| Kojto | 93:e188a91d3eaa | 391 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| Kojto | 93:e188a91d3eaa | 392 | |
| Kojto | 93:e188a91d3eaa | 393 | /** |
| Kojto | 93:e188a91d3eaa | 394 | * @} |
| Kojto | 93:e188a91d3eaa | 395 | */ |
| Kojto | 93:e188a91d3eaa | 396 | |
| Kojto | 93:e188a91d3eaa | 397 | /* Include DMA HAL Extension module */ |
| Kojto | 93:e188a91d3eaa | 398 | #include "stm32f0xx_hal_dma_ex.h" |
| Kojto | 93:e188a91d3eaa | 399 | |
| Kojto | 93:e188a91d3eaa | 400 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 93:e188a91d3eaa | 401 | /** @addtogroup DMA_Exported_Functions DMA Exported Functions |
| Kojto | 93:e188a91d3eaa | 402 | * @{ |
| Kojto | 93:e188a91d3eaa | 403 | */ |
| Kojto | 93:e188a91d3eaa | 404 | /** @addtogroup DMA_Exported_Functions_Group1 |
| Kojto | 93:e188a91d3eaa | 405 | * @brief Initialization and de-initialization functions |
| Kojto | 93:e188a91d3eaa | 406 | * @{ |
| Kojto | 93:e188a91d3eaa | 407 | */ |
| Kojto | 93:e188a91d3eaa | 408 | /* Initialization and de-initialization functions *****************************/ |
| Kojto | 93:e188a91d3eaa | 409 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| Kojto | 93:e188a91d3eaa | 410 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
| Kojto | 93:e188a91d3eaa | 411 | /** |
| Kojto | 93:e188a91d3eaa | 412 | * @} |
| Kojto | 93:e188a91d3eaa | 413 | */ |
| Kojto | 93:e188a91d3eaa | 414 | |
| Kojto | 93:e188a91d3eaa | 415 | /** @addtogroup DMA_Exported_Functions_Group2 |
| Kojto | 93:e188a91d3eaa | 416 | * @brief I/O operation functions |
| Kojto | 93:e188a91d3eaa | 417 | * @{ |
| Kojto | 93:e188a91d3eaa | 418 | */ |
| Kojto | 93:e188a91d3eaa | 419 | /* IO operation functions *****************************************************/ |
| Kojto | 93:e188a91d3eaa | 420 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| Kojto | 93:e188a91d3eaa | 421 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| Kojto | 93:e188a91d3eaa | 422 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| Kojto | 93:e188a91d3eaa | 423 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| Kojto | 93:e188a91d3eaa | 424 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| Kojto | 93:e188a91d3eaa | 425 | /** |
| Kojto | 93:e188a91d3eaa | 426 | * @} |
| Kojto | 93:e188a91d3eaa | 427 | */ |
| Kojto | 93:e188a91d3eaa | 428 | |
| Kojto | 93:e188a91d3eaa | 429 | /* Peripheral State and Error functions ***************************************/ |
| Kojto | 93:e188a91d3eaa | 430 | /** @addtogroup DMA_Exported_Functions_Group3 |
| Kojto | 93:e188a91d3eaa | 431 | * @brief Peripheral State functions |
| Kojto | 93:e188a91d3eaa | 432 | * @{ |
| Kojto | 93:e188a91d3eaa | 433 | */ |
| Kojto | 93:e188a91d3eaa | 434 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| Kojto | 93:e188a91d3eaa | 435 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| Kojto | 93:e188a91d3eaa | 436 | /** |
| Kojto | 93:e188a91d3eaa | 437 | * @} |
| Kojto | 93:e188a91d3eaa | 438 | */ |
| Kojto | 93:e188a91d3eaa | 439 | |
| Kojto | 93:e188a91d3eaa | 440 | /** |
| Kojto | 93:e188a91d3eaa | 441 | * @} |
| Kojto | 93:e188a91d3eaa | 442 | */ |
| Kojto | 93:e188a91d3eaa | 443 | |
| Kojto | 93:e188a91d3eaa | 444 | /** |
| Kojto | 93:e188a91d3eaa | 445 | * @} |
| Kojto | 93:e188a91d3eaa | 446 | */ |
| Kojto | 93:e188a91d3eaa | 447 | |
| Kojto | 93:e188a91d3eaa | 448 | /** |
| Kojto | 93:e188a91d3eaa | 449 | * @} |
| Kojto | 93:e188a91d3eaa | 450 | */ |
| Kojto | 93:e188a91d3eaa | 451 | |
| Kojto | 93:e188a91d3eaa | 452 | #ifdef __cplusplus |
| Kojto | 93:e188a91d3eaa | 453 | } |
| Kojto | 93:e188a91d3eaa | 454 | #endif |
| Kojto | 93:e188a91d3eaa | 455 | |
| Kojto | 93:e188a91d3eaa | 456 | #endif /* __STM32F0xx_HAL_DMA_H */ |
| Kojto | 93:e188a91d3eaa | 457 | |
| Kojto | 93:e188a91d3eaa | 458 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| Kojto | 93:e188a91d3eaa | 459 |