SD card player with variable cotoff frequency lowpass and highpass IIR filter. SD カードの *.wav ファイルのオーディオ信号を,遮断周波数可変 IIR 低域通過および高域通過フィルタを通して,ボードに搭載されているCODEC で出力する.このプログラムについては,CQ出版社インターフェース誌 2018年8月号で解説している.
Dependencies: F746_GUI F746_SAI_IO FrequencyResponseDrawer SD_PlayerSkeleton
mbed_src_STM32F7/targets/cmsis/core_sc000.h@11:399670d24ed9, 2017-04-10 (annotated)
- Committer:
- MikamiUitOpen
- Date:
- Mon Apr 10 01:44:22 2017 +0000
- Revision:
- 11:399670d24ed9
- Parent:
- 2:dcaee06f6ccb
12
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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MikamiUitOpen | 2:dcaee06f6ccb | 1 | /**************************************************************************//** |
MikamiUitOpen | 2:dcaee06f6ccb | 2 | * @file core_sc000.h |
MikamiUitOpen | 2:dcaee06f6ccb | 3 | * @brief CMSIS SC000 Core Peripheral Access Layer Header File |
MikamiUitOpen | 2:dcaee06f6ccb | 4 | * @version V4.10 |
MikamiUitOpen | 2:dcaee06f6ccb | 5 | * @date 18. March 2015 |
MikamiUitOpen | 2:dcaee06f6ccb | 6 | * |
MikamiUitOpen | 2:dcaee06f6ccb | 7 | * @note |
MikamiUitOpen | 2:dcaee06f6ccb | 8 | * |
MikamiUitOpen | 2:dcaee06f6ccb | 9 | ******************************************************************************/ |
MikamiUitOpen | 2:dcaee06f6ccb | 10 | /* Copyright (c) 2009 - 2015 ARM LIMITED |
MikamiUitOpen | 2:dcaee06f6ccb | 11 | |
MikamiUitOpen | 2:dcaee06f6ccb | 12 | All rights reserved. |
MikamiUitOpen | 2:dcaee06f6ccb | 13 | Redistribution and use in source and binary forms, with or without |
MikamiUitOpen | 2:dcaee06f6ccb | 14 | modification, are permitted provided that the following conditions are met: |
MikamiUitOpen | 2:dcaee06f6ccb | 15 | - Redistributions of source code must retain the above copyright |
MikamiUitOpen | 2:dcaee06f6ccb | 16 | notice, this list of conditions and the following disclaimer. |
MikamiUitOpen | 2:dcaee06f6ccb | 17 | - Redistributions in binary form must reproduce the above copyright |
MikamiUitOpen | 2:dcaee06f6ccb | 18 | notice, this list of conditions and the following disclaimer in the |
MikamiUitOpen | 2:dcaee06f6ccb | 19 | documentation and/or other materials provided with the distribution. |
MikamiUitOpen | 2:dcaee06f6ccb | 20 | - Neither the name of ARM nor the names of its contributors may be used |
MikamiUitOpen | 2:dcaee06f6ccb | 21 | to endorse or promote products derived from this software without |
MikamiUitOpen | 2:dcaee06f6ccb | 22 | specific prior written permission. |
MikamiUitOpen | 2:dcaee06f6ccb | 23 | * |
MikamiUitOpen | 2:dcaee06f6ccb | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
MikamiUitOpen | 2:dcaee06f6ccb | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
MikamiUitOpen | 2:dcaee06f6ccb | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
MikamiUitOpen | 2:dcaee06f6ccb | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
MikamiUitOpen | 2:dcaee06f6ccb | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
MikamiUitOpen | 2:dcaee06f6ccb | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
MikamiUitOpen | 2:dcaee06f6ccb | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
MikamiUitOpen | 2:dcaee06f6ccb | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
MikamiUitOpen | 2:dcaee06f6ccb | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
MikamiUitOpen | 2:dcaee06f6ccb | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
MikamiUitOpen | 2:dcaee06f6ccb | 34 | POSSIBILITY OF SUCH DAMAGE. |
MikamiUitOpen | 2:dcaee06f6ccb | 35 | ---------------------------------------------------------------------------*/ |
MikamiUitOpen | 2:dcaee06f6ccb | 36 | |
MikamiUitOpen | 2:dcaee06f6ccb | 37 | |
MikamiUitOpen | 2:dcaee06f6ccb | 38 | #if defined ( __ICCARM__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
MikamiUitOpen | 2:dcaee06f6ccb | 40 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 41 | |
MikamiUitOpen | 2:dcaee06f6ccb | 42 | #ifndef __CORE_SC000_H_GENERIC |
MikamiUitOpen | 2:dcaee06f6ccb | 43 | #define __CORE_SC000_H_GENERIC |
MikamiUitOpen | 2:dcaee06f6ccb | 44 | |
MikamiUitOpen | 2:dcaee06f6ccb | 45 | #ifdef __cplusplus |
MikamiUitOpen | 2:dcaee06f6ccb | 46 | extern "C" { |
MikamiUitOpen | 2:dcaee06f6ccb | 47 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 48 | |
MikamiUitOpen | 2:dcaee06f6ccb | 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
MikamiUitOpen | 2:dcaee06f6ccb | 50 | CMSIS violates the following MISRA-C:2004 rules: |
MikamiUitOpen | 2:dcaee06f6ccb | 51 | |
MikamiUitOpen | 2:dcaee06f6ccb | 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
MikamiUitOpen | 2:dcaee06f6ccb | 53 | Function definitions in header files are used to allow 'inlining'. |
MikamiUitOpen | 2:dcaee06f6ccb | 54 | |
MikamiUitOpen | 2:dcaee06f6ccb | 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
MikamiUitOpen | 2:dcaee06f6ccb | 56 | Unions are used for effective representation of core registers. |
MikamiUitOpen | 2:dcaee06f6ccb | 57 | |
MikamiUitOpen | 2:dcaee06f6ccb | 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
MikamiUitOpen | 2:dcaee06f6ccb | 59 | Function-like macros are used to allow more efficient code. |
MikamiUitOpen | 2:dcaee06f6ccb | 60 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 61 | |
MikamiUitOpen | 2:dcaee06f6ccb | 62 | |
MikamiUitOpen | 2:dcaee06f6ccb | 63 | /******************************************************************************* |
MikamiUitOpen | 2:dcaee06f6ccb | 64 | * CMSIS definitions |
MikamiUitOpen | 2:dcaee06f6ccb | 65 | ******************************************************************************/ |
MikamiUitOpen | 2:dcaee06f6ccb | 66 | /** \ingroup SC000 |
MikamiUitOpen | 2:dcaee06f6ccb | 67 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 68 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 69 | |
MikamiUitOpen | 2:dcaee06f6ccb | 70 | /* CMSIS SC000 definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 71 | #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ |
MikamiUitOpen | 2:dcaee06f6ccb | 72 | #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ |
MikamiUitOpen | 2:dcaee06f6ccb | 73 | #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ |
MikamiUitOpen | 2:dcaee06f6ccb | 74 | __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
MikamiUitOpen | 2:dcaee06f6ccb | 75 | |
MikamiUitOpen | 2:dcaee06f6ccb | 76 | #define __CORTEX_SC (000) /*!< Cortex secure core */ |
MikamiUitOpen | 2:dcaee06f6ccb | 77 | |
MikamiUitOpen | 2:dcaee06f6ccb | 78 | |
MikamiUitOpen | 2:dcaee06f6ccb | 79 | #if defined ( __CC_ARM ) |
MikamiUitOpen | 2:dcaee06f6ccb | 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 82 | #define __STATIC_INLINE static __inline |
MikamiUitOpen | 2:dcaee06f6ccb | 83 | |
MikamiUitOpen | 2:dcaee06f6ccb | 84 | #elif defined ( __GNUC__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 87 | #define __STATIC_INLINE static inline |
MikamiUitOpen | 2:dcaee06f6ccb | 88 | |
MikamiUitOpen | 2:dcaee06f6ccb | 89 | #elif defined ( __ICCARM__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
MikamiUitOpen | 2:dcaee06f6ccb | 92 | #define __STATIC_INLINE static inline |
MikamiUitOpen | 2:dcaee06f6ccb | 93 | |
MikamiUitOpen | 2:dcaee06f6ccb | 94 | #elif defined ( __TMS470__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 96 | #define __STATIC_INLINE static inline |
MikamiUitOpen | 2:dcaee06f6ccb | 97 | |
MikamiUitOpen | 2:dcaee06f6ccb | 98 | #elif defined ( __TASKING__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 101 | #define __STATIC_INLINE static inline |
MikamiUitOpen | 2:dcaee06f6ccb | 102 | |
MikamiUitOpen | 2:dcaee06f6ccb | 103 | #elif defined ( __CSMC__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 104 | #define __packed |
MikamiUitOpen | 2:dcaee06f6ccb | 105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ |
MikamiUitOpen | 2:dcaee06f6ccb | 107 | #define __STATIC_INLINE static inline |
MikamiUitOpen | 2:dcaee06f6ccb | 108 | |
MikamiUitOpen | 2:dcaee06f6ccb | 109 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 110 | |
MikamiUitOpen | 2:dcaee06f6ccb | 111 | /** __FPU_USED indicates whether an FPU is used or not. |
MikamiUitOpen | 2:dcaee06f6ccb | 112 | This core does not support an FPU at all |
MikamiUitOpen | 2:dcaee06f6ccb | 113 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 114 | #define __FPU_USED 0 |
MikamiUitOpen | 2:dcaee06f6ccb | 115 | |
MikamiUitOpen | 2:dcaee06f6ccb | 116 | #if defined ( __CC_ARM ) |
MikamiUitOpen | 2:dcaee06f6ccb | 117 | #if defined __TARGET_FPU_VFP |
MikamiUitOpen | 2:dcaee06f6ccb | 118 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
MikamiUitOpen | 2:dcaee06f6ccb | 119 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 120 | |
MikamiUitOpen | 2:dcaee06f6ccb | 121 | #elif defined ( __GNUC__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 122 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
MikamiUitOpen | 2:dcaee06f6ccb | 123 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
MikamiUitOpen | 2:dcaee06f6ccb | 124 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 125 | |
MikamiUitOpen | 2:dcaee06f6ccb | 126 | #elif defined ( __ICCARM__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 127 | #if defined __ARMVFP__ |
MikamiUitOpen | 2:dcaee06f6ccb | 128 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
MikamiUitOpen | 2:dcaee06f6ccb | 129 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 130 | |
MikamiUitOpen | 2:dcaee06f6ccb | 131 | #elif defined ( __TMS470__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 132 | #if defined __TI__VFP_SUPPORT____ |
MikamiUitOpen | 2:dcaee06f6ccb | 133 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
MikamiUitOpen | 2:dcaee06f6ccb | 134 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 135 | |
MikamiUitOpen | 2:dcaee06f6ccb | 136 | #elif defined ( __TASKING__ ) |
MikamiUitOpen | 2:dcaee06f6ccb | 137 | #if defined __FPU_VFP__ |
MikamiUitOpen | 2:dcaee06f6ccb | 138 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
MikamiUitOpen | 2:dcaee06f6ccb | 139 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 140 | |
MikamiUitOpen | 2:dcaee06f6ccb | 141 | #elif defined ( __CSMC__ ) /* Cosmic */ |
MikamiUitOpen | 2:dcaee06f6ccb | 142 | #if ( __CSMC__ & 0x400) // FPU present for parser |
MikamiUitOpen | 2:dcaee06f6ccb | 143 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
MikamiUitOpen | 2:dcaee06f6ccb | 144 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 145 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 146 | |
MikamiUitOpen | 2:dcaee06f6ccb | 147 | #include <stdint.h> /* standard types definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 148 | #include <core_cmInstr.h> /* Core Instruction Access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 149 | #include <core_cmFunc.h> /* Core Function Access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 150 | |
MikamiUitOpen | 2:dcaee06f6ccb | 151 | #ifdef __cplusplus |
MikamiUitOpen | 2:dcaee06f6ccb | 152 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 153 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 154 | |
MikamiUitOpen | 2:dcaee06f6ccb | 155 | #endif /* __CORE_SC000_H_GENERIC */ |
MikamiUitOpen | 2:dcaee06f6ccb | 156 | |
MikamiUitOpen | 2:dcaee06f6ccb | 157 | #ifndef __CMSIS_GENERIC |
MikamiUitOpen | 2:dcaee06f6ccb | 158 | |
MikamiUitOpen | 2:dcaee06f6ccb | 159 | #ifndef __CORE_SC000_H_DEPENDANT |
MikamiUitOpen | 2:dcaee06f6ccb | 160 | #define __CORE_SC000_H_DEPENDANT |
MikamiUitOpen | 2:dcaee06f6ccb | 161 | |
MikamiUitOpen | 2:dcaee06f6ccb | 162 | #ifdef __cplusplus |
MikamiUitOpen | 2:dcaee06f6ccb | 163 | extern "C" { |
MikamiUitOpen | 2:dcaee06f6ccb | 164 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 165 | |
MikamiUitOpen | 2:dcaee06f6ccb | 166 | /* check device defines and use defaults */ |
MikamiUitOpen | 2:dcaee06f6ccb | 167 | #if defined __CHECK_DEVICE_DEFINES |
MikamiUitOpen | 2:dcaee06f6ccb | 168 | #ifndef __SC000_REV |
MikamiUitOpen | 2:dcaee06f6ccb | 169 | #define __SC000_REV 0x0000 |
MikamiUitOpen | 2:dcaee06f6ccb | 170 | #warning "__SC000_REV not defined in device header file; using default!" |
MikamiUitOpen | 2:dcaee06f6ccb | 171 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 172 | |
MikamiUitOpen | 2:dcaee06f6ccb | 173 | #ifndef __MPU_PRESENT |
MikamiUitOpen | 2:dcaee06f6ccb | 174 | #define __MPU_PRESENT 0 |
MikamiUitOpen | 2:dcaee06f6ccb | 175 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
MikamiUitOpen | 2:dcaee06f6ccb | 176 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 177 | |
MikamiUitOpen | 2:dcaee06f6ccb | 178 | #ifndef __NVIC_PRIO_BITS |
MikamiUitOpen | 2:dcaee06f6ccb | 179 | #define __NVIC_PRIO_BITS 2 |
MikamiUitOpen | 2:dcaee06f6ccb | 180 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
MikamiUitOpen | 2:dcaee06f6ccb | 181 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 182 | |
MikamiUitOpen | 2:dcaee06f6ccb | 183 | #ifndef __Vendor_SysTickConfig |
MikamiUitOpen | 2:dcaee06f6ccb | 184 | #define __Vendor_SysTickConfig 0 |
MikamiUitOpen | 2:dcaee06f6ccb | 185 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
MikamiUitOpen | 2:dcaee06f6ccb | 186 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 187 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 188 | |
MikamiUitOpen | 2:dcaee06f6ccb | 189 | /* IO definitions (access restrictions to peripheral registers) */ |
MikamiUitOpen | 2:dcaee06f6ccb | 190 | /** |
MikamiUitOpen | 2:dcaee06f6ccb | 191 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
MikamiUitOpen | 2:dcaee06f6ccb | 192 | |
MikamiUitOpen | 2:dcaee06f6ccb | 193 | <strong>IO Type Qualifiers</strong> are used |
MikamiUitOpen | 2:dcaee06f6ccb | 194 | \li to specify the access to peripheral variables. |
MikamiUitOpen | 2:dcaee06f6ccb | 195 | \li for automatic generation of peripheral register debug information. |
MikamiUitOpen | 2:dcaee06f6ccb | 196 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 197 | #ifdef __cplusplus |
MikamiUitOpen | 2:dcaee06f6ccb | 198 | #define __I volatile /*!< Defines 'read only' permissions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 199 | #else |
MikamiUitOpen | 2:dcaee06f6ccb | 200 | #define __I volatile const /*!< Defines 'read only' permissions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 201 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 202 | #define __O volatile /*!< Defines 'write only' permissions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 203 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 204 | |
MikamiUitOpen | 2:dcaee06f6ccb | 205 | /*@} end of group SC000 */ |
MikamiUitOpen | 2:dcaee06f6ccb | 206 | |
MikamiUitOpen | 2:dcaee06f6ccb | 207 | |
MikamiUitOpen | 2:dcaee06f6ccb | 208 | |
MikamiUitOpen | 2:dcaee06f6ccb | 209 | /******************************************************************************* |
MikamiUitOpen | 2:dcaee06f6ccb | 210 | * Register Abstraction |
MikamiUitOpen | 2:dcaee06f6ccb | 211 | Core Register contain: |
MikamiUitOpen | 2:dcaee06f6ccb | 212 | - Core Register |
MikamiUitOpen | 2:dcaee06f6ccb | 213 | - Core NVIC Register |
MikamiUitOpen | 2:dcaee06f6ccb | 214 | - Core SCB Register |
MikamiUitOpen | 2:dcaee06f6ccb | 215 | - Core SysTick Register |
MikamiUitOpen | 2:dcaee06f6ccb | 216 | - Core MPU Register |
MikamiUitOpen | 2:dcaee06f6ccb | 217 | ******************************************************************************/ |
MikamiUitOpen | 2:dcaee06f6ccb | 218 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
MikamiUitOpen | 2:dcaee06f6ccb | 219 | \brief Type definitions and defines for Cortex-M processor based devices. |
MikamiUitOpen | 2:dcaee06f6ccb | 220 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 221 | |
MikamiUitOpen | 2:dcaee06f6ccb | 222 | /** \ingroup CMSIS_core_register |
MikamiUitOpen | 2:dcaee06f6ccb | 223 | \defgroup CMSIS_CORE Status and Control Registers |
MikamiUitOpen | 2:dcaee06f6ccb | 224 | \brief Core Register type definitions. |
MikamiUitOpen | 2:dcaee06f6ccb | 225 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 226 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 227 | |
MikamiUitOpen | 2:dcaee06f6ccb | 228 | /** \brief Union type to access the Application Program Status Register (APSR). |
MikamiUitOpen | 2:dcaee06f6ccb | 229 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 230 | typedef union |
MikamiUitOpen | 2:dcaee06f6ccb | 231 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 232 | struct |
MikamiUitOpen | 2:dcaee06f6ccb | 233 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 234 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
MikamiUitOpen | 2:dcaee06f6ccb | 235 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
MikamiUitOpen | 2:dcaee06f6ccb | 236 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
MikamiUitOpen | 2:dcaee06f6ccb | 237 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
MikamiUitOpen | 2:dcaee06f6ccb | 238 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
MikamiUitOpen | 2:dcaee06f6ccb | 239 | } b; /*!< Structure used for bit access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 240 | uint32_t w; /*!< Type used for word access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 241 | } APSR_Type; |
MikamiUitOpen | 2:dcaee06f6ccb | 242 | |
MikamiUitOpen | 2:dcaee06f6ccb | 243 | /* APSR Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 244 | #define APSR_N_Pos 31 /*!< APSR: N Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 245 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 246 | |
MikamiUitOpen | 2:dcaee06f6ccb | 247 | #define APSR_Z_Pos 30 /*!< APSR: Z Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 248 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 249 | |
MikamiUitOpen | 2:dcaee06f6ccb | 250 | #define APSR_C_Pos 29 /*!< APSR: C Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 251 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 252 | |
MikamiUitOpen | 2:dcaee06f6ccb | 253 | #define APSR_V_Pos 28 /*!< APSR: V Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 254 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 255 | |
MikamiUitOpen | 2:dcaee06f6ccb | 256 | |
MikamiUitOpen | 2:dcaee06f6ccb | 257 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
MikamiUitOpen | 2:dcaee06f6ccb | 258 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 259 | typedef union |
MikamiUitOpen | 2:dcaee06f6ccb | 260 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 261 | struct |
MikamiUitOpen | 2:dcaee06f6ccb | 262 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 263 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
MikamiUitOpen | 2:dcaee06f6ccb | 264 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
MikamiUitOpen | 2:dcaee06f6ccb | 265 | } b; /*!< Structure used for bit access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 266 | uint32_t w; /*!< Type used for word access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 267 | } IPSR_Type; |
MikamiUitOpen | 2:dcaee06f6ccb | 268 | |
MikamiUitOpen | 2:dcaee06f6ccb | 269 | /* IPSR Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 270 | #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 271 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 272 | |
MikamiUitOpen | 2:dcaee06f6ccb | 273 | |
MikamiUitOpen | 2:dcaee06f6ccb | 274 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
MikamiUitOpen | 2:dcaee06f6ccb | 275 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 276 | typedef union |
MikamiUitOpen | 2:dcaee06f6ccb | 277 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 278 | struct |
MikamiUitOpen | 2:dcaee06f6ccb | 279 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 280 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
MikamiUitOpen | 2:dcaee06f6ccb | 281 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
MikamiUitOpen | 2:dcaee06f6ccb | 282 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
MikamiUitOpen | 2:dcaee06f6ccb | 283 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
MikamiUitOpen | 2:dcaee06f6ccb | 284 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
MikamiUitOpen | 2:dcaee06f6ccb | 285 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
MikamiUitOpen | 2:dcaee06f6ccb | 286 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
MikamiUitOpen | 2:dcaee06f6ccb | 287 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
MikamiUitOpen | 2:dcaee06f6ccb | 288 | } b; /*!< Structure used for bit access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 289 | uint32_t w; /*!< Type used for word access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 290 | } xPSR_Type; |
MikamiUitOpen | 2:dcaee06f6ccb | 291 | |
MikamiUitOpen | 2:dcaee06f6ccb | 292 | /* xPSR Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 293 | #define xPSR_N_Pos 31 /*!< xPSR: N Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 294 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 295 | |
MikamiUitOpen | 2:dcaee06f6ccb | 296 | #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 297 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 298 | |
MikamiUitOpen | 2:dcaee06f6ccb | 299 | #define xPSR_C_Pos 29 /*!< xPSR: C Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 300 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 301 | |
MikamiUitOpen | 2:dcaee06f6ccb | 302 | #define xPSR_V_Pos 28 /*!< xPSR: V Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 303 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 304 | |
MikamiUitOpen | 2:dcaee06f6ccb | 305 | #define xPSR_T_Pos 24 /*!< xPSR: T Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 306 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 307 | |
MikamiUitOpen | 2:dcaee06f6ccb | 308 | #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 309 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 310 | |
MikamiUitOpen | 2:dcaee06f6ccb | 311 | |
MikamiUitOpen | 2:dcaee06f6ccb | 312 | /** \brief Union type to access the Control Registers (CONTROL). |
MikamiUitOpen | 2:dcaee06f6ccb | 313 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 314 | typedef union |
MikamiUitOpen | 2:dcaee06f6ccb | 315 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 316 | struct |
MikamiUitOpen | 2:dcaee06f6ccb | 317 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 318 | uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
MikamiUitOpen | 2:dcaee06f6ccb | 319 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
MikamiUitOpen | 2:dcaee06f6ccb | 320 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
MikamiUitOpen | 2:dcaee06f6ccb | 321 | } b; /*!< Structure used for bit access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 322 | uint32_t w; /*!< Type used for word access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 323 | } CONTROL_Type; |
MikamiUitOpen | 2:dcaee06f6ccb | 324 | |
MikamiUitOpen | 2:dcaee06f6ccb | 325 | /* CONTROL Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 326 | #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 327 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 328 | |
MikamiUitOpen | 2:dcaee06f6ccb | 329 | /*@} end of group CMSIS_CORE */ |
MikamiUitOpen | 2:dcaee06f6ccb | 330 | |
MikamiUitOpen | 2:dcaee06f6ccb | 331 | |
MikamiUitOpen | 2:dcaee06f6ccb | 332 | /** \ingroup CMSIS_core_register |
MikamiUitOpen | 2:dcaee06f6ccb | 333 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
MikamiUitOpen | 2:dcaee06f6ccb | 334 | \brief Type definitions for the NVIC Registers |
MikamiUitOpen | 2:dcaee06f6ccb | 335 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 336 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 337 | |
MikamiUitOpen | 2:dcaee06f6ccb | 338 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
MikamiUitOpen | 2:dcaee06f6ccb | 339 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 340 | typedef struct |
MikamiUitOpen | 2:dcaee06f6ccb | 341 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 342 | __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 343 | uint32_t RESERVED0[31]; |
MikamiUitOpen | 2:dcaee06f6ccb | 344 | __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 345 | uint32_t RSERVED1[31]; |
MikamiUitOpen | 2:dcaee06f6ccb | 346 | __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 347 | uint32_t RESERVED2[31]; |
MikamiUitOpen | 2:dcaee06f6ccb | 348 | __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 349 | uint32_t RESERVED3[31]; |
MikamiUitOpen | 2:dcaee06f6ccb | 350 | uint32_t RESERVED4[64]; |
MikamiUitOpen | 2:dcaee06f6ccb | 351 | __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 352 | } NVIC_Type; |
MikamiUitOpen | 2:dcaee06f6ccb | 353 | |
MikamiUitOpen | 2:dcaee06f6ccb | 354 | /*@} end of group CMSIS_NVIC */ |
MikamiUitOpen | 2:dcaee06f6ccb | 355 | |
MikamiUitOpen | 2:dcaee06f6ccb | 356 | |
MikamiUitOpen | 2:dcaee06f6ccb | 357 | /** \ingroup CMSIS_core_register |
MikamiUitOpen | 2:dcaee06f6ccb | 358 | \defgroup CMSIS_SCB System Control Block (SCB) |
MikamiUitOpen | 2:dcaee06f6ccb | 359 | \brief Type definitions for the System Control Block Registers |
MikamiUitOpen | 2:dcaee06f6ccb | 360 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 361 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 362 | |
MikamiUitOpen | 2:dcaee06f6ccb | 363 | /** \brief Structure type to access the System Control Block (SCB). |
MikamiUitOpen | 2:dcaee06f6ccb | 364 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 365 | typedef struct |
MikamiUitOpen | 2:dcaee06f6ccb | 366 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 367 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 368 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 369 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 370 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 371 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 372 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 373 | uint32_t RESERVED0[1]; |
MikamiUitOpen | 2:dcaee06f6ccb | 374 | __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
MikamiUitOpen | 2:dcaee06f6ccb | 375 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 376 | uint32_t RESERVED1[154]; |
MikamiUitOpen | 2:dcaee06f6ccb | 377 | __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 378 | } SCB_Type; |
MikamiUitOpen | 2:dcaee06f6ccb | 379 | |
MikamiUitOpen | 2:dcaee06f6ccb | 380 | /* SCB CPUID Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 381 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 382 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 383 | |
MikamiUitOpen | 2:dcaee06f6ccb | 384 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 385 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 386 | |
MikamiUitOpen | 2:dcaee06f6ccb | 387 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 388 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 389 | |
MikamiUitOpen | 2:dcaee06f6ccb | 390 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 391 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 392 | |
MikamiUitOpen | 2:dcaee06f6ccb | 393 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 394 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 395 | |
MikamiUitOpen | 2:dcaee06f6ccb | 396 | /* SCB Interrupt Control State Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 397 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 398 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 399 | |
MikamiUitOpen | 2:dcaee06f6ccb | 400 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 401 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 402 | |
MikamiUitOpen | 2:dcaee06f6ccb | 403 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 404 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 405 | |
MikamiUitOpen | 2:dcaee06f6ccb | 406 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 407 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 408 | |
MikamiUitOpen | 2:dcaee06f6ccb | 409 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 410 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 411 | |
MikamiUitOpen | 2:dcaee06f6ccb | 412 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 413 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 414 | |
MikamiUitOpen | 2:dcaee06f6ccb | 415 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 416 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 417 | |
MikamiUitOpen | 2:dcaee06f6ccb | 418 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 419 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 420 | |
MikamiUitOpen | 2:dcaee06f6ccb | 421 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 422 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 423 | |
MikamiUitOpen | 2:dcaee06f6ccb | 424 | /* SCB Interrupt Control State Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 425 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 426 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 427 | |
MikamiUitOpen | 2:dcaee06f6ccb | 428 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 429 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 430 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 431 | |
MikamiUitOpen | 2:dcaee06f6ccb | 432 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 433 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 434 | |
MikamiUitOpen | 2:dcaee06f6ccb | 435 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 436 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 437 | |
MikamiUitOpen | 2:dcaee06f6ccb | 438 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 439 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 440 | |
MikamiUitOpen | 2:dcaee06f6ccb | 441 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 442 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 443 | |
MikamiUitOpen | 2:dcaee06f6ccb | 444 | /* SCB System Control Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 445 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 446 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 447 | |
MikamiUitOpen | 2:dcaee06f6ccb | 448 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 449 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 450 | |
MikamiUitOpen | 2:dcaee06f6ccb | 451 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 452 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 453 | |
MikamiUitOpen | 2:dcaee06f6ccb | 454 | /* SCB Configuration Control Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 455 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 456 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 457 | |
MikamiUitOpen | 2:dcaee06f6ccb | 458 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 459 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 460 | |
MikamiUitOpen | 2:dcaee06f6ccb | 461 | /* SCB System Handler Control and State Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 462 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 463 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 464 | |
MikamiUitOpen | 2:dcaee06f6ccb | 465 | /*@} end of group CMSIS_SCB */ |
MikamiUitOpen | 2:dcaee06f6ccb | 466 | |
MikamiUitOpen | 2:dcaee06f6ccb | 467 | |
MikamiUitOpen | 2:dcaee06f6ccb | 468 | /** \ingroup CMSIS_core_register |
MikamiUitOpen | 2:dcaee06f6ccb | 469 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
MikamiUitOpen | 2:dcaee06f6ccb | 470 | \brief Type definitions for the System Control and ID Register not in the SCB |
MikamiUitOpen | 2:dcaee06f6ccb | 471 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 472 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 473 | |
MikamiUitOpen | 2:dcaee06f6ccb | 474 | /** \brief Structure type to access the System Control and ID Register not in the SCB. |
MikamiUitOpen | 2:dcaee06f6ccb | 475 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 476 | typedef struct |
MikamiUitOpen | 2:dcaee06f6ccb | 477 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 478 | uint32_t RESERVED0[2]; |
MikamiUitOpen | 2:dcaee06f6ccb | 479 | __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 480 | } SCnSCB_Type; |
MikamiUitOpen | 2:dcaee06f6ccb | 481 | |
MikamiUitOpen | 2:dcaee06f6ccb | 482 | /* Auxiliary Control Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 483 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 484 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 485 | |
MikamiUitOpen | 2:dcaee06f6ccb | 486 | /*@} end of group CMSIS_SCnotSCB */ |
MikamiUitOpen | 2:dcaee06f6ccb | 487 | |
MikamiUitOpen | 2:dcaee06f6ccb | 488 | |
MikamiUitOpen | 2:dcaee06f6ccb | 489 | /** \ingroup CMSIS_core_register |
MikamiUitOpen | 2:dcaee06f6ccb | 490 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
MikamiUitOpen | 2:dcaee06f6ccb | 491 | \brief Type definitions for the System Timer Registers. |
MikamiUitOpen | 2:dcaee06f6ccb | 492 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 493 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 494 | |
MikamiUitOpen | 2:dcaee06f6ccb | 495 | /** \brief Structure type to access the System Timer (SysTick). |
MikamiUitOpen | 2:dcaee06f6ccb | 496 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 497 | typedef struct |
MikamiUitOpen | 2:dcaee06f6ccb | 498 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 499 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 500 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 501 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 502 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 503 | } SysTick_Type; |
MikamiUitOpen | 2:dcaee06f6ccb | 504 | |
MikamiUitOpen | 2:dcaee06f6ccb | 505 | /* SysTick Control / Status Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 506 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 507 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 508 | |
MikamiUitOpen | 2:dcaee06f6ccb | 509 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 510 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 511 | |
MikamiUitOpen | 2:dcaee06f6ccb | 512 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 513 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 514 | |
MikamiUitOpen | 2:dcaee06f6ccb | 515 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 516 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 517 | |
MikamiUitOpen | 2:dcaee06f6ccb | 518 | /* SysTick Reload Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 519 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 520 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 521 | |
MikamiUitOpen | 2:dcaee06f6ccb | 522 | /* SysTick Current Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 523 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 524 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 525 | |
MikamiUitOpen | 2:dcaee06f6ccb | 526 | /* SysTick Calibration Register Definitions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 527 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 528 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 529 | |
MikamiUitOpen | 2:dcaee06f6ccb | 530 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 531 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 532 | |
MikamiUitOpen | 2:dcaee06f6ccb | 533 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 534 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 535 | |
MikamiUitOpen | 2:dcaee06f6ccb | 536 | /*@} end of group CMSIS_SysTick */ |
MikamiUitOpen | 2:dcaee06f6ccb | 537 | |
MikamiUitOpen | 2:dcaee06f6ccb | 538 | #if (__MPU_PRESENT == 1) |
MikamiUitOpen | 2:dcaee06f6ccb | 539 | /** \ingroup CMSIS_core_register |
MikamiUitOpen | 2:dcaee06f6ccb | 540 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
MikamiUitOpen | 2:dcaee06f6ccb | 541 | \brief Type definitions for the Memory Protection Unit (MPU) |
MikamiUitOpen | 2:dcaee06f6ccb | 542 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 543 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 544 | |
MikamiUitOpen | 2:dcaee06f6ccb | 545 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
MikamiUitOpen | 2:dcaee06f6ccb | 546 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 547 | typedef struct |
MikamiUitOpen | 2:dcaee06f6ccb | 548 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 549 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 550 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 551 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 552 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 553 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 554 | } MPU_Type; |
MikamiUitOpen | 2:dcaee06f6ccb | 555 | |
MikamiUitOpen | 2:dcaee06f6ccb | 556 | /* MPU Type Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 557 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 558 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 559 | |
MikamiUitOpen | 2:dcaee06f6ccb | 560 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 561 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 562 | |
MikamiUitOpen | 2:dcaee06f6ccb | 563 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 564 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 565 | |
MikamiUitOpen | 2:dcaee06f6ccb | 566 | /* MPU Control Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 567 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 568 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 569 | |
MikamiUitOpen | 2:dcaee06f6ccb | 570 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 571 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 572 | |
MikamiUitOpen | 2:dcaee06f6ccb | 573 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 574 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 575 | |
MikamiUitOpen | 2:dcaee06f6ccb | 576 | /* MPU Region Number Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 577 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 578 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 579 | |
MikamiUitOpen | 2:dcaee06f6ccb | 580 | /* MPU Region Base Address Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 581 | #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 582 | #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 583 | |
MikamiUitOpen | 2:dcaee06f6ccb | 584 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 585 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 586 | |
MikamiUitOpen | 2:dcaee06f6ccb | 587 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 588 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 589 | |
MikamiUitOpen | 2:dcaee06f6ccb | 590 | /* MPU Region Attribute and Size Register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 591 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 592 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 593 | |
MikamiUitOpen | 2:dcaee06f6ccb | 594 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 595 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 596 | |
MikamiUitOpen | 2:dcaee06f6ccb | 597 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 598 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 599 | |
MikamiUitOpen | 2:dcaee06f6ccb | 600 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 601 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 602 | |
MikamiUitOpen | 2:dcaee06f6ccb | 603 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 604 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 605 | |
MikamiUitOpen | 2:dcaee06f6ccb | 606 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 607 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 608 | |
MikamiUitOpen | 2:dcaee06f6ccb | 609 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 610 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 611 | |
MikamiUitOpen | 2:dcaee06f6ccb | 612 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 613 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 614 | |
MikamiUitOpen | 2:dcaee06f6ccb | 615 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 616 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 617 | |
MikamiUitOpen | 2:dcaee06f6ccb | 618 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
MikamiUitOpen | 2:dcaee06f6ccb | 619 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
MikamiUitOpen | 2:dcaee06f6ccb | 620 | |
MikamiUitOpen | 2:dcaee06f6ccb | 621 | /*@} end of group CMSIS_MPU */ |
MikamiUitOpen | 2:dcaee06f6ccb | 622 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 623 | |
MikamiUitOpen | 2:dcaee06f6ccb | 624 | |
MikamiUitOpen | 2:dcaee06f6ccb | 625 | /** \ingroup CMSIS_core_register |
MikamiUitOpen | 2:dcaee06f6ccb | 626 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
MikamiUitOpen | 2:dcaee06f6ccb | 627 | \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) |
MikamiUitOpen | 2:dcaee06f6ccb | 628 | are only accessible over DAP and not via processor. Therefore |
MikamiUitOpen | 2:dcaee06f6ccb | 629 | they are not covered by the Cortex-M0 header file. |
MikamiUitOpen | 2:dcaee06f6ccb | 630 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 631 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 632 | /*@} end of group CMSIS_CoreDebug */ |
MikamiUitOpen | 2:dcaee06f6ccb | 633 | |
MikamiUitOpen | 2:dcaee06f6ccb | 634 | |
MikamiUitOpen | 2:dcaee06f6ccb | 635 | /** \ingroup CMSIS_core_register |
MikamiUitOpen | 2:dcaee06f6ccb | 636 | \defgroup CMSIS_core_base Core Definitions |
MikamiUitOpen | 2:dcaee06f6ccb | 637 | \brief Definitions for base addresses, unions, and structures. |
MikamiUitOpen | 2:dcaee06f6ccb | 638 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 639 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 640 | |
MikamiUitOpen | 2:dcaee06f6ccb | 641 | /* Memory mapping of SC000 Hardware */ |
MikamiUitOpen | 2:dcaee06f6ccb | 642 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
MikamiUitOpen | 2:dcaee06f6ccb | 643 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
MikamiUitOpen | 2:dcaee06f6ccb | 644 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
MikamiUitOpen | 2:dcaee06f6ccb | 645 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
MikamiUitOpen | 2:dcaee06f6ccb | 646 | |
MikamiUitOpen | 2:dcaee06f6ccb | 647 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
MikamiUitOpen | 2:dcaee06f6ccb | 648 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
MikamiUitOpen | 2:dcaee06f6ccb | 649 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
MikamiUitOpen | 2:dcaee06f6ccb | 650 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
MikamiUitOpen | 2:dcaee06f6ccb | 651 | |
MikamiUitOpen | 2:dcaee06f6ccb | 652 | #if (__MPU_PRESENT == 1) |
MikamiUitOpen | 2:dcaee06f6ccb | 653 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
MikamiUitOpen | 2:dcaee06f6ccb | 654 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
MikamiUitOpen | 2:dcaee06f6ccb | 655 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 656 | |
MikamiUitOpen | 2:dcaee06f6ccb | 657 | /*@} */ |
MikamiUitOpen | 2:dcaee06f6ccb | 658 | |
MikamiUitOpen | 2:dcaee06f6ccb | 659 | |
MikamiUitOpen | 2:dcaee06f6ccb | 660 | |
MikamiUitOpen | 2:dcaee06f6ccb | 661 | /******************************************************************************* |
MikamiUitOpen | 2:dcaee06f6ccb | 662 | * Hardware Abstraction Layer |
MikamiUitOpen | 2:dcaee06f6ccb | 663 | Core Function Interface contains: |
MikamiUitOpen | 2:dcaee06f6ccb | 664 | - Core NVIC Functions |
MikamiUitOpen | 2:dcaee06f6ccb | 665 | - Core SysTick Functions |
MikamiUitOpen | 2:dcaee06f6ccb | 666 | - Core Register Access Functions |
MikamiUitOpen | 2:dcaee06f6ccb | 667 | ******************************************************************************/ |
MikamiUitOpen | 2:dcaee06f6ccb | 668 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
MikamiUitOpen | 2:dcaee06f6ccb | 669 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 670 | |
MikamiUitOpen | 2:dcaee06f6ccb | 671 | |
MikamiUitOpen | 2:dcaee06f6ccb | 672 | |
MikamiUitOpen | 2:dcaee06f6ccb | 673 | /* ########################## NVIC functions #################################### */ |
MikamiUitOpen | 2:dcaee06f6ccb | 674 | /** \ingroup CMSIS_Core_FunctionInterface |
MikamiUitOpen | 2:dcaee06f6ccb | 675 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
MikamiUitOpen | 2:dcaee06f6ccb | 676 | \brief Functions that manage interrupts and exceptions via the NVIC. |
MikamiUitOpen | 2:dcaee06f6ccb | 677 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 678 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 679 | |
MikamiUitOpen | 2:dcaee06f6ccb | 680 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
MikamiUitOpen | 2:dcaee06f6ccb | 681 | /* The following MACROS handle generation of the register offset and byte masks */ |
MikamiUitOpen | 2:dcaee06f6ccb | 682 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
MikamiUitOpen | 2:dcaee06f6ccb | 683 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
MikamiUitOpen | 2:dcaee06f6ccb | 684 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
MikamiUitOpen | 2:dcaee06f6ccb | 685 | |
MikamiUitOpen | 2:dcaee06f6ccb | 686 | |
MikamiUitOpen | 2:dcaee06f6ccb | 687 | /** \brief Enable External Interrupt |
MikamiUitOpen | 2:dcaee06f6ccb | 688 | |
MikamiUitOpen | 2:dcaee06f6ccb | 689 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
MikamiUitOpen | 2:dcaee06f6ccb | 690 | |
MikamiUitOpen | 2:dcaee06f6ccb | 691 | \param [in] IRQn External interrupt number. Value cannot be negative. |
MikamiUitOpen | 2:dcaee06f6ccb | 692 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 693 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
MikamiUitOpen | 2:dcaee06f6ccb | 694 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 695 | NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
MikamiUitOpen | 2:dcaee06f6ccb | 696 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 697 | |
MikamiUitOpen | 2:dcaee06f6ccb | 698 | |
MikamiUitOpen | 2:dcaee06f6ccb | 699 | /** \brief Disable External Interrupt |
MikamiUitOpen | 2:dcaee06f6ccb | 700 | |
MikamiUitOpen | 2:dcaee06f6ccb | 701 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
MikamiUitOpen | 2:dcaee06f6ccb | 702 | |
MikamiUitOpen | 2:dcaee06f6ccb | 703 | \param [in] IRQn External interrupt number. Value cannot be negative. |
MikamiUitOpen | 2:dcaee06f6ccb | 704 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 705 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
MikamiUitOpen | 2:dcaee06f6ccb | 706 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 707 | NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
MikamiUitOpen | 2:dcaee06f6ccb | 708 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 709 | |
MikamiUitOpen | 2:dcaee06f6ccb | 710 | |
MikamiUitOpen | 2:dcaee06f6ccb | 711 | /** \brief Get Pending Interrupt |
MikamiUitOpen | 2:dcaee06f6ccb | 712 | |
MikamiUitOpen | 2:dcaee06f6ccb | 713 | The function reads the pending register in the NVIC and returns the pending bit |
MikamiUitOpen | 2:dcaee06f6ccb | 714 | for the specified interrupt. |
MikamiUitOpen | 2:dcaee06f6ccb | 715 | |
MikamiUitOpen | 2:dcaee06f6ccb | 716 | \param [in] IRQn Interrupt number. |
MikamiUitOpen | 2:dcaee06f6ccb | 717 | |
MikamiUitOpen | 2:dcaee06f6ccb | 718 | \return 0 Interrupt status is not pending. |
MikamiUitOpen | 2:dcaee06f6ccb | 719 | \return 1 Interrupt status is pending. |
MikamiUitOpen | 2:dcaee06f6ccb | 720 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 721 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
MikamiUitOpen | 2:dcaee06f6ccb | 722 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 723 | return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
MikamiUitOpen | 2:dcaee06f6ccb | 724 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 725 | |
MikamiUitOpen | 2:dcaee06f6ccb | 726 | |
MikamiUitOpen | 2:dcaee06f6ccb | 727 | /** \brief Set Pending Interrupt |
MikamiUitOpen | 2:dcaee06f6ccb | 728 | |
MikamiUitOpen | 2:dcaee06f6ccb | 729 | The function sets the pending bit of an external interrupt. |
MikamiUitOpen | 2:dcaee06f6ccb | 730 | |
MikamiUitOpen | 2:dcaee06f6ccb | 731 | \param [in] IRQn Interrupt number. Value cannot be negative. |
MikamiUitOpen | 2:dcaee06f6ccb | 732 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 733 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
MikamiUitOpen | 2:dcaee06f6ccb | 734 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 735 | NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
MikamiUitOpen | 2:dcaee06f6ccb | 736 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 737 | |
MikamiUitOpen | 2:dcaee06f6ccb | 738 | |
MikamiUitOpen | 2:dcaee06f6ccb | 739 | /** \brief Clear Pending Interrupt |
MikamiUitOpen | 2:dcaee06f6ccb | 740 | |
MikamiUitOpen | 2:dcaee06f6ccb | 741 | The function clears the pending bit of an external interrupt. |
MikamiUitOpen | 2:dcaee06f6ccb | 742 | |
MikamiUitOpen | 2:dcaee06f6ccb | 743 | \param [in] IRQn External interrupt number. Value cannot be negative. |
MikamiUitOpen | 2:dcaee06f6ccb | 744 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 745 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
MikamiUitOpen | 2:dcaee06f6ccb | 746 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 747 | NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
MikamiUitOpen | 2:dcaee06f6ccb | 748 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 749 | |
MikamiUitOpen | 2:dcaee06f6ccb | 750 | |
MikamiUitOpen | 2:dcaee06f6ccb | 751 | /** \brief Set Interrupt Priority |
MikamiUitOpen | 2:dcaee06f6ccb | 752 | |
MikamiUitOpen | 2:dcaee06f6ccb | 753 | The function sets the priority of an interrupt. |
MikamiUitOpen | 2:dcaee06f6ccb | 754 | |
MikamiUitOpen | 2:dcaee06f6ccb | 755 | \note The priority cannot be set for every core interrupt. |
MikamiUitOpen | 2:dcaee06f6ccb | 756 | |
MikamiUitOpen | 2:dcaee06f6ccb | 757 | \param [in] IRQn Interrupt number. |
MikamiUitOpen | 2:dcaee06f6ccb | 758 | \param [in] priority Priority to set. |
MikamiUitOpen | 2:dcaee06f6ccb | 759 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 760 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
MikamiUitOpen | 2:dcaee06f6ccb | 761 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 762 | if((int32_t)(IRQn) < 0) { |
MikamiUitOpen | 2:dcaee06f6ccb | 763 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
MikamiUitOpen | 2:dcaee06f6ccb | 764 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
MikamiUitOpen | 2:dcaee06f6ccb | 765 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 766 | else { |
MikamiUitOpen | 2:dcaee06f6ccb | 767 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
MikamiUitOpen | 2:dcaee06f6ccb | 768 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
MikamiUitOpen | 2:dcaee06f6ccb | 769 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 770 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 771 | |
MikamiUitOpen | 2:dcaee06f6ccb | 772 | |
MikamiUitOpen | 2:dcaee06f6ccb | 773 | /** \brief Get Interrupt Priority |
MikamiUitOpen | 2:dcaee06f6ccb | 774 | |
MikamiUitOpen | 2:dcaee06f6ccb | 775 | The function reads the priority of an interrupt. The interrupt |
MikamiUitOpen | 2:dcaee06f6ccb | 776 | number can be positive to specify an external (device specific) |
MikamiUitOpen | 2:dcaee06f6ccb | 777 | interrupt, or negative to specify an internal (core) interrupt. |
MikamiUitOpen | 2:dcaee06f6ccb | 778 | |
MikamiUitOpen | 2:dcaee06f6ccb | 779 | |
MikamiUitOpen | 2:dcaee06f6ccb | 780 | \param [in] IRQn Interrupt number. |
MikamiUitOpen | 2:dcaee06f6ccb | 781 | \return Interrupt Priority. Value is aligned automatically to the implemented |
MikamiUitOpen | 2:dcaee06f6ccb | 782 | priority bits of the microcontroller. |
MikamiUitOpen | 2:dcaee06f6ccb | 783 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 784 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
MikamiUitOpen | 2:dcaee06f6ccb | 785 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 786 | |
MikamiUitOpen | 2:dcaee06f6ccb | 787 | if((int32_t)(IRQn) < 0) { |
MikamiUitOpen | 2:dcaee06f6ccb | 788 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
MikamiUitOpen | 2:dcaee06f6ccb | 789 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 790 | else { |
MikamiUitOpen | 2:dcaee06f6ccb | 791 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
MikamiUitOpen | 2:dcaee06f6ccb | 792 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 793 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 794 | |
MikamiUitOpen | 2:dcaee06f6ccb | 795 | |
MikamiUitOpen | 2:dcaee06f6ccb | 796 | /** \brief System Reset |
MikamiUitOpen | 2:dcaee06f6ccb | 797 | |
MikamiUitOpen | 2:dcaee06f6ccb | 798 | The function initiates a system reset request to reset the MCU. |
MikamiUitOpen | 2:dcaee06f6ccb | 799 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 800 | __STATIC_INLINE void NVIC_SystemReset(void) |
MikamiUitOpen | 2:dcaee06f6ccb | 801 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 802 | __DSB(); /* Ensure all outstanding memory accesses included |
MikamiUitOpen | 2:dcaee06f6ccb | 803 | buffered write are completed before reset */ |
MikamiUitOpen | 2:dcaee06f6ccb | 804 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
MikamiUitOpen | 2:dcaee06f6ccb | 805 | SCB_AIRCR_SYSRESETREQ_Msk); |
MikamiUitOpen | 2:dcaee06f6ccb | 806 | __DSB(); /* Ensure completion of memory access */ |
MikamiUitOpen | 2:dcaee06f6ccb | 807 | while(1) { __NOP(); } /* wait until reset */ |
MikamiUitOpen | 2:dcaee06f6ccb | 808 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 809 | |
MikamiUitOpen | 2:dcaee06f6ccb | 810 | /*@} end of CMSIS_Core_NVICFunctions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 811 | |
MikamiUitOpen | 2:dcaee06f6ccb | 812 | |
MikamiUitOpen | 2:dcaee06f6ccb | 813 | |
MikamiUitOpen | 2:dcaee06f6ccb | 814 | /* ################################## SysTick function ############################################ */ |
MikamiUitOpen | 2:dcaee06f6ccb | 815 | /** \ingroup CMSIS_Core_FunctionInterface |
MikamiUitOpen | 2:dcaee06f6ccb | 816 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
MikamiUitOpen | 2:dcaee06f6ccb | 817 | \brief Functions that configure the System. |
MikamiUitOpen | 2:dcaee06f6ccb | 818 | @{ |
MikamiUitOpen | 2:dcaee06f6ccb | 819 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 820 | |
MikamiUitOpen | 2:dcaee06f6ccb | 821 | #if (__Vendor_SysTickConfig == 0) |
MikamiUitOpen | 2:dcaee06f6ccb | 822 | |
MikamiUitOpen | 2:dcaee06f6ccb | 823 | /** \brief System Tick Configuration |
MikamiUitOpen | 2:dcaee06f6ccb | 824 | |
MikamiUitOpen | 2:dcaee06f6ccb | 825 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
MikamiUitOpen | 2:dcaee06f6ccb | 826 | Counter is in free running mode to generate periodic interrupts. |
MikamiUitOpen | 2:dcaee06f6ccb | 827 | |
MikamiUitOpen | 2:dcaee06f6ccb | 828 | \param [in] ticks Number of ticks between two interrupts. |
MikamiUitOpen | 2:dcaee06f6ccb | 829 | |
MikamiUitOpen | 2:dcaee06f6ccb | 830 | \return 0 Function succeeded. |
MikamiUitOpen | 2:dcaee06f6ccb | 831 | \return 1 Function failed. |
MikamiUitOpen | 2:dcaee06f6ccb | 832 | |
MikamiUitOpen | 2:dcaee06f6ccb | 833 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
MikamiUitOpen | 2:dcaee06f6ccb | 834 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
MikamiUitOpen | 2:dcaee06f6ccb | 835 | must contain a vendor-specific implementation of this function. |
MikamiUitOpen | 2:dcaee06f6ccb | 836 | |
MikamiUitOpen | 2:dcaee06f6ccb | 837 | */ |
MikamiUitOpen | 2:dcaee06f6ccb | 838 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
MikamiUitOpen | 2:dcaee06f6ccb | 839 | { |
MikamiUitOpen | 2:dcaee06f6ccb | 840 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ |
MikamiUitOpen | 2:dcaee06f6ccb | 841 | |
MikamiUitOpen | 2:dcaee06f6ccb | 842 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
MikamiUitOpen | 2:dcaee06f6ccb | 843 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
MikamiUitOpen | 2:dcaee06f6ccb | 844 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
MikamiUitOpen | 2:dcaee06f6ccb | 845 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
MikamiUitOpen | 2:dcaee06f6ccb | 846 | SysTick_CTRL_TICKINT_Msk | |
MikamiUitOpen | 2:dcaee06f6ccb | 847 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
MikamiUitOpen | 2:dcaee06f6ccb | 848 | return (0UL); /* Function successful */ |
MikamiUitOpen | 2:dcaee06f6ccb | 849 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 850 | |
MikamiUitOpen | 2:dcaee06f6ccb | 851 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 852 | |
MikamiUitOpen | 2:dcaee06f6ccb | 853 | /*@} end of CMSIS_Core_SysTickFunctions */ |
MikamiUitOpen | 2:dcaee06f6ccb | 854 | |
MikamiUitOpen | 2:dcaee06f6ccb | 855 | |
MikamiUitOpen | 2:dcaee06f6ccb | 856 | |
MikamiUitOpen | 2:dcaee06f6ccb | 857 | |
MikamiUitOpen | 2:dcaee06f6ccb | 858 | #ifdef __cplusplus |
MikamiUitOpen | 2:dcaee06f6ccb | 859 | } |
MikamiUitOpen | 2:dcaee06f6ccb | 860 | #endif |
MikamiUitOpen | 2:dcaee06f6ccb | 861 | |
MikamiUitOpen | 2:dcaee06f6ccb | 862 | #endif /* __CORE_SC000_H_DEPENDANT */ |
MikamiUitOpen | 2:dcaee06f6ccb | 863 | |
MikamiUitOpen | 2:dcaee06f6ccb | 864 | #endif /* __CMSIS_GENERIC */ |