不韋 呂 / F746_SD_VarableFilter

SD card player with variable cotoff frequency lowpass and highpass IIR filter. SD カードの *.wav ファイルのオーディオ信号を，遮断周波数可変 IIR 低域通過および高域通過フィルタを通して，ボードに搭載されているCODEC で出力する．このプログラムについては，CQ出版社インターフェース誌 2018年8月号で解説している．

Dependencies:   F746_GUI F746_SAI_IO FrequencyResponseDrawer SD_PlayerSkeleton

mbed_src_STM32F7/targets/cmsis/core_cmInstr.h@11:399670d24ed9, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 01:44:22 2017 +0000
Revision:
11:399670d24ed9
Parent:
2:dcaee06f6ccb 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 2:dcaee06f6ccb 1 /**************************************************************************//**
MikamiUitOpen 2:dcaee06f6ccb 2 * @file core_cmInstr.h
MikamiUitOpen 2:dcaee06f6ccb 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
MikamiUitOpen 2:dcaee06f6ccb 4 * @version V4.10
MikamiUitOpen 2:dcaee06f6ccb 5 * @date 18. March 2015
MikamiUitOpen 2:dcaee06f6ccb 6 *
MikamiUitOpen 2:dcaee06f6ccb 7 * @note
MikamiUitOpen 2:dcaee06f6ccb 8 *
MikamiUitOpen 2:dcaee06f6ccb 9 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
MikamiUitOpen 2:dcaee06f6ccb 11
MikamiUitOpen 2:dcaee06f6ccb 12 All rights reserved.
MikamiUitOpen 2:dcaee06f6ccb 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 2:dcaee06f6ccb 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 2:dcaee06f6ccb 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 2:dcaee06f6ccb 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 2:dcaee06f6ccb 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 2:dcaee06f6ccb 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 2:dcaee06f6ccb 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 2:dcaee06f6ccb 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 2:dcaee06f6ccb 21 to endorse or promote products derived from this software without
MikamiUitOpen 2:dcaee06f6ccb 22 specific prior written permission.
MikamiUitOpen 2:dcaee06f6ccb 23 *
MikamiUitOpen 2:dcaee06f6ccb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 2:dcaee06f6ccb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 2:dcaee06f6ccb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 2:dcaee06f6ccb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 2:dcaee06f6ccb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 2:dcaee06f6ccb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 2:dcaee06f6ccb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 2:dcaee06f6ccb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 2:dcaee06f6ccb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 2:dcaee06f6ccb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 2:dcaee06f6ccb 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 2:dcaee06f6ccb 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 2:dcaee06f6ccb 36
MikamiUitOpen 2:dcaee06f6ccb 37
MikamiUitOpen 2:dcaee06f6ccb 38 #ifndef __CORE_CMINSTR_H
MikamiUitOpen 2:dcaee06f6ccb 39 #define __CORE_CMINSTR_H
MikamiUitOpen 2:dcaee06f6ccb 40
MikamiUitOpen 2:dcaee06f6ccb 41
MikamiUitOpen 2:dcaee06f6ccb 42 /* ########################## Core Instruction Access ######################### */
MikamiUitOpen 2:dcaee06f6ccb 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
MikamiUitOpen 2:dcaee06f6ccb 44 Access to dedicated instructions
MikamiUitOpen 2:dcaee06f6ccb 45 @{
MikamiUitOpen 2:dcaee06f6ccb 46 */
MikamiUitOpen 2:dcaee06f6ccb 47
MikamiUitOpen 2:dcaee06f6ccb 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 2:dcaee06f6ccb 49 /* ARM armcc specific functions */
MikamiUitOpen 2:dcaee06f6ccb 50
MikamiUitOpen 2:dcaee06f6ccb 51 #if (__ARMCC_VERSION < 400677)
MikamiUitOpen 2:dcaee06f6ccb 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MikamiUitOpen 2:dcaee06f6ccb 53 #endif
MikamiUitOpen 2:dcaee06f6ccb 54
MikamiUitOpen 2:dcaee06f6ccb 55
MikamiUitOpen 2:dcaee06f6ccb 56 /** \brief No Operation
MikamiUitOpen 2:dcaee06f6ccb 57
MikamiUitOpen 2:dcaee06f6ccb 58 No Operation does nothing. This instruction can be used for code alignment purposes.
MikamiUitOpen 2:dcaee06f6ccb 59 */
MikamiUitOpen 2:dcaee06f6ccb 60 #define __NOP __nop
MikamiUitOpen 2:dcaee06f6ccb 61
MikamiUitOpen 2:dcaee06f6ccb 62
MikamiUitOpen 2:dcaee06f6ccb 63 /** \brief Wait For Interrupt
MikamiUitOpen 2:dcaee06f6ccb 64
MikamiUitOpen 2:dcaee06f6ccb 65 Wait For Interrupt is a hint instruction that suspends execution
MikamiUitOpen 2:dcaee06f6ccb 66 until one of a number of events occurs.
MikamiUitOpen 2:dcaee06f6ccb 67 */
MikamiUitOpen 2:dcaee06f6ccb 68 #define __WFI __wfi
MikamiUitOpen 2:dcaee06f6ccb 69
MikamiUitOpen 2:dcaee06f6ccb 70
MikamiUitOpen 2:dcaee06f6ccb 71 /** \brief Wait For Event
MikamiUitOpen 2:dcaee06f6ccb 72
MikamiUitOpen 2:dcaee06f6ccb 73 Wait For Event is a hint instruction that permits the processor to enter
MikamiUitOpen 2:dcaee06f6ccb 74 a low-power state until one of a number of events occurs.
MikamiUitOpen 2:dcaee06f6ccb 75 */
MikamiUitOpen 2:dcaee06f6ccb 76 #define __WFE __wfe
MikamiUitOpen 2:dcaee06f6ccb 77
MikamiUitOpen 2:dcaee06f6ccb 78
MikamiUitOpen 2:dcaee06f6ccb 79 /** \brief Send Event
MikamiUitOpen 2:dcaee06f6ccb 80
MikamiUitOpen 2:dcaee06f6ccb 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
MikamiUitOpen 2:dcaee06f6ccb 82 */
MikamiUitOpen 2:dcaee06f6ccb 83 #define __SEV __sev
MikamiUitOpen 2:dcaee06f6ccb 84
MikamiUitOpen 2:dcaee06f6ccb 85
MikamiUitOpen 2:dcaee06f6ccb 86 /** \brief Instruction Synchronization Barrier
MikamiUitOpen 2:dcaee06f6ccb 87
MikamiUitOpen 2:dcaee06f6ccb 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
MikamiUitOpen 2:dcaee06f6ccb 89 so that all instructions following the ISB are fetched from cache or
MikamiUitOpen 2:dcaee06f6ccb 90 memory, after the instruction has been completed.
MikamiUitOpen 2:dcaee06f6ccb 91 */
MikamiUitOpen 2:dcaee06f6ccb 92 #define __ISB() do {\
MikamiUitOpen 2:dcaee06f6ccb 93 __schedule_barrier();\
MikamiUitOpen 2:dcaee06f6ccb 94 __isb(0xF);\
MikamiUitOpen 2:dcaee06f6ccb 95 __schedule_barrier();\
MikamiUitOpen 2:dcaee06f6ccb 96 } while (0)
MikamiUitOpen 2:dcaee06f6ccb 97
MikamiUitOpen 2:dcaee06f6ccb 98 /** \brief Data Synchronization Barrier
MikamiUitOpen 2:dcaee06f6ccb 99
MikamiUitOpen 2:dcaee06f6ccb 100 This function acts as a special kind of Data Memory Barrier.
MikamiUitOpen 2:dcaee06f6ccb 101 It completes when all explicit memory accesses before this instruction complete.
MikamiUitOpen 2:dcaee06f6ccb 102 */
MikamiUitOpen 2:dcaee06f6ccb 103 #define __DSB() do {\
MikamiUitOpen 2:dcaee06f6ccb 104 __schedule_barrier();\
MikamiUitOpen 2:dcaee06f6ccb 105 __dsb(0xF);\
MikamiUitOpen 2:dcaee06f6ccb 106 __schedule_barrier();\
MikamiUitOpen 2:dcaee06f6ccb 107 } while (0)
MikamiUitOpen 2:dcaee06f6ccb 108
MikamiUitOpen 2:dcaee06f6ccb 109 /** \brief Data Memory Barrier
MikamiUitOpen 2:dcaee06f6ccb 110
MikamiUitOpen 2:dcaee06f6ccb 111 This function ensures the apparent order of the explicit memory operations before
MikamiUitOpen 2:dcaee06f6ccb 112 and after the instruction, without ensuring their completion.
MikamiUitOpen 2:dcaee06f6ccb 113 */
MikamiUitOpen 2:dcaee06f6ccb 114 #define __DMB() do {\
MikamiUitOpen 2:dcaee06f6ccb 115 __schedule_barrier();\
MikamiUitOpen 2:dcaee06f6ccb 116 __dmb(0xF);\
MikamiUitOpen 2:dcaee06f6ccb 117 __schedule_barrier();\
MikamiUitOpen 2:dcaee06f6ccb 118 } while (0)
MikamiUitOpen 2:dcaee06f6ccb 119
MikamiUitOpen 2:dcaee06f6ccb 120 /** \brief Reverse byte order (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 121
MikamiUitOpen 2:dcaee06f6ccb 122 This function reverses the byte order in integer value.
MikamiUitOpen 2:dcaee06f6ccb 123
MikamiUitOpen 2:dcaee06f6ccb 124 \param [in] value Value to reverse
MikamiUitOpen 2:dcaee06f6ccb 125 \return Reversed value
MikamiUitOpen 2:dcaee06f6ccb 126 */
MikamiUitOpen 2:dcaee06f6ccb 127 #define __REV __rev
MikamiUitOpen 2:dcaee06f6ccb 128
MikamiUitOpen 2:dcaee06f6ccb 129
MikamiUitOpen 2:dcaee06f6ccb 130 /** \brief Reverse byte order (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 131
MikamiUitOpen 2:dcaee06f6ccb 132 This function reverses the byte order in two unsigned short values.
MikamiUitOpen 2:dcaee06f6ccb 133
MikamiUitOpen 2:dcaee06f6ccb 134 \param [in] value Value to reverse
MikamiUitOpen 2:dcaee06f6ccb 135 \return Reversed value
MikamiUitOpen 2:dcaee06f6ccb 136 */
MikamiUitOpen 2:dcaee06f6ccb 137 #ifndef __NO_EMBEDDED_ASM
MikamiUitOpen 2:dcaee06f6ccb 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
MikamiUitOpen 2:dcaee06f6ccb 139 {
MikamiUitOpen 2:dcaee06f6ccb 140 rev16 r0, r0
MikamiUitOpen 2:dcaee06f6ccb 141 bx lr
MikamiUitOpen 2:dcaee06f6ccb 142 }
MikamiUitOpen 2:dcaee06f6ccb 143 #endif
MikamiUitOpen 2:dcaee06f6ccb 144
MikamiUitOpen 2:dcaee06f6ccb 145 /** \brief Reverse byte order in signed short value
MikamiUitOpen 2:dcaee06f6ccb 146
MikamiUitOpen 2:dcaee06f6ccb 147 This function reverses the byte order in a signed short value with sign extension to integer.
MikamiUitOpen 2:dcaee06f6ccb 148
MikamiUitOpen 2:dcaee06f6ccb 149 \param [in] value Value to reverse
MikamiUitOpen 2:dcaee06f6ccb 150 \return Reversed value
MikamiUitOpen 2:dcaee06f6ccb 151 */
MikamiUitOpen 2:dcaee06f6ccb 152 #ifndef __NO_EMBEDDED_ASM
MikamiUitOpen 2:dcaee06f6ccb 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
MikamiUitOpen 2:dcaee06f6ccb 154 {
MikamiUitOpen 2:dcaee06f6ccb 155 revsh r0, r0
MikamiUitOpen 2:dcaee06f6ccb 156 bx lr
MikamiUitOpen 2:dcaee06f6ccb 157 }
MikamiUitOpen 2:dcaee06f6ccb 158 #endif
MikamiUitOpen 2:dcaee06f6ccb 159
MikamiUitOpen 2:dcaee06f6ccb 160
MikamiUitOpen 2:dcaee06f6ccb 161 /** \brief Rotate Right in unsigned value (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 162
MikamiUitOpen 2:dcaee06f6ccb 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
MikamiUitOpen 2:dcaee06f6ccb 164
MikamiUitOpen 2:dcaee06f6ccb 165 \param [in] value Value to rotate
MikamiUitOpen 2:dcaee06f6ccb 166 \param [in] value Number of Bits to rotate
MikamiUitOpen 2:dcaee06f6ccb 167 \return Rotated value
MikamiUitOpen 2:dcaee06f6ccb 168 */
MikamiUitOpen 2:dcaee06f6ccb 169 #define __ROR __ror
MikamiUitOpen 2:dcaee06f6ccb 170
MikamiUitOpen 2:dcaee06f6ccb 171
MikamiUitOpen 2:dcaee06f6ccb 172 /** \brief Breakpoint
MikamiUitOpen 2:dcaee06f6ccb 173
MikamiUitOpen 2:dcaee06f6ccb 174 This function causes the processor to enter Debug state.
MikamiUitOpen 2:dcaee06f6ccb 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
MikamiUitOpen 2:dcaee06f6ccb 176
MikamiUitOpen 2:dcaee06f6ccb 177 \param [in] value is ignored by the processor.
MikamiUitOpen 2:dcaee06f6ccb 178 If required, a debugger can use it to store additional information about the breakpoint.
MikamiUitOpen 2:dcaee06f6ccb 179 */
MikamiUitOpen 2:dcaee06f6ccb 180 #define __BKPT(value) __breakpoint(value)
MikamiUitOpen 2:dcaee06f6ccb 181
MikamiUitOpen 2:dcaee06f6ccb 182
MikamiUitOpen 2:dcaee06f6ccb 183 /** \brief Reverse bit order of value
MikamiUitOpen 2:dcaee06f6ccb 184
MikamiUitOpen 2:dcaee06f6ccb 185 This function reverses the bit order of the given value.
MikamiUitOpen 2:dcaee06f6ccb 186
MikamiUitOpen 2:dcaee06f6ccb 187 \param [in] value Value to reverse
MikamiUitOpen 2:dcaee06f6ccb 188 \return Reversed value
MikamiUitOpen 2:dcaee06f6ccb 189 */
MikamiUitOpen 2:dcaee06f6ccb 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 2:dcaee06f6ccb 191 #define __RBIT __rbit
MikamiUitOpen 2:dcaee06f6ccb 192 #else
MikamiUitOpen 2:dcaee06f6ccb 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
MikamiUitOpen 2:dcaee06f6ccb 194 {
MikamiUitOpen 2:dcaee06f6ccb 195 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
MikamiUitOpen 2:dcaee06f6ccb 197
MikamiUitOpen 2:dcaee06f6ccb 198 result = value; // r will be reversed bits of v; first get LSB of v
MikamiUitOpen 2:dcaee06f6ccb 199 for (value >>= 1; value; value >>= 1)
MikamiUitOpen 2:dcaee06f6ccb 200 {
MikamiUitOpen 2:dcaee06f6ccb 201 result <<= 1;
MikamiUitOpen 2:dcaee06f6ccb 202 result |= value & 1;
MikamiUitOpen 2:dcaee06f6ccb 203 s--;
MikamiUitOpen 2:dcaee06f6ccb 204 }
MikamiUitOpen 2:dcaee06f6ccb 205 result <<= s; // shift when v's highest bits are zero
MikamiUitOpen 2:dcaee06f6ccb 206 return(result);
MikamiUitOpen 2:dcaee06f6ccb 207 }
MikamiUitOpen 2:dcaee06f6ccb 208 #endif
MikamiUitOpen 2:dcaee06f6ccb 209
MikamiUitOpen 2:dcaee06f6ccb 210
MikamiUitOpen 2:dcaee06f6ccb 211 /** \brief Count leading zeros
MikamiUitOpen 2:dcaee06f6ccb 212
MikamiUitOpen 2:dcaee06f6ccb 213 This function counts the number of leading zeros of a data value.
MikamiUitOpen 2:dcaee06f6ccb 214
MikamiUitOpen 2:dcaee06f6ccb 215 \param [in] value Value to count the leading zeros
MikamiUitOpen 2:dcaee06f6ccb 216 \return number of leading zeros in value
MikamiUitOpen 2:dcaee06f6ccb 217 */
MikamiUitOpen 2:dcaee06f6ccb 218 #define __CLZ __clz
MikamiUitOpen 2:dcaee06f6ccb 219
MikamiUitOpen 2:dcaee06f6ccb 220
MikamiUitOpen 2:dcaee06f6ccb 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 2:dcaee06f6ccb 222
MikamiUitOpen 2:dcaee06f6ccb 223 /** \brief LDR Exclusive (8 bit)
MikamiUitOpen 2:dcaee06f6ccb 224
MikamiUitOpen 2:dcaee06f6ccb 225 This function executes a exclusive LDR instruction for 8 bit value.
MikamiUitOpen 2:dcaee06f6ccb 226
MikamiUitOpen 2:dcaee06f6ccb 227 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 228 \return value of type uint8_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 229 */
MikamiUitOpen 2:dcaee06f6ccb 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
MikamiUitOpen 2:dcaee06f6ccb 231
MikamiUitOpen 2:dcaee06f6ccb 232
MikamiUitOpen 2:dcaee06f6ccb 233 /** \brief LDR Exclusive (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 234
MikamiUitOpen 2:dcaee06f6ccb 235 This function executes a exclusive LDR instruction for 16 bit values.
MikamiUitOpen 2:dcaee06f6ccb 236
MikamiUitOpen 2:dcaee06f6ccb 237 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 238 \return value of type uint16_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 239 */
MikamiUitOpen 2:dcaee06f6ccb 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
MikamiUitOpen 2:dcaee06f6ccb 241
MikamiUitOpen 2:dcaee06f6ccb 242
MikamiUitOpen 2:dcaee06f6ccb 243 /** \brief LDR Exclusive (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 244
MikamiUitOpen 2:dcaee06f6ccb 245 This function executes a exclusive LDR instruction for 32 bit values.
MikamiUitOpen 2:dcaee06f6ccb 246
MikamiUitOpen 2:dcaee06f6ccb 247 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 248 \return value of type uint32_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 249 */
MikamiUitOpen 2:dcaee06f6ccb 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
MikamiUitOpen 2:dcaee06f6ccb 251
MikamiUitOpen 2:dcaee06f6ccb 252
MikamiUitOpen 2:dcaee06f6ccb 253 /** \brief STR Exclusive (8 bit)
MikamiUitOpen 2:dcaee06f6ccb 254
MikamiUitOpen 2:dcaee06f6ccb 255 This function executes a exclusive STR instruction for 8 bit values.
MikamiUitOpen 2:dcaee06f6ccb 256
MikamiUitOpen 2:dcaee06f6ccb 257 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 258 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 259 \return 0 Function succeeded
MikamiUitOpen 2:dcaee06f6ccb 260 \return 1 Function failed
MikamiUitOpen 2:dcaee06f6ccb 261 */
MikamiUitOpen 2:dcaee06f6ccb 262 #define __STREXB(value, ptr) __strex(value, ptr)
MikamiUitOpen 2:dcaee06f6ccb 263
MikamiUitOpen 2:dcaee06f6ccb 264
MikamiUitOpen 2:dcaee06f6ccb 265 /** \brief STR Exclusive (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 266
MikamiUitOpen 2:dcaee06f6ccb 267 This function executes a exclusive STR instruction for 16 bit values.
MikamiUitOpen 2:dcaee06f6ccb 268
MikamiUitOpen 2:dcaee06f6ccb 269 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 270 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 271 \return 0 Function succeeded
MikamiUitOpen 2:dcaee06f6ccb 272 \return 1 Function failed
MikamiUitOpen 2:dcaee06f6ccb 273 */
MikamiUitOpen 2:dcaee06f6ccb 274 #define __STREXH(value, ptr) __strex(value, ptr)
MikamiUitOpen 2:dcaee06f6ccb 275
MikamiUitOpen 2:dcaee06f6ccb 276
MikamiUitOpen 2:dcaee06f6ccb 277 /** \brief STR Exclusive (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 278
MikamiUitOpen 2:dcaee06f6ccb 279 This function executes a exclusive STR instruction for 32 bit values.
MikamiUitOpen 2:dcaee06f6ccb 280
MikamiUitOpen 2:dcaee06f6ccb 281 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 282 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 283 \return 0 Function succeeded
MikamiUitOpen 2:dcaee06f6ccb 284 \return 1 Function failed
MikamiUitOpen 2:dcaee06f6ccb 285 */
MikamiUitOpen 2:dcaee06f6ccb 286 #define __STREXW(value, ptr) __strex(value, ptr)
MikamiUitOpen 2:dcaee06f6ccb 287
MikamiUitOpen 2:dcaee06f6ccb 288
MikamiUitOpen 2:dcaee06f6ccb 289 /** \brief Remove the exclusive lock
MikamiUitOpen 2:dcaee06f6ccb 290
MikamiUitOpen 2:dcaee06f6ccb 291 This function removes the exclusive lock which is created by LDREX.
MikamiUitOpen 2:dcaee06f6ccb 292
MikamiUitOpen 2:dcaee06f6ccb 293 */
MikamiUitOpen 2:dcaee06f6ccb 294 #define __CLREX __clrex
MikamiUitOpen 2:dcaee06f6ccb 295
MikamiUitOpen 2:dcaee06f6ccb 296
MikamiUitOpen 2:dcaee06f6ccb 297 /** \brief Signed Saturate
MikamiUitOpen 2:dcaee06f6ccb 298
MikamiUitOpen 2:dcaee06f6ccb 299 This function saturates a signed value.
MikamiUitOpen 2:dcaee06f6ccb 300
MikamiUitOpen 2:dcaee06f6ccb 301 \param [in] value Value to be saturated
MikamiUitOpen 2:dcaee06f6ccb 302 \param [in] sat Bit position to saturate to (1..32)
MikamiUitOpen 2:dcaee06f6ccb 303 \return Saturated value
MikamiUitOpen 2:dcaee06f6ccb 304 */
MikamiUitOpen 2:dcaee06f6ccb 305 #define __SSAT __ssat
MikamiUitOpen 2:dcaee06f6ccb 306
MikamiUitOpen 2:dcaee06f6ccb 307
MikamiUitOpen 2:dcaee06f6ccb 308 /** \brief Unsigned Saturate
MikamiUitOpen 2:dcaee06f6ccb 309
MikamiUitOpen 2:dcaee06f6ccb 310 This function saturates an unsigned value.
MikamiUitOpen 2:dcaee06f6ccb 311
MikamiUitOpen 2:dcaee06f6ccb 312 \param [in] value Value to be saturated
MikamiUitOpen 2:dcaee06f6ccb 313 \param [in] sat Bit position to saturate to (0..31)
MikamiUitOpen 2:dcaee06f6ccb 314 \return Saturated value
MikamiUitOpen 2:dcaee06f6ccb 315 */
MikamiUitOpen 2:dcaee06f6ccb 316 #define __USAT __usat
MikamiUitOpen 2:dcaee06f6ccb 317
MikamiUitOpen 2:dcaee06f6ccb 318
MikamiUitOpen 2:dcaee06f6ccb 319 /** \brief Rotate Right with Extend (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 320
MikamiUitOpen 2:dcaee06f6ccb 321 This function moves each bit of a bitstring right by one bit.
MikamiUitOpen 2:dcaee06f6ccb 322 The carry input is shifted in at the left end of the bitstring.
MikamiUitOpen 2:dcaee06f6ccb 323
MikamiUitOpen 2:dcaee06f6ccb 324 \param [in] value Value to rotate
MikamiUitOpen 2:dcaee06f6ccb 325 \return Rotated value
MikamiUitOpen 2:dcaee06f6ccb 326 */
MikamiUitOpen 2:dcaee06f6ccb 327 #ifndef __NO_EMBEDDED_ASM
MikamiUitOpen 2:dcaee06f6ccb 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
MikamiUitOpen 2:dcaee06f6ccb 329 {
MikamiUitOpen 2:dcaee06f6ccb 330 rrx r0, r0
MikamiUitOpen 2:dcaee06f6ccb 331 bx lr
MikamiUitOpen 2:dcaee06f6ccb 332 }
MikamiUitOpen 2:dcaee06f6ccb 333 #endif
MikamiUitOpen 2:dcaee06f6ccb 334
MikamiUitOpen 2:dcaee06f6ccb 335
MikamiUitOpen 2:dcaee06f6ccb 336 /** \brief LDRT Unprivileged (8 bit)
MikamiUitOpen 2:dcaee06f6ccb 337
MikamiUitOpen 2:dcaee06f6ccb 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
MikamiUitOpen 2:dcaee06f6ccb 339
MikamiUitOpen 2:dcaee06f6ccb 340 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 341 \return value of type uint8_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 342 */
MikamiUitOpen 2:dcaee06f6ccb 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
MikamiUitOpen 2:dcaee06f6ccb 344
MikamiUitOpen 2:dcaee06f6ccb 345
MikamiUitOpen 2:dcaee06f6ccb 346 /** \brief LDRT Unprivileged (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 347
MikamiUitOpen 2:dcaee06f6ccb 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
MikamiUitOpen 2:dcaee06f6ccb 349
MikamiUitOpen 2:dcaee06f6ccb 350 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 351 \return value of type uint16_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 352 */
MikamiUitOpen 2:dcaee06f6ccb 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
MikamiUitOpen 2:dcaee06f6ccb 354
MikamiUitOpen 2:dcaee06f6ccb 355
MikamiUitOpen 2:dcaee06f6ccb 356 /** \brief LDRT Unprivileged (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 357
MikamiUitOpen 2:dcaee06f6ccb 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
MikamiUitOpen 2:dcaee06f6ccb 359
MikamiUitOpen 2:dcaee06f6ccb 360 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 361 \return value of type uint32_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 362 */
MikamiUitOpen 2:dcaee06f6ccb 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
MikamiUitOpen 2:dcaee06f6ccb 364
MikamiUitOpen 2:dcaee06f6ccb 365
MikamiUitOpen 2:dcaee06f6ccb 366 /** \brief STRT Unprivileged (8 bit)
MikamiUitOpen 2:dcaee06f6ccb 367
MikamiUitOpen 2:dcaee06f6ccb 368 This function executes a Unprivileged STRT instruction for 8 bit values.
MikamiUitOpen 2:dcaee06f6ccb 369
MikamiUitOpen 2:dcaee06f6ccb 370 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 371 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 372 */
MikamiUitOpen 2:dcaee06f6ccb 373 #define __STRBT(value, ptr) __strt(value, ptr)
MikamiUitOpen 2:dcaee06f6ccb 374
MikamiUitOpen 2:dcaee06f6ccb 375
MikamiUitOpen 2:dcaee06f6ccb 376 /** \brief STRT Unprivileged (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 377
MikamiUitOpen 2:dcaee06f6ccb 378 This function executes a Unprivileged STRT instruction for 16 bit values.
MikamiUitOpen 2:dcaee06f6ccb 379
MikamiUitOpen 2:dcaee06f6ccb 380 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 381 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 382 */
MikamiUitOpen 2:dcaee06f6ccb 383 #define __STRHT(value, ptr) __strt(value, ptr)
MikamiUitOpen 2:dcaee06f6ccb 384
MikamiUitOpen 2:dcaee06f6ccb 385
MikamiUitOpen 2:dcaee06f6ccb 386 /** \brief STRT Unprivileged (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 387
MikamiUitOpen 2:dcaee06f6ccb 388 This function executes a Unprivileged STRT instruction for 32 bit values.
MikamiUitOpen 2:dcaee06f6ccb 389
MikamiUitOpen 2:dcaee06f6ccb 390 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 391 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 392 */
MikamiUitOpen 2:dcaee06f6ccb 393 #define __STRT(value, ptr) __strt(value, ptr)
MikamiUitOpen 2:dcaee06f6ccb 394
MikamiUitOpen 2:dcaee06f6ccb 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 2:dcaee06f6ccb 396
MikamiUitOpen 2:dcaee06f6ccb 397
MikamiUitOpen 2:dcaee06f6ccb 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 2:dcaee06f6ccb 399 /* GNU gcc specific functions */
MikamiUitOpen 2:dcaee06f6ccb 400
MikamiUitOpen 2:dcaee06f6ccb 401 /* Define macros for porting to both thumb1 and thumb2.
MikamiUitOpen 2:dcaee06f6ccb 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
MikamiUitOpen 2:dcaee06f6ccb 403 * Otherwise, use general registers, specified by constrant "r" */
MikamiUitOpen 2:dcaee06f6ccb 404 #if defined (__thumb__) && !defined (__thumb2__)
MikamiUitOpen 2:dcaee06f6ccb 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
MikamiUitOpen 2:dcaee06f6ccb 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
MikamiUitOpen 2:dcaee06f6ccb 407 #else
MikamiUitOpen 2:dcaee06f6ccb 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
MikamiUitOpen 2:dcaee06f6ccb 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
MikamiUitOpen 2:dcaee06f6ccb 410 #endif
MikamiUitOpen 2:dcaee06f6ccb 411
MikamiUitOpen 2:dcaee06f6ccb 412 /** \brief No Operation
MikamiUitOpen 2:dcaee06f6ccb 413
MikamiUitOpen 2:dcaee06f6ccb 414 No Operation does nothing. This instruction can be used for code alignment purposes.
MikamiUitOpen 2:dcaee06f6ccb 415 */
MikamiUitOpen 2:dcaee06f6ccb 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
MikamiUitOpen 2:dcaee06f6ccb 417 {
MikamiUitOpen 2:dcaee06f6ccb 418 __ASM volatile ("nop");
MikamiUitOpen 2:dcaee06f6ccb 419 }
MikamiUitOpen 2:dcaee06f6ccb 420
MikamiUitOpen 2:dcaee06f6ccb 421
MikamiUitOpen 2:dcaee06f6ccb 422 /** \brief Wait For Interrupt
MikamiUitOpen 2:dcaee06f6ccb 423
MikamiUitOpen 2:dcaee06f6ccb 424 Wait For Interrupt is a hint instruction that suspends execution
MikamiUitOpen 2:dcaee06f6ccb 425 until one of a number of events occurs.
MikamiUitOpen 2:dcaee06f6ccb 426 */
MikamiUitOpen 2:dcaee06f6ccb 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
MikamiUitOpen 2:dcaee06f6ccb 428 {
MikamiUitOpen 2:dcaee06f6ccb 429 __ASM volatile ("wfi");
MikamiUitOpen 2:dcaee06f6ccb 430 }
MikamiUitOpen 2:dcaee06f6ccb 431
MikamiUitOpen 2:dcaee06f6ccb 432
MikamiUitOpen 2:dcaee06f6ccb 433 /** \brief Wait For Event
MikamiUitOpen 2:dcaee06f6ccb 434
MikamiUitOpen 2:dcaee06f6ccb 435 Wait For Event is a hint instruction that permits the processor to enter
MikamiUitOpen 2:dcaee06f6ccb 436 a low-power state until one of a number of events occurs.
MikamiUitOpen 2:dcaee06f6ccb 437 */
MikamiUitOpen 2:dcaee06f6ccb 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
MikamiUitOpen 2:dcaee06f6ccb 439 {
MikamiUitOpen 2:dcaee06f6ccb 440 __ASM volatile ("wfe");
MikamiUitOpen 2:dcaee06f6ccb 441 }
MikamiUitOpen 2:dcaee06f6ccb 442
MikamiUitOpen 2:dcaee06f6ccb 443
MikamiUitOpen 2:dcaee06f6ccb 444 /** \brief Send Event
MikamiUitOpen 2:dcaee06f6ccb 445
MikamiUitOpen 2:dcaee06f6ccb 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
MikamiUitOpen 2:dcaee06f6ccb 447 */
MikamiUitOpen 2:dcaee06f6ccb 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
MikamiUitOpen 2:dcaee06f6ccb 449 {
MikamiUitOpen 2:dcaee06f6ccb 450 __ASM volatile ("sev");
MikamiUitOpen 2:dcaee06f6ccb 451 }
MikamiUitOpen 2:dcaee06f6ccb 452
MikamiUitOpen 2:dcaee06f6ccb 453
MikamiUitOpen 2:dcaee06f6ccb 454 /** \brief Instruction Synchronization Barrier
MikamiUitOpen 2:dcaee06f6ccb 455
MikamiUitOpen 2:dcaee06f6ccb 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
MikamiUitOpen 2:dcaee06f6ccb 457 so that all instructions following the ISB are fetched from cache or
MikamiUitOpen 2:dcaee06f6ccb 458 memory, after the instruction has been completed.
MikamiUitOpen 2:dcaee06f6ccb 459 */
MikamiUitOpen 2:dcaee06f6ccb 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
MikamiUitOpen 2:dcaee06f6ccb 461 {
MikamiUitOpen 2:dcaee06f6ccb 462 __ASM volatile ("isb 0xF":::"memory");
MikamiUitOpen 2:dcaee06f6ccb 463 }
MikamiUitOpen 2:dcaee06f6ccb 464
MikamiUitOpen 2:dcaee06f6ccb 465
MikamiUitOpen 2:dcaee06f6ccb 466 /** \brief Data Synchronization Barrier
MikamiUitOpen 2:dcaee06f6ccb 467
MikamiUitOpen 2:dcaee06f6ccb 468 This function acts as a special kind of Data Memory Barrier.
MikamiUitOpen 2:dcaee06f6ccb 469 It completes when all explicit memory accesses before this instruction complete.
MikamiUitOpen 2:dcaee06f6ccb 470 */
MikamiUitOpen 2:dcaee06f6ccb 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
MikamiUitOpen 2:dcaee06f6ccb 472 {
MikamiUitOpen 2:dcaee06f6ccb 473 __ASM volatile ("dsb 0xF":::"memory");
MikamiUitOpen 2:dcaee06f6ccb 474 }
MikamiUitOpen 2:dcaee06f6ccb 475
MikamiUitOpen 2:dcaee06f6ccb 476
MikamiUitOpen 2:dcaee06f6ccb 477 /** \brief Data Memory Barrier
MikamiUitOpen 2:dcaee06f6ccb 478
MikamiUitOpen 2:dcaee06f6ccb 479 This function ensures the apparent order of the explicit memory operations before
MikamiUitOpen 2:dcaee06f6ccb 480 and after the instruction, without ensuring their completion.
MikamiUitOpen 2:dcaee06f6ccb 481 */
MikamiUitOpen 2:dcaee06f6ccb 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
MikamiUitOpen 2:dcaee06f6ccb 483 {
MikamiUitOpen 2:dcaee06f6ccb 484 __ASM volatile ("dmb 0xF":::"memory");
MikamiUitOpen 2:dcaee06f6ccb 485 }
MikamiUitOpen 2:dcaee06f6ccb 486
MikamiUitOpen 2:dcaee06f6ccb 487
MikamiUitOpen 2:dcaee06f6ccb 488 /** \brief Reverse byte order (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 489
MikamiUitOpen 2:dcaee06f6ccb 490 This function reverses the byte order in integer value.
MikamiUitOpen 2:dcaee06f6ccb 491
MikamiUitOpen 2:dcaee06f6ccb 492 \param [in] value Value to reverse
MikamiUitOpen 2:dcaee06f6ccb 493 \return Reversed value
MikamiUitOpen 2:dcaee06f6ccb 494 */
MikamiUitOpen 2:dcaee06f6ccb 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
MikamiUitOpen 2:dcaee06f6ccb 496 {
MikamiUitOpen 2:dcaee06f6ccb 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
MikamiUitOpen 2:dcaee06f6ccb 498 return __builtin_bswap32(value);
MikamiUitOpen 2:dcaee06f6ccb 499 #else
MikamiUitOpen 2:dcaee06f6ccb 500 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 501
MikamiUitOpen 2:dcaee06f6ccb 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 2:dcaee06f6ccb 503 return(result);
MikamiUitOpen 2:dcaee06f6ccb 504 #endif
MikamiUitOpen 2:dcaee06f6ccb 505 }
MikamiUitOpen 2:dcaee06f6ccb 506
MikamiUitOpen 2:dcaee06f6ccb 507
MikamiUitOpen 2:dcaee06f6ccb 508 /** \brief Reverse byte order (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 509
MikamiUitOpen 2:dcaee06f6ccb 510 This function reverses the byte order in two unsigned short values.
MikamiUitOpen 2:dcaee06f6ccb 511
MikamiUitOpen 2:dcaee06f6ccb 512 \param [in] value Value to reverse
MikamiUitOpen 2:dcaee06f6ccb 513 \return Reversed value
MikamiUitOpen 2:dcaee06f6ccb 514 */
MikamiUitOpen 2:dcaee06f6ccb 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
MikamiUitOpen 2:dcaee06f6ccb 516 {
MikamiUitOpen 2:dcaee06f6ccb 517 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 518
MikamiUitOpen 2:dcaee06f6ccb 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 2:dcaee06f6ccb 520 return(result);
MikamiUitOpen 2:dcaee06f6ccb 521 }
MikamiUitOpen 2:dcaee06f6ccb 522
MikamiUitOpen 2:dcaee06f6ccb 523
MikamiUitOpen 2:dcaee06f6ccb 524 /** \brief Reverse byte order in signed short value
MikamiUitOpen 2:dcaee06f6ccb 525
MikamiUitOpen 2:dcaee06f6ccb 526 This function reverses the byte order in a signed short value with sign extension to integer.
MikamiUitOpen 2:dcaee06f6ccb 527
MikamiUitOpen 2:dcaee06f6ccb 528 \param [in] value Value to reverse
MikamiUitOpen 2:dcaee06f6ccb 529 \return Reversed value
MikamiUitOpen 2:dcaee06f6ccb 530 */
MikamiUitOpen 2:dcaee06f6ccb 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
MikamiUitOpen 2:dcaee06f6ccb 532 {
MikamiUitOpen 2:dcaee06f6ccb 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 2:dcaee06f6ccb 534 return (short)__builtin_bswap16(value);
MikamiUitOpen 2:dcaee06f6ccb 535 #else
MikamiUitOpen 2:dcaee06f6ccb 536 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 537
MikamiUitOpen 2:dcaee06f6ccb 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 2:dcaee06f6ccb 539 return(result);
MikamiUitOpen 2:dcaee06f6ccb 540 #endif
MikamiUitOpen 2:dcaee06f6ccb 541 }
MikamiUitOpen 2:dcaee06f6ccb 542
MikamiUitOpen 2:dcaee06f6ccb 543
MikamiUitOpen 2:dcaee06f6ccb 544 /** \brief Rotate Right in unsigned value (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 545
MikamiUitOpen 2:dcaee06f6ccb 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
MikamiUitOpen 2:dcaee06f6ccb 547
MikamiUitOpen 2:dcaee06f6ccb 548 \param [in] value Value to rotate
MikamiUitOpen 2:dcaee06f6ccb 549 \param [in] value Number of Bits to rotate
MikamiUitOpen 2:dcaee06f6ccb 550 \return Rotated value
MikamiUitOpen 2:dcaee06f6ccb 551 */
MikamiUitOpen 2:dcaee06f6ccb 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
MikamiUitOpen 2:dcaee06f6ccb 553 {
MikamiUitOpen 2:dcaee06f6ccb 554 return (op1 >> op2) | (op1 << (32 - op2));
MikamiUitOpen 2:dcaee06f6ccb 555 }
MikamiUitOpen 2:dcaee06f6ccb 556
MikamiUitOpen 2:dcaee06f6ccb 557
MikamiUitOpen 2:dcaee06f6ccb 558 /** \brief Breakpoint
MikamiUitOpen 2:dcaee06f6ccb 559
MikamiUitOpen 2:dcaee06f6ccb 560 This function causes the processor to enter Debug state.
MikamiUitOpen 2:dcaee06f6ccb 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
MikamiUitOpen 2:dcaee06f6ccb 562
MikamiUitOpen 2:dcaee06f6ccb 563 \param [in] value is ignored by the processor.
MikamiUitOpen 2:dcaee06f6ccb 564 If required, a debugger can use it to store additional information about the breakpoint.
MikamiUitOpen 2:dcaee06f6ccb 565 */
MikamiUitOpen 2:dcaee06f6ccb 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
MikamiUitOpen 2:dcaee06f6ccb 567
MikamiUitOpen 2:dcaee06f6ccb 568
MikamiUitOpen 2:dcaee06f6ccb 569 /** \brief Reverse bit order of value
MikamiUitOpen 2:dcaee06f6ccb 570
MikamiUitOpen 2:dcaee06f6ccb 571 This function reverses the bit order of the given value.
MikamiUitOpen 2:dcaee06f6ccb 572
MikamiUitOpen 2:dcaee06f6ccb 573 \param [in] value Value to reverse
MikamiUitOpen 2:dcaee06f6ccb 574 \return Reversed value
MikamiUitOpen 2:dcaee06f6ccb 575 */
MikamiUitOpen 2:dcaee06f6ccb 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
MikamiUitOpen 2:dcaee06f6ccb 577 {
MikamiUitOpen 2:dcaee06f6ccb 578 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 579
MikamiUitOpen 2:dcaee06f6ccb 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 2:dcaee06f6ccb 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
MikamiUitOpen 2:dcaee06f6ccb 582 #else
MikamiUitOpen 2:dcaee06f6ccb 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
MikamiUitOpen 2:dcaee06f6ccb 584
MikamiUitOpen 2:dcaee06f6ccb 585 result = value; // r will be reversed bits of v; first get LSB of v
MikamiUitOpen 2:dcaee06f6ccb 586 for (value >>= 1; value; value >>= 1)
MikamiUitOpen 2:dcaee06f6ccb 587 {
MikamiUitOpen 2:dcaee06f6ccb 588 result <<= 1;
MikamiUitOpen 2:dcaee06f6ccb 589 result |= value & 1;
MikamiUitOpen 2:dcaee06f6ccb 590 s--;
MikamiUitOpen 2:dcaee06f6ccb 591 }
MikamiUitOpen 2:dcaee06f6ccb 592 result <<= s; // shift when v's highest bits are zero
MikamiUitOpen 2:dcaee06f6ccb 593 #endif
MikamiUitOpen 2:dcaee06f6ccb 594 return(result);
MikamiUitOpen 2:dcaee06f6ccb 595 }
MikamiUitOpen 2:dcaee06f6ccb 596
MikamiUitOpen 2:dcaee06f6ccb 597
MikamiUitOpen 2:dcaee06f6ccb 598 /** \brief Count leading zeros
MikamiUitOpen 2:dcaee06f6ccb 599
MikamiUitOpen 2:dcaee06f6ccb 600 This function counts the number of leading zeros of a data value.
MikamiUitOpen 2:dcaee06f6ccb 601
MikamiUitOpen 2:dcaee06f6ccb 602 \param [in] value Value to count the leading zeros
MikamiUitOpen 2:dcaee06f6ccb 603 \return number of leading zeros in value
MikamiUitOpen 2:dcaee06f6ccb 604 */
MikamiUitOpen 2:dcaee06f6ccb 605 #define __CLZ __builtin_clz
MikamiUitOpen 2:dcaee06f6ccb 606
MikamiUitOpen 2:dcaee06f6ccb 607
MikamiUitOpen 2:dcaee06f6ccb 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 2:dcaee06f6ccb 609
MikamiUitOpen 2:dcaee06f6ccb 610 /** \brief LDR Exclusive (8 bit)
MikamiUitOpen 2:dcaee06f6ccb 611
MikamiUitOpen 2:dcaee06f6ccb 612 This function executes a exclusive LDR instruction for 8 bit value.
MikamiUitOpen 2:dcaee06f6ccb 613
MikamiUitOpen 2:dcaee06f6ccb 614 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 615 \return value of type uint8_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 616 */
MikamiUitOpen 2:dcaee06f6ccb 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 618 {
MikamiUitOpen 2:dcaee06f6ccb 619 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 620
MikamiUitOpen 2:dcaee06f6ccb 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 2:dcaee06f6ccb 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 2:dcaee06f6ccb 623 #else
MikamiUitOpen 2:dcaee06f6ccb 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 2:dcaee06f6ccb 625 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 2:dcaee06f6ccb 626 */
MikamiUitOpen 2:dcaee06f6ccb 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 2:dcaee06f6ccb 628 #endif
MikamiUitOpen 2:dcaee06f6ccb 629 return ((uint8_t) result); /* Add explicit type cast here */
MikamiUitOpen 2:dcaee06f6ccb 630 }
MikamiUitOpen 2:dcaee06f6ccb 631
MikamiUitOpen 2:dcaee06f6ccb 632
MikamiUitOpen 2:dcaee06f6ccb 633 /** \brief LDR Exclusive (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 634
MikamiUitOpen 2:dcaee06f6ccb 635 This function executes a exclusive LDR instruction for 16 bit values.
MikamiUitOpen 2:dcaee06f6ccb 636
MikamiUitOpen 2:dcaee06f6ccb 637 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 638 \return value of type uint16_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 639 */
MikamiUitOpen 2:dcaee06f6ccb 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 641 {
MikamiUitOpen 2:dcaee06f6ccb 642 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 643
MikamiUitOpen 2:dcaee06f6ccb 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 2:dcaee06f6ccb 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 2:dcaee06f6ccb 646 #else
MikamiUitOpen 2:dcaee06f6ccb 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 2:dcaee06f6ccb 648 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 2:dcaee06f6ccb 649 */
MikamiUitOpen 2:dcaee06f6ccb 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 2:dcaee06f6ccb 651 #endif
MikamiUitOpen 2:dcaee06f6ccb 652 return ((uint16_t) result); /* Add explicit type cast here */
MikamiUitOpen 2:dcaee06f6ccb 653 }
MikamiUitOpen 2:dcaee06f6ccb 654
MikamiUitOpen 2:dcaee06f6ccb 655
MikamiUitOpen 2:dcaee06f6ccb 656 /** \brief LDR Exclusive (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 657
MikamiUitOpen 2:dcaee06f6ccb 658 This function executes a exclusive LDR instruction for 32 bit values.
MikamiUitOpen 2:dcaee06f6ccb 659
MikamiUitOpen 2:dcaee06f6ccb 660 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 661 \return value of type uint32_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 662 */
MikamiUitOpen 2:dcaee06f6ccb 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 664 {
MikamiUitOpen 2:dcaee06f6ccb 665 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 666
MikamiUitOpen 2:dcaee06f6ccb 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 2:dcaee06f6ccb 668 return(result);
MikamiUitOpen 2:dcaee06f6ccb 669 }
MikamiUitOpen 2:dcaee06f6ccb 670
MikamiUitOpen 2:dcaee06f6ccb 671
MikamiUitOpen 2:dcaee06f6ccb 672 /** \brief STR Exclusive (8 bit)
MikamiUitOpen 2:dcaee06f6ccb 673
MikamiUitOpen 2:dcaee06f6ccb 674 This function executes a exclusive STR instruction for 8 bit values.
MikamiUitOpen 2:dcaee06f6ccb 675
MikamiUitOpen 2:dcaee06f6ccb 676 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 677 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 678 \return 0 Function succeeded
MikamiUitOpen 2:dcaee06f6ccb 679 \return 1 Function failed
MikamiUitOpen 2:dcaee06f6ccb 680 */
MikamiUitOpen 2:dcaee06f6ccb 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 682 {
MikamiUitOpen 2:dcaee06f6ccb 683 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 684
MikamiUitOpen 2:dcaee06f6ccb 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 2:dcaee06f6ccb 686 return(result);
MikamiUitOpen 2:dcaee06f6ccb 687 }
MikamiUitOpen 2:dcaee06f6ccb 688
MikamiUitOpen 2:dcaee06f6ccb 689
MikamiUitOpen 2:dcaee06f6ccb 690 /** \brief STR Exclusive (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 691
MikamiUitOpen 2:dcaee06f6ccb 692 This function executes a exclusive STR instruction for 16 bit values.
MikamiUitOpen 2:dcaee06f6ccb 693
MikamiUitOpen 2:dcaee06f6ccb 694 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 695 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 696 \return 0 Function succeeded
MikamiUitOpen 2:dcaee06f6ccb 697 \return 1 Function failed
MikamiUitOpen 2:dcaee06f6ccb 698 */
MikamiUitOpen 2:dcaee06f6ccb 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 700 {
MikamiUitOpen 2:dcaee06f6ccb 701 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 702
MikamiUitOpen 2:dcaee06f6ccb 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 2:dcaee06f6ccb 704 return(result);
MikamiUitOpen 2:dcaee06f6ccb 705 }
MikamiUitOpen 2:dcaee06f6ccb 706
MikamiUitOpen 2:dcaee06f6ccb 707
MikamiUitOpen 2:dcaee06f6ccb 708 /** \brief STR Exclusive (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 709
MikamiUitOpen 2:dcaee06f6ccb 710 This function executes a exclusive STR instruction for 32 bit values.
MikamiUitOpen 2:dcaee06f6ccb 711
MikamiUitOpen 2:dcaee06f6ccb 712 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 713 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 714 \return 0 Function succeeded
MikamiUitOpen 2:dcaee06f6ccb 715 \return 1 Function failed
MikamiUitOpen 2:dcaee06f6ccb 716 */
MikamiUitOpen 2:dcaee06f6ccb 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 718 {
MikamiUitOpen 2:dcaee06f6ccb 719 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 720
MikamiUitOpen 2:dcaee06f6ccb 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
MikamiUitOpen 2:dcaee06f6ccb 722 return(result);
MikamiUitOpen 2:dcaee06f6ccb 723 }
MikamiUitOpen 2:dcaee06f6ccb 724
MikamiUitOpen 2:dcaee06f6ccb 725
MikamiUitOpen 2:dcaee06f6ccb 726 /** \brief Remove the exclusive lock
MikamiUitOpen 2:dcaee06f6ccb 727
MikamiUitOpen 2:dcaee06f6ccb 728 This function removes the exclusive lock which is created by LDREX.
MikamiUitOpen 2:dcaee06f6ccb 729
MikamiUitOpen 2:dcaee06f6ccb 730 */
MikamiUitOpen 2:dcaee06f6ccb 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
MikamiUitOpen 2:dcaee06f6ccb 732 {
MikamiUitOpen 2:dcaee06f6ccb 733 __ASM volatile ("clrex" ::: "memory");
MikamiUitOpen 2:dcaee06f6ccb 734 }
MikamiUitOpen 2:dcaee06f6ccb 735
MikamiUitOpen 2:dcaee06f6ccb 736
MikamiUitOpen 2:dcaee06f6ccb 737 /** \brief Signed Saturate
MikamiUitOpen 2:dcaee06f6ccb 738
MikamiUitOpen 2:dcaee06f6ccb 739 This function saturates a signed value.
MikamiUitOpen 2:dcaee06f6ccb 740
MikamiUitOpen 2:dcaee06f6ccb 741 \param [in] value Value to be saturated
MikamiUitOpen 2:dcaee06f6ccb 742 \param [in] sat Bit position to saturate to (1..32)
MikamiUitOpen 2:dcaee06f6ccb 743 \return Saturated value
MikamiUitOpen 2:dcaee06f6ccb 744 */
MikamiUitOpen 2:dcaee06f6ccb 745 #define __SSAT(ARG1,ARG2) \
MikamiUitOpen 2:dcaee06f6ccb 746 ({ \
MikamiUitOpen 2:dcaee06f6ccb 747 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 2:dcaee06f6ccb 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 2:dcaee06f6ccb 749 __RES; \
MikamiUitOpen 2:dcaee06f6ccb 750 })
MikamiUitOpen 2:dcaee06f6ccb 751
MikamiUitOpen 2:dcaee06f6ccb 752
MikamiUitOpen 2:dcaee06f6ccb 753 /** \brief Unsigned Saturate
MikamiUitOpen 2:dcaee06f6ccb 754
MikamiUitOpen 2:dcaee06f6ccb 755 This function saturates an unsigned value.
MikamiUitOpen 2:dcaee06f6ccb 756
MikamiUitOpen 2:dcaee06f6ccb 757 \param [in] value Value to be saturated
MikamiUitOpen 2:dcaee06f6ccb 758 \param [in] sat Bit position to saturate to (0..31)
MikamiUitOpen 2:dcaee06f6ccb 759 \return Saturated value
MikamiUitOpen 2:dcaee06f6ccb 760 */
MikamiUitOpen 2:dcaee06f6ccb 761 #define __USAT(ARG1,ARG2) \
MikamiUitOpen 2:dcaee06f6ccb 762 ({ \
MikamiUitOpen 2:dcaee06f6ccb 763 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 2:dcaee06f6ccb 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 2:dcaee06f6ccb 765 __RES; \
MikamiUitOpen 2:dcaee06f6ccb 766 })
MikamiUitOpen 2:dcaee06f6ccb 767
MikamiUitOpen 2:dcaee06f6ccb 768
MikamiUitOpen 2:dcaee06f6ccb 769 /** \brief Rotate Right with Extend (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 770
MikamiUitOpen 2:dcaee06f6ccb 771 This function moves each bit of a bitstring right by one bit.
MikamiUitOpen 2:dcaee06f6ccb 772 The carry input is shifted in at the left end of the bitstring.
MikamiUitOpen 2:dcaee06f6ccb 773
MikamiUitOpen 2:dcaee06f6ccb 774 \param [in] value Value to rotate
MikamiUitOpen 2:dcaee06f6ccb 775 \return Rotated value
MikamiUitOpen 2:dcaee06f6ccb 776 */
MikamiUitOpen 2:dcaee06f6ccb 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
MikamiUitOpen 2:dcaee06f6ccb 778 {
MikamiUitOpen 2:dcaee06f6ccb 779 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 780
MikamiUitOpen 2:dcaee06f6ccb 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 2:dcaee06f6ccb 782 return(result);
MikamiUitOpen 2:dcaee06f6ccb 783 }
MikamiUitOpen 2:dcaee06f6ccb 784
MikamiUitOpen 2:dcaee06f6ccb 785
MikamiUitOpen 2:dcaee06f6ccb 786 /** \brief LDRT Unprivileged (8 bit)
MikamiUitOpen 2:dcaee06f6ccb 787
MikamiUitOpen 2:dcaee06f6ccb 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
MikamiUitOpen 2:dcaee06f6ccb 789
MikamiUitOpen 2:dcaee06f6ccb 790 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 791 \return value of type uint8_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 792 */
MikamiUitOpen 2:dcaee06f6ccb 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 794 {
MikamiUitOpen 2:dcaee06f6ccb 795 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 796
MikamiUitOpen 2:dcaee06f6ccb 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 2:dcaee06f6ccb 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 2:dcaee06f6ccb 799 #else
MikamiUitOpen 2:dcaee06f6ccb 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 2:dcaee06f6ccb 801 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 2:dcaee06f6ccb 802 */
MikamiUitOpen 2:dcaee06f6ccb 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 2:dcaee06f6ccb 804 #endif
MikamiUitOpen 2:dcaee06f6ccb 805 return ((uint8_t) result); /* Add explicit type cast here */
MikamiUitOpen 2:dcaee06f6ccb 806 }
MikamiUitOpen 2:dcaee06f6ccb 807
MikamiUitOpen 2:dcaee06f6ccb 808
MikamiUitOpen 2:dcaee06f6ccb 809 /** \brief LDRT Unprivileged (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 810
MikamiUitOpen 2:dcaee06f6ccb 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
MikamiUitOpen 2:dcaee06f6ccb 812
MikamiUitOpen 2:dcaee06f6ccb 813 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 814 \return value of type uint16_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 815 */
MikamiUitOpen 2:dcaee06f6ccb 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 817 {
MikamiUitOpen 2:dcaee06f6ccb 818 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 819
MikamiUitOpen 2:dcaee06f6ccb 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 2:dcaee06f6ccb 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 2:dcaee06f6ccb 822 #else
MikamiUitOpen 2:dcaee06f6ccb 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 2:dcaee06f6ccb 824 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 2:dcaee06f6ccb 825 */
MikamiUitOpen 2:dcaee06f6ccb 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 2:dcaee06f6ccb 827 #endif
MikamiUitOpen 2:dcaee06f6ccb 828 return ((uint16_t) result); /* Add explicit type cast here */
MikamiUitOpen 2:dcaee06f6ccb 829 }
MikamiUitOpen 2:dcaee06f6ccb 830
MikamiUitOpen 2:dcaee06f6ccb 831
MikamiUitOpen 2:dcaee06f6ccb 832 /** \brief LDRT Unprivileged (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 833
MikamiUitOpen 2:dcaee06f6ccb 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
MikamiUitOpen 2:dcaee06f6ccb 835
MikamiUitOpen 2:dcaee06f6ccb 836 \param [in] ptr Pointer to data
MikamiUitOpen 2:dcaee06f6ccb 837 \return value of type uint32_t at (*ptr)
MikamiUitOpen 2:dcaee06f6ccb 838 */
MikamiUitOpen 2:dcaee06f6ccb 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 840 {
MikamiUitOpen 2:dcaee06f6ccb 841 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 842
MikamiUitOpen 2:dcaee06f6ccb 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 2:dcaee06f6ccb 844 return(result);
MikamiUitOpen 2:dcaee06f6ccb 845 }
MikamiUitOpen 2:dcaee06f6ccb 846
MikamiUitOpen 2:dcaee06f6ccb 847
MikamiUitOpen 2:dcaee06f6ccb 848 /** \brief STRT Unprivileged (8 bit)
MikamiUitOpen 2:dcaee06f6ccb 849
MikamiUitOpen 2:dcaee06f6ccb 850 This function executes a Unprivileged STRT instruction for 8 bit values.
MikamiUitOpen 2:dcaee06f6ccb 851
MikamiUitOpen 2:dcaee06f6ccb 852 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 853 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 854 */
MikamiUitOpen 2:dcaee06f6ccb 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 856 {
MikamiUitOpen 2:dcaee06f6ccb 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 2:dcaee06f6ccb 858 }
MikamiUitOpen 2:dcaee06f6ccb 859
MikamiUitOpen 2:dcaee06f6ccb 860
MikamiUitOpen 2:dcaee06f6ccb 861 /** \brief STRT Unprivileged (16 bit)
MikamiUitOpen 2:dcaee06f6ccb 862
MikamiUitOpen 2:dcaee06f6ccb 863 This function executes a Unprivileged STRT instruction for 16 bit values.
MikamiUitOpen 2:dcaee06f6ccb 864
MikamiUitOpen 2:dcaee06f6ccb 865 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 866 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 867 */
MikamiUitOpen 2:dcaee06f6ccb 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 869 {
MikamiUitOpen 2:dcaee06f6ccb 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 2:dcaee06f6ccb 871 }
MikamiUitOpen 2:dcaee06f6ccb 872
MikamiUitOpen 2:dcaee06f6ccb 873
MikamiUitOpen 2:dcaee06f6ccb 874 /** \brief STRT Unprivileged (32 bit)
MikamiUitOpen 2:dcaee06f6ccb 875
MikamiUitOpen 2:dcaee06f6ccb 876 This function executes a Unprivileged STRT instruction for 32 bit values.
MikamiUitOpen 2:dcaee06f6ccb 877
MikamiUitOpen 2:dcaee06f6ccb 878 \param [in] value Value to store
MikamiUitOpen 2:dcaee06f6ccb 879 \param [in] ptr Pointer to location
MikamiUitOpen 2:dcaee06f6ccb 880 */
MikamiUitOpen 2:dcaee06f6ccb 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
MikamiUitOpen 2:dcaee06f6ccb 882 {
MikamiUitOpen 2:dcaee06f6ccb 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
MikamiUitOpen 2:dcaee06f6ccb 884 }
MikamiUitOpen 2:dcaee06f6ccb 885
MikamiUitOpen 2:dcaee06f6ccb 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 2:dcaee06f6ccb 887
MikamiUitOpen 2:dcaee06f6ccb 888
MikamiUitOpen 2:dcaee06f6ccb 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 2:dcaee06f6ccb 890 /* IAR iccarm specific functions */
MikamiUitOpen 2:dcaee06f6ccb 891 #include <cmsis_iar.h>
MikamiUitOpen 2:dcaee06f6ccb 892
MikamiUitOpen 2:dcaee06f6ccb 893
MikamiUitOpen 2:dcaee06f6ccb 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 2:dcaee06f6ccb 895 /* TI CCS specific functions */
MikamiUitOpen 2:dcaee06f6ccb 896 #include <cmsis_ccs.h>
MikamiUitOpen 2:dcaee06f6ccb 897
MikamiUitOpen 2:dcaee06f6ccb 898
MikamiUitOpen 2:dcaee06f6ccb 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 2:dcaee06f6ccb 900 /* TASKING carm specific functions */
MikamiUitOpen 2:dcaee06f6ccb 901 /*
MikamiUitOpen 2:dcaee06f6ccb 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
MikamiUitOpen 2:dcaee06f6ccb 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
MikamiUitOpen 2:dcaee06f6ccb 904 * Including the CMSIS ones.
MikamiUitOpen 2:dcaee06f6ccb 905 */
MikamiUitOpen 2:dcaee06f6ccb 906
MikamiUitOpen 2:dcaee06f6ccb 907
MikamiUitOpen 2:dcaee06f6ccb 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MikamiUitOpen 2:dcaee06f6ccb 909 /* Cosmic specific functions */
MikamiUitOpen 2:dcaee06f6ccb 910 #include <cmsis_csm.h>
MikamiUitOpen 2:dcaee06f6ccb 911
MikamiUitOpen 2:dcaee06f6ccb 912 #endif
MikamiUitOpen 2:dcaee06f6ccb 913
MikamiUitOpen 2:dcaee06f6ccb 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
MikamiUitOpen 2:dcaee06f6ccb 915
MikamiUitOpen 2:dcaee06f6ccb 916 #endif /* __CORE_CMINSTR_H */