不韋 呂 / F746_SD_VarableFilter

SD card player with variable cotoff frequency lowpass and highpass IIR filter. SD カードの *.wav ファイルのオーディオ信号を，遮断周波数可変 IIR 低域通過および高域通過フィルタを通して，ボードに搭載されているCODEC で出力する．このプログラムについては，CQ出版社インターフェース誌 2018年8月号で解説している．

Dependencies:   F746_GUI F746_SAI_IO FrequencyResponseDrawer SD_PlayerSkeleton

mbed_src_STM32F7/targets/cmsis/core_cmFunc.h@11:399670d24ed9, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 01:44:22 2017 +0000
Revision:
11:399670d24ed9
Parent:
2:dcaee06f6ccb 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 2:dcaee06f6ccb 1 /**************************************************************************//**
MikamiUitOpen 2:dcaee06f6ccb 2 * @file core_cmFunc.h
MikamiUitOpen 2:dcaee06f6ccb 3 * @brief CMSIS Cortex-M Core Function Access Header File
MikamiUitOpen 2:dcaee06f6ccb 4 * @version V4.10
MikamiUitOpen 2:dcaee06f6ccb 5 * @date 18. March 2015
MikamiUitOpen 2:dcaee06f6ccb 6 *
MikamiUitOpen 2:dcaee06f6ccb 7 * @note
MikamiUitOpen 2:dcaee06f6ccb 8 *
MikamiUitOpen 2:dcaee06f6ccb 9 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 2:dcaee06f6ccb 11
MikamiUitOpen 2:dcaee06f6ccb 12 All rights reserved.
MikamiUitOpen 2:dcaee06f6ccb 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 2:dcaee06f6ccb 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 2:dcaee06f6ccb 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 2:dcaee06f6ccb 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 2:dcaee06f6ccb 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 2:dcaee06f6ccb 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 2:dcaee06f6ccb 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 2:dcaee06f6ccb 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 2:dcaee06f6ccb 21 to endorse or promote products derived from this software without
MikamiUitOpen 2:dcaee06f6ccb 22 specific prior written permission.
MikamiUitOpen 2:dcaee06f6ccb 23 *
MikamiUitOpen 2:dcaee06f6ccb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 2:dcaee06f6ccb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 2:dcaee06f6ccb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 2:dcaee06f6ccb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 2:dcaee06f6ccb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 2:dcaee06f6ccb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 2:dcaee06f6ccb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 2:dcaee06f6ccb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 2:dcaee06f6ccb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 2:dcaee06f6ccb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 2:dcaee06f6ccb 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 2:dcaee06f6ccb 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 2:dcaee06f6ccb 36
MikamiUitOpen 2:dcaee06f6ccb 37
MikamiUitOpen 2:dcaee06f6ccb 38 #ifndef __CORE_CMFUNC_H
MikamiUitOpen 2:dcaee06f6ccb 39 #define __CORE_CMFUNC_H
MikamiUitOpen 2:dcaee06f6ccb 40
MikamiUitOpen 2:dcaee06f6ccb 41
MikamiUitOpen 2:dcaee06f6ccb 42 /* ########################### Core Function Access ########################### */
MikamiUitOpen 2:dcaee06f6ccb 43 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 2:dcaee06f6ccb 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
MikamiUitOpen 2:dcaee06f6ccb 45 @{
MikamiUitOpen 2:dcaee06f6ccb 46 */
MikamiUitOpen 2:dcaee06f6ccb 47
MikamiUitOpen 2:dcaee06f6ccb 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 2:dcaee06f6ccb 49 /* ARM armcc specific functions */
MikamiUitOpen 2:dcaee06f6ccb 50
MikamiUitOpen 2:dcaee06f6ccb 51 #if (__ARMCC_VERSION < 400677)
MikamiUitOpen 2:dcaee06f6ccb 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MikamiUitOpen 2:dcaee06f6ccb 53 #endif
MikamiUitOpen 2:dcaee06f6ccb 54
MikamiUitOpen 2:dcaee06f6ccb 55 /* intrinsic void __enable_irq(); */
MikamiUitOpen 2:dcaee06f6ccb 56 /* intrinsic void __disable_irq(); */
MikamiUitOpen 2:dcaee06f6ccb 57
MikamiUitOpen 2:dcaee06f6ccb 58 /** \brief Get Control Register
MikamiUitOpen 2:dcaee06f6ccb 59
MikamiUitOpen 2:dcaee06f6ccb 60 This function returns the content of the Control Register.
MikamiUitOpen 2:dcaee06f6ccb 61
MikamiUitOpen 2:dcaee06f6ccb 62 \return Control Register value
MikamiUitOpen 2:dcaee06f6ccb 63 */
MikamiUitOpen 2:dcaee06f6ccb 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
MikamiUitOpen 2:dcaee06f6ccb 65 {
MikamiUitOpen 2:dcaee06f6ccb 66 register uint32_t __regControl __ASM("control");
MikamiUitOpen 2:dcaee06f6ccb 67 return(__regControl);
MikamiUitOpen 2:dcaee06f6ccb 68 }
MikamiUitOpen 2:dcaee06f6ccb 69
MikamiUitOpen 2:dcaee06f6ccb 70
MikamiUitOpen 2:dcaee06f6ccb 71 /** \brief Set Control Register
MikamiUitOpen 2:dcaee06f6ccb 72
MikamiUitOpen 2:dcaee06f6ccb 73 This function writes the given value to the Control Register.
MikamiUitOpen 2:dcaee06f6ccb 74
MikamiUitOpen 2:dcaee06f6ccb 75 \param [in] control Control Register value to set
MikamiUitOpen 2:dcaee06f6ccb 76 */
MikamiUitOpen 2:dcaee06f6ccb 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
MikamiUitOpen 2:dcaee06f6ccb 78 {
MikamiUitOpen 2:dcaee06f6ccb 79 register uint32_t __regControl __ASM("control");
MikamiUitOpen 2:dcaee06f6ccb 80 __regControl = control;
MikamiUitOpen 2:dcaee06f6ccb 81 }
MikamiUitOpen 2:dcaee06f6ccb 82
MikamiUitOpen 2:dcaee06f6ccb 83
MikamiUitOpen 2:dcaee06f6ccb 84 /** \brief Get IPSR Register
MikamiUitOpen 2:dcaee06f6ccb 85
MikamiUitOpen 2:dcaee06f6ccb 86 This function returns the content of the IPSR Register.
MikamiUitOpen 2:dcaee06f6ccb 87
MikamiUitOpen 2:dcaee06f6ccb 88 \return IPSR Register value
MikamiUitOpen 2:dcaee06f6ccb 89 */
MikamiUitOpen 2:dcaee06f6ccb 90 __STATIC_INLINE uint32_t __get_IPSR(void)
MikamiUitOpen 2:dcaee06f6ccb 91 {
MikamiUitOpen 2:dcaee06f6ccb 92 register uint32_t __regIPSR __ASM("ipsr");
MikamiUitOpen 2:dcaee06f6ccb 93 return(__regIPSR);
MikamiUitOpen 2:dcaee06f6ccb 94 }
MikamiUitOpen 2:dcaee06f6ccb 95
MikamiUitOpen 2:dcaee06f6ccb 96
MikamiUitOpen 2:dcaee06f6ccb 97 /** \brief Get APSR Register
MikamiUitOpen 2:dcaee06f6ccb 98
MikamiUitOpen 2:dcaee06f6ccb 99 This function returns the content of the APSR Register.
MikamiUitOpen 2:dcaee06f6ccb 100
MikamiUitOpen 2:dcaee06f6ccb 101 \return APSR Register value
MikamiUitOpen 2:dcaee06f6ccb 102 */
MikamiUitOpen 2:dcaee06f6ccb 103 __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 2:dcaee06f6ccb 104 {
MikamiUitOpen 2:dcaee06f6ccb 105 register uint32_t __regAPSR __ASM("apsr");
MikamiUitOpen 2:dcaee06f6ccb 106 return(__regAPSR);
MikamiUitOpen 2:dcaee06f6ccb 107 }
MikamiUitOpen 2:dcaee06f6ccb 108
MikamiUitOpen 2:dcaee06f6ccb 109
MikamiUitOpen 2:dcaee06f6ccb 110 /** \brief Get xPSR Register
MikamiUitOpen 2:dcaee06f6ccb 111
MikamiUitOpen 2:dcaee06f6ccb 112 This function returns the content of the xPSR Register.
MikamiUitOpen 2:dcaee06f6ccb 113
MikamiUitOpen 2:dcaee06f6ccb 114 \return xPSR Register value
MikamiUitOpen 2:dcaee06f6ccb 115 */
MikamiUitOpen 2:dcaee06f6ccb 116 __STATIC_INLINE uint32_t __get_xPSR(void)
MikamiUitOpen 2:dcaee06f6ccb 117 {
MikamiUitOpen 2:dcaee06f6ccb 118 register uint32_t __regXPSR __ASM("xpsr");
MikamiUitOpen 2:dcaee06f6ccb 119 return(__regXPSR);
MikamiUitOpen 2:dcaee06f6ccb 120 }
MikamiUitOpen 2:dcaee06f6ccb 121
MikamiUitOpen 2:dcaee06f6ccb 122
MikamiUitOpen 2:dcaee06f6ccb 123 /** \brief Get Process Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 124
MikamiUitOpen 2:dcaee06f6ccb 125 This function returns the current value of the Process Stack Pointer (PSP).
MikamiUitOpen 2:dcaee06f6ccb 126
MikamiUitOpen 2:dcaee06f6ccb 127 \return PSP Register value
MikamiUitOpen 2:dcaee06f6ccb 128 */
MikamiUitOpen 2:dcaee06f6ccb 129 __STATIC_INLINE uint32_t __get_PSP(void)
MikamiUitOpen 2:dcaee06f6ccb 130 {
MikamiUitOpen 2:dcaee06f6ccb 131 register uint32_t __regProcessStackPointer __ASM("psp");
MikamiUitOpen 2:dcaee06f6ccb 132 return(__regProcessStackPointer);
MikamiUitOpen 2:dcaee06f6ccb 133 }
MikamiUitOpen 2:dcaee06f6ccb 134
MikamiUitOpen 2:dcaee06f6ccb 135
MikamiUitOpen 2:dcaee06f6ccb 136 /** \brief Set Process Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 137
MikamiUitOpen 2:dcaee06f6ccb 138 This function assigns the given value to the Process Stack Pointer (PSP).
MikamiUitOpen 2:dcaee06f6ccb 139
MikamiUitOpen 2:dcaee06f6ccb 140 \param [in] topOfProcStack Process Stack Pointer value to set
MikamiUitOpen 2:dcaee06f6ccb 141 */
MikamiUitOpen 2:dcaee06f6ccb 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 2:dcaee06f6ccb 143 {
MikamiUitOpen 2:dcaee06f6ccb 144 register uint32_t __regProcessStackPointer __ASM("psp");
MikamiUitOpen 2:dcaee06f6ccb 145 __regProcessStackPointer = topOfProcStack;
MikamiUitOpen 2:dcaee06f6ccb 146 }
MikamiUitOpen 2:dcaee06f6ccb 147
MikamiUitOpen 2:dcaee06f6ccb 148
MikamiUitOpen 2:dcaee06f6ccb 149 /** \brief Get Main Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 150
MikamiUitOpen 2:dcaee06f6ccb 151 This function returns the current value of the Main Stack Pointer (MSP).
MikamiUitOpen 2:dcaee06f6ccb 152
MikamiUitOpen 2:dcaee06f6ccb 153 \return MSP Register value
MikamiUitOpen 2:dcaee06f6ccb 154 */
MikamiUitOpen 2:dcaee06f6ccb 155 __STATIC_INLINE uint32_t __get_MSP(void)
MikamiUitOpen 2:dcaee06f6ccb 156 {
MikamiUitOpen 2:dcaee06f6ccb 157 register uint32_t __regMainStackPointer __ASM("msp");
MikamiUitOpen 2:dcaee06f6ccb 158 return(__regMainStackPointer);
MikamiUitOpen 2:dcaee06f6ccb 159 }
MikamiUitOpen 2:dcaee06f6ccb 160
MikamiUitOpen 2:dcaee06f6ccb 161
MikamiUitOpen 2:dcaee06f6ccb 162 /** \brief Set Main Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 163
MikamiUitOpen 2:dcaee06f6ccb 164 This function assigns the given value to the Main Stack Pointer (MSP).
MikamiUitOpen 2:dcaee06f6ccb 165
MikamiUitOpen 2:dcaee06f6ccb 166 \param [in] topOfMainStack Main Stack Pointer value to set
MikamiUitOpen 2:dcaee06f6ccb 167 */
MikamiUitOpen 2:dcaee06f6ccb 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MikamiUitOpen 2:dcaee06f6ccb 169 {
MikamiUitOpen 2:dcaee06f6ccb 170 register uint32_t __regMainStackPointer __ASM("msp");
MikamiUitOpen 2:dcaee06f6ccb 171 __regMainStackPointer = topOfMainStack;
MikamiUitOpen 2:dcaee06f6ccb 172 }
MikamiUitOpen 2:dcaee06f6ccb 173
MikamiUitOpen 2:dcaee06f6ccb 174
MikamiUitOpen 2:dcaee06f6ccb 175 /** \brief Get Priority Mask
MikamiUitOpen 2:dcaee06f6ccb 176
MikamiUitOpen 2:dcaee06f6ccb 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
MikamiUitOpen 2:dcaee06f6ccb 178
MikamiUitOpen 2:dcaee06f6ccb 179 \return Priority Mask value
MikamiUitOpen 2:dcaee06f6ccb 180 */
MikamiUitOpen 2:dcaee06f6ccb 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
MikamiUitOpen 2:dcaee06f6ccb 182 {
MikamiUitOpen 2:dcaee06f6ccb 183 register uint32_t __regPriMask __ASM("primask");
MikamiUitOpen 2:dcaee06f6ccb 184 return(__regPriMask);
MikamiUitOpen 2:dcaee06f6ccb 185 }
MikamiUitOpen 2:dcaee06f6ccb 186
MikamiUitOpen 2:dcaee06f6ccb 187
MikamiUitOpen 2:dcaee06f6ccb 188 /** \brief Set Priority Mask
MikamiUitOpen 2:dcaee06f6ccb 189
MikamiUitOpen 2:dcaee06f6ccb 190 This function assigns the given value to the Priority Mask Register.
MikamiUitOpen 2:dcaee06f6ccb 191
MikamiUitOpen 2:dcaee06f6ccb 192 \param [in] priMask Priority Mask
MikamiUitOpen 2:dcaee06f6ccb 193 */
MikamiUitOpen 2:dcaee06f6ccb 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MikamiUitOpen 2:dcaee06f6ccb 195 {
MikamiUitOpen 2:dcaee06f6ccb 196 register uint32_t __regPriMask __ASM("primask");
MikamiUitOpen 2:dcaee06f6ccb 197 __regPriMask = (priMask);
MikamiUitOpen 2:dcaee06f6ccb 198 }
MikamiUitOpen 2:dcaee06f6ccb 199
MikamiUitOpen 2:dcaee06f6ccb 200
MikamiUitOpen 2:dcaee06f6ccb 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 2:dcaee06f6ccb 202
MikamiUitOpen 2:dcaee06f6ccb 203 /** \brief Enable FIQ
MikamiUitOpen 2:dcaee06f6ccb 204
MikamiUitOpen 2:dcaee06f6ccb 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 206 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 207 */
MikamiUitOpen 2:dcaee06f6ccb 208 #define __enable_fault_irq __enable_fiq
MikamiUitOpen 2:dcaee06f6ccb 209
MikamiUitOpen 2:dcaee06f6ccb 210
MikamiUitOpen 2:dcaee06f6ccb 211 /** \brief Disable FIQ
MikamiUitOpen 2:dcaee06f6ccb 212
MikamiUitOpen 2:dcaee06f6ccb 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 214 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 215 */
MikamiUitOpen 2:dcaee06f6ccb 216 #define __disable_fault_irq __disable_fiq
MikamiUitOpen 2:dcaee06f6ccb 217
MikamiUitOpen 2:dcaee06f6ccb 218
MikamiUitOpen 2:dcaee06f6ccb 219 /** \brief Get Base Priority
MikamiUitOpen 2:dcaee06f6ccb 220
MikamiUitOpen 2:dcaee06f6ccb 221 This function returns the current value of the Base Priority register.
MikamiUitOpen 2:dcaee06f6ccb 222
MikamiUitOpen 2:dcaee06f6ccb 223 \return Base Priority register value
MikamiUitOpen 2:dcaee06f6ccb 224 */
MikamiUitOpen 2:dcaee06f6ccb 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
MikamiUitOpen 2:dcaee06f6ccb 226 {
MikamiUitOpen 2:dcaee06f6ccb 227 register uint32_t __regBasePri __ASM("basepri");
MikamiUitOpen 2:dcaee06f6ccb 228 return(__regBasePri);
MikamiUitOpen 2:dcaee06f6ccb 229 }
MikamiUitOpen 2:dcaee06f6ccb 230
MikamiUitOpen 2:dcaee06f6ccb 231
MikamiUitOpen 2:dcaee06f6ccb 232 /** \brief Set Base Priority
MikamiUitOpen 2:dcaee06f6ccb 233
MikamiUitOpen 2:dcaee06f6ccb 234 This function assigns the given value to the Base Priority register.
MikamiUitOpen 2:dcaee06f6ccb 235
MikamiUitOpen 2:dcaee06f6ccb 236 \param [in] basePri Base Priority value to set
MikamiUitOpen 2:dcaee06f6ccb 237 */
MikamiUitOpen 2:dcaee06f6ccb 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
MikamiUitOpen 2:dcaee06f6ccb 239 {
MikamiUitOpen 2:dcaee06f6ccb 240 register uint32_t __regBasePri __ASM("basepri");
MikamiUitOpen 2:dcaee06f6ccb 241 __regBasePri = (basePri & 0xff);
MikamiUitOpen 2:dcaee06f6ccb 242 }
MikamiUitOpen 2:dcaee06f6ccb 243
MikamiUitOpen 2:dcaee06f6ccb 244
MikamiUitOpen 2:dcaee06f6ccb 245 /** \brief Set Base Priority with condition
MikamiUitOpen 2:dcaee06f6ccb 246
MikamiUitOpen 2:dcaee06f6ccb 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MikamiUitOpen 2:dcaee06f6ccb 248 or the new value increases the BASEPRI priority level.
MikamiUitOpen 2:dcaee06f6ccb 249
MikamiUitOpen 2:dcaee06f6ccb 250 \param [in] basePri Base Priority value to set
MikamiUitOpen 2:dcaee06f6ccb 251 */
MikamiUitOpen 2:dcaee06f6ccb 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
MikamiUitOpen 2:dcaee06f6ccb 253 {
MikamiUitOpen 2:dcaee06f6ccb 254 register uint32_t __regBasePriMax __ASM("basepri_max");
MikamiUitOpen 2:dcaee06f6ccb 255 __regBasePriMax = (basePri & 0xff);
MikamiUitOpen 2:dcaee06f6ccb 256 }
MikamiUitOpen 2:dcaee06f6ccb 257
MikamiUitOpen 2:dcaee06f6ccb 258
MikamiUitOpen 2:dcaee06f6ccb 259 /** \brief Get Fault Mask
MikamiUitOpen 2:dcaee06f6ccb 260
MikamiUitOpen 2:dcaee06f6ccb 261 This function returns the current value of the Fault Mask register.
MikamiUitOpen 2:dcaee06f6ccb 262
MikamiUitOpen 2:dcaee06f6ccb 263 \return Fault Mask register value
MikamiUitOpen 2:dcaee06f6ccb 264 */
MikamiUitOpen 2:dcaee06f6ccb 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MikamiUitOpen 2:dcaee06f6ccb 266 {
MikamiUitOpen 2:dcaee06f6ccb 267 register uint32_t __regFaultMask __ASM("faultmask");
MikamiUitOpen 2:dcaee06f6ccb 268 return(__regFaultMask);
MikamiUitOpen 2:dcaee06f6ccb 269 }
MikamiUitOpen 2:dcaee06f6ccb 270
MikamiUitOpen 2:dcaee06f6ccb 271
MikamiUitOpen 2:dcaee06f6ccb 272 /** \brief Set Fault Mask
MikamiUitOpen 2:dcaee06f6ccb 273
MikamiUitOpen 2:dcaee06f6ccb 274 This function assigns the given value to the Fault Mask register.
MikamiUitOpen 2:dcaee06f6ccb 275
MikamiUitOpen 2:dcaee06f6ccb 276 \param [in] faultMask Fault Mask value to set
MikamiUitOpen 2:dcaee06f6ccb 277 */
MikamiUitOpen 2:dcaee06f6ccb 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MikamiUitOpen 2:dcaee06f6ccb 279 {
MikamiUitOpen 2:dcaee06f6ccb 280 register uint32_t __regFaultMask __ASM("faultmask");
MikamiUitOpen 2:dcaee06f6ccb 281 __regFaultMask = (faultMask & (uint32_t)1);
MikamiUitOpen 2:dcaee06f6ccb 282 }
MikamiUitOpen 2:dcaee06f6ccb 283
MikamiUitOpen 2:dcaee06f6ccb 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 2:dcaee06f6ccb 285
MikamiUitOpen 2:dcaee06f6ccb 286
MikamiUitOpen 2:dcaee06f6ccb 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MikamiUitOpen 2:dcaee06f6ccb 288
MikamiUitOpen 2:dcaee06f6ccb 289 /** \brief Get FPSCR
MikamiUitOpen 2:dcaee06f6ccb 290
MikamiUitOpen 2:dcaee06f6ccb 291 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 2:dcaee06f6ccb 292
MikamiUitOpen 2:dcaee06f6ccb 293 \return Floating Point Status/Control register value
MikamiUitOpen 2:dcaee06f6ccb 294 */
MikamiUitOpen 2:dcaee06f6ccb 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 2:dcaee06f6ccb 296 {
MikamiUitOpen 2:dcaee06f6ccb 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 2:dcaee06f6ccb 298 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 2:dcaee06f6ccb 299 return(__regfpscr);
MikamiUitOpen 2:dcaee06f6ccb 300 #else
MikamiUitOpen 2:dcaee06f6ccb 301 return(0);
MikamiUitOpen 2:dcaee06f6ccb 302 #endif
MikamiUitOpen 2:dcaee06f6ccb 303 }
MikamiUitOpen 2:dcaee06f6ccb 304
MikamiUitOpen 2:dcaee06f6ccb 305
MikamiUitOpen 2:dcaee06f6ccb 306 /** \brief Set FPSCR
MikamiUitOpen 2:dcaee06f6ccb 307
MikamiUitOpen 2:dcaee06f6ccb 308 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 2:dcaee06f6ccb 309
MikamiUitOpen 2:dcaee06f6ccb 310 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 2:dcaee06f6ccb 311 */
MikamiUitOpen 2:dcaee06f6ccb 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 2:dcaee06f6ccb 313 {
MikamiUitOpen 2:dcaee06f6ccb 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 2:dcaee06f6ccb 315 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 2:dcaee06f6ccb 316 __regfpscr = (fpscr);
MikamiUitOpen 2:dcaee06f6ccb 317 #endif
MikamiUitOpen 2:dcaee06f6ccb 318 }
MikamiUitOpen 2:dcaee06f6ccb 319
MikamiUitOpen 2:dcaee06f6ccb 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MikamiUitOpen 2:dcaee06f6ccb 321
MikamiUitOpen 2:dcaee06f6ccb 322
MikamiUitOpen 2:dcaee06f6ccb 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 2:dcaee06f6ccb 324 /* GNU gcc specific functions */
MikamiUitOpen 2:dcaee06f6ccb 325
MikamiUitOpen 2:dcaee06f6ccb 326 /** \brief Enable IRQ Interrupts
MikamiUitOpen 2:dcaee06f6ccb 327
MikamiUitOpen 2:dcaee06f6ccb 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 329 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 330 */
MikamiUitOpen 2:dcaee06f6ccb 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
MikamiUitOpen 2:dcaee06f6ccb 332 {
MikamiUitOpen 2:dcaee06f6ccb 333 __ASM volatile ("cpsie i" : : : "memory");
MikamiUitOpen 2:dcaee06f6ccb 334 }
MikamiUitOpen 2:dcaee06f6ccb 335
MikamiUitOpen 2:dcaee06f6ccb 336
MikamiUitOpen 2:dcaee06f6ccb 337 /** \brief Disable IRQ Interrupts
MikamiUitOpen 2:dcaee06f6ccb 338
MikamiUitOpen 2:dcaee06f6ccb 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 340 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 341 */
MikamiUitOpen 2:dcaee06f6ccb 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
MikamiUitOpen 2:dcaee06f6ccb 343 {
MikamiUitOpen 2:dcaee06f6ccb 344 __ASM volatile ("cpsid i" : : : "memory");
MikamiUitOpen 2:dcaee06f6ccb 345 }
MikamiUitOpen 2:dcaee06f6ccb 346
MikamiUitOpen 2:dcaee06f6ccb 347
MikamiUitOpen 2:dcaee06f6ccb 348 /** \brief Get Control Register
MikamiUitOpen 2:dcaee06f6ccb 349
MikamiUitOpen 2:dcaee06f6ccb 350 This function returns the content of the Control Register.
MikamiUitOpen 2:dcaee06f6ccb 351
MikamiUitOpen 2:dcaee06f6ccb 352 \return Control Register value
MikamiUitOpen 2:dcaee06f6ccb 353 */
MikamiUitOpen 2:dcaee06f6ccb 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
MikamiUitOpen 2:dcaee06f6ccb 355 {
MikamiUitOpen 2:dcaee06f6ccb 356 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 357
MikamiUitOpen 2:dcaee06f6ccb 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 359 return(result);
MikamiUitOpen 2:dcaee06f6ccb 360 }
MikamiUitOpen 2:dcaee06f6ccb 361
MikamiUitOpen 2:dcaee06f6ccb 362
MikamiUitOpen 2:dcaee06f6ccb 363 /** \brief Set Control Register
MikamiUitOpen 2:dcaee06f6ccb 364
MikamiUitOpen 2:dcaee06f6ccb 365 This function writes the given value to the Control Register.
MikamiUitOpen 2:dcaee06f6ccb 366
MikamiUitOpen 2:dcaee06f6ccb 367 \param [in] control Control Register value to set
MikamiUitOpen 2:dcaee06f6ccb 368 */
MikamiUitOpen 2:dcaee06f6ccb 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
MikamiUitOpen 2:dcaee06f6ccb 370 {
MikamiUitOpen 2:dcaee06f6ccb 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
MikamiUitOpen 2:dcaee06f6ccb 372 }
MikamiUitOpen 2:dcaee06f6ccb 373
MikamiUitOpen 2:dcaee06f6ccb 374
MikamiUitOpen 2:dcaee06f6ccb 375 /** \brief Get IPSR Register
MikamiUitOpen 2:dcaee06f6ccb 376
MikamiUitOpen 2:dcaee06f6ccb 377 This function returns the content of the IPSR Register.
MikamiUitOpen 2:dcaee06f6ccb 378
MikamiUitOpen 2:dcaee06f6ccb 379 \return IPSR Register value
MikamiUitOpen 2:dcaee06f6ccb 380 */
MikamiUitOpen 2:dcaee06f6ccb 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
MikamiUitOpen 2:dcaee06f6ccb 382 {
MikamiUitOpen 2:dcaee06f6ccb 383 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 384
MikamiUitOpen 2:dcaee06f6ccb 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 386 return(result);
MikamiUitOpen 2:dcaee06f6ccb 387 }
MikamiUitOpen 2:dcaee06f6ccb 388
MikamiUitOpen 2:dcaee06f6ccb 389
MikamiUitOpen 2:dcaee06f6ccb 390 /** \brief Get APSR Register
MikamiUitOpen 2:dcaee06f6ccb 391
MikamiUitOpen 2:dcaee06f6ccb 392 This function returns the content of the APSR Register.
MikamiUitOpen 2:dcaee06f6ccb 393
MikamiUitOpen 2:dcaee06f6ccb 394 \return APSR Register value
MikamiUitOpen 2:dcaee06f6ccb 395 */
MikamiUitOpen 2:dcaee06f6ccb 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 2:dcaee06f6ccb 397 {
MikamiUitOpen 2:dcaee06f6ccb 398 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 399
MikamiUitOpen 2:dcaee06f6ccb 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 401 return(result);
MikamiUitOpen 2:dcaee06f6ccb 402 }
MikamiUitOpen 2:dcaee06f6ccb 403
MikamiUitOpen 2:dcaee06f6ccb 404
MikamiUitOpen 2:dcaee06f6ccb 405 /** \brief Get xPSR Register
MikamiUitOpen 2:dcaee06f6ccb 406
MikamiUitOpen 2:dcaee06f6ccb 407 This function returns the content of the xPSR Register.
MikamiUitOpen 2:dcaee06f6ccb 408
MikamiUitOpen 2:dcaee06f6ccb 409 \return xPSR Register value
MikamiUitOpen 2:dcaee06f6ccb 410 */
MikamiUitOpen 2:dcaee06f6ccb 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
MikamiUitOpen 2:dcaee06f6ccb 412 {
MikamiUitOpen 2:dcaee06f6ccb 413 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 414
MikamiUitOpen 2:dcaee06f6ccb 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 416 return(result);
MikamiUitOpen 2:dcaee06f6ccb 417 }
MikamiUitOpen 2:dcaee06f6ccb 418
MikamiUitOpen 2:dcaee06f6ccb 419
MikamiUitOpen 2:dcaee06f6ccb 420 /** \brief Get Process Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 421
MikamiUitOpen 2:dcaee06f6ccb 422 This function returns the current value of the Process Stack Pointer (PSP).
MikamiUitOpen 2:dcaee06f6ccb 423
MikamiUitOpen 2:dcaee06f6ccb 424 \return PSP Register value
MikamiUitOpen 2:dcaee06f6ccb 425 */
MikamiUitOpen 2:dcaee06f6ccb 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
MikamiUitOpen 2:dcaee06f6ccb 427 {
MikamiUitOpen 2:dcaee06f6ccb 428 register uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 429
MikamiUitOpen 2:dcaee06f6ccb 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 431 return(result);
MikamiUitOpen 2:dcaee06f6ccb 432 }
MikamiUitOpen 2:dcaee06f6ccb 433
MikamiUitOpen 2:dcaee06f6ccb 434
MikamiUitOpen 2:dcaee06f6ccb 435 /** \brief Set Process Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 436
MikamiUitOpen 2:dcaee06f6ccb 437 This function assigns the given value to the Process Stack Pointer (PSP).
MikamiUitOpen 2:dcaee06f6ccb 438
MikamiUitOpen 2:dcaee06f6ccb 439 \param [in] topOfProcStack Process Stack Pointer value to set
MikamiUitOpen 2:dcaee06f6ccb 440 */
MikamiUitOpen 2:dcaee06f6ccb 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 2:dcaee06f6ccb 442 {
MikamiUitOpen 2:dcaee06f6ccb 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
MikamiUitOpen 2:dcaee06f6ccb 444 }
MikamiUitOpen 2:dcaee06f6ccb 445
MikamiUitOpen 2:dcaee06f6ccb 446
MikamiUitOpen 2:dcaee06f6ccb 447 /** \brief Get Main Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 448
MikamiUitOpen 2:dcaee06f6ccb 449 This function returns the current value of the Main Stack Pointer (MSP).
MikamiUitOpen 2:dcaee06f6ccb 450
MikamiUitOpen 2:dcaee06f6ccb 451 \return MSP Register value
MikamiUitOpen 2:dcaee06f6ccb 452 */
MikamiUitOpen 2:dcaee06f6ccb 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
MikamiUitOpen 2:dcaee06f6ccb 454 {
MikamiUitOpen 2:dcaee06f6ccb 455 register uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 456
MikamiUitOpen 2:dcaee06f6ccb 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 458 return(result);
MikamiUitOpen 2:dcaee06f6ccb 459 }
MikamiUitOpen 2:dcaee06f6ccb 460
MikamiUitOpen 2:dcaee06f6ccb 461
MikamiUitOpen 2:dcaee06f6ccb 462 /** \brief Set Main Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 463
MikamiUitOpen 2:dcaee06f6ccb 464 This function assigns the given value to the Main Stack Pointer (MSP).
MikamiUitOpen 2:dcaee06f6ccb 465
MikamiUitOpen 2:dcaee06f6ccb 466 \param [in] topOfMainStack Main Stack Pointer value to set
MikamiUitOpen 2:dcaee06f6ccb 467 */
MikamiUitOpen 2:dcaee06f6ccb 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MikamiUitOpen 2:dcaee06f6ccb 469 {
MikamiUitOpen 2:dcaee06f6ccb 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
MikamiUitOpen 2:dcaee06f6ccb 471 }
MikamiUitOpen 2:dcaee06f6ccb 472
MikamiUitOpen 2:dcaee06f6ccb 473
MikamiUitOpen 2:dcaee06f6ccb 474 /** \brief Get Priority Mask
MikamiUitOpen 2:dcaee06f6ccb 475
MikamiUitOpen 2:dcaee06f6ccb 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
MikamiUitOpen 2:dcaee06f6ccb 477
MikamiUitOpen 2:dcaee06f6ccb 478 \return Priority Mask value
MikamiUitOpen 2:dcaee06f6ccb 479 */
MikamiUitOpen 2:dcaee06f6ccb 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
MikamiUitOpen 2:dcaee06f6ccb 481 {
MikamiUitOpen 2:dcaee06f6ccb 482 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 483
MikamiUitOpen 2:dcaee06f6ccb 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 485 return(result);
MikamiUitOpen 2:dcaee06f6ccb 486 }
MikamiUitOpen 2:dcaee06f6ccb 487
MikamiUitOpen 2:dcaee06f6ccb 488
MikamiUitOpen 2:dcaee06f6ccb 489 /** \brief Set Priority Mask
MikamiUitOpen 2:dcaee06f6ccb 490
MikamiUitOpen 2:dcaee06f6ccb 491 This function assigns the given value to the Priority Mask Register.
MikamiUitOpen 2:dcaee06f6ccb 492
MikamiUitOpen 2:dcaee06f6ccb 493 \param [in] priMask Priority Mask
MikamiUitOpen 2:dcaee06f6ccb 494 */
MikamiUitOpen 2:dcaee06f6ccb 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MikamiUitOpen 2:dcaee06f6ccb 496 {
MikamiUitOpen 2:dcaee06f6ccb 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
MikamiUitOpen 2:dcaee06f6ccb 498 }
MikamiUitOpen 2:dcaee06f6ccb 499
MikamiUitOpen 2:dcaee06f6ccb 500
MikamiUitOpen 2:dcaee06f6ccb 501 #if (__CORTEX_M >= 0x03)
MikamiUitOpen 2:dcaee06f6ccb 502
MikamiUitOpen 2:dcaee06f6ccb 503 /** \brief Enable FIQ
MikamiUitOpen 2:dcaee06f6ccb 504
MikamiUitOpen 2:dcaee06f6ccb 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 506 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 507 */
MikamiUitOpen 2:dcaee06f6ccb 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
MikamiUitOpen 2:dcaee06f6ccb 509 {
MikamiUitOpen 2:dcaee06f6ccb 510 __ASM volatile ("cpsie f" : : : "memory");
MikamiUitOpen 2:dcaee06f6ccb 511 }
MikamiUitOpen 2:dcaee06f6ccb 512
MikamiUitOpen 2:dcaee06f6ccb 513
MikamiUitOpen 2:dcaee06f6ccb 514 /** \brief Disable FIQ
MikamiUitOpen 2:dcaee06f6ccb 515
MikamiUitOpen 2:dcaee06f6ccb 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 517 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 518 */
MikamiUitOpen 2:dcaee06f6ccb 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
MikamiUitOpen 2:dcaee06f6ccb 520 {
MikamiUitOpen 2:dcaee06f6ccb 521 __ASM volatile ("cpsid f" : : : "memory");
MikamiUitOpen 2:dcaee06f6ccb 522 }
MikamiUitOpen 2:dcaee06f6ccb 523
MikamiUitOpen 2:dcaee06f6ccb 524
MikamiUitOpen 2:dcaee06f6ccb 525 /** \brief Get Base Priority
MikamiUitOpen 2:dcaee06f6ccb 526
MikamiUitOpen 2:dcaee06f6ccb 527 This function returns the current value of the Base Priority register.
MikamiUitOpen 2:dcaee06f6ccb 528
MikamiUitOpen 2:dcaee06f6ccb 529 \return Base Priority register value
MikamiUitOpen 2:dcaee06f6ccb 530 */
MikamiUitOpen 2:dcaee06f6ccb 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
MikamiUitOpen 2:dcaee06f6ccb 532 {
MikamiUitOpen 2:dcaee06f6ccb 533 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 534
MikamiUitOpen 2:dcaee06f6ccb 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 536 return(result);
MikamiUitOpen 2:dcaee06f6ccb 537 }
MikamiUitOpen 2:dcaee06f6ccb 538
MikamiUitOpen 2:dcaee06f6ccb 539
MikamiUitOpen 2:dcaee06f6ccb 540 /** \brief Set Base Priority
MikamiUitOpen 2:dcaee06f6ccb 541
MikamiUitOpen 2:dcaee06f6ccb 542 This function assigns the given value to the Base Priority register.
MikamiUitOpen 2:dcaee06f6ccb 543
MikamiUitOpen 2:dcaee06f6ccb 544 \param [in] basePri Base Priority value to set
MikamiUitOpen 2:dcaee06f6ccb 545 */
MikamiUitOpen 2:dcaee06f6ccb 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
MikamiUitOpen 2:dcaee06f6ccb 547 {
MikamiUitOpen 2:dcaee06f6ccb 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
MikamiUitOpen 2:dcaee06f6ccb 549 }
MikamiUitOpen 2:dcaee06f6ccb 550
MikamiUitOpen 2:dcaee06f6ccb 551
MikamiUitOpen 2:dcaee06f6ccb 552 /** \brief Set Base Priority with condition
MikamiUitOpen 2:dcaee06f6ccb 553
MikamiUitOpen 2:dcaee06f6ccb 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MikamiUitOpen 2:dcaee06f6ccb 555 or the new value increases the BASEPRI priority level.
MikamiUitOpen 2:dcaee06f6ccb 556
MikamiUitOpen 2:dcaee06f6ccb 557 \param [in] basePri Base Priority value to set
MikamiUitOpen 2:dcaee06f6ccb 558 */
MikamiUitOpen 2:dcaee06f6ccb 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
MikamiUitOpen 2:dcaee06f6ccb 560 {
MikamiUitOpen 2:dcaee06f6ccb 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
MikamiUitOpen 2:dcaee06f6ccb 562 }
MikamiUitOpen 2:dcaee06f6ccb 563
MikamiUitOpen 2:dcaee06f6ccb 564
MikamiUitOpen 2:dcaee06f6ccb 565 /** \brief Get Fault Mask
MikamiUitOpen 2:dcaee06f6ccb 566
MikamiUitOpen 2:dcaee06f6ccb 567 This function returns the current value of the Fault Mask register.
MikamiUitOpen 2:dcaee06f6ccb 568
MikamiUitOpen 2:dcaee06f6ccb 569 \return Fault Mask register value
MikamiUitOpen 2:dcaee06f6ccb 570 */
MikamiUitOpen 2:dcaee06f6ccb 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MikamiUitOpen 2:dcaee06f6ccb 572 {
MikamiUitOpen 2:dcaee06f6ccb 573 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 574
MikamiUitOpen 2:dcaee06f6ccb 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 576 return(result);
MikamiUitOpen 2:dcaee06f6ccb 577 }
MikamiUitOpen 2:dcaee06f6ccb 578
MikamiUitOpen 2:dcaee06f6ccb 579
MikamiUitOpen 2:dcaee06f6ccb 580 /** \brief Set Fault Mask
MikamiUitOpen 2:dcaee06f6ccb 581
MikamiUitOpen 2:dcaee06f6ccb 582 This function assigns the given value to the Fault Mask register.
MikamiUitOpen 2:dcaee06f6ccb 583
MikamiUitOpen 2:dcaee06f6ccb 584 \param [in] faultMask Fault Mask value to set
MikamiUitOpen 2:dcaee06f6ccb 585 */
MikamiUitOpen 2:dcaee06f6ccb 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MikamiUitOpen 2:dcaee06f6ccb 587 {
MikamiUitOpen 2:dcaee06f6ccb 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
MikamiUitOpen 2:dcaee06f6ccb 589 }
MikamiUitOpen 2:dcaee06f6ccb 590
MikamiUitOpen 2:dcaee06f6ccb 591 #endif /* (__CORTEX_M >= 0x03) */
MikamiUitOpen 2:dcaee06f6ccb 592
MikamiUitOpen 2:dcaee06f6ccb 593
MikamiUitOpen 2:dcaee06f6ccb 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MikamiUitOpen 2:dcaee06f6ccb 595
MikamiUitOpen 2:dcaee06f6ccb 596 /** \brief Get FPSCR
MikamiUitOpen 2:dcaee06f6ccb 597
MikamiUitOpen 2:dcaee06f6ccb 598 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 2:dcaee06f6ccb 599
MikamiUitOpen 2:dcaee06f6ccb 600 \return Floating Point Status/Control register value
MikamiUitOpen 2:dcaee06f6ccb 601 */
MikamiUitOpen 2:dcaee06f6ccb 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 2:dcaee06f6ccb 603 {
MikamiUitOpen 2:dcaee06f6ccb 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 2:dcaee06f6ccb 605 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 606
MikamiUitOpen 2:dcaee06f6ccb 607 /* Empty asm statement works as a scheduling barrier */
MikamiUitOpen 2:dcaee06f6ccb 608 __ASM volatile ("");
MikamiUitOpen 2:dcaee06f6ccb 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 610 __ASM volatile ("");
MikamiUitOpen 2:dcaee06f6ccb 611 return(result);
MikamiUitOpen 2:dcaee06f6ccb 612 #else
MikamiUitOpen 2:dcaee06f6ccb 613 return(0);
MikamiUitOpen 2:dcaee06f6ccb 614 #endif
MikamiUitOpen 2:dcaee06f6ccb 615 }
MikamiUitOpen 2:dcaee06f6ccb 616
MikamiUitOpen 2:dcaee06f6ccb 617
MikamiUitOpen 2:dcaee06f6ccb 618 /** \brief Set FPSCR
MikamiUitOpen 2:dcaee06f6ccb 619
MikamiUitOpen 2:dcaee06f6ccb 620 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 2:dcaee06f6ccb 621
MikamiUitOpen 2:dcaee06f6ccb 622 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 2:dcaee06f6ccb 623 */
MikamiUitOpen 2:dcaee06f6ccb 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 2:dcaee06f6ccb 625 {
MikamiUitOpen 2:dcaee06f6ccb 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 2:dcaee06f6ccb 627 /* Empty asm statement works as a scheduling barrier */
MikamiUitOpen 2:dcaee06f6ccb 628 __ASM volatile ("");
MikamiUitOpen 2:dcaee06f6ccb 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
MikamiUitOpen 2:dcaee06f6ccb 630 __ASM volatile ("");
MikamiUitOpen 2:dcaee06f6ccb 631 #endif
MikamiUitOpen 2:dcaee06f6ccb 632 }
MikamiUitOpen 2:dcaee06f6ccb 633
MikamiUitOpen 2:dcaee06f6ccb 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MikamiUitOpen 2:dcaee06f6ccb 635
MikamiUitOpen 2:dcaee06f6ccb 636
MikamiUitOpen 2:dcaee06f6ccb 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 2:dcaee06f6ccb 638 /* IAR iccarm specific functions */
MikamiUitOpen 2:dcaee06f6ccb 639 #include <cmsis_iar.h>
MikamiUitOpen 2:dcaee06f6ccb 640
MikamiUitOpen 2:dcaee06f6ccb 641
MikamiUitOpen 2:dcaee06f6ccb 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 2:dcaee06f6ccb 643 /* TI CCS specific functions */
MikamiUitOpen 2:dcaee06f6ccb 644 #include <cmsis_ccs.h>
MikamiUitOpen 2:dcaee06f6ccb 645
MikamiUitOpen 2:dcaee06f6ccb 646
MikamiUitOpen 2:dcaee06f6ccb 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 2:dcaee06f6ccb 648 /* TASKING carm specific functions */
MikamiUitOpen 2:dcaee06f6ccb 649 /*
MikamiUitOpen 2:dcaee06f6ccb 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
MikamiUitOpen 2:dcaee06f6ccb 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
MikamiUitOpen 2:dcaee06f6ccb 652 * Including the CMSIS ones.
MikamiUitOpen 2:dcaee06f6ccb 653 */
MikamiUitOpen 2:dcaee06f6ccb 654
MikamiUitOpen 2:dcaee06f6ccb 655
MikamiUitOpen 2:dcaee06f6ccb 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MikamiUitOpen 2:dcaee06f6ccb 657 /* Cosmic specific functions */
MikamiUitOpen 2:dcaee06f6ccb 658 #include <cmsis_csm.h>
MikamiUitOpen 2:dcaee06f6ccb 659
MikamiUitOpen 2:dcaee06f6ccb 660 #endif
MikamiUitOpen 2:dcaee06f6ccb 661
MikamiUitOpen 2:dcaee06f6ccb 662 /*@} end of CMSIS_Core_RegAccFunctions */
MikamiUitOpen 2:dcaee06f6ccb 663
MikamiUitOpen 2:dcaee06f6ccb 664 #endif /* __CORE_CMFUNC_H */