不韋 呂 / F746_SD_VarableFilter

SD card player with variable cotoff frequency lowpass and highpass IIR filter. SD カードの *.wav ファイルのオーディオ信号を，遮断周波数可変 IIR 低域通過および高域通過フィルタを通して，ボードに搭載されているCODEC で出力する．このプログラムについては，CQ出版社インターフェース誌 2018年8月号で解説している．

Dependencies:   F746_GUI F746_SAI_IO FrequencyResponseDrawer SD_PlayerSkeleton

mbed_src_STM32F7/targets/cmsis/core_cm3.h@11:399670d24ed9, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 01:44:22 2017 +0000
Revision:
11:399670d24ed9
Parent:
2:dcaee06f6ccb 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 2:dcaee06f6ccb 1 /**************************************************************************//**
MikamiUitOpen 2:dcaee06f6ccb 2 * @file core_cm3.h
MikamiUitOpen 2:dcaee06f6ccb 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
MikamiUitOpen 2:dcaee06f6ccb 4 * @version V4.10
MikamiUitOpen 2:dcaee06f6ccb 5 * @date 18. March 2015
MikamiUitOpen 2:dcaee06f6ccb 6 *
MikamiUitOpen 2:dcaee06f6ccb 7 * @note
MikamiUitOpen 2:dcaee06f6ccb 8 *
MikamiUitOpen 2:dcaee06f6ccb 9 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 2:dcaee06f6ccb 11
MikamiUitOpen 2:dcaee06f6ccb 12 All rights reserved.
MikamiUitOpen 2:dcaee06f6ccb 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 2:dcaee06f6ccb 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 2:dcaee06f6ccb 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 2:dcaee06f6ccb 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 2:dcaee06f6ccb 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 2:dcaee06f6ccb 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 2:dcaee06f6ccb 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 2:dcaee06f6ccb 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 2:dcaee06f6ccb 21 to endorse or promote products derived from this software without
MikamiUitOpen 2:dcaee06f6ccb 22 specific prior written permission.
MikamiUitOpen 2:dcaee06f6ccb 23 *
MikamiUitOpen 2:dcaee06f6ccb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 2:dcaee06f6ccb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 2:dcaee06f6ccb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 2:dcaee06f6ccb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 2:dcaee06f6ccb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 2:dcaee06f6ccb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 2:dcaee06f6ccb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 2:dcaee06f6ccb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 2:dcaee06f6ccb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 2:dcaee06f6ccb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 2:dcaee06f6ccb 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 2:dcaee06f6ccb 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 2:dcaee06f6ccb 36
MikamiUitOpen 2:dcaee06f6ccb 37
MikamiUitOpen 2:dcaee06f6ccb 38 #if defined ( __ICCARM__ )
MikamiUitOpen 2:dcaee06f6ccb 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 2:dcaee06f6ccb 40 #endif
MikamiUitOpen 2:dcaee06f6ccb 41
MikamiUitOpen 2:dcaee06f6ccb 42 #ifndef __CORE_CM3_H_GENERIC
MikamiUitOpen 2:dcaee06f6ccb 43 #define __CORE_CM3_H_GENERIC
MikamiUitOpen 2:dcaee06f6ccb 44
MikamiUitOpen 2:dcaee06f6ccb 45 #ifdef __cplusplus
MikamiUitOpen 2:dcaee06f6ccb 46 extern "C" {
MikamiUitOpen 2:dcaee06f6ccb 47 #endif
MikamiUitOpen 2:dcaee06f6ccb 48
MikamiUitOpen 2:dcaee06f6ccb 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen 2:dcaee06f6ccb 50 CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen 2:dcaee06f6ccb 51
MikamiUitOpen 2:dcaee06f6ccb 52 \li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen 2:dcaee06f6ccb 53 Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen 2:dcaee06f6ccb 54
MikamiUitOpen 2:dcaee06f6ccb 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen 2:dcaee06f6ccb 56 Unions are used for effective representation of core registers.
MikamiUitOpen 2:dcaee06f6ccb 57
MikamiUitOpen 2:dcaee06f6ccb 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen 2:dcaee06f6ccb 59 Function-like macros are used to allow more efficient code.
MikamiUitOpen 2:dcaee06f6ccb 60 */
MikamiUitOpen 2:dcaee06f6ccb 61
MikamiUitOpen 2:dcaee06f6ccb 62
MikamiUitOpen 2:dcaee06f6ccb 63 /*******************************************************************************
MikamiUitOpen 2:dcaee06f6ccb 64 * CMSIS definitions
MikamiUitOpen 2:dcaee06f6ccb 65 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 66 /** \ingroup Cortex_M3
MikamiUitOpen 2:dcaee06f6ccb 67 @{
MikamiUitOpen 2:dcaee06f6ccb 68 */
MikamiUitOpen 2:dcaee06f6ccb 69
MikamiUitOpen 2:dcaee06f6ccb 70 /* CMSIS CM3 definitions */
MikamiUitOpen 2:dcaee06f6ccb 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
MikamiUitOpen 2:dcaee06f6ccb 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
MikamiUitOpen 2:dcaee06f6ccb 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
MikamiUitOpen 2:dcaee06f6ccb 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
MikamiUitOpen 2:dcaee06f6ccb 75
MikamiUitOpen 2:dcaee06f6ccb 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
MikamiUitOpen 2:dcaee06f6ccb 77
MikamiUitOpen 2:dcaee06f6ccb 78
MikamiUitOpen 2:dcaee06f6ccb 79 #if defined ( __CC_ARM )
MikamiUitOpen 2:dcaee06f6ccb 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
MikamiUitOpen 2:dcaee06f6ccb 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
MikamiUitOpen 2:dcaee06f6ccb 82 #define __STATIC_INLINE static __inline
MikamiUitOpen 2:dcaee06f6ccb 83
MikamiUitOpen 2:dcaee06f6ccb 84 #elif defined ( __GNUC__ )
MikamiUitOpen 2:dcaee06f6ccb 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
MikamiUitOpen 2:dcaee06f6ccb 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
MikamiUitOpen 2:dcaee06f6ccb 87 #define __STATIC_INLINE static inline
MikamiUitOpen 2:dcaee06f6ccb 88
MikamiUitOpen 2:dcaee06f6ccb 89 #elif defined ( __ICCARM__ )
MikamiUitOpen 2:dcaee06f6ccb 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
MikamiUitOpen 2:dcaee06f6ccb 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
MikamiUitOpen 2:dcaee06f6ccb 92 #define __STATIC_INLINE static inline
MikamiUitOpen 2:dcaee06f6ccb 93
MikamiUitOpen 2:dcaee06f6ccb 94 #elif defined ( __TMS470__ )
MikamiUitOpen 2:dcaee06f6ccb 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
MikamiUitOpen 2:dcaee06f6ccb 96 #define __STATIC_INLINE static inline
MikamiUitOpen 2:dcaee06f6ccb 97
MikamiUitOpen 2:dcaee06f6ccb 98 #elif defined ( __TASKING__ )
MikamiUitOpen 2:dcaee06f6ccb 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
MikamiUitOpen 2:dcaee06f6ccb 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
MikamiUitOpen 2:dcaee06f6ccb 101 #define __STATIC_INLINE static inline
MikamiUitOpen 2:dcaee06f6ccb 102
MikamiUitOpen 2:dcaee06f6ccb 103 #elif defined ( __CSMC__ )
MikamiUitOpen 2:dcaee06f6ccb 104 #define __packed
MikamiUitOpen 2:dcaee06f6ccb 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
MikamiUitOpen 2:dcaee06f6ccb 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
MikamiUitOpen 2:dcaee06f6ccb 107 #define __STATIC_INLINE static inline
MikamiUitOpen 2:dcaee06f6ccb 108
MikamiUitOpen 2:dcaee06f6ccb 109 #endif
MikamiUitOpen 2:dcaee06f6ccb 110
MikamiUitOpen 2:dcaee06f6ccb 111 /** __FPU_USED indicates whether an FPU is used or not.
MikamiUitOpen 2:dcaee06f6ccb 112 This core does not support an FPU at all
MikamiUitOpen 2:dcaee06f6ccb 113 */
MikamiUitOpen 2:dcaee06f6ccb 114 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 115
MikamiUitOpen 2:dcaee06f6ccb 116 #if defined ( __CC_ARM )
MikamiUitOpen 2:dcaee06f6ccb 117 #if defined __TARGET_FPU_VFP
MikamiUitOpen 2:dcaee06f6ccb 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 119 #endif
MikamiUitOpen 2:dcaee06f6ccb 120
MikamiUitOpen 2:dcaee06f6ccb 121 #elif defined ( __GNUC__ )
MikamiUitOpen 2:dcaee06f6ccb 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen 2:dcaee06f6ccb 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 124 #endif
MikamiUitOpen 2:dcaee06f6ccb 125
MikamiUitOpen 2:dcaee06f6ccb 126 #elif defined ( __ICCARM__ )
MikamiUitOpen 2:dcaee06f6ccb 127 #if defined __ARMVFP__
MikamiUitOpen 2:dcaee06f6ccb 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 129 #endif
MikamiUitOpen 2:dcaee06f6ccb 130
MikamiUitOpen 2:dcaee06f6ccb 131 #elif defined ( __TMS470__ )
MikamiUitOpen 2:dcaee06f6ccb 132 #if defined __TI__VFP_SUPPORT____
MikamiUitOpen 2:dcaee06f6ccb 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 134 #endif
MikamiUitOpen 2:dcaee06f6ccb 135
MikamiUitOpen 2:dcaee06f6ccb 136 #elif defined ( __TASKING__ )
MikamiUitOpen 2:dcaee06f6ccb 137 #if defined __FPU_VFP__
MikamiUitOpen 2:dcaee06f6ccb 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 139 #endif
MikamiUitOpen 2:dcaee06f6ccb 140
MikamiUitOpen 2:dcaee06f6ccb 141 #elif defined ( __CSMC__ ) /* Cosmic */
MikamiUitOpen 2:dcaee06f6ccb 142 #if ( __CSMC__ & 0x400) // FPU present for parser
MikamiUitOpen 2:dcaee06f6ccb 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 144 #endif
MikamiUitOpen 2:dcaee06f6ccb 145 #endif
MikamiUitOpen 2:dcaee06f6ccb 146
MikamiUitOpen 2:dcaee06f6ccb 147 #include <stdint.h> /* standard types definitions */
MikamiUitOpen 2:dcaee06f6ccb 148 #include <core_cmInstr.h> /* Core Instruction Access */
MikamiUitOpen 2:dcaee06f6ccb 149 #include <core_cmFunc.h> /* Core Function Access */
MikamiUitOpen 2:dcaee06f6ccb 150
MikamiUitOpen 2:dcaee06f6ccb 151 #ifdef __cplusplus
MikamiUitOpen 2:dcaee06f6ccb 152 }
MikamiUitOpen 2:dcaee06f6ccb 153 #endif
MikamiUitOpen 2:dcaee06f6ccb 154
MikamiUitOpen 2:dcaee06f6ccb 155 #endif /* __CORE_CM3_H_GENERIC */
MikamiUitOpen 2:dcaee06f6ccb 156
MikamiUitOpen 2:dcaee06f6ccb 157 #ifndef __CMSIS_GENERIC
MikamiUitOpen 2:dcaee06f6ccb 158
MikamiUitOpen 2:dcaee06f6ccb 159 #ifndef __CORE_CM3_H_DEPENDANT
MikamiUitOpen 2:dcaee06f6ccb 160 #define __CORE_CM3_H_DEPENDANT
MikamiUitOpen 2:dcaee06f6ccb 161
MikamiUitOpen 2:dcaee06f6ccb 162 #ifdef __cplusplus
MikamiUitOpen 2:dcaee06f6ccb 163 extern "C" {
MikamiUitOpen 2:dcaee06f6ccb 164 #endif
MikamiUitOpen 2:dcaee06f6ccb 165
MikamiUitOpen 2:dcaee06f6ccb 166 /* check device defines and use defaults */
MikamiUitOpen 2:dcaee06f6ccb 167 #if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen 2:dcaee06f6ccb 168 #ifndef __CM3_REV
MikamiUitOpen 2:dcaee06f6ccb 169 #define __CM3_REV 0x0200
MikamiUitOpen 2:dcaee06f6ccb 170 #warning "__CM3_REV not defined in device header file; using default!"
MikamiUitOpen 2:dcaee06f6ccb 171 #endif
MikamiUitOpen 2:dcaee06f6ccb 172
MikamiUitOpen 2:dcaee06f6ccb 173 #ifndef __MPU_PRESENT
MikamiUitOpen 2:dcaee06f6ccb 174 #define __MPU_PRESENT 0
MikamiUitOpen 2:dcaee06f6ccb 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen 2:dcaee06f6ccb 176 #endif
MikamiUitOpen 2:dcaee06f6ccb 177
MikamiUitOpen 2:dcaee06f6ccb 178 #ifndef __NVIC_PRIO_BITS
MikamiUitOpen 2:dcaee06f6ccb 179 #define __NVIC_PRIO_BITS 4
MikamiUitOpen 2:dcaee06f6ccb 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
MikamiUitOpen 2:dcaee06f6ccb 181 #endif
MikamiUitOpen 2:dcaee06f6ccb 182
MikamiUitOpen 2:dcaee06f6ccb 183 #ifndef __Vendor_SysTickConfig
MikamiUitOpen 2:dcaee06f6ccb 184 #define __Vendor_SysTickConfig 0
MikamiUitOpen 2:dcaee06f6ccb 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
MikamiUitOpen 2:dcaee06f6ccb 186 #endif
MikamiUitOpen 2:dcaee06f6ccb 187 #endif
MikamiUitOpen 2:dcaee06f6ccb 188
MikamiUitOpen 2:dcaee06f6ccb 189 /* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen 2:dcaee06f6ccb 190 /**
MikamiUitOpen 2:dcaee06f6ccb 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen 2:dcaee06f6ccb 192
MikamiUitOpen 2:dcaee06f6ccb 193 <strong>IO Type Qualifiers</strong> are used
MikamiUitOpen 2:dcaee06f6ccb 194 \li to specify the access to peripheral variables.
MikamiUitOpen 2:dcaee06f6ccb 195 \li for automatic generation of peripheral register debug information.
MikamiUitOpen 2:dcaee06f6ccb 196 */
MikamiUitOpen 2:dcaee06f6ccb 197 #ifdef __cplusplus
MikamiUitOpen 2:dcaee06f6ccb 198 #define __I volatile /*!< Defines 'read only' permissions */
MikamiUitOpen 2:dcaee06f6ccb 199 #else
MikamiUitOpen 2:dcaee06f6ccb 200 #define __I volatile const /*!< Defines 'read only' permissions */
MikamiUitOpen 2:dcaee06f6ccb 201 #endif
MikamiUitOpen 2:dcaee06f6ccb 202 #define __O volatile /*!< Defines 'write only' permissions */
MikamiUitOpen 2:dcaee06f6ccb 203 #define __IO volatile /*!< Defines 'read / write' permissions */
MikamiUitOpen 2:dcaee06f6ccb 204
MikamiUitOpen 2:dcaee06f6ccb 205 /*@} end of group Cortex_M3 */
MikamiUitOpen 2:dcaee06f6ccb 206
MikamiUitOpen 2:dcaee06f6ccb 207
MikamiUitOpen 2:dcaee06f6ccb 208
MikamiUitOpen 2:dcaee06f6ccb 209 /*******************************************************************************
MikamiUitOpen 2:dcaee06f6ccb 210 * Register Abstraction
MikamiUitOpen 2:dcaee06f6ccb 211 Core Register contain:
MikamiUitOpen 2:dcaee06f6ccb 212 - Core Register
MikamiUitOpen 2:dcaee06f6ccb 213 - Core NVIC Register
MikamiUitOpen 2:dcaee06f6ccb 214 - Core SCB Register
MikamiUitOpen 2:dcaee06f6ccb 215 - Core SysTick Register
MikamiUitOpen 2:dcaee06f6ccb 216 - Core Debug Register
MikamiUitOpen 2:dcaee06f6ccb 217 - Core MPU Register
MikamiUitOpen 2:dcaee06f6ccb 218 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen 2:dcaee06f6ccb 220 \brief Type definitions and defines for Cortex-M processor based devices.
MikamiUitOpen 2:dcaee06f6ccb 221 */
MikamiUitOpen 2:dcaee06f6ccb 222
MikamiUitOpen 2:dcaee06f6ccb 223 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 224 \defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen 2:dcaee06f6ccb 225 \brief Core Register type definitions.
MikamiUitOpen 2:dcaee06f6ccb 226 @{
MikamiUitOpen 2:dcaee06f6ccb 227 */
MikamiUitOpen 2:dcaee06f6ccb 228
MikamiUitOpen 2:dcaee06f6ccb 229 /** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen 2:dcaee06f6ccb 230 */
MikamiUitOpen 2:dcaee06f6ccb 231 typedef union
MikamiUitOpen 2:dcaee06f6ccb 232 {
MikamiUitOpen 2:dcaee06f6ccb 233 struct
MikamiUitOpen 2:dcaee06f6ccb 234 {
MikamiUitOpen 2:dcaee06f6ccb 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
MikamiUitOpen 2:dcaee06f6ccb 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
MikamiUitOpen 2:dcaee06f6ccb 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 241 } b; /*!< Structure used for bit access */
MikamiUitOpen 2:dcaee06f6ccb 242 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 2:dcaee06f6ccb 243 } APSR_Type;
MikamiUitOpen 2:dcaee06f6ccb 244
MikamiUitOpen 2:dcaee06f6ccb 245 /* APSR Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
MikamiUitOpen 2:dcaee06f6ccb 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
MikamiUitOpen 2:dcaee06f6ccb 248
MikamiUitOpen 2:dcaee06f6ccb 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
MikamiUitOpen 2:dcaee06f6ccb 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
MikamiUitOpen 2:dcaee06f6ccb 251
MikamiUitOpen 2:dcaee06f6ccb 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
MikamiUitOpen 2:dcaee06f6ccb 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
MikamiUitOpen 2:dcaee06f6ccb 254
MikamiUitOpen 2:dcaee06f6ccb 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
MikamiUitOpen 2:dcaee06f6ccb 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
MikamiUitOpen 2:dcaee06f6ccb 257
MikamiUitOpen 2:dcaee06f6ccb 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
MikamiUitOpen 2:dcaee06f6ccb 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
MikamiUitOpen 2:dcaee06f6ccb 260
MikamiUitOpen 2:dcaee06f6ccb 261
MikamiUitOpen 2:dcaee06f6ccb 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
MikamiUitOpen 2:dcaee06f6ccb 263 */
MikamiUitOpen 2:dcaee06f6ccb 264 typedef union
MikamiUitOpen 2:dcaee06f6ccb 265 {
MikamiUitOpen 2:dcaee06f6ccb 266 struct
MikamiUitOpen 2:dcaee06f6ccb 267 {
MikamiUitOpen 2:dcaee06f6ccb 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 2:dcaee06f6ccb 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
MikamiUitOpen 2:dcaee06f6ccb 270 } b; /*!< Structure used for bit access */
MikamiUitOpen 2:dcaee06f6ccb 271 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 2:dcaee06f6ccb 272 } IPSR_Type;
MikamiUitOpen 2:dcaee06f6ccb 273
MikamiUitOpen 2:dcaee06f6ccb 274 /* IPSR Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
MikamiUitOpen 2:dcaee06f6ccb 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
MikamiUitOpen 2:dcaee06f6ccb 277
MikamiUitOpen 2:dcaee06f6ccb 278
MikamiUitOpen 2:dcaee06f6ccb 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
MikamiUitOpen 2:dcaee06f6ccb 280 */
MikamiUitOpen 2:dcaee06f6ccb 281 typedef union
MikamiUitOpen 2:dcaee06f6ccb 282 {
MikamiUitOpen 2:dcaee06f6ccb 283 struct
MikamiUitOpen 2:dcaee06f6ccb 284 {
MikamiUitOpen 2:dcaee06f6ccb 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 2:dcaee06f6ccb 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
MikamiUitOpen 2:dcaee06f6ccb 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
MikamiUitOpen 2:dcaee06f6ccb 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
MikamiUitOpen 2:dcaee06f6ccb 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
MikamiUitOpen 2:dcaee06f6ccb 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 294 } b; /*!< Structure used for bit access */
MikamiUitOpen 2:dcaee06f6ccb 295 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 2:dcaee06f6ccb 296 } xPSR_Type;
MikamiUitOpen 2:dcaee06f6ccb 297
MikamiUitOpen 2:dcaee06f6ccb 298 /* xPSR Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
MikamiUitOpen 2:dcaee06f6ccb 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
MikamiUitOpen 2:dcaee06f6ccb 301
MikamiUitOpen 2:dcaee06f6ccb 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
MikamiUitOpen 2:dcaee06f6ccb 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
MikamiUitOpen 2:dcaee06f6ccb 304
MikamiUitOpen 2:dcaee06f6ccb 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
MikamiUitOpen 2:dcaee06f6ccb 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
MikamiUitOpen 2:dcaee06f6ccb 307
MikamiUitOpen 2:dcaee06f6ccb 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
MikamiUitOpen 2:dcaee06f6ccb 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
MikamiUitOpen 2:dcaee06f6ccb 310
MikamiUitOpen 2:dcaee06f6ccb 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
MikamiUitOpen 2:dcaee06f6ccb 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
MikamiUitOpen 2:dcaee06f6ccb 313
MikamiUitOpen 2:dcaee06f6ccb 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
MikamiUitOpen 2:dcaee06f6ccb 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
MikamiUitOpen 2:dcaee06f6ccb 316
MikamiUitOpen 2:dcaee06f6ccb 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
MikamiUitOpen 2:dcaee06f6ccb 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
MikamiUitOpen 2:dcaee06f6ccb 319
MikamiUitOpen 2:dcaee06f6ccb 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
MikamiUitOpen 2:dcaee06f6ccb 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
MikamiUitOpen 2:dcaee06f6ccb 322
MikamiUitOpen 2:dcaee06f6ccb 323
MikamiUitOpen 2:dcaee06f6ccb 324 /** \brief Union type to access the Control Registers (CONTROL).
MikamiUitOpen 2:dcaee06f6ccb 325 */
MikamiUitOpen 2:dcaee06f6ccb 326 typedef union
MikamiUitOpen 2:dcaee06f6ccb 327 {
MikamiUitOpen 2:dcaee06f6ccb 328 struct
MikamiUitOpen 2:dcaee06f6ccb 329 {
MikamiUitOpen 2:dcaee06f6ccb 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
MikamiUitOpen 2:dcaee06f6ccb 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
MikamiUitOpen 2:dcaee06f6ccb 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
MikamiUitOpen 2:dcaee06f6ccb 333 } b; /*!< Structure used for bit access */
MikamiUitOpen 2:dcaee06f6ccb 334 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 2:dcaee06f6ccb 335 } CONTROL_Type;
MikamiUitOpen 2:dcaee06f6ccb 336
MikamiUitOpen 2:dcaee06f6ccb 337 /* CONTROL Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
MikamiUitOpen 2:dcaee06f6ccb 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
MikamiUitOpen 2:dcaee06f6ccb 340
MikamiUitOpen 2:dcaee06f6ccb 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
MikamiUitOpen 2:dcaee06f6ccb 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
MikamiUitOpen 2:dcaee06f6ccb 343
MikamiUitOpen 2:dcaee06f6ccb 344 /*@} end of group CMSIS_CORE */
MikamiUitOpen 2:dcaee06f6ccb 345
MikamiUitOpen 2:dcaee06f6ccb 346
MikamiUitOpen 2:dcaee06f6ccb 347 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
MikamiUitOpen 2:dcaee06f6ccb 349 \brief Type definitions for the NVIC Registers
MikamiUitOpen 2:dcaee06f6ccb 350 @{
MikamiUitOpen 2:dcaee06f6ccb 351 */
MikamiUitOpen 2:dcaee06f6ccb 352
MikamiUitOpen 2:dcaee06f6ccb 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
MikamiUitOpen 2:dcaee06f6ccb 354 */
MikamiUitOpen 2:dcaee06f6ccb 355 typedef struct
MikamiUitOpen 2:dcaee06f6ccb 356 {
MikamiUitOpen 2:dcaee06f6ccb 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
MikamiUitOpen 2:dcaee06f6ccb 358 uint32_t RESERVED0[24];
MikamiUitOpen 2:dcaee06f6ccb 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
MikamiUitOpen 2:dcaee06f6ccb 360 uint32_t RSERVED1[24];
MikamiUitOpen 2:dcaee06f6ccb 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
MikamiUitOpen 2:dcaee06f6ccb 362 uint32_t RESERVED2[24];
MikamiUitOpen 2:dcaee06f6ccb 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
MikamiUitOpen 2:dcaee06f6ccb 364 uint32_t RESERVED3[24];
MikamiUitOpen 2:dcaee06f6ccb 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
MikamiUitOpen 2:dcaee06f6ccb 366 uint32_t RESERVED4[56];
MikamiUitOpen 2:dcaee06f6ccb 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
MikamiUitOpen 2:dcaee06f6ccb 368 uint32_t RESERVED5[644];
MikamiUitOpen 2:dcaee06f6ccb 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
MikamiUitOpen 2:dcaee06f6ccb 370 } NVIC_Type;
MikamiUitOpen 2:dcaee06f6ccb 371
MikamiUitOpen 2:dcaee06f6ccb 372 /* Software Triggered Interrupt Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
MikamiUitOpen 2:dcaee06f6ccb 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
MikamiUitOpen 2:dcaee06f6ccb 375
MikamiUitOpen 2:dcaee06f6ccb 376 /*@} end of group CMSIS_NVIC */
MikamiUitOpen 2:dcaee06f6ccb 377
MikamiUitOpen 2:dcaee06f6ccb 378
MikamiUitOpen 2:dcaee06f6ccb 379 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 380 \defgroup CMSIS_SCB System Control Block (SCB)
MikamiUitOpen 2:dcaee06f6ccb 381 \brief Type definitions for the System Control Block Registers
MikamiUitOpen 2:dcaee06f6ccb 382 @{
MikamiUitOpen 2:dcaee06f6ccb 383 */
MikamiUitOpen 2:dcaee06f6ccb 384
MikamiUitOpen 2:dcaee06f6ccb 385 /** \brief Structure type to access the System Control Block (SCB).
MikamiUitOpen 2:dcaee06f6ccb 386 */
MikamiUitOpen 2:dcaee06f6ccb 387 typedef struct
MikamiUitOpen 2:dcaee06f6ccb 388 {
MikamiUitOpen 2:dcaee06f6ccb 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
MikamiUitOpen 2:dcaee06f6ccb 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
MikamiUitOpen 2:dcaee06f6ccb 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
MikamiUitOpen 2:dcaee06f6ccb 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
MikamiUitOpen 2:dcaee06f6ccb 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
MikamiUitOpen 2:dcaee06f6ccb 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
MikamiUitOpen 2:dcaee06f6ccb 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
MikamiUitOpen 2:dcaee06f6ccb 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
MikamiUitOpen 2:dcaee06f6ccb 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
MikamiUitOpen 2:dcaee06f6ccb 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
MikamiUitOpen 2:dcaee06f6ccb 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
MikamiUitOpen 2:dcaee06f6ccb 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
MikamiUitOpen 2:dcaee06f6ccb 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
MikamiUitOpen 2:dcaee06f6ccb 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
MikamiUitOpen 2:dcaee06f6ccb 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
MikamiUitOpen 2:dcaee06f6ccb 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
MikamiUitOpen 2:dcaee06f6ccb 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
MikamiUitOpen 2:dcaee06f6ccb 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
MikamiUitOpen 2:dcaee06f6ccb 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
MikamiUitOpen 2:dcaee06f6ccb 408 uint32_t RESERVED0[5];
MikamiUitOpen 2:dcaee06f6ccb 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
MikamiUitOpen 2:dcaee06f6ccb 410 } SCB_Type;
MikamiUitOpen 2:dcaee06f6ccb 411
MikamiUitOpen 2:dcaee06f6ccb 412 /* SCB CPUID Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 413 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
MikamiUitOpen 2:dcaee06f6ccb 414 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
MikamiUitOpen 2:dcaee06f6ccb 415
MikamiUitOpen 2:dcaee06f6ccb 416 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
MikamiUitOpen 2:dcaee06f6ccb 417 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
MikamiUitOpen 2:dcaee06f6ccb 418
MikamiUitOpen 2:dcaee06f6ccb 419 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
MikamiUitOpen 2:dcaee06f6ccb 420 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
MikamiUitOpen 2:dcaee06f6ccb 421
MikamiUitOpen 2:dcaee06f6ccb 422 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
MikamiUitOpen 2:dcaee06f6ccb 423 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
MikamiUitOpen 2:dcaee06f6ccb 424
MikamiUitOpen 2:dcaee06f6ccb 425 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
MikamiUitOpen 2:dcaee06f6ccb 426 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
MikamiUitOpen 2:dcaee06f6ccb 427
MikamiUitOpen 2:dcaee06f6ccb 428 /* SCB Interrupt Control State Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 429 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
MikamiUitOpen 2:dcaee06f6ccb 430 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
MikamiUitOpen 2:dcaee06f6ccb 431
MikamiUitOpen 2:dcaee06f6ccb 432 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
MikamiUitOpen 2:dcaee06f6ccb 433 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
MikamiUitOpen 2:dcaee06f6ccb 434
MikamiUitOpen 2:dcaee06f6ccb 435 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
MikamiUitOpen 2:dcaee06f6ccb 436 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
MikamiUitOpen 2:dcaee06f6ccb 437
MikamiUitOpen 2:dcaee06f6ccb 438 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
MikamiUitOpen 2:dcaee06f6ccb 439 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
MikamiUitOpen 2:dcaee06f6ccb 440
MikamiUitOpen 2:dcaee06f6ccb 441 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
MikamiUitOpen 2:dcaee06f6ccb 442 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
MikamiUitOpen 2:dcaee06f6ccb 443
MikamiUitOpen 2:dcaee06f6ccb 444 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
MikamiUitOpen 2:dcaee06f6ccb 445 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
MikamiUitOpen 2:dcaee06f6ccb 446
MikamiUitOpen 2:dcaee06f6ccb 447 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
MikamiUitOpen 2:dcaee06f6ccb 448 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
MikamiUitOpen 2:dcaee06f6ccb 449
MikamiUitOpen 2:dcaee06f6ccb 450 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
MikamiUitOpen 2:dcaee06f6ccb 451 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
MikamiUitOpen 2:dcaee06f6ccb 452
MikamiUitOpen 2:dcaee06f6ccb 453 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
MikamiUitOpen 2:dcaee06f6ccb 454 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
MikamiUitOpen 2:dcaee06f6ccb 455
MikamiUitOpen 2:dcaee06f6ccb 456 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
MikamiUitOpen 2:dcaee06f6ccb 457 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
MikamiUitOpen 2:dcaee06f6ccb 458
MikamiUitOpen 2:dcaee06f6ccb 459 /* SCB Vector Table Offset Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 460 #if (__CM3_REV < 0x0201) /* core r2p1 */
MikamiUitOpen 2:dcaee06f6ccb 461 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
MikamiUitOpen 2:dcaee06f6ccb 462 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
MikamiUitOpen 2:dcaee06f6ccb 463
MikamiUitOpen 2:dcaee06f6ccb 464 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
MikamiUitOpen 2:dcaee06f6ccb 465 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
MikamiUitOpen 2:dcaee06f6ccb 466 #else
MikamiUitOpen 2:dcaee06f6ccb 467 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
MikamiUitOpen 2:dcaee06f6ccb 468 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
MikamiUitOpen 2:dcaee06f6ccb 469 #endif
MikamiUitOpen 2:dcaee06f6ccb 470
MikamiUitOpen 2:dcaee06f6ccb 471 /* SCB Application Interrupt and Reset Control Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 472 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
MikamiUitOpen 2:dcaee06f6ccb 473 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
MikamiUitOpen 2:dcaee06f6ccb 474
MikamiUitOpen 2:dcaee06f6ccb 475 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
MikamiUitOpen 2:dcaee06f6ccb 476 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
MikamiUitOpen 2:dcaee06f6ccb 477
MikamiUitOpen 2:dcaee06f6ccb 478 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
MikamiUitOpen 2:dcaee06f6ccb 479 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
MikamiUitOpen 2:dcaee06f6ccb 480
MikamiUitOpen 2:dcaee06f6ccb 481 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
MikamiUitOpen 2:dcaee06f6ccb 482 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
MikamiUitOpen 2:dcaee06f6ccb 483
MikamiUitOpen 2:dcaee06f6ccb 484 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
MikamiUitOpen 2:dcaee06f6ccb 485 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
MikamiUitOpen 2:dcaee06f6ccb 486
MikamiUitOpen 2:dcaee06f6ccb 487 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
MikamiUitOpen 2:dcaee06f6ccb 488 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
MikamiUitOpen 2:dcaee06f6ccb 489
MikamiUitOpen 2:dcaee06f6ccb 490 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
MikamiUitOpen 2:dcaee06f6ccb 491 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
MikamiUitOpen 2:dcaee06f6ccb 492
MikamiUitOpen 2:dcaee06f6ccb 493 /* SCB System Control Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 494 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
MikamiUitOpen 2:dcaee06f6ccb 495 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
MikamiUitOpen 2:dcaee06f6ccb 496
MikamiUitOpen 2:dcaee06f6ccb 497 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
MikamiUitOpen 2:dcaee06f6ccb 498 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
MikamiUitOpen 2:dcaee06f6ccb 499
MikamiUitOpen 2:dcaee06f6ccb 500 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
MikamiUitOpen 2:dcaee06f6ccb 501 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
MikamiUitOpen 2:dcaee06f6ccb 502
MikamiUitOpen 2:dcaee06f6ccb 503 /* SCB Configuration Control Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 504 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
MikamiUitOpen 2:dcaee06f6ccb 505 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
MikamiUitOpen 2:dcaee06f6ccb 506
MikamiUitOpen 2:dcaee06f6ccb 507 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
MikamiUitOpen 2:dcaee06f6ccb 508 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
MikamiUitOpen 2:dcaee06f6ccb 509
MikamiUitOpen 2:dcaee06f6ccb 510 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
MikamiUitOpen 2:dcaee06f6ccb 511 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
MikamiUitOpen 2:dcaee06f6ccb 512
MikamiUitOpen 2:dcaee06f6ccb 513 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
MikamiUitOpen 2:dcaee06f6ccb 514 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
MikamiUitOpen 2:dcaee06f6ccb 515
MikamiUitOpen 2:dcaee06f6ccb 516 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
MikamiUitOpen 2:dcaee06f6ccb 517 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
MikamiUitOpen 2:dcaee06f6ccb 518
MikamiUitOpen 2:dcaee06f6ccb 519 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
MikamiUitOpen 2:dcaee06f6ccb 520 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 521
MikamiUitOpen 2:dcaee06f6ccb 522 /* SCB System Handler Control and State Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 523 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 524 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 525
MikamiUitOpen 2:dcaee06f6ccb 526 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 527 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 528
MikamiUitOpen 2:dcaee06f6ccb 529 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 530 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 531
MikamiUitOpen 2:dcaee06f6ccb 532 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
MikamiUitOpen 2:dcaee06f6ccb 533 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
MikamiUitOpen 2:dcaee06f6ccb 534
MikamiUitOpen 2:dcaee06f6ccb 535 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
MikamiUitOpen 2:dcaee06f6ccb 536 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
MikamiUitOpen 2:dcaee06f6ccb 537
MikamiUitOpen 2:dcaee06f6ccb 538 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
MikamiUitOpen 2:dcaee06f6ccb 539 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
MikamiUitOpen 2:dcaee06f6ccb 540
MikamiUitOpen 2:dcaee06f6ccb 541 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
MikamiUitOpen 2:dcaee06f6ccb 542 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
MikamiUitOpen 2:dcaee06f6ccb 543
MikamiUitOpen 2:dcaee06f6ccb 544 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
MikamiUitOpen 2:dcaee06f6ccb 545 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
MikamiUitOpen 2:dcaee06f6ccb 546
MikamiUitOpen 2:dcaee06f6ccb 547 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
MikamiUitOpen 2:dcaee06f6ccb 548 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
MikamiUitOpen 2:dcaee06f6ccb 549
MikamiUitOpen 2:dcaee06f6ccb 550 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
MikamiUitOpen 2:dcaee06f6ccb 551 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
MikamiUitOpen 2:dcaee06f6ccb 552
MikamiUitOpen 2:dcaee06f6ccb 553 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
MikamiUitOpen 2:dcaee06f6ccb 554 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
MikamiUitOpen 2:dcaee06f6ccb 555
MikamiUitOpen 2:dcaee06f6ccb 556 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
MikamiUitOpen 2:dcaee06f6ccb 557 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
MikamiUitOpen 2:dcaee06f6ccb 558
MikamiUitOpen 2:dcaee06f6ccb 559 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
MikamiUitOpen 2:dcaee06f6ccb 560 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
MikamiUitOpen 2:dcaee06f6ccb 561
MikamiUitOpen 2:dcaee06f6ccb 562 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
MikamiUitOpen 2:dcaee06f6ccb 563 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
MikamiUitOpen 2:dcaee06f6ccb 564
MikamiUitOpen 2:dcaee06f6ccb 565 /* SCB Configurable Fault Status Registers Definitions */
MikamiUitOpen 2:dcaee06f6ccb 566 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
MikamiUitOpen 2:dcaee06f6ccb 567 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
MikamiUitOpen 2:dcaee06f6ccb 568
MikamiUitOpen 2:dcaee06f6ccb 569 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
MikamiUitOpen 2:dcaee06f6ccb 570 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
MikamiUitOpen 2:dcaee06f6ccb 571
MikamiUitOpen 2:dcaee06f6ccb 572 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
MikamiUitOpen 2:dcaee06f6ccb 573 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
MikamiUitOpen 2:dcaee06f6ccb 574
MikamiUitOpen 2:dcaee06f6ccb 575 /* SCB Hard Fault Status Registers Definitions */
MikamiUitOpen 2:dcaee06f6ccb 576 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
MikamiUitOpen 2:dcaee06f6ccb 577 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
MikamiUitOpen 2:dcaee06f6ccb 578
MikamiUitOpen 2:dcaee06f6ccb 579 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
MikamiUitOpen 2:dcaee06f6ccb 580 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
MikamiUitOpen 2:dcaee06f6ccb 581
MikamiUitOpen 2:dcaee06f6ccb 582 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
MikamiUitOpen 2:dcaee06f6ccb 583 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
MikamiUitOpen 2:dcaee06f6ccb 584
MikamiUitOpen 2:dcaee06f6ccb 585 /* SCB Debug Fault Status Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 586 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
MikamiUitOpen 2:dcaee06f6ccb 587 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
MikamiUitOpen 2:dcaee06f6ccb 588
MikamiUitOpen 2:dcaee06f6ccb 589 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
MikamiUitOpen 2:dcaee06f6ccb 590 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
MikamiUitOpen 2:dcaee06f6ccb 591
MikamiUitOpen 2:dcaee06f6ccb 592 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
MikamiUitOpen 2:dcaee06f6ccb 593 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
MikamiUitOpen 2:dcaee06f6ccb 594
MikamiUitOpen 2:dcaee06f6ccb 595 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
MikamiUitOpen 2:dcaee06f6ccb 596 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
MikamiUitOpen 2:dcaee06f6ccb 597
MikamiUitOpen 2:dcaee06f6ccb 598 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
MikamiUitOpen 2:dcaee06f6ccb 599 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
MikamiUitOpen 2:dcaee06f6ccb 600
MikamiUitOpen 2:dcaee06f6ccb 601 /*@} end of group CMSIS_SCB */
MikamiUitOpen 2:dcaee06f6ccb 602
MikamiUitOpen 2:dcaee06f6ccb 603
MikamiUitOpen 2:dcaee06f6ccb 604 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 605 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
MikamiUitOpen 2:dcaee06f6ccb 606 \brief Type definitions for the System Control and ID Register not in the SCB
MikamiUitOpen 2:dcaee06f6ccb 607 @{
MikamiUitOpen 2:dcaee06f6ccb 608 */
MikamiUitOpen 2:dcaee06f6ccb 609
MikamiUitOpen 2:dcaee06f6ccb 610 /** \brief Structure type to access the System Control and ID Register not in the SCB.
MikamiUitOpen 2:dcaee06f6ccb 611 */
MikamiUitOpen 2:dcaee06f6ccb 612 typedef struct
MikamiUitOpen 2:dcaee06f6ccb 613 {
MikamiUitOpen 2:dcaee06f6ccb 614 uint32_t RESERVED0[1];
MikamiUitOpen 2:dcaee06f6ccb 615 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
MikamiUitOpen 2:dcaee06f6ccb 616 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
MikamiUitOpen 2:dcaee06f6ccb 617 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
MikamiUitOpen 2:dcaee06f6ccb 618 #else
MikamiUitOpen 2:dcaee06f6ccb 619 uint32_t RESERVED1[1];
MikamiUitOpen 2:dcaee06f6ccb 620 #endif
MikamiUitOpen 2:dcaee06f6ccb 621 } SCnSCB_Type;
MikamiUitOpen 2:dcaee06f6ccb 622
MikamiUitOpen 2:dcaee06f6ccb 623 /* Interrupt Controller Type Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 624 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
MikamiUitOpen 2:dcaee06f6ccb 625 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
MikamiUitOpen 2:dcaee06f6ccb 626
MikamiUitOpen 2:dcaee06f6ccb 627 /* Auxiliary Control Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 628
MikamiUitOpen 2:dcaee06f6ccb 629 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
MikamiUitOpen 2:dcaee06f6ccb 630 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
MikamiUitOpen 2:dcaee06f6ccb 631
MikamiUitOpen 2:dcaee06f6ccb 632 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
MikamiUitOpen 2:dcaee06f6ccb 633 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
MikamiUitOpen 2:dcaee06f6ccb 634
MikamiUitOpen 2:dcaee06f6ccb 635 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
MikamiUitOpen 2:dcaee06f6ccb 636 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
MikamiUitOpen 2:dcaee06f6ccb 637
MikamiUitOpen 2:dcaee06f6ccb 638 /*@} end of group CMSIS_SCnotSCB */
MikamiUitOpen 2:dcaee06f6ccb 639
MikamiUitOpen 2:dcaee06f6ccb 640
MikamiUitOpen 2:dcaee06f6ccb 641 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 642 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
MikamiUitOpen 2:dcaee06f6ccb 643 \brief Type definitions for the System Timer Registers.
MikamiUitOpen 2:dcaee06f6ccb 644 @{
MikamiUitOpen 2:dcaee06f6ccb 645 */
MikamiUitOpen 2:dcaee06f6ccb 646
MikamiUitOpen 2:dcaee06f6ccb 647 /** \brief Structure type to access the System Timer (SysTick).
MikamiUitOpen 2:dcaee06f6ccb 648 */
MikamiUitOpen 2:dcaee06f6ccb 649 typedef struct
MikamiUitOpen 2:dcaee06f6ccb 650 {
MikamiUitOpen 2:dcaee06f6ccb 651 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
MikamiUitOpen 2:dcaee06f6ccb 652 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
MikamiUitOpen 2:dcaee06f6ccb 653 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
MikamiUitOpen 2:dcaee06f6ccb 654 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
MikamiUitOpen 2:dcaee06f6ccb 655 } SysTick_Type;
MikamiUitOpen 2:dcaee06f6ccb 656
MikamiUitOpen 2:dcaee06f6ccb 657 /* SysTick Control / Status Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 658 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
MikamiUitOpen 2:dcaee06f6ccb 659 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
MikamiUitOpen 2:dcaee06f6ccb 660
MikamiUitOpen 2:dcaee06f6ccb 661 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
MikamiUitOpen 2:dcaee06f6ccb 662 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
MikamiUitOpen 2:dcaee06f6ccb 663
MikamiUitOpen 2:dcaee06f6ccb 664 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
MikamiUitOpen 2:dcaee06f6ccb 665 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
MikamiUitOpen 2:dcaee06f6ccb 666
MikamiUitOpen 2:dcaee06f6ccb 667 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
MikamiUitOpen 2:dcaee06f6ccb 668 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
MikamiUitOpen 2:dcaee06f6ccb 669
MikamiUitOpen 2:dcaee06f6ccb 670 /* SysTick Reload Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 671 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
MikamiUitOpen 2:dcaee06f6ccb 672 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
MikamiUitOpen 2:dcaee06f6ccb 673
MikamiUitOpen 2:dcaee06f6ccb 674 /* SysTick Current Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 675 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
MikamiUitOpen 2:dcaee06f6ccb 676 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
MikamiUitOpen 2:dcaee06f6ccb 677
MikamiUitOpen 2:dcaee06f6ccb 678 /* SysTick Calibration Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 679 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
MikamiUitOpen 2:dcaee06f6ccb 680 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
MikamiUitOpen 2:dcaee06f6ccb 681
MikamiUitOpen 2:dcaee06f6ccb 682 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
MikamiUitOpen 2:dcaee06f6ccb 683 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
MikamiUitOpen 2:dcaee06f6ccb 684
MikamiUitOpen 2:dcaee06f6ccb 685 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
MikamiUitOpen 2:dcaee06f6ccb 686 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
MikamiUitOpen 2:dcaee06f6ccb 687
MikamiUitOpen 2:dcaee06f6ccb 688 /*@} end of group CMSIS_SysTick */
MikamiUitOpen 2:dcaee06f6ccb 689
MikamiUitOpen 2:dcaee06f6ccb 690
MikamiUitOpen 2:dcaee06f6ccb 691 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 692 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
MikamiUitOpen 2:dcaee06f6ccb 693 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
MikamiUitOpen 2:dcaee06f6ccb 694 @{
MikamiUitOpen 2:dcaee06f6ccb 695 */
MikamiUitOpen 2:dcaee06f6ccb 696
MikamiUitOpen 2:dcaee06f6ccb 697 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
MikamiUitOpen 2:dcaee06f6ccb 698 */
MikamiUitOpen 2:dcaee06f6ccb 699 typedef struct
MikamiUitOpen 2:dcaee06f6ccb 700 {
MikamiUitOpen 2:dcaee06f6ccb 701 __O union
MikamiUitOpen 2:dcaee06f6ccb 702 {
MikamiUitOpen 2:dcaee06f6ccb 703 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
MikamiUitOpen 2:dcaee06f6ccb 704 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
MikamiUitOpen 2:dcaee06f6ccb 705 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
MikamiUitOpen 2:dcaee06f6ccb 706 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
MikamiUitOpen 2:dcaee06f6ccb 707 uint32_t RESERVED0[864];
MikamiUitOpen 2:dcaee06f6ccb 708 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
MikamiUitOpen 2:dcaee06f6ccb 709 uint32_t RESERVED1[15];
MikamiUitOpen 2:dcaee06f6ccb 710 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
MikamiUitOpen 2:dcaee06f6ccb 711 uint32_t RESERVED2[15];
MikamiUitOpen 2:dcaee06f6ccb 712 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
MikamiUitOpen 2:dcaee06f6ccb 713 uint32_t RESERVED3[29];
MikamiUitOpen 2:dcaee06f6ccb 714 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
MikamiUitOpen 2:dcaee06f6ccb 715 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
MikamiUitOpen 2:dcaee06f6ccb 716 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
MikamiUitOpen 2:dcaee06f6ccb 717 uint32_t RESERVED4[43];
MikamiUitOpen 2:dcaee06f6ccb 718 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
MikamiUitOpen 2:dcaee06f6ccb 719 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
MikamiUitOpen 2:dcaee06f6ccb 720 uint32_t RESERVED5[6];
MikamiUitOpen 2:dcaee06f6ccb 721 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
MikamiUitOpen 2:dcaee06f6ccb 722 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
MikamiUitOpen 2:dcaee06f6ccb 723 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
MikamiUitOpen 2:dcaee06f6ccb 724 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
MikamiUitOpen 2:dcaee06f6ccb 725 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
MikamiUitOpen 2:dcaee06f6ccb 726 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
MikamiUitOpen 2:dcaee06f6ccb 727 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
MikamiUitOpen 2:dcaee06f6ccb 728 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
MikamiUitOpen 2:dcaee06f6ccb 729 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
MikamiUitOpen 2:dcaee06f6ccb 730 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
MikamiUitOpen 2:dcaee06f6ccb 731 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
MikamiUitOpen 2:dcaee06f6ccb 732 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
MikamiUitOpen 2:dcaee06f6ccb 733 } ITM_Type;
MikamiUitOpen 2:dcaee06f6ccb 734
MikamiUitOpen 2:dcaee06f6ccb 735 /* ITM Trace Privilege Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 736 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
MikamiUitOpen 2:dcaee06f6ccb 737 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
MikamiUitOpen 2:dcaee06f6ccb 738
MikamiUitOpen 2:dcaee06f6ccb 739 /* ITM Trace Control Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 740 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
MikamiUitOpen 2:dcaee06f6ccb 741 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
MikamiUitOpen 2:dcaee06f6ccb 742
MikamiUitOpen 2:dcaee06f6ccb 743 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
MikamiUitOpen 2:dcaee06f6ccb 744 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
MikamiUitOpen 2:dcaee06f6ccb 745
MikamiUitOpen 2:dcaee06f6ccb 746 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
MikamiUitOpen 2:dcaee06f6ccb 747 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
MikamiUitOpen 2:dcaee06f6ccb 748
MikamiUitOpen 2:dcaee06f6ccb 749 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
MikamiUitOpen 2:dcaee06f6ccb 750 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
MikamiUitOpen 2:dcaee06f6ccb 751
MikamiUitOpen 2:dcaee06f6ccb 752 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
MikamiUitOpen 2:dcaee06f6ccb 753 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 754
MikamiUitOpen 2:dcaee06f6ccb 755 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 756 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 757
MikamiUitOpen 2:dcaee06f6ccb 758 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
MikamiUitOpen 2:dcaee06f6ccb 759 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 760
MikamiUitOpen 2:dcaee06f6ccb 761 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
MikamiUitOpen 2:dcaee06f6ccb 762 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 763
MikamiUitOpen 2:dcaee06f6ccb 764 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
MikamiUitOpen 2:dcaee06f6ccb 765 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
MikamiUitOpen 2:dcaee06f6ccb 766
MikamiUitOpen 2:dcaee06f6ccb 767 /* ITM Integration Write Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 768 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
MikamiUitOpen 2:dcaee06f6ccb 769 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
MikamiUitOpen 2:dcaee06f6ccb 770
MikamiUitOpen 2:dcaee06f6ccb 771 /* ITM Integration Read Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 772 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
MikamiUitOpen 2:dcaee06f6ccb 773 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
MikamiUitOpen 2:dcaee06f6ccb 774
MikamiUitOpen 2:dcaee06f6ccb 775 /* ITM Integration Mode Control Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 776 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
MikamiUitOpen 2:dcaee06f6ccb 777 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
MikamiUitOpen 2:dcaee06f6ccb 778
MikamiUitOpen 2:dcaee06f6ccb 779 /* ITM Lock Status Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 780 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
MikamiUitOpen 2:dcaee06f6ccb 781 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
MikamiUitOpen 2:dcaee06f6ccb 782
MikamiUitOpen 2:dcaee06f6ccb 783 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
MikamiUitOpen 2:dcaee06f6ccb 784 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
MikamiUitOpen 2:dcaee06f6ccb 785
MikamiUitOpen 2:dcaee06f6ccb 786 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
MikamiUitOpen 2:dcaee06f6ccb 787 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
MikamiUitOpen 2:dcaee06f6ccb 788
MikamiUitOpen 2:dcaee06f6ccb 789 /*@}*/ /* end of group CMSIS_ITM */
MikamiUitOpen 2:dcaee06f6ccb 790
MikamiUitOpen 2:dcaee06f6ccb 791
MikamiUitOpen 2:dcaee06f6ccb 792 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 793 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
MikamiUitOpen 2:dcaee06f6ccb 794 \brief Type definitions for the Data Watchpoint and Trace (DWT)
MikamiUitOpen 2:dcaee06f6ccb 795 @{
MikamiUitOpen 2:dcaee06f6ccb 796 */
MikamiUitOpen 2:dcaee06f6ccb 797
MikamiUitOpen 2:dcaee06f6ccb 798 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
MikamiUitOpen 2:dcaee06f6ccb 799 */
MikamiUitOpen 2:dcaee06f6ccb 800 typedef struct
MikamiUitOpen 2:dcaee06f6ccb 801 {
MikamiUitOpen 2:dcaee06f6ccb 802 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
MikamiUitOpen 2:dcaee06f6ccb 803 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
MikamiUitOpen 2:dcaee06f6ccb 804 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
MikamiUitOpen 2:dcaee06f6ccb 805 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
MikamiUitOpen 2:dcaee06f6ccb 806 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
MikamiUitOpen 2:dcaee06f6ccb 807 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
MikamiUitOpen 2:dcaee06f6ccb 808 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
MikamiUitOpen 2:dcaee06f6ccb 809 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
MikamiUitOpen 2:dcaee06f6ccb 810 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
MikamiUitOpen 2:dcaee06f6ccb 811 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
MikamiUitOpen 2:dcaee06f6ccb 812 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
MikamiUitOpen 2:dcaee06f6ccb 813 uint32_t RESERVED0[1];
MikamiUitOpen 2:dcaee06f6ccb 814 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
MikamiUitOpen 2:dcaee06f6ccb 815 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
MikamiUitOpen 2:dcaee06f6ccb 816 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
MikamiUitOpen 2:dcaee06f6ccb 817 uint32_t RESERVED1[1];
MikamiUitOpen 2:dcaee06f6ccb 818 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
MikamiUitOpen 2:dcaee06f6ccb 819 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
MikamiUitOpen 2:dcaee06f6ccb 820 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
MikamiUitOpen 2:dcaee06f6ccb 821 uint32_t RESERVED2[1];
MikamiUitOpen 2:dcaee06f6ccb 822 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
MikamiUitOpen 2:dcaee06f6ccb 823 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
MikamiUitOpen 2:dcaee06f6ccb 824 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
MikamiUitOpen 2:dcaee06f6ccb 825 } DWT_Type;
MikamiUitOpen 2:dcaee06f6ccb 826
MikamiUitOpen 2:dcaee06f6ccb 827 /* DWT Control Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 828 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
MikamiUitOpen 2:dcaee06f6ccb 829 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
MikamiUitOpen 2:dcaee06f6ccb 830
MikamiUitOpen 2:dcaee06f6ccb 831 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
MikamiUitOpen 2:dcaee06f6ccb 832 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
MikamiUitOpen 2:dcaee06f6ccb 833
MikamiUitOpen 2:dcaee06f6ccb 834 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
MikamiUitOpen 2:dcaee06f6ccb 835 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
MikamiUitOpen 2:dcaee06f6ccb 836
MikamiUitOpen 2:dcaee06f6ccb 837 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
MikamiUitOpen 2:dcaee06f6ccb 838 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
MikamiUitOpen 2:dcaee06f6ccb 839
MikamiUitOpen 2:dcaee06f6ccb 840 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
MikamiUitOpen 2:dcaee06f6ccb 841 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
MikamiUitOpen 2:dcaee06f6ccb 842
MikamiUitOpen 2:dcaee06f6ccb 843 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 844 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 845
MikamiUitOpen 2:dcaee06f6ccb 846 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 847 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 848
MikamiUitOpen 2:dcaee06f6ccb 849 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 850 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 851
MikamiUitOpen 2:dcaee06f6ccb 852 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 853 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 854
MikamiUitOpen 2:dcaee06f6ccb 855 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 856 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 857
MikamiUitOpen 2:dcaee06f6ccb 858 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 859 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 860
MikamiUitOpen 2:dcaee06f6ccb 861 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
MikamiUitOpen 2:dcaee06f6ccb 862 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 863
MikamiUitOpen 2:dcaee06f6ccb 864 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
MikamiUitOpen 2:dcaee06f6ccb 865 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 866
MikamiUitOpen 2:dcaee06f6ccb 867 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
MikamiUitOpen 2:dcaee06f6ccb 868 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
MikamiUitOpen 2:dcaee06f6ccb 869
MikamiUitOpen 2:dcaee06f6ccb 870 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
MikamiUitOpen 2:dcaee06f6ccb 871 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
MikamiUitOpen 2:dcaee06f6ccb 872
MikamiUitOpen 2:dcaee06f6ccb 873 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
MikamiUitOpen 2:dcaee06f6ccb 874 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
MikamiUitOpen 2:dcaee06f6ccb 875
MikamiUitOpen 2:dcaee06f6ccb 876 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
MikamiUitOpen 2:dcaee06f6ccb 877 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
MikamiUitOpen 2:dcaee06f6ccb 878
MikamiUitOpen 2:dcaee06f6ccb 879 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
MikamiUitOpen 2:dcaee06f6ccb 880 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 881
MikamiUitOpen 2:dcaee06f6ccb 882 /* DWT CPI Count Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 883 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
MikamiUitOpen 2:dcaee06f6ccb 884 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
MikamiUitOpen 2:dcaee06f6ccb 885
MikamiUitOpen 2:dcaee06f6ccb 886 /* DWT Exception Overhead Count Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 887 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
MikamiUitOpen 2:dcaee06f6ccb 888 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
MikamiUitOpen 2:dcaee06f6ccb 889
MikamiUitOpen 2:dcaee06f6ccb 890 /* DWT Sleep Count Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 891 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
MikamiUitOpen 2:dcaee06f6ccb 892 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
MikamiUitOpen 2:dcaee06f6ccb 893
MikamiUitOpen 2:dcaee06f6ccb 894 /* DWT LSU Count Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 895 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
MikamiUitOpen 2:dcaee06f6ccb 896 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
MikamiUitOpen 2:dcaee06f6ccb 897
MikamiUitOpen 2:dcaee06f6ccb 898 /* DWT Folded-instruction Count Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 899 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
MikamiUitOpen 2:dcaee06f6ccb 900 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
MikamiUitOpen 2:dcaee06f6ccb 901
MikamiUitOpen 2:dcaee06f6ccb 902 /* DWT Comparator Mask Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 903 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
MikamiUitOpen 2:dcaee06f6ccb 904 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
MikamiUitOpen 2:dcaee06f6ccb 905
MikamiUitOpen 2:dcaee06f6ccb 906 /* DWT Comparator Function Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 907 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
MikamiUitOpen 2:dcaee06f6ccb 908 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
MikamiUitOpen 2:dcaee06f6ccb 909
MikamiUitOpen 2:dcaee06f6ccb 910 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
MikamiUitOpen 2:dcaee06f6ccb 911 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
MikamiUitOpen 2:dcaee06f6ccb 912
MikamiUitOpen 2:dcaee06f6ccb 913 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
MikamiUitOpen 2:dcaee06f6ccb 914 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
MikamiUitOpen 2:dcaee06f6ccb 915
MikamiUitOpen 2:dcaee06f6ccb 916 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
MikamiUitOpen 2:dcaee06f6ccb 917 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
MikamiUitOpen 2:dcaee06f6ccb 918
MikamiUitOpen 2:dcaee06f6ccb 919 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
MikamiUitOpen 2:dcaee06f6ccb 920 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 921
MikamiUitOpen 2:dcaee06f6ccb 922 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
MikamiUitOpen 2:dcaee06f6ccb 923 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
MikamiUitOpen 2:dcaee06f6ccb 924
MikamiUitOpen 2:dcaee06f6ccb 925 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
MikamiUitOpen 2:dcaee06f6ccb 926 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
MikamiUitOpen 2:dcaee06f6ccb 927
MikamiUitOpen 2:dcaee06f6ccb 928 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
MikamiUitOpen 2:dcaee06f6ccb 929 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
MikamiUitOpen 2:dcaee06f6ccb 930
MikamiUitOpen 2:dcaee06f6ccb 931 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
MikamiUitOpen 2:dcaee06f6ccb 932 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
MikamiUitOpen 2:dcaee06f6ccb 933
MikamiUitOpen 2:dcaee06f6ccb 934 /*@}*/ /* end of group CMSIS_DWT */
MikamiUitOpen 2:dcaee06f6ccb 935
MikamiUitOpen 2:dcaee06f6ccb 936
MikamiUitOpen 2:dcaee06f6ccb 937 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 938 \defgroup CMSIS_TPI Trace Port Interface (TPI)
MikamiUitOpen 2:dcaee06f6ccb 939 \brief Type definitions for the Trace Port Interface (TPI)
MikamiUitOpen 2:dcaee06f6ccb 940 @{
MikamiUitOpen 2:dcaee06f6ccb 941 */
MikamiUitOpen 2:dcaee06f6ccb 942
MikamiUitOpen 2:dcaee06f6ccb 943 /** \brief Structure type to access the Trace Port Interface Register (TPI).
MikamiUitOpen 2:dcaee06f6ccb 944 */
MikamiUitOpen 2:dcaee06f6ccb 945 typedef struct
MikamiUitOpen 2:dcaee06f6ccb 946 {
MikamiUitOpen 2:dcaee06f6ccb 947 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
MikamiUitOpen 2:dcaee06f6ccb 948 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
MikamiUitOpen 2:dcaee06f6ccb 949 uint32_t RESERVED0[2];
MikamiUitOpen 2:dcaee06f6ccb 950 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
MikamiUitOpen 2:dcaee06f6ccb 951 uint32_t RESERVED1[55];
MikamiUitOpen 2:dcaee06f6ccb 952 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
MikamiUitOpen 2:dcaee06f6ccb 953 uint32_t RESERVED2[131];
MikamiUitOpen 2:dcaee06f6ccb 954 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
MikamiUitOpen 2:dcaee06f6ccb 955 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
MikamiUitOpen 2:dcaee06f6ccb 956 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
MikamiUitOpen 2:dcaee06f6ccb 957 uint32_t RESERVED3[759];
MikamiUitOpen 2:dcaee06f6ccb 958 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
MikamiUitOpen 2:dcaee06f6ccb 959 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
MikamiUitOpen 2:dcaee06f6ccb 960 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
MikamiUitOpen 2:dcaee06f6ccb 961 uint32_t RESERVED4[1];
MikamiUitOpen 2:dcaee06f6ccb 962 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
MikamiUitOpen 2:dcaee06f6ccb 963 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
MikamiUitOpen 2:dcaee06f6ccb 964 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
MikamiUitOpen 2:dcaee06f6ccb 965 uint32_t RESERVED5[39];
MikamiUitOpen 2:dcaee06f6ccb 966 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
MikamiUitOpen 2:dcaee06f6ccb 967 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
MikamiUitOpen 2:dcaee06f6ccb 968 uint32_t RESERVED7[8];
MikamiUitOpen 2:dcaee06f6ccb 969 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
MikamiUitOpen 2:dcaee06f6ccb 970 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
MikamiUitOpen 2:dcaee06f6ccb 971 } TPI_Type;
MikamiUitOpen 2:dcaee06f6ccb 972
MikamiUitOpen 2:dcaee06f6ccb 973 /* TPI Asynchronous Clock Prescaler Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 974 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
MikamiUitOpen 2:dcaee06f6ccb 975 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
MikamiUitOpen 2:dcaee06f6ccb 976
MikamiUitOpen 2:dcaee06f6ccb 977 /* TPI Selected Pin Protocol Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 978 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
MikamiUitOpen 2:dcaee06f6ccb 979 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
MikamiUitOpen 2:dcaee06f6ccb 980
MikamiUitOpen 2:dcaee06f6ccb 981 /* TPI Formatter and Flush Status Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 982 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
MikamiUitOpen 2:dcaee06f6ccb 983 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
MikamiUitOpen 2:dcaee06f6ccb 984
MikamiUitOpen 2:dcaee06f6ccb 985 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
MikamiUitOpen 2:dcaee06f6ccb 986 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
MikamiUitOpen 2:dcaee06f6ccb 987
MikamiUitOpen 2:dcaee06f6ccb 988 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
MikamiUitOpen 2:dcaee06f6ccb 989 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
MikamiUitOpen 2:dcaee06f6ccb 990
MikamiUitOpen 2:dcaee06f6ccb 991 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
MikamiUitOpen 2:dcaee06f6ccb 992 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
MikamiUitOpen 2:dcaee06f6ccb 993
MikamiUitOpen 2:dcaee06f6ccb 994 /* TPI Formatter and Flush Control Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 995 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
MikamiUitOpen 2:dcaee06f6ccb 996 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
MikamiUitOpen 2:dcaee06f6ccb 997
MikamiUitOpen 2:dcaee06f6ccb 998 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
MikamiUitOpen 2:dcaee06f6ccb 999 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
MikamiUitOpen 2:dcaee06f6ccb 1000
MikamiUitOpen 2:dcaee06f6ccb 1001 /* TPI TRIGGER Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 1002 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
MikamiUitOpen 2:dcaee06f6ccb 1003 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
MikamiUitOpen 2:dcaee06f6ccb 1004
MikamiUitOpen 2:dcaee06f6ccb 1005 /* TPI Integration ETM Data Register Definitions (FIFO0) */
MikamiUitOpen 2:dcaee06f6ccb 1006 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
MikamiUitOpen 2:dcaee06f6ccb 1007 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
MikamiUitOpen 2:dcaee06f6ccb 1008
MikamiUitOpen 2:dcaee06f6ccb 1009 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
MikamiUitOpen 2:dcaee06f6ccb 1010 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
MikamiUitOpen 2:dcaee06f6ccb 1011
MikamiUitOpen 2:dcaee06f6ccb 1012 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
MikamiUitOpen 2:dcaee06f6ccb 1013 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
MikamiUitOpen 2:dcaee06f6ccb 1014
MikamiUitOpen 2:dcaee06f6ccb 1015 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
MikamiUitOpen 2:dcaee06f6ccb 1016 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
MikamiUitOpen 2:dcaee06f6ccb 1017
MikamiUitOpen 2:dcaee06f6ccb 1018 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
MikamiUitOpen 2:dcaee06f6ccb 1019 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
MikamiUitOpen 2:dcaee06f6ccb 1020
MikamiUitOpen 2:dcaee06f6ccb 1021 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
MikamiUitOpen 2:dcaee06f6ccb 1022 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
MikamiUitOpen 2:dcaee06f6ccb 1023
MikamiUitOpen 2:dcaee06f6ccb 1024 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
MikamiUitOpen 2:dcaee06f6ccb 1025 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
MikamiUitOpen 2:dcaee06f6ccb 1026
MikamiUitOpen 2:dcaee06f6ccb 1027 /* TPI ITATBCTR2 Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 1028 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
MikamiUitOpen 2:dcaee06f6ccb 1029 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
MikamiUitOpen 2:dcaee06f6ccb 1030
MikamiUitOpen 2:dcaee06f6ccb 1031 /* TPI Integration ITM Data Register Definitions (FIFO1) */
MikamiUitOpen 2:dcaee06f6ccb 1032 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
MikamiUitOpen 2:dcaee06f6ccb 1033 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
MikamiUitOpen 2:dcaee06f6ccb 1034
MikamiUitOpen 2:dcaee06f6ccb 1035 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
MikamiUitOpen 2:dcaee06f6ccb 1036 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
MikamiUitOpen 2:dcaee06f6ccb 1037
MikamiUitOpen 2:dcaee06f6ccb 1038 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
MikamiUitOpen 2:dcaee06f6ccb 1039 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
MikamiUitOpen 2:dcaee06f6ccb 1040
MikamiUitOpen 2:dcaee06f6ccb 1041 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
MikamiUitOpen 2:dcaee06f6ccb 1042 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
MikamiUitOpen 2:dcaee06f6ccb 1043
MikamiUitOpen 2:dcaee06f6ccb 1044 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
MikamiUitOpen 2:dcaee06f6ccb 1045 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
MikamiUitOpen 2:dcaee06f6ccb 1046
MikamiUitOpen 2:dcaee06f6ccb 1047 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
MikamiUitOpen 2:dcaee06f6ccb 1048 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
MikamiUitOpen 2:dcaee06f6ccb 1049
MikamiUitOpen 2:dcaee06f6ccb 1050 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
MikamiUitOpen 2:dcaee06f6ccb 1051 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
MikamiUitOpen 2:dcaee06f6ccb 1052
MikamiUitOpen 2:dcaee06f6ccb 1053 /* TPI ITATBCTR0 Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 1054 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
MikamiUitOpen 2:dcaee06f6ccb 1055 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
MikamiUitOpen 2:dcaee06f6ccb 1056
MikamiUitOpen 2:dcaee06f6ccb 1057 /* TPI Integration Mode Control Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 1058 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
MikamiUitOpen 2:dcaee06f6ccb 1059 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
MikamiUitOpen 2:dcaee06f6ccb 1060
MikamiUitOpen 2:dcaee06f6ccb 1061 /* TPI DEVID Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 1062 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
MikamiUitOpen 2:dcaee06f6ccb 1063 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
MikamiUitOpen 2:dcaee06f6ccb 1064
MikamiUitOpen 2:dcaee06f6ccb 1065 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
MikamiUitOpen 2:dcaee06f6ccb 1066 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
MikamiUitOpen 2:dcaee06f6ccb 1067
MikamiUitOpen 2:dcaee06f6ccb 1068 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
MikamiUitOpen 2:dcaee06f6ccb 1069 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
MikamiUitOpen 2:dcaee06f6ccb 1070
MikamiUitOpen 2:dcaee06f6ccb 1071 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
MikamiUitOpen 2:dcaee06f6ccb 1072 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
MikamiUitOpen 2:dcaee06f6ccb 1073
MikamiUitOpen 2:dcaee06f6ccb 1074 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
MikamiUitOpen 2:dcaee06f6ccb 1075 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
MikamiUitOpen 2:dcaee06f6ccb 1076
MikamiUitOpen 2:dcaee06f6ccb 1077 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
MikamiUitOpen 2:dcaee06f6ccb 1078 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
MikamiUitOpen 2:dcaee06f6ccb 1079
MikamiUitOpen 2:dcaee06f6ccb 1080 /* TPI DEVTYPE Register Definitions */
MikamiUitOpen 2:dcaee06f6ccb 1081 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
MikamiUitOpen 2:dcaee06f6ccb 1082 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
MikamiUitOpen 2:dcaee06f6ccb 1083
MikamiUitOpen 2:dcaee06f6ccb 1084 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
MikamiUitOpen 2:dcaee06f6ccb 1085 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
MikamiUitOpen 2:dcaee06f6ccb 1086
MikamiUitOpen 2:dcaee06f6ccb 1087 /*@}*/ /* end of group CMSIS_TPI */
MikamiUitOpen 2:dcaee06f6ccb 1088
MikamiUitOpen 2:dcaee06f6ccb 1089
MikamiUitOpen 2:dcaee06f6ccb 1090 #if (__MPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 1091 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 1092 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
MikamiUitOpen 2:dcaee06f6ccb 1093 \brief Type definitions for the Memory Protection Unit (MPU)
MikamiUitOpen 2:dcaee06f6ccb 1094 @{
MikamiUitOpen 2:dcaee06f6ccb 1095 */
MikamiUitOpen 2:dcaee06f6ccb 1096
MikamiUitOpen 2:dcaee06f6ccb 1097 /** \brief Structure type to access the Memory Protection Unit (MPU).
MikamiUitOpen 2:dcaee06f6ccb 1098 */
MikamiUitOpen 2:dcaee06f6ccb 1099 typedef struct
MikamiUitOpen 2:dcaee06f6ccb 1100 {
MikamiUitOpen 2:dcaee06f6ccb 1101 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
MikamiUitOpen 2:dcaee06f6ccb 1102 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
MikamiUitOpen 2:dcaee06f6ccb 1103 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
MikamiUitOpen 2:dcaee06f6ccb 1104 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
MikamiUitOpen 2:dcaee06f6ccb 1105 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
MikamiUitOpen 2:dcaee06f6ccb 1106 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
MikamiUitOpen 2:dcaee06f6ccb 1107 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
MikamiUitOpen 2:dcaee06f6ccb 1108 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
MikamiUitOpen 2:dcaee06f6ccb 1109 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
MikamiUitOpen 2:dcaee06f6ccb 1110 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
MikamiUitOpen 2:dcaee06f6ccb 1111 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
MikamiUitOpen 2:dcaee06f6ccb 1112 } MPU_Type;
MikamiUitOpen 2:dcaee06f6ccb 1113
MikamiUitOpen 2:dcaee06f6ccb 1114 /* MPU Type Register */
MikamiUitOpen 2:dcaee06f6ccb 1115 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
MikamiUitOpen 2:dcaee06f6ccb 1116 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
MikamiUitOpen 2:dcaee06f6ccb 1117
MikamiUitOpen 2:dcaee06f6ccb 1118 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
MikamiUitOpen 2:dcaee06f6ccb 1119 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
MikamiUitOpen 2:dcaee06f6ccb 1120
MikamiUitOpen 2:dcaee06f6ccb 1121 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
MikamiUitOpen 2:dcaee06f6ccb 1122 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
MikamiUitOpen 2:dcaee06f6ccb 1123
MikamiUitOpen 2:dcaee06f6ccb 1124 /* MPU Control Register */
MikamiUitOpen 2:dcaee06f6ccb 1125 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
MikamiUitOpen 2:dcaee06f6ccb 1126 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 1127
MikamiUitOpen 2:dcaee06f6ccb 1128 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
MikamiUitOpen 2:dcaee06f6ccb 1129 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 1130
MikamiUitOpen 2:dcaee06f6ccb 1131 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
MikamiUitOpen 2:dcaee06f6ccb 1132 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
MikamiUitOpen 2:dcaee06f6ccb 1133
MikamiUitOpen 2:dcaee06f6ccb 1134 /* MPU Region Number Register */
MikamiUitOpen 2:dcaee06f6ccb 1135 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
MikamiUitOpen 2:dcaee06f6ccb 1136 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
MikamiUitOpen 2:dcaee06f6ccb 1137
MikamiUitOpen 2:dcaee06f6ccb 1138 /* MPU Region Base Address Register */
MikamiUitOpen 2:dcaee06f6ccb 1139 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
MikamiUitOpen 2:dcaee06f6ccb 1140 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
MikamiUitOpen 2:dcaee06f6ccb 1141
MikamiUitOpen 2:dcaee06f6ccb 1142 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
MikamiUitOpen 2:dcaee06f6ccb 1143 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
MikamiUitOpen 2:dcaee06f6ccb 1144
MikamiUitOpen 2:dcaee06f6ccb 1145 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
MikamiUitOpen 2:dcaee06f6ccb 1146 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
MikamiUitOpen 2:dcaee06f6ccb 1147
MikamiUitOpen 2:dcaee06f6ccb 1148 /* MPU Region Attribute and Size Register */
MikamiUitOpen 2:dcaee06f6ccb 1149 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
MikamiUitOpen 2:dcaee06f6ccb 1150 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
MikamiUitOpen 2:dcaee06f6ccb 1151
MikamiUitOpen 2:dcaee06f6ccb 1152 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
MikamiUitOpen 2:dcaee06f6ccb 1153 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
MikamiUitOpen 2:dcaee06f6ccb 1154
MikamiUitOpen 2:dcaee06f6ccb 1155 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
MikamiUitOpen 2:dcaee06f6ccb 1156 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
MikamiUitOpen 2:dcaee06f6ccb 1157
MikamiUitOpen 2:dcaee06f6ccb 1158 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
MikamiUitOpen 2:dcaee06f6ccb 1159 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
MikamiUitOpen 2:dcaee06f6ccb 1160
MikamiUitOpen 2:dcaee06f6ccb 1161 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
MikamiUitOpen 2:dcaee06f6ccb 1162 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
MikamiUitOpen 2:dcaee06f6ccb 1163
MikamiUitOpen 2:dcaee06f6ccb 1164 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
MikamiUitOpen 2:dcaee06f6ccb 1165 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
MikamiUitOpen 2:dcaee06f6ccb 1166
MikamiUitOpen 2:dcaee06f6ccb 1167 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
MikamiUitOpen 2:dcaee06f6ccb 1168 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
MikamiUitOpen 2:dcaee06f6ccb 1169
MikamiUitOpen 2:dcaee06f6ccb 1170 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
MikamiUitOpen 2:dcaee06f6ccb 1171 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
MikamiUitOpen 2:dcaee06f6ccb 1172
MikamiUitOpen 2:dcaee06f6ccb 1173 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
MikamiUitOpen 2:dcaee06f6ccb 1174 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
MikamiUitOpen 2:dcaee06f6ccb 1175
MikamiUitOpen 2:dcaee06f6ccb 1176 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
MikamiUitOpen 2:dcaee06f6ccb 1177 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
MikamiUitOpen 2:dcaee06f6ccb 1178
MikamiUitOpen 2:dcaee06f6ccb 1179 /*@} end of group CMSIS_MPU */
MikamiUitOpen 2:dcaee06f6ccb 1180 #endif
MikamiUitOpen 2:dcaee06f6ccb 1181
MikamiUitOpen 2:dcaee06f6ccb 1182
MikamiUitOpen 2:dcaee06f6ccb 1183 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 1184 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
MikamiUitOpen 2:dcaee06f6ccb 1185 \brief Type definitions for the Core Debug Registers
MikamiUitOpen 2:dcaee06f6ccb 1186 @{
MikamiUitOpen 2:dcaee06f6ccb 1187 */
MikamiUitOpen 2:dcaee06f6ccb 1188
MikamiUitOpen 2:dcaee06f6ccb 1189 /** \brief Structure type to access the Core Debug Register (CoreDebug).
MikamiUitOpen 2:dcaee06f6ccb 1190 */
MikamiUitOpen 2:dcaee06f6ccb 1191 typedef struct
MikamiUitOpen 2:dcaee06f6ccb 1192 {
MikamiUitOpen 2:dcaee06f6ccb 1193 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
MikamiUitOpen 2:dcaee06f6ccb 1194 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
MikamiUitOpen 2:dcaee06f6ccb 1195 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
MikamiUitOpen 2:dcaee06f6ccb 1196 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
MikamiUitOpen 2:dcaee06f6ccb 1197 } CoreDebug_Type;
MikamiUitOpen 2:dcaee06f6ccb 1198
MikamiUitOpen 2:dcaee06f6ccb 1199 /* Debug Halting Control and Status Register */
MikamiUitOpen 2:dcaee06f6ccb 1200 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
MikamiUitOpen 2:dcaee06f6ccb 1201 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
MikamiUitOpen 2:dcaee06f6ccb 1202
MikamiUitOpen 2:dcaee06f6ccb 1203 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
MikamiUitOpen 2:dcaee06f6ccb 1204 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
MikamiUitOpen 2:dcaee06f6ccb 1205
MikamiUitOpen 2:dcaee06f6ccb 1206 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
MikamiUitOpen 2:dcaee06f6ccb 1207 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
MikamiUitOpen 2:dcaee06f6ccb 1208
MikamiUitOpen 2:dcaee06f6ccb 1209 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
MikamiUitOpen 2:dcaee06f6ccb 1210 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
MikamiUitOpen 2:dcaee06f6ccb 1211
MikamiUitOpen 2:dcaee06f6ccb 1212 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
MikamiUitOpen 2:dcaee06f6ccb 1213 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
MikamiUitOpen 2:dcaee06f6ccb 1214
MikamiUitOpen 2:dcaee06f6ccb 1215 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
MikamiUitOpen 2:dcaee06f6ccb 1216 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
MikamiUitOpen 2:dcaee06f6ccb 1217
MikamiUitOpen 2:dcaee06f6ccb 1218 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
MikamiUitOpen 2:dcaee06f6ccb 1219 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
MikamiUitOpen 2:dcaee06f6ccb 1220
MikamiUitOpen 2:dcaee06f6ccb 1221 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
MikamiUitOpen 2:dcaee06f6ccb 1222 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
MikamiUitOpen 2:dcaee06f6ccb 1223
MikamiUitOpen 2:dcaee06f6ccb 1224 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
MikamiUitOpen 2:dcaee06f6ccb 1225 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
MikamiUitOpen 2:dcaee06f6ccb 1226
MikamiUitOpen 2:dcaee06f6ccb 1227 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
MikamiUitOpen 2:dcaee06f6ccb 1228 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
MikamiUitOpen 2:dcaee06f6ccb 1229
MikamiUitOpen 2:dcaee06f6ccb 1230 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
MikamiUitOpen 2:dcaee06f6ccb 1231 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
MikamiUitOpen 2:dcaee06f6ccb 1232
MikamiUitOpen 2:dcaee06f6ccb 1233 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
MikamiUitOpen 2:dcaee06f6ccb 1234 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
MikamiUitOpen 2:dcaee06f6ccb 1235
MikamiUitOpen 2:dcaee06f6ccb 1236 /* Debug Core Register Selector Register */
MikamiUitOpen 2:dcaee06f6ccb 1237 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
MikamiUitOpen 2:dcaee06f6ccb 1238 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
MikamiUitOpen 2:dcaee06f6ccb 1239
MikamiUitOpen 2:dcaee06f6ccb 1240 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
MikamiUitOpen 2:dcaee06f6ccb 1241 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
MikamiUitOpen 2:dcaee06f6ccb 1242
MikamiUitOpen 2:dcaee06f6ccb 1243 /* Debug Exception and Monitor Control Register */
MikamiUitOpen 2:dcaee06f6ccb 1244 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
MikamiUitOpen 2:dcaee06f6ccb 1245 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
MikamiUitOpen 2:dcaee06f6ccb 1246
MikamiUitOpen 2:dcaee06f6ccb 1247 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
MikamiUitOpen 2:dcaee06f6ccb 1248 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
MikamiUitOpen 2:dcaee06f6ccb 1249
MikamiUitOpen 2:dcaee06f6ccb 1250 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
MikamiUitOpen 2:dcaee06f6ccb 1251 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
MikamiUitOpen 2:dcaee06f6ccb 1252
MikamiUitOpen 2:dcaee06f6ccb 1253 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
MikamiUitOpen 2:dcaee06f6ccb 1254 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
MikamiUitOpen 2:dcaee06f6ccb 1255
MikamiUitOpen 2:dcaee06f6ccb 1256 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
MikamiUitOpen 2:dcaee06f6ccb 1257 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
MikamiUitOpen 2:dcaee06f6ccb 1258
MikamiUitOpen 2:dcaee06f6ccb 1259 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
MikamiUitOpen 2:dcaee06f6ccb 1260 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
MikamiUitOpen 2:dcaee06f6ccb 1261
MikamiUitOpen 2:dcaee06f6ccb 1262 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
MikamiUitOpen 2:dcaee06f6ccb 1263 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
MikamiUitOpen 2:dcaee06f6ccb 1264
MikamiUitOpen 2:dcaee06f6ccb 1265 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
MikamiUitOpen 2:dcaee06f6ccb 1266 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
MikamiUitOpen 2:dcaee06f6ccb 1267
MikamiUitOpen 2:dcaee06f6ccb 1268 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
MikamiUitOpen 2:dcaee06f6ccb 1269 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
MikamiUitOpen 2:dcaee06f6ccb 1270
MikamiUitOpen 2:dcaee06f6ccb 1271 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
MikamiUitOpen 2:dcaee06f6ccb 1272 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
MikamiUitOpen 2:dcaee06f6ccb 1273
MikamiUitOpen 2:dcaee06f6ccb 1274 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
MikamiUitOpen 2:dcaee06f6ccb 1275 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
MikamiUitOpen 2:dcaee06f6ccb 1276
MikamiUitOpen 2:dcaee06f6ccb 1277 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
MikamiUitOpen 2:dcaee06f6ccb 1278 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
MikamiUitOpen 2:dcaee06f6ccb 1279
MikamiUitOpen 2:dcaee06f6ccb 1280 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
MikamiUitOpen 2:dcaee06f6ccb 1281 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
MikamiUitOpen 2:dcaee06f6ccb 1282
MikamiUitOpen 2:dcaee06f6ccb 1283 /*@} end of group CMSIS_CoreDebug */
MikamiUitOpen 2:dcaee06f6ccb 1284
MikamiUitOpen 2:dcaee06f6ccb 1285
MikamiUitOpen 2:dcaee06f6ccb 1286 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 1287 \defgroup CMSIS_core_base Core Definitions
MikamiUitOpen 2:dcaee06f6ccb 1288 \brief Definitions for base addresses, unions, and structures.
MikamiUitOpen 2:dcaee06f6ccb 1289 @{
MikamiUitOpen 2:dcaee06f6ccb 1290 */
MikamiUitOpen 2:dcaee06f6ccb 1291
MikamiUitOpen 2:dcaee06f6ccb 1292 /* Memory mapping of Cortex-M3 Hardware */
MikamiUitOpen 2:dcaee06f6ccb 1293 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
MikamiUitOpen 2:dcaee06f6ccb 1294 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
MikamiUitOpen 2:dcaee06f6ccb 1295 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
MikamiUitOpen 2:dcaee06f6ccb 1296 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
MikamiUitOpen 2:dcaee06f6ccb 1297 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
MikamiUitOpen 2:dcaee06f6ccb 1298 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
MikamiUitOpen 2:dcaee06f6ccb 1299 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
MikamiUitOpen 2:dcaee06f6ccb 1300 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
MikamiUitOpen 2:dcaee06f6ccb 1301
MikamiUitOpen 2:dcaee06f6ccb 1302 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
MikamiUitOpen 2:dcaee06f6ccb 1303 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
MikamiUitOpen 2:dcaee06f6ccb 1304 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
MikamiUitOpen 2:dcaee06f6ccb 1305 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
MikamiUitOpen 2:dcaee06f6ccb 1306 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
MikamiUitOpen 2:dcaee06f6ccb 1307 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
MikamiUitOpen 2:dcaee06f6ccb 1308 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
MikamiUitOpen 2:dcaee06f6ccb 1309 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
MikamiUitOpen 2:dcaee06f6ccb 1310
MikamiUitOpen 2:dcaee06f6ccb 1311 #if (__MPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 1312 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
MikamiUitOpen 2:dcaee06f6ccb 1313 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
MikamiUitOpen 2:dcaee06f6ccb 1314 #endif
MikamiUitOpen 2:dcaee06f6ccb 1315
MikamiUitOpen 2:dcaee06f6ccb 1316 /*@} */
MikamiUitOpen 2:dcaee06f6ccb 1317
MikamiUitOpen 2:dcaee06f6ccb 1318
MikamiUitOpen 2:dcaee06f6ccb 1319
MikamiUitOpen 2:dcaee06f6ccb 1320 /*******************************************************************************
MikamiUitOpen 2:dcaee06f6ccb 1321 * Hardware Abstraction Layer
MikamiUitOpen 2:dcaee06f6ccb 1322 Core Function Interface contains:
MikamiUitOpen 2:dcaee06f6ccb 1323 - Core NVIC Functions
MikamiUitOpen 2:dcaee06f6ccb 1324 - Core SysTick Functions
MikamiUitOpen 2:dcaee06f6ccb 1325 - Core Debug Functions
MikamiUitOpen 2:dcaee06f6ccb 1326 - Core Register Access Functions
MikamiUitOpen 2:dcaee06f6ccb 1327 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 1328 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
MikamiUitOpen 2:dcaee06f6ccb 1329 */
MikamiUitOpen 2:dcaee06f6ccb 1330
MikamiUitOpen 2:dcaee06f6ccb 1331
MikamiUitOpen 2:dcaee06f6ccb 1332
MikamiUitOpen 2:dcaee06f6ccb 1333 /* ########################## NVIC functions #################################### */
MikamiUitOpen 2:dcaee06f6ccb 1334 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 2:dcaee06f6ccb 1335 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
MikamiUitOpen 2:dcaee06f6ccb 1336 \brief Functions that manage interrupts and exceptions via the NVIC.
MikamiUitOpen 2:dcaee06f6ccb 1337 @{
MikamiUitOpen 2:dcaee06f6ccb 1338 */
MikamiUitOpen 2:dcaee06f6ccb 1339
MikamiUitOpen 2:dcaee06f6ccb 1340 /** \brief Set Priority Grouping
MikamiUitOpen 2:dcaee06f6ccb 1341
MikamiUitOpen 2:dcaee06f6ccb 1342 The function sets the priority grouping field using the required unlock sequence.
MikamiUitOpen 2:dcaee06f6ccb 1343 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
MikamiUitOpen 2:dcaee06f6ccb 1344 Only values from 0..7 are used.
MikamiUitOpen 2:dcaee06f6ccb 1345 In case of a conflict between priority grouping and available
MikamiUitOpen 2:dcaee06f6ccb 1346 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MikamiUitOpen 2:dcaee06f6ccb 1347
MikamiUitOpen 2:dcaee06f6ccb 1348 \param [in] PriorityGroup Priority grouping field.
MikamiUitOpen 2:dcaee06f6ccb 1349 */
MikamiUitOpen 2:dcaee06f6ccb 1350 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
MikamiUitOpen 2:dcaee06f6ccb 1351 {
MikamiUitOpen 2:dcaee06f6ccb 1352 uint32_t reg_value;
MikamiUitOpen 2:dcaee06f6ccb 1353 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MikamiUitOpen 2:dcaee06f6ccb 1354
MikamiUitOpen 2:dcaee06f6ccb 1355 reg_value = SCB->AIRCR; /* read old register configuration */
MikamiUitOpen 2:dcaee06f6ccb 1356 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
MikamiUitOpen 2:dcaee06f6ccb 1357 reg_value = (reg_value |
MikamiUitOpen 2:dcaee06f6ccb 1358 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
MikamiUitOpen 2:dcaee06f6ccb 1359 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
MikamiUitOpen 2:dcaee06f6ccb 1360 SCB->AIRCR = reg_value;
MikamiUitOpen 2:dcaee06f6ccb 1361 }
MikamiUitOpen 2:dcaee06f6ccb 1362
MikamiUitOpen 2:dcaee06f6ccb 1363
MikamiUitOpen 2:dcaee06f6ccb 1364 /** \brief Get Priority Grouping
MikamiUitOpen 2:dcaee06f6ccb 1365
MikamiUitOpen 2:dcaee06f6ccb 1366 The function reads the priority grouping field from the NVIC Interrupt Controller.
MikamiUitOpen 2:dcaee06f6ccb 1367
MikamiUitOpen 2:dcaee06f6ccb 1368 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
MikamiUitOpen 2:dcaee06f6ccb 1369 */
MikamiUitOpen 2:dcaee06f6ccb 1370 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
MikamiUitOpen 2:dcaee06f6ccb 1371 {
MikamiUitOpen 2:dcaee06f6ccb 1372 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
MikamiUitOpen 2:dcaee06f6ccb 1373 }
MikamiUitOpen 2:dcaee06f6ccb 1374
MikamiUitOpen 2:dcaee06f6ccb 1375
MikamiUitOpen 2:dcaee06f6ccb 1376 /** \brief Enable External Interrupt
MikamiUitOpen 2:dcaee06f6ccb 1377
MikamiUitOpen 2:dcaee06f6ccb 1378 The function enables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 2:dcaee06f6ccb 1379
MikamiUitOpen 2:dcaee06f6ccb 1380 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 2:dcaee06f6ccb 1381 */
MikamiUitOpen 2:dcaee06f6ccb 1382 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
MikamiUitOpen 2:dcaee06f6ccb 1383 {
MikamiUitOpen 2:dcaee06f6ccb 1384 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 2:dcaee06f6ccb 1385 }
MikamiUitOpen 2:dcaee06f6ccb 1386
MikamiUitOpen 2:dcaee06f6ccb 1387
MikamiUitOpen 2:dcaee06f6ccb 1388 /** \brief Disable External Interrupt
MikamiUitOpen 2:dcaee06f6ccb 1389
MikamiUitOpen 2:dcaee06f6ccb 1390 The function disables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 2:dcaee06f6ccb 1391
MikamiUitOpen 2:dcaee06f6ccb 1392 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 2:dcaee06f6ccb 1393 */
MikamiUitOpen 2:dcaee06f6ccb 1394 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
MikamiUitOpen 2:dcaee06f6ccb 1395 {
MikamiUitOpen 2:dcaee06f6ccb 1396 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 2:dcaee06f6ccb 1397 }
MikamiUitOpen 2:dcaee06f6ccb 1398
MikamiUitOpen 2:dcaee06f6ccb 1399
MikamiUitOpen 2:dcaee06f6ccb 1400 /** \brief Get Pending Interrupt
MikamiUitOpen 2:dcaee06f6ccb 1401
MikamiUitOpen 2:dcaee06f6ccb 1402 The function reads the pending register in the NVIC and returns the pending bit
MikamiUitOpen 2:dcaee06f6ccb 1403 for the specified interrupt.
MikamiUitOpen 2:dcaee06f6ccb 1404
MikamiUitOpen 2:dcaee06f6ccb 1405 \param [in] IRQn Interrupt number.
MikamiUitOpen 2:dcaee06f6ccb 1406
MikamiUitOpen 2:dcaee06f6ccb 1407 \return 0 Interrupt status is not pending.
MikamiUitOpen 2:dcaee06f6ccb 1408 \return 1 Interrupt status is pending.
MikamiUitOpen 2:dcaee06f6ccb 1409 */
MikamiUitOpen 2:dcaee06f6ccb 1410 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 2:dcaee06f6ccb 1411 {
MikamiUitOpen 2:dcaee06f6ccb 1412 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen 2:dcaee06f6ccb 1413 }
MikamiUitOpen 2:dcaee06f6ccb 1414
MikamiUitOpen 2:dcaee06f6ccb 1415
MikamiUitOpen 2:dcaee06f6ccb 1416 /** \brief Set Pending Interrupt
MikamiUitOpen 2:dcaee06f6ccb 1417
MikamiUitOpen 2:dcaee06f6ccb 1418 The function sets the pending bit of an external interrupt.
MikamiUitOpen 2:dcaee06f6ccb 1419
MikamiUitOpen 2:dcaee06f6ccb 1420 \param [in] IRQn Interrupt number. Value cannot be negative.
MikamiUitOpen 2:dcaee06f6ccb 1421 */
MikamiUitOpen 2:dcaee06f6ccb 1422 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 2:dcaee06f6ccb 1423 {
MikamiUitOpen 2:dcaee06f6ccb 1424 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 2:dcaee06f6ccb 1425 }
MikamiUitOpen 2:dcaee06f6ccb 1426
MikamiUitOpen 2:dcaee06f6ccb 1427
MikamiUitOpen 2:dcaee06f6ccb 1428 /** \brief Clear Pending Interrupt
MikamiUitOpen 2:dcaee06f6ccb 1429
MikamiUitOpen 2:dcaee06f6ccb 1430 The function clears the pending bit of an external interrupt.
MikamiUitOpen 2:dcaee06f6ccb 1431
MikamiUitOpen 2:dcaee06f6ccb 1432 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 2:dcaee06f6ccb 1433 */
MikamiUitOpen 2:dcaee06f6ccb 1434 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 2:dcaee06f6ccb 1435 {
MikamiUitOpen 2:dcaee06f6ccb 1436 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 2:dcaee06f6ccb 1437 }
MikamiUitOpen 2:dcaee06f6ccb 1438
MikamiUitOpen 2:dcaee06f6ccb 1439
MikamiUitOpen 2:dcaee06f6ccb 1440 /** \brief Get Active Interrupt
MikamiUitOpen 2:dcaee06f6ccb 1441
MikamiUitOpen 2:dcaee06f6ccb 1442 The function reads the active register in NVIC and returns the active bit.
MikamiUitOpen 2:dcaee06f6ccb 1443
MikamiUitOpen 2:dcaee06f6ccb 1444 \param [in] IRQn Interrupt number.
MikamiUitOpen 2:dcaee06f6ccb 1445
MikamiUitOpen 2:dcaee06f6ccb 1446 \return 0 Interrupt status is not active.
MikamiUitOpen 2:dcaee06f6ccb 1447 \return 1 Interrupt status is active.
MikamiUitOpen 2:dcaee06f6ccb 1448 */
MikamiUitOpen 2:dcaee06f6ccb 1449 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
MikamiUitOpen 2:dcaee06f6ccb 1450 {
MikamiUitOpen 2:dcaee06f6ccb 1451 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen 2:dcaee06f6ccb 1452 }
MikamiUitOpen 2:dcaee06f6ccb 1453
MikamiUitOpen 2:dcaee06f6ccb 1454
MikamiUitOpen 2:dcaee06f6ccb 1455 /** \brief Set Interrupt Priority
MikamiUitOpen 2:dcaee06f6ccb 1456
MikamiUitOpen 2:dcaee06f6ccb 1457 The function sets the priority of an interrupt.
MikamiUitOpen 2:dcaee06f6ccb 1458
MikamiUitOpen 2:dcaee06f6ccb 1459 \note The priority cannot be set for every core interrupt.
MikamiUitOpen 2:dcaee06f6ccb 1460
MikamiUitOpen 2:dcaee06f6ccb 1461 \param [in] IRQn Interrupt number.
MikamiUitOpen 2:dcaee06f6ccb 1462 \param [in] priority Priority to set.
MikamiUitOpen 2:dcaee06f6ccb 1463 */
MikamiUitOpen 2:dcaee06f6ccb 1464 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
MikamiUitOpen 2:dcaee06f6ccb 1465 {
MikamiUitOpen 2:dcaee06f6ccb 1466 if((int32_t)IRQn < 0) {
MikamiUitOpen 2:dcaee06f6ccb 1467 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MikamiUitOpen 2:dcaee06f6ccb 1468 }
MikamiUitOpen 2:dcaee06f6ccb 1469 else {
MikamiUitOpen 2:dcaee06f6ccb 1470 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MikamiUitOpen 2:dcaee06f6ccb 1471 }
MikamiUitOpen 2:dcaee06f6ccb 1472 }
MikamiUitOpen 2:dcaee06f6ccb 1473
MikamiUitOpen 2:dcaee06f6ccb 1474
MikamiUitOpen 2:dcaee06f6ccb 1475 /** \brief Get Interrupt Priority
MikamiUitOpen 2:dcaee06f6ccb 1476
MikamiUitOpen 2:dcaee06f6ccb 1477 The function reads the priority of an interrupt. The interrupt
MikamiUitOpen 2:dcaee06f6ccb 1478 number can be positive to specify an external (device specific)
MikamiUitOpen 2:dcaee06f6ccb 1479 interrupt, or negative to specify an internal (core) interrupt.
MikamiUitOpen 2:dcaee06f6ccb 1480
MikamiUitOpen 2:dcaee06f6ccb 1481
MikamiUitOpen 2:dcaee06f6ccb 1482 \param [in] IRQn Interrupt number.
MikamiUitOpen 2:dcaee06f6ccb 1483 \return Interrupt Priority. Value is aligned automatically to the implemented
MikamiUitOpen 2:dcaee06f6ccb 1484 priority bits of the microcontroller.
MikamiUitOpen 2:dcaee06f6ccb 1485 */
MikamiUitOpen 2:dcaee06f6ccb 1486 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
MikamiUitOpen 2:dcaee06f6ccb 1487 {
MikamiUitOpen 2:dcaee06f6ccb 1488
MikamiUitOpen 2:dcaee06f6ccb 1489 if((int32_t)IRQn < 0) {
MikamiUitOpen 2:dcaee06f6ccb 1490 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 2:dcaee06f6ccb 1491 }
MikamiUitOpen 2:dcaee06f6ccb 1492 else {
MikamiUitOpen 2:dcaee06f6ccb 1493 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 2:dcaee06f6ccb 1494 }
MikamiUitOpen 2:dcaee06f6ccb 1495 }
MikamiUitOpen 2:dcaee06f6ccb 1496
MikamiUitOpen 2:dcaee06f6ccb 1497
MikamiUitOpen 2:dcaee06f6ccb 1498 /** \brief Encode Priority
MikamiUitOpen 2:dcaee06f6ccb 1499
MikamiUitOpen 2:dcaee06f6ccb 1500 The function encodes the priority for an interrupt with the given priority group,
MikamiUitOpen 2:dcaee06f6ccb 1501 preemptive priority value, and subpriority value.
MikamiUitOpen 2:dcaee06f6ccb 1502 In case of a conflict between priority grouping and available
MikamiUitOpen 2:dcaee06f6ccb 1503 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MikamiUitOpen 2:dcaee06f6ccb 1504
MikamiUitOpen 2:dcaee06f6ccb 1505 \param [in] PriorityGroup Used priority group.
MikamiUitOpen 2:dcaee06f6ccb 1506 \param [in] PreemptPriority Preemptive priority value (starting from 0).
MikamiUitOpen 2:dcaee06f6ccb 1507 \param [in] SubPriority Subpriority value (starting from 0).
MikamiUitOpen 2:dcaee06f6ccb 1508 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
MikamiUitOpen 2:dcaee06f6ccb 1509 */
MikamiUitOpen 2:dcaee06f6ccb 1510 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
MikamiUitOpen 2:dcaee06f6ccb 1511 {
MikamiUitOpen 2:dcaee06f6ccb 1512 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MikamiUitOpen 2:dcaee06f6ccb 1513 uint32_t PreemptPriorityBits;
MikamiUitOpen 2:dcaee06f6ccb 1514 uint32_t SubPriorityBits;
MikamiUitOpen 2:dcaee06f6ccb 1515
MikamiUitOpen 2:dcaee06f6ccb 1516 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MikamiUitOpen 2:dcaee06f6ccb 1517 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MikamiUitOpen 2:dcaee06f6ccb 1518
MikamiUitOpen 2:dcaee06f6ccb 1519 return (
MikamiUitOpen 2:dcaee06f6ccb 1520 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
MikamiUitOpen 2:dcaee06f6ccb 1521 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
MikamiUitOpen 2:dcaee06f6ccb 1522 );
MikamiUitOpen 2:dcaee06f6ccb 1523 }
MikamiUitOpen 2:dcaee06f6ccb 1524
MikamiUitOpen 2:dcaee06f6ccb 1525
MikamiUitOpen 2:dcaee06f6ccb 1526 /** \brief Decode Priority
MikamiUitOpen 2:dcaee06f6ccb 1527
MikamiUitOpen 2:dcaee06f6ccb 1528 The function decodes an interrupt priority value with a given priority group to
MikamiUitOpen 2:dcaee06f6ccb 1529 preemptive priority value and subpriority value.
MikamiUitOpen 2:dcaee06f6ccb 1530 In case of a conflict between priority grouping and available
MikamiUitOpen 2:dcaee06f6ccb 1531 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
MikamiUitOpen 2:dcaee06f6ccb 1532
MikamiUitOpen 2:dcaee06f6ccb 1533 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
MikamiUitOpen 2:dcaee06f6ccb 1534 \param [in] PriorityGroup Used priority group.
MikamiUitOpen 2:dcaee06f6ccb 1535 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
MikamiUitOpen 2:dcaee06f6ccb 1536 \param [out] pSubPriority Subpriority value (starting from 0).
MikamiUitOpen 2:dcaee06f6ccb 1537 */
MikamiUitOpen 2:dcaee06f6ccb 1538 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
MikamiUitOpen 2:dcaee06f6ccb 1539 {
MikamiUitOpen 2:dcaee06f6ccb 1540 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MikamiUitOpen 2:dcaee06f6ccb 1541 uint32_t PreemptPriorityBits;
MikamiUitOpen 2:dcaee06f6ccb 1542 uint32_t SubPriorityBits;
MikamiUitOpen 2:dcaee06f6ccb 1543
MikamiUitOpen 2:dcaee06f6ccb 1544 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MikamiUitOpen 2:dcaee06f6ccb 1545 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MikamiUitOpen 2:dcaee06f6ccb 1546
MikamiUitOpen 2:dcaee06f6ccb 1547 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
MikamiUitOpen 2:dcaee06f6ccb 1548 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
MikamiUitOpen 2:dcaee06f6ccb 1549 }
MikamiUitOpen 2:dcaee06f6ccb 1550
MikamiUitOpen 2:dcaee06f6ccb 1551
MikamiUitOpen 2:dcaee06f6ccb 1552 /** \brief System Reset
MikamiUitOpen 2:dcaee06f6ccb 1553
MikamiUitOpen 2:dcaee06f6ccb 1554 The function initiates a system reset request to reset the MCU.
MikamiUitOpen 2:dcaee06f6ccb 1555 */
MikamiUitOpen 2:dcaee06f6ccb 1556 __STATIC_INLINE void NVIC_SystemReset(void)
MikamiUitOpen 2:dcaee06f6ccb 1557 {
MikamiUitOpen 2:dcaee06f6ccb 1558 __DSB(); /* Ensure all outstanding memory accesses included
MikamiUitOpen 2:dcaee06f6ccb 1559 buffered write are completed before reset */
MikamiUitOpen 2:dcaee06f6ccb 1560 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
MikamiUitOpen 2:dcaee06f6ccb 1561 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
MikamiUitOpen 2:dcaee06f6ccb 1562 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
MikamiUitOpen 2:dcaee06f6ccb 1563 __DSB(); /* Ensure completion of memory access */
MikamiUitOpen 2:dcaee06f6ccb 1564 while(1) { __NOP(); } /* wait until reset */
MikamiUitOpen 2:dcaee06f6ccb 1565 }
MikamiUitOpen 2:dcaee06f6ccb 1566
MikamiUitOpen 2:dcaee06f6ccb 1567 /*@} end of CMSIS_Core_NVICFunctions */
MikamiUitOpen 2:dcaee06f6ccb 1568
MikamiUitOpen 2:dcaee06f6ccb 1569
MikamiUitOpen 2:dcaee06f6ccb 1570
MikamiUitOpen 2:dcaee06f6ccb 1571 /* ################################## SysTick function ############################################ */
MikamiUitOpen 2:dcaee06f6ccb 1572 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 2:dcaee06f6ccb 1573 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
MikamiUitOpen 2:dcaee06f6ccb 1574 \brief Functions that configure the System.
MikamiUitOpen 2:dcaee06f6ccb 1575 @{
MikamiUitOpen 2:dcaee06f6ccb 1576 */
MikamiUitOpen 2:dcaee06f6ccb 1577
MikamiUitOpen 2:dcaee06f6ccb 1578 #if (__Vendor_SysTickConfig == 0)
MikamiUitOpen 2:dcaee06f6ccb 1579
MikamiUitOpen 2:dcaee06f6ccb 1580 /** \brief System Tick Configuration
MikamiUitOpen 2:dcaee06f6ccb 1581
MikamiUitOpen 2:dcaee06f6ccb 1582 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
MikamiUitOpen 2:dcaee06f6ccb 1583 Counter is in free running mode to generate periodic interrupts.
MikamiUitOpen 2:dcaee06f6ccb 1584
MikamiUitOpen 2:dcaee06f6ccb 1585 \param [in] ticks Number of ticks between two interrupts.
MikamiUitOpen 2:dcaee06f6ccb 1586
MikamiUitOpen 2:dcaee06f6ccb 1587 \return 0 Function succeeded.
MikamiUitOpen 2:dcaee06f6ccb 1588 \return 1 Function failed.
MikamiUitOpen 2:dcaee06f6ccb 1589
MikamiUitOpen 2:dcaee06f6ccb 1590 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MikamiUitOpen 2:dcaee06f6ccb 1591 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
MikamiUitOpen 2:dcaee06f6ccb 1592 must contain a vendor-specific implementation of this function.
MikamiUitOpen 2:dcaee06f6ccb 1593
MikamiUitOpen 2:dcaee06f6ccb 1594 */
MikamiUitOpen 2:dcaee06f6ccb 1595 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
MikamiUitOpen 2:dcaee06f6ccb 1596 {
MikamiUitOpen 2:dcaee06f6ccb 1597 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
MikamiUitOpen 2:dcaee06f6ccb 1598
MikamiUitOpen 2:dcaee06f6ccb 1599 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MikamiUitOpen 2:dcaee06f6ccb 1600 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MikamiUitOpen 2:dcaee06f6ccb 1601 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
MikamiUitOpen 2:dcaee06f6ccb 1602 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
MikamiUitOpen 2:dcaee06f6ccb 1603 SysTick_CTRL_TICKINT_Msk |
MikamiUitOpen 2:dcaee06f6ccb 1604 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MikamiUitOpen 2:dcaee06f6ccb 1605 return (0UL); /* Function successful */
MikamiUitOpen 2:dcaee06f6ccb 1606 }
MikamiUitOpen 2:dcaee06f6ccb 1607
MikamiUitOpen 2:dcaee06f6ccb 1608 #endif
MikamiUitOpen 2:dcaee06f6ccb 1609
MikamiUitOpen 2:dcaee06f6ccb 1610 /*@} end of CMSIS_Core_SysTickFunctions */
MikamiUitOpen 2:dcaee06f6ccb 1611
MikamiUitOpen 2:dcaee06f6ccb 1612
MikamiUitOpen 2:dcaee06f6ccb 1613
MikamiUitOpen 2:dcaee06f6ccb 1614 /* ##################################### Debug In/Output function ########################################### */
MikamiUitOpen 2:dcaee06f6ccb 1615 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 2:dcaee06f6ccb 1616 \defgroup CMSIS_core_DebugFunctions ITM Functions
MikamiUitOpen 2:dcaee06f6ccb 1617 \brief Functions that access the ITM debug interface.
MikamiUitOpen 2:dcaee06f6ccb 1618 @{
MikamiUitOpen 2:dcaee06f6ccb 1619 */
MikamiUitOpen 2:dcaee06f6ccb 1620
MikamiUitOpen 2:dcaee06f6ccb 1621 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
MikamiUitOpen 2:dcaee06f6ccb 1622 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
MikamiUitOpen 2:dcaee06f6ccb 1623
MikamiUitOpen 2:dcaee06f6ccb 1624
MikamiUitOpen 2:dcaee06f6ccb 1625 /** \brief ITM Send Character
MikamiUitOpen 2:dcaee06f6ccb 1626
MikamiUitOpen 2:dcaee06f6ccb 1627 The function transmits a character via the ITM channel 0, and
MikamiUitOpen 2:dcaee06f6ccb 1628 \li Just returns when no debugger is connected that has booked the output.
MikamiUitOpen 2:dcaee06f6ccb 1629 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
MikamiUitOpen 2:dcaee06f6ccb 1630
MikamiUitOpen 2:dcaee06f6ccb 1631 \param [in] ch Character to transmit.
MikamiUitOpen 2:dcaee06f6ccb 1632
MikamiUitOpen 2:dcaee06f6ccb 1633 \returns Character to transmit.
MikamiUitOpen 2:dcaee06f6ccb 1634 */
MikamiUitOpen 2:dcaee06f6ccb 1635 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
MikamiUitOpen 2:dcaee06f6ccb 1636 {
MikamiUitOpen 2:dcaee06f6ccb 1637 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
MikamiUitOpen 2:dcaee06f6ccb 1638 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
MikamiUitOpen 2:dcaee06f6ccb 1639 {
MikamiUitOpen 2:dcaee06f6ccb 1640 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
MikamiUitOpen 2:dcaee06f6ccb 1641 ITM->PORT[0].u8 = (uint8_t)ch;
MikamiUitOpen 2:dcaee06f6ccb 1642 }
MikamiUitOpen 2:dcaee06f6ccb 1643 return (ch);
MikamiUitOpen 2:dcaee06f6ccb 1644 }
MikamiUitOpen 2:dcaee06f6ccb 1645
MikamiUitOpen 2:dcaee06f6ccb 1646
MikamiUitOpen 2:dcaee06f6ccb 1647 /** \brief ITM Receive Character
MikamiUitOpen 2:dcaee06f6ccb 1648
MikamiUitOpen 2:dcaee06f6ccb 1649 The function inputs a character via the external variable \ref ITM_RxBuffer.
MikamiUitOpen 2:dcaee06f6ccb 1650
MikamiUitOpen 2:dcaee06f6ccb 1651 \return Received character.
MikamiUitOpen 2:dcaee06f6ccb 1652 \return -1 No character pending.
MikamiUitOpen 2:dcaee06f6ccb 1653 */
MikamiUitOpen 2:dcaee06f6ccb 1654 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
MikamiUitOpen 2:dcaee06f6ccb 1655 int32_t ch = -1; /* no character available */
MikamiUitOpen 2:dcaee06f6ccb 1656
MikamiUitOpen 2:dcaee06f6ccb 1657 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
MikamiUitOpen 2:dcaee06f6ccb 1658 ch = ITM_RxBuffer;
MikamiUitOpen 2:dcaee06f6ccb 1659 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
MikamiUitOpen 2:dcaee06f6ccb 1660 }
MikamiUitOpen 2:dcaee06f6ccb 1661
MikamiUitOpen 2:dcaee06f6ccb 1662 return (ch);
MikamiUitOpen 2:dcaee06f6ccb 1663 }
MikamiUitOpen 2:dcaee06f6ccb 1664
MikamiUitOpen 2:dcaee06f6ccb 1665
MikamiUitOpen 2:dcaee06f6ccb 1666 /** \brief ITM Check Character
MikamiUitOpen 2:dcaee06f6ccb 1667
MikamiUitOpen 2:dcaee06f6ccb 1668 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
MikamiUitOpen 2:dcaee06f6ccb 1669
MikamiUitOpen 2:dcaee06f6ccb 1670 \return 0 No character available.
MikamiUitOpen 2:dcaee06f6ccb 1671 \return 1 Character available.
MikamiUitOpen 2:dcaee06f6ccb 1672 */
MikamiUitOpen 2:dcaee06f6ccb 1673 __STATIC_INLINE int32_t ITM_CheckChar (void) {
MikamiUitOpen 2:dcaee06f6ccb 1674
MikamiUitOpen 2:dcaee06f6ccb 1675 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
MikamiUitOpen 2:dcaee06f6ccb 1676 return (0); /* no character available */
MikamiUitOpen 2:dcaee06f6ccb 1677 } else {
MikamiUitOpen 2:dcaee06f6ccb 1678 return (1); /* character available */
MikamiUitOpen 2:dcaee06f6ccb 1679 }
MikamiUitOpen 2:dcaee06f6ccb 1680 }
MikamiUitOpen 2:dcaee06f6ccb 1681
MikamiUitOpen 2:dcaee06f6ccb 1682 /*@} end of CMSIS_core_DebugFunctions */
MikamiUitOpen 2:dcaee06f6ccb 1683
MikamiUitOpen 2:dcaee06f6ccb 1684
MikamiUitOpen 2:dcaee06f6ccb 1685
MikamiUitOpen 2:dcaee06f6ccb 1686
MikamiUitOpen 2:dcaee06f6ccb 1687 #ifdef __cplusplus
MikamiUitOpen 2:dcaee06f6ccb 1688 }
MikamiUitOpen 2:dcaee06f6ccb 1689 #endif
MikamiUitOpen 2:dcaee06f6ccb 1690
MikamiUitOpen 2:dcaee06f6ccb 1691 #endif /* __CORE_CM3_H_DEPENDANT */
MikamiUitOpen 2:dcaee06f6ccb 1692
MikamiUitOpen 2:dcaee06f6ccb 1693 #endif /* __CMSIS_GENERIC */