不韋 呂 / F746_SD_VarableFilter

SD card player with variable cotoff frequency lowpass and highpass IIR filter. SD カードの *.wav ファイルのオーディオ信号を，遮断周波数可変 IIR 低域通過および高域通過フィルタを通して，ボードに搭載されているCODEC で出力する．このプログラムについては，CQ出版社インターフェース誌 2018年8月号で解説している．

Dependencies:   F746_GUI F746_SAI_IO FrequencyResponseDrawer SD_PlayerSkeleton

mbed_src_STM32F7/targets/cmsis/core_caFunc.h@11:399670d24ed9, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 01:44:22 2017 +0000
Revision:
11:399670d24ed9
Parent:
2:dcaee06f6ccb 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 2:dcaee06f6ccb 1 /**************************************************************************//**
MikamiUitOpen 2:dcaee06f6ccb 2 * @file core_caFunc.h
MikamiUitOpen 2:dcaee06f6ccb 3 * @brief CMSIS Cortex-A Core Function Access Header File
MikamiUitOpen 2:dcaee06f6ccb 4 * @version V3.10
MikamiUitOpen 2:dcaee06f6ccb 5 * @date 30 Oct 2013
MikamiUitOpen 2:dcaee06f6ccb 6 *
MikamiUitOpen 2:dcaee06f6ccb 7 * @note
MikamiUitOpen 2:dcaee06f6ccb 8 *
MikamiUitOpen 2:dcaee06f6ccb 9 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
MikamiUitOpen 2:dcaee06f6ccb 11
MikamiUitOpen 2:dcaee06f6ccb 12 All rights reserved.
MikamiUitOpen 2:dcaee06f6ccb 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 2:dcaee06f6ccb 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 2:dcaee06f6ccb 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 2:dcaee06f6ccb 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 2:dcaee06f6ccb 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 2:dcaee06f6ccb 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 2:dcaee06f6ccb 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 2:dcaee06f6ccb 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 2:dcaee06f6ccb 21 to endorse or promote products derived from this software without
MikamiUitOpen 2:dcaee06f6ccb 22 specific prior written permission.
MikamiUitOpen 2:dcaee06f6ccb 23 *
MikamiUitOpen 2:dcaee06f6ccb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 2:dcaee06f6ccb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 2:dcaee06f6ccb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 2:dcaee06f6ccb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 2:dcaee06f6ccb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 2:dcaee06f6ccb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 2:dcaee06f6ccb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 2:dcaee06f6ccb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 2:dcaee06f6ccb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 2:dcaee06f6ccb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 2:dcaee06f6ccb 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 2:dcaee06f6ccb 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 2:dcaee06f6ccb 36
MikamiUitOpen 2:dcaee06f6ccb 37
MikamiUitOpen 2:dcaee06f6ccb 38 #ifndef __CORE_CAFUNC_H__
MikamiUitOpen 2:dcaee06f6ccb 39 #define __CORE_CAFUNC_H__
MikamiUitOpen 2:dcaee06f6ccb 40
MikamiUitOpen 2:dcaee06f6ccb 41
MikamiUitOpen 2:dcaee06f6ccb 42 /* ########################### Core Function Access ########################### */
MikamiUitOpen 2:dcaee06f6ccb 43 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 2:dcaee06f6ccb 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
MikamiUitOpen 2:dcaee06f6ccb 45 @{
MikamiUitOpen 2:dcaee06f6ccb 46 */
MikamiUitOpen 2:dcaee06f6ccb 47
MikamiUitOpen 2:dcaee06f6ccb 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 2:dcaee06f6ccb 49 /* ARM armcc specific functions */
MikamiUitOpen 2:dcaee06f6ccb 50
MikamiUitOpen 2:dcaee06f6ccb 51 #if (__ARMCC_VERSION < 400677)
MikamiUitOpen 2:dcaee06f6ccb 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MikamiUitOpen 2:dcaee06f6ccb 53 #endif
MikamiUitOpen 2:dcaee06f6ccb 54
MikamiUitOpen 2:dcaee06f6ccb 55 #define MODE_USR 0x10
MikamiUitOpen 2:dcaee06f6ccb 56 #define MODE_FIQ 0x11
MikamiUitOpen 2:dcaee06f6ccb 57 #define MODE_IRQ 0x12
MikamiUitOpen 2:dcaee06f6ccb 58 #define MODE_SVC 0x13
MikamiUitOpen 2:dcaee06f6ccb 59 #define MODE_MON 0x16
MikamiUitOpen 2:dcaee06f6ccb 60 #define MODE_ABT 0x17
MikamiUitOpen 2:dcaee06f6ccb 61 #define MODE_HYP 0x1A
MikamiUitOpen 2:dcaee06f6ccb 62 #define MODE_UND 0x1B
MikamiUitOpen 2:dcaee06f6ccb 63 #define MODE_SYS 0x1F
MikamiUitOpen 2:dcaee06f6ccb 64
MikamiUitOpen 2:dcaee06f6ccb 65 /** \brief Get APSR Register
MikamiUitOpen 2:dcaee06f6ccb 66
MikamiUitOpen 2:dcaee06f6ccb 67 This function returns the content of the APSR Register.
MikamiUitOpen 2:dcaee06f6ccb 68
MikamiUitOpen 2:dcaee06f6ccb 69 \return APSR Register value
MikamiUitOpen 2:dcaee06f6ccb 70 */
MikamiUitOpen 2:dcaee06f6ccb 71 __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 2:dcaee06f6ccb 72 {
MikamiUitOpen 2:dcaee06f6ccb 73 register uint32_t __regAPSR __ASM("apsr");
MikamiUitOpen 2:dcaee06f6ccb 74 return(__regAPSR);
MikamiUitOpen 2:dcaee06f6ccb 75 }
MikamiUitOpen 2:dcaee06f6ccb 76
MikamiUitOpen 2:dcaee06f6ccb 77
MikamiUitOpen 2:dcaee06f6ccb 78 /** \brief Get CPSR Register
MikamiUitOpen 2:dcaee06f6ccb 79
MikamiUitOpen 2:dcaee06f6ccb 80 This function returns the content of the CPSR Register.
MikamiUitOpen 2:dcaee06f6ccb 81
MikamiUitOpen 2:dcaee06f6ccb 82 \return CPSR Register value
MikamiUitOpen 2:dcaee06f6ccb 83 */
MikamiUitOpen 2:dcaee06f6ccb 84 __STATIC_INLINE uint32_t __get_CPSR(void)
MikamiUitOpen 2:dcaee06f6ccb 85 {
MikamiUitOpen 2:dcaee06f6ccb 86 register uint32_t __regCPSR __ASM("cpsr");
MikamiUitOpen 2:dcaee06f6ccb 87 return(__regCPSR);
MikamiUitOpen 2:dcaee06f6ccb 88 }
MikamiUitOpen 2:dcaee06f6ccb 89
MikamiUitOpen 2:dcaee06f6ccb 90 /** \brief Set Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 91
MikamiUitOpen 2:dcaee06f6ccb 92 This function assigns the given value to the current stack pointer.
MikamiUitOpen 2:dcaee06f6ccb 93
MikamiUitOpen 2:dcaee06f6ccb 94 \param [in] topOfStack Stack Pointer value to set
MikamiUitOpen 2:dcaee06f6ccb 95 */
MikamiUitOpen 2:dcaee06f6ccb 96 register uint32_t __regSP __ASM("sp");
MikamiUitOpen 2:dcaee06f6ccb 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
MikamiUitOpen 2:dcaee06f6ccb 98 {
MikamiUitOpen 2:dcaee06f6ccb 99 __regSP = topOfStack;
MikamiUitOpen 2:dcaee06f6ccb 100 }
MikamiUitOpen 2:dcaee06f6ccb 101
MikamiUitOpen 2:dcaee06f6ccb 102
MikamiUitOpen 2:dcaee06f6ccb 103 /** \brief Get link register
MikamiUitOpen 2:dcaee06f6ccb 104
MikamiUitOpen 2:dcaee06f6ccb 105 This function returns the value of the link register
MikamiUitOpen 2:dcaee06f6ccb 106
MikamiUitOpen 2:dcaee06f6ccb 107 \return Value of link register
MikamiUitOpen 2:dcaee06f6ccb 108 */
MikamiUitOpen 2:dcaee06f6ccb 109 register uint32_t __reglr __ASM("lr");
MikamiUitOpen 2:dcaee06f6ccb 110 __STATIC_INLINE uint32_t __get_LR(void)
MikamiUitOpen 2:dcaee06f6ccb 111 {
MikamiUitOpen 2:dcaee06f6ccb 112 return(__reglr);
MikamiUitOpen 2:dcaee06f6ccb 113 }
MikamiUitOpen 2:dcaee06f6ccb 114
MikamiUitOpen 2:dcaee06f6ccb 115 /** \brief Set link register
MikamiUitOpen 2:dcaee06f6ccb 116
MikamiUitOpen 2:dcaee06f6ccb 117 This function sets the value of the link register
MikamiUitOpen 2:dcaee06f6ccb 118
MikamiUitOpen 2:dcaee06f6ccb 119 \param [in] lr LR value to set
MikamiUitOpen 2:dcaee06f6ccb 120 */
MikamiUitOpen 2:dcaee06f6ccb 121 __STATIC_INLINE void __set_LR(uint32_t lr)
MikamiUitOpen 2:dcaee06f6ccb 122 {
MikamiUitOpen 2:dcaee06f6ccb 123 __reglr = lr;
MikamiUitOpen 2:dcaee06f6ccb 124 }
MikamiUitOpen 2:dcaee06f6ccb 125
MikamiUitOpen 2:dcaee06f6ccb 126 /** \brief Set Process Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 127
MikamiUitOpen 2:dcaee06f6ccb 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
MikamiUitOpen 2:dcaee06f6ccb 129
MikamiUitOpen 2:dcaee06f6ccb 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
MikamiUitOpen 2:dcaee06f6ccb 131 */
MikamiUitOpen 2:dcaee06f6ccb 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 2:dcaee06f6ccb 133 {
MikamiUitOpen 2:dcaee06f6ccb 134 ARM
MikamiUitOpen 2:dcaee06f6ccb 135 PRESERVE8
MikamiUitOpen 2:dcaee06f6ccb 136
MikamiUitOpen 2:dcaee06f6ccb 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
MikamiUitOpen 2:dcaee06f6ccb 138 MRS R1, CPSR
MikamiUitOpen 2:dcaee06f6ccb 139 CPS #MODE_SYS ;no effect in USR mode
MikamiUitOpen 2:dcaee06f6ccb 140 MOV SP, R0
MikamiUitOpen 2:dcaee06f6ccb 141 MSR CPSR_c, R1 ;no effect in USR mode
MikamiUitOpen 2:dcaee06f6ccb 142 ISB
MikamiUitOpen 2:dcaee06f6ccb 143 BX LR
MikamiUitOpen 2:dcaee06f6ccb 144
MikamiUitOpen 2:dcaee06f6ccb 145 }
MikamiUitOpen 2:dcaee06f6ccb 146
MikamiUitOpen 2:dcaee06f6ccb 147 /** \brief Set User Mode
MikamiUitOpen 2:dcaee06f6ccb 148
MikamiUitOpen 2:dcaee06f6ccb 149 This function changes the processor state to User Mode
MikamiUitOpen 2:dcaee06f6ccb 150 */
MikamiUitOpen 2:dcaee06f6ccb 151 __STATIC_ASM void __set_CPS_USR(void)
MikamiUitOpen 2:dcaee06f6ccb 152 {
MikamiUitOpen 2:dcaee06f6ccb 153 ARM
MikamiUitOpen 2:dcaee06f6ccb 154
MikamiUitOpen 2:dcaee06f6ccb 155 CPS #MODE_USR
MikamiUitOpen 2:dcaee06f6ccb 156 BX LR
MikamiUitOpen 2:dcaee06f6ccb 157 }
MikamiUitOpen 2:dcaee06f6ccb 158
MikamiUitOpen 2:dcaee06f6ccb 159
MikamiUitOpen 2:dcaee06f6ccb 160 /** \brief Enable FIQ
MikamiUitOpen 2:dcaee06f6ccb 161
MikamiUitOpen 2:dcaee06f6ccb 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 163 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 164 */
MikamiUitOpen 2:dcaee06f6ccb 165 #define __enable_fault_irq __enable_fiq
MikamiUitOpen 2:dcaee06f6ccb 166
MikamiUitOpen 2:dcaee06f6ccb 167
MikamiUitOpen 2:dcaee06f6ccb 168 /** \brief Disable FIQ
MikamiUitOpen 2:dcaee06f6ccb 169
MikamiUitOpen 2:dcaee06f6ccb 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 171 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 172 */
MikamiUitOpen 2:dcaee06f6ccb 173 #define __disable_fault_irq __disable_fiq
MikamiUitOpen 2:dcaee06f6ccb 174
MikamiUitOpen 2:dcaee06f6ccb 175
MikamiUitOpen 2:dcaee06f6ccb 176 /** \brief Get FPSCR
MikamiUitOpen 2:dcaee06f6ccb 177
MikamiUitOpen 2:dcaee06f6ccb 178 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 2:dcaee06f6ccb 179
MikamiUitOpen 2:dcaee06f6ccb 180 \return Floating Point Status/Control register value
MikamiUitOpen 2:dcaee06f6ccb 181 */
MikamiUitOpen 2:dcaee06f6ccb 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 2:dcaee06f6ccb 183 {
MikamiUitOpen 2:dcaee06f6ccb 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 2:dcaee06f6ccb 185 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 2:dcaee06f6ccb 186 return(__regfpscr);
MikamiUitOpen 2:dcaee06f6ccb 187 #else
MikamiUitOpen 2:dcaee06f6ccb 188 return(0);
MikamiUitOpen 2:dcaee06f6ccb 189 #endif
MikamiUitOpen 2:dcaee06f6ccb 190 }
MikamiUitOpen 2:dcaee06f6ccb 191
MikamiUitOpen 2:dcaee06f6ccb 192
MikamiUitOpen 2:dcaee06f6ccb 193 /** \brief Set FPSCR
MikamiUitOpen 2:dcaee06f6ccb 194
MikamiUitOpen 2:dcaee06f6ccb 195 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 2:dcaee06f6ccb 196
MikamiUitOpen 2:dcaee06f6ccb 197 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 2:dcaee06f6ccb 198 */
MikamiUitOpen 2:dcaee06f6ccb 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 2:dcaee06f6ccb 200 {
MikamiUitOpen 2:dcaee06f6ccb 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 2:dcaee06f6ccb 202 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 2:dcaee06f6ccb 203 __regfpscr = (fpscr);
MikamiUitOpen 2:dcaee06f6ccb 204 #endif
MikamiUitOpen 2:dcaee06f6ccb 205 }
MikamiUitOpen 2:dcaee06f6ccb 206
MikamiUitOpen 2:dcaee06f6ccb 207 /** \brief Get FPEXC
MikamiUitOpen 2:dcaee06f6ccb 208
MikamiUitOpen 2:dcaee06f6ccb 209 This function returns the current value of the Floating Point Exception Control register.
MikamiUitOpen 2:dcaee06f6ccb 210
MikamiUitOpen 2:dcaee06f6ccb 211 \return Floating Point Exception Control register value
MikamiUitOpen 2:dcaee06f6ccb 212 */
MikamiUitOpen 2:dcaee06f6ccb 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
MikamiUitOpen 2:dcaee06f6ccb 214 {
MikamiUitOpen 2:dcaee06f6ccb 215 #if (__FPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 216 register uint32_t __regfpexc __ASM("fpexc");
MikamiUitOpen 2:dcaee06f6ccb 217 return(__regfpexc);
MikamiUitOpen 2:dcaee06f6ccb 218 #else
MikamiUitOpen 2:dcaee06f6ccb 219 return(0);
MikamiUitOpen 2:dcaee06f6ccb 220 #endif
MikamiUitOpen 2:dcaee06f6ccb 221 }
MikamiUitOpen 2:dcaee06f6ccb 222
MikamiUitOpen 2:dcaee06f6ccb 223
MikamiUitOpen 2:dcaee06f6ccb 224 /** \brief Set FPEXC
MikamiUitOpen 2:dcaee06f6ccb 225
MikamiUitOpen 2:dcaee06f6ccb 226 This function assigns the given value to the Floating Point Exception Control register.
MikamiUitOpen 2:dcaee06f6ccb 227
MikamiUitOpen 2:dcaee06f6ccb 228 \param [in] fpscr Floating Point Exception Control value to set
MikamiUitOpen 2:dcaee06f6ccb 229 */
MikamiUitOpen 2:dcaee06f6ccb 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
MikamiUitOpen 2:dcaee06f6ccb 231 {
MikamiUitOpen 2:dcaee06f6ccb 232 #if (__FPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 233 register uint32_t __regfpexc __ASM("fpexc");
MikamiUitOpen 2:dcaee06f6ccb 234 __regfpexc = (fpexc);
MikamiUitOpen 2:dcaee06f6ccb 235 #endif
MikamiUitOpen 2:dcaee06f6ccb 236 }
MikamiUitOpen 2:dcaee06f6ccb 237
MikamiUitOpen 2:dcaee06f6ccb 238 /** \brief Get CPACR
MikamiUitOpen 2:dcaee06f6ccb 239
MikamiUitOpen 2:dcaee06f6ccb 240 This function returns the current value of the Coprocessor Access Control register.
MikamiUitOpen 2:dcaee06f6ccb 241
MikamiUitOpen 2:dcaee06f6ccb 242 \return Coprocessor Access Control register value
MikamiUitOpen 2:dcaee06f6ccb 243 */
MikamiUitOpen 2:dcaee06f6ccb 244 __STATIC_INLINE uint32_t __get_CPACR(void)
MikamiUitOpen 2:dcaee06f6ccb 245 {
MikamiUitOpen 2:dcaee06f6ccb 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MikamiUitOpen 2:dcaee06f6ccb 247 return __regCPACR;
MikamiUitOpen 2:dcaee06f6ccb 248 }
MikamiUitOpen 2:dcaee06f6ccb 249
MikamiUitOpen 2:dcaee06f6ccb 250 /** \brief Set CPACR
MikamiUitOpen 2:dcaee06f6ccb 251
MikamiUitOpen 2:dcaee06f6ccb 252 This function assigns the given value to the Coprocessor Access Control register.
MikamiUitOpen 2:dcaee06f6ccb 253
MikamiUitOpen 2:dcaee06f6ccb 254 \param [in] cpacr Coprocessor Acccess Control value to set
MikamiUitOpen 2:dcaee06f6ccb 255 */
MikamiUitOpen 2:dcaee06f6ccb 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
MikamiUitOpen 2:dcaee06f6ccb 257 {
MikamiUitOpen 2:dcaee06f6ccb 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MikamiUitOpen 2:dcaee06f6ccb 259 __regCPACR = cpacr;
MikamiUitOpen 2:dcaee06f6ccb 260 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 261 }
MikamiUitOpen 2:dcaee06f6ccb 262
MikamiUitOpen 2:dcaee06f6ccb 263 /** \brief Get CBAR
MikamiUitOpen 2:dcaee06f6ccb 264
MikamiUitOpen 2:dcaee06f6ccb 265 This function returns the value of the Configuration Base Address register.
MikamiUitOpen 2:dcaee06f6ccb 266
MikamiUitOpen 2:dcaee06f6ccb 267 \return Configuration Base Address register value
MikamiUitOpen 2:dcaee06f6ccb 268 */
MikamiUitOpen 2:dcaee06f6ccb 269 __STATIC_INLINE uint32_t __get_CBAR() {
MikamiUitOpen 2:dcaee06f6ccb 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 271 return(__regCBAR);
MikamiUitOpen 2:dcaee06f6ccb 272 }
MikamiUitOpen 2:dcaee06f6ccb 273
MikamiUitOpen 2:dcaee06f6ccb 274 /** \brief Get TTBR0
MikamiUitOpen 2:dcaee06f6ccb 275
MikamiUitOpen 2:dcaee06f6ccb 276 This function returns the value of the Translation Table Base Register 0.
MikamiUitOpen 2:dcaee06f6ccb 277
MikamiUitOpen 2:dcaee06f6ccb 278 \return Translation Table Base Register 0 value
MikamiUitOpen 2:dcaee06f6ccb 279 */
MikamiUitOpen 2:dcaee06f6ccb 280 __STATIC_INLINE uint32_t __get_TTBR0() {
MikamiUitOpen 2:dcaee06f6ccb 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 282 return(__regTTBR0);
MikamiUitOpen 2:dcaee06f6ccb 283 }
MikamiUitOpen 2:dcaee06f6ccb 284
MikamiUitOpen 2:dcaee06f6ccb 285 /** \brief Set TTBR0
MikamiUitOpen 2:dcaee06f6ccb 286
MikamiUitOpen 2:dcaee06f6ccb 287 This function assigns the given value to the Translation Table Base Register 0.
MikamiUitOpen 2:dcaee06f6ccb 288
MikamiUitOpen 2:dcaee06f6ccb 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
MikamiUitOpen 2:dcaee06f6ccb 290 */
MikamiUitOpen 2:dcaee06f6ccb 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
MikamiUitOpen 2:dcaee06f6ccb 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 293 __regTTBR0 = ttbr0;
MikamiUitOpen 2:dcaee06f6ccb 294 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 295 }
MikamiUitOpen 2:dcaee06f6ccb 296
MikamiUitOpen 2:dcaee06f6ccb 297 /** \brief Get DACR
MikamiUitOpen 2:dcaee06f6ccb 298
MikamiUitOpen 2:dcaee06f6ccb 299 This function returns the value of the Domain Access Control Register.
MikamiUitOpen 2:dcaee06f6ccb 300
MikamiUitOpen 2:dcaee06f6ccb 301 \return Domain Access Control Register value
MikamiUitOpen 2:dcaee06f6ccb 302 */
MikamiUitOpen 2:dcaee06f6ccb 303 __STATIC_INLINE uint32_t __get_DACR() {
MikamiUitOpen 2:dcaee06f6ccb 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 305 return(__regDACR);
MikamiUitOpen 2:dcaee06f6ccb 306 }
MikamiUitOpen 2:dcaee06f6ccb 307
MikamiUitOpen 2:dcaee06f6ccb 308 /** \brief Set DACR
MikamiUitOpen 2:dcaee06f6ccb 309
MikamiUitOpen 2:dcaee06f6ccb 310 This function assigns the given value to the Domain Access Control Register.
MikamiUitOpen 2:dcaee06f6ccb 311
MikamiUitOpen 2:dcaee06f6ccb 312 \param [in] dacr Domain Access Control Register value to set
MikamiUitOpen 2:dcaee06f6ccb 313 */
MikamiUitOpen 2:dcaee06f6ccb 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
MikamiUitOpen 2:dcaee06f6ccb 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 316 __regDACR = dacr;
MikamiUitOpen 2:dcaee06f6ccb 317 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 318 }
MikamiUitOpen 2:dcaee06f6ccb 319
MikamiUitOpen 2:dcaee06f6ccb 320 /******************************** Cache and BTAC enable ****************************************************/
MikamiUitOpen 2:dcaee06f6ccb 321
MikamiUitOpen 2:dcaee06f6ccb 322 /** \brief Set SCTLR
MikamiUitOpen 2:dcaee06f6ccb 323
MikamiUitOpen 2:dcaee06f6ccb 324 This function assigns the given value to the System Control Register.
MikamiUitOpen 2:dcaee06f6ccb 325
MikamiUitOpen 2:dcaee06f6ccb 326 \param [in] sctlr System Control Register value to set
MikamiUitOpen 2:dcaee06f6ccb 327 */
MikamiUitOpen 2:dcaee06f6ccb 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
MikamiUitOpen 2:dcaee06f6ccb 329 {
MikamiUitOpen 2:dcaee06f6ccb 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 331 __regSCTLR = sctlr;
MikamiUitOpen 2:dcaee06f6ccb 332 }
MikamiUitOpen 2:dcaee06f6ccb 333
MikamiUitOpen 2:dcaee06f6ccb 334 /** \brief Get SCTLR
MikamiUitOpen 2:dcaee06f6ccb 335
MikamiUitOpen 2:dcaee06f6ccb 336 This function returns the value of the System Control Register.
MikamiUitOpen 2:dcaee06f6ccb 337
MikamiUitOpen 2:dcaee06f6ccb 338 \return System Control Register value
MikamiUitOpen 2:dcaee06f6ccb 339 */
MikamiUitOpen 2:dcaee06f6ccb 340 __STATIC_INLINE uint32_t __get_SCTLR() {
MikamiUitOpen 2:dcaee06f6ccb 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 342 return(__regSCTLR);
MikamiUitOpen 2:dcaee06f6ccb 343 }
MikamiUitOpen 2:dcaee06f6ccb 344
MikamiUitOpen 2:dcaee06f6ccb 345 /** \brief Enable Caches
MikamiUitOpen 2:dcaee06f6ccb 346
MikamiUitOpen 2:dcaee06f6ccb 347 Enable Caches
MikamiUitOpen 2:dcaee06f6ccb 348 */
MikamiUitOpen 2:dcaee06f6ccb 349 __STATIC_INLINE void __enable_caches(void) {
MikamiUitOpen 2:dcaee06f6ccb 350 // Set I bit 12 to enable I Cache
MikamiUitOpen 2:dcaee06f6ccb 351 // Set C bit 2 to enable D Cache
MikamiUitOpen 2:dcaee06f6ccb 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
MikamiUitOpen 2:dcaee06f6ccb 353 }
MikamiUitOpen 2:dcaee06f6ccb 354
MikamiUitOpen 2:dcaee06f6ccb 355 /** \brief Disable Caches
MikamiUitOpen 2:dcaee06f6ccb 356
MikamiUitOpen 2:dcaee06f6ccb 357 Disable Caches
MikamiUitOpen 2:dcaee06f6ccb 358 */
MikamiUitOpen 2:dcaee06f6ccb 359 __STATIC_INLINE void __disable_caches(void) {
MikamiUitOpen 2:dcaee06f6ccb 360 // Clear I bit 12 to disable I Cache
MikamiUitOpen 2:dcaee06f6ccb 361 // Clear C bit 2 to disable D Cache
MikamiUitOpen 2:dcaee06f6ccb 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
MikamiUitOpen 2:dcaee06f6ccb 363 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 364 }
MikamiUitOpen 2:dcaee06f6ccb 365
MikamiUitOpen 2:dcaee06f6ccb 366 /** \brief Enable BTAC
MikamiUitOpen 2:dcaee06f6ccb 367
MikamiUitOpen 2:dcaee06f6ccb 368 Enable BTAC
MikamiUitOpen 2:dcaee06f6ccb 369 */
MikamiUitOpen 2:dcaee06f6ccb 370 __STATIC_INLINE void __enable_btac(void) {
MikamiUitOpen 2:dcaee06f6ccb 371 // Set Z bit 11 to enable branch prediction
MikamiUitOpen 2:dcaee06f6ccb 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
MikamiUitOpen 2:dcaee06f6ccb 373 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 374 }
MikamiUitOpen 2:dcaee06f6ccb 375
MikamiUitOpen 2:dcaee06f6ccb 376 /** \brief Disable BTAC
MikamiUitOpen 2:dcaee06f6ccb 377
MikamiUitOpen 2:dcaee06f6ccb 378 Disable BTAC
MikamiUitOpen 2:dcaee06f6ccb 379 */
MikamiUitOpen 2:dcaee06f6ccb 380 __STATIC_INLINE void __disable_btac(void) {
MikamiUitOpen 2:dcaee06f6ccb 381 // Clear Z bit 11 to disable branch prediction
MikamiUitOpen 2:dcaee06f6ccb 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
MikamiUitOpen 2:dcaee06f6ccb 383 }
MikamiUitOpen 2:dcaee06f6ccb 384
MikamiUitOpen 2:dcaee06f6ccb 385
MikamiUitOpen 2:dcaee06f6ccb 386 /** \brief Enable MMU
MikamiUitOpen 2:dcaee06f6ccb 387
MikamiUitOpen 2:dcaee06f6ccb 388 Enable MMU
MikamiUitOpen 2:dcaee06f6ccb 389 */
MikamiUitOpen 2:dcaee06f6ccb 390 __STATIC_INLINE void __enable_mmu(void) {
MikamiUitOpen 2:dcaee06f6ccb 391 // Set M bit 0 to enable the MMU
MikamiUitOpen 2:dcaee06f6ccb 392 // Set AFE bit to enable simplified access permissions model
MikamiUitOpen 2:dcaee06f6ccb 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
MikamiUitOpen 2:dcaee06f6ccb 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
MikamiUitOpen 2:dcaee06f6ccb 395 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 396 }
MikamiUitOpen 2:dcaee06f6ccb 397
MikamiUitOpen 2:dcaee06f6ccb 398 /** \brief Disable MMU
MikamiUitOpen 2:dcaee06f6ccb 399
MikamiUitOpen 2:dcaee06f6ccb 400 Disable MMU
MikamiUitOpen 2:dcaee06f6ccb 401 */
MikamiUitOpen 2:dcaee06f6ccb 402 __STATIC_INLINE void __disable_mmu(void) {
MikamiUitOpen 2:dcaee06f6ccb 403 // Clear M bit 0 to disable the MMU
MikamiUitOpen 2:dcaee06f6ccb 404 __set_SCTLR( __get_SCTLR() & ~1);
MikamiUitOpen 2:dcaee06f6ccb 405 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 406 }
MikamiUitOpen 2:dcaee06f6ccb 407
MikamiUitOpen 2:dcaee06f6ccb 408 /******************************** TLB maintenance operations ************************************************/
MikamiUitOpen 2:dcaee06f6ccb 409 /** \brief Invalidate the whole tlb
MikamiUitOpen 2:dcaee06f6ccb 410
MikamiUitOpen 2:dcaee06f6ccb 411 TLBIALL. Invalidate the whole tlb
MikamiUitOpen 2:dcaee06f6ccb 412 */
MikamiUitOpen 2:dcaee06f6ccb 413
MikamiUitOpen 2:dcaee06f6ccb 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
MikamiUitOpen 2:dcaee06f6ccb 416 __TLBIALL = 0;
MikamiUitOpen 2:dcaee06f6ccb 417 __DSB();
MikamiUitOpen 2:dcaee06f6ccb 418 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 419 }
MikamiUitOpen 2:dcaee06f6ccb 420
MikamiUitOpen 2:dcaee06f6ccb 421 /******************************** BTB maintenance operations ************************************************/
MikamiUitOpen 2:dcaee06f6ccb 422 /** \brief Invalidate entire branch predictor array
MikamiUitOpen 2:dcaee06f6ccb 423
MikamiUitOpen 2:dcaee06f6ccb 424 BPIALL. Branch Predictor Invalidate All.
MikamiUitOpen 2:dcaee06f6ccb 425 */
MikamiUitOpen 2:dcaee06f6ccb 426
MikamiUitOpen 2:dcaee06f6ccb 427 __STATIC_INLINE void __v7_inv_btac(void) {
MikamiUitOpen 2:dcaee06f6ccb 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
MikamiUitOpen 2:dcaee06f6ccb 429 __BPIALL = 0;
MikamiUitOpen 2:dcaee06f6ccb 430 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 2:dcaee06f6ccb 431 __ISB(); //ensure instruction fetch path sees new state
MikamiUitOpen 2:dcaee06f6ccb 432 }
MikamiUitOpen 2:dcaee06f6ccb 433
MikamiUitOpen 2:dcaee06f6ccb 434
MikamiUitOpen 2:dcaee06f6ccb 435 /******************************** L1 cache operations ******************************************************/
MikamiUitOpen 2:dcaee06f6ccb 436
MikamiUitOpen 2:dcaee06f6ccb 437 /** \brief Invalidate the whole I$
MikamiUitOpen 2:dcaee06f6ccb 438
MikamiUitOpen 2:dcaee06f6ccb 439 ICIALLU. Instruction Cache Invalidate All to PoU
MikamiUitOpen 2:dcaee06f6ccb 440 */
MikamiUitOpen 2:dcaee06f6ccb 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
MikamiUitOpen 2:dcaee06f6ccb 443 __ICIALLU = 0;
MikamiUitOpen 2:dcaee06f6ccb 444 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 2:dcaee06f6ccb 445 __ISB(); //ensure instruction fetch path sees new I cache state
MikamiUitOpen 2:dcaee06f6ccb 446 }
MikamiUitOpen 2:dcaee06f6ccb 447
MikamiUitOpen 2:dcaee06f6ccb 448 /** \brief Clean D$ by MVA
MikamiUitOpen 2:dcaee06f6ccb 449
MikamiUitOpen 2:dcaee06f6ccb 450 DCCMVAC. Data cache clean by MVA to PoC
MikamiUitOpen 2:dcaee06f6ccb 451 */
MikamiUitOpen 2:dcaee06f6ccb 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
MikamiUitOpen 2:dcaee06f6ccb 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
MikamiUitOpen 2:dcaee06f6ccb 454 __DCCMVAC = (uint32_t)va;
MikamiUitOpen 2:dcaee06f6ccb 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 2:dcaee06f6ccb 456 }
MikamiUitOpen 2:dcaee06f6ccb 457
MikamiUitOpen 2:dcaee06f6ccb 458 /** \brief Invalidate D$ by MVA
MikamiUitOpen 2:dcaee06f6ccb 459
MikamiUitOpen 2:dcaee06f6ccb 460 DCIMVAC. Data cache invalidate by MVA to PoC
MikamiUitOpen 2:dcaee06f6ccb 461 */
MikamiUitOpen 2:dcaee06f6ccb 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
MikamiUitOpen 2:dcaee06f6ccb 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
MikamiUitOpen 2:dcaee06f6ccb 464 __DCIMVAC = (uint32_t)va;
MikamiUitOpen 2:dcaee06f6ccb 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 2:dcaee06f6ccb 466 }
MikamiUitOpen 2:dcaee06f6ccb 467
MikamiUitOpen 2:dcaee06f6ccb 468 /** \brief Clean and Invalidate D$ by MVA
MikamiUitOpen 2:dcaee06f6ccb 469
MikamiUitOpen 2:dcaee06f6ccb 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
MikamiUitOpen 2:dcaee06f6ccb 471 */
MikamiUitOpen 2:dcaee06f6ccb 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
MikamiUitOpen 2:dcaee06f6ccb 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
MikamiUitOpen 2:dcaee06f6ccb 474 __DCCIMVAC = (uint32_t)va;
MikamiUitOpen 2:dcaee06f6ccb 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 2:dcaee06f6ccb 476 }
MikamiUitOpen 2:dcaee06f6ccb 477
MikamiUitOpen 2:dcaee06f6ccb 478 /** \brief Clean and Invalidate the entire data or unified cache
MikamiUitOpen 2:dcaee06f6ccb 479
MikamiUitOpen 2:dcaee06f6ccb 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
MikamiUitOpen 2:dcaee06f6ccb 481 */
MikamiUitOpen 2:dcaee06f6ccb 482 #pragma push
MikamiUitOpen 2:dcaee06f6ccb 483 #pragma arm
MikamiUitOpen 2:dcaee06f6ccb 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
MikamiUitOpen 2:dcaee06f6ccb 485 ARM
MikamiUitOpen 2:dcaee06f6ccb 486
MikamiUitOpen 2:dcaee06f6ccb 487 PUSH {R4-R11}
MikamiUitOpen 2:dcaee06f6ccb 488
MikamiUitOpen 2:dcaee06f6ccb 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
MikamiUitOpen 2:dcaee06f6ccb 490 ANDS R3, R6, #0x07000000 // Extract coherency level
MikamiUitOpen 2:dcaee06f6ccb 491 MOV R3, R3, LSR #23 // Total cache levels << 1
MikamiUitOpen 2:dcaee06f6ccb 492 BEQ Finished // If 0, no need to clean
MikamiUitOpen 2:dcaee06f6ccb 493
MikamiUitOpen 2:dcaee06f6ccb 494 MOV R10, #0 // R10 holds current cache level << 1
MikamiUitOpen 2:dcaee06f6ccb 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
MikamiUitOpen 2:dcaee06f6ccb 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
MikamiUitOpen 2:dcaee06f6ccb 497 AND R1, R1, #7 // Isolate those lower 3 bits
MikamiUitOpen 2:dcaee06f6ccb 498 CMP R1, #2
MikamiUitOpen 2:dcaee06f6ccb 499 BLT Skip // No cache or only instruction cache at this level
MikamiUitOpen 2:dcaee06f6ccb 500
MikamiUitOpen 2:dcaee06f6ccb 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
MikamiUitOpen 2:dcaee06f6ccb 502 ISB // ISB to sync the change to the CacheSizeID reg
MikamiUitOpen 2:dcaee06f6ccb 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
MikamiUitOpen 2:dcaee06f6ccb 504 AND R2, R1, #7 // Extract the line length field
MikamiUitOpen 2:dcaee06f6ccb 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
MikamiUitOpen 2:dcaee06f6ccb 506 LDR R4, =0x3FF
MikamiUitOpen 2:dcaee06f6ccb 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
MikamiUitOpen 2:dcaee06f6ccb 508 CLZ R5, R4 // R5 is the bit position of the way size increment
MikamiUitOpen 2:dcaee06f6ccb 509 LDR R7, =0x7FFF
MikamiUitOpen 2:dcaee06f6ccb 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
MikamiUitOpen 2:dcaee06f6ccb 511
MikamiUitOpen 2:dcaee06f6ccb 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
MikamiUitOpen 2:dcaee06f6ccb 513
MikamiUitOpen 2:dcaee06f6ccb 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
MikamiUitOpen 2:dcaee06f6ccb 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
MikamiUitOpen 2:dcaee06f6ccb 516 CMP R0, #0
MikamiUitOpen 2:dcaee06f6ccb 517 BNE Dccsw
MikamiUitOpen 2:dcaee06f6ccb 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 519 B cont
MikamiUitOpen 2:dcaee06f6ccb 520 Dccsw CMP R0, #1
MikamiUitOpen 2:dcaee06f6ccb 521 BNE Dccisw
MikamiUitOpen 2:dcaee06f6ccb 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 523 B cont
MikamiUitOpen 2:dcaee06f6ccb 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 525 cont SUBS R9, R9, #1 // Decrement the Way number
MikamiUitOpen 2:dcaee06f6ccb 526 BGE Loop3
MikamiUitOpen 2:dcaee06f6ccb 527 SUBS R7, R7, #1 // Decrement the Set number
MikamiUitOpen 2:dcaee06f6ccb 528 BGE Loop2
MikamiUitOpen 2:dcaee06f6ccb 529 Skip ADD R10, R10, #2 // Increment the cache number
MikamiUitOpen 2:dcaee06f6ccb 530 CMP R3, R10
MikamiUitOpen 2:dcaee06f6ccb 531 BGT Loop1
MikamiUitOpen 2:dcaee06f6ccb 532
MikamiUitOpen 2:dcaee06f6ccb 533 Finished
MikamiUitOpen 2:dcaee06f6ccb 534 DSB
MikamiUitOpen 2:dcaee06f6ccb 535 POP {R4-R11}
MikamiUitOpen 2:dcaee06f6ccb 536 BX lr
MikamiUitOpen 2:dcaee06f6ccb 537
MikamiUitOpen 2:dcaee06f6ccb 538 }
MikamiUitOpen 2:dcaee06f6ccb 539 #pragma pop
MikamiUitOpen 2:dcaee06f6ccb 540
MikamiUitOpen 2:dcaee06f6ccb 541
MikamiUitOpen 2:dcaee06f6ccb 542 /** \brief Invalidate the whole D$
MikamiUitOpen 2:dcaee06f6ccb 543
MikamiUitOpen 2:dcaee06f6ccb 544 DCISW. Invalidate by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 545 */
MikamiUitOpen 2:dcaee06f6ccb 546
MikamiUitOpen 2:dcaee06f6ccb 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 548 __v7_all_cache(0);
MikamiUitOpen 2:dcaee06f6ccb 549 }
MikamiUitOpen 2:dcaee06f6ccb 550
MikamiUitOpen 2:dcaee06f6ccb 551 /** \brief Clean the whole D$
MikamiUitOpen 2:dcaee06f6ccb 552
MikamiUitOpen 2:dcaee06f6ccb 553 DCCSW. Clean by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 554 */
MikamiUitOpen 2:dcaee06f6ccb 555
MikamiUitOpen 2:dcaee06f6ccb 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 557 __v7_all_cache(1);
MikamiUitOpen 2:dcaee06f6ccb 558 }
MikamiUitOpen 2:dcaee06f6ccb 559
MikamiUitOpen 2:dcaee06f6ccb 560 /** \brief Clean and invalidate the whole D$
MikamiUitOpen 2:dcaee06f6ccb 561
MikamiUitOpen 2:dcaee06f6ccb 562 DCCISW. Clean and Invalidate by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 563 */
MikamiUitOpen 2:dcaee06f6ccb 564
MikamiUitOpen 2:dcaee06f6ccb 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 566 __v7_all_cache(2);
MikamiUitOpen 2:dcaee06f6ccb 567 }
MikamiUitOpen 2:dcaee06f6ccb 568
MikamiUitOpen 2:dcaee06f6ccb 569 #include "core_ca_mmu.h"
MikamiUitOpen 2:dcaee06f6ccb 570
MikamiUitOpen 2:dcaee06f6ccb 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
MikamiUitOpen 2:dcaee06f6ccb 572
MikamiUitOpen 2:dcaee06f6ccb 573 #define __inline inline
MikamiUitOpen 2:dcaee06f6ccb 574
MikamiUitOpen 2:dcaee06f6ccb 575 inline static uint32_t __disable_irq_iar() {
MikamiUitOpen 2:dcaee06f6ccb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
MikamiUitOpen 2:dcaee06f6ccb 577 __disable_irq();
MikamiUitOpen 2:dcaee06f6ccb 578 return irq_dis;
MikamiUitOpen 2:dcaee06f6ccb 579 }
MikamiUitOpen 2:dcaee06f6ccb 580
MikamiUitOpen 2:dcaee06f6ccb 581 #define MODE_USR 0x10
MikamiUitOpen 2:dcaee06f6ccb 582 #define MODE_FIQ 0x11
MikamiUitOpen 2:dcaee06f6ccb 583 #define MODE_IRQ 0x12
MikamiUitOpen 2:dcaee06f6ccb 584 #define MODE_SVC 0x13
MikamiUitOpen 2:dcaee06f6ccb 585 #define MODE_MON 0x16
MikamiUitOpen 2:dcaee06f6ccb 586 #define MODE_ABT 0x17
MikamiUitOpen 2:dcaee06f6ccb 587 #define MODE_HYP 0x1A
MikamiUitOpen 2:dcaee06f6ccb 588 #define MODE_UND 0x1B
MikamiUitOpen 2:dcaee06f6ccb 589 #define MODE_SYS 0x1F
MikamiUitOpen 2:dcaee06f6ccb 590
MikamiUitOpen 2:dcaee06f6ccb 591 /** \brief Set Process Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 592
MikamiUitOpen 2:dcaee06f6ccb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
MikamiUitOpen 2:dcaee06f6ccb 594
MikamiUitOpen 2:dcaee06f6ccb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
MikamiUitOpen 2:dcaee06f6ccb 596 */
MikamiUitOpen 2:dcaee06f6ccb 597 // from rt_CMSIS.c
MikamiUitOpen 2:dcaee06f6ccb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
MikamiUitOpen 2:dcaee06f6ccb 599 __asm(
MikamiUitOpen 2:dcaee06f6ccb 600 " ARM\n"
MikamiUitOpen 2:dcaee06f6ccb 601 // " PRESERVE8\n"
MikamiUitOpen 2:dcaee06f6ccb 602
MikamiUitOpen 2:dcaee06f6ccb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
MikamiUitOpen 2:dcaee06f6ccb 604 " MRS R1, CPSR \n"
MikamiUitOpen 2:dcaee06f6ccb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
MikamiUitOpen 2:dcaee06f6ccb 606 " MOV SP, R0 \n"
MikamiUitOpen 2:dcaee06f6ccb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
MikamiUitOpen 2:dcaee06f6ccb 608 " ISB \n"
MikamiUitOpen 2:dcaee06f6ccb 609 " BX LR \n");
MikamiUitOpen 2:dcaee06f6ccb 610 }
MikamiUitOpen 2:dcaee06f6ccb 611
MikamiUitOpen 2:dcaee06f6ccb 612 /** \brief Set User Mode
MikamiUitOpen 2:dcaee06f6ccb 613
MikamiUitOpen 2:dcaee06f6ccb 614 This function changes the processor state to User Mode
MikamiUitOpen 2:dcaee06f6ccb 615 */
MikamiUitOpen 2:dcaee06f6ccb 616 // from rt_CMSIS.c
MikamiUitOpen 2:dcaee06f6ccb 617 __arm static inline void __set_CPS_USR(void) {
MikamiUitOpen 2:dcaee06f6ccb 618 __asm(
MikamiUitOpen 2:dcaee06f6ccb 619 " ARM \n"
MikamiUitOpen 2:dcaee06f6ccb 620
MikamiUitOpen 2:dcaee06f6ccb 621 " CPS #0x10 \n" // MODE_USR
MikamiUitOpen 2:dcaee06f6ccb 622 " BX LR\n");
MikamiUitOpen 2:dcaee06f6ccb 623 }
MikamiUitOpen 2:dcaee06f6ccb 624
MikamiUitOpen 2:dcaee06f6ccb 625 /** \brief Set TTBR0
MikamiUitOpen 2:dcaee06f6ccb 626
MikamiUitOpen 2:dcaee06f6ccb 627 This function assigns the given value to the Translation Table Base Register 0.
MikamiUitOpen 2:dcaee06f6ccb 628
MikamiUitOpen 2:dcaee06f6ccb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
MikamiUitOpen 2:dcaee06f6ccb 630 */
MikamiUitOpen 2:dcaee06f6ccb 631 // from mmu_Renesas_RZ_A1.c
MikamiUitOpen 2:dcaee06f6ccb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
MikamiUitOpen 2:dcaee06f6ccb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
MikamiUitOpen 2:dcaee06f6ccb 634 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 635 }
MikamiUitOpen 2:dcaee06f6ccb 636
MikamiUitOpen 2:dcaee06f6ccb 637 /** \brief Set DACR
MikamiUitOpen 2:dcaee06f6ccb 638
MikamiUitOpen 2:dcaee06f6ccb 639 This function assigns the given value to the Domain Access Control Register.
MikamiUitOpen 2:dcaee06f6ccb 640
MikamiUitOpen 2:dcaee06f6ccb 641 \param [in] dacr Domain Access Control Register value to set
MikamiUitOpen 2:dcaee06f6ccb 642 */
MikamiUitOpen 2:dcaee06f6ccb 643 // from mmu_Renesas_RZ_A1.c
MikamiUitOpen 2:dcaee06f6ccb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
MikamiUitOpen 2:dcaee06f6ccb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
MikamiUitOpen 2:dcaee06f6ccb 646 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 647 }
MikamiUitOpen 2:dcaee06f6ccb 648
MikamiUitOpen 2:dcaee06f6ccb 649
MikamiUitOpen 2:dcaee06f6ccb 650 /******************************** Cache and BTAC enable ****************************************************/
MikamiUitOpen 2:dcaee06f6ccb 651 /** \brief Set SCTLR
MikamiUitOpen 2:dcaee06f6ccb 652
MikamiUitOpen 2:dcaee06f6ccb 653 This function assigns the given value to the System Control Register.
MikamiUitOpen 2:dcaee06f6ccb 654
MikamiUitOpen 2:dcaee06f6ccb 655 \param [in] sctlr System Control Register value to set
MikamiUitOpen 2:dcaee06f6ccb 656 */
MikamiUitOpen 2:dcaee06f6ccb 657 // from __enable_mmu()
MikamiUitOpen 2:dcaee06f6ccb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
MikamiUitOpen 2:dcaee06f6ccb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
MikamiUitOpen 2:dcaee06f6ccb 660 }
MikamiUitOpen 2:dcaee06f6ccb 661
MikamiUitOpen 2:dcaee06f6ccb 662 /** \brief Get SCTLR
MikamiUitOpen 2:dcaee06f6ccb 663
MikamiUitOpen 2:dcaee06f6ccb 664 This function returns the value of the System Control Register.
MikamiUitOpen 2:dcaee06f6ccb 665
MikamiUitOpen 2:dcaee06f6ccb 666 \return System Control Register value
MikamiUitOpen 2:dcaee06f6ccb 667 */
MikamiUitOpen 2:dcaee06f6ccb 668 // from __enable_mmu()
MikamiUitOpen 2:dcaee06f6ccb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
MikamiUitOpen 2:dcaee06f6ccb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
MikamiUitOpen 2:dcaee06f6ccb 671 return __regSCTLR;
MikamiUitOpen 2:dcaee06f6ccb 672 }
MikamiUitOpen 2:dcaee06f6ccb 673
MikamiUitOpen 2:dcaee06f6ccb 674 /** \brief Enable Caches
MikamiUitOpen 2:dcaee06f6ccb 675
MikamiUitOpen 2:dcaee06f6ccb 676 Enable Caches
MikamiUitOpen 2:dcaee06f6ccb 677 */
MikamiUitOpen 2:dcaee06f6ccb 678 // from system_Renesas_RZ_A1.c
MikamiUitOpen 2:dcaee06f6ccb 679 __STATIC_INLINE void __enable_caches(void) {
MikamiUitOpen 2:dcaee06f6ccb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
MikamiUitOpen 2:dcaee06f6ccb 681 }
MikamiUitOpen 2:dcaee06f6ccb 682
MikamiUitOpen 2:dcaee06f6ccb 683 /** \brief Enable BTAC
MikamiUitOpen 2:dcaee06f6ccb 684
MikamiUitOpen 2:dcaee06f6ccb 685 Enable BTAC
MikamiUitOpen 2:dcaee06f6ccb 686 */
MikamiUitOpen 2:dcaee06f6ccb 687 // from system_Renesas_RZ_A1.c
MikamiUitOpen 2:dcaee06f6ccb 688 __STATIC_INLINE void __enable_btac(void) {
MikamiUitOpen 2:dcaee06f6ccb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
MikamiUitOpen 2:dcaee06f6ccb 690 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 691 }
MikamiUitOpen 2:dcaee06f6ccb 692
MikamiUitOpen 2:dcaee06f6ccb 693 /** \brief Enable MMU
MikamiUitOpen 2:dcaee06f6ccb 694
MikamiUitOpen 2:dcaee06f6ccb 695 Enable MMU
MikamiUitOpen 2:dcaee06f6ccb 696 */
MikamiUitOpen 2:dcaee06f6ccb 697 // from system_Renesas_RZ_A1.c
MikamiUitOpen 2:dcaee06f6ccb 698 __STATIC_INLINE void __enable_mmu(void) {
MikamiUitOpen 2:dcaee06f6ccb 699 // Set M bit 0 to enable the MMU
MikamiUitOpen 2:dcaee06f6ccb 700 // Set AFE bit to enable simplified access permissions model
MikamiUitOpen 2:dcaee06f6ccb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
MikamiUitOpen 2:dcaee06f6ccb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
MikamiUitOpen 2:dcaee06f6ccb 703 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 704 }
MikamiUitOpen 2:dcaee06f6ccb 705
MikamiUitOpen 2:dcaee06f6ccb 706 /******************************** TLB maintenance operations ************************************************/
MikamiUitOpen 2:dcaee06f6ccb 707 /** \brief Invalidate the whole tlb
MikamiUitOpen 2:dcaee06f6ccb 708
MikamiUitOpen 2:dcaee06f6ccb 709 TLBIALL. Invalidate the whole tlb
MikamiUitOpen 2:dcaee06f6ccb 710 */
MikamiUitOpen 2:dcaee06f6ccb 711 // from system_Renesas_RZ_A1.c
MikamiUitOpen 2:dcaee06f6ccb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 713 uint32_t val = 0;
MikamiUitOpen 2:dcaee06f6ccb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
MikamiUitOpen 2:dcaee06f6ccb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
MikamiUitOpen 2:dcaee06f6ccb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
MikamiUitOpen 2:dcaee06f6ccb 717 __DSB();
MikamiUitOpen 2:dcaee06f6ccb 718 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 719 }
MikamiUitOpen 2:dcaee06f6ccb 720
MikamiUitOpen 2:dcaee06f6ccb 721 /******************************** BTB maintenance operations ************************************************/
MikamiUitOpen 2:dcaee06f6ccb 722 /** \brief Invalidate entire branch predictor array
MikamiUitOpen 2:dcaee06f6ccb 723
MikamiUitOpen 2:dcaee06f6ccb 724 BPIALL. Branch Predictor Invalidate All.
MikamiUitOpen 2:dcaee06f6ccb 725 */
MikamiUitOpen 2:dcaee06f6ccb 726 // from system_Renesas_RZ_A1.c
MikamiUitOpen 2:dcaee06f6ccb 727 __STATIC_INLINE void __v7_inv_btac(void) {
MikamiUitOpen 2:dcaee06f6ccb 728 uint32_t val = 0;
MikamiUitOpen 2:dcaee06f6ccb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
MikamiUitOpen 2:dcaee06f6ccb 730 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 2:dcaee06f6ccb 731 __ISB(); //ensure instruction fetch path sees new state
MikamiUitOpen 2:dcaee06f6ccb 732 }
MikamiUitOpen 2:dcaee06f6ccb 733
MikamiUitOpen 2:dcaee06f6ccb 734
MikamiUitOpen 2:dcaee06f6ccb 735 /******************************** L1 cache operations ******************************************************/
MikamiUitOpen 2:dcaee06f6ccb 736
MikamiUitOpen 2:dcaee06f6ccb 737 /** \brief Invalidate the whole I$
MikamiUitOpen 2:dcaee06f6ccb 738
MikamiUitOpen 2:dcaee06f6ccb 739 ICIALLU. Instruction Cache Invalidate All to PoU
MikamiUitOpen 2:dcaee06f6ccb 740 */
MikamiUitOpen 2:dcaee06f6ccb 741 // from system_Renesas_RZ_A1.c
MikamiUitOpen 2:dcaee06f6ccb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 743 uint32_t val = 0;
MikamiUitOpen 2:dcaee06f6ccb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
MikamiUitOpen 2:dcaee06f6ccb 745 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 2:dcaee06f6ccb 746 __ISB(); //ensure instruction fetch path sees new I cache state
MikamiUitOpen 2:dcaee06f6ccb 747 }
MikamiUitOpen 2:dcaee06f6ccb 748
MikamiUitOpen 2:dcaee06f6ccb 749 // from __v7_inv_dcache_all()
MikamiUitOpen 2:dcaee06f6ccb 750 __arm static inline void __v7_all_cache(uint32_t op) {
MikamiUitOpen 2:dcaee06f6ccb 751 __asm(
MikamiUitOpen 2:dcaee06f6ccb 752 " ARM \n"
MikamiUitOpen 2:dcaee06f6ccb 753
MikamiUitOpen 2:dcaee06f6ccb 754 " PUSH {R4-R11} \n"
MikamiUitOpen 2:dcaee06f6ccb 755
MikamiUitOpen 2:dcaee06f6ccb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
MikamiUitOpen 2:dcaee06f6ccb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
MikamiUitOpen 2:dcaee06f6ccb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
MikamiUitOpen 2:dcaee06f6ccb 759 " BEQ Finished\n" // If 0, no need to clean
MikamiUitOpen 2:dcaee06f6ccb 760
MikamiUitOpen 2:dcaee06f6ccb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
MikamiUitOpen 2:dcaee06f6ccb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
MikamiUitOpen 2:dcaee06f6ccb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
MikamiUitOpen 2:dcaee06f6ccb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
MikamiUitOpen 2:dcaee06f6ccb 765 " CMP R1, #2 \n"
MikamiUitOpen 2:dcaee06f6ccb 766 " BLT Skip \n" // No cache or only instruction cache at this level
MikamiUitOpen 2:dcaee06f6ccb 767
MikamiUitOpen 2:dcaee06f6ccb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
MikamiUitOpen 2:dcaee06f6ccb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
MikamiUitOpen 2:dcaee06f6ccb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
MikamiUitOpen 2:dcaee06f6ccb 771 " AND R2, R1, #7 \n" // Extract the line length field
MikamiUitOpen 2:dcaee06f6ccb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
MikamiUitOpen 2:dcaee06f6ccb 773 " movw R4, #0x3FF \n"
MikamiUitOpen 2:dcaee06f6ccb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
MikamiUitOpen 2:dcaee06f6ccb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
MikamiUitOpen 2:dcaee06f6ccb 776 " movw R7, #0x7FFF \n"
MikamiUitOpen 2:dcaee06f6ccb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
MikamiUitOpen 2:dcaee06f6ccb 778
MikamiUitOpen 2:dcaee06f6ccb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
MikamiUitOpen 2:dcaee06f6ccb 780
MikamiUitOpen 2:dcaee06f6ccb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
MikamiUitOpen 2:dcaee06f6ccb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
MikamiUitOpen 2:dcaee06f6ccb 783 " CMP R0, #0 \n"
MikamiUitOpen 2:dcaee06f6ccb 784 " BNE Dccsw \n"
MikamiUitOpen 2:dcaee06f6ccb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 786 " B cont \n"
MikamiUitOpen 2:dcaee06f6ccb 787 "Dccsw: CMP R0, #1 \n"
MikamiUitOpen 2:dcaee06f6ccb 788 " BNE Dccisw \n"
MikamiUitOpen 2:dcaee06f6ccb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 790 " B cont \n"
MikamiUitOpen 2:dcaee06f6ccb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
MikamiUitOpen 2:dcaee06f6ccb 793 " BGE Loop3 \n"
MikamiUitOpen 2:dcaee06f6ccb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
MikamiUitOpen 2:dcaee06f6ccb 795 " BGE Loop2 \n"
MikamiUitOpen 2:dcaee06f6ccb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
MikamiUitOpen 2:dcaee06f6ccb 797 " CMP R3, R10 \n"
MikamiUitOpen 2:dcaee06f6ccb 798 " BGT Loop1 \n"
MikamiUitOpen 2:dcaee06f6ccb 799
MikamiUitOpen 2:dcaee06f6ccb 800 "Finished: \n"
MikamiUitOpen 2:dcaee06f6ccb 801 " DSB \n"
MikamiUitOpen 2:dcaee06f6ccb 802 " POP {R4-R11} \n"
MikamiUitOpen 2:dcaee06f6ccb 803 " BX lr \n" );
MikamiUitOpen 2:dcaee06f6ccb 804 }
MikamiUitOpen 2:dcaee06f6ccb 805
MikamiUitOpen 2:dcaee06f6ccb 806 /** \brief Invalidate the whole D$
MikamiUitOpen 2:dcaee06f6ccb 807
MikamiUitOpen 2:dcaee06f6ccb 808 DCISW. Invalidate by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 809 */
MikamiUitOpen 2:dcaee06f6ccb 810 // from system_Renesas_RZ_A1.c
MikamiUitOpen 2:dcaee06f6ccb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 812 __v7_all_cache(0);
MikamiUitOpen 2:dcaee06f6ccb 813 }
MikamiUitOpen 2:dcaee06f6ccb 814 /** \brief Clean and Invalidate D$ by MVA
MikamiUitOpen 2:dcaee06f6ccb 815
MikamiUitOpen 2:dcaee06f6ccb 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
MikamiUitOpen 2:dcaee06f6ccb 817 */
MikamiUitOpen 2:dcaee06f6ccb 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
MikamiUitOpen 2:dcaee06f6ccb 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
MikamiUitOpen 2:dcaee06f6ccb 820 __DMB();
MikamiUitOpen 2:dcaee06f6ccb 821 }
MikamiUitOpen 2:dcaee06f6ccb 822
MikamiUitOpen 2:dcaee06f6ccb 823 #include "core_ca_mmu.h"
MikamiUitOpen 2:dcaee06f6ccb 824
MikamiUitOpen 2:dcaee06f6ccb 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 2:dcaee06f6ccb 826 /* GNU gcc specific functions */
MikamiUitOpen 2:dcaee06f6ccb 827
MikamiUitOpen 2:dcaee06f6ccb 828 #define MODE_USR 0x10
MikamiUitOpen 2:dcaee06f6ccb 829 #define MODE_FIQ 0x11
MikamiUitOpen 2:dcaee06f6ccb 830 #define MODE_IRQ 0x12
MikamiUitOpen 2:dcaee06f6ccb 831 #define MODE_SVC 0x13
MikamiUitOpen 2:dcaee06f6ccb 832 #define MODE_MON 0x16
MikamiUitOpen 2:dcaee06f6ccb 833 #define MODE_ABT 0x17
MikamiUitOpen 2:dcaee06f6ccb 834 #define MODE_HYP 0x1A
MikamiUitOpen 2:dcaee06f6ccb 835 #define MODE_UND 0x1B
MikamiUitOpen 2:dcaee06f6ccb 836 #define MODE_SYS 0x1F
MikamiUitOpen 2:dcaee06f6ccb 837
MikamiUitOpen 2:dcaee06f6ccb 838
MikamiUitOpen 2:dcaee06f6ccb 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
MikamiUitOpen 2:dcaee06f6ccb 840 {
MikamiUitOpen 2:dcaee06f6ccb 841 __ASM volatile ("cpsie i");
MikamiUitOpen 2:dcaee06f6ccb 842 }
MikamiUitOpen 2:dcaee06f6ccb 843
MikamiUitOpen 2:dcaee06f6ccb 844 /** \brief Disable IRQ Interrupts
MikamiUitOpen 2:dcaee06f6ccb 845
MikamiUitOpen 2:dcaee06f6ccb 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 847 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 848 */
MikamiUitOpen 2:dcaee06f6ccb 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
MikamiUitOpen 2:dcaee06f6ccb 850 {
MikamiUitOpen 2:dcaee06f6ccb 851 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 852
MikamiUitOpen 2:dcaee06f6ccb 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
MikamiUitOpen 2:dcaee06f6ccb 854 __ASM volatile ("cpsid i");
MikamiUitOpen 2:dcaee06f6ccb 855 return(result & 0x80);
MikamiUitOpen 2:dcaee06f6ccb 856 }
MikamiUitOpen 2:dcaee06f6ccb 857
MikamiUitOpen 2:dcaee06f6ccb 858
MikamiUitOpen 2:dcaee06f6ccb 859 /** \brief Get APSR Register
MikamiUitOpen 2:dcaee06f6ccb 860
MikamiUitOpen 2:dcaee06f6ccb 861 This function returns the content of the APSR Register.
MikamiUitOpen 2:dcaee06f6ccb 862
MikamiUitOpen 2:dcaee06f6ccb 863 \return APSR Register value
MikamiUitOpen 2:dcaee06f6ccb 864 */
MikamiUitOpen 2:dcaee06f6ccb 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 2:dcaee06f6ccb 866 {
MikamiUitOpen 2:dcaee06f6ccb 867 #if 1
MikamiUitOpen 2:dcaee06f6ccb 868 register uint32_t __regAPSR;
MikamiUitOpen 2:dcaee06f6ccb 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
MikamiUitOpen 2:dcaee06f6ccb 870 #else
MikamiUitOpen 2:dcaee06f6ccb 871 register uint32_t __regAPSR __ASM("apsr");
MikamiUitOpen 2:dcaee06f6ccb 872 #endif
MikamiUitOpen 2:dcaee06f6ccb 873 return(__regAPSR);
MikamiUitOpen 2:dcaee06f6ccb 874 }
MikamiUitOpen 2:dcaee06f6ccb 875
MikamiUitOpen 2:dcaee06f6ccb 876
MikamiUitOpen 2:dcaee06f6ccb 877 /** \brief Get CPSR Register
MikamiUitOpen 2:dcaee06f6ccb 878
MikamiUitOpen 2:dcaee06f6ccb 879 This function returns the content of the CPSR Register.
MikamiUitOpen 2:dcaee06f6ccb 880
MikamiUitOpen 2:dcaee06f6ccb 881 \return CPSR Register value
MikamiUitOpen 2:dcaee06f6ccb 882 */
MikamiUitOpen 2:dcaee06f6ccb 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
MikamiUitOpen 2:dcaee06f6ccb 884 {
MikamiUitOpen 2:dcaee06f6ccb 885 #if 1
MikamiUitOpen 2:dcaee06f6ccb 886 register uint32_t __regCPSR;
MikamiUitOpen 2:dcaee06f6ccb 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
MikamiUitOpen 2:dcaee06f6ccb 888 #else
MikamiUitOpen 2:dcaee06f6ccb 889 register uint32_t __regCPSR __ASM("cpsr");
MikamiUitOpen 2:dcaee06f6ccb 890 #endif
MikamiUitOpen 2:dcaee06f6ccb 891 return(__regCPSR);
MikamiUitOpen 2:dcaee06f6ccb 892 }
MikamiUitOpen 2:dcaee06f6ccb 893
MikamiUitOpen 2:dcaee06f6ccb 894 #if 0
MikamiUitOpen 2:dcaee06f6ccb 895 /** \brief Set Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 896
MikamiUitOpen 2:dcaee06f6ccb 897 This function assigns the given value to the current stack pointer.
MikamiUitOpen 2:dcaee06f6ccb 898
MikamiUitOpen 2:dcaee06f6ccb 899 \param [in] topOfStack Stack Pointer value to set
MikamiUitOpen 2:dcaee06f6ccb 900 */
MikamiUitOpen 2:dcaee06f6ccb 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
MikamiUitOpen 2:dcaee06f6ccb 902 {
MikamiUitOpen 2:dcaee06f6ccb 903 register uint32_t __regSP __ASM("sp");
MikamiUitOpen 2:dcaee06f6ccb 904 __regSP = topOfStack;
MikamiUitOpen 2:dcaee06f6ccb 905 }
MikamiUitOpen 2:dcaee06f6ccb 906 #endif
MikamiUitOpen 2:dcaee06f6ccb 907
MikamiUitOpen 2:dcaee06f6ccb 908 /** \brief Get link register
MikamiUitOpen 2:dcaee06f6ccb 909
MikamiUitOpen 2:dcaee06f6ccb 910 This function returns the value of the link register
MikamiUitOpen 2:dcaee06f6ccb 911
MikamiUitOpen 2:dcaee06f6ccb 912 \return Value of link register
MikamiUitOpen 2:dcaee06f6ccb 913 */
MikamiUitOpen 2:dcaee06f6ccb 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
MikamiUitOpen 2:dcaee06f6ccb 915 {
MikamiUitOpen 2:dcaee06f6ccb 916 register uint32_t __reglr __ASM("lr");
MikamiUitOpen 2:dcaee06f6ccb 917 return(__reglr);
MikamiUitOpen 2:dcaee06f6ccb 918 }
MikamiUitOpen 2:dcaee06f6ccb 919
MikamiUitOpen 2:dcaee06f6ccb 920 #if 0
MikamiUitOpen 2:dcaee06f6ccb 921 /** \brief Set link register
MikamiUitOpen 2:dcaee06f6ccb 922
MikamiUitOpen 2:dcaee06f6ccb 923 This function sets the value of the link register
MikamiUitOpen 2:dcaee06f6ccb 924
MikamiUitOpen 2:dcaee06f6ccb 925 \param [in] lr LR value to set
MikamiUitOpen 2:dcaee06f6ccb 926 */
MikamiUitOpen 2:dcaee06f6ccb 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
MikamiUitOpen 2:dcaee06f6ccb 928 {
MikamiUitOpen 2:dcaee06f6ccb 929 register uint32_t __reglr __ASM("lr");
MikamiUitOpen 2:dcaee06f6ccb 930 __reglr = lr;
MikamiUitOpen 2:dcaee06f6ccb 931 }
MikamiUitOpen 2:dcaee06f6ccb 932 #endif
MikamiUitOpen 2:dcaee06f6ccb 933
MikamiUitOpen 2:dcaee06f6ccb 934 /** \brief Set Process Stack Pointer
MikamiUitOpen 2:dcaee06f6ccb 935
MikamiUitOpen 2:dcaee06f6ccb 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
MikamiUitOpen 2:dcaee06f6ccb 937
MikamiUitOpen 2:dcaee06f6ccb 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
MikamiUitOpen 2:dcaee06f6ccb 939 */
MikamiUitOpen 2:dcaee06f6ccb 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 2:dcaee06f6ccb 941 {
MikamiUitOpen 2:dcaee06f6ccb 942 __asm__ volatile (
MikamiUitOpen 2:dcaee06f6ccb 943 ".ARM;"
MikamiUitOpen 2:dcaee06f6ccb 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
MikamiUitOpen 2:dcaee06f6ccb 945
MikamiUitOpen 2:dcaee06f6ccb 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
MikamiUitOpen 2:dcaee06f6ccb 947 "MRS R1, CPSR;"
MikamiUitOpen 2:dcaee06f6ccb 948 "CPS %0;" /* ;no effect in USR mode */
MikamiUitOpen 2:dcaee06f6ccb 949 "MOV SP, R0;"
MikamiUitOpen 2:dcaee06f6ccb 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
MikamiUitOpen 2:dcaee06f6ccb 951 "ISB;"
MikamiUitOpen 2:dcaee06f6ccb 952 //"BX LR;"
MikamiUitOpen 2:dcaee06f6ccb 953 :
MikamiUitOpen 2:dcaee06f6ccb 954 : "i"(MODE_SYS)
MikamiUitOpen 2:dcaee06f6ccb 955 : "r0", "r1");
MikamiUitOpen 2:dcaee06f6ccb 956 return;
MikamiUitOpen 2:dcaee06f6ccb 957 }
MikamiUitOpen 2:dcaee06f6ccb 958
MikamiUitOpen 2:dcaee06f6ccb 959 /** \brief Set User Mode
MikamiUitOpen 2:dcaee06f6ccb 960
MikamiUitOpen 2:dcaee06f6ccb 961 This function changes the processor state to User Mode
MikamiUitOpen 2:dcaee06f6ccb 962 */
MikamiUitOpen 2:dcaee06f6ccb 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
MikamiUitOpen 2:dcaee06f6ccb 964 {
MikamiUitOpen 2:dcaee06f6ccb 965 __asm__ volatile (
MikamiUitOpen 2:dcaee06f6ccb 966 ".ARM;"
MikamiUitOpen 2:dcaee06f6ccb 967
MikamiUitOpen 2:dcaee06f6ccb 968 "CPS %0;"
MikamiUitOpen 2:dcaee06f6ccb 969 //"BX LR;"
MikamiUitOpen 2:dcaee06f6ccb 970 :
MikamiUitOpen 2:dcaee06f6ccb 971 : "i"(MODE_USR)
MikamiUitOpen 2:dcaee06f6ccb 972 : );
MikamiUitOpen 2:dcaee06f6ccb 973 return;
MikamiUitOpen 2:dcaee06f6ccb 974 }
MikamiUitOpen 2:dcaee06f6ccb 975
MikamiUitOpen 2:dcaee06f6ccb 976
MikamiUitOpen 2:dcaee06f6ccb 977 /** \brief Enable FIQ
MikamiUitOpen 2:dcaee06f6ccb 978
MikamiUitOpen 2:dcaee06f6ccb 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 980 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 981 */
MikamiUitOpen 2:dcaee06f6ccb 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
MikamiUitOpen 2:dcaee06f6ccb 983
MikamiUitOpen 2:dcaee06f6ccb 984
MikamiUitOpen 2:dcaee06f6ccb 985 /** \brief Disable FIQ
MikamiUitOpen 2:dcaee06f6ccb 986
MikamiUitOpen 2:dcaee06f6ccb 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 2:dcaee06f6ccb 988 Can only be executed in Privileged modes.
MikamiUitOpen 2:dcaee06f6ccb 989 */
MikamiUitOpen 2:dcaee06f6ccb 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
MikamiUitOpen 2:dcaee06f6ccb 991
MikamiUitOpen 2:dcaee06f6ccb 992
MikamiUitOpen 2:dcaee06f6ccb 993 /** \brief Get FPSCR
MikamiUitOpen 2:dcaee06f6ccb 994
MikamiUitOpen 2:dcaee06f6ccb 995 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 2:dcaee06f6ccb 996
MikamiUitOpen 2:dcaee06f6ccb 997 \return Floating Point Status/Control register value
MikamiUitOpen 2:dcaee06f6ccb 998 */
MikamiUitOpen 2:dcaee06f6ccb 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 2:dcaee06f6ccb 1000 {
MikamiUitOpen 2:dcaee06f6ccb 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 2:dcaee06f6ccb 1002 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1003 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 1004
MikamiUitOpen 2:dcaee06f6ccb 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
MikamiUitOpen 2:dcaee06f6ccb 1006 return (result);
MikamiUitOpen 2:dcaee06f6ccb 1007 #else
MikamiUitOpen 2:dcaee06f6ccb 1008 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 2:dcaee06f6ccb 1009 return(__regfpscr);
MikamiUitOpen 2:dcaee06f6ccb 1010 #endif
MikamiUitOpen 2:dcaee06f6ccb 1011 #else
MikamiUitOpen 2:dcaee06f6ccb 1012 return(0);
MikamiUitOpen 2:dcaee06f6ccb 1013 #endif
MikamiUitOpen 2:dcaee06f6ccb 1014 }
MikamiUitOpen 2:dcaee06f6ccb 1015
MikamiUitOpen 2:dcaee06f6ccb 1016
MikamiUitOpen 2:dcaee06f6ccb 1017 /** \brief Set FPSCR
MikamiUitOpen 2:dcaee06f6ccb 1018
MikamiUitOpen 2:dcaee06f6ccb 1019 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 2:dcaee06f6ccb 1020
MikamiUitOpen 2:dcaee06f6ccb 1021 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 2:dcaee06f6ccb 1022 */
MikamiUitOpen 2:dcaee06f6ccb 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 2:dcaee06f6ccb 1024 {
MikamiUitOpen 2:dcaee06f6ccb 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 2:dcaee06f6ccb 1026 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
MikamiUitOpen 2:dcaee06f6ccb 1028 #else
MikamiUitOpen 2:dcaee06f6ccb 1029 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 2:dcaee06f6ccb 1030 __regfpscr = (fpscr);
MikamiUitOpen 2:dcaee06f6ccb 1031 #endif
MikamiUitOpen 2:dcaee06f6ccb 1032 #endif
MikamiUitOpen 2:dcaee06f6ccb 1033 }
MikamiUitOpen 2:dcaee06f6ccb 1034
MikamiUitOpen 2:dcaee06f6ccb 1035 /** \brief Get FPEXC
MikamiUitOpen 2:dcaee06f6ccb 1036
MikamiUitOpen 2:dcaee06f6ccb 1037 This function returns the current value of the Floating Point Exception Control register.
MikamiUitOpen 2:dcaee06f6ccb 1038
MikamiUitOpen 2:dcaee06f6ccb 1039 \return Floating Point Exception Control register value
MikamiUitOpen 2:dcaee06f6ccb 1040 */
MikamiUitOpen 2:dcaee06f6ccb 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
MikamiUitOpen 2:dcaee06f6ccb 1042 {
MikamiUitOpen 2:dcaee06f6ccb 1043 #if (__FPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 1044 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1045 uint32_t result;
MikamiUitOpen 2:dcaee06f6ccb 1046
MikamiUitOpen 2:dcaee06f6ccb 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
MikamiUitOpen 2:dcaee06f6ccb 1048 return (result);
MikamiUitOpen 2:dcaee06f6ccb 1049 #else
MikamiUitOpen 2:dcaee06f6ccb 1050 register uint32_t __regfpexc __ASM("fpexc");
MikamiUitOpen 2:dcaee06f6ccb 1051 return(__regfpexc);
MikamiUitOpen 2:dcaee06f6ccb 1052 #endif
MikamiUitOpen 2:dcaee06f6ccb 1053 #else
MikamiUitOpen 2:dcaee06f6ccb 1054 return(0);
MikamiUitOpen 2:dcaee06f6ccb 1055 #endif
MikamiUitOpen 2:dcaee06f6ccb 1056 }
MikamiUitOpen 2:dcaee06f6ccb 1057
MikamiUitOpen 2:dcaee06f6ccb 1058
MikamiUitOpen 2:dcaee06f6ccb 1059 /** \brief Set FPEXC
MikamiUitOpen 2:dcaee06f6ccb 1060
MikamiUitOpen 2:dcaee06f6ccb 1061 This function assigns the given value to the Floating Point Exception Control register.
MikamiUitOpen 2:dcaee06f6ccb 1062
MikamiUitOpen 2:dcaee06f6ccb 1063 \param [in] fpscr Floating Point Exception Control value to set
MikamiUitOpen 2:dcaee06f6ccb 1064 */
MikamiUitOpen 2:dcaee06f6ccb 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
MikamiUitOpen 2:dcaee06f6ccb 1066 {
MikamiUitOpen 2:dcaee06f6ccb 1067 #if (__FPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 1068 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
MikamiUitOpen 2:dcaee06f6ccb 1070 #else
MikamiUitOpen 2:dcaee06f6ccb 1071 register uint32_t __regfpexc __ASM("fpexc");
MikamiUitOpen 2:dcaee06f6ccb 1072 __regfpexc = (fpexc);
MikamiUitOpen 2:dcaee06f6ccb 1073 #endif
MikamiUitOpen 2:dcaee06f6ccb 1074 #endif
MikamiUitOpen 2:dcaee06f6ccb 1075 }
MikamiUitOpen 2:dcaee06f6ccb 1076
MikamiUitOpen 2:dcaee06f6ccb 1077 /** \brief Get CPACR
MikamiUitOpen 2:dcaee06f6ccb 1078
MikamiUitOpen 2:dcaee06f6ccb 1079 This function returns the current value of the Coprocessor Access Control register.
MikamiUitOpen 2:dcaee06f6ccb 1080
MikamiUitOpen 2:dcaee06f6ccb 1081 \return Coprocessor Access Control register value
MikamiUitOpen 2:dcaee06f6ccb 1082 */
MikamiUitOpen 2:dcaee06f6ccb 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
MikamiUitOpen 2:dcaee06f6ccb 1084 {
MikamiUitOpen 2:dcaee06f6ccb 1085 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1086 register uint32_t __regCPACR;
MikamiUitOpen 2:dcaee06f6ccb 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
MikamiUitOpen 2:dcaee06f6ccb 1088 #else
MikamiUitOpen 2:dcaee06f6ccb 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MikamiUitOpen 2:dcaee06f6ccb 1090 #endif
MikamiUitOpen 2:dcaee06f6ccb 1091 return __regCPACR;
MikamiUitOpen 2:dcaee06f6ccb 1092 }
MikamiUitOpen 2:dcaee06f6ccb 1093
MikamiUitOpen 2:dcaee06f6ccb 1094 /** \brief Set CPACR
MikamiUitOpen 2:dcaee06f6ccb 1095
MikamiUitOpen 2:dcaee06f6ccb 1096 This function assigns the given value to the Coprocessor Access Control register.
MikamiUitOpen 2:dcaee06f6ccb 1097
MikamiUitOpen 2:dcaee06f6ccb 1098 \param [in] cpacr Coprocessor Acccess Control value to set
MikamiUitOpen 2:dcaee06f6ccb 1099 */
MikamiUitOpen 2:dcaee06f6ccb 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
MikamiUitOpen 2:dcaee06f6ccb 1101 {
MikamiUitOpen 2:dcaee06f6ccb 1102 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
MikamiUitOpen 2:dcaee06f6ccb 1104 #else
MikamiUitOpen 2:dcaee06f6ccb 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MikamiUitOpen 2:dcaee06f6ccb 1106 __regCPACR = cpacr;
MikamiUitOpen 2:dcaee06f6ccb 1107 #endif
MikamiUitOpen 2:dcaee06f6ccb 1108 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 1109 }
MikamiUitOpen 2:dcaee06f6ccb 1110
MikamiUitOpen 2:dcaee06f6ccb 1111 /** \brief Get CBAR
MikamiUitOpen 2:dcaee06f6ccb 1112
MikamiUitOpen 2:dcaee06f6ccb 1113 This function returns the value of the Configuration Base Address register.
MikamiUitOpen 2:dcaee06f6ccb 1114
MikamiUitOpen 2:dcaee06f6ccb 1115 \return Configuration Base Address register value
MikamiUitOpen 2:dcaee06f6ccb 1116 */
MikamiUitOpen 2:dcaee06f6ccb 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
MikamiUitOpen 2:dcaee06f6ccb 1118 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1119 register uint32_t __regCBAR;
MikamiUitOpen 2:dcaee06f6ccb 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
MikamiUitOpen 2:dcaee06f6ccb 1121 #else
MikamiUitOpen 2:dcaee06f6ccb 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 1123 #endif
MikamiUitOpen 2:dcaee06f6ccb 1124 return(__regCBAR);
MikamiUitOpen 2:dcaee06f6ccb 1125 }
MikamiUitOpen 2:dcaee06f6ccb 1126
MikamiUitOpen 2:dcaee06f6ccb 1127 /** \brief Get TTBR0
MikamiUitOpen 2:dcaee06f6ccb 1128
MikamiUitOpen 2:dcaee06f6ccb 1129 This function returns the value of the Translation Table Base Register 0.
MikamiUitOpen 2:dcaee06f6ccb 1130
MikamiUitOpen 2:dcaee06f6ccb 1131 \return Translation Table Base Register 0 value
MikamiUitOpen 2:dcaee06f6ccb 1132 */
MikamiUitOpen 2:dcaee06f6ccb 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
MikamiUitOpen 2:dcaee06f6ccb 1134 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1135 register uint32_t __regTTBR0;
MikamiUitOpen 2:dcaee06f6ccb 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
MikamiUitOpen 2:dcaee06f6ccb 1137 #else
MikamiUitOpen 2:dcaee06f6ccb 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 1139 #endif
MikamiUitOpen 2:dcaee06f6ccb 1140 return(__regTTBR0);
MikamiUitOpen 2:dcaee06f6ccb 1141 }
MikamiUitOpen 2:dcaee06f6ccb 1142
MikamiUitOpen 2:dcaee06f6ccb 1143 /** \brief Set TTBR0
MikamiUitOpen 2:dcaee06f6ccb 1144
MikamiUitOpen 2:dcaee06f6ccb 1145 This function assigns the given value to the Translation Table Base Register 0.
MikamiUitOpen 2:dcaee06f6ccb 1146
MikamiUitOpen 2:dcaee06f6ccb 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
MikamiUitOpen 2:dcaee06f6ccb 1148 */
MikamiUitOpen 2:dcaee06f6ccb 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
MikamiUitOpen 2:dcaee06f6ccb 1150 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
MikamiUitOpen 2:dcaee06f6ccb 1152 #else
MikamiUitOpen 2:dcaee06f6ccb 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 1154 __regTTBR0 = ttbr0;
MikamiUitOpen 2:dcaee06f6ccb 1155 #endif
MikamiUitOpen 2:dcaee06f6ccb 1156 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 1157 }
MikamiUitOpen 2:dcaee06f6ccb 1158
MikamiUitOpen 2:dcaee06f6ccb 1159 /** \brief Get DACR
MikamiUitOpen 2:dcaee06f6ccb 1160
MikamiUitOpen 2:dcaee06f6ccb 1161 This function returns the value of the Domain Access Control Register.
MikamiUitOpen 2:dcaee06f6ccb 1162
MikamiUitOpen 2:dcaee06f6ccb 1163 \return Domain Access Control Register value
MikamiUitOpen 2:dcaee06f6ccb 1164 */
MikamiUitOpen 2:dcaee06f6ccb 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
MikamiUitOpen 2:dcaee06f6ccb 1166 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1167 register uint32_t __regDACR;
MikamiUitOpen 2:dcaee06f6ccb 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
MikamiUitOpen 2:dcaee06f6ccb 1169 #else
MikamiUitOpen 2:dcaee06f6ccb 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 1171 #endif
MikamiUitOpen 2:dcaee06f6ccb 1172 return(__regDACR);
MikamiUitOpen 2:dcaee06f6ccb 1173 }
MikamiUitOpen 2:dcaee06f6ccb 1174
MikamiUitOpen 2:dcaee06f6ccb 1175 /** \brief Set DACR
MikamiUitOpen 2:dcaee06f6ccb 1176
MikamiUitOpen 2:dcaee06f6ccb 1177 This function assigns the given value to the Domain Access Control Register.
MikamiUitOpen 2:dcaee06f6ccb 1178
MikamiUitOpen 2:dcaee06f6ccb 1179 \param [in] dacr Domain Access Control Register value to set
MikamiUitOpen 2:dcaee06f6ccb 1180 */
MikamiUitOpen 2:dcaee06f6ccb 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
MikamiUitOpen 2:dcaee06f6ccb 1182 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
MikamiUitOpen 2:dcaee06f6ccb 1184 #else
MikamiUitOpen 2:dcaee06f6ccb 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 1186 __regDACR = dacr;
MikamiUitOpen 2:dcaee06f6ccb 1187 #endif
MikamiUitOpen 2:dcaee06f6ccb 1188 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 1189 }
MikamiUitOpen 2:dcaee06f6ccb 1190
MikamiUitOpen 2:dcaee06f6ccb 1191 /******************************** Cache and BTAC enable ****************************************************/
MikamiUitOpen 2:dcaee06f6ccb 1192
MikamiUitOpen 2:dcaee06f6ccb 1193 /** \brief Set SCTLR
MikamiUitOpen 2:dcaee06f6ccb 1194
MikamiUitOpen 2:dcaee06f6ccb 1195 This function assigns the given value to the System Control Register.
MikamiUitOpen 2:dcaee06f6ccb 1196
MikamiUitOpen 2:dcaee06f6ccb 1197 \param [in] sctlr System Control Register value to set
MikamiUitOpen 2:dcaee06f6ccb 1198 */
MikamiUitOpen 2:dcaee06f6ccb 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
MikamiUitOpen 2:dcaee06f6ccb 1200 {
MikamiUitOpen 2:dcaee06f6ccb 1201 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
MikamiUitOpen 2:dcaee06f6ccb 1203 #else
MikamiUitOpen 2:dcaee06f6ccb 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 1205 __regSCTLR = sctlr;
MikamiUitOpen 2:dcaee06f6ccb 1206 #endif
MikamiUitOpen 2:dcaee06f6ccb 1207 }
MikamiUitOpen 2:dcaee06f6ccb 1208
MikamiUitOpen 2:dcaee06f6ccb 1209 /** \brief Get SCTLR
MikamiUitOpen 2:dcaee06f6ccb 1210
MikamiUitOpen 2:dcaee06f6ccb 1211 This function returns the value of the System Control Register.
MikamiUitOpen 2:dcaee06f6ccb 1212
MikamiUitOpen 2:dcaee06f6ccb 1213 \return System Control Register value
MikamiUitOpen 2:dcaee06f6ccb 1214 */
MikamiUitOpen 2:dcaee06f6ccb 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
MikamiUitOpen 2:dcaee06f6ccb 1216 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1217 register uint32_t __regSCTLR;
MikamiUitOpen 2:dcaee06f6ccb 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
MikamiUitOpen 2:dcaee06f6ccb 1219 #else
MikamiUitOpen 2:dcaee06f6ccb 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MikamiUitOpen 2:dcaee06f6ccb 1221 #endif
MikamiUitOpen 2:dcaee06f6ccb 1222 return(__regSCTLR);
MikamiUitOpen 2:dcaee06f6ccb 1223 }
MikamiUitOpen 2:dcaee06f6ccb 1224
MikamiUitOpen 2:dcaee06f6ccb 1225 /** \brief Enable Caches
MikamiUitOpen 2:dcaee06f6ccb 1226
MikamiUitOpen 2:dcaee06f6ccb 1227 Enable Caches
MikamiUitOpen 2:dcaee06f6ccb 1228 */
MikamiUitOpen 2:dcaee06f6ccb 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
MikamiUitOpen 2:dcaee06f6ccb 1230 // Set I bit 12 to enable I Cache
MikamiUitOpen 2:dcaee06f6ccb 1231 // Set C bit 2 to enable D Cache
MikamiUitOpen 2:dcaee06f6ccb 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
MikamiUitOpen 2:dcaee06f6ccb 1233 }
MikamiUitOpen 2:dcaee06f6ccb 1234
MikamiUitOpen 2:dcaee06f6ccb 1235 /** \brief Disable Caches
MikamiUitOpen 2:dcaee06f6ccb 1236
MikamiUitOpen 2:dcaee06f6ccb 1237 Disable Caches
MikamiUitOpen 2:dcaee06f6ccb 1238 */
MikamiUitOpen 2:dcaee06f6ccb 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
MikamiUitOpen 2:dcaee06f6ccb 1240 // Clear I bit 12 to disable I Cache
MikamiUitOpen 2:dcaee06f6ccb 1241 // Clear C bit 2 to disable D Cache
MikamiUitOpen 2:dcaee06f6ccb 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
MikamiUitOpen 2:dcaee06f6ccb 1243 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 1244 }
MikamiUitOpen 2:dcaee06f6ccb 1245
MikamiUitOpen 2:dcaee06f6ccb 1246 /** \brief Enable BTAC
MikamiUitOpen 2:dcaee06f6ccb 1247
MikamiUitOpen 2:dcaee06f6ccb 1248 Enable BTAC
MikamiUitOpen 2:dcaee06f6ccb 1249 */
MikamiUitOpen 2:dcaee06f6ccb 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
MikamiUitOpen 2:dcaee06f6ccb 1251 // Set Z bit 11 to enable branch prediction
MikamiUitOpen 2:dcaee06f6ccb 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
MikamiUitOpen 2:dcaee06f6ccb 1253 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 1254 }
MikamiUitOpen 2:dcaee06f6ccb 1255
MikamiUitOpen 2:dcaee06f6ccb 1256 /** \brief Disable BTAC
MikamiUitOpen 2:dcaee06f6ccb 1257
MikamiUitOpen 2:dcaee06f6ccb 1258 Disable BTAC
MikamiUitOpen 2:dcaee06f6ccb 1259 */
MikamiUitOpen 2:dcaee06f6ccb 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
MikamiUitOpen 2:dcaee06f6ccb 1261 // Clear Z bit 11 to disable branch prediction
MikamiUitOpen 2:dcaee06f6ccb 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
MikamiUitOpen 2:dcaee06f6ccb 1263 }
MikamiUitOpen 2:dcaee06f6ccb 1264
MikamiUitOpen 2:dcaee06f6ccb 1265
MikamiUitOpen 2:dcaee06f6ccb 1266 /** \brief Enable MMU
MikamiUitOpen 2:dcaee06f6ccb 1267
MikamiUitOpen 2:dcaee06f6ccb 1268 Enable MMU
MikamiUitOpen 2:dcaee06f6ccb 1269 */
MikamiUitOpen 2:dcaee06f6ccb 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
MikamiUitOpen 2:dcaee06f6ccb 1271 // Set M bit 0 to enable the MMU
MikamiUitOpen 2:dcaee06f6ccb 1272 // Set AFE bit to enable simplified access permissions model
MikamiUitOpen 2:dcaee06f6ccb 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
MikamiUitOpen 2:dcaee06f6ccb 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
MikamiUitOpen 2:dcaee06f6ccb 1275 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 1276 }
MikamiUitOpen 2:dcaee06f6ccb 1277
MikamiUitOpen 2:dcaee06f6ccb 1278 /** \brief Disable MMU
MikamiUitOpen 2:dcaee06f6ccb 1279
MikamiUitOpen 2:dcaee06f6ccb 1280 Disable MMU
MikamiUitOpen 2:dcaee06f6ccb 1281 */
MikamiUitOpen 2:dcaee06f6ccb 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
MikamiUitOpen 2:dcaee06f6ccb 1283 // Clear M bit 0 to disable the MMU
MikamiUitOpen 2:dcaee06f6ccb 1284 __set_SCTLR( __get_SCTLR() & ~1);
MikamiUitOpen 2:dcaee06f6ccb 1285 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 1286 }
MikamiUitOpen 2:dcaee06f6ccb 1287
MikamiUitOpen 2:dcaee06f6ccb 1288 /******************************** TLB maintenance operations ************************************************/
MikamiUitOpen 2:dcaee06f6ccb 1289 /** \brief Invalidate the whole tlb
MikamiUitOpen 2:dcaee06f6ccb 1290
MikamiUitOpen 2:dcaee06f6ccb 1291 TLBIALL. Invalidate the whole tlb
MikamiUitOpen 2:dcaee06f6ccb 1292 */
MikamiUitOpen 2:dcaee06f6ccb 1293
MikamiUitOpen 2:dcaee06f6ccb 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 1295 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
MikamiUitOpen 2:dcaee06f6ccb 1297 #else
MikamiUitOpen 2:dcaee06f6ccb 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
MikamiUitOpen 2:dcaee06f6ccb 1299 __TLBIALL = 0;
MikamiUitOpen 2:dcaee06f6ccb 1300 #endif
MikamiUitOpen 2:dcaee06f6ccb 1301 __DSB();
MikamiUitOpen 2:dcaee06f6ccb 1302 __ISB();
MikamiUitOpen 2:dcaee06f6ccb 1303 }
MikamiUitOpen 2:dcaee06f6ccb 1304
MikamiUitOpen 2:dcaee06f6ccb 1305 /******************************** BTB maintenance operations ************************************************/
MikamiUitOpen 2:dcaee06f6ccb 1306 /** \brief Invalidate entire branch predictor array
MikamiUitOpen 2:dcaee06f6ccb 1307
MikamiUitOpen 2:dcaee06f6ccb 1308 BPIALL. Branch Predictor Invalidate All.
MikamiUitOpen 2:dcaee06f6ccb 1309 */
MikamiUitOpen 2:dcaee06f6ccb 1310
MikamiUitOpen 2:dcaee06f6ccb 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
MikamiUitOpen 2:dcaee06f6ccb 1312 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
MikamiUitOpen 2:dcaee06f6ccb 1314 #else
MikamiUitOpen 2:dcaee06f6ccb 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
MikamiUitOpen 2:dcaee06f6ccb 1316 __BPIALL = 0;
MikamiUitOpen 2:dcaee06f6ccb 1317 #endif
MikamiUitOpen 2:dcaee06f6ccb 1318 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 2:dcaee06f6ccb 1319 __ISB(); //ensure instruction fetch path sees new state
MikamiUitOpen 2:dcaee06f6ccb 1320 }
MikamiUitOpen 2:dcaee06f6ccb 1321
MikamiUitOpen 2:dcaee06f6ccb 1322
MikamiUitOpen 2:dcaee06f6ccb 1323 /******************************** L1 cache operations ******************************************************/
MikamiUitOpen 2:dcaee06f6ccb 1324
MikamiUitOpen 2:dcaee06f6ccb 1325 /** \brief Invalidate the whole I$
MikamiUitOpen 2:dcaee06f6ccb 1326
MikamiUitOpen 2:dcaee06f6ccb 1327 ICIALLU. Instruction Cache Invalidate All to PoU
MikamiUitOpen 2:dcaee06f6ccb 1328 */
MikamiUitOpen 2:dcaee06f6ccb 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 1330 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
MikamiUitOpen 2:dcaee06f6ccb 1332 #else
MikamiUitOpen 2:dcaee06f6ccb 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
MikamiUitOpen 2:dcaee06f6ccb 1334 __ICIALLU = 0;
MikamiUitOpen 2:dcaee06f6ccb 1335 #endif
MikamiUitOpen 2:dcaee06f6ccb 1336 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 2:dcaee06f6ccb 1337 __ISB(); //ensure instruction fetch path sees new I cache state
MikamiUitOpen 2:dcaee06f6ccb 1338 }
MikamiUitOpen 2:dcaee06f6ccb 1339
MikamiUitOpen 2:dcaee06f6ccb 1340 /** \brief Clean D$ by MVA
MikamiUitOpen 2:dcaee06f6ccb 1341
MikamiUitOpen 2:dcaee06f6ccb 1342 DCCMVAC. Data cache clean by MVA to PoC
MikamiUitOpen 2:dcaee06f6ccb 1343 */
MikamiUitOpen 2:dcaee06f6ccb 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
MikamiUitOpen 2:dcaee06f6ccb 1345 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
MikamiUitOpen 2:dcaee06f6ccb 1347 #else
MikamiUitOpen 2:dcaee06f6ccb 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
MikamiUitOpen 2:dcaee06f6ccb 1349 __DCCMVAC = (uint32_t)va;
MikamiUitOpen 2:dcaee06f6ccb 1350 #endif
MikamiUitOpen 2:dcaee06f6ccb 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 2:dcaee06f6ccb 1352 }
MikamiUitOpen 2:dcaee06f6ccb 1353
MikamiUitOpen 2:dcaee06f6ccb 1354 /** \brief Invalidate D$ by MVA
MikamiUitOpen 2:dcaee06f6ccb 1355
MikamiUitOpen 2:dcaee06f6ccb 1356 DCIMVAC. Data cache invalidate by MVA to PoC
MikamiUitOpen 2:dcaee06f6ccb 1357 */
MikamiUitOpen 2:dcaee06f6ccb 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
MikamiUitOpen 2:dcaee06f6ccb 1359 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
MikamiUitOpen 2:dcaee06f6ccb 1361 #else
MikamiUitOpen 2:dcaee06f6ccb 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
MikamiUitOpen 2:dcaee06f6ccb 1363 __DCIMVAC = (uint32_t)va;
MikamiUitOpen 2:dcaee06f6ccb 1364 #endif
MikamiUitOpen 2:dcaee06f6ccb 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 2:dcaee06f6ccb 1366 }
MikamiUitOpen 2:dcaee06f6ccb 1367
MikamiUitOpen 2:dcaee06f6ccb 1368 /** \brief Clean and Invalidate D$ by MVA
MikamiUitOpen 2:dcaee06f6ccb 1369
MikamiUitOpen 2:dcaee06f6ccb 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
MikamiUitOpen 2:dcaee06f6ccb 1371 */
MikamiUitOpen 2:dcaee06f6ccb 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
MikamiUitOpen 2:dcaee06f6ccb 1373 #if 1
MikamiUitOpen 2:dcaee06f6ccb 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
MikamiUitOpen 2:dcaee06f6ccb 1375 #else
MikamiUitOpen 2:dcaee06f6ccb 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
MikamiUitOpen 2:dcaee06f6ccb 1377 __DCCIMVAC = (uint32_t)va;
MikamiUitOpen 2:dcaee06f6ccb 1378 #endif
MikamiUitOpen 2:dcaee06f6ccb 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 2:dcaee06f6ccb 1380 }
MikamiUitOpen 2:dcaee06f6ccb 1381
MikamiUitOpen 2:dcaee06f6ccb 1382 /** \brief Clean and Invalidate the entire data or unified cache
MikamiUitOpen 2:dcaee06f6ccb 1383
MikamiUitOpen 2:dcaee06f6ccb 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
MikamiUitOpen 2:dcaee06f6ccb 1385 */
MikamiUitOpen 2:dcaee06f6ccb 1386 extern void __v7_all_cache(uint32_t op);
MikamiUitOpen 2:dcaee06f6ccb 1387
MikamiUitOpen 2:dcaee06f6ccb 1388
MikamiUitOpen 2:dcaee06f6ccb 1389 /** \brief Invalidate the whole D$
MikamiUitOpen 2:dcaee06f6ccb 1390
MikamiUitOpen 2:dcaee06f6ccb 1391 DCISW. Invalidate by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 1392 */
MikamiUitOpen 2:dcaee06f6ccb 1393
MikamiUitOpen 2:dcaee06f6ccb 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 1395 __v7_all_cache(0);
MikamiUitOpen 2:dcaee06f6ccb 1396 }
MikamiUitOpen 2:dcaee06f6ccb 1397
MikamiUitOpen 2:dcaee06f6ccb 1398 /** \brief Clean the whole D$
MikamiUitOpen 2:dcaee06f6ccb 1399
MikamiUitOpen 2:dcaee06f6ccb 1400 DCCSW. Clean by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 1401 */
MikamiUitOpen 2:dcaee06f6ccb 1402
MikamiUitOpen 2:dcaee06f6ccb 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 1404 __v7_all_cache(1);
MikamiUitOpen 2:dcaee06f6ccb 1405 }
MikamiUitOpen 2:dcaee06f6ccb 1406
MikamiUitOpen 2:dcaee06f6ccb 1407 /** \brief Clean and invalidate the whole D$
MikamiUitOpen 2:dcaee06f6ccb 1408
MikamiUitOpen 2:dcaee06f6ccb 1409 DCCISW. Clean and Invalidate by Set/Way
MikamiUitOpen 2:dcaee06f6ccb 1410 */
MikamiUitOpen 2:dcaee06f6ccb 1411
MikamiUitOpen 2:dcaee06f6ccb 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
MikamiUitOpen 2:dcaee06f6ccb 1413 __v7_all_cache(2);
MikamiUitOpen 2:dcaee06f6ccb 1414 }
MikamiUitOpen 2:dcaee06f6ccb 1415
MikamiUitOpen 2:dcaee06f6ccb 1416 #include "core_ca_mmu.h"
MikamiUitOpen 2:dcaee06f6ccb 1417
MikamiUitOpen 2:dcaee06f6ccb 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
MikamiUitOpen 2:dcaee06f6ccb 1419
MikamiUitOpen 2:dcaee06f6ccb 1420 #error TASKING Compiler support not implemented for Cortex-A
MikamiUitOpen 2:dcaee06f6ccb 1421
MikamiUitOpen 2:dcaee06f6ccb 1422 #endif
MikamiUitOpen 2:dcaee06f6ccb 1423
MikamiUitOpen 2:dcaee06f6ccb 1424 /*@} end of CMSIS_Core_RegAccFunctions */
MikamiUitOpen 2:dcaee06f6ccb 1425
MikamiUitOpen 2:dcaee06f6ccb 1426
MikamiUitOpen 2:dcaee06f6ccb 1427 #endif /* __CORE_CAFUNC_H__ */