不韋 呂 / F746_SD_VarableFilter

SD card player with variable cotoff frequency lowpass and highpass IIR filter. SD カードの *.wav ファイルのオーディオ信号を，遮断周波数可変 IIR 低域通過および高域通過フィルタを通して，ボードに搭載されているCODEC で出力する．このプログラムについては，CQ出版社インターフェース誌 2018年8月号で解説している．

Dependencies:   F746_GUI F746_SAI_IO FrequencyResponseDrawer SD_PlayerSkeleton

mbed_src_STM32F7/targets/cmsis/core_ca9.h@11:399670d24ed9, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 01:44:22 2017 +0000
Revision:
11:399670d24ed9
Parent:
2:dcaee06f6ccb 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 2:dcaee06f6ccb 1 /**************************************************************************//**
MikamiUitOpen 2:dcaee06f6ccb 2 * @file core_ca9.h
MikamiUitOpen 2:dcaee06f6ccb 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
MikamiUitOpen 2:dcaee06f6ccb 4 * @version
MikamiUitOpen 2:dcaee06f6ccb 5 * @date 25 March 2013
MikamiUitOpen 2:dcaee06f6ccb 6 *
MikamiUitOpen 2:dcaee06f6ccb 7 * @note
MikamiUitOpen 2:dcaee06f6ccb 8 *
MikamiUitOpen 2:dcaee06f6ccb 9 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
MikamiUitOpen 2:dcaee06f6ccb 11
MikamiUitOpen 2:dcaee06f6ccb 12 All rights reserved.
MikamiUitOpen 2:dcaee06f6ccb 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 2:dcaee06f6ccb 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 2:dcaee06f6ccb 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 2:dcaee06f6ccb 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 2:dcaee06f6ccb 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 2:dcaee06f6ccb 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 2:dcaee06f6ccb 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 2:dcaee06f6ccb 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 2:dcaee06f6ccb 21 to endorse or promote products derived from this software without
MikamiUitOpen 2:dcaee06f6ccb 22 specific prior written permission.
MikamiUitOpen 2:dcaee06f6ccb 23 *
MikamiUitOpen 2:dcaee06f6ccb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 2:dcaee06f6ccb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 2:dcaee06f6ccb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 2:dcaee06f6ccb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 2:dcaee06f6ccb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 2:dcaee06f6ccb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 2:dcaee06f6ccb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 2:dcaee06f6ccb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 2:dcaee06f6ccb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 2:dcaee06f6ccb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 2:dcaee06f6ccb 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 2:dcaee06f6ccb 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 2:dcaee06f6ccb 36
MikamiUitOpen 2:dcaee06f6ccb 37
MikamiUitOpen 2:dcaee06f6ccb 38 #if defined ( __ICCARM__ )
MikamiUitOpen 2:dcaee06f6ccb 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 2:dcaee06f6ccb 40 #endif
MikamiUitOpen 2:dcaee06f6ccb 41
MikamiUitOpen 2:dcaee06f6ccb 42 #ifdef __cplusplus
MikamiUitOpen 2:dcaee06f6ccb 43 extern "C" {
MikamiUitOpen 2:dcaee06f6ccb 44 #endif
MikamiUitOpen 2:dcaee06f6ccb 45
MikamiUitOpen 2:dcaee06f6ccb 46 #ifndef __CORE_CA9_H_GENERIC
MikamiUitOpen 2:dcaee06f6ccb 47 #define __CORE_CA9_H_GENERIC
MikamiUitOpen 2:dcaee06f6ccb 48
MikamiUitOpen 2:dcaee06f6ccb 49
MikamiUitOpen 2:dcaee06f6ccb 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen 2:dcaee06f6ccb 51 CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen 2:dcaee06f6ccb 52
MikamiUitOpen 2:dcaee06f6ccb 53 \li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen 2:dcaee06f6ccb 54 Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen 2:dcaee06f6ccb 55
MikamiUitOpen 2:dcaee06f6ccb 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen 2:dcaee06f6ccb 57 Unions are used for effective representation of core registers.
MikamiUitOpen 2:dcaee06f6ccb 58
MikamiUitOpen 2:dcaee06f6ccb 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen 2:dcaee06f6ccb 60 Function-like macros are used to allow more efficient code.
MikamiUitOpen 2:dcaee06f6ccb 61 */
MikamiUitOpen 2:dcaee06f6ccb 62
MikamiUitOpen 2:dcaee06f6ccb 63
MikamiUitOpen 2:dcaee06f6ccb 64 /*******************************************************************************
MikamiUitOpen 2:dcaee06f6ccb 65 * CMSIS definitions
MikamiUitOpen 2:dcaee06f6ccb 66 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 67 /** \ingroup Cortex_A9
MikamiUitOpen 2:dcaee06f6ccb 68 @{
MikamiUitOpen 2:dcaee06f6ccb 69 */
MikamiUitOpen 2:dcaee06f6ccb 70
MikamiUitOpen 2:dcaee06f6ccb 71 /* CMSIS CA9 definitions */
MikamiUitOpen 2:dcaee06f6ccb 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
MikamiUitOpen 2:dcaee06f6ccb 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
MikamiUitOpen 2:dcaee06f6ccb 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
MikamiUitOpen 2:dcaee06f6ccb 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
MikamiUitOpen 2:dcaee06f6ccb 76
MikamiUitOpen 2:dcaee06f6ccb 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
MikamiUitOpen 2:dcaee06f6ccb 78
MikamiUitOpen 2:dcaee06f6ccb 79
MikamiUitOpen 2:dcaee06f6ccb 80 #if defined ( __CC_ARM )
MikamiUitOpen 2:dcaee06f6ccb 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
MikamiUitOpen 2:dcaee06f6ccb 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
MikamiUitOpen 2:dcaee06f6ccb 83 #define __STATIC_INLINE static __inline
MikamiUitOpen 2:dcaee06f6ccb 84 #define __STATIC_ASM static __asm
MikamiUitOpen 2:dcaee06f6ccb 85
MikamiUitOpen 2:dcaee06f6ccb 86 #elif defined ( __ICCARM__ )
MikamiUitOpen 2:dcaee06f6ccb 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
MikamiUitOpen 2:dcaee06f6ccb 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
MikamiUitOpen 2:dcaee06f6ccb 89 #define __STATIC_INLINE static inline
MikamiUitOpen 2:dcaee06f6ccb 90 #define __STATIC_ASM static __asm
MikamiUitOpen 2:dcaee06f6ccb 91
MikamiUitOpen 2:dcaee06f6ccb 92 #include <stdint.h>
MikamiUitOpen 2:dcaee06f6ccb 93 inline uint32_t __get_PSR(void) {
MikamiUitOpen 2:dcaee06f6ccb 94 __ASM("mrs r0, cpsr");
MikamiUitOpen 2:dcaee06f6ccb 95 }
MikamiUitOpen 2:dcaee06f6ccb 96
MikamiUitOpen 2:dcaee06f6ccb 97 #elif defined ( __TMS470__ )
MikamiUitOpen 2:dcaee06f6ccb 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
MikamiUitOpen 2:dcaee06f6ccb 99 #define __STATIC_INLINE static inline
MikamiUitOpen 2:dcaee06f6ccb 100 #define __STATIC_ASM static __asm
MikamiUitOpen 2:dcaee06f6ccb 101
MikamiUitOpen 2:dcaee06f6ccb 102 #elif defined ( __GNUC__ )
MikamiUitOpen 2:dcaee06f6ccb 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
MikamiUitOpen 2:dcaee06f6ccb 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
MikamiUitOpen 2:dcaee06f6ccb 105 #define __STATIC_INLINE static inline
MikamiUitOpen 2:dcaee06f6ccb 106 #define __STATIC_ASM static __asm
MikamiUitOpen 2:dcaee06f6ccb 107
MikamiUitOpen 2:dcaee06f6ccb 108 #elif defined ( __TASKING__ )
MikamiUitOpen 2:dcaee06f6ccb 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
MikamiUitOpen 2:dcaee06f6ccb 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
MikamiUitOpen 2:dcaee06f6ccb 111 #define __STATIC_INLINE static inline
MikamiUitOpen 2:dcaee06f6ccb 112 #define __STATIC_ASM static __asm
MikamiUitOpen 2:dcaee06f6ccb 113
MikamiUitOpen 2:dcaee06f6ccb 114 #endif
MikamiUitOpen 2:dcaee06f6ccb 115
MikamiUitOpen 2:dcaee06f6ccb 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
MikamiUitOpen 2:dcaee06f6ccb 117 */
MikamiUitOpen 2:dcaee06f6ccb 118 #if defined ( __CC_ARM )
MikamiUitOpen 2:dcaee06f6ccb 119 #if defined __TARGET_FPU_VFP
MikamiUitOpen 2:dcaee06f6ccb 120 #if (__FPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 121 #define __FPU_USED 1
MikamiUitOpen 2:dcaee06f6ccb 122 #else
MikamiUitOpen 2:dcaee06f6ccb 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 124 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 125 #endif
MikamiUitOpen 2:dcaee06f6ccb 126 #else
MikamiUitOpen 2:dcaee06f6ccb 127 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 128 #endif
MikamiUitOpen 2:dcaee06f6ccb 129
MikamiUitOpen 2:dcaee06f6ccb 130 #elif defined ( __ICCARM__ )
MikamiUitOpen 2:dcaee06f6ccb 131 #if defined __ARMVFP__
MikamiUitOpen 2:dcaee06f6ccb 132 #if (__FPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 133 #define __FPU_USED 1
MikamiUitOpen 2:dcaee06f6ccb 134 #else
MikamiUitOpen 2:dcaee06f6ccb 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 136 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 137 #endif
MikamiUitOpen 2:dcaee06f6ccb 138 #else
MikamiUitOpen 2:dcaee06f6ccb 139 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 140 #endif
MikamiUitOpen 2:dcaee06f6ccb 141
MikamiUitOpen 2:dcaee06f6ccb 142 #elif defined ( __TMS470__ )
MikamiUitOpen 2:dcaee06f6ccb 143 #if defined __TI_VFP_SUPPORT__
MikamiUitOpen 2:dcaee06f6ccb 144 #if (__FPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 145 #define __FPU_USED 1
MikamiUitOpen 2:dcaee06f6ccb 146 #else
MikamiUitOpen 2:dcaee06f6ccb 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 148 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 149 #endif
MikamiUitOpen 2:dcaee06f6ccb 150 #else
MikamiUitOpen 2:dcaee06f6ccb 151 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 152 #endif
MikamiUitOpen 2:dcaee06f6ccb 153
MikamiUitOpen 2:dcaee06f6ccb 154 #elif defined ( __GNUC__ )
MikamiUitOpen 2:dcaee06f6ccb 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen 2:dcaee06f6ccb 156 #if (__FPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 157 #define __FPU_USED 1
MikamiUitOpen 2:dcaee06f6ccb 158 #else
MikamiUitOpen 2:dcaee06f6ccb 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 160 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 161 #endif
MikamiUitOpen 2:dcaee06f6ccb 162 #else
MikamiUitOpen 2:dcaee06f6ccb 163 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 164 #endif
MikamiUitOpen 2:dcaee06f6ccb 165
MikamiUitOpen 2:dcaee06f6ccb 166 #elif defined ( __TASKING__ )
MikamiUitOpen 2:dcaee06f6ccb 167 #if defined __FPU_VFP__
MikamiUitOpen 2:dcaee06f6ccb 168 #if (__FPU_PRESENT == 1)
MikamiUitOpen 2:dcaee06f6ccb 169 #define __FPU_USED 1
MikamiUitOpen 2:dcaee06f6ccb 170 #else
MikamiUitOpen 2:dcaee06f6ccb 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 2:dcaee06f6ccb 172 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 173 #endif
MikamiUitOpen 2:dcaee06f6ccb 174 #else
MikamiUitOpen 2:dcaee06f6ccb 175 #define __FPU_USED 0
MikamiUitOpen 2:dcaee06f6ccb 176 #endif
MikamiUitOpen 2:dcaee06f6ccb 177 #endif
MikamiUitOpen 2:dcaee06f6ccb 178
MikamiUitOpen 2:dcaee06f6ccb 179 #include <stdint.h> /*!< standard types definitions */
MikamiUitOpen 2:dcaee06f6ccb 180 #include "core_caInstr.h" /*!< Core Instruction Access */
MikamiUitOpen 2:dcaee06f6ccb 181 #include "core_caFunc.h" /*!< Core Function Access */
MikamiUitOpen 2:dcaee06f6ccb 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
MikamiUitOpen 2:dcaee06f6ccb 183
MikamiUitOpen 2:dcaee06f6ccb 184 #endif /* __CORE_CA9_H_GENERIC */
MikamiUitOpen 2:dcaee06f6ccb 185
MikamiUitOpen 2:dcaee06f6ccb 186 #ifndef __CMSIS_GENERIC
MikamiUitOpen 2:dcaee06f6ccb 187
MikamiUitOpen 2:dcaee06f6ccb 188 #ifndef __CORE_CA9_H_DEPENDANT
MikamiUitOpen 2:dcaee06f6ccb 189 #define __CORE_CA9_H_DEPENDANT
MikamiUitOpen 2:dcaee06f6ccb 190
MikamiUitOpen 2:dcaee06f6ccb 191 /* check device defines and use defaults */
MikamiUitOpen 2:dcaee06f6ccb 192 #if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen 2:dcaee06f6ccb 193 #ifndef __CA9_REV
MikamiUitOpen 2:dcaee06f6ccb 194 #define __CA9_REV 0x0000
MikamiUitOpen 2:dcaee06f6ccb 195 #warning "__CA9_REV not defined in device header file; using default!"
MikamiUitOpen 2:dcaee06f6ccb 196 #endif
MikamiUitOpen 2:dcaee06f6ccb 197
MikamiUitOpen 2:dcaee06f6ccb 198 #ifndef __FPU_PRESENT
MikamiUitOpen 2:dcaee06f6ccb 199 #define __FPU_PRESENT 1
MikamiUitOpen 2:dcaee06f6ccb 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen 2:dcaee06f6ccb 201 #endif
MikamiUitOpen 2:dcaee06f6ccb 202
MikamiUitOpen 2:dcaee06f6ccb 203 #ifndef __Vendor_SysTickConfig
MikamiUitOpen 2:dcaee06f6ccb 204 #define __Vendor_SysTickConfig 1
MikamiUitOpen 2:dcaee06f6ccb 205 #endif
MikamiUitOpen 2:dcaee06f6ccb 206
MikamiUitOpen 2:dcaee06f6ccb 207 #if __Vendor_SysTickConfig == 0
MikamiUitOpen 2:dcaee06f6ccb 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
MikamiUitOpen 2:dcaee06f6ccb 209 #endif
MikamiUitOpen 2:dcaee06f6ccb 210 #endif
MikamiUitOpen 2:dcaee06f6ccb 211
MikamiUitOpen 2:dcaee06f6ccb 212 /* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen 2:dcaee06f6ccb 213 /**
MikamiUitOpen 2:dcaee06f6ccb 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen 2:dcaee06f6ccb 215
MikamiUitOpen 2:dcaee06f6ccb 216 <strong>IO Type Qualifiers</strong> are used
MikamiUitOpen 2:dcaee06f6ccb 217 \li to specify the access to peripheral variables.
MikamiUitOpen 2:dcaee06f6ccb 218 \li for automatic generation of peripheral register debug information.
MikamiUitOpen 2:dcaee06f6ccb 219 */
MikamiUitOpen 2:dcaee06f6ccb 220 #ifdef __cplusplus
MikamiUitOpen 2:dcaee06f6ccb 221 #define __I volatile /*!< Defines 'read only' permissions */
MikamiUitOpen 2:dcaee06f6ccb 222 #else
MikamiUitOpen 2:dcaee06f6ccb 223 #define __I volatile const /*!< Defines 'read only' permissions */
MikamiUitOpen 2:dcaee06f6ccb 224 #endif
MikamiUitOpen 2:dcaee06f6ccb 225 #define __O volatile /*!< Defines 'write only' permissions */
MikamiUitOpen 2:dcaee06f6ccb 226 #define __IO volatile /*!< Defines 'read / write' permissions */
MikamiUitOpen 2:dcaee06f6ccb 227
MikamiUitOpen 2:dcaee06f6ccb 228 /*@} end of group Cortex_A9 */
MikamiUitOpen 2:dcaee06f6ccb 229
MikamiUitOpen 2:dcaee06f6ccb 230
MikamiUitOpen 2:dcaee06f6ccb 231 /*******************************************************************************
MikamiUitOpen 2:dcaee06f6ccb 232 * Register Abstraction
MikamiUitOpen 2:dcaee06f6ccb 233 ******************************************************************************/
MikamiUitOpen 2:dcaee06f6ccb 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen 2:dcaee06f6ccb 235 \brief Type definitions and defines for Cortex-A processor based devices.
MikamiUitOpen 2:dcaee06f6ccb 236 */
MikamiUitOpen 2:dcaee06f6ccb 237
MikamiUitOpen 2:dcaee06f6ccb 238 /** \ingroup CMSIS_core_register
MikamiUitOpen 2:dcaee06f6ccb 239 \defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen 2:dcaee06f6ccb 240 \brief Core Register type definitions.
MikamiUitOpen 2:dcaee06f6ccb 241 @{
MikamiUitOpen 2:dcaee06f6ccb 242 */
MikamiUitOpen 2:dcaee06f6ccb 243
MikamiUitOpen 2:dcaee06f6ccb 244 /** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen 2:dcaee06f6ccb 245 */
MikamiUitOpen 2:dcaee06f6ccb 246 typedef union
MikamiUitOpen 2:dcaee06f6ccb 247 {
MikamiUitOpen 2:dcaee06f6ccb 248 struct
MikamiUitOpen 2:dcaee06f6ccb 249 {
MikamiUitOpen 2:dcaee06f6ccb 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
MikamiUitOpen 2:dcaee06f6ccb 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
MikamiUitOpen 2:dcaee06f6ccb 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
MikamiUitOpen 2:dcaee06f6ccb 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
MikamiUitOpen 2:dcaee06f6ccb 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 2:dcaee06f6ccb 258 } b; /*!< Structure used for bit access */
MikamiUitOpen 2:dcaee06f6ccb 259 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 2:dcaee06f6ccb 260 } APSR_Type;
MikamiUitOpen 2:dcaee06f6ccb 261
MikamiUitOpen 2:dcaee06f6ccb 262
MikamiUitOpen 2:dcaee06f6ccb 263 /*@} end of group CMSIS_CORE */
MikamiUitOpen 2:dcaee06f6ccb 264
MikamiUitOpen 2:dcaee06f6ccb 265 /*@} end of CMSIS_Core_FPUFunctions */
MikamiUitOpen 2:dcaee06f6ccb 266
MikamiUitOpen 2:dcaee06f6ccb 267
MikamiUitOpen 2:dcaee06f6ccb 268 #endif /* __CORE_CA9_H_GENERIC */
MikamiUitOpen 2:dcaee06f6ccb 269
MikamiUitOpen 2:dcaee06f6ccb 270 #endif /* __CMSIS_GENERIC */
MikamiUitOpen 2:dcaee06f6ccb 271
MikamiUitOpen 2:dcaee06f6ccb 272 #ifdef __cplusplus
MikamiUitOpen 2:dcaee06f6ccb 273 }
MikamiUitOpen 2:dcaee06f6ccb 274
MikamiUitOpen 2:dcaee06f6ccb 275
MikamiUitOpen 2:dcaee06f6ccb 276 #endif