不韋 呂 / F746_SD_GraphicEqualizer

Output the audio signal with filtering by graphic equalizer in the *.wav file on the SD card using onboard CODEC. SD カードの *.wav ファイルのオーディオ信号をグラフィック･イコライザを通して，ボードに搭載されているCODEC で出力する．

Dependencies:   F746_GUI F746_SAI_IO SD_PlayerSkeleton FrequencyResponseDrawer

mbed_src_STM32F7/targets/cmsis/core_cmFunc.h@24:f78f9d0ac262, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 04:07:35 2017 +0000
Revision:
24:f78f9d0ac262
Parent:
16:cbb726ac20d8 
25

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 16:cbb726ac20d8 1 /**************************************************************************//**
MikamiUitOpen 16:cbb726ac20d8 2 * @file core_cmFunc.h
MikamiUitOpen 16:cbb726ac20d8 3 * @brief CMSIS Cortex-M Core Function Access Header File
MikamiUitOpen 16:cbb726ac20d8 4 * @version V4.10
MikamiUitOpen 16:cbb726ac20d8 5 * @date 18. March 2015
MikamiUitOpen 16:cbb726ac20d8 6 *
MikamiUitOpen 16:cbb726ac20d8 7 * @note
MikamiUitOpen 16:cbb726ac20d8 8 *
MikamiUitOpen 16:cbb726ac20d8 9 ******************************************************************************/
MikamiUitOpen 16:cbb726ac20d8 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 16:cbb726ac20d8 11
MikamiUitOpen 16:cbb726ac20d8 12 All rights reserved.
MikamiUitOpen 16:cbb726ac20d8 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 16:cbb726ac20d8 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 16:cbb726ac20d8 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 16:cbb726ac20d8 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 16:cbb726ac20d8 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 16:cbb726ac20d8 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 16:cbb726ac20d8 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 16:cbb726ac20d8 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 16:cbb726ac20d8 21 to endorse or promote products derived from this software without
MikamiUitOpen 16:cbb726ac20d8 22 specific prior written permission.
MikamiUitOpen 16:cbb726ac20d8 23 *
MikamiUitOpen 16:cbb726ac20d8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 16:cbb726ac20d8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 16:cbb726ac20d8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 16:cbb726ac20d8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 16:cbb726ac20d8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 16:cbb726ac20d8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 16:cbb726ac20d8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 16:cbb726ac20d8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 16:cbb726ac20d8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 16:cbb726ac20d8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 16:cbb726ac20d8 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 16:cbb726ac20d8 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 36
MikamiUitOpen 16:cbb726ac20d8 37
MikamiUitOpen 16:cbb726ac20d8 38 #ifndef __CORE_CMFUNC_H
MikamiUitOpen 16:cbb726ac20d8 39 #define __CORE_CMFUNC_H
MikamiUitOpen 16:cbb726ac20d8 40
MikamiUitOpen 16:cbb726ac20d8 41
MikamiUitOpen 16:cbb726ac20d8 42 /* ########################### Core Function Access ########################### */
MikamiUitOpen 16:cbb726ac20d8 43 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 16:cbb726ac20d8 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
MikamiUitOpen 16:cbb726ac20d8 45 @{
MikamiUitOpen 16:cbb726ac20d8 46 */
MikamiUitOpen 16:cbb726ac20d8 47
MikamiUitOpen 16:cbb726ac20d8 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 16:cbb726ac20d8 49 /* ARM armcc specific functions */
MikamiUitOpen 16:cbb726ac20d8 50
MikamiUitOpen 16:cbb726ac20d8 51 #if (__ARMCC_VERSION < 400677)
MikamiUitOpen 16:cbb726ac20d8 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MikamiUitOpen 16:cbb726ac20d8 53 #endif
MikamiUitOpen 16:cbb726ac20d8 54
MikamiUitOpen 16:cbb726ac20d8 55 /* intrinsic void __enable_irq(); */
MikamiUitOpen 16:cbb726ac20d8 56 /* intrinsic void __disable_irq(); */
MikamiUitOpen 16:cbb726ac20d8 57
MikamiUitOpen 16:cbb726ac20d8 58 /** \brief Get Control Register
MikamiUitOpen 16:cbb726ac20d8 59
MikamiUitOpen 16:cbb726ac20d8 60 This function returns the content of the Control Register.
MikamiUitOpen 16:cbb726ac20d8 61
MikamiUitOpen 16:cbb726ac20d8 62 \return Control Register value
MikamiUitOpen 16:cbb726ac20d8 63 */
MikamiUitOpen 16:cbb726ac20d8 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
MikamiUitOpen 16:cbb726ac20d8 65 {
MikamiUitOpen 16:cbb726ac20d8 66 register uint32_t __regControl __ASM("control");
MikamiUitOpen 16:cbb726ac20d8 67 return(__regControl);
MikamiUitOpen 16:cbb726ac20d8 68 }
MikamiUitOpen 16:cbb726ac20d8 69
MikamiUitOpen 16:cbb726ac20d8 70
MikamiUitOpen 16:cbb726ac20d8 71 /** \brief Set Control Register
MikamiUitOpen 16:cbb726ac20d8 72
MikamiUitOpen 16:cbb726ac20d8 73 This function writes the given value to the Control Register.
MikamiUitOpen 16:cbb726ac20d8 74
MikamiUitOpen 16:cbb726ac20d8 75 \param [in] control Control Register value to set
MikamiUitOpen 16:cbb726ac20d8 76 */
MikamiUitOpen 16:cbb726ac20d8 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
MikamiUitOpen 16:cbb726ac20d8 78 {
MikamiUitOpen 16:cbb726ac20d8 79 register uint32_t __regControl __ASM("control");
MikamiUitOpen 16:cbb726ac20d8 80 __regControl = control;
MikamiUitOpen 16:cbb726ac20d8 81 }
MikamiUitOpen 16:cbb726ac20d8 82
MikamiUitOpen 16:cbb726ac20d8 83
MikamiUitOpen 16:cbb726ac20d8 84 /** \brief Get IPSR Register
MikamiUitOpen 16:cbb726ac20d8 85
MikamiUitOpen 16:cbb726ac20d8 86 This function returns the content of the IPSR Register.
MikamiUitOpen 16:cbb726ac20d8 87
MikamiUitOpen 16:cbb726ac20d8 88 \return IPSR Register value
MikamiUitOpen 16:cbb726ac20d8 89 */
MikamiUitOpen 16:cbb726ac20d8 90 __STATIC_INLINE uint32_t __get_IPSR(void)
MikamiUitOpen 16:cbb726ac20d8 91 {
MikamiUitOpen 16:cbb726ac20d8 92 register uint32_t __regIPSR __ASM("ipsr");
MikamiUitOpen 16:cbb726ac20d8 93 return(__regIPSR);
MikamiUitOpen 16:cbb726ac20d8 94 }
MikamiUitOpen 16:cbb726ac20d8 95
MikamiUitOpen 16:cbb726ac20d8 96
MikamiUitOpen 16:cbb726ac20d8 97 /** \brief Get APSR Register
MikamiUitOpen 16:cbb726ac20d8 98
MikamiUitOpen 16:cbb726ac20d8 99 This function returns the content of the APSR Register.
MikamiUitOpen 16:cbb726ac20d8 100
MikamiUitOpen 16:cbb726ac20d8 101 \return APSR Register value
MikamiUitOpen 16:cbb726ac20d8 102 */
MikamiUitOpen 16:cbb726ac20d8 103 __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 16:cbb726ac20d8 104 {
MikamiUitOpen 16:cbb726ac20d8 105 register uint32_t __regAPSR __ASM("apsr");
MikamiUitOpen 16:cbb726ac20d8 106 return(__regAPSR);
MikamiUitOpen 16:cbb726ac20d8 107 }
MikamiUitOpen 16:cbb726ac20d8 108
MikamiUitOpen 16:cbb726ac20d8 109
MikamiUitOpen 16:cbb726ac20d8 110 /** \brief Get xPSR Register
MikamiUitOpen 16:cbb726ac20d8 111
MikamiUitOpen 16:cbb726ac20d8 112 This function returns the content of the xPSR Register.
MikamiUitOpen 16:cbb726ac20d8 113
MikamiUitOpen 16:cbb726ac20d8 114 \return xPSR Register value
MikamiUitOpen 16:cbb726ac20d8 115 */
MikamiUitOpen 16:cbb726ac20d8 116 __STATIC_INLINE uint32_t __get_xPSR(void)
MikamiUitOpen 16:cbb726ac20d8 117 {
MikamiUitOpen 16:cbb726ac20d8 118 register uint32_t __regXPSR __ASM("xpsr");
MikamiUitOpen 16:cbb726ac20d8 119 return(__regXPSR);
MikamiUitOpen 16:cbb726ac20d8 120 }
MikamiUitOpen 16:cbb726ac20d8 121
MikamiUitOpen 16:cbb726ac20d8 122
MikamiUitOpen 16:cbb726ac20d8 123 /** \brief Get Process Stack Pointer
MikamiUitOpen 16:cbb726ac20d8 124
MikamiUitOpen 16:cbb726ac20d8 125 This function returns the current value of the Process Stack Pointer (PSP).
MikamiUitOpen 16:cbb726ac20d8 126
MikamiUitOpen 16:cbb726ac20d8 127 \return PSP Register value
MikamiUitOpen 16:cbb726ac20d8 128 */
MikamiUitOpen 16:cbb726ac20d8 129 __STATIC_INLINE uint32_t __get_PSP(void)
MikamiUitOpen 16:cbb726ac20d8 130 {
MikamiUitOpen 16:cbb726ac20d8 131 register uint32_t __regProcessStackPointer __ASM("psp");
MikamiUitOpen 16:cbb726ac20d8 132 return(__regProcessStackPointer);
MikamiUitOpen 16:cbb726ac20d8 133 }
MikamiUitOpen 16:cbb726ac20d8 134
MikamiUitOpen 16:cbb726ac20d8 135
MikamiUitOpen 16:cbb726ac20d8 136 /** \brief Set Process Stack Pointer
MikamiUitOpen 16:cbb726ac20d8 137
MikamiUitOpen 16:cbb726ac20d8 138 This function assigns the given value to the Process Stack Pointer (PSP).
MikamiUitOpen 16:cbb726ac20d8 139
MikamiUitOpen 16:cbb726ac20d8 140 \param [in] topOfProcStack Process Stack Pointer value to set
MikamiUitOpen 16:cbb726ac20d8 141 */
MikamiUitOpen 16:cbb726ac20d8 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 16:cbb726ac20d8 143 {
MikamiUitOpen 16:cbb726ac20d8 144 register uint32_t __regProcessStackPointer __ASM("psp");
MikamiUitOpen 16:cbb726ac20d8 145 __regProcessStackPointer = topOfProcStack;
MikamiUitOpen 16:cbb726ac20d8 146 }
MikamiUitOpen 16:cbb726ac20d8 147
MikamiUitOpen 16:cbb726ac20d8 148
MikamiUitOpen 16:cbb726ac20d8 149 /** \brief Get Main Stack Pointer
MikamiUitOpen 16:cbb726ac20d8 150
MikamiUitOpen 16:cbb726ac20d8 151 This function returns the current value of the Main Stack Pointer (MSP).
MikamiUitOpen 16:cbb726ac20d8 152
MikamiUitOpen 16:cbb726ac20d8 153 \return MSP Register value
MikamiUitOpen 16:cbb726ac20d8 154 */
MikamiUitOpen 16:cbb726ac20d8 155 __STATIC_INLINE uint32_t __get_MSP(void)
MikamiUitOpen 16:cbb726ac20d8 156 {
MikamiUitOpen 16:cbb726ac20d8 157 register uint32_t __regMainStackPointer __ASM("msp");
MikamiUitOpen 16:cbb726ac20d8 158 return(__regMainStackPointer);
MikamiUitOpen 16:cbb726ac20d8 159 }
MikamiUitOpen 16:cbb726ac20d8 160
MikamiUitOpen 16:cbb726ac20d8 161
MikamiUitOpen 16:cbb726ac20d8 162 /** \brief Set Main Stack Pointer
MikamiUitOpen 16:cbb726ac20d8 163
MikamiUitOpen 16:cbb726ac20d8 164 This function assigns the given value to the Main Stack Pointer (MSP).
MikamiUitOpen 16:cbb726ac20d8 165
MikamiUitOpen 16:cbb726ac20d8 166 \param [in] topOfMainStack Main Stack Pointer value to set
MikamiUitOpen 16:cbb726ac20d8 167 */
MikamiUitOpen 16:cbb726ac20d8 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MikamiUitOpen 16:cbb726ac20d8 169 {
MikamiUitOpen 16:cbb726ac20d8 170 register uint32_t __regMainStackPointer __ASM("msp");
MikamiUitOpen 16:cbb726ac20d8 171 __regMainStackPointer = topOfMainStack;
MikamiUitOpen 16:cbb726ac20d8 172 }
MikamiUitOpen 16:cbb726ac20d8 173
MikamiUitOpen 16:cbb726ac20d8 174
MikamiUitOpen 16:cbb726ac20d8 175 /** \brief Get Priority Mask
MikamiUitOpen 16:cbb726ac20d8 176
MikamiUitOpen 16:cbb726ac20d8 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
MikamiUitOpen 16:cbb726ac20d8 178
MikamiUitOpen 16:cbb726ac20d8 179 \return Priority Mask value
MikamiUitOpen 16:cbb726ac20d8 180 */
MikamiUitOpen 16:cbb726ac20d8 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
MikamiUitOpen 16:cbb726ac20d8 182 {
MikamiUitOpen 16:cbb726ac20d8 183 register uint32_t __regPriMask __ASM("primask");
MikamiUitOpen 16:cbb726ac20d8 184 return(__regPriMask);
MikamiUitOpen 16:cbb726ac20d8 185 }
MikamiUitOpen 16:cbb726ac20d8 186
MikamiUitOpen 16:cbb726ac20d8 187
MikamiUitOpen 16:cbb726ac20d8 188 /** \brief Set Priority Mask
MikamiUitOpen 16:cbb726ac20d8 189
MikamiUitOpen 16:cbb726ac20d8 190 This function assigns the given value to the Priority Mask Register.
MikamiUitOpen 16:cbb726ac20d8 191
MikamiUitOpen 16:cbb726ac20d8 192 \param [in] priMask Priority Mask
MikamiUitOpen 16:cbb726ac20d8 193 */
MikamiUitOpen 16:cbb726ac20d8 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MikamiUitOpen 16:cbb726ac20d8 195 {
MikamiUitOpen 16:cbb726ac20d8 196 register uint32_t __regPriMask __ASM("primask");
MikamiUitOpen 16:cbb726ac20d8 197 __regPriMask = (priMask);
MikamiUitOpen 16:cbb726ac20d8 198 }
MikamiUitOpen 16:cbb726ac20d8 199
MikamiUitOpen 16:cbb726ac20d8 200
MikamiUitOpen 16:cbb726ac20d8 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 16:cbb726ac20d8 202
MikamiUitOpen 16:cbb726ac20d8 203 /** \brief Enable FIQ
MikamiUitOpen 16:cbb726ac20d8 204
MikamiUitOpen 16:cbb726ac20d8 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 16:cbb726ac20d8 206 Can only be executed in Privileged modes.
MikamiUitOpen 16:cbb726ac20d8 207 */
MikamiUitOpen 16:cbb726ac20d8 208 #define __enable_fault_irq __enable_fiq
MikamiUitOpen 16:cbb726ac20d8 209
MikamiUitOpen 16:cbb726ac20d8 210
MikamiUitOpen 16:cbb726ac20d8 211 /** \brief Disable FIQ
MikamiUitOpen 16:cbb726ac20d8 212
MikamiUitOpen 16:cbb726ac20d8 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 16:cbb726ac20d8 214 Can only be executed in Privileged modes.
MikamiUitOpen 16:cbb726ac20d8 215 */
MikamiUitOpen 16:cbb726ac20d8 216 #define __disable_fault_irq __disable_fiq
MikamiUitOpen 16:cbb726ac20d8 217
MikamiUitOpen 16:cbb726ac20d8 218
MikamiUitOpen 16:cbb726ac20d8 219 /** \brief Get Base Priority
MikamiUitOpen 16:cbb726ac20d8 220
MikamiUitOpen 16:cbb726ac20d8 221 This function returns the current value of the Base Priority register.
MikamiUitOpen 16:cbb726ac20d8 222
MikamiUitOpen 16:cbb726ac20d8 223 \return Base Priority register value
MikamiUitOpen 16:cbb726ac20d8 224 */
MikamiUitOpen 16:cbb726ac20d8 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
MikamiUitOpen 16:cbb726ac20d8 226 {
MikamiUitOpen 16:cbb726ac20d8 227 register uint32_t __regBasePri __ASM("basepri");
MikamiUitOpen 16:cbb726ac20d8 228 return(__regBasePri);
MikamiUitOpen 16:cbb726ac20d8 229 }
MikamiUitOpen 16:cbb726ac20d8 230
MikamiUitOpen 16:cbb726ac20d8 231
MikamiUitOpen 16:cbb726ac20d8 232 /** \brief Set Base Priority
MikamiUitOpen 16:cbb726ac20d8 233
MikamiUitOpen 16:cbb726ac20d8 234 This function assigns the given value to the Base Priority register.
MikamiUitOpen 16:cbb726ac20d8 235
MikamiUitOpen 16:cbb726ac20d8 236 \param [in] basePri Base Priority value to set
MikamiUitOpen 16:cbb726ac20d8 237 */
MikamiUitOpen 16:cbb726ac20d8 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
MikamiUitOpen 16:cbb726ac20d8 239 {
MikamiUitOpen 16:cbb726ac20d8 240 register uint32_t __regBasePri __ASM("basepri");
MikamiUitOpen 16:cbb726ac20d8 241 __regBasePri = (basePri & 0xff);
MikamiUitOpen 16:cbb726ac20d8 242 }
MikamiUitOpen 16:cbb726ac20d8 243
MikamiUitOpen 16:cbb726ac20d8 244
MikamiUitOpen 16:cbb726ac20d8 245 /** \brief Set Base Priority with condition
MikamiUitOpen 16:cbb726ac20d8 246
MikamiUitOpen 16:cbb726ac20d8 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MikamiUitOpen 16:cbb726ac20d8 248 or the new value increases the BASEPRI priority level.
MikamiUitOpen 16:cbb726ac20d8 249
MikamiUitOpen 16:cbb726ac20d8 250 \param [in] basePri Base Priority value to set
MikamiUitOpen 16:cbb726ac20d8 251 */
MikamiUitOpen 16:cbb726ac20d8 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
MikamiUitOpen 16:cbb726ac20d8 253 {
MikamiUitOpen 16:cbb726ac20d8 254 register uint32_t __regBasePriMax __ASM("basepri_max");
MikamiUitOpen 16:cbb726ac20d8 255 __regBasePriMax = (basePri & 0xff);
MikamiUitOpen 16:cbb726ac20d8 256 }
MikamiUitOpen 16:cbb726ac20d8 257
MikamiUitOpen 16:cbb726ac20d8 258
MikamiUitOpen 16:cbb726ac20d8 259 /** \brief Get Fault Mask
MikamiUitOpen 16:cbb726ac20d8 260
MikamiUitOpen 16:cbb726ac20d8 261 This function returns the current value of the Fault Mask register.
MikamiUitOpen 16:cbb726ac20d8 262
MikamiUitOpen 16:cbb726ac20d8 263 \return Fault Mask register value
MikamiUitOpen 16:cbb726ac20d8 264 */
MikamiUitOpen 16:cbb726ac20d8 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MikamiUitOpen 16:cbb726ac20d8 266 {
MikamiUitOpen 16:cbb726ac20d8 267 register uint32_t __regFaultMask __ASM("faultmask");
MikamiUitOpen 16:cbb726ac20d8 268 return(__regFaultMask);
MikamiUitOpen 16:cbb726ac20d8 269 }
MikamiUitOpen 16:cbb726ac20d8 270
MikamiUitOpen 16:cbb726ac20d8 271
MikamiUitOpen 16:cbb726ac20d8 272 /** \brief Set Fault Mask
MikamiUitOpen 16:cbb726ac20d8 273
MikamiUitOpen 16:cbb726ac20d8 274 This function assigns the given value to the Fault Mask register.
MikamiUitOpen 16:cbb726ac20d8 275
MikamiUitOpen 16:cbb726ac20d8 276 \param [in] faultMask Fault Mask value to set
MikamiUitOpen 16:cbb726ac20d8 277 */
MikamiUitOpen 16:cbb726ac20d8 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MikamiUitOpen 16:cbb726ac20d8 279 {
MikamiUitOpen 16:cbb726ac20d8 280 register uint32_t __regFaultMask __ASM("faultmask");
MikamiUitOpen 16:cbb726ac20d8 281 __regFaultMask = (faultMask & (uint32_t)1);
MikamiUitOpen 16:cbb726ac20d8 282 }
MikamiUitOpen 16:cbb726ac20d8 283
MikamiUitOpen 16:cbb726ac20d8 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 16:cbb726ac20d8 285
MikamiUitOpen 16:cbb726ac20d8 286
MikamiUitOpen 16:cbb726ac20d8 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MikamiUitOpen 16:cbb726ac20d8 288
MikamiUitOpen 16:cbb726ac20d8 289 /** \brief Get FPSCR
MikamiUitOpen 16:cbb726ac20d8 290
MikamiUitOpen 16:cbb726ac20d8 291 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 16:cbb726ac20d8 292
MikamiUitOpen 16:cbb726ac20d8 293 \return Floating Point Status/Control register value
MikamiUitOpen 16:cbb726ac20d8 294 */
MikamiUitOpen 16:cbb726ac20d8 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 16:cbb726ac20d8 296 {
MikamiUitOpen 16:cbb726ac20d8 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 16:cbb726ac20d8 298 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 16:cbb726ac20d8 299 return(__regfpscr);
MikamiUitOpen 16:cbb726ac20d8 300 #else
MikamiUitOpen 16:cbb726ac20d8 301 return(0);
MikamiUitOpen 16:cbb726ac20d8 302 #endif
MikamiUitOpen 16:cbb726ac20d8 303 }
MikamiUitOpen 16:cbb726ac20d8 304
MikamiUitOpen 16:cbb726ac20d8 305
MikamiUitOpen 16:cbb726ac20d8 306 /** \brief Set FPSCR
MikamiUitOpen 16:cbb726ac20d8 307
MikamiUitOpen 16:cbb726ac20d8 308 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 16:cbb726ac20d8 309
MikamiUitOpen 16:cbb726ac20d8 310 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 16:cbb726ac20d8 311 */
MikamiUitOpen 16:cbb726ac20d8 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 16:cbb726ac20d8 313 {
MikamiUitOpen 16:cbb726ac20d8 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 16:cbb726ac20d8 315 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 16:cbb726ac20d8 316 __regfpscr = (fpscr);
MikamiUitOpen 16:cbb726ac20d8 317 #endif
MikamiUitOpen 16:cbb726ac20d8 318 }
MikamiUitOpen 16:cbb726ac20d8 319
MikamiUitOpen 16:cbb726ac20d8 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MikamiUitOpen 16:cbb726ac20d8 321
MikamiUitOpen 16:cbb726ac20d8 322
MikamiUitOpen 16:cbb726ac20d8 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 16:cbb726ac20d8 324 /* GNU gcc specific functions */
MikamiUitOpen 16:cbb726ac20d8 325
MikamiUitOpen 16:cbb726ac20d8 326 /** \brief Enable IRQ Interrupts
MikamiUitOpen 16:cbb726ac20d8 327
MikamiUitOpen 16:cbb726ac20d8 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
MikamiUitOpen 16:cbb726ac20d8 329 Can only be executed in Privileged modes.
MikamiUitOpen 16:cbb726ac20d8 330 */
MikamiUitOpen 16:cbb726ac20d8 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
MikamiUitOpen 16:cbb726ac20d8 332 {
MikamiUitOpen 16:cbb726ac20d8 333 __ASM volatile ("cpsie i" : : : "memory");
MikamiUitOpen 16:cbb726ac20d8 334 }
MikamiUitOpen 16:cbb726ac20d8 335
MikamiUitOpen 16:cbb726ac20d8 336
MikamiUitOpen 16:cbb726ac20d8 337 /** \brief Disable IRQ Interrupts
MikamiUitOpen 16:cbb726ac20d8 338
MikamiUitOpen 16:cbb726ac20d8 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
MikamiUitOpen 16:cbb726ac20d8 340 Can only be executed in Privileged modes.
MikamiUitOpen 16:cbb726ac20d8 341 */
MikamiUitOpen 16:cbb726ac20d8 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
MikamiUitOpen 16:cbb726ac20d8 343 {
MikamiUitOpen 16:cbb726ac20d8 344 __ASM volatile ("cpsid i" : : : "memory");
MikamiUitOpen 16:cbb726ac20d8 345 }
MikamiUitOpen 16:cbb726ac20d8 346
MikamiUitOpen 16:cbb726ac20d8 347
MikamiUitOpen 16:cbb726ac20d8 348 /** \brief Get Control Register
MikamiUitOpen 16:cbb726ac20d8 349
MikamiUitOpen 16:cbb726ac20d8 350 This function returns the content of the Control Register.
MikamiUitOpen 16:cbb726ac20d8 351
MikamiUitOpen 16:cbb726ac20d8 352 \return Control Register value
MikamiUitOpen 16:cbb726ac20d8 353 */
MikamiUitOpen 16:cbb726ac20d8 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
MikamiUitOpen 16:cbb726ac20d8 355 {
MikamiUitOpen 16:cbb726ac20d8 356 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 357
MikamiUitOpen 16:cbb726ac20d8 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 359 return(result);
MikamiUitOpen 16:cbb726ac20d8 360 }
MikamiUitOpen 16:cbb726ac20d8 361
MikamiUitOpen 16:cbb726ac20d8 362
MikamiUitOpen 16:cbb726ac20d8 363 /** \brief Set Control Register
MikamiUitOpen 16:cbb726ac20d8 364
MikamiUitOpen 16:cbb726ac20d8 365 This function writes the given value to the Control Register.
MikamiUitOpen 16:cbb726ac20d8 366
MikamiUitOpen 16:cbb726ac20d8 367 \param [in] control Control Register value to set
MikamiUitOpen 16:cbb726ac20d8 368 */
MikamiUitOpen 16:cbb726ac20d8 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
MikamiUitOpen 16:cbb726ac20d8 370 {
MikamiUitOpen 16:cbb726ac20d8 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
MikamiUitOpen 16:cbb726ac20d8 372 }
MikamiUitOpen 16:cbb726ac20d8 373
MikamiUitOpen 16:cbb726ac20d8 374
MikamiUitOpen 16:cbb726ac20d8 375 /** \brief Get IPSR Register
MikamiUitOpen 16:cbb726ac20d8 376
MikamiUitOpen 16:cbb726ac20d8 377 This function returns the content of the IPSR Register.
MikamiUitOpen 16:cbb726ac20d8 378
MikamiUitOpen 16:cbb726ac20d8 379 \return IPSR Register value
MikamiUitOpen 16:cbb726ac20d8 380 */
MikamiUitOpen 16:cbb726ac20d8 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
MikamiUitOpen 16:cbb726ac20d8 382 {
MikamiUitOpen 16:cbb726ac20d8 383 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 384
MikamiUitOpen 16:cbb726ac20d8 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 386 return(result);
MikamiUitOpen 16:cbb726ac20d8 387 }
MikamiUitOpen 16:cbb726ac20d8 388
MikamiUitOpen 16:cbb726ac20d8 389
MikamiUitOpen 16:cbb726ac20d8 390 /** \brief Get APSR Register
MikamiUitOpen 16:cbb726ac20d8 391
MikamiUitOpen 16:cbb726ac20d8 392 This function returns the content of the APSR Register.
MikamiUitOpen 16:cbb726ac20d8 393
MikamiUitOpen 16:cbb726ac20d8 394 \return APSR Register value
MikamiUitOpen 16:cbb726ac20d8 395 */
MikamiUitOpen 16:cbb726ac20d8 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 16:cbb726ac20d8 397 {
MikamiUitOpen 16:cbb726ac20d8 398 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 399
MikamiUitOpen 16:cbb726ac20d8 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 401 return(result);
MikamiUitOpen 16:cbb726ac20d8 402 }
MikamiUitOpen 16:cbb726ac20d8 403
MikamiUitOpen 16:cbb726ac20d8 404
MikamiUitOpen 16:cbb726ac20d8 405 /** \brief Get xPSR Register
MikamiUitOpen 16:cbb726ac20d8 406
MikamiUitOpen 16:cbb726ac20d8 407 This function returns the content of the xPSR Register.
MikamiUitOpen 16:cbb726ac20d8 408
MikamiUitOpen 16:cbb726ac20d8 409 \return xPSR Register value
MikamiUitOpen 16:cbb726ac20d8 410 */
MikamiUitOpen 16:cbb726ac20d8 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
MikamiUitOpen 16:cbb726ac20d8 412 {
MikamiUitOpen 16:cbb726ac20d8 413 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 414
MikamiUitOpen 16:cbb726ac20d8 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 416 return(result);
MikamiUitOpen 16:cbb726ac20d8 417 }
MikamiUitOpen 16:cbb726ac20d8 418
MikamiUitOpen 16:cbb726ac20d8 419
MikamiUitOpen 16:cbb726ac20d8 420 /** \brief Get Process Stack Pointer
MikamiUitOpen 16:cbb726ac20d8 421
MikamiUitOpen 16:cbb726ac20d8 422 This function returns the current value of the Process Stack Pointer (PSP).
MikamiUitOpen 16:cbb726ac20d8 423
MikamiUitOpen 16:cbb726ac20d8 424 \return PSP Register value
MikamiUitOpen 16:cbb726ac20d8 425 */
MikamiUitOpen 16:cbb726ac20d8 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
MikamiUitOpen 16:cbb726ac20d8 427 {
MikamiUitOpen 16:cbb726ac20d8 428 register uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 429
MikamiUitOpen 16:cbb726ac20d8 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 431 return(result);
MikamiUitOpen 16:cbb726ac20d8 432 }
MikamiUitOpen 16:cbb726ac20d8 433
MikamiUitOpen 16:cbb726ac20d8 434
MikamiUitOpen 16:cbb726ac20d8 435 /** \brief Set Process Stack Pointer
MikamiUitOpen 16:cbb726ac20d8 436
MikamiUitOpen 16:cbb726ac20d8 437 This function assigns the given value to the Process Stack Pointer (PSP).
MikamiUitOpen 16:cbb726ac20d8 438
MikamiUitOpen 16:cbb726ac20d8 439 \param [in] topOfProcStack Process Stack Pointer value to set
MikamiUitOpen 16:cbb726ac20d8 440 */
MikamiUitOpen 16:cbb726ac20d8 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 16:cbb726ac20d8 442 {
MikamiUitOpen 16:cbb726ac20d8 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
MikamiUitOpen 16:cbb726ac20d8 444 }
MikamiUitOpen 16:cbb726ac20d8 445
MikamiUitOpen 16:cbb726ac20d8 446
MikamiUitOpen 16:cbb726ac20d8 447 /** \brief Get Main Stack Pointer
MikamiUitOpen 16:cbb726ac20d8 448
MikamiUitOpen 16:cbb726ac20d8 449 This function returns the current value of the Main Stack Pointer (MSP).
MikamiUitOpen 16:cbb726ac20d8 450
MikamiUitOpen 16:cbb726ac20d8 451 \return MSP Register value
MikamiUitOpen 16:cbb726ac20d8 452 */
MikamiUitOpen 16:cbb726ac20d8 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
MikamiUitOpen 16:cbb726ac20d8 454 {
MikamiUitOpen 16:cbb726ac20d8 455 register uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 456
MikamiUitOpen 16:cbb726ac20d8 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 458 return(result);
MikamiUitOpen 16:cbb726ac20d8 459 }
MikamiUitOpen 16:cbb726ac20d8 460
MikamiUitOpen 16:cbb726ac20d8 461
MikamiUitOpen 16:cbb726ac20d8 462 /** \brief Set Main Stack Pointer
MikamiUitOpen 16:cbb726ac20d8 463
MikamiUitOpen 16:cbb726ac20d8 464 This function assigns the given value to the Main Stack Pointer (MSP).
MikamiUitOpen 16:cbb726ac20d8 465
MikamiUitOpen 16:cbb726ac20d8 466 \param [in] topOfMainStack Main Stack Pointer value to set
MikamiUitOpen 16:cbb726ac20d8 467 */
MikamiUitOpen 16:cbb726ac20d8 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
MikamiUitOpen 16:cbb726ac20d8 469 {
MikamiUitOpen 16:cbb726ac20d8 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
MikamiUitOpen 16:cbb726ac20d8 471 }
MikamiUitOpen 16:cbb726ac20d8 472
MikamiUitOpen 16:cbb726ac20d8 473
MikamiUitOpen 16:cbb726ac20d8 474 /** \brief Get Priority Mask
MikamiUitOpen 16:cbb726ac20d8 475
MikamiUitOpen 16:cbb726ac20d8 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
MikamiUitOpen 16:cbb726ac20d8 477
MikamiUitOpen 16:cbb726ac20d8 478 \return Priority Mask value
MikamiUitOpen 16:cbb726ac20d8 479 */
MikamiUitOpen 16:cbb726ac20d8 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
MikamiUitOpen 16:cbb726ac20d8 481 {
MikamiUitOpen 16:cbb726ac20d8 482 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 483
MikamiUitOpen 16:cbb726ac20d8 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 485 return(result);
MikamiUitOpen 16:cbb726ac20d8 486 }
MikamiUitOpen 16:cbb726ac20d8 487
MikamiUitOpen 16:cbb726ac20d8 488
MikamiUitOpen 16:cbb726ac20d8 489 /** \brief Set Priority Mask
MikamiUitOpen 16:cbb726ac20d8 490
MikamiUitOpen 16:cbb726ac20d8 491 This function assigns the given value to the Priority Mask Register.
MikamiUitOpen 16:cbb726ac20d8 492
MikamiUitOpen 16:cbb726ac20d8 493 \param [in] priMask Priority Mask
MikamiUitOpen 16:cbb726ac20d8 494 */
MikamiUitOpen 16:cbb726ac20d8 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
MikamiUitOpen 16:cbb726ac20d8 496 {
MikamiUitOpen 16:cbb726ac20d8 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
MikamiUitOpen 16:cbb726ac20d8 498 }
MikamiUitOpen 16:cbb726ac20d8 499
MikamiUitOpen 16:cbb726ac20d8 500
MikamiUitOpen 16:cbb726ac20d8 501 #if (__CORTEX_M >= 0x03)
MikamiUitOpen 16:cbb726ac20d8 502
MikamiUitOpen 16:cbb726ac20d8 503 /** \brief Enable FIQ
MikamiUitOpen 16:cbb726ac20d8 504
MikamiUitOpen 16:cbb726ac20d8 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 16:cbb726ac20d8 506 Can only be executed in Privileged modes.
MikamiUitOpen 16:cbb726ac20d8 507 */
MikamiUitOpen 16:cbb726ac20d8 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
MikamiUitOpen 16:cbb726ac20d8 509 {
MikamiUitOpen 16:cbb726ac20d8 510 __ASM volatile ("cpsie f" : : : "memory");
MikamiUitOpen 16:cbb726ac20d8 511 }
MikamiUitOpen 16:cbb726ac20d8 512
MikamiUitOpen 16:cbb726ac20d8 513
MikamiUitOpen 16:cbb726ac20d8 514 /** \brief Disable FIQ
MikamiUitOpen 16:cbb726ac20d8 515
MikamiUitOpen 16:cbb726ac20d8 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 16:cbb726ac20d8 517 Can only be executed in Privileged modes.
MikamiUitOpen 16:cbb726ac20d8 518 */
MikamiUitOpen 16:cbb726ac20d8 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
MikamiUitOpen 16:cbb726ac20d8 520 {
MikamiUitOpen 16:cbb726ac20d8 521 __ASM volatile ("cpsid f" : : : "memory");
MikamiUitOpen 16:cbb726ac20d8 522 }
MikamiUitOpen 16:cbb726ac20d8 523
MikamiUitOpen 16:cbb726ac20d8 524
MikamiUitOpen 16:cbb726ac20d8 525 /** \brief Get Base Priority
MikamiUitOpen 16:cbb726ac20d8 526
MikamiUitOpen 16:cbb726ac20d8 527 This function returns the current value of the Base Priority register.
MikamiUitOpen 16:cbb726ac20d8 528
MikamiUitOpen 16:cbb726ac20d8 529 \return Base Priority register value
MikamiUitOpen 16:cbb726ac20d8 530 */
MikamiUitOpen 16:cbb726ac20d8 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
MikamiUitOpen 16:cbb726ac20d8 532 {
MikamiUitOpen 16:cbb726ac20d8 533 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 534
MikamiUitOpen 16:cbb726ac20d8 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 536 return(result);
MikamiUitOpen 16:cbb726ac20d8 537 }
MikamiUitOpen 16:cbb726ac20d8 538
MikamiUitOpen 16:cbb726ac20d8 539
MikamiUitOpen 16:cbb726ac20d8 540 /** \brief Set Base Priority
MikamiUitOpen 16:cbb726ac20d8 541
MikamiUitOpen 16:cbb726ac20d8 542 This function assigns the given value to the Base Priority register.
MikamiUitOpen 16:cbb726ac20d8 543
MikamiUitOpen 16:cbb726ac20d8 544 \param [in] basePri Base Priority value to set
MikamiUitOpen 16:cbb726ac20d8 545 */
MikamiUitOpen 16:cbb726ac20d8 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
MikamiUitOpen 16:cbb726ac20d8 547 {
MikamiUitOpen 16:cbb726ac20d8 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
MikamiUitOpen 16:cbb726ac20d8 549 }
MikamiUitOpen 16:cbb726ac20d8 550
MikamiUitOpen 16:cbb726ac20d8 551
MikamiUitOpen 16:cbb726ac20d8 552 /** \brief Set Base Priority with condition
MikamiUitOpen 16:cbb726ac20d8 553
MikamiUitOpen 16:cbb726ac20d8 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
MikamiUitOpen 16:cbb726ac20d8 555 or the new value increases the BASEPRI priority level.
MikamiUitOpen 16:cbb726ac20d8 556
MikamiUitOpen 16:cbb726ac20d8 557 \param [in] basePri Base Priority value to set
MikamiUitOpen 16:cbb726ac20d8 558 */
MikamiUitOpen 16:cbb726ac20d8 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
MikamiUitOpen 16:cbb726ac20d8 560 {
MikamiUitOpen 16:cbb726ac20d8 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
MikamiUitOpen 16:cbb726ac20d8 562 }
MikamiUitOpen 16:cbb726ac20d8 563
MikamiUitOpen 16:cbb726ac20d8 564
MikamiUitOpen 16:cbb726ac20d8 565 /** \brief Get Fault Mask
MikamiUitOpen 16:cbb726ac20d8 566
MikamiUitOpen 16:cbb726ac20d8 567 This function returns the current value of the Fault Mask register.
MikamiUitOpen 16:cbb726ac20d8 568
MikamiUitOpen 16:cbb726ac20d8 569 \return Fault Mask register value
MikamiUitOpen 16:cbb726ac20d8 570 */
MikamiUitOpen 16:cbb726ac20d8 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
MikamiUitOpen 16:cbb726ac20d8 572 {
MikamiUitOpen 16:cbb726ac20d8 573 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 574
MikamiUitOpen 16:cbb726ac20d8 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 576 return(result);
MikamiUitOpen 16:cbb726ac20d8 577 }
MikamiUitOpen 16:cbb726ac20d8 578
MikamiUitOpen 16:cbb726ac20d8 579
MikamiUitOpen 16:cbb726ac20d8 580 /** \brief Set Fault Mask
MikamiUitOpen 16:cbb726ac20d8 581
MikamiUitOpen 16:cbb726ac20d8 582 This function assigns the given value to the Fault Mask register.
MikamiUitOpen 16:cbb726ac20d8 583
MikamiUitOpen 16:cbb726ac20d8 584 \param [in] faultMask Fault Mask value to set
MikamiUitOpen 16:cbb726ac20d8 585 */
MikamiUitOpen 16:cbb726ac20d8 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
MikamiUitOpen 16:cbb726ac20d8 587 {
MikamiUitOpen 16:cbb726ac20d8 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
MikamiUitOpen 16:cbb726ac20d8 589 }
MikamiUitOpen 16:cbb726ac20d8 590
MikamiUitOpen 16:cbb726ac20d8 591 #endif /* (__CORTEX_M >= 0x03) */
MikamiUitOpen 16:cbb726ac20d8 592
MikamiUitOpen 16:cbb726ac20d8 593
MikamiUitOpen 16:cbb726ac20d8 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
MikamiUitOpen 16:cbb726ac20d8 595
MikamiUitOpen 16:cbb726ac20d8 596 /** \brief Get FPSCR
MikamiUitOpen 16:cbb726ac20d8 597
MikamiUitOpen 16:cbb726ac20d8 598 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 16:cbb726ac20d8 599
MikamiUitOpen 16:cbb726ac20d8 600 \return Floating Point Status/Control register value
MikamiUitOpen 16:cbb726ac20d8 601 */
MikamiUitOpen 16:cbb726ac20d8 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 16:cbb726ac20d8 603 {
MikamiUitOpen 16:cbb726ac20d8 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 16:cbb726ac20d8 605 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 606
MikamiUitOpen 16:cbb726ac20d8 607 /* Empty asm statement works as a scheduling barrier */
MikamiUitOpen 16:cbb726ac20d8 608 __ASM volatile ("");
MikamiUitOpen 16:cbb726ac20d8 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
MikamiUitOpen 16:cbb726ac20d8 610 __ASM volatile ("");
MikamiUitOpen 16:cbb726ac20d8 611 return(result);
MikamiUitOpen 16:cbb726ac20d8 612 #else
MikamiUitOpen 16:cbb726ac20d8 613 return(0);
MikamiUitOpen 16:cbb726ac20d8 614 #endif
MikamiUitOpen 16:cbb726ac20d8 615 }
MikamiUitOpen 16:cbb726ac20d8 616
MikamiUitOpen 16:cbb726ac20d8 617
MikamiUitOpen 16:cbb726ac20d8 618 /** \brief Set FPSCR
MikamiUitOpen 16:cbb726ac20d8 619
MikamiUitOpen 16:cbb726ac20d8 620 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 16:cbb726ac20d8 621
MikamiUitOpen 16:cbb726ac20d8 622 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 16:cbb726ac20d8 623 */
MikamiUitOpen 16:cbb726ac20d8 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 16:cbb726ac20d8 625 {
MikamiUitOpen 16:cbb726ac20d8 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 16:cbb726ac20d8 627 /* Empty asm statement works as a scheduling barrier */
MikamiUitOpen 16:cbb726ac20d8 628 __ASM volatile ("");
MikamiUitOpen 16:cbb726ac20d8 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
MikamiUitOpen 16:cbb726ac20d8 630 __ASM volatile ("");
MikamiUitOpen 16:cbb726ac20d8 631 #endif
MikamiUitOpen 16:cbb726ac20d8 632 }
MikamiUitOpen 16:cbb726ac20d8 633
MikamiUitOpen 16:cbb726ac20d8 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
MikamiUitOpen 16:cbb726ac20d8 635
MikamiUitOpen 16:cbb726ac20d8 636
MikamiUitOpen 16:cbb726ac20d8 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 16:cbb726ac20d8 638 /* IAR iccarm specific functions */
MikamiUitOpen 16:cbb726ac20d8 639 #include <cmsis_iar.h>
MikamiUitOpen 16:cbb726ac20d8 640
MikamiUitOpen 16:cbb726ac20d8 641
MikamiUitOpen 16:cbb726ac20d8 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 16:cbb726ac20d8 643 /* TI CCS specific functions */
MikamiUitOpen 16:cbb726ac20d8 644 #include <cmsis_ccs.h>
MikamiUitOpen 16:cbb726ac20d8 645
MikamiUitOpen 16:cbb726ac20d8 646
MikamiUitOpen 16:cbb726ac20d8 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 16:cbb726ac20d8 648 /* TASKING carm specific functions */
MikamiUitOpen 16:cbb726ac20d8 649 /*
MikamiUitOpen 16:cbb726ac20d8 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
MikamiUitOpen 16:cbb726ac20d8 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
MikamiUitOpen 16:cbb726ac20d8 652 * Including the CMSIS ones.
MikamiUitOpen 16:cbb726ac20d8 653 */
MikamiUitOpen 16:cbb726ac20d8 654
MikamiUitOpen 16:cbb726ac20d8 655
MikamiUitOpen 16:cbb726ac20d8 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MikamiUitOpen 16:cbb726ac20d8 657 /* Cosmic specific functions */
MikamiUitOpen 16:cbb726ac20d8 658 #include <cmsis_csm.h>
MikamiUitOpen 16:cbb726ac20d8 659
MikamiUitOpen 16:cbb726ac20d8 660 #endif
MikamiUitOpen 16:cbb726ac20d8 661
MikamiUitOpen 16:cbb726ac20d8 662 /*@} end of CMSIS_Core_RegAccFunctions */
MikamiUitOpen 16:cbb726ac20d8 663
MikamiUitOpen 16:cbb726ac20d8 664 #endif /* __CORE_CMFUNC_H */