不韋 呂 / F746_SD_GraphicEqualizer

Output the audio signal with filtering by graphic equalizer in the *.wav file on the SD card using onboard CODEC. SD カードの *.wav ファイルのオーディオ信号をグラフィック･イコライザを通して，ボードに搭載されているCODEC で出力する．

Dependencies:   F746_GUI F746_SAI_IO SD_PlayerSkeleton FrequencyResponseDrawer

mbed_src_STM32F7/targets/cmsis/core_cm4_simd.h@24:f78f9d0ac262, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 04:07:35 2017 +0000
Revision:
24:f78f9d0ac262
Parent:
16:cbb726ac20d8 
25

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 16:cbb726ac20d8 1 /**************************************************************************//**
MikamiUitOpen 16:cbb726ac20d8 2 * @file core_cm4_simd.h
MikamiUitOpen 16:cbb726ac20d8 3 * @brief CMSIS Cortex-M4 SIMD Header File
MikamiUitOpen 16:cbb726ac20d8 4 * @version V3.20
MikamiUitOpen 16:cbb726ac20d8 5 * @date 25. February 2013
MikamiUitOpen 16:cbb726ac20d8 6 *
MikamiUitOpen 16:cbb726ac20d8 7 * @note
MikamiUitOpen 16:cbb726ac20d8 8 *
MikamiUitOpen 16:cbb726ac20d8 9 ******************************************************************************/
MikamiUitOpen 16:cbb726ac20d8 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
MikamiUitOpen 16:cbb726ac20d8 11
MikamiUitOpen 16:cbb726ac20d8 12 All rights reserved.
MikamiUitOpen 16:cbb726ac20d8 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 16:cbb726ac20d8 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 16:cbb726ac20d8 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 16:cbb726ac20d8 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 16:cbb726ac20d8 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 16:cbb726ac20d8 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 16:cbb726ac20d8 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 16:cbb726ac20d8 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 16:cbb726ac20d8 21 to endorse or promote products derived from this software without
MikamiUitOpen 16:cbb726ac20d8 22 specific prior written permission.
MikamiUitOpen 16:cbb726ac20d8 23 *
MikamiUitOpen 16:cbb726ac20d8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 16:cbb726ac20d8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 16:cbb726ac20d8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 16:cbb726ac20d8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 16:cbb726ac20d8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 16:cbb726ac20d8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 16:cbb726ac20d8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 16:cbb726ac20d8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 16:cbb726ac20d8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 16:cbb726ac20d8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 16:cbb726ac20d8 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 16:cbb726ac20d8 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 36
MikamiUitOpen 16:cbb726ac20d8 37
MikamiUitOpen 16:cbb726ac20d8 38 #ifdef __cplusplus
MikamiUitOpen 16:cbb726ac20d8 39 extern "C" {
MikamiUitOpen 16:cbb726ac20d8 40 #endif
MikamiUitOpen 16:cbb726ac20d8 41
MikamiUitOpen 16:cbb726ac20d8 42 #ifndef __CORE_CM4_SIMD_H
MikamiUitOpen 16:cbb726ac20d8 43 #define __CORE_CM4_SIMD_H
MikamiUitOpen 16:cbb726ac20d8 44
MikamiUitOpen 16:cbb726ac20d8 45
MikamiUitOpen 16:cbb726ac20d8 46 /*******************************************************************************
MikamiUitOpen 16:cbb726ac20d8 47 * Hardware Abstraction Layer
MikamiUitOpen 16:cbb726ac20d8 48 ******************************************************************************/
MikamiUitOpen 16:cbb726ac20d8 49
MikamiUitOpen 16:cbb726ac20d8 50
MikamiUitOpen 16:cbb726ac20d8 51 /* ################### Compiler specific Intrinsics ########################### */
MikamiUitOpen 16:cbb726ac20d8 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
MikamiUitOpen 16:cbb726ac20d8 53 Access to dedicated SIMD instructions
MikamiUitOpen 16:cbb726ac20d8 54 @{
MikamiUitOpen 16:cbb726ac20d8 55 */
MikamiUitOpen 16:cbb726ac20d8 56
MikamiUitOpen 16:cbb726ac20d8 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 16:cbb726ac20d8 58 /* ARM armcc specific functions */
MikamiUitOpen 16:cbb726ac20d8 59
MikamiUitOpen 16:cbb726ac20d8 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 61 #define __SADD8 __sadd8
MikamiUitOpen 16:cbb726ac20d8 62 #define __QADD8 __qadd8
MikamiUitOpen 16:cbb726ac20d8 63 #define __SHADD8 __shadd8
MikamiUitOpen 16:cbb726ac20d8 64 #define __UADD8 __uadd8
MikamiUitOpen 16:cbb726ac20d8 65 #define __UQADD8 __uqadd8
MikamiUitOpen 16:cbb726ac20d8 66 #define __UHADD8 __uhadd8
MikamiUitOpen 16:cbb726ac20d8 67 #define __SSUB8 __ssub8
MikamiUitOpen 16:cbb726ac20d8 68 #define __QSUB8 __qsub8
MikamiUitOpen 16:cbb726ac20d8 69 #define __SHSUB8 __shsub8
MikamiUitOpen 16:cbb726ac20d8 70 #define __USUB8 __usub8
MikamiUitOpen 16:cbb726ac20d8 71 #define __UQSUB8 __uqsub8
MikamiUitOpen 16:cbb726ac20d8 72 #define __UHSUB8 __uhsub8
MikamiUitOpen 16:cbb726ac20d8 73 #define __SADD16 __sadd16
MikamiUitOpen 16:cbb726ac20d8 74 #define __QADD16 __qadd16
MikamiUitOpen 16:cbb726ac20d8 75 #define __SHADD16 __shadd16
MikamiUitOpen 16:cbb726ac20d8 76 #define __UADD16 __uadd16
MikamiUitOpen 16:cbb726ac20d8 77 #define __UQADD16 __uqadd16
MikamiUitOpen 16:cbb726ac20d8 78 #define __UHADD16 __uhadd16
MikamiUitOpen 16:cbb726ac20d8 79 #define __SSUB16 __ssub16
MikamiUitOpen 16:cbb726ac20d8 80 #define __QSUB16 __qsub16
MikamiUitOpen 16:cbb726ac20d8 81 #define __SHSUB16 __shsub16
MikamiUitOpen 16:cbb726ac20d8 82 #define __USUB16 __usub16
MikamiUitOpen 16:cbb726ac20d8 83 #define __UQSUB16 __uqsub16
MikamiUitOpen 16:cbb726ac20d8 84 #define __UHSUB16 __uhsub16
MikamiUitOpen 16:cbb726ac20d8 85 #define __SASX __sasx
MikamiUitOpen 16:cbb726ac20d8 86 #define __QASX __qasx
MikamiUitOpen 16:cbb726ac20d8 87 #define __SHASX __shasx
MikamiUitOpen 16:cbb726ac20d8 88 #define __UASX __uasx
MikamiUitOpen 16:cbb726ac20d8 89 #define __UQASX __uqasx
MikamiUitOpen 16:cbb726ac20d8 90 #define __UHASX __uhasx
MikamiUitOpen 16:cbb726ac20d8 91 #define __SSAX __ssax
MikamiUitOpen 16:cbb726ac20d8 92 #define __QSAX __qsax
MikamiUitOpen 16:cbb726ac20d8 93 #define __SHSAX __shsax
MikamiUitOpen 16:cbb726ac20d8 94 #define __USAX __usax
MikamiUitOpen 16:cbb726ac20d8 95 #define __UQSAX __uqsax
MikamiUitOpen 16:cbb726ac20d8 96 #define __UHSAX __uhsax
MikamiUitOpen 16:cbb726ac20d8 97 #define __USAD8 __usad8
MikamiUitOpen 16:cbb726ac20d8 98 #define __USADA8 __usada8
MikamiUitOpen 16:cbb726ac20d8 99 #define __SSAT16 __ssat16
MikamiUitOpen 16:cbb726ac20d8 100 #define __USAT16 __usat16
MikamiUitOpen 16:cbb726ac20d8 101 #define __UXTB16 __uxtb16
MikamiUitOpen 16:cbb726ac20d8 102 #define __UXTAB16 __uxtab16
MikamiUitOpen 16:cbb726ac20d8 103 #define __SXTB16 __sxtb16
MikamiUitOpen 16:cbb726ac20d8 104 #define __SXTAB16 __sxtab16
MikamiUitOpen 16:cbb726ac20d8 105 #define __SMUAD __smuad
MikamiUitOpen 16:cbb726ac20d8 106 #define __SMUADX __smuadx
MikamiUitOpen 16:cbb726ac20d8 107 #define __SMLAD __smlad
MikamiUitOpen 16:cbb726ac20d8 108 #define __SMLADX __smladx
MikamiUitOpen 16:cbb726ac20d8 109 #define __SMLALD __smlald
MikamiUitOpen 16:cbb726ac20d8 110 #define __SMLALDX __smlaldx
MikamiUitOpen 16:cbb726ac20d8 111 #define __SMUSD __smusd
MikamiUitOpen 16:cbb726ac20d8 112 #define __SMUSDX __smusdx
MikamiUitOpen 16:cbb726ac20d8 113 #define __SMLSD __smlsd
MikamiUitOpen 16:cbb726ac20d8 114 #define __SMLSDX __smlsdx
MikamiUitOpen 16:cbb726ac20d8 115 #define __SMLSLD __smlsld
MikamiUitOpen 16:cbb726ac20d8 116 #define __SMLSLDX __smlsldx
MikamiUitOpen 16:cbb726ac20d8 117 #define __SEL __sel
MikamiUitOpen 16:cbb726ac20d8 118 #define __QADD __qadd
MikamiUitOpen 16:cbb726ac20d8 119 #define __QSUB __qsub
MikamiUitOpen 16:cbb726ac20d8 120
MikamiUitOpen 16:cbb726ac20d8 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
MikamiUitOpen 16:cbb726ac20d8 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
MikamiUitOpen 16:cbb726ac20d8 123
MikamiUitOpen 16:cbb726ac20d8 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
MikamiUitOpen 16:cbb726ac20d8 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
MikamiUitOpen 16:cbb726ac20d8 126
MikamiUitOpen 16:cbb726ac20d8 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
MikamiUitOpen 16:cbb726ac20d8 128 ((int64_t)(ARG3) << 32) ) >> 32))
MikamiUitOpen 16:cbb726ac20d8 129
MikamiUitOpen 16:cbb726ac20d8 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 131
MikamiUitOpen 16:cbb726ac20d8 132
MikamiUitOpen 16:cbb726ac20d8 133
MikamiUitOpen 16:cbb726ac20d8 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 16:cbb726ac20d8 135 /* IAR iccarm specific functions */
MikamiUitOpen 16:cbb726ac20d8 136
MikamiUitOpen 16:cbb726ac20d8 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 138 #include <cmsis_iar.h>
MikamiUitOpen 16:cbb726ac20d8 139
MikamiUitOpen 16:cbb726ac20d8 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 141
MikamiUitOpen 16:cbb726ac20d8 142
MikamiUitOpen 16:cbb726ac20d8 143
MikamiUitOpen 16:cbb726ac20d8 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 16:cbb726ac20d8 145 /* TI CCS specific functions */
MikamiUitOpen 16:cbb726ac20d8 146
MikamiUitOpen 16:cbb726ac20d8 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 148 #include <cmsis_ccs.h>
MikamiUitOpen 16:cbb726ac20d8 149
MikamiUitOpen 16:cbb726ac20d8 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 151
MikamiUitOpen 16:cbb726ac20d8 152
MikamiUitOpen 16:cbb726ac20d8 153
MikamiUitOpen 16:cbb726ac20d8 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 16:cbb726ac20d8 155 /* GNU gcc specific functions */
MikamiUitOpen 16:cbb726ac20d8 156
MikamiUitOpen 16:cbb726ac20d8 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 159 {
MikamiUitOpen 16:cbb726ac20d8 160 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 161
MikamiUitOpen 16:cbb726ac20d8 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 163 return(result);
MikamiUitOpen 16:cbb726ac20d8 164 }
MikamiUitOpen 16:cbb726ac20d8 165
MikamiUitOpen 16:cbb726ac20d8 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 167 {
MikamiUitOpen 16:cbb726ac20d8 168 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 169
MikamiUitOpen 16:cbb726ac20d8 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 171 return(result);
MikamiUitOpen 16:cbb726ac20d8 172 }
MikamiUitOpen 16:cbb726ac20d8 173
MikamiUitOpen 16:cbb726ac20d8 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 175 {
MikamiUitOpen 16:cbb726ac20d8 176 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 177
MikamiUitOpen 16:cbb726ac20d8 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 179 return(result);
MikamiUitOpen 16:cbb726ac20d8 180 }
MikamiUitOpen 16:cbb726ac20d8 181
MikamiUitOpen 16:cbb726ac20d8 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 183 {
MikamiUitOpen 16:cbb726ac20d8 184 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 185
MikamiUitOpen 16:cbb726ac20d8 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 187 return(result);
MikamiUitOpen 16:cbb726ac20d8 188 }
MikamiUitOpen 16:cbb726ac20d8 189
MikamiUitOpen 16:cbb726ac20d8 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 191 {
MikamiUitOpen 16:cbb726ac20d8 192 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 193
MikamiUitOpen 16:cbb726ac20d8 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 195 return(result);
MikamiUitOpen 16:cbb726ac20d8 196 }
MikamiUitOpen 16:cbb726ac20d8 197
MikamiUitOpen 16:cbb726ac20d8 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 199 {
MikamiUitOpen 16:cbb726ac20d8 200 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 201
MikamiUitOpen 16:cbb726ac20d8 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 203 return(result);
MikamiUitOpen 16:cbb726ac20d8 204 }
MikamiUitOpen 16:cbb726ac20d8 205
MikamiUitOpen 16:cbb726ac20d8 206
MikamiUitOpen 16:cbb726ac20d8 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 208 {
MikamiUitOpen 16:cbb726ac20d8 209 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 210
MikamiUitOpen 16:cbb726ac20d8 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 212 return(result);
MikamiUitOpen 16:cbb726ac20d8 213 }
MikamiUitOpen 16:cbb726ac20d8 214
MikamiUitOpen 16:cbb726ac20d8 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 216 {
MikamiUitOpen 16:cbb726ac20d8 217 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 218
MikamiUitOpen 16:cbb726ac20d8 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 220 return(result);
MikamiUitOpen 16:cbb726ac20d8 221 }
MikamiUitOpen 16:cbb726ac20d8 222
MikamiUitOpen 16:cbb726ac20d8 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 224 {
MikamiUitOpen 16:cbb726ac20d8 225 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 226
MikamiUitOpen 16:cbb726ac20d8 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 228 return(result);
MikamiUitOpen 16:cbb726ac20d8 229 }
MikamiUitOpen 16:cbb726ac20d8 230
MikamiUitOpen 16:cbb726ac20d8 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 232 {
MikamiUitOpen 16:cbb726ac20d8 233 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 234
MikamiUitOpen 16:cbb726ac20d8 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 236 return(result);
MikamiUitOpen 16:cbb726ac20d8 237 }
MikamiUitOpen 16:cbb726ac20d8 238
MikamiUitOpen 16:cbb726ac20d8 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 240 {
MikamiUitOpen 16:cbb726ac20d8 241 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 242
MikamiUitOpen 16:cbb726ac20d8 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 244 return(result);
MikamiUitOpen 16:cbb726ac20d8 245 }
MikamiUitOpen 16:cbb726ac20d8 246
MikamiUitOpen 16:cbb726ac20d8 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 248 {
MikamiUitOpen 16:cbb726ac20d8 249 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 250
MikamiUitOpen 16:cbb726ac20d8 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 252 return(result);
MikamiUitOpen 16:cbb726ac20d8 253 }
MikamiUitOpen 16:cbb726ac20d8 254
MikamiUitOpen 16:cbb726ac20d8 255
MikamiUitOpen 16:cbb726ac20d8 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 257 {
MikamiUitOpen 16:cbb726ac20d8 258 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 259
MikamiUitOpen 16:cbb726ac20d8 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 261 return(result);
MikamiUitOpen 16:cbb726ac20d8 262 }
MikamiUitOpen 16:cbb726ac20d8 263
MikamiUitOpen 16:cbb726ac20d8 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 265 {
MikamiUitOpen 16:cbb726ac20d8 266 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 267
MikamiUitOpen 16:cbb726ac20d8 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 269 return(result);
MikamiUitOpen 16:cbb726ac20d8 270 }
MikamiUitOpen 16:cbb726ac20d8 271
MikamiUitOpen 16:cbb726ac20d8 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 273 {
MikamiUitOpen 16:cbb726ac20d8 274 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 275
MikamiUitOpen 16:cbb726ac20d8 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 277 return(result);
MikamiUitOpen 16:cbb726ac20d8 278 }
MikamiUitOpen 16:cbb726ac20d8 279
MikamiUitOpen 16:cbb726ac20d8 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 281 {
MikamiUitOpen 16:cbb726ac20d8 282 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 283
MikamiUitOpen 16:cbb726ac20d8 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 285 return(result);
MikamiUitOpen 16:cbb726ac20d8 286 }
MikamiUitOpen 16:cbb726ac20d8 287
MikamiUitOpen 16:cbb726ac20d8 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 289 {
MikamiUitOpen 16:cbb726ac20d8 290 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 291
MikamiUitOpen 16:cbb726ac20d8 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 293 return(result);
MikamiUitOpen 16:cbb726ac20d8 294 }
MikamiUitOpen 16:cbb726ac20d8 295
MikamiUitOpen 16:cbb726ac20d8 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 297 {
MikamiUitOpen 16:cbb726ac20d8 298 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 299
MikamiUitOpen 16:cbb726ac20d8 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 301 return(result);
MikamiUitOpen 16:cbb726ac20d8 302 }
MikamiUitOpen 16:cbb726ac20d8 303
MikamiUitOpen 16:cbb726ac20d8 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 305 {
MikamiUitOpen 16:cbb726ac20d8 306 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 307
MikamiUitOpen 16:cbb726ac20d8 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 309 return(result);
MikamiUitOpen 16:cbb726ac20d8 310 }
MikamiUitOpen 16:cbb726ac20d8 311
MikamiUitOpen 16:cbb726ac20d8 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 313 {
MikamiUitOpen 16:cbb726ac20d8 314 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 315
MikamiUitOpen 16:cbb726ac20d8 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 317 return(result);
MikamiUitOpen 16:cbb726ac20d8 318 }
MikamiUitOpen 16:cbb726ac20d8 319
MikamiUitOpen 16:cbb726ac20d8 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 321 {
MikamiUitOpen 16:cbb726ac20d8 322 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 323
MikamiUitOpen 16:cbb726ac20d8 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 325 return(result);
MikamiUitOpen 16:cbb726ac20d8 326 }
MikamiUitOpen 16:cbb726ac20d8 327
MikamiUitOpen 16:cbb726ac20d8 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 329 {
MikamiUitOpen 16:cbb726ac20d8 330 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 331
MikamiUitOpen 16:cbb726ac20d8 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 333 return(result);
MikamiUitOpen 16:cbb726ac20d8 334 }
MikamiUitOpen 16:cbb726ac20d8 335
MikamiUitOpen 16:cbb726ac20d8 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 337 {
MikamiUitOpen 16:cbb726ac20d8 338 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 339
MikamiUitOpen 16:cbb726ac20d8 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 341 return(result);
MikamiUitOpen 16:cbb726ac20d8 342 }
MikamiUitOpen 16:cbb726ac20d8 343
MikamiUitOpen 16:cbb726ac20d8 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 345 {
MikamiUitOpen 16:cbb726ac20d8 346 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 347
MikamiUitOpen 16:cbb726ac20d8 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 349 return(result);
MikamiUitOpen 16:cbb726ac20d8 350 }
MikamiUitOpen 16:cbb726ac20d8 351
MikamiUitOpen 16:cbb726ac20d8 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 353 {
MikamiUitOpen 16:cbb726ac20d8 354 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 355
MikamiUitOpen 16:cbb726ac20d8 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 357 return(result);
MikamiUitOpen 16:cbb726ac20d8 358 }
MikamiUitOpen 16:cbb726ac20d8 359
MikamiUitOpen 16:cbb726ac20d8 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 361 {
MikamiUitOpen 16:cbb726ac20d8 362 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 363
MikamiUitOpen 16:cbb726ac20d8 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 365 return(result);
MikamiUitOpen 16:cbb726ac20d8 366 }
MikamiUitOpen 16:cbb726ac20d8 367
MikamiUitOpen 16:cbb726ac20d8 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 369 {
MikamiUitOpen 16:cbb726ac20d8 370 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 371
MikamiUitOpen 16:cbb726ac20d8 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 373 return(result);
MikamiUitOpen 16:cbb726ac20d8 374 }
MikamiUitOpen 16:cbb726ac20d8 375
MikamiUitOpen 16:cbb726ac20d8 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 377 {
MikamiUitOpen 16:cbb726ac20d8 378 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 379
MikamiUitOpen 16:cbb726ac20d8 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 381 return(result);
MikamiUitOpen 16:cbb726ac20d8 382 }
MikamiUitOpen 16:cbb726ac20d8 383
MikamiUitOpen 16:cbb726ac20d8 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 385 {
MikamiUitOpen 16:cbb726ac20d8 386 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 387
MikamiUitOpen 16:cbb726ac20d8 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 389 return(result);
MikamiUitOpen 16:cbb726ac20d8 390 }
MikamiUitOpen 16:cbb726ac20d8 391
MikamiUitOpen 16:cbb726ac20d8 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 393 {
MikamiUitOpen 16:cbb726ac20d8 394 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 395
MikamiUitOpen 16:cbb726ac20d8 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 397 return(result);
MikamiUitOpen 16:cbb726ac20d8 398 }
MikamiUitOpen 16:cbb726ac20d8 399
MikamiUitOpen 16:cbb726ac20d8 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 401 {
MikamiUitOpen 16:cbb726ac20d8 402 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 403
MikamiUitOpen 16:cbb726ac20d8 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 405 return(result);
MikamiUitOpen 16:cbb726ac20d8 406 }
MikamiUitOpen 16:cbb726ac20d8 407
MikamiUitOpen 16:cbb726ac20d8 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 409 {
MikamiUitOpen 16:cbb726ac20d8 410 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 411
MikamiUitOpen 16:cbb726ac20d8 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 413 return(result);
MikamiUitOpen 16:cbb726ac20d8 414 }
MikamiUitOpen 16:cbb726ac20d8 415
MikamiUitOpen 16:cbb726ac20d8 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 417 {
MikamiUitOpen 16:cbb726ac20d8 418 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 419
MikamiUitOpen 16:cbb726ac20d8 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 421 return(result);
MikamiUitOpen 16:cbb726ac20d8 422 }
MikamiUitOpen 16:cbb726ac20d8 423
MikamiUitOpen 16:cbb726ac20d8 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 425 {
MikamiUitOpen 16:cbb726ac20d8 426 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 427
MikamiUitOpen 16:cbb726ac20d8 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 429 return(result);
MikamiUitOpen 16:cbb726ac20d8 430 }
MikamiUitOpen 16:cbb726ac20d8 431
MikamiUitOpen 16:cbb726ac20d8 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 433 {
MikamiUitOpen 16:cbb726ac20d8 434 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 435
MikamiUitOpen 16:cbb726ac20d8 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 437 return(result);
MikamiUitOpen 16:cbb726ac20d8 438 }
MikamiUitOpen 16:cbb726ac20d8 439
MikamiUitOpen 16:cbb726ac20d8 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 441 {
MikamiUitOpen 16:cbb726ac20d8 442 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 443
MikamiUitOpen 16:cbb726ac20d8 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 445 return(result);
MikamiUitOpen 16:cbb726ac20d8 446 }
MikamiUitOpen 16:cbb726ac20d8 447
MikamiUitOpen 16:cbb726ac20d8 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 449 {
MikamiUitOpen 16:cbb726ac20d8 450 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 451
MikamiUitOpen 16:cbb726ac20d8 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 453 return(result);
MikamiUitOpen 16:cbb726ac20d8 454 }
MikamiUitOpen 16:cbb726ac20d8 455
MikamiUitOpen 16:cbb726ac20d8 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 16:cbb726ac20d8 457 {
MikamiUitOpen 16:cbb726ac20d8 458 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 459
MikamiUitOpen 16:cbb726ac20d8 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 16:cbb726ac20d8 461 return(result);
MikamiUitOpen 16:cbb726ac20d8 462 }
MikamiUitOpen 16:cbb726ac20d8 463
MikamiUitOpen 16:cbb726ac20d8 464 #define __SSAT16(ARG1,ARG2) \
MikamiUitOpen 16:cbb726ac20d8 465 ({ \
MikamiUitOpen 16:cbb726ac20d8 466 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 16:cbb726ac20d8 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 16:cbb726ac20d8 468 __RES; \
MikamiUitOpen 16:cbb726ac20d8 469 })
MikamiUitOpen 16:cbb726ac20d8 470
MikamiUitOpen 16:cbb726ac20d8 471 #define __USAT16(ARG1,ARG2) \
MikamiUitOpen 16:cbb726ac20d8 472 ({ \
MikamiUitOpen 16:cbb726ac20d8 473 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 16:cbb726ac20d8 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 16:cbb726ac20d8 475 __RES; \
MikamiUitOpen 16:cbb726ac20d8 476 })
MikamiUitOpen 16:cbb726ac20d8 477
MikamiUitOpen 16:cbb726ac20d8 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
MikamiUitOpen 16:cbb726ac20d8 479 {
MikamiUitOpen 16:cbb726ac20d8 480 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 481
MikamiUitOpen 16:cbb726ac20d8 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 16:cbb726ac20d8 483 return(result);
MikamiUitOpen 16:cbb726ac20d8 484 }
MikamiUitOpen 16:cbb726ac20d8 485
MikamiUitOpen 16:cbb726ac20d8 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 487 {
MikamiUitOpen 16:cbb726ac20d8 488 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 489
MikamiUitOpen 16:cbb726ac20d8 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 491 return(result);
MikamiUitOpen 16:cbb726ac20d8 492 }
MikamiUitOpen 16:cbb726ac20d8 493
MikamiUitOpen 16:cbb726ac20d8 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
MikamiUitOpen 16:cbb726ac20d8 495 {
MikamiUitOpen 16:cbb726ac20d8 496 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 497
MikamiUitOpen 16:cbb726ac20d8 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 16:cbb726ac20d8 499 return(result);
MikamiUitOpen 16:cbb726ac20d8 500 }
MikamiUitOpen 16:cbb726ac20d8 501
MikamiUitOpen 16:cbb726ac20d8 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 503 {
MikamiUitOpen 16:cbb726ac20d8 504 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 505
MikamiUitOpen 16:cbb726ac20d8 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 507 return(result);
MikamiUitOpen 16:cbb726ac20d8 508 }
MikamiUitOpen 16:cbb726ac20d8 509
MikamiUitOpen 16:cbb726ac20d8 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 511 {
MikamiUitOpen 16:cbb726ac20d8 512 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 513
MikamiUitOpen 16:cbb726ac20d8 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 515 return(result);
MikamiUitOpen 16:cbb726ac20d8 516 }
MikamiUitOpen 16:cbb726ac20d8 517
MikamiUitOpen 16:cbb726ac20d8 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 519 {
MikamiUitOpen 16:cbb726ac20d8 520 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 521
MikamiUitOpen 16:cbb726ac20d8 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 523 return(result);
MikamiUitOpen 16:cbb726ac20d8 524 }
MikamiUitOpen 16:cbb726ac20d8 525
MikamiUitOpen 16:cbb726ac20d8 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 16:cbb726ac20d8 527 {
MikamiUitOpen 16:cbb726ac20d8 528 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 529
MikamiUitOpen 16:cbb726ac20d8 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 16:cbb726ac20d8 531 return(result);
MikamiUitOpen 16:cbb726ac20d8 532 }
MikamiUitOpen 16:cbb726ac20d8 533
MikamiUitOpen 16:cbb726ac20d8 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 16:cbb726ac20d8 535 {
MikamiUitOpen 16:cbb726ac20d8 536 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 537
MikamiUitOpen 16:cbb726ac20d8 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 16:cbb726ac20d8 539 return(result);
MikamiUitOpen 16:cbb726ac20d8 540 }
MikamiUitOpen 16:cbb726ac20d8 541
MikamiUitOpen 16:cbb726ac20d8 542 #define __SMLALD(ARG1,ARG2,ARG3) \
MikamiUitOpen 16:cbb726ac20d8 543 ({ \
MikamiUitOpen 16:cbb726ac20d8 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 16:cbb726ac20d8 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 16:cbb726ac20d8 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 16:cbb726ac20d8 547 })
MikamiUitOpen 16:cbb726ac20d8 548
MikamiUitOpen 16:cbb726ac20d8 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
MikamiUitOpen 16:cbb726ac20d8 550 ({ \
MikamiUitOpen 16:cbb726ac20d8 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 16:cbb726ac20d8 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 16:cbb726ac20d8 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 16:cbb726ac20d8 554 })
MikamiUitOpen 16:cbb726ac20d8 555
MikamiUitOpen 16:cbb726ac20d8 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 557 {
MikamiUitOpen 16:cbb726ac20d8 558 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 559
MikamiUitOpen 16:cbb726ac20d8 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 561 return(result);
MikamiUitOpen 16:cbb726ac20d8 562 }
MikamiUitOpen 16:cbb726ac20d8 563
MikamiUitOpen 16:cbb726ac20d8 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 565 {
MikamiUitOpen 16:cbb726ac20d8 566 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 567
MikamiUitOpen 16:cbb726ac20d8 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 569 return(result);
MikamiUitOpen 16:cbb726ac20d8 570 }
MikamiUitOpen 16:cbb726ac20d8 571
MikamiUitOpen 16:cbb726ac20d8 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 16:cbb726ac20d8 573 {
MikamiUitOpen 16:cbb726ac20d8 574 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 575
MikamiUitOpen 16:cbb726ac20d8 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 16:cbb726ac20d8 577 return(result);
MikamiUitOpen 16:cbb726ac20d8 578 }
MikamiUitOpen 16:cbb726ac20d8 579
MikamiUitOpen 16:cbb726ac20d8 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 16:cbb726ac20d8 581 {
MikamiUitOpen 16:cbb726ac20d8 582 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 583
MikamiUitOpen 16:cbb726ac20d8 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 16:cbb726ac20d8 585 return(result);
MikamiUitOpen 16:cbb726ac20d8 586 }
MikamiUitOpen 16:cbb726ac20d8 587
MikamiUitOpen 16:cbb726ac20d8 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
MikamiUitOpen 16:cbb726ac20d8 589 ({ \
MikamiUitOpen 16:cbb726ac20d8 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 16:cbb726ac20d8 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 16:cbb726ac20d8 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 16:cbb726ac20d8 593 })
MikamiUitOpen 16:cbb726ac20d8 594
MikamiUitOpen 16:cbb726ac20d8 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
MikamiUitOpen 16:cbb726ac20d8 596 ({ \
MikamiUitOpen 16:cbb726ac20d8 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 16:cbb726ac20d8 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 16:cbb726ac20d8 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 16:cbb726ac20d8 600 })
MikamiUitOpen 16:cbb726ac20d8 601
MikamiUitOpen 16:cbb726ac20d8 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 603 {
MikamiUitOpen 16:cbb726ac20d8 604 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 605
MikamiUitOpen 16:cbb726ac20d8 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 607 return(result);
MikamiUitOpen 16:cbb726ac20d8 608 }
MikamiUitOpen 16:cbb726ac20d8 609
MikamiUitOpen 16:cbb726ac20d8 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 611 {
MikamiUitOpen 16:cbb726ac20d8 612 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 613
MikamiUitOpen 16:cbb726ac20d8 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 615 return(result);
MikamiUitOpen 16:cbb726ac20d8 616 }
MikamiUitOpen 16:cbb726ac20d8 617
MikamiUitOpen 16:cbb726ac20d8 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
MikamiUitOpen 16:cbb726ac20d8 619 {
MikamiUitOpen 16:cbb726ac20d8 620 uint32_t result;
MikamiUitOpen 16:cbb726ac20d8 621
MikamiUitOpen 16:cbb726ac20d8 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 16:cbb726ac20d8 623 return(result);
MikamiUitOpen 16:cbb726ac20d8 624 }
MikamiUitOpen 16:cbb726ac20d8 625
MikamiUitOpen 16:cbb726ac20d8 626 #define __PKHBT(ARG1,ARG2,ARG3) \
MikamiUitOpen 16:cbb726ac20d8 627 ({ \
MikamiUitOpen 16:cbb726ac20d8 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 16:cbb726ac20d8 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 16:cbb726ac20d8 630 __RES; \
MikamiUitOpen 16:cbb726ac20d8 631 })
MikamiUitOpen 16:cbb726ac20d8 632
MikamiUitOpen 16:cbb726ac20d8 633 #define __PKHTB(ARG1,ARG2,ARG3) \
MikamiUitOpen 16:cbb726ac20d8 634 ({ \
MikamiUitOpen 16:cbb726ac20d8 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 16:cbb726ac20d8 636 if (ARG3 == 0) \
MikamiUitOpen 16:cbb726ac20d8 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
MikamiUitOpen 16:cbb726ac20d8 638 else \
MikamiUitOpen 16:cbb726ac20d8 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 16:cbb726ac20d8 640 __RES; \
MikamiUitOpen 16:cbb726ac20d8 641 })
MikamiUitOpen 16:cbb726ac20d8 642
MikamiUitOpen 16:cbb726ac20d8 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
MikamiUitOpen 16:cbb726ac20d8 644 {
MikamiUitOpen 16:cbb726ac20d8 645 int32_t result;
MikamiUitOpen 16:cbb726ac20d8 646
MikamiUitOpen 16:cbb726ac20d8 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 16:cbb726ac20d8 648 return(result);
MikamiUitOpen 16:cbb726ac20d8 649 }
MikamiUitOpen 16:cbb726ac20d8 650
MikamiUitOpen 16:cbb726ac20d8 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 652
MikamiUitOpen 16:cbb726ac20d8 653
MikamiUitOpen 16:cbb726ac20d8 654
MikamiUitOpen 16:cbb726ac20d8 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 16:cbb726ac20d8 656 /* TASKING carm specific functions */
MikamiUitOpen 16:cbb726ac20d8 657
MikamiUitOpen 16:cbb726ac20d8 658
MikamiUitOpen 16:cbb726ac20d8 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 660 /* not yet supported */
MikamiUitOpen 16:cbb726ac20d8 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 662
MikamiUitOpen 16:cbb726ac20d8 663
MikamiUitOpen 16:cbb726ac20d8 664 #endif
MikamiUitOpen 16:cbb726ac20d8 665
MikamiUitOpen 16:cbb726ac20d8 666 /*@} end of group CMSIS_SIMD_intrinsics */
MikamiUitOpen 16:cbb726ac20d8 667
MikamiUitOpen 16:cbb726ac20d8 668
MikamiUitOpen 16:cbb726ac20d8 669 #endif /* __CORE_CM4_SIMD_H */
MikamiUitOpen 16:cbb726ac20d8 670
MikamiUitOpen 16:cbb726ac20d8 671 #ifdef __cplusplus
MikamiUitOpen 16:cbb726ac20d8 672 }
MikamiUitOpen 16:cbb726ac20d8 673 #endif