不韋 呂 / F746_SD_GraphicEqualizer

Output the audio signal with filtering by graphic equalizer in the *.wav file on the SD card using onboard CODEC. SD カードの *.wav ファイルのオーディオ信号をグラフィック･イコライザを通して，ボードに搭載されているCODEC で出力する．

Dependencies:   F746_GUI F746_SAI_IO SD_PlayerSkeleton FrequencyResponseDrawer

mbed_src_STM32F7/targets/cmsis/core_cm0plus.h@24:f78f9d0ac262, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 04:07:35 2017 +0000
Revision:
24:f78f9d0ac262
Parent:
16:cbb726ac20d8 
25

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 16:cbb726ac20d8 1 /**************************************************************************//**
MikamiUitOpen 16:cbb726ac20d8 2 * @file core_cm0plus.h
MikamiUitOpen 16:cbb726ac20d8 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
MikamiUitOpen 16:cbb726ac20d8 4 * @version V4.10
MikamiUitOpen 16:cbb726ac20d8 5 * @date 18. March 2015
MikamiUitOpen 16:cbb726ac20d8 6 *
MikamiUitOpen 16:cbb726ac20d8 7 * @note
MikamiUitOpen 16:cbb726ac20d8 8 *
MikamiUitOpen 16:cbb726ac20d8 9 ******************************************************************************/
MikamiUitOpen 16:cbb726ac20d8 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 16:cbb726ac20d8 11
MikamiUitOpen 16:cbb726ac20d8 12 All rights reserved.
MikamiUitOpen 16:cbb726ac20d8 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 16:cbb726ac20d8 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 16:cbb726ac20d8 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 16:cbb726ac20d8 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 16:cbb726ac20d8 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 16:cbb726ac20d8 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 16:cbb726ac20d8 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 16:cbb726ac20d8 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 16:cbb726ac20d8 21 to endorse or promote products derived from this software without
MikamiUitOpen 16:cbb726ac20d8 22 specific prior written permission.
MikamiUitOpen 16:cbb726ac20d8 23 *
MikamiUitOpen 16:cbb726ac20d8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 16:cbb726ac20d8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 16:cbb726ac20d8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 16:cbb726ac20d8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 16:cbb726ac20d8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 16:cbb726ac20d8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 16:cbb726ac20d8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 16:cbb726ac20d8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 16:cbb726ac20d8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 16:cbb726ac20d8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 16:cbb726ac20d8 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 16:cbb726ac20d8 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 16:cbb726ac20d8 36
MikamiUitOpen 16:cbb726ac20d8 37
MikamiUitOpen 16:cbb726ac20d8 38 #if defined ( __ICCARM__ )
MikamiUitOpen 16:cbb726ac20d8 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 16:cbb726ac20d8 40 #endif
MikamiUitOpen 16:cbb726ac20d8 41
MikamiUitOpen 16:cbb726ac20d8 42 #ifndef __CORE_CM0PLUS_H_GENERIC
MikamiUitOpen 16:cbb726ac20d8 43 #define __CORE_CM0PLUS_H_GENERIC
MikamiUitOpen 16:cbb726ac20d8 44
MikamiUitOpen 16:cbb726ac20d8 45 #ifdef __cplusplus
MikamiUitOpen 16:cbb726ac20d8 46 extern "C" {
MikamiUitOpen 16:cbb726ac20d8 47 #endif
MikamiUitOpen 16:cbb726ac20d8 48
MikamiUitOpen 16:cbb726ac20d8 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen 16:cbb726ac20d8 50 CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen 16:cbb726ac20d8 51
MikamiUitOpen 16:cbb726ac20d8 52 \li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen 16:cbb726ac20d8 53 Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen 16:cbb726ac20d8 54
MikamiUitOpen 16:cbb726ac20d8 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen 16:cbb726ac20d8 56 Unions are used for effective representation of core registers.
MikamiUitOpen 16:cbb726ac20d8 57
MikamiUitOpen 16:cbb726ac20d8 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen 16:cbb726ac20d8 59 Function-like macros are used to allow more efficient code.
MikamiUitOpen 16:cbb726ac20d8 60 */
MikamiUitOpen 16:cbb726ac20d8 61
MikamiUitOpen 16:cbb726ac20d8 62
MikamiUitOpen 16:cbb726ac20d8 63 /*******************************************************************************
MikamiUitOpen 16:cbb726ac20d8 64 * CMSIS definitions
MikamiUitOpen 16:cbb726ac20d8 65 ******************************************************************************/
MikamiUitOpen 16:cbb726ac20d8 66 /** \ingroup Cortex-M0+
MikamiUitOpen 16:cbb726ac20d8 67 @{
MikamiUitOpen 16:cbb726ac20d8 68 */
MikamiUitOpen 16:cbb726ac20d8 69
MikamiUitOpen 16:cbb726ac20d8 70 /* CMSIS CM0P definitions */
MikamiUitOpen 16:cbb726ac20d8 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
MikamiUitOpen 16:cbb726ac20d8 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
MikamiUitOpen 16:cbb726ac20d8 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
MikamiUitOpen 16:cbb726ac20d8 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
MikamiUitOpen 16:cbb726ac20d8 75
MikamiUitOpen 16:cbb726ac20d8 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
MikamiUitOpen 16:cbb726ac20d8 77
MikamiUitOpen 16:cbb726ac20d8 78
MikamiUitOpen 16:cbb726ac20d8 79 #if defined ( __CC_ARM )
MikamiUitOpen 16:cbb726ac20d8 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
MikamiUitOpen 16:cbb726ac20d8 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
MikamiUitOpen 16:cbb726ac20d8 82 #define __STATIC_INLINE static __inline
MikamiUitOpen 16:cbb726ac20d8 83
MikamiUitOpen 16:cbb726ac20d8 84 #elif defined ( __GNUC__ )
MikamiUitOpen 16:cbb726ac20d8 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
MikamiUitOpen 16:cbb726ac20d8 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
MikamiUitOpen 16:cbb726ac20d8 87 #define __STATIC_INLINE static inline
MikamiUitOpen 16:cbb726ac20d8 88
MikamiUitOpen 16:cbb726ac20d8 89 #elif defined ( __ICCARM__ )
MikamiUitOpen 16:cbb726ac20d8 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
MikamiUitOpen 16:cbb726ac20d8 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
MikamiUitOpen 16:cbb726ac20d8 92 #define __STATIC_INLINE static inline
MikamiUitOpen 16:cbb726ac20d8 93
MikamiUitOpen 16:cbb726ac20d8 94 #elif defined ( __TMS470__ )
MikamiUitOpen 16:cbb726ac20d8 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
MikamiUitOpen 16:cbb726ac20d8 96 #define __STATIC_INLINE static inline
MikamiUitOpen 16:cbb726ac20d8 97
MikamiUitOpen 16:cbb726ac20d8 98 #elif defined ( __TASKING__ )
MikamiUitOpen 16:cbb726ac20d8 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
MikamiUitOpen 16:cbb726ac20d8 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
MikamiUitOpen 16:cbb726ac20d8 101 #define __STATIC_INLINE static inline
MikamiUitOpen 16:cbb726ac20d8 102
MikamiUitOpen 16:cbb726ac20d8 103 #elif defined ( __CSMC__ )
MikamiUitOpen 16:cbb726ac20d8 104 #define __packed
MikamiUitOpen 16:cbb726ac20d8 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
MikamiUitOpen 16:cbb726ac20d8 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
MikamiUitOpen 16:cbb726ac20d8 107 #define __STATIC_INLINE static inline
MikamiUitOpen 16:cbb726ac20d8 108
MikamiUitOpen 16:cbb726ac20d8 109 #endif
MikamiUitOpen 16:cbb726ac20d8 110
MikamiUitOpen 16:cbb726ac20d8 111 /** __FPU_USED indicates whether an FPU is used or not.
MikamiUitOpen 16:cbb726ac20d8 112 This core does not support an FPU at all
MikamiUitOpen 16:cbb726ac20d8 113 */
MikamiUitOpen 16:cbb726ac20d8 114 #define __FPU_USED 0
MikamiUitOpen 16:cbb726ac20d8 115
MikamiUitOpen 16:cbb726ac20d8 116 #if defined ( __CC_ARM )
MikamiUitOpen 16:cbb726ac20d8 117 #if defined __TARGET_FPU_VFP
MikamiUitOpen 16:cbb726ac20d8 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 16:cbb726ac20d8 119 #endif
MikamiUitOpen 16:cbb726ac20d8 120
MikamiUitOpen 16:cbb726ac20d8 121 #elif defined ( __GNUC__ )
MikamiUitOpen 16:cbb726ac20d8 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen 16:cbb726ac20d8 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 16:cbb726ac20d8 124 #endif
MikamiUitOpen 16:cbb726ac20d8 125
MikamiUitOpen 16:cbb726ac20d8 126 #elif defined ( __ICCARM__ )
MikamiUitOpen 16:cbb726ac20d8 127 #if defined __ARMVFP__
MikamiUitOpen 16:cbb726ac20d8 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 16:cbb726ac20d8 129 #endif
MikamiUitOpen 16:cbb726ac20d8 130
MikamiUitOpen 16:cbb726ac20d8 131 #elif defined ( __TMS470__ )
MikamiUitOpen 16:cbb726ac20d8 132 #if defined __TI__VFP_SUPPORT____
MikamiUitOpen 16:cbb726ac20d8 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 16:cbb726ac20d8 134 #endif
MikamiUitOpen 16:cbb726ac20d8 135
MikamiUitOpen 16:cbb726ac20d8 136 #elif defined ( __TASKING__ )
MikamiUitOpen 16:cbb726ac20d8 137 #if defined __FPU_VFP__
MikamiUitOpen 16:cbb726ac20d8 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 16:cbb726ac20d8 139 #endif
MikamiUitOpen 16:cbb726ac20d8 140
MikamiUitOpen 16:cbb726ac20d8 141 #elif defined ( __CSMC__ ) /* Cosmic */
MikamiUitOpen 16:cbb726ac20d8 142 #if ( __CSMC__ & 0x400) // FPU present for parser
MikamiUitOpen 16:cbb726ac20d8 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 16:cbb726ac20d8 144 #endif
MikamiUitOpen 16:cbb726ac20d8 145 #endif
MikamiUitOpen 16:cbb726ac20d8 146
MikamiUitOpen 16:cbb726ac20d8 147 #include <stdint.h> /* standard types definitions */
MikamiUitOpen 16:cbb726ac20d8 148 #include <core_cmInstr.h> /* Core Instruction Access */
MikamiUitOpen 16:cbb726ac20d8 149 #include <core_cmFunc.h> /* Core Function Access */
MikamiUitOpen 16:cbb726ac20d8 150
MikamiUitOpen 16:cbb726ac20d8 151 #ifdef __cplusplus
MikamiUitOpen 16:cbb726ac20d8 152 }
MikamiUitOpen 16:cbb726ac20d8 153 #endif
MikamiUitOpen 16:cbb726ac20d8 154
MikamiUitOpen 16:cbb726ac20d8 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
MikamiUitOpen 16:cbb726ac20d8 156
MikamiUitOpen 16:cbb726ac20d8 157 #ifndef __CMSIS_GENERIC
MikamiUitOpen 16:cbb726ac20d8 158
MikamiUitOpen 16:cbb726ac20d8 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
MikamiUitOpen 16:cbb726ac20d8 160 #define __CORE_CM0PLUS_H_DEPENDANT
MikamiUitOpen 16:cbb726ac20d8 161
MikamiUitOpen 16:cbb726ac20d8 162 #ifdef __cplusplus
MikamiUitOpen 16:cbb726ac20d8 163 extern "C" {
MikamiUitOpen 16:cbb726ac20d8 164 #endif
MikamiUitOpen 16:cbb726ac20d8 165
MikamiUitOpen 16:cbb726ac20d8 166 /* check device defines and use defaults */
MikamiUitOpen 16:cbb726ac20d8 167 #if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen 16:cbb726ac20d8 168 #ifndef __CM0PLUS_REV
MikamiUitOpen 16:cbb726ac20d8 169 #define __CM0PLUS_REV 0x0000
MikamiUitOpen 16:cbb726ac20d8 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
MikamiUitOpen 16:cbb726ac20d8 171 #endif
MikamiUitOpen 16:cbb726ac20d8 172
MikamiUitOpen 16:cbb726ac20d8 173 #ifndef __MPU_PRESENT
MikamiUitOpen 16:cbb726ac20d8 174 #define __MPU_PRESENT 0
MikamiUitOpen 16:cbb726ac20d8 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen 16:cbb726ac20d8 176 #endif
MikamiUitOpen 16:cbb726ac20d8 177
MikamiUitOpen 16:cbb726ac20d8 178 #ifndef __VTOR_PRESENT
MikamiUitOpen 16:cbb726ac20d8 179 #define __VTOR_PRESENT 0
MikamiUitOpen 16:cbb726ac20d8 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
MikamiUitOpen 16:cbb726ac20d8 181 #endif
MikamiUitOpen 16:cbb726ac20d8 182
MikamiUitOpen 16:cbb726ac20d8 183 #ifndef __NVIC_PRIO_BITS
MikamiUitOpen 16:cbb726ac20d8 184 #define __NVIC_PRIO_BITS 2
MikamiUitOpen 16:cbb726ac20d8 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
MikamiUitOpen 16:cbb726ac20d8 186 #endif
MikamiUitOpen 16:cbb726ac20d8 187
MikamiUitOpen 16:cbb726ac20d8 188 #ifndef __Vendor_SysTickConfig
MikamiUitOpen 16:cbb726ac20d8 189 #define __Vendor_SysTickConfig 0
MikamiUitOpen 16:cbb726ac20d8 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
MikamiUitOpen 16:cbb726ac20d8 191 #endif
MikamiUitOpen 16:cbb726ac20d8 192 #endif
MikamiUitOpen 16:cbb726ac20d8 193
MikamiUitOpen 16:cbb726ac20d8 194 /* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen 16:cbb726ac20d8 195 /**
MikamiUitOpen 16:cbb726ac20d8 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen 16:cbb726ac20d8 197
MikamiUitOpen 16:cbb726ac20d8 198 <strong>IO Type Qualifiers</strong> are used
MikamiUitOpen 16:cbb726ac20d8 199 \li to specify the access to peripheral variables.
MikamiUitOpen 16:cbb726ac20d8 200 \li for automatic generation of peripheral register debug information.
MikamiUitOpen 16:cbb726ac20d8 201 */
MikamiUitOpen 16:cbb726ac20d8 202 #ifdef __cplusplus
MikamiUitOpen 16:cbb726ac20d8 203 #define __I volatile /*!< Defines 'read only' permissions */
MikamiUitOpen 16:cbb726ac20d8 204 #else
MikamiUitOpen 16:cbb726ac20d8 205 #define __I volatile const /*!< Defines 'read only' permissions */
MikamiUitOpen 16:cbb726ac20d8 206 #endif
MikamiUitOpen 16:cbb726ac20d8 207 #define __O volatile /*!< Defines 'write only' permissions */
MikamiUitOpen 16:cbb726ac20d8 208 #define __IO volatile /*!< Defines 'read / write' permissions */
MikamiUitOpen 16:cbb726ac20d8 209
MikamiUitOpen 16:cbb726ac20d8 210 /*@} end of group Cortex-M0+ */
MikamiUitOpen 16:cbb726ac20d8 211
MikamiUitOpen 16:cbb726ac20d8 212
MikamiUitOpen 16:cbb726ac20d8 213
MikamiUitOpen 16:cbb726ac20d8 214 /*******************************************************************************
MikamiUitOpen 16:cbb726ac20d8 215 * Register Abstraction
MikamiUitOpen 16:cbb726ac20d8 216 Core Register contain:
MikamiUitOpen 16:cbb726ac20d8 217 - Core Register
MikamiUitOpen 16:cbb726ac20d8 218 - Core NVIC Register
MikamiUitOpen 16:cbb726ac20d8 219 - Core SCB Register
MikamiUitOpen 16:cbb726ac20d8 220 - Core SysTick Register
MikamiUitOpen 16:cbb726ac20d8 221 - Core MPU Register
MikamiUitOpen 16:cbb726ac20d8 222 ******************************************************************************/
MikamiUitOpen 16:cbb726ac20d8 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen 16:cbb726ac20d8 224 \brief Type definitions and defines for Cortex-M processor based devices.
MikamiUitOpen 16:cbb726ac20d8 225 */
MikamiUitOpen 16:cbb726ac20d8 226
MikamiUitOpen 16:cbb726ac20d8 227 /** \ingroup CMSIS_core_register
MikamiUitOpen 16:cbb726ac20d8 228 \defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen 16:cbb726ac20d8 229 \brief Core Register type definitions.
MikamiUitOpen 16:cbb726ac20d8 230 @{
MikamiUitOpen 16:cbb726ac20d8 231 */
MikamiUitOpen 16:cbb726ac20d8 232
MikamiUitOpen 16:cbb726ac20d8 233 /** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen 16:cbb726ac20d8 234 */
MikamiUitOpen 16:cbb726ac20d8 235 typedef union
MikamiUitOpen 16:cbb726ac20d8 236 {
MikamiUitOpen 16:cbb726ac20d8 237 struct
MikamiUitOpen 16:cbb726ac20d8 238 {
MikamiUitOpen 16:cbb726ac20d8 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
MikamiUitOpen 16:cbb726ac20d8 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 16:cbb726ac20d8 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 16:cbb726ac20d8 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 16:cbb726ac20d8 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 16:cbb726ac20d8 244 } b; /*!< Structure used for bit access */
MikamiUitOpen 16:cbb726ac20d8 245 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 16:cbb726ac20d8 246 } APSR_Type;
MikamiUitOpen 16:cbb726ac20d8 247
MikamiUitOpen 16:cbb726ac20d8 248 /* APSR Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
MikamiUitOpen 16:cbb726ac20d8 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
MikamiUitOpen 16:cbb726ac20d8 251
MikamiUitOpen 16:cbb726ac20d8 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
MikamiUitOpen 16:cbb726ac20d8 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
MikamiUitOpen 16:cbb726ac20d8 254
MikamiUitOpen 16:cbb726ac20d8 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
MikamiUitOpen 16:cbb726ac20d8 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
MikamiUitOpen 16:cbb726ac20d8 257
MikamiUitOpen 16:cbb726ac20d8 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
MikamiUitOpen 16:cbb726ac20d8 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
MikamiUitOpen 16:cbb726ac20d8 260
MikamiUitOpen 16:cbb726ac20d8 261
MikamiUitOpen 16:cbb726ac20d8 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
MikamiUitOpen 16:cbb726ac20d8 263 */
MikamiUitOpen 16:cbb726ac20d8 264 typedef union
MikamiUitOpen 16:cbb726ac20d8 265 {
MikamiUitOpen 16:cbb726ac20d8 266 struct
MikamiUitOpen 16:cbb726ac20d8 267 {
MikamiUitOpen 16:cbb726ac20d8 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 16:cbb726ac20d8 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
MikamiUitOpen 16:cbb726ac20d8 270 } b; /*!< Structure used for bit access */
MikamiUitOpen 16:cbb726ac20d8 271 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 16:cbb726ac20d8 272 } IPSR_Type;
MikamiUitOpen 16:cbb726ac20d8 273
MikamiUitOpen 16:cbb726ac20d8 274 /* IPSR Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
MikamiUitOpen 16:cbb726ac20d8 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
MikamiUitOpen 16:cbb726ac20d8 277
MikamiUitOpen 16:cbb726ac20d8 278
MikamiUitOpen 16:cbb726ac20d8 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
MikamiUitOpen 16:cbb726ac20d8 280 */
MikamiUitOpen 16:cbb726ac20d8 281 typedef union
MikamiUitOpen 16:cbb726ac20d8 282 {
MikamiUitOpen 16:cbb726ac20d8 283 struct
MikamiUitOpen 16:cbb726ac20d8 284 {
MikamiUitOpen 16:cbb726ac20d8 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 16:cbb726ac20d8 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
MikamiUitOpen 16:cbb726ac20d8 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
MikamiUitOpen 16:cbb726ac20d8 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
MikamiUitOpen 16:cbb726ac20d8 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 16:cbb726ac20d8 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 16:cbb726ac20d8 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 16:cbb726ac20d8 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 16:cbb726ac20d8 293 } b; /*!< Structure used for bit access */
MikamiUitOpen 16:cbb726ac20d8 294 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 16:cbb726ac20d8 295 } xPSR_Type;
MikamiUitOpen 16:cbb726ac20d8 296
MikamiUitOpen 16:cbb726ac20d8 297 /* xPSR Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
MikamiUitOpen 16:cbb726ac20d8 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
MikamiUitOpen 16:cbb726ac20d8 300
MikamiUitOpen 16:cbb726ac20d8 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
MikamiUitOpen 16:cbb726ac20d8 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
MikamiUitOpen 16:cbb726ac20d8 303
MikamiUitOpen 16:cbb726ac20d8 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
MikamiUitOpen 16:cbb726ac20d8 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
MikamiUitOpen 16:cbb726ac20d8 306
MikamiUitOpen 16:cbb726ac20d8 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
MikamiUitOpen 16:cbb726ac20d8 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
MikamiUitOpen 16:cbb726ac20d8 309
MikamiUitOpen 16:cbb726ac20d8 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
MikamiUitOpen 16:cbb726ac20d8 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
MikamiUitOpen 16:cbb726ac20d8 312
MikamiUitOpen 16:cbb726ac20d8 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
MikamiUitOpen 16:cbb726ac20d8 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
MikamiUitOpen 16:cbb726ac20d8 315
MikamiUitOpen 16:cbb726ac20d8 316
MikamiUitOpen 16:cbb726ac20d8 317 /** \brief Union type to access the Control Registers (CONTROL).
MikamiUitOpen 16:cbb726ac20d8 318 */
MikamiUitOpen 16:cbb726ac20d8 319 typedef union
MikamiUitOpen 16:cbb726ac20d8 320 {
MikamiUitOpen 16:cbb726ac20d8 321 struct
MikamiUitOpen 16:cbb726ac20d8 322 {
MikamiUitOpen 16:cbb726ac20d8 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
MikamiUitOpen 16:cbb726ac20d8 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
MikamiUitOpen 16:cbb726ac20d8 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
MikamiUitOpen 16:cbb726ac20d8 326 } b; /*!< Structure used for bit access */
MikamiUitOpen 16:cbb726ac20d8 327 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 16:cbb726ac20d8 328 } CONTROL_Type;
MikamiUitOpen 16:cbb726ac20d8 329
MikamiUitOpen 16:cbb726ac20d8 330 /* CONTROL Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
MikamiUitOpen 16:cbb726ac20d8 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
MikamiUitOpen 16:cbb726ac20d8 333
MikamiUitOpen 16:cbb726ac20d8 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
MikamiUitOpen 16:cbb726ac20d8 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
MikamiUitOpen 16:cbb726ac20d8 336
MikamiUitOpen 16:cbb726ac20d8 337 /*@} end of group CMSIS_CORE */
MikamiUitOpen 16:cbb726ac20d8 338
MikamiUitOpen 16:cbb726ac20d8 339
MikamiUitOpen 16:cbb726ac20d8 340 /** \ingroup CMSIS_core_register
MikamiUitOpen 16:cbb726ac20d8 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
MikamiUitOpen 16:cbb726ac20d8 342 \brief Type definitions for the NVIC Registers
MikamiUitOpen 16:cbb726ac20d8 343 @{
MikamiUitOpen 16:cbb726ac20d8 344 */
MikamiUitOpen 16:cbb726ac20d8 345
MikamiUitOpen 16:cbb726ac20d8 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
MikamiUitOpen 16:cbb726ac20d8 347 */
MikamiUitOpen 16:cbb726ac20d8 348 typedef struct
MikamiUitOpen 16:cbb726ac20d8 349 {
MikamiUitOpen 16:cbb726ac20d8 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
MikamiUitOpen 16:cbb726ac20d8 351 uint32_t RESERVED0[31];
MikamiUitOpen 16:cbb726ac20d8 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
MikamiUitOpen 16:cbb726ac20d8 353 uint32_t RSERVED1[31];
MikamiUitOpen 16:cbb726ac20d8 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
MikamiUitOpen 16:cbb726ac20d8 355 uint32_t RESERVED2[31];
MikamiUitOpen 16:cbb726ac20d8 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
MikamiUitOpen 16:cbb726ac20d8 357 uint32_t RESERVED3[31];
MikamiUitOpen 16:cbb726ac20d8 358 uint32_t RESERVED4[64];
MikamiUitOpen 16:cbb726ac20d8 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
MikamiUitOpen 16:cbb726ac20d8 360 } NVIC_Type;
MikamiUitOpen 16:cbb726ac20d8 361
MikamiUitOpen 16:cbb726ac20d8 362 /*@} end of group CMSIS_NVIC */
MikamiUitOpen 16:cbb726ac20d8 363
MikamiUitOpen 16:cbb726ac20d8 364
MikamiUitOpen 16:cbb726ac20d8 365 /** \ingroup CMSIS_core_register
MikamiUitOpen 16:cbb726ac20d8 366 \defgroup CMSIS_SCB System Control Block (SCB)
MikamiUitOpen 16:cbb726ac20d8 367 \brief Type definitions for the System Control Block Registers
MikamiUitOpen 16:cbb726ac20d8 368 @{
MikamiUitOpen 16:cbb726ac20d8 369 */
MikamiUitOpen 16:cbb726ac20d8 370
MikamiUitOpen 16:cbb726ac20d8 371 /** \brief Structure type to access the System Control Block (SCB).
MikamiUitOpen 16:cbb726ac20d8 372 */
MikamiUitOpen 16:cbb726ac20d8 373 typedef struct
MikamiUitOpen 16:cbb726ac20d8 374 {
MikamiUitOpen 16:cbb726ac20d8 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
MikamiUitOpen 16:cbb726ac20d8 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
MikamiUitOpen 16:cbb726ac20d8 377 #if (__VTOR_PRESENT == 1)
MikamiUitOpen 16:cbb726ac20d8 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
MikamiUitOpen 16:cbb726ac20d8 379 #else
MikamiUitOpen 16:cbb726ac20d8 380 uint32_t RESERVED0;
MikamiUitOpen 16:cbb726ac20d8 381 #endif
MikamiUitOpen 16:cbb726ac20d8 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
MikamiUitOpen 16:cbb726ac20d8 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
MikamiUitOpen 16:cbb726ac20d8 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
MikamiUitOpen 16:cbb726ac20d8 385 uint32_t RESERVED1;
MikamiUitOpen 16:cbb726ac20d8 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
MikamiUitOpen 16:cbb726ac20d8 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
MikamiUitOpen 16:cbb726ac20d8 388 } SCB_Type;
MikamiUitOpen 16:cbb726ac20d8 389
MikamiUitOpen 16:cbb726ac20d8 390 /* SCB CPUID Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
MikamiUitOpen 16:cbb726ac20d8 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
MikamiUitOpen 16:cbb726ac20d8 393
MikamiUitOpen 16:cbb726ac20d8 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
MikamiUitOpen 16:cbb726ac20d8 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
MikamiUitOpen 16:cbb726ac20d8 396
MikamiUitOpen 16:cbb726ac20d8 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
MikamiUitOpen 16:cbb726ac20d8 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
MikamiUitOpen 16:cbb726ac20d8 399
MikamiUitOpen 16:cbb726ac20d8 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
MikamiUitOpen 16:cbb726ac20d8 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
MikamiUitOpen 16:cbb726ac20d8 402
MikamiUitOpen 16:cbb726ac20d8 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
MikamiUitOpen 16:cbb726ac20d8 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
MikamiUitOpen 16:cbb726ac20d8 405
MikamiUitOpen 16:cbb726ac20d8 406 /* SCB Interrupt Control State Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
MikamiUitOpen 16:cbb726ac20d8 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
MikamiUitOpen 16:cbb726ac20d8 409
MikamiUitOpen 16:cbb726ac20d8 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
MikamiUitOpen 16:cbb726ac20d8 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
MikamiUitOpen 16:cbb726ac20d8 412
MikamiUitOpen 16:cbb726ac20d8 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
MikamiUitOpen 16:cbb726ac20d8 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
MikamiUitOpen 16:cbb726ac20d8 415
MikamiUitOpen 16:cbb726ac20d8 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
MikamiUitOpen 16:cbb726ac20d8 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
MikamiUitOpen 16:cbb726ac20d8 418
MikamiUitOpen 16:cbb726ac20d8 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
MikamiUitOpen 16:cbb726ac20d8 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
MikamiUitOpen 16:cbb726ac20d8 421
MikamiUitOpen 16:cbb726ac20d8 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
MikamiUitOpen 16:cbb726ac20d8 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
MikamiUitOpen 16:cbb726ac20d8 424
MikamiUitOpen 16:cbb726ac20d8 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
MikamiUitOpen 16:cbb726ac20d8 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
MikamiUitOpen 16:cbb726ac20d8 427
MikamiUitOpen 16:cbb726ac20d8 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
MikamiUitOpen 16:cbb726ac20d8 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
MikamiUitOpen 16:cbb726ac20d8 430
MikamiUitOpen 16:cbb726ac20d8 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
MikamiUitOpen 16:cbb726ac20d8 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
MikamiUitOpen 16:cbb726ac20d8 433
MikamiUitOpen 16:cbb726ac20d8 434 #if (__VTOR_PRESENT == 1)
MikamiUitOpen 16:cbb726ac20d8 435 /* SCB Interrupt Control State Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
MikamiUitOpen 16:cbb726ac20d8 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
MikamiUitOpen 16:cbb726ac20d8 438 #endif
MikamiUitOpen 16:cbb726ac20d8 439
MikamiUitOpen 16:cbb726ac20d8 440 /* SCB Application Interrupt and Reset Control Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
MikamiUitOpen 16:cbb726ac20d8 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
MikamiUitOpen 16:cbb726ac20d8 443
MikamiUitOpen 16:cbb726ac20d8 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
MikamiUitOpen 16:cbb726ac20d8 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
MikamiUitOpen 16:cbb726ac20d8 446
MikamiUitOpen 16:cbb726ac20d8 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
MikamiUitOpen 16:cbb726ac20d8 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
MikamiUitOpen 16:cbb726ac20d8 449
MikamiUitOpen 16:cbb726ac20d8 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
MikamiUitOpen 16:cbb726ac20d8 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
MikamiUitOpen 16:cbb726ac20d8 452
MikamiUitOpen 16:cbb726ac20d8 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
MikamiUitOpen 16:cbb726ac20d8 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
MikamiUitOpen 16:cbb726ac20d8 455
MikamiUitOpen 16:cbb726ac20d8 456 /* SCB System Control Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
MikamiUitOpen 16:cbb726ac20d8 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
MikamiUitOpen 16:cbb726ac20d8 459
MikamiUitOpen 16:cbb726ac20d8 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
MikamiUitOpen 16:cbb726ac20d8 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
MikamiUitOpen 16:cbb726ac20d8 462
MikamiUitOpen 16:cbb726ac20d8 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
MikamiUitOpen 16:cbb726ac20d8 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
MikamiUitOpen 16:cbb726ac20d8 465
MikamiUitOpen 16:cbb726ac20d8 466 /* SCB Configuration Control Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
MikamiUitOpen 16:cbb726ac20d8 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
MikamiUitOpen 16:cbb726ac20d8 469
MikamiUitOpen 16:cbb726ac20d8 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
MikamiUitOpen 16:cbb726ac20d8 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
MikamiUitOpen 16:cbb726ac20d8 472
MikamiUitOpen 16:cbb726ac20d8 473 /* SCB System Handler Control and State Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
MikamiUitOpen 16:cbb726ac20d8 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
MikamiUitOpen 16:cbb726ac20d8 476
MikamiUitOpen 16:cbb726ac20d8 477 /*@} end of group CMSIS_SCB */
MikamiUitOpen 16:cbb726ac20d8 478
MikamiUitOpen 16:cbb726ac20d8 479
MikamiUitOpen 16:cbb726ac20d8 480 /** \ingroup CMSIS_core_register
MikamiUitOpen 16:cbb726ac20d8 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
MikamiUitOpen 16:cbb726ac20d8 482 \brief Type definitions for the System Timer Registers.
MikamiUitOpen 16:cbb726ac20d8 483 @{
MikamiUitOpen 16:cbb726ac20d8 484 */
MikamiUitOpen 16:cbb726ac20d8 485
MikamiUitOpen 16:cbb726ac20d8 486 /** \brief Structure type to access the System Timer (SysTick).
MikamiUitOpen 16:cbb726ac20d8 487 */
MikamiUitOpen 16:cbb726ac20d8 488 typedef struct
MikamiUitOpen 16:cbb726ac20d8 489 {
MikamiUitOpen 16:cbb726ac20d8 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
MikamiUitOpen 16:cbb726ac20d8 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
MikamiUitOpen 16:cbb726ac20d8 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
MikamiUitOpen 16:cbb726ac20d8 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
MikamiUitOpen 16:cbb726ac20d8 494 } SysTick_Type;
MikamiUitOpen 16:cbb726ac20d8 495
MikamiUitOpen 16:cbb726ac20d8 496 /* SysTick Control / Status Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
MikamiUitOpen 16:cbb726ac20d8 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
MikamiUitOpen 16:cbb726ac20d8 499
MikamiUitOpen 16:cbb726ac20d8 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
MikamiUitOpen 16:cbb726ac20d8 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
MikamiUitOpen 16:cbb726ac20d8 502
MikamiUitOpen 16:cbb726ac20d8 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
MikamiUitOpen 16:cbb726ac20d8 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
MikamiUitOpen 16:cbb726ac20d8 505
MikamiUitOpen 16:cbb726ac20d8 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
MikamiUitOpen 16:cbb726ac20d8 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
MikamiUitOpen 16:cbb726ac20d8 508
MikamiUitOpen 16:cbb726ac20d8 509 /* SysTick Reload Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
MikamiUitOpen 16:cbb726ac20d8 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
MikamiUitOpen 16:cbb726ac20d8 512
MikamiUitOpen 16:cbb726ac20d8 513 /* SysTick Current Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
MikamiUitOpen 16:cbb726ac20d8 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
MikamiUitOpen 16:cbb726ac20d8 516
MikamiUitOpen 16:cbb726ac20d8 517 /* SysTick Calibration Register Definitions */
MikamiUitOpen 16:cbb726ac20d8 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
MikamiUitOpen 16:cbb726ac20d8 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
MikamiUitOpen 16:cbb726ac20d8 520
MikamiUitOpen 16:cbb726ac20d8 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
MikamiUitOpen 16:cbb726ac20d8 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
MikamiUitOpen 16:cbb726ac20d8 523
MikamiUitOpen 16:cbb726ac20d8 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
MikamiUitOpen 16:cbb726ac20d8 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
MikamiUitOpen 16:cbb726ac20d8 526
MikamiUitOpen 16:cbb726ac20d8 527 /*@} end of group CMSIS_SysTick */
MikamiUitOpen 16:cbb726ac20d8 528
MikamiUitOpen 16:cbb726ac20d8 529 #if (__MPU_PRESENT == 1)
MikamiUitOpen 16:cbb726ac20d8 530 /** \ingroup CMSIS_core_register
MikamiUitOpen 16:cbb726ac20d8 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
MikamiUitOpen 16:cbb726ac20d8 532 \brief Type definitions for the Memory Protection Unit (MPU)
MikamiUitOpen 16:cbb726ac20d8 533 @{
MikamiUitOpen 16:cbb726ac20d8 534 */
MikamiUitOpen 16:cbb726ac20d8 535
MikamiUitOpen 16:cbb726ac20d8 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
MikamiUitOpen 16:cbb726ac20d8 537 */
MikamiUitOpen 16:cbb726ac20d8 538 typedef struct
MikamiUitOpen 16:cbb726ac20d8 539 {
MikamiUitOpen 16:cbb726ac20d8 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
MikamiUitOpen 16:cbb726ac20d8 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
MikamiUitOpen 16:cbb726ac20d8 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
MikamiUitOpen 16:cbb726ac20d8 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
MikamiUitOpen 16:cbb726ac20d8 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
MikamiUitOpen 16:cbb726ac20d8 545 } MPU_Type;
MikamiUitOpen 16:cbb726ac20d8 546
MikamiUitOpen 16:cbb726ac20d8 547 /* MPU Type Register */
MikamiUitOpen 16:cbb726ac20d8 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
MikamiUitOpen 16:cbb726ac20d8 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
MikamiUitOpen 16:cbb726ac20d8 550
MikamiUitOpen 16:cbb726ac20d8 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
MikamiUitOpen 16:cbb726ac20d8 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
MikamiUitOpen 16:cbb726ac20d8 553
MikamiUitOpen 16:cbb726ac20d8 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
MikamiUitOpen 16:cbb726ac20d8 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
MikamiUitOpen 16:cbb726ac20d8 556
MikamiUitOpen 16:cbb726ac20d8 557 /* MPU Control Register */
MikamiUitOpen 16:cbb726ac20d8 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
MikamiUitOpen 16:cbb726ac20d8 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
MikamiUitOpen 16:cbb726ac20d8 560
MikamiUitOpen 16:cbb726ac20d8 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
MikamiUitOpen 16:cbb726ac20d8 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
MikamiUitOpen 16:cbb726ac20d8 563
MikamiUitOpen 16:cbb726ac20d8 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
MikamiUitOpen 16:cbb726ac20d8 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
MikamiUitOpen 16:cbb726ac20d8 566
MikamiUitOpen 16:cbb726ac20d8 567 /* MPU Region Number Register */
MikamiUitOpen 16:cbb726ac20d8 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
MikamiUitOpen 16:cbb726ac20d8 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
MikamiUitOpen 16:cbb726ac20d8 570
MikamiUitOpen 16:cbb726ac20d8 571 /* MPU Region Base Address Register */
MikamiUitOpen 16:cbb726ac20d8 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
MikamiUitOpen 16:cbb726ac20d8 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
MikamiUitOpen 16:cbb726ac20d8 574
MikamiUitOpen 16:cbb726ac20d8 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
MikamiUitOpen 16:cbb726ac20d8 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
MikamiUitOpen 16:cbb726ac20d8 577
MikamiUitOpen 16:cbb726ac20d8 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
MikamiUitOpen 16:cbb726ac20d8 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
MikamiUitOpen 16:cbb726ac20d8 580
MikamiUitOpen 16:cbb726ac20d8 581 /* MPU Region Attribute and Size Register */
MikamiUitOpen 16:cbb726ac20d8 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
MikamiUitOpen 16:cbb726ac20d8 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
MikamiUitOpen 16:cbb726ac20d8 584
MikamiUitOpen 16:cbb726ac20d8 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
MikamiUitOpen 16:cbb726ac20d8 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
MikamiUitOpen 16:cbb726ac20d8 587
MikamiUitOpen 16:cbb726ac20d8 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
MikamiUitOpen 16:cbb726ac20d8 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
MikamiUitOpen 16:cbb726ac20d8 590
MikamiUitOpen 16:cbb726ac20d8 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
MikamiUitOpen 16:cbb726ac20d8 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
MikamiUitOpen 16:cbb726ac20d8 593
MikamiUitOpen 16:cbb726ac20d8 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
MikamiUitOpen 16:cbb726ac20d8 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
MikamiUitOpen 16:cbb726ac20d8 596
MikamiUitOpen 16:cbb726ac20d8 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
MikamiUitOpen 16:cbb726ac20d8 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
MikamiUitOpen 16:cbb726ac20d8 599
MikamiUitOpen 16:cbb726ac20d8 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
MikamiUitOpen 16:cbb726ac20d8 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
MikamiUitOpen 16:cbb726ac20d8 602
MikamiUitOpen 16:cbb726ac20d8 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
MikamiUitOpen 16:cbb726ac20d8 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
MikamiUitOpen 16:cbb726ac20d8 605
MikamiUitOpen 16:cbb726ac20d8 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
MikamiUitOpen 16:cbb726ac20d8 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
MikamiUitOpen 16:cbb726ac20d8 608
MikamiUitOpen 16:cbb726ac20d8 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
MikamiUitOpen 16:cbb726ac20d8 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
MikamiUitOpen 16:cbb726ac20d8 611
MikamiUitOpen 16:cbb726ac20d8 612 /*@} end of group CMSIS_MPU */
MikamiUitOpen 16:cbb726ac20d8 613 #endif
MikamiUitOpen 16:cbb726ac20d8 614
MikamiUitOpen 16:cbb726ac20d8 615
MikamiUitOpen 16:cbb726ac20d8 616 /** \ingroup CMSIS_core_register
MikamiUitOpen 16:cbb726ac20d8 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
MikamiUitOpen 16:cbb726ac20d8 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
MikamiUitOpen 16:cbb726ac20d8 619 are only accessible over DAP and not via processor. Therefore
MikamiUitOpen 16:cbb726ac20d8 620 they are not covered by the Cortex-M0 header file.
MikamiUitOpen 16:cbb726ac20d8 621 @{
MikamiUitOpen 16:cbb726ac20d8 622 */
MikamiUitOpen 16:cbb726ac20d8 623 /*@} end of group CMSIS_CoreDebug */
MikamiUitOpen 16:cbb726ac20d8 624
MikamiUitOpen 16:cbb726ac20d8 625
MikamiUitOpen 16:cbb726ac20d8 626 /** \ingroup CMSIS_core_register
MikamiUitOpen 16:cbb726ac20d8 627 \defgroup CMSIS_core_base Core Definitions
MikamiUitOpen 16:cbb726ac20d8 628 \brief Definitions for base addresses, unions, and structures.
MikamiUitOpen 16:cbb726ac20d8 629 @{
MikamiUitOpen 16:cbb726ac20d8 630 */
MikamiUitOpen 16:cbb726ac20d8 631
MikamiUitOpen 16:cbb726ac20d8 632 /* Memory mapping of Cortex-M0+ Hardware */
MikamiUitOpen 16:cbb726ac20d8 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
MikamiUitOpen 16:cbb726ac20d8 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
MikamiUitOpen 16:cbb726ac20d8 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
MikamiUitOpen 16:cbb726ac20d8 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
MikamiUitOpen 16:cbb726ac20d8 637
MikamiUitOpen 16:cbb726ac20d8 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
MikamiUitOpen 16:cbb726ac20d8 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
MikamiUitOpen 16:cbb726ac20d8 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
MikamiUitOpen 16:cbb726ac20d8 641
MikamiUitOpen 16:cbb726ac20d8 642 #if (__MPU_PRESENT == 1)
MikamiUitOpen 16:cbb726ac20d8 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
MikamiUitOpen 16:cbb726ac20d8 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
MikamiUitOpen 16:cbb726ac20d8 645 #endif
MikamiUitOpen 16:cbb726ac20d8 646
MikamiUitOpen 16:cbb726ac20d8 647 /*@} */
MikamiUitOpen 16:cbb726ac20d8 648
MikamiUitOpen 16:cbb726ac20d8 649
MikamiUitOpen 16:cbb726ac20d8 650
MikamiUitOpen 16:cbb726ac20d8 651 /*******************************************************************************
MikamiUitOpen 16:cbb726ac20d8 652 * Hardware Abstraction Layer
MikamiUitOpen 16:cbb726ac20d8 653 Core Function Interface contains:
MikamiUitOpen 16:cbb726ac20d8 654 - Core NVIC Functions
MikamiUitOpen 16:cbb726ac20d8 655 - Core SysTick Functions
MikamiUitOpen 16:cbb726ac20d8 656 - Core Register Access Functions
MikamiUitOpen 16:cbb726ac20d8 657 ******************************************************************************/
MikamiUitOpen 16:cbb726ac20d8 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
MikamiUitOpen 16:cbb726ac20d8 659 */
MikamiUitOpen 16:cbb726ac20d8 660
MikamiUitOpen 16:cbb726ac20d8 661
MikamiUitOpen 16:cbb726ac20d8 662
MikamiUitOpen 16:cbb726ac20d8 663 /* ########################## NVIC functions #################################### */
MikamiUitOpen 16:cbb726ac20d8 664 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 16:cbb726ac20d8 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
MikamiUitOpen 16:cbb726ac20d8 666 \brief Functions that manage interrupts and exceptions via the NVIC.
MikamiUitOpen 16:cbb726ac20d8 667 @{
MikamiUitOpen 16:cbb726ac20d8 668 */
MikamiUitOpen 16:cbb726ac20d8 669
MikamiUitOpen 16:cbb726ac20d8 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
MikamiUitOpen 16:cbb726ac20d8 671 /* The following MACROS handle generation of the register offset and byte masks */
MikamiUitOpen 16:cbb726ac20d8 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
MikamiUitOpen 16:cbb726ac20d8 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
MikamiUitOpen 16:cbb726ac20d8 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
MikamiUitOpen 16:cbb726ac20d8 675
MikamiUitOpen 16:cbb726ac20d8 676
MikamiUitOpen 16:cbb726ac20d8 677 /** \brief Enable External Interrupt
MikamiUitOpen 16:cbb726ac20d8 678
MikamiUitOpen 16:cbb726ac20d8 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 16:cbb726ac20d8 680
MikamiUitOpen 16:cbb726ac20d8 681 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 16:cbb726ac20d8 682 */
MikamiUitOpen 16:cbb726ac20d8 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
MikamiUitOpen 16:cbb726ac20d8 684 {
MikamiUitOpen 16:cbb726ac20d8 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 16:cbb726ac20d8 686 }
MikamiUitOpen 16:cbb726ac20d8 687
MikamiUitOpen 16:cbb726ac20d8 688
MikamiUitOpen 16:cbb726ac20d8 689 /** \brief Disable External Interrupt
MikamiUitOpen 16:cbb726ac20d8 690
MikamiUitOpen 16:cbb726ac20d8 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 16:cbb726ac20d8 692
MikamiUitOpen 16:cbb726ac20d8 693 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 16:cbb726ac20d8 694 */
MikamiUitOpen 16:cbb726ac20d8 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
MikamiUitOpen 16:cbb726ac20d8 696 {
MikamiUitOpen 16:cbb726ac20d8 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 16:cbb726ac20d8 698 }
MikamiUitOpen 16:cbb726ac20d8 699
MikamiUitOpen 16:cbb726ac20d8 700
MikamiUitOpen 16:cbb726ac20d8 701 /** \brief Get Pending Interrupt
MikamiUitOpen 16:cbb726ac20d8 702
MikamiUitOpen 16:cbb726ac20d8 703 The function reads the pending register in the NVIC and returns the pending bit
MikamiUitOpen 16:cbb726ac20d8 704 for the specified interrupt.
MikamiUitOpen 16:cbb726ac20d8 705
MikamiUitOpen 16:cbb726ac20d8 706 \param [in] IRQn Interrupt number.
MikamiUitOpen 16:cbb726ac20d8 707
MikamiUitOpen 16:cbb726ac20d8 708 \return 0 Interrupt status is not pending.
MikamiUitOpen 16:cbb726ac20d8 709 \return 1 Interrupt status is pending.
MikamiUitOpen 16:cbb726ac20d8 710 */
MikamiUitOpen 16:cbb726ac20d8 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 16:cbb726ac20d8 712 {
MikamiUitOpen 16:cbb726ac20d8 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen 16:cbb726ac20d8 714 }
MikamiUitOpen 16:cbb726ac20d8 715
MikamiUitOpen 16:cbb726ac20d8 716
MikamiUitOpen 16:cbb726ac20d8 717 /** \brief Set Pending Interrupt
MikamiUitOpen 16:cbb726ac20d8 718
MikamiUitOpen 16:cbb726ac20d8 719 The function sets the pending bit of an external interrupt.
MikamiUitOpen 16:cbb726ac20d8 720
MikamiUitOpen 16:cbb726ac20d8 721 \param [in] IRQn Interrupt number. Value cannot be negative.
MikamiUitOpen 16:cbb726ac20d8 722 */
MikamiUitOpen 16:cbb726ac20d8 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 16:cbb726ac20d8 724 {
MikamiUitOpen 16:cbb726ac20d8 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 16:cbb726ac20d8 726 }
MikamiUitOpen 16:cbb726ac20d8 727
MikamiUitOpen 16:cbb726ac20d8 728
MikamiUitOpen 16:cbb726ac20d8 729 /** \brief Clear Pending Interrupt
MikamiUitOpen 16:cbb726ac20d8 730
MikamiUitOpen 16:cbb726ac20d8 731 The function clears the pending bit of an external interrupt.
MikamiUitOpen 16:cbb726ac20d8 732
MikamiUitOpen 16:cbb726ac20d8 733 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 16:cbb726ac20d8 734 */
MikamiUitOpen 16:cbb726ac20d8 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 16:cbb726ac20d8 736 {
MikamiUitOpen 16:cbb726ac20d8 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 16:cbb726ac20d8 738 }
MikamiUitOpen 16:cbb726ac20d8 739
MikamiUitOpen 16:cbb726ac20d8 740
MikamiUitOpen 16:cbb726ac20d8 741 /** \brief Set Interrupt Priority
MikamiUitOpen 16:cbb726ac20d8 742
MikamiUitOpen 16:cbb726ac20d8 743 The function sets the priority of an interrupt.
MikamiUitOpen 16:cbb726ac20d8 744
MikamiUitOpen 16:cbb726ac20d8 745 \note The priority cannot be set for every core interrupt.
MikamiUitOpen 16:cbb726ac20d8 746
MikamiUitOpen 16:cbb726ac20d8 747 \param [in] IRQn Interrupt number.
MikamiUitOpen 16:cbb726ac20d8 748 \param [in] priority Priority to set.
MikamiUitOpen 16:cbb726ac20d8 749 */
MikamiUitOpen 16:cbb726ac20d8 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
MikamiUitOpen 16:cbb726ac20d8 751 {
MikamiUitOpen 16:cbb726ac20d8 752 if((int32_t)(IRQn) < 0) {
MikamiUitOpen 16:cbb726ac20d8 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
MikamiUitOpen 16:cbb726ac20d8 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
MikamiUitOpen 16:cbb726ac20d8 755 }
MikamiUitOpen 16:cbb726ac20d8 756 else {
MikamiUitOpen 16:cbb726ac20d8 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
MikamiUitOpen 16:cbb726ac20d8 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
MikamiUitOpen 16:cbb726ac20d8 759 }
MikamiUitOpen 16:cbb726ac20d8 760 }
MikamiUitOpen 16:cbb726ac20d8 761
MikamiUitOpen 16:cbb726ac20d8 762
MikamiUitOpen 16:cbb726ac20d8 763 /** \brief Get Interrupt Priority
MikamiUitOpen 16:cbb726ac20d8 764
MikamiUitOpen 16:cbb726ac20d8 765 The function reads the priority of an interrupt. The interrupt
MikamiUitOpen 16:cbb726ac20d8 766 number can be positive to specify an external (device specific)
MikamiUitOpen 16:cbb726ac20d8 767 interrupt, or negative to specify an internal (core) interrupt.
MikamiUitOpen 16:cbb726ac20d8 768
MikamiUitOpen 16:cbb726ac20d8 769
MikamiUitOpen 16:cbb726ac20d8 770 \param [in] IRQn Interrupt number.
MikamiUitOpen 16:cbb726ac20d8 771 \return Interrupt Priority. Value is aligned automatically to the implemented
MikamiUitOpen 16:cbb726ac20d8 772 priority bits of the microcontroller.
MikamiUitOpen 16:cbb726ac20d8 773 */
MikamiUitOpen 16:cbb726ac20d8 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
MikamiUitOpen 16:cbb726ac20d8 775 {
MikamiUitOpen 16:cbb726ac20d8 776
MikamiUitOpen 16:cbb726ac20d8 777 if((int32_t)(IRQn) < 0) {
MikamiUitOpen 16:cbb726ac20d8 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 16:cbb726ac20d8 779 }
MikamiUitOpen 16:cbb726ac20d8 780 else {
MikamiUitOpen 16:cbb726ac20d8 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 16:cbb726ac20d8 782 }
MikamiUitOpen 16:cbb726ac20d8 783 }
MikamiUitOpen 16:cbb726ac20d8 784
MikamiUitOpen 16:cbb726ac20d8 785
MikamiUitOpen 16:cbb726ac20d8 786 /** \brief System Reset
MikamiUitOpen 16:cbb726ac20d8 787
MikamiUitOpen 16:cbb726ac20d8 788 The function initiates a system reset request to reset the MCU.
MikamiUitOpen 16:cbb726ac20d8 789 */
MikamiUitOpen 16:cbb726ac20d8 790 __STATIC_INLINE void NVIC_SystemReset(void)
MikamiUitOpen 16:cbb726ac20d8 791 {
MikamiUitOpen 16:cbb726ac20d8 792 __DSB(); /* Ensure all outstanding memory accesses included
MikamiUitOpen 16:cbb726ac20d8 793 buffered write are completed before reset */
MikamiUitOpen 16:cbb726ac20d8 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
MikamiUitOpen 16:cbb726ac20d8 795 SCB_AIRCR_SYSRESETREQ_Msk);
MikamiUitOpen 16:cbb726ac20d8 796 __DSB(); /* Ensure completion of memory access */
MikamiUitOpen 16:cbb726ac20d8 797 while(1) { __NOP(); } /* wait until reset */
MikamiUitOpen 16:cbb726ac20d8 798 }
MikamiUitOpen 16:cbb726ac20d8 799
MikamiUitOpen 16:cbb726ac20d8 800 /*@} end of CMSIS_Core_NVICFunctions */
MikamiUitOpen 16:cbb726ac20d8 801
MikamiUitOpen 16:cbb726ac20d8 802
MikamiUitOpen 16:cbb726ac20d8 803
MikamiUitOpen 16:cbb726ac20d8 804 /* ################################## SysTick function ############################################ */
MikamiUitOpen 16:cbb726ac20d8 805 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 16:cbb726ac20d8 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
MikamiUitOpen 16:cbb726ac20d8 807 \brief Functions that configure the System.
MikamiUitOpen 16:cbb726ac20d8 808 @{
MikamiUitOpen 16:cbb726ac20d8 809 */
MikamiUitOpen 16:cbb726ac20d8 810
MikamiUitOpen 16:cbb726ac20d8 811 #if (__Vendor_SysTickConfig == 0)
MikamiUitOpen 16:cbb726ac20d8 812
MikamiUitOpen 16:cbb726ac20d8 813 /** \brief System Tick Configuration
MikamiUitOpen 16:cbb726ac20d8 814
MikamiUitOpen 16:cbb726ac20d8 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
MikamiUitOpen 16:cbb726ac20d8 816 Counter is in free running mode to generate periodic interrupts.
MikamiUitOpen 16:cbb726ac20d8 817
MikamiUitOpen 16:cbb726ac20d8 818 \param [in] ticks Number of ticks between two interrupts.
MikamiUitOpen 16:cbb726ac20d8 819
MikamiUitOpen 16:cbb726ac20d8 820 \return 0 Function succeeded.
MikamiUitOpen 16:cbb726ac20d8 821 \return 1 Function failed.
MikamiUitOpen 16:cbb726ac20d8 822
MikamiUitOpen 16:cbb726ac20d8 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MikamiUitOpen 16:cbb726ac20d8 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
MikamiUitOpen 16:cbb726ac20d8 825 must contain a vendor-specific implementation of this function.
MikamiUitOpen 16:cbb726ac20d8 826
MikamiUitOpen 16:cbb726ac20d8 827 */
MikamiUitOpen 16:cbb726ac20d8 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
MikamiUitOpen 16:cbb726ac20d8 829 {
MikamiUitOpen 16:cbb726ac20d8 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
MikamiUitOpen 16:cbb726ac20d8 831
MikamiUitOpen 16:cbb726ac20d8 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MikamiUitOpen 16:cbb726ac20d8 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MikamiUitOpen 16:cbb726ac20d8 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
MikamiUitOpen 16:cbb726ac20d8 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
MikamiUitOpen 16:cbb726ac20d8 836 SysTick_CTRL_TICKINT_Msk |
MikamiUitOpen 16:cbb726ac20d8 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MikamiUitOpen 16:cbb726ac20d8 838 return (0UL); /* Function successful */
MikamiUitOpen 16:cbb726ac20d8 839 }
MikamiUitOpen 16:cbb726ac20d8 840
MikamiUitOpen 16:cbb726ac20d8 841 #endif
MikamiUitOpen 16:cbb726ac20d8 842
MikamiUitOpen 16:cbb726ac20d8 843 /*@} end of CMSIS_Core_SysTickFunctions */
MikamiUitOpen 16:cbb726ac20d8 844
MikamiUitOpen 16:cbb726ac20d8 845
MikamiUitOpen 16:cbb726ac20d8 846
MikamiUitOpen 16:cbb726ac20d8 847
MikamiUitOpen 16:cbb726ac20d8 848 #ifdef __cplusplus
MikamiUitOpen 16:cbb726ac20d8 849 }
MikamiUitOpen 16:cbb726ac20d8 850 #endif
MikamiUitOpen 16:cbb726ac20d8 851
MikamiUitOpen 16:cbb726ac20d8 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
MikamiUitOpen 16:cbb726ac20d8 853
MikamiUitOpen 16:cbb726ac20d8 854 #endif /* __CMSIS_GENERIC */