不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/hal/spi_api.h@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /* mbed Microcontroller Library
MikamiUitOpen 6:38f7dce055d0 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 6:38f7dce055d0 3 *
MikamiUitOpen 6:38f7dce055d0 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 6:38f7dce055d0 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 6:38f7dce055d0 6 * You may obtain a copy of the License at
MikamiUitOpen 6:38f7dce055d0 7 *
MikamiUitOpen 6:38f7dce055d0 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 6:38f7dce055d0 9 *
MikamiUitOpen 6:38f7dce055d0 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 6:38f7dce055d0 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 6:38f7dce055d0 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 6:38f7dce055d0 13 * See the License for the specific language governing permissions and
MikamiUitOpen 6:38f7dce055d0 14 * limitations under the License.
MikamiUitOpen 6:38f7dce055d0 15 */
MikamiUitOpen 6:38f7dce055d0 16 #ifndef MBED_SPI_API_H
MikamiUitOpen 6:38f7dce055d0 17 #define MBED_SPI_API_H
MikamiUitOpen 6:38f7dce055d0 18
MikamiUitOpen 6:38f7dce055d0 19 #include "device.h"
MikamiUitOpen 6:38f7dce055d0 20 #include "dma_api.h"
MikamiUitOpen 6:38f7dce055d0 21 #include "buffer.h"
MikamiUitOpen 6:38f7dce055d0 22
MikamiUitOpen 6:38f7dce055d0 23 #if DEVICE_SPI
MikamiUitOpen 6:38f7dce055d0 24
MikamiUitOpen 6:38f7dce055d0 25 #define SPI_EVENT_ERROR (1 << 1)
MikamiUitOpen 6:38f7dce055d0 26 #define SPI_EVENT_COMPLETE (1 << 2)
MikamiUitOpen 6:38f7dce055d0 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
MikamiUitOpen 6:38f7dce055d0 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
MikamiUitOpen 6:38f7dce055d0 29
MikamiUitOpen 6:38f7dce055d0 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred
MikamiUitOpen 6:38f7dce055d0 31
MikamiUitOpen 6:38f7dce055d0 32 #define SPI_FILL_WORD (0xFFFF)
MikamiUitOpen 6:38f7dce055d0 33
MikamiUitOpen 6:38f7dce055d0 34 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 6:38f7dce055d0 35 /** Asynch spi hal structure
MikamiUitOpen 6:38f7dce055d0 36 */
MikamiUitOpen 6:38f7dce055d0 37 typedef struct {
MikamiUitOpen 6:38f7dce055d0 38 struct spi_s spi; /**< Target specific spi structure */
MikamiUitOpen 6:38f7dce055d0 39 struct buffer_s tx_buff; /**< Tx buffer */
MikamiUitOpen 6:38f7dce055d0 40 struct buffer_s rx_buff; /**< Rx buffer */
MikamiUitOpen 6:38f7dce055d0 41 } spi_t;
MikamiUitOpen 6:38f7dce055d0 42
MikamiUitOpen 6:38f7dce055d0 43 #else
MikamiUitOpen 6:38f7dce055d0 44 /** Non-asynch spi hal structure
MikamiUitOpen 6:38f7dce055d0 45 */
MikamiUitOpen 6:38f7dce055d0 46 typedef struct spi_s spi_t;
MikamiUitOpen 6:38f7dce055d0 47
MikamiUitOpen 6:38f7dce055d0 48 #endif
MikamiUitOpen 6:38f7dce055d0 49
MikamiUitOpen 6:38f7dce055d0 50 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 51 extern "C" {
MikamiUitOpen 6:38f7dce055d0 52 #endif
MikamiUitOpen 6:38f7dce055d0 53
MikamiUitOpen 6:38f7dce055d0 54 /**
MikamiUitOpen 6:38f7dce055d0 55 * \defgroup GeneralSPI SPI Configuration Functions
MikamiUitOpen 6:38f7dce055d0 56 * @{
MikamiUitOpen 6:38f7dce055d0 57 */
MikamiUitOpen 6:38f7dce055d0 58
MikamiUitOpen 6:38f7dce055d0 59 /** Initialize the SPI peripheral
MikamiUitOpen 6:38f7dce055d0 60 *
MikamiUitOpen 6:38f7dce055d0 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
MikamiUitOpen 6:38f7dce055d0 62 * @param[out] obj The SPI object to initialize
MikamiUitOpen 6:38f7dce055d0 63 * @param[in] mosi The pin to use for MOSI
MikamiUitOpen 6:38f7dce055d0 64 * @param[in] miso The pin to use for MISO
MikamiUitOpen 6:38f7dce055d0 65 * @param[in] sclk The pin to use for SCLK
MikamiUitOpen 6:38f7dce055d0 66 * @param[in] ssel The pin to use for SSEL
MikamiUitOpen 6:38f7dce055d0 67 */
MikamiUitOpen 6:38f7dce055d0 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
MikamiUitOpen 6:38f7dce055d0 69
MikamiUitOpen 6:38f7dce055d0 70 /** Release a SPI object
MikamiUitOpen 6:38f7dce055d0 71 *
MikamiUitOpen 6:38f7dce055d0 72 * TODO: spi_free is currently unimplemented
MikamiUitOpen 6:38f7dce055d0 73 * This will require reference counting at the C++ level to be safe
MikamiUitOpen 6:38f7dce055d0 74 *
MikamiUitOpen 6:38f7dce055d0 75 * Return the pins owned by the SPI object to their reset state
MikamiUitOpen 6:38f7dce055d0 76 * Disable the SPI peripheral
MikamiUitOpen 6:38f7dce055d0 77 * Disable the SPI clock
MikamiUitOpen 6:38f7dce055d0 78 * @param[in] obj The SPI object to deinitialize
MikamiUitOpen 6:38f7dce055d0 79 */
MikamiUitOpen 6:38f7dce055d0 80 void spi_free(spi_t *obj);
MikamiUitOpen 6:38f7dce055d0 81
MikamiUitOpen 6:38f7dce055d0 82 /** Configure the SPI format
MikamiUitOpen 6:38f7dce055d0 83 *
MikamiUitOpen 6:38f7dce055d0 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
MikamiUitOpen 6:38f7dce055d0 85 * @param[in,out] obj The SPI object to configure
MikamiUitOpen 6:38f7dce055d0 86 * @param[in] bits The number of bits per frame
MikamiUitOpen 6:38f7dce055d0 87 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
MikamiUitOpen 6:38f7dce055d0 88 * @param[in] slave Zero for master mode or non-zero for slave mode
MikamiUitOpen 6:38f7dce055d0 89 */
MikamiUitOpen 6:38f7dce055d0 90 void spi_format(spi_t *obj, int bits, int mode, int slave);
MikamiUitOpen 6:38f7dce055d0 91
MikamiUitOpen 6:38f7dce055d0 92 /** Set the SPI baud rate
MikamiUitOpen 6:38f7dce055d0 93 *
MikamiUitOpen 6:38f7dce055d0 94 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
MikamiUitOpen 6:38f7dce055d0 95 * Configures the SPI peripheral's baud rate
MikamiUitOpen 6:38f7dce055d0 96 * @param[in,out] obj The SPI object to configure
MikamiUitOpen 6:38f7dce055d0 97 * @param[in] hz The baud rate in Hz
MikamiUitOpen 6:38f7dce055d0 98 */
MikamiUitOpen 6:38f7dce055d0 99 void spi_frequency(spi_t *obj, int hz);
MikamiUitOpen 6:38f7dce055d0 100
MikamiUitOpen 6:38f7dce055d0 101 /**@}*/
MikamiUitOpen 6:38f7dce055d0 102 /**
MikamiUitOpen 6:38f7dce055d0 103 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
MikamiUitOpen 6:38f7dce055d0 104 * @{
MikamiUitOpen 6:38f7dce055d0 105 */
MikamiUitOpen 6:38f7dce055d0 106
MikamiUitOpen 6:38f7dce055d0 107 /** Write a byte out in master mode and receive a value
MikamiUitOpen 6:38f7dce055d0 108 *
MikamiUitOpen 6:38f7dce055d0 109 * @param[in] obj The SPI peripheral to use for sending
MikamiUitOpen 6:38f7dce055d0 110 * @param[in] value The value to send
MikamiUitOpen 6:38f7dce055d0 111 * @return Returns the value received during send
MikamiUitOpen 6:38f7dce055d0 112 */
MikamiUitOpen 6:38f7dce055d0 113 int spi_master_write(spi_t *obj, int value);
MikamiUitOpen 6:38f7dce055d0 114
MikamiUitOpen 6:38f7dce055d0 115 /** Check if a value is available to read
MikamiUitOpen 6:38f7dce055d0 116 *
MikamiUitOpen 6:38f7dce055d0 117 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 6:38f7dce055d0 118 * @return non-zero if a value is available
MikamiUitOpen 6:38f7dce055d0 119 */
MikamiUitOpen 6:38f7dce055d0 120 int spi_slave_receive(spi_t *obj);
MikamiUitOpen 6:38f7dce055d0 121
MikamiUitOpen 6:38f7dce055d0 122 /** Get a received value out of the SPI receive buffer in slave mode
MikamiUitOpen 6:38f7dce055d0 123 *
MikamiUitOpen 6:38f7dce055d0 124 * Blocks until a value is available
MikamiUitOpen 6:38f7dce055d0 125 * @param[in] obj The SPI peripheral to read
MikamiUitOpen 6:38f7dce055d0 126 * @return The value received
MikamiUitOpen 6:38f7dce055d0 127 */
MikamiUitOpen 6:38f7dce055d0 128 int spi_slave_read(spi_t *obj);
MikamiUitOpen 6:38f7dce055d0 129
MikamiUitOpen 6:38f7dce055d0 130 /** Write a value to the SPI peripheral in slave mode
MikamiUitOpen 6:38f7dce055d0 131 *
MikamiUitOpen 6:38f7dce055d0 132 * Blocks until the SPI peripheral can be written to
MikamiUitOpen 6:38f7dce055d0 133 * @param[in] obj The SPI peripheral to write
MikamiUitOpen 6:38f7dce055d0 134 * @param[in] value The value to write
MikamiUitOpen 6:38f7dce055d0 135 */
MikamiUitOpen 6:38f7dce055d0 136 void spi_slave_write(spi_t *obj, int value);
MikamiUitOpen 6:38f7dce055d0 137
MikamiUitOpen 6:38f7dce055d0 138 /** Checks if the specified SPI peripheral is in use
MikamiUitOpen 6:38f7dce055d0 139 *
MikamiUitOpen 6:38f7dce055d0 140 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 6:38f7dce055d0 141 * @return non-zero if the peripheral is currently transmitting
MikamiUitOpen 6:38f7dce055d0 142 */
MikamiUitOpen 6:38f7dce055d0 143 int spi_busy(spi_t *obj);
MikamiUitOpen 6:38f7dce055d0 144
MikamiUitOpen 6:38f7dce055d0 145 /** Get the module number
MikamiUitOpen 6:38f7dce055d0 146 *
MikamiUitOpen 6:38f7dce055d0 147 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 6:38f7dce055d0 148 * @return The module number
MikamiUitOpen 6:38f7dce055d0 149 */
MikamiUitOpen 6:38f7dce055d0 150 uint8_t spi_get_module(spi_t *obj);
MikamiUitOpen 6:38f7dce055d0 151
MikamiUitOpen 6:38f7dce055d0 152 /**@}*/
MikamiUitOpen 6:38f7dce055d0 153
MikamiUitOpen 6:38f7dce055d0 154 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 6:38f7dce055d0 155 /**
MikamiUitOpen 6:38f7dce055d0 156 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
MikamiUitOpen 6:38f7dce055d0 157 * @{
MikamiUitOpen 6:38f7dce055d0 158 */
MikamiUitOpen 6:38f7dce055d0 159
MikamiUitOpen 6:38f7dce055d0 160 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
MikamiUitOpen 6:38f7dce055d0 161 *
MikamiUitOpen 6:38f7dce055d0 162 * @param[in] obj The SPI object which holds the transfer information
MikamiUitOpen 6:38f7dce055d0 163 * @param[in] tx The buffer to send
MikamiUitOpen 6:38f7dce055d0 164 * @param[in] tx_length The number of words to transmit
MikamiUitOpen 6:38f7dce055d0 165 * @param[in] rx The buffer to receive
MikamiUitOpen 6:38f7dce055d0 166 * @param[in] rx_length The number of words to receive
MikamiUitOpen 6:38f7dce055d0 167 * @param[in] bit_width The bit width of buffer words
MikamiUitOpen 6:38f7dce055d0 168 * @param[in] event The logical OR of events to be registered
MikamiUitOpen 6:38f7dce055d0 169 * @param[in] handler SPI interrupt handler
MikamiUitOpen 6:38f7dce055d0 170 * @param[in] hint A suggestion for how to use DMA with this transfer
MikamiUitOpen 6:38f7dce055d0 171 */
MikamiUitOpen 6:38f7dce055d0 172 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
MikamiUitOpen 6:38f7dce055d0 173
MikamiUitOpen 6:38f7dce055d0 174 /** The asynchronous IRQ handler
MikamiUitOpen 6:38f7dce055d0 175 *
MikamiUitOpen 6:38f7dce055d0 176 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
MikamiUitOpen 6:38f7dce055d0 177 * conditions, such as buffer overflows or transfer complete.
MikamiUitOpen 6:38f7dce055d0 178 * @param[in] obj The SPI object which holds the transfer information
MikamiUitOpen 6:38f7dce055d0 179 * @return event flags if a transfer termination condition was met or 0 otherwise.
MikamiUitOpen 6:38f7dce055d0 180 */
MikamiUitOpen 6:38f7dce055d0 181 uint32_t spi_irq_handler_asynch(spi_t *obj);
MikamiUitOpen 6:38f7dce055d0 182
MikamiUitOpen 6:38f7dce055d0 183 /** Attempts to determine if the SPI peripheral is already in use.
MikamiUitOpen 6:38f7dce055d0 184 *
MikamiUitOpen 6:38f7dce055d0 185 * If a temporary DMA channel has been allocated, peripheral is in use.
MikamiUitOpen 6:38f7dce055d0 186 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
MikamiUitOpen 6:38f7dce055d0 187 * channel were allocated.
MikamiUitOpen 6:38f7dce055d0 188 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
MikamiUitOpen 6:38f7dce055d0 189 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
MikamiUitOpen 6:38f7dce055d0 190 * there are any bytes in the FIFOs.
MikamiUitOpen 6:38f7dce055d0 191 * @param[in] obj The SPI object to check for activity
MikamiUitOpen 6:38f7dce055d0 192 * @return non-zero if the SPI port is active or zero if it is not.
MikamiUitOpen 6:38f7dce055d0 193 */
MikamiUitOpen 6:38f7dce055d0 194 uint8_t spi_active(spi_t *obj);
MikamiUitOpen 6:38f7dce055d0 195
MikamiUitOpen 6:38f7dce055d0 196 /** Abort an SPI transfer
MikamiUitOpen 6:38f7dce055d0 197 *
MikamiUitOpen 6:38f7dce055d0 198 * @param obj The SPI peripheral to stop
MikamiUitOpen 6:38f7dce055d0 199 */
MikamiUitOpen 6:38f7dce055d0 200 void spi_abort_asynch(spi_t *obj);
MikamiUitOpen 6:38f7dce055d0 201
MikamiUitOpen 6:38f7dce055d0 202
MikamiUitOpen 6:38f7dce055d0 203 #endif
MikamiUitOpen 6:38f7dce055d0 204
MikamiUitOpen 6:38f7dce055d0 205 /**@}*/
MikamiUitOpen 6:38f7dce055d0 206
MikamiUitOpen 6:38f7dce055d0 207 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 208 }
MikamiUitOpen 6:38f7dce055d0 209 #endif // __cplusplus
MikamiUitOpen 6:38f7dce055d0 210
MikamiUitOpen 6:38f7dce055d0 211 #endif // SPI_DEVICE
MikamiUitOpen 6:38f7dce055d0 212
MikamiUitOpen 6:38f7dce055d0 213 #endif // MBED_SPI_API_H