不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/common/SPI.cpp@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /* mbed Microcontroller Library
MikamiUitOpen 6:38f7dce055d0 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 6:38f7dce055d0 3 *
MikamiUitOpen 6:38f7dce055d0 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 6:38f7dce055d0 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 6:38f7dce055d0 6 * You may obtain a copy of the License at
MikamiUitOpen 6:38f7dce055d0 7 *
MikamiUitOpen 6:38f7dce055d0 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 6:38f7dce055d0 9 *
MikamiUitOpen 6:38f7dce055d0 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 6:38f7dce055d0 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 6:38f7dce055d0 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 6:38f7dce055d0 13 * See the License for the specific language governing permissions and
MikamiUitOpen 6:38f7dce055d0 14 * limitations under the License.
MikamiUitOpen 6:38f7dce055d0 15 */
MikamiUitOpen 6:38f7dce055d0 16 #include "SPI.h"
MikamiUitOpen 6:38f7dce055d0 17
MikamiUitOpen 6:38f7dce055d0 18 #if DEVICE_SPI
MikamiUitOpen 6:38f7dce055d0 19
MikamiUitOpen 6:38f7dce055d0 20 namespace mbed {
MikamiUitOpen 6:38f7dce055d0 21
MikamiUitOpen 6:38f7dce055d0 22 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 6:38f7dce055d0 23 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
MikamiUitOpen 6:38f7dce055d0 24 #endif
MikamiUitOpen 6:38f7dce055d0 25
MikamiUitOpen 6:38f7dce055d0 26 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
MikamiUitOpen 6:38f7dce055d0 27 _spi(),
MikamiUitOpen 6:38f7dce055d0 28 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 6:38f7dce055d0 29 _irq(this),
MikamiUitOpen 6:38f7dce055d0 30 _usage(DMA_USAGE_NEVER),
MikamiUitOpen 6:38f7dce055d0 31 #endif
MikamiUitOpen 6:38f7dce055d0 32 _bits(8),
MikamiUitOpen 6:38f7dce055d0 33 _mode(0),
MikamiUitOpen 6:38f7dce055d0 34 _hz(1000000) {
MikamiUitOpen 6:38f7dce055d0 35 spi_init(&_spi, mosi, miso, sclk, ssel);
MikamiUitOpen 6:38f7dce055d0 36 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 6:38f7dce055d0 37 spi_frequency(&_spi, _hz);
MikamiUitOpen 6:38f7dce055d0 38 }
MikamiUitOpen 6:38f7dce055d0 39
MikamiUitOpen 6:38f7dce055d0 40 void SPI::format(int bits, int mode) {
MikamiUitOpen 6:38f7dce055d0 41 _bits = bits;
MikamiUitOpen 6:38f7dce055d0 42 _mode = mode;
MikamiUitOpen 6:38f7dce055d0 43 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 6:38f7dce055d0 44 aquire();
MikamiUitOpen 6:38f7dce055d0 45 }
MikamiUitOpen 6:38f7dce055d0 46
MikamiUitOpen 6:38f7dce055d0 47 void SPI::frequency(int hz) {
MikamiUitOpen 6:38f7dce055d0 48 _hz = hz;
MikamiUitOpen 6:38f7dce055d0 49 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 6:38f7dce055d0 50 aquire();
MikamiUitOpen 6:38f7dce055d0 51 }
MikamiUitOpen 6:38f7dce055d0 52
MikamiUitOpen 6:38f7dce055d0 53 SPI* SPI::_owner = NULL;
MikamiUitOpen 6:38f7dce055d0 54
MikamiUitOpen 6:38f7dce055d0 55 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
MikamiUitOpen 6:38f7dce055d0 56 void SPI::aquire() {
MikamiUitOpen 6:38f7dce055d0 57 if (_owner != this) {
MikamiUitOpen 6:38f7dce055d0 58 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 6:38f7dce055d0 59 spi_frequency(&_spi, _hz);
MikamiUitOpen 6:38f7dce055d0 60 _owner = this;
MikamiUitOpen 6:38f7dce055d0 61 }
MikamiUitOpen 6:38f7dce055d0 62 }
MikamiUitOpen 6:38f7dce055d0 63
MikamiUitOpen 6:38f7dce055d0 64 int SPI::write(int value) {
MikamiUitOpen 6:38f7dce055d0 65 aquire();
MikamiUitOpen 6:38f7dce055d0 66 return spi_master_write(&_spi, value);
MikamiUitOpen 6:38f7dce055d0 67 }
MikamiUitOpen 6:38f7dce055d0 68
MikamiUitOpen 6:38f7dce055d0 69 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 6:38f7dce055d0 70
MikamiUitOpen 6:38f7dce055d0 71 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 6:38f7dce055d0 72 {
MikamiUitOpen 6:38f7dce055d0 73 if (spi_active(&_spi)) {
MikamiUitOpen 6:38f7dce055d0 74 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 6:38f7dce055d0 75 }
MikamiUitOpen 6:38f7dce055d0 76 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 6:38f7dce055d0 77 return 0;
MikamiUitOpen 6:38f7dce055d0 78 }
MikamiUitOpen 6:38f7dce055d0 79
MikamiUitOpen 6:38f7dce055d0 80 void SPI::abort_transfer()
MikamiUitOpen 6:38f7dce055d0 81 {
MikamiUitOpen 6:38f7dce055d0 82 spi_abort_asynch(&_spi);
MikamiUitOpen 6:38f7dce055d0 83 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 6:38f7dce055d0 84 dequeue_transaction();
MikamiUitOpen 6:38f7dce055d0 85 #endif
MikamiUitOpen 6:38f7dce055d0 86 }
MikamiUitOpen 6:38f7dce055d0 87
MikamiUitOpen 6:38f7dce055d0 88
MikamiUitOpen 6:38f7dce055d0 89 void SPI::clear_transfer_buffer()
MikamiUitOpen 6:38f7dce055d0 90 {
MikamiUitOpen 6:38f7dce055d0 91 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 6:38f7dce055d0 92 _transaction_buffer.reset();
MikamiUitOpen 6:38f7dce055d0 93 #endif
MikamiUitOpen 6:38f7dce055d0 94 }
MikamiUitOpen 6:38f7dce055d0 95
MikamiUitOpen 6:38f7dce055d0 96 void SPI::abort_all_transfers()
MikamiUitOpen 6:38f7dce055d0 97 {
MikamiUitOpen 6:38f7dce055d0 98 clear_transfer_buffer();
MikamiUitOpen 6:38f7dce055d0 99 abort_transfer();
MikamiUitOpen 6:38f7dce055d0 100 }
MikamiUitOpen 6:38f7dce055d0 101
MikamiUitOpen 6:38f7dce055d0 102 int SPI::set_dma_usage(DMAUsage usage)
MikamiUitOpen 6:38f7dce055d0 103 {
MikamiUitOpen 6:38f7dce055d0 104 if (spi_active(&_spi)) {
MikamiUitOpen 6:38f7dce055d0 105 return -1;
MikamiUitOpen 6:38f7dce055d0 106 }
MikamiUitOpen 6:38f7dce055d0 107 _usage = usage;
MikamiUitOpen 6:38f7dce055d0 108 return 0;
MikamiUitOpen 6:38f7dce055d0 109 }
MikamiUitOpen 6:38f7dce055d0 110
MikamiUitOpen 6:38f7dce055d0 111 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 6:38f7dce055d0 112 {
MikamiUitOpen 6:38f7dce055d0 113 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 6:38f7dce055d0 114 transaction_t t;
MikamiUitOpen 6:38f7dce055d0 115
MikamiUitOpen 6:38f7dce055d0 116 t.tx_buffer = const_cast<void *>(tx_buffer);
MikamiUitOpen 6:38f7dce055d0 117 t.tx_length = tx_length;
MikamiUitOpen 6:38f7dce055d0 118 t.rx_buffer = rx_buffer;
MikamiUitOpen 6:38f7dce055d0 119 t.rx_length = rx_length;
MikamiUitOpen 6:38f7dce055d0 120 t.event = event;
MikamiUitOpen 6:38f7dce055d0 121 t.callback = callback;
MikamiUitOpen 6:38f7dce055d0 122 t.width = bit_width;
MikamiUitOpen 6:38f7dce055d0 123 Transaction<SPI> transaction(this, t);
MikamiUitOpen 6:38f7dce055d0 124 if (_transaction_buffer.full()) {
MikamiUitOpen 6:38f7dce055d0 125 return -1; // the buffer is full
MikamiUitOpen 6:38f7dce055d0 126 } else {
MikamiUitOpen 6:38f7dce055d0 127 __disable_irq();
MikamiUitOpen 6:38f7dce055d0 128 _transaction_buffer.push(transaction);
MikamiUitOpen 6:38f7dce055d0 129 if (!spi_active(&_spi)) {
MikamiUitOpen 6:38f7dce055d0 130 dequeue_transaction();
MikamiUitOpen 6:38f7dce055d0 131 }
MikamiUitOpen 6:38f7dce055d0 132 __enable_irq();
MikamiUitOpen 6:38f7dce055d0 133 return 0;
MikamiUitOpen 6:38f7dce055d0 134 }
MikamiUitOpen 6:38f7dce055d0 135 #else
MikamiUitOpen 6:38f7dce055d0 136 return -1;
MikamiUitOpen 6:38f7dce055d0 137 #endif
MikamiUitOpen 6:38f7dce055d0 138 }
MikamiUitOpen 6:38f7dce055d0 139
MikamiUitOpen 6:38f7dce055d0 140 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 6:38f7dce055d0 141 {
MikamiUitOpen 6:38f7dce055d0 142 aquire();
MikamiUitOpen 6:38f7dce055d0 143 _callback = callback;
MikamiUitOpen 6:38f7dce055d0 144 _irq.callback(&SPI::irq_handler_asynch);
MikamiUitOpen 6:38f7dce055d0 145 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
MikamiUitOpen 6:38f7dce055d0 146 }
MikamiUitOpen 6:38f7dce055d0 147
MikamiUitOpen 6:38f7dce055d0 148 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 6:38f7dce055d0 149
MikamiUitOpen 6:38f7dce055d0 150 void SPI::start_transaction(transaction_t *data)
MikamiUitOpen 6:38f7dce055d0 151 {
MikamiUitOpen 6:38f7dce055d0 152 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
MikamiUitOpen 6:38f7dce055d0 153 }
MikamiUitOpen 6:38f7dce055d0 154
MikamiUitOpen 6:38f7dce055d0 155 void SPI::dequeue_transaction()
MikamiUitOpen 6:38f7dce055d0 156 {
MikamiUitOpen 6:38f7dce055d0 157 Transaction<SPI> t;
MikamiUitOpen 6:38f7dce055d0 158 if (_transaction_buffer.pop(t)) {
MikamiUitOpen 6:38f7dce055d0 159 SPI* obj = t.get_object();
MikamiUitOpen 6:38f7dce055d0 160 transaction_t* data = t.get_transaction();
MikamiUitOpen 6:38f7dce055d0 161 obj->start_transaction(data);
MikamiUitOpen 6:38f7dce055d0 162 }
MikamiUitOpen 6:38f7dce055d0 163 }
MikamiUitOpen 6:38f7dce055d0 164
MikamiUitOpen 6:38f7dce055d0 165 #endif
MikamiUitOpen 6:38f7dce055d0 166
MikamiUitOpen 6:38f7dce055d0 167 void SPI::irq_handler_asynch(void)
MikamiUitOpen 6:38f7dce055d0 168 {
MikamiUitOpen 6:38f7dce055d0 169 int event = spi_irq_handler_asynch(&_spi);
MikamiUitOpen 6:38f7dce055d0 170 if (_callback && (event & SPI_EVENT_ALL)) {
MikamiUitOpen 6:38f7dce055d0 171 _callback.call(event & SPI_EVENT_ALL);
MikamiUitOpen 6:38f7dce055d0 172 }
MikamiUitOpen 6:38f7dce055d0 173 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 6:38f7dce055d0 174 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
MikamiUitOpen 6:38f7dce055d0 175 // SPI peripheral is free (event happend), dequeue transaction
MikamiUitOpen 6:38f7dce055d0 176 dequeue_transaction();
MikamiUitOpen 6:38f7dce055d0 177 }
MikamiUitOpen 6:38f7dce055d0 178 #endif
MikamiUitOpen 6:38f7dce055d0 179 }
MikamiUitOpen 6:38f7dce055d0 180
MikamiUitOpen 6:38f7dce055d0 181 #endif
MikamiUitOpen 6:38f7dce055d0 182
MikamiUitOpen 6:38f7dce055d0 183 } // namespace mbed
MikamiUitOpen 6:38f7dce055d0 184
MikamiUitOpen 6:38f7dce055d0 185 #endif