不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/common/InterruptIn.cpp@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /* mbed Microcontroller Library
MikamiUitOpen 6:38f7dce055d0 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 6:38f7dce055d0 3 *
MikamiUitOpen 6:38f7dce055d0 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 6:38f7dce055d0 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 6:38f7dce055d0 6 * You may obtain a copy of the License at
MikamiUitOpen 6:38f7dce055d0 7 *
MikamiUitOpen 6:38f7dce055d0 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 6:38f7dce055d0 9 *
MikamiUitOpen 6:38f7dce055d0 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 6:38f7dce055d0 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 6:38f7dce055d0 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 6:38f7dce055d0 13 * See the License for the specific language governing permissions and
MikamiUitOpen 6:38f7dce055d0 14 * limitations under the License.
MikamiUitOpen 6:38f7dce055d0 15 */
MikamiUitOpen 6:38f7dce055d0 16 #include "InterruptIn.h"
MikamiUitOpen 6:38f7dce055d0 17
MikamiUitOpen 6:38f7dce055d0 18 #if DEVICE_INTERRUPTIN
MikamiUitOpen 6:38f7dce055d0 19
MikamiUitOpen 6:38f7dce055d0 20 namespace mbed {
MikamiUitOpen 6:38f7dce055d0 21
MikamiUitOpen 6:38f7dce055d0 22 InterruptIn::InterruptIn(PinName pin) : gpio(),
MikamiUitOpen 6:38f7dce055d0 23 gpio_irq(),
MikamiUitOpen 6:38f7dce055d0 24 _rise(),
MikamiUitOpen 6:38f7dce055d0 25 _fall() {
MikamiUitOpen 6:38f7dce055d0 26 gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
MikamiUitOpen 6:38f7dce055d0 27 gpio_init_in(&gpio, pin);
MikamiUitOpen 6:38f7dce055d0 28 }
MikamiUitOpen 6:38f7dce055d0 29
MikamiUitOpen 6:38f7dce055d0 30 InterruptIn::~InterruptIn() {
MikamiUitOpen 6:38f7dce055d0 31 gpio_irq_free(&gpio_irq);
MikamiUitOpen 6:38f7dce055d0 32 }
MikamiUitOpen 6:38f7dce055d0 33
MikamiUitOpen 6:38f7dce055d0 34 int InterruptIn::read() {
MikamiUitOpen 6:38f7dce055d0 35 return gpio_read(&gpio);
MikamiUitOpen 6:38f7dce055d0 36 }
MikamiUitOpen 6:38f7dce055d0 37
MikamiUitOpen 6:38f7dce055d0 38 void InterruptIn::mode(PinMode pull) {
MikamiUitOpen 6:38f7dce055d0 39 gpio_mode(&gpio, pull);
MikamiUitOpen 6:38f7dce055d0 40 }
MikamiUitOpen 6:38f7dce055d0 41
MikamiUitOpen 6:38f7dce055d0 42 void InterruptIn::rise(void (*fptr)(void)) {
MikamiUitOpen 6:38f7dce055d0 43 if (fptr) {
MikamiUitOpen 6:38f7dce055d0 44 _rise.attach(fptr);
MikamiUitOpen 6:38f7dce055d0 45 gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
MikamiUitOpen 6:38f7dce055d0 46 } else {
MikamiUitOpen 6:38f7dce055d0 47 _rise.attach(NULL);
MikamiUitOpen 6:38f7dce055d0 48 gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
MikamiUitOpen 6:38f7dce055d0 49 }
MikamiUitOpen 6:38f7dce055d0 50 }
MikamiUitOpen 6:38f7dce055d0 51
MikamiUitOpen 6:38f7dce055d0 52 void InterruptIn::fall(void (*fptr)(void)) {
MikamiUitOpen 6:38f7dce055d0 53 if (fptr) {
MikamiUitOpen 6:38f7dce055d0 54 _fall.attach(fptr);
MikamiUitOpen 6:38f7dce055d0 55 gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
MikamiUitOpen 6:38f7dce055d0 56 } else {
MikamiUitOpen 6:38f7dce055d0 57 _fall.attach(NULL);
MikamiUitOpen 6:38f7dce055d0 58 gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
MikamiUitOpen 6:38f7dce055d0 59 }
MikamiUitOpen 6:38f7dce055d0 60 }
MikamiUitOpen 6:38f7dce055d0 61
MikamiUitOpen 6:38f7dce055d0 62 void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
MikamiUitOpen 6:38f7dce055d0 63 InterruptIn *handler = (InterruptIn*)id;
MikamiUitOpen 6:38f7dce055d0 64 switch (event) {
MikamiUitOpen 6:38f7dce055d0 65 case IRQ_RISE: handler->_rise.call(); break;
MikamiUitOpen 6:38f7dce055d0 66 case IRQ_FALL: handler->_fall.call(); break;
MikamiUitOpen 6:38f7dce055d0 67 case IRQ_NONE: break;
MikamiUitOpen 6:38f7dce055d0 68 }
MikamiUitOpen 6:38f7dce055d0 69 }
MikamiUitOpen 6:38f7dce055d0 70
MikamiUitOpen 6:38f7dce055d0 71 void InterruptIn::enable_irq() {
MikamiUitOpen 6:38f7dce055d0 72 gpio_irq_enable(&gpio_irq);
MikamiUitOpen 6:38f7dce055d0 73 }
MikamiUitOpen 6:38f7dce055d0 74
MikamiUitOpen 6:38f7dce055d0 75 void InterruptIn::disable_irq() {
MikamiUitOpen 6:38f7dce055d0 76 gpio_irq_disable(&gpio_irq);
MikamiUitOpen 6:38f7dce055d0 77 }
MikamiUitOpen 6:38f7dce055d0 78
MikamiUitOpen 6:38f7dce055d0 79 #ifdef MBED_OPERATORS
MikamiUitOpen 6:38f7dce055d0 80 InterruptIn::operator int() {
MikamiUitOpen 6:38f7dce055d0 81 return read();
MikamiUitOpen 6:38f7dce055d0 82 }
MikamiUitOpen 6:38f7dce055d0 83 #endif
MikamiUitOpen 6:38f7dce055d0 84
MikamiUitOpen 6:38f7dce055d0 85 } // namespace mbed
MikamiUitOpen 6:38f7dce055d0 86
MikamiUitOpen 6:38f7dce055d0 87 #endif