不韋 呂 / Mbed 2 deprecated CQ_DigitalFilterLab_ADC

CQエレクトロニクス･セミナ「実習・マイコンを動かしながら学ぶディジタル･フィルタ」で使うプログラムを，入力として STM32F746 の内蔵 ADC を使うように変更したもの． http://seminar.cqpub.co.jp/ccm/ES18-0020

Dependencies:   mbed Array_Matrix BSP_DISCO_F746NG LCD_DISCO_F746NG TS_DISCO_F746NG

F764_Adc/F746_ADC.hpp@2:dd48e1e59daa, 2018-03-12 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Mar 12 05:10:31 2018 +0000
Revision:
2:dd48e1e59daa
Parent:
0:ab7a35d87173 
3

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 0:ab7a35d87173 1 //----------------------------------------------------------
MikamiUitOpen 0:ab7a35d87173 2 // Simultanuous AD Conversion by polling using
MikamiUitOpen 0:ab7a35d87173 3 // ADC1 and ADC3 on STM32F746 ---- Header
MikamiUitOpen 0:ab7a35d87173 4 //
MikamiUitOpen 0:ab7a35d87173 5 // STM32F746 の ADC1, ADC3 を使って同時に AD 変換を開始し，
MikamiUitOpen 0:ab7a35d87173 6 // ポーリングによりアナログ信号を入力するクラス
MikamiUitOpen 0:ab7a35d87173 7 // PA_0 (DISCO-F746 の A0) : ADC1 CH0
MikamiUitOpen 0:ab7a35d87173 8 // PF_10 (DISCO-F746 の A1) : ADC3 CH8
MikamiUitOpen 0:ab7a35d87173 9 //
MikamiUitOpen 0:ab7a35d87173 10 // Read() の引数：
MikamiUitOpen 0:ab7a35d87173 11 // 第一引数：A0 (左)，第二引数：A1 (右)
MikamiUitOpen 0:ab7a35d87173 12 //
MikamiUitOpen 0:ab7a35d87173 13 // 2017/08/16, Copyright (c) 2017 MIKAMI, Naoki
MikamiUitOpen 0:ab7a35d87173 14 //----------------------------------------------------------
MikamiUitOpen 0:ab7a35d87173 15
MikamiUitOpen 0:ab7a35d87173 16 #include "mbed.h"
MikamiUitOpen 0:ab7a35d87173 17
MikamiUitOpen 0:ab7a35d87173 18 #ifndef STM32F746xx
MikamiUitOpen 0:ab7a35d87173 19 #error Target is not STM32F746
MikamiUitOpen 0:ab7a35d87173 20 #endif
MikamiUitOpen 0:ab7a35d87173 21
MikamiUitOpen 0:ab7a35d87173 22 #ifndef F746_ADC_DUAL_HPP
MikamiUitOpen 0:ab7a35d87173 23 #define F746_ADC_DUAL_HPP
MikamiUitOpen 0:ab7a35d87173 24
MikamiUitOpen 0:ab7a35d87173 25 namespace Mikami
MikamiUitOpen 0:ab7a35d87173 26 {
MikamiUitOpen 0:ab7a35d87173 27 class AdcDual
MikamiUitOpen 0:ab7a35d87173 28 {
MikamiUitOpen 0:ab7a35d87173 29 public:
MikamiUitOpen 0:ab7a35d87173 30 // Constructor
MikamiUitOpen 0:ab7a35d87173 31 // frequency: 標本化周波数
MikamiUitOpen 0:ab7a35d87173 32 explicit AdcDual(int frequency);
MikamiUitOpen 0:ab7a35d87173 33
MikamiUitOpen 0:ab7a35d87173 34 virtual ~AdcDual() {}
MikamiUitOpen 0:ab7a35d87173 35
MikamiUitOpen 0:ab7a35d87173 36 // -1.0f <= ad1, ad2 <= 1.0f
MikamiUitOpen 0:ab7a35d87173 37 // ad1: left, ad2: right
MikamiUitOpen 0:ab7a35d87173 38 virtual void Read(float &ad1, float &ad2);
MikamiUitOpen 0:ab7a35d87173 39
MikamiUitOpen 0:ab7a35d87173 40 // 0 <= ad1, ad2 <= 4095
MikamiUitOpen 0:ab7a35d87173 41 // ad1: left, ad2: right
MikamiUitOpen 0:ab7a35d87173 42 virtual void Read(uint16_t &ad1, uint16_t &ad2);
MikamiUitOpen 0:ab7a35d87173 43
MikamiUitOpen 0:ab7a35d87173 44 protected:
MikamiUitOpen 0:ab7a35d87173 45 float ToFloat(uint16_t x)
MikamiUitOpen 0:ab7a35d87173 46 { return AMP_*(x - 2048); }
MikamiUitOpen 0:ab7a35d87173 47
MikamiUitOpen 0:ab7a35d87173 48 private:
MikamiUitOpen 0:ab7a35d87173 49 static const float AMP_ = 1.0f/2048.0f;
MikamiUitOpen 0:ab7a35d87173 50 static const uint32_t EOC13_ = ADC_CSR_EOC1 | ADC_CSR_EOC3;
MikamiUitOpen 0:ab7a35d87173 51
MikamiUitOpen 0:ab7a35d87173 52 // AD 変換が完了するまで待つ
MikamiUitOpen 0:ab7a35d87173 53 void WaitDone()
MikamiUitOpen 0:ab7a35d87173 54 { while((ADC->CSR & EOC13_) != EOC13_); }
MikamiUitOpen 0:ab7a35d87173 55
MikamiUitOpen 0:ab7a35d87173 56 // AD 変換器の外部トリガに使うタイマ (TIM6) の設定
MikamiUitOpen 0:ab7a35d87173 57 void SetTim6(int frequency);
MikamiUitOpen 0:ab7a35d87173 58
MikamiUitOpen 0:ab7a35d87173 59 // for inhibition of copy constructor
MikamiUitOpen 0:ab7a35d87173 60 AdcDual(const AdcDual&);
MikamiUitOpen 0:ab7a35d87173 61 // for inhibition of substitute operator
MikamiUitOpen 0:ab7a35d87173 62 AdcDual& operator=(const AdcDual&);
MikamiUitOpen 0:ab7a35d87173 63 };
MikamiUitOpen 0:ab7a35d87173 64 }
MikamiUitOpen 0:ab7a35d87173 65 #endif // F746_ADC_DUAL_HPP
MikamiUitOpen 0:ab7a35d87173 66
MikamiUitOpen 0:ab7a35d87173 67 /*
MikamiUitOpen 0:ab7a35d87173 68 typedef struct
MikamiUitOpen 0:ab7a35d87173 69 {
MikamiUitOpen 0:ab7a35d87173 70 __IO uint32_t SR; //!< ADC status register, Address offset: 0x00 //
MikamiUitOpen 0:ab7a35d87173 71 __IO uint32_t CR1; //!< ADC control register 1, Address offset: 0x04 //
MikamiUitOpen 0:ab7a35d87173 72 __IO uint32_t CR2; //!< ADC control register 2, Address offset: 0x08 //
MikamiUitOpen 0:ab7a35d87173 73 __IO uint32_t SMPR1; //!< ADC sample time register 1, Address offset: 0x0C //
MikamiUitOpen 0:ab7a35d87173 74 __IO uint32_t SMPR2; //!< ADC sample time register 2, Address offset: 0x10 //
MikamiUitOpen 0:ab7a35d87173 75 __IO uint32_t JOFR1; //!< ADC injected channel data offset register 1, Address offset: 0x14 //
MikamiUitOpen 0:ab7a35d87173 76 __IO uint32_t JOFR2; //!< ADC injected channel data offset register 2, Address offset: 0x18 //
MikamiUitOpen 0:ab7a35d87173 77 __IO uint32_t JOFR3; //!< ADC injected channel data offset register 3, Address offset: 0x1C //
MikamiUitOpen 0:ab7a35d87173 78 __IO uint32_t JOFR4; //!< ADC injected channel data offset register 4, Address offset: 0x20 //
MikamiUitOpen 0:ab7a35d87173 79 __IO uint32_t HTR; //!< ADC watchdog higher threshold register, Address offset: 0x24 //
MikamiUitOpen 0:ab7a35d87173 80 __IO uint32_t LTR; //!< ADC watchdog lower threshold register, Address offset: 0x28 //
MikamiUitOpen 0:ab7a35d87173 81 __IO uint32_t SQR1; //!< ADC regular sequence register 1, Address offset: 0x2C //
MikamiUitOpen 0:ab7a35d87173 82 __IO uint32_t SQR2; //!< ADC regular sequence register 2, Address offset: 0x30 //
MikamiUitOpen 0:ab7a35d87173 83 __IO uint32_t SQR3; //!< ADC regular sequence register 3, Address offset: 0x34 //
MikamiUitOpen 0:ab7a35d87173 84 __IO uint32_t JSQR; //!< ADC injected sequence register, Address offset: 0x38 //
MikamiUitOpen 0:ab7a35d87173 85 __IO uint32_t JDR1; //!< ADC injected data register 1, Address offset: 0x3C //
MikamiUitOpen 0:ab7a35d87173 86 __IO uint32_t JDR2; //!< ADC injected data register 2, Address offset: 0x40 //
MikamiUitOpen 0:ab7a35d87173 87 __IO uint32_t JDR3; //!< ADC injected data register 3, Address offset: 0x44 //
MikamiUitOpen 0:ab7a35d87173 88 __IO uint32_t JDR4; //!< ADC injected data register 4, Address offset: 0x48 //
MikamiUitOpen 0:ab7a35d87173 89 __IO uint32_t DR; //!< ADC regular data register, Address offset: 0x4C //
MikamiUitOpen 0:ab7a35d87173 90 } ADC_TypeDef;
MikamiUitOpen 0:ab7a35d87173 91
MikamiUitOpen 0:ab7a35d87173 92 typedef struct
MikamiUitOpen 0:ab7a35d87173 93 {
MikamiUitOpen 0:ab7a35d87173 94 __IO uint32_t CSR; //!< ADC Common status register, Address offset: ADC1 base address + 0x300 //
MikamiUitOpen 0:ab7a35d87173 95 __IO uint32_t CCR; //!< ADC common control register, Address offset: ADC1 base address + 0x304 //
MikamiUitOpen 0:ab7a35d87173 96 __IO uint32_t CDR; //!< ADC common regular data register for dual
MikamiUitOpen 0:ab7a35d87173 97 AND triple modes, Address offset: ADC1 base address + 0x308 //
MikamiUitOpen 0:ab7a35d87173 98 } ADC_Common_TypeDef;
MikamiUitOpen 0:ab7a35d87173 99 */