Teste Flash
Dependencies: pulga-lorawan-drv Si1133 BME280
SPI_MX25R.cpp@70:99b7a15c09da, 2021-09-13 (annotated)
- Committer:
- MatteusCarr
- Date:
- Mon Sep 13 18:55:32 2021 +0000
- Revision:
- 70:99b7a15c09da
Teste Flash
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
MatteusCarr | 70:99b7a15c09da | 1 | /* |
MatteusCarr | 70:99b7a15c09da | 2 | * SPI_MX25R Series SPI-Flash Memory |
MatteusCarr | 70:99b7a15c09da | 3 | * Macronix Low Power Serial NOR Flash |
MatteusCarr | 70:99b7a15c09da | 4 | * (x2, and x4 I/O modes not implemented) |
MatteusCarr | 70:99b7a15c09da | 5 | */ |
MatteusCarr | 70:99b7a15c09da | 6 | |
MatteusCarr | 70:99b7a15c09da | 7 | #include "SPI_MX25R.h" |
MatteusCarr | 70:99b7a15c09da | 8 | |
MatteusCarr | 70:99b7a15c09da | 9 | |
MatteusCarr | 70:99b7a15c09da | 10 | SPI_MX25R::SPI_MX25R(PinName mosi, PinName miso, PinName sclk, PinName cs) : |
MatteusCarr | 70:99b7a15c09da | 11 | m_spi(mosi, miso, sclk), m_cs(cs) { } |
MatteusCarr | 70:99b7a15c09da | 12 | |
MatteusCarr | 70:99b7a15c09da | 13 | SPI_MX25R::~SPI_MX25R() { } |
MatteusCarr | 70:99b7a15c09da | 14 | |
MatteusCarr | 70:99b7a15c09da | 15 | void SPI_MX25R::writeEnable(void) |
MatteusCarr | 70:99b7a15c09da | 16 | { |
MatteusCarr | 70:99b7a15c09da | 17 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 18 | m_spi.write(CMD_WREN) ; |
MatteusCarr | 70:99b7a15c09da | 19 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 20 | } |
MatteusCarr | 70:99b7a15c09da | 21 | |
MatteusCarr | 70:99b7a15c09da | 22 | void SPI_MX25R::writeDisable(void) |
MatteusCarr | 70:99b7a15c09da | 23 | { |
MatteusCarr | 70:99b7a15c09da | 24 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 25 | m_spi.write(CMD_WRDI) ; |
MatteusCarr | 70:99b7a15c09da | 26 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 27 | } |
MatteusCarr | 70:99b7a15c09da | 28 | |
MatteusCarr | 70:99b7a15c09da | 29 | void SPI_MX25R::resetEnable(void) |
MatteusCarr | 70:99b7a15c09da | 30 | { |
MatteusCarr | 70:99b7a15c09da | 31 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 32 | m_spi.write(CMD_RSTEN) ; |
MatteusCarr | 70:99b7a15c09da | 33 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 34 | } |
MatteusCarr | 70:99b7a15c09da | 35 | |
MatteusCarr | 70:99b7a15c09da | 36 | void SPI_MX25R::reset(void) |
MatteusCarr | 70:99b7a15c09da | 37 | { |
MatteusCarr | 70:99b7a15c09da | 38 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 39 | m_spi.write(CMD_RST) ; |
MatteusCarr | 70:99b7a15c09da | 40 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 41 | } |
MatteusCarr | 70:99b7a15c09da | 42 | |
MatteusCarr | 70:99b7a15c09da | 43 | void SPI_MX25R::pgmersSuspend(void) |
MatteusCarr | 70:99b7a15c09da | 44 | { |
MatteusCarr | 70:99b7a15c09da | 45 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 46 | m_spi.write(CMD_PESUS) ; |
MatteusCarr | 70:99b7a15c09da | 47 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 48 | } |
MatteusCarr | 70:99b7a15c09da | 49 | |
MatteusCarr | 70:99b7a15c09da | 50 | void SPI_MX25R::pgmersResume(void) |
MatteusCarr | 70:99b7a15c09da | 51 | { |
MatteusCarr | 70:99b7a15c09da | 52 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 53 | m_spi.write(CMD_PERES) ; |
MatteusCarr | 70:99b7a15c09da | 54 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 55 | } |
MatteusCarr | 70:99b7a15c09da | 56 | |
MatteusCarr | 70:99b7a15c09da | 57 | void SPI_MX25R::deepPowerdown(void) |
MatteusCarr | 70:99b7a15c09da | 58 | { |
MatteusCarr | 70:99b7a15c09da | 59 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 60 | m_spi.write(CMD_DP) ; |
MatteusCarr | 70:99b7a15c09da | 61 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 62 | } |
MatteusCarr | 70:99b7a15c09da | 63 | |
MatteusCarr | 70:99b7a15c09da | 64 | void SPI_MX25R::setBurstlength(void) |
MatteusCarr | 70:99b7a15c09da | 65 | { |
MatteusCarr | 70:99b7a15c09da | 66 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 67 | m_spi.write(CMD_SBL) ; |
MatteusCarr | 70:99b7a15c09da | 68 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 69 | } |
MatteusCarr | 70:99b7a15c09da | 70 | |
MatteusCarr | 70:99b7a15c09da | 71 | void SPI_MX25R::releaseReadenhaced(void) |
MatteusCarr | 70:99b7a15c09da | 72 | { |
MatteusCarr | 70:99b7a15c09da | 73 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 74 | m_spi.write(CMD_RRE) ; |
MatteusCarr | 70:99b7a15c09da | 75 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 76 | } |
MatteusCarr | 70:99b7a15c09da | 77 | |
MatteusCarr | 70:99b7a15c09da | 78 | void SPI_MX25R::noOperation(void) |
MatteusCarr | 70:99b7a15c09da | 79 | { |
MatteusCarr | 70:99b7a15c09da | 80 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 81 | m_spi.write(CMD_NOP) ; |
MatteusCarr | 70:99b7a15c09da | 82 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 83 | } |
MatteusCarr | 70:99b7a15c09da | 84 | |
MatteusCarr | 70:99b7a15c09da | 85 | void SPI_MX25R::enterSecureOTP(void) |
MatteusCarr | 70:99b7a15c09da | 86 | { |
MatteusCarr | 70:99b7a15c09da | 87 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 88 | m_spi.write(CMD_ENSO) ; |
MatteusCarr | 70:99b7a15c09da | 89 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 90 | } |
MatteusCarr | 70:99b7a15c09da | 91 | |
MatteusCarr | 70:99b7a15c09da | 92 | void SPI_MX25R::exitSecureOTP(void) |
MatteusCarr | 70:99b7a15c09da | 93 | { |
MatteusCarr | 70:99b7a15c09da | 94 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 95 | m_spi.write(CMD_EXSO) ; |
MatteusCarr | 70:99b7a15c09da | 96 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 97 | } |
MatteusCarr | 70:99b7a15c09da | 98 | |
MatteusCarr | 70:99b7a15c09da | 99 | uint8_t SPI_MX25R::readStatus(void) |
MatteusCarr | 70:99b7a15c09da | 100 | { |
MatteusCarr | 70:99b7a15c09da | 101 | uint8_t data ; |
MatteusCarr | 70:99b7a15c09da | 102 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 103 | m_spi.write(CMD_RDSR) ; |
MatteusCarr | 70:99b7a15c09da | 104 | data = m_spi.write(DUMMY) ; // dummy |
MatteusCarr | 70:99b7a15c09da | 105 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 106 | return( data ) ; |
MatteusCarr | 70:99b7a15c09da | 107 | } |
MatteusCarr | 70:99b7a15c09da | 108 | |
MatteusCarr | 70:99b7a15c09da | 109 | uint32_t SPI_MX25R::readConfig(void) |
MatteusCarr | 70:99b7a15c09da | 110 | { |
MatteusCarr | 70:99b7a15c09da | 111 | uint8_t data; |
MatteusCarr | 70:99b7a15c09da | 112 | uint32_t config32 = 0 ; |
MatteusCarr | 70:99b7a15c09da | 113 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 114 | m_spi.write(CMD_RDCR) ; // send 15h |
MatteusCarr | 70:99b7a15c09da | 115 | data= m_spi.write(DUMMY) ; // dumy to get 1st Byte out |
MatteusCarr | 70:99b7a15c09da | 116 | config32 = config32 | data ; // put in 32b reg |
MatteusCarr | 70:99b7a15c09da | 117 | data= m_spi.write(DUMMY) ; // dummy to get 2nd Byte out |
MatteusCarr | 70:99b7a15c09da | 118 | config32 = (config32 << 8) | data ; // shift and put in reg |
MatteusCarr | 70:99b7a15c09da | 119 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 120 | return( config32 ) ; |
MatteusCarr | 70:99b7a15c09da | 121 | } |
MatteusCarr | 70:99b7a15c09da | 122 | |
MatteusCarr | 70:99b7a15c09da | 123 | uint8_t SPI_MX25R::readSecurity(void) |
MatteusCarr | 70:99b7a15c09da | 124 | { |
MatteusCarr | 70:99b7a15c09da | 125 | uint8_t data ; |
MatteusCarr | 70:99b7a15c09da | 126 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 127 | m_spi.write(CMD_RDSCUR) ; // send 2Bh |
MatteusCarr | 70:99b7a15c09da | 128 | data = m_spi.write(DUMMY) ; // dummy |
MatteusCarr | 70:99b7a15c09da | 129 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 130 | return( data ) ; |
MatteusCarr | 70:99b7a15c09da | 131 | } |
MatteusCarr | 70:99b7a15c09da | 132 | |
MatteusCarr | 70:99b7a15c09da | 133 | uint32_t SPI_MX25R::readID(void) |
MatteusCarr | 70:99b7a15c09da | 134 | { |
MatteusCarr | 70:99b7a15c09da | 135 | uint8_t data; |
MatteusCarr | 70:99b7a15c09da | 136 | uint32_t data32 = 0 ; |
MatteusCarr | 70:99b7a15c09da | 137 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 138 | m_spi.write(CMD_RDID) ; // send 9Fh |
MatteusCarr | 70:99b7a15c09da | 139 | data= m_spi.write(DUMMY) ; // dumy to get 1st Byte out |
MatteusCarr | 70:99b7a15c09da | 140 | data32 = data32 | data ; // put in 32b reg |
MatteusCarr | 70:99b7a15c09da | 141 | data= m_spi.write(DUMMY) ; // dummy to get 2nd Byte out |
MatteusCarr | 70:99b7a15c09da | 142 | data32 = (data32 << 8) | data ; // shift and put in reg |
MatteusCarr | 70:99b7a15c09da | 143 | data= m_spi.write(DUMMY) ; // dummy to get 3rd Byte out |
MatteusCarr | 70:99b7a15c09da | 144 | data32 = (data32 << 8) | data ; // shift again and put in reg |
MatteusCarr | 70:99b7a15c09da | 145 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 146 | return( data32 ) ; |
MatteusCarr | 70:99b7a15c09da | 147 | } |
MatteusCarr | 70:99b7a15c09da | 148 | |
MatteusCarr | 70:99b7a15c09da | 149 | uint32_t SPI_MX25R::readREMS(void) |
MatteusCarr | 70:99b7a15c09da | 150 | { |
MatteusCarr | 70:99b7a15c09da | 151 | uint8_t data; |
MatteusCarr | 70:99b7a15c09da | 152 | uint32_t data32 = 0 ; |
MatteusCarr | 70:99b7a15c09da | 153 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 154 | m_spi.write(CMD_REMS) ; // send 90h |
MatteusCarr | 70:99b7a15c09da | 155 | m_spi.write(DUMMY) ; // send DUMMY1 |
MatteusCarr | 70:99b7a15c09da | 156 | m_spi.write(DUMMY) ; // send DUMMY2 |
MatteusCarr | 70:99b7a15c09da | 157 | m_spi.write(0) ; // send address=0x00 to get Manu ID 1st. |
MatteusCarr | 70:99b7a15c09da | 158 | data= m_spi.write(DUMMY) ; // dumy to get Manufacturer ID= C2h out |
MatteusCarr | 70:99b7a15c09da | 159 | data32 = data32 | data ; // put in 32b reg |
MatteusCarr | 70:99b7a15c09da | 160 | data= m_spi.write(DUMMY) ; // dummy to get 2nd Byte = Device ID out |
MatteusCarr | 70:99b7a15c09da | 161 | data32 = (data32 << 8) | data ; // shift and put in reg |
MatteusCarr | 70:99b7a15c09da | 162 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 163 | return( data32 ) ; |
MatteusCarr | 70:99b7a15c09da | 164 | } |
MatteusCarr | 70:99b7a15c09da | 165 | |
MatteusCarr | 70:99b7a15c09da | 166 | uint8_t SPI_MX25R::readRES(void) |
MatteusCarr | 70:99b7a15c09da | 167 | { |
MatteusCarr | 70:99b7a15c09da | 168 | uint8_t data; |
MatteusCarr | 70:99b7a15c09da | 169 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 170 | m_spi.write(CMD_RES) ; // send ABh |
MatteusCarr | 70:99b7a15c09da | 171 | m_spi.write(DUMMY) ; // send DUMMY1 |
MatteusCarr | 70:99b7a15c09da | 172 | m_spi.write(DUMMY) ; // send DUMMY2 |
MatteusCarr | 70:99b7a15c09da | 173 | m_spi.write(DUMMY) ; // send DUMMY3 |
MatteusCarr | 70:99b7a15c09da | 174 | data= m_spi.write(DUMMY) ; // dumy to get Electronic Sig. out |
MatteusCarr | 70:99b7a15c09da | 175 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 176 | return( data ) ; |
MatteusCarr | 70:99b7a15c09da | 177 | } |
MatteusCarr | 70:99b7a15c09da | 178 | |
MatteusCarr | 70:99b7a15c09da | 179 | void SPI_MX25R::programPage(int addr, uint8_t *data, int numData) |
MatteusCarr | 70:99b7a15c09da | 180 | { |
MatteusCarr | 70:99b7a15c09da | 181 | int i ; |
MatteusCarr | 70:99b7a15c09da | 182 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 183 | m_spi.write(CMD_PP) ; // Program Page 02h |
MatteusCarr | 70:99b7a15c09da | 184 | m_spi.write((addr >> 16)&0xFF) ; // adr 23:16 |
MatteusCarr | 70:99b7a15c09da | 185 | m_spi.write((addr >> 8)&0xFF) ; // adr 15:8 |
MatteusCarr | 70:99b7a15c09da | 186 | m_spi.write(addr & 0xFF) ; // adr 7:0 |
MatteusCarr | 70:99b7a15c09da | 187 | for (i = 0 ; i < numData ; i++ ) { // data = 00, 01, 02, .. to FEh, FFh = all 256 Bytes in 1 page. |
MatteusCarr | 70:99b7a15c09da | 188 | m_spi.write(data[i]) ; |
MatteusCarr | 70:99b7a15c09da | 189 | } |
MatteusCarr | 70:99b7a15c09da | 190 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 191 | // poll in main |
MatteusCarr | 70:99b7a15c09da | 192 | } |
MatteusCarr | 70:99b7a15c09da | 193 | |
MatteusCarr | 70:99b7a15c09da | 194 | void SPI_MX25R::writeStatusreg(int addr) // Write SR cmd 01h + 3B data |
MatteusCarr | 70:99b7a15c09da | 195 | { |
MatteusCarr | 70:99b7a15c09da | 196 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 197 | m_spi.write(CMD_WRSR) ; // Write SR cmd 01h |
MatteusCarr | 70:99b7a15c09da | 198 | m_spi.write((addr >> 16)&0xFF) ; // address |
MatteusCarr | 70:99b7a15c09da | 199 | m_spi.write((addr >> 8)&0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 200 | m_spi.write(addr & 0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 201 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 202 | } |
MatteusCarr | 70:99b7a15c09da | 203 | |
MatteusCarr | 70:99b7a15c09da | 204 | void SPI_MX25R::writeSecurityreg(int addr) // WRSCUR cmd 2Fh + 1B data |
MatteusCarr | 70:99b7a15c09da | 205 | { |
MatteusCarr | 70:99b7a15c09da | 206 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 207 | m_spi.write(CMD_WRSCUR) ; // Write SR cmd 01h |
MatteusCarr | 70:99b7a15c09da | 208 | m_spi.write(addr & 0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 209 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 210 | } |
MatteusCarr | 70:99b7a15c09da | 211 | |
MatteusCarr | 70:99b7a15c09da | 212 | void SPI_MX25R::blockErase(int addr) // 64KB Block Erase |
MatteusCarr | 70:99b7a15c09da | 213 | { |
MatteusCarr | 70:99b7a15c09da | 214 | uint8_t data[3] ; |
MatteusCarr | 70:99b7a15c09da | 215 | data[0] = (addr >> 16) & 0xFF ; |
MatteusCarr | 70:99b7a15c09da | 216 | data[1] = (addr >> 8) & 0xFF ; |
MatteusCarr | 70:99b7a15c09da | 217 | data[2] = (addr & 0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 218 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 219 | m_spi.write(CMD_BE) ; |
MatteusCarr | 70:99b7a15c09da | 220 | for (int i = 0 ; i < 3 ; i++ ) { // Address setting |
MatteusCarr | 70:99b7a15c09da | 221 | m_spi.write(data[i]) ; |
MatteusCarr | 70:99b7a15c09da | 222 | } |
MatteusCarr | 70:99b7a15c09da | 223 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 224 | // poll in main |
MatteusCarr | 70:99b7a15c09da | 225 | } |
MatteusCarr | 70:99b7a15c09da | 226 | |
MatteusCarr | 70:99b7a15c09da | 227 | void SPI_MX25R::blockErase32KB(int addr) // 32KB Block Erase |
MatteusCarr | 70:99b7a15c09da | 228 | { |
MatteusCarr | 70:99b7a15c09da | 229 | uint8_t data[3] ; |
MatteusCarr | 70:99b7a15c09da | 230 | data[0] = (addr >> 16) & 0xFF ; |
MatteusCarr | 70:99b7a15c09da | 231 | data[1] = (addr >> 8) & 0xFF ; |
MatteusCarr | 70:99b7a15c09da | 232 | data[2] = (addr & 0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 233 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 234 | m_spi.write(CMD_32KBE) ; |
MatteusCarr | 70:99b7a15c09da | 235 | for (int i = 0 ; i < 3 ; i++ ) { // Address Setting |
MatteusCarr | 70:99b7a15c09da | 236 | m_spi.write(data[i]) ; |
MatteusCarr | 70:99b7a15c09da | 237 | } |
MatteusCarr | 70:99b7a15c09da | 238 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 239 | // poll in main |
MatteusCarr | 70:99b7a15c09da | 240 | } |
MatteusCarr | 70:99b7a15c09da | 241 | |
MatteusCarr | 70:99b7a15c09da | 242 | void SPI_MX25R::sectorErase(int addr) // 4KB Sector Erase |
MatteusCarr | 70:99b7a15c09da | 243 | { |
MatteusCarr | 70:99b7a15c09da | 244 | uint8_t data[3] ; |
MatteusCarr | 70:99b7a15c09da | 245 | data[0] = (addr >> 16) & 0xFF ; |
MatteusCarr | 70:99b7a15c09da | 246 | data[1] = (addr >> 8) & 0xFF ; |
MatteusCarr | 70:99b7a15c09da | 247 | data[2] = (addr & 0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 248 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 249 | m_spi.write(CMD_SE) ; |
MatteusCarr | 70:99b7a15c09da | 250 | for (int i = 0 ; i < 3 ; i++ ) { // Address Setting |
MatteusCarr | 70:99b7a15c09da | 251 | m_spi.write(data[i]) ; |
MatteusCarr | 70:99b7a15c09da | 252 | } |
MatteusCarr | 70:99b7a15c09da | 253 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 254 | // poll in main |
MatteusCarr | 70:99b7a15c09da | 255 | } |
MatteusCarr | 70:99b7a15c09da | 256 | |
MatteusCarr | 70:99b7a15c09da | 257 | void SPI_MX25R::chipErase(void) // Chip Erase |
MatteusCarr | 70:99b7a15c09da | 258 | { |
MatteusCarr | 70:99b7a15c09da | 259 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 260 | m_spi.write(CMD_CE) ; |
MatteusCarr | 70:99b7a15c09da | 261 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 262 | // poll in main |
MatteusCarr | 70:99b7a15c09da | 263 | } |
MatteusCarr | 70:99b7a15c09da | 264 | |
MatteusCarr | 70:99b7a15c09da | 265 | uint8_t SPI_MX25R::read8(int addr) // Single Byte Read |
MatteusCarr | 70:99b7a15c09da | 266 | { |
MatteusCarr | 70:99b7a15c09da | 267 | uint8_t data ; |
MatteusCarr | 70:99b7a15c09da | 268 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 269 | m_spi.write(CMD_READ) ; // send 03h |
MatteusCarr | 70:99b7a15c09da | 270 | m_spi.write((addr >> 16)&0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 271 | m_spi.write((addr >> 8)&0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 272 | m_spi.write(addr & 0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 273 | data = m_spi.write(DUMMY) ; // write data is dummy |
MatteusCarr | 70:99b7a15c09da | 274 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 275 | return( data ) ; // return 1 byte |
MatteusCarr | 70:99b7a15c09da | 276 | } |
MatteusCarr | 70:99b7a15c09da | 277 | |
MatteusCarr | 70:99b7a15c09da | 278 | uint8_t SPI_MX25R::readSFDP(int addr) // Read SFDP |
MatteusCarr | 70:99b7a15c09da | 279 | { |
MatteusCarr | 70:99b7a15c09da | 280 | uint8_t data ; |
MatteusCarr | 70:99b7a15c09da | 281 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 282 | m_spi.write(CMD_RDSFDP) ; // send cmd 5Ah |
MatteusCarr | 70:99b7a15c09da | 283 | m_spi.write((addr >> 16)&0xFF) ; // address[23:16] |
MatteusCarr | 70:99b7a15c09da | 284 | m_spi.write((addr >> 8)&0xFF) ; // address[15:8] |
MatteusCarr | 70:99b7a15c09da | 285 | m_spi.write(addr & 0xFF) ; // address[7:0] |
MatteusCarr | 70:99b7a15c09da | 286 | m_spi.write(DUMMY) ; // dummy cycle |
MatteusCarr | 70:99b7a15c09da | 287 | data = m_spi.write(DUMMY) ; // return 1 byte |
MatteusCarr | 70:99b7a15c09da | 288 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 289 | return( data ) ; |
MatteusCarr | 70:99b7a15c09da | 290 | } |
MatteusCarr | 70:99b7a15c09da | 291 | |
MatteusCarr | 70:99b7a15c09da | 292 | uint8_t SPI_MX25R::readFREAD(int addr) // x1 Fast Read Data Byte |
MatteusCarr | 70:99b7a15c09da | 293 | { |
MatteusCarr | 70:99b7a15c09da | 294 | uint8_t data ; |
MatteusCarr | 70:99b7a15c09da | 295 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 296 | m_spi.write(CMD_FREAD) ; // send cmd 0BH |
MatteusCarr | 70:99b7a15c09da | 297 | m_spi.write((addr >> 16)&0xFF) ; // address[23:16] |
MatteusCarr | 70:99b7a15c09da | 298 | m_spi.write((addr >> 8)&0xFF) ; // address[15:8] |
MatteusCarr | 70:99b7a15c09da | 299 | m_spi.write(addr & 0xFF) ; // address[7:0] |
MatteusCarr | 70:99b7a15c09da | 300 | m_spi.write(DUMMY) ; // dummy cycle |
MatteusCarr | 70:99b7a15c09da | 301 | data = m_spi.write(DUMMY) ; // return 1 byte |
MatteusCarr | 70:99b7a15c09da | 302 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 303 | return( data ) ; |
MatteusCarr | 70:99b7a15c09da | 304 | } |
MatteusCarr | 70:99b7a15c09da | 305 | |
MatteusCarr | 70:99b7a15c09da | 306 | |
MatteusCarr | 70:99b7a15c09da | 307 | void SPI_MX25R::readNBytes(int addr, uint8_t *data, int nBytes) // read sequential n bytes |
MatteusCarr | 70:99b7a15c09da | 308 | { |
MatteusCarr | 70:99b7a15c09da | 309 | int i; |
MatteusCarr | 70:99b7a15c09da | 310 | m_cs = CS_LOW ; |
MatteusCarr | 70:99b7a15c09da | 311 | m_spi.write(CMD_READ) ; // send 03h |
MatteusCarr | 70:99b7a15c09da | 312 | m_spi.write((addr >> 16)&0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 313 | m_spi.write((addr >> 8)&0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 314 | m_spi.write(addr & 0xFF) ; |
MatteusCarr | 70:99b7a15c09da | 315 | for (i = 0 ; i < nBytes ; i++ ) { // data: sequential data bytes |
MatteusCarr | 70:99b7a15c09da | 316 | data[i] = m_spi.write(DUMMY) ; |
MatteusCarr | 70:99b7a15c09da | 317 | } |
MatteusCarr | 70:99b7a15c09da | 318 | m_cs = CS_HIGH ; |
MatteusCarr | 70:99b7a15c09da | 319 | } |