stm32f30x_syscfg.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f30x_syscfg.c
00004   * @author  MCD Application Team
00005   * @version V1.2.3
00006   * @date    10-July-2015
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the SYSCFG peripheral:
00009   *           + Remapping the memory mapped at 0x00000000  
00010   *           + Remapping the DMA channels
00011   *           + Enabling I2C fast mode plus driving capability for I2C plus
00012   *           + Remapping USB interrupt line    
00013   *           + Configuring the EXTI lines connection to the GPIO port
00014   *           + Configuring the CLASSB requirements
00015   *   
00016   @verbatim
00017   
00018  ===============================================================================
00019                       ##### How to use this driver #####
00020  ===============================================================================
00021     [..] The SYSCFG registers can be accessed only when the SYSCFG 
00022          interface APB clock is enabled.
00023     [..] To enable SYSCFG APB clock use:
00024          RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE);
00025   
00026   @endverbatim
00027   
00028   ******************************************************************************
00029   * @attention
00030   *
00031   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
00032   *
00033   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00034   * You may not use this file except in compliance with the License.
00035   * You may obtain a copy of the License at:
00036   *
00037   *        http://www.st.com/software_license_agreement_liberty_v2
00038   *
00039   * Unless required by applicable law or agreed to in writing, software 
00040   * distributed under the License is distributed on an "AS IS" BASIS, 
00041   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00042   * See the License for the specific language governing permissions and
00043   * limitations under the License.
00044   *
00045   ******************************************************************************
00046   */
00047 
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f30x_syscfg.h"
00050 
00051 /** @addtogroup STM32F30x_StdPeriph_Driver
00052   * @{
00053   */
00054 
00055 /** @defgroup SYSCFG 
00056   * @brief SYSCFG driver modules
00057   * @{
00058   */ 
00059 
00060 /* Private typedef -----------------------------------------------------------*/
00061 /* Private define ------------------------------------------------------------*/
00062 /* Reset value of SYSCFG_CFGR1 register */
00063 #define CFGR1_CLEAR_MASK            ((uint32_t)0x7C000000)
00064 
00065 /* ------------ SYSCFG registers bit address in the alias region -------------*/
00066 #define SYSCFG_OFFSET                (SYSCFG_BASE - PERIPH_BASE)
00067 
00068 /* --- CFGR1 Register ---*/
00069 /* Alias word address of USB_IT_RMP bit */
00070 #define CFGR1_OFFSET                 (SYSCFG_OFFSET + 0x00)
00071 #define USBITRMP_BitNumber            0x05
00072 #define CFGR1_USBITRMP_BB            (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4))
00073 
00074 /* --- CFGR2 Register ---*/
00075 /* Alias word address of BYP_ADDR_PAR bit */
00076 #define CFGR2_OFFSET                 (SYSCFG_OFFSET + 0x18)
00077 #define BYPADDRPAR_BitNumber          0x04
00078 #define CFGR1_BYPADDRPAR_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
00079 
00080 /* Private macro -------------------------------------------------------------*/
00081 /* Private variables ---------------------------------------------------------*/
00082 /* Private function prototypes -----------------------------------------------*/
00083 /* Private functions ---------------------------------------------------------*/
00084 
00085 /** @defgroup SYSCFG_Private_Functions
00086   * @{
00087   */ 
00088 
00089 /** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
00090  *  @brief   SYSCFG Initialization and Configuration functions 
00091  *
00092 @verbatim
00093  ===============================================================================
00094          ##### SYSCFG Initialization and Configuration functions #####
00095  ===============================================================================
00096 
00097 @endverbatim
00098   * @{
00099   */
00100 
00101 /**
00102   * @brief  Deinitializes the SYSCFG registers to their default reset values.
00103   * @param  None
00104   * @retval None
00105   * @note   MEM_MODE bits are not affected by APB reset.
00106   *         MEM_MODE bits took the value from the user option bytes.
00107   */
00108 void SYSCFG_DeInit(void)
00109 {
00110   /* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
00111   SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
00112   /* Set FPU Interrupt Enable bits to default value */
00113   SYSCFG->CFGR1 |= 0x7C000000;
00114   /* Reset RAM Write protection bits to default value */
00115   SYSCFG->RCR = 0x00000000;
00116   /* Set EXTICRx registers to reset value */
00117   SYSCFG->EXTICR[0] = 0;
00118   SYSCFG->EXTICR[1] = 0;
00119   SYSCFG->EXTICR[2] = 0;
00120   SYSCFG->EXTICR[3] = 0;
00121   /* Set CFGR2 register to reset value */
00122   SYSCFG->CFGR2 = 0;
00123   /* Set CFGR3 register to reset value */
00124   SYSCFG->CFGR3 = 0;
00125   /* Set CFGR4 register to reset value */
00126   SYSCFG->CFGR4 = 0;
00127 }
00128 
00129 /**
00130   * @brief  Configures the memory mapping at address 0x00000000.
00131   * @param  SYSCFG_MemoryRemap: selects the memory remapping.
00132   *   This parameter can be one of the following values:
00133   *     @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000  
00134   *     @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
00135   *     @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
00136   *     @arg SYSCFG_MemoryRemap_FMC: External memory through FMC   
00137   * @retval None
00138   */
00139 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
00140 {
00141   uint32_t tmpcfgr1 = 0;
00142 
00143   /* Check the parameter */
00144   assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
00145 
00146   /* Get CFGR1 register value */
00147   tmpcfgr1 = SYSCFG->CFGR1;
00148 
00149   /* Clear MEM_MODE bits */
00150   tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
00151 
00152   /* Set the new MEM_MODE bits value */
00153   tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap;
00154 
00155   /* Set CFGR1 register with the new memory remap configuration */
00156   SYSCFG->CFGR1 = tmpcfgr1;
00157 }
00158 
00159 /**
00160   * @brief  Configures the DMA channels remapping.
00161   * @param  SYSCFG_DMARemap: selects the DMA channels remap.
00162   *   This parameter can be one of the following values:
00163   *     @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from DMA1 channel1 to channel2
00164   *     @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from DMA1 channel3 to channel4
00165   *     @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 DMA requests from DMA2 channel 3 to DMA1 channel 3
00166   *     @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC2 DMA requests from DMA2 channel 4 to DMA1 channel 4
00167   *     @arg SYSCFG_DMARemap_ADC2ADC4: Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4
00168   *     @arg SYSCFG_DMARemap_DAC2Ch1: Remap DAC2 DMA requests to DMA1 channel5
00169   *     @arg SYSCFG_DMARemapCh2_SPI1_RX: Remap SPI1 RX DMA1 CH2 requests
00170   *     @arg SYSCFG_DMARemapCh4_SPI1_RX: Remap SPI1 RX DMA CH4 requests        
00171   *     @arg SYSCFG_DMARemapCh6_SPI1_RX: Remap SPI1 RX DMA CH6 requests       
00172   *     @arg SYSCFG_DMARemapCh3_SPI1_TX: Remap SPI1 TX DMA CH2 requests      
00173   *     @arg SYSCFG_DMARemapCh5_SPI1_TX: Remap SPI1 TX DMA CH5 requests       
00174   *     @arg SYSCFG_DMARemapCh7_SPI1_TX: Remap SPI1 TX DMA CH7 requests       
00175   *     @arg SYSCFG_DMARemapCh7_I2C1_RX: Remap I2C1 RX DMA CH7 requests
00176   *     @arg SYSCFG_DMARemapCh3_I2C1_RX: Remap I2C1 RX DMA CH3 requests       
00177   *     @arg SYSCFG_DMARemapCh5_I2C1_RX: Remap I2C1 RX DMA CH5 requests      
00178   *     @arg SYSCFG_DMARemapCh6_I2C1_TX: Remap I2C1 TX DMA CH6 requests       
00179   *     @arg SYSCFG_DMARemapCh2_I2C1_TX: Remap I2C1 TX DMA CH2 requests       
00180   *     @arg SYSCFG_DMARemapCh4_I2C1_TX: Remap I2C1 TX DMA CH4 requests   
00181   *     @arg SYSCFG_DMARemapCh4_ADC2: Remap ADC2 DMA1 Ch4 requests    
00182   *     @arg SYSCFG_DMARemapCh2_ADC2: Remap ADC2 DMA1 Ch2 requests
00183   * @param  NewState: new state of the DMA channel remapping. 
00184   *         This parameter can be: Enable or Disable.
00185   * @note   When enabled, DMA channel of the selected peripheral is remapped
00186   * @note   When disabled, Default DMA channel is mapped to the selected peripheral
00187   * @note
00188   *           By default TIM17 DMA requests is mapped to channel 1
00189   *           use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
00190   *           to remap TIM17 DMA requests to DMA1 channel 2
00191   *           use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
00192   *           to map TIM17 DMA requests to DMA1 channel 1 (default mapping)
00193   * @retval None
00194   */
00195 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
00196 {
00197   /* Check the parameters */
00198   assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
00199   assert_param(IS_FUNCTIONAL_STATE(NewState));
00200 
00201   if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000)
00202   {
00203     if (NewState != DISABLE)
00204     {
00205       /* Remap the DMA channel */
00206       SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
00207     }
00208     else
00209     {
00210       /* use the default DMA channel mapping */
00211       SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
00212     }
00213   }
00214   else
00215   {
00216     if (NewState != DISABLE)
00217     {
00218       /* Remap the DMA channel */
00219       SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap;
00220     }
00221     else
00222     {
00223       /* use the default DMA channel mapping */
00224       SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap);
00225     }
00226   }
00227 }
00228 
00229 /**
00230   * @brief  Configures the remapping capabilities of DAC/TIM triggers.
00231   * @param  SYSCFG_TriggerRemap: selects the trigger to be remapped.
00232   *   This parameter can be one of the following values:
00233   *     @arg SYSCFG_TriggerRemap_DACTIM3: Remap DAC trigger from TIM8 to TIM3
00234   *     @arg SYSCFG_TriggerRemap_TIM1TIM17: Remap TIM1 ITR3 from TIM4 TRGO to TIM17 OC
00235   *     @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG1: Remap DAC trigger to HRTIM1 TRIG1
00236   *     @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG2: Remap DAC trigger to HRTIM1 TRIG2    
00237   * @param  NewState: new state of the trigger mapping. 
00238   *         This parameter can be: ENABLE or DISABLE.
00239   * @note   ENABLE:  Enable fast mode plus driving capability for selected pin
00240   * @note   DISABLE: Disable fast mode plus driving capability for selected pin
00241   * @retval None
00242   */
00243 void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState)
00244 {
00245   /* Check the parameters */
00246   assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap));
00247   assert_param(IS_FUNCTIONAL_STATE(NewState));
00248   
00249   if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000)
00250   {
00251     if (NewState != DISABLE)
00252     {
00253       /* Remap the trigger */
00254       SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap;
00255     }
00256     else
00257     {
00258       /* Use the default trigger mapping */
00259       SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap);
00260     }
00261   }
00262   else
00263   {
00264     if (NewState != DISABLE)
00265     {
00266       /* Remap the trigger */
00267       SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap;
00268     }
00269     else
00270     {
00271       /* Use the default trigger mapping */
00272       SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap);
00273     }
00274   }
00275 }
00276 
00277 /**
00278   * @brief  Configures the remapping capabilities of encoder mode.
00279   * @ note This feature implement the so-called M/T method for measuring speed
00280   *        and position using quadrature encoders.  
00281   * @param  SYSCFG_EncoderRemap: selects the remap option for encoder mode.
00282   *   This parameter can be one of the following values:
00283   *     @arg SYSCFG_EncoderRemap_No: No remap
00284   *     @arg SYSCFG_EncoderRemap_TIM2: Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2
00285   *     @arg SYSCFG_EncoderRemap_TIM3: Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2
00286   *     @arg SYSCFG_EncoderRemap_TIM4: Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2
00287   * @retval None
00288   */
00289 void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap)
00290 {
00291   /* Check the parameter */
00292   assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap));
00293 
00294   /* Reset the encoder mode remapping bits */
00295   SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE);
00296 
00297   /* Set the selected configuration */
00298   SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap);
00299 }
00300 
00301 /**
00302   * @brief  Remaps the USB interrupt lines.
00303   * @param  NewState: new state of the mapping of USB interrupt lines. 
00304   *         This parameter can be:
00305   * @param  ENABLE: Remap the USB interrupt line as following:
00306   *         @arg  USB Device High Priority (USB_HP) interrupt mapped to line 74.
00307   *         @arg  USB Device Low Priority (USB_LP) interrupt mapped to line 75.
00308   *         @arg  USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 76.
00309   * @param  DISABLE: Use the default USB interrupt line:
00310   *         @arg  USB Device High Priority (USB_HP) interrupt mapped to line 19.
00311   *         @arg  USB Device Low Priority (USB_LP) interrupt mapped to line 20.
00312   *         @arg  USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 42.
00313   * @retval None
00314   */
00315 void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState)
00316 {
00317   /* Check the parameter */
00318   assert_param(IS_FUNCTIONAL_STATE(NewState));
00319 
00320   /* Remap the USB interrupt lines */
00321   *(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState;
00322 }
00323 
00324 /**
00325   * @brief  Configures the I2C fast mode plus driving capability.
00326   * @param  SYSCFG_I2CFastModePlus: selects the pin.
00327   *   This parameter can be one of the following values:
00328   *     @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
00329   *     @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
00330   *     @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
00331   *     @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
00332   *     @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins
00333   *     @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
00334   *     @arg SYSCFG_I2CFastModePlus_I2C3: Configure fast mode plus driving capability for I2C3 pins  
00335   * @param  NewState: new state of the DMA channel remapping. 
00336   *         This parameter can be:
00337   *     @arg ENABLE: Enable fast mode plus driving capability for selected I2C pin
00338   *     @arg DISABLE: Disable fast mode plus driving capability for selected I2C pin
00339   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
00340   *        I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
00341   *        on each one of the following pins PB6, PB7, PB8 and PB9.
00342   * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
00343   *        can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
00344   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
00345   *        only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
00346   * @retval None
00347   */
00348 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
00349 {
00350   /* Check the parameters */
00351   assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
00352   assert_param(IS_FUNCTIONAL_STATE(NewState));
00353 
00354   if (NewState != DISABLE)
00355   {
00356     /* Enable fast mode plus driving capability for selected I2C pin */
00357     SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
00358   }
00359   else
00360   {
00361     /* Disable fast mode plus driving capability for selected I2C pin */
00362     SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
00363   }
00364 }
00365 
00366 /**
00367   * @brief  Enables or disables the selected SYSCFG interrupts.
00368   * @param  SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled.
00369   *   This parameter can be one of the following values:
00370   *     @arg SYSCFG_IT_IXC: Inexact Interrupt
00371   *     @arg SYSCFG_IT_IDC: Input denormal Interrupt
00372   *     @arg SYSCFG_IT_OFC: Overflow Interrupt
00373   *     @arg SYSCFG_IT_UFC: Underflow Interrupt
00374   *     @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt
00375   *     @arg SYSCFG_IT_IOC: Invalid operation Interrupt
00376   * @param  NewState: new state of the specified SYSCFG interrupts.
00377   *         This parameter can be: ENABLE or DISABLE.
00378   * @retval None
00379   */
00380 void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)  
00381 {
00382   /* Check the parameters */
00383   assert_param(IS_FUNCTIONAL_STATE(NewState));
00384   assert_param(IS_SYSCFG_IT(SYSCFG_IT)); 
00385 
00386   if (NewState != DISABLE)
00387   {
00388     /* Enable the selected SYSCFG interrupts */
00389     SYSCFG->CFGR1 |= SYSCFG_IT;
00390   }
00391   else
00392   {
00393     /* Disable the selected SYSCFG interrupts */
00394     SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT);
00395   }
00396 }
00397 
00398 /**
00399   * @brief  Selects the GPIO pin used as EXTI Line.
00400   * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source 
00401   *                                for EXTI lines where x can be (A, B, C, D, E, F, G, H).
00402   * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
00403   *         This parameter can be EXTI_PinSourcex where x can be (0..15)
00404   * @retval None
00405   */
00406 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
00407 {
00408   uint32_t tmp = 0x00;
00409 
00410   /* Check the parameters */
00411   assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
00412   assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
00413   
00414   tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
00415   SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
00416   SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
00417 }
00418 
00419 /**
00420   * @brief  Connects the selected parameter to the break input of TIM1.
00421   * @note   The selected configuration is locked and can be unlocked by system reset
00422   * @param  SYSCFG_Break: selects the configuration to be connected to break
00423   *         input of TIM1
00424   *   This parameter can be any combination of the following values:
00425   *     @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1.
00426   *     @arg SYSCFG_Break_SRAMParity: SRAM Parity error is connected to the break input of TIM1.
00427   *     @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1.
00428   * @retval None
00429   */
00430 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
00431 {
00432   /* Check the parameter */
00433   assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
00434 
00435   SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
00436 }
00437 
00438 /**
00439   * @brief  Disables the parity check on RAM.
00440   * @note   Disabling the parity check on RAM locks the configuration bit.
00441   *         To re-enable the parity check on RAM perform a system reset.  
00442   * @param  None
00443   * @retval None
00444   */
00445 void SYSCFG_BypassParityCheckDisable(void)
00446 {
00447   /* Disable the address parity check on RAM */
00448   *(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001;
00449 }
00450 
00451 /**
00452   * @brief  Configures the remapping capabilities of DAC/TIM triggers.
00453   * @param  SYSCFG_ADCTriggerRemap: selects the ADC trigger to be remapped.
00454   *   This parameter can be one of the following values: 
00455   *     @arg REMAPADCTRIGGER_ADC12_EXT2: Input trigger of ADC12 regular channel EXT2
00456   *     @arg REMAPADCTRIGGER_ADC12_EXT3: Input trigger of ADC12 regular channel EXT3
00457   *     @arg REMAPADCTRIGGER_ADC12_EXT5: Input trigger of ADC12 regular channel EXT5
00458   *     @arg REMAPADCTRIGGER_ADC12_EXT13: Input trigger of ADC12 regular channel EXT13
00459   *     @arg REMAPADCTRIGGER_ADC12_EXT15: Input trigger of ADC12 regular channel EXT15
00460   *     @arg REMAPADCTRIGGER_ADC12_JEXT3: Input trigger of ADC12 injected channel JEXT3
00461   *     @arg REMAPADCTRIGGER_ADC12_JEXT6: Input trigger of ADC12 injected channel JEXT6
00462   *     @arg REMAPADCTRIGGER_ADC12_JEXT13: Input trigger of ADC12 injected channel JEXT16
00463   *     @arg REMAPADCTRIGGER_ADC34_EXT5: Input trigger of ADC34 regular channel EXT5
00464   *     @arg REMAPADCTRIGGER_ADC34_EXT6: Input trigger of ADC34 regular channel EXT6
00465   *     @arg REMAPADCTRIGGER_ADC34_EXT15: Input trigger of ADC34 regular channel EXT15
00466   *     @arg REMAPADCTRIGGER_ADC34_JEXT5: Input trigger of ADC34 injected channel JEXT5
00467   *     @arg REMAPADCTRIGGER_ADC34_JEXT11: Input trigger of ADC34 injected channel JEXT11
00468   *     @arg REMAPADCTRIGGER_ADC34_JEXT14: Input trigger of ADC34 injected channel JEXT14  
00469   * @param  NewState: new state of the trigger mapping. 
00470   *         This parameter can be: ENABLE or DISABLE.
00471   * @note   ENABLE:  Enable fast mode plus driving capability for selected pin
00472   * @note   DISABLE: Disable fast mode plus driving capability for selected pin
00473   * @retval None
00474   */
00475 void SYSCFG_ADCTriggerRemapConfig(uint32_t SYSCFG_ADCTriggerRemap, FunctionalState NewState)
00476 {
00477   /* Check the parameters */
00478   assert_param(IS_SYSCFG_ADC_TRIGGER_REMAP(SYSCFG_ADCTriggerRemap));
00479   assert_param(IS_FUNCTIONAL_STATE(NewState));
00480   
00481   if (NewState != DISABLE)
00482   {
00483     /* Remap the trigger */
00484     SYSCFG->CFGR4 |= (uint32_t)SYSCFG_ADCTriggerRemap;
00485   }
00486   else
00487   {
00488     /* Use the default trigger mapping */
00489     SYSCFG->CFGR4 &= (uint32_t)(~SYSCFG_ADCTriggerRemap);
00490   }
00491 }
00492 
00493 /**
00494   * @brief  Enables the ICODE SRAM write protection.
00495   * @note   Enabling the ICODE SRAM write protection locks the configuration bit.
00496   *         To disable the ICODE SRAM write protection perform a system reset.
00497   * @param  None
00498   * @retval None
00499   */
00500 void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP)
00501 {
00502   /* Check the parameter */
00503   assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP));
00504 
00505   /* Enable the write-protection on the selected ICODE SRAM page */
00506   SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP;
00507 }
00508 
00509 /**
00510   * @brief  Checks whether the specified SYSCFG flag is set or not.
00511   * @param  SYSCFG_Flag: specifies the SYSCFG flag to check. 
00512   *   This parameter can be one of the following values:
00513   *     @arg SYSCFG_FLAG_PE: SRAM parity error flag.
00514   * @retval The new state of SYSCFG_Flag (SET or RESET).
00515   */
00516 FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
00517 {
00518   FlagStatus bitstatus = RESET;
00519 
00520   /* Check the parameter */
00521   assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
00522 
00523   /* Check the status of the specified SPI flag */
00524   if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
00525   {
00526     /* SYSCFG_Flag is set */
00527     bitstatus = SET;
00528   }
00529   else
00530   {
00531     /* SYSCFG_Flag is reset */
00532     bitstatus = RESET;
00533   }
00534   /* Return the SYSCFG_Flag status */
00535   return  bitstatus;
00536 }
00537 
00538 /**
00539   * @brief  Clears the selected SYSCFG flag.
00540   * @param  SYSCFG_Flag: selects the flag to be cleared.
00541   *   This parameter can be any combination of the following values:
00542   *     @arg SYSCFG_FLAG_PE: SRAM parity error flag.
00543   * @retval None
00544   */
00545 void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
00546 {
00547   /* Check the parameter */
00548   assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
00549 
00550   SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
00551 }
00552 
00553 /**
00554   * @}
00555   */
00556 
00557 /**
00558   * @}
00559   */ 
00560 
00561 /**
00562   * @}
00563   */ 
00564 
00565 /**
00566   * @}
00567   */ 
00568 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00569